PGM.cpp@ 41393

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PGM: Initialize the A20 mask correctly.
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1	/* $Id: PGM.cpp 41393 2012-05-22 14:23:13Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred to
30	* as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successful this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgm_phys PGM Physical Guest Memory Management
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery associated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attempted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the other way around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
484	* however on 32-bit darwin the ring-0 code is running in a different memory
485	* context and therefore needs a separate cache. In raw-mode context we also
486	* need a separate cache. The 32-bit darwin mapping cache and the one for
487	* raw-mode context share a lot of code, see PGMRZDYNMAP.
488	*
489	*
490	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
491	*
492	* We've considered implementing the ring-3 mapping cache page based but found
493	* that this was bother some when one had to take into account TLBs+SMP and
494	* portability (missing the necessary APIs on several platforms). There were
495	* also some performance concerns with this approach which hadn't quite been
496	* worked out.
497	*
498	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
499	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
500	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
501	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
502	* costly than a single page, although how much more costly is uncertain. We'll
503	* try address this by using a very big cache, preferably bigger than the actual
504	* VM RAM size if possible. The current VM RAM sizes should give some idea for
505	* 32-bit boxes, while on 64-bit we can probably get away with employing an
506	* unlimited cache.
507	*
508	* The cache have to parts, as already indicated, the ring-3 side and the
509	* ring-0 side.
510	*
511	* The ring-0 will be tied to the page allocator since it will operate on the
512	* memory objects it contains. It will therefore require the first ring-0 mutex
513	* discussed in @ref subsec_pgmPhys_Serializing. We
514	* some double house keeping wrt to who has mapped what I think, since both
515	* VMMR0.r0 and RTR0MemObj will keep track of mapping relations
516	*
517	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
518	* require anyone that desires to do changes to the mapping cache to do that
519	* from within this critsect. Alternatively, we could employ a separate critsect
520	* for serializing changes to the mapping cache as this would reduce potential
521	* contention with other threads accessing mappings unrelated to the changes
522	* that are in process. We can see about this later, contention will show
523	* up in the statistics anyway, so it'll be simple to tell.
524	*
525	* The organization of the ring-3 part will be very much like how the allocation
526	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
527	* having to walk the tree all the time, we'll have a couple of lookaside entries
528	* like in we do for I/O ports and MMIO in IOM.
529	*
530	* The simplified flow of a PGMPhysRead/Write function:
531	* -# Enter the PGM critsect.
532	* -# Lookup GCPhys in the ram ranges and get the Page ID.
533	* -# Calc the Allocation Chunk ID from the Page ID.
534	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
535	* If not found in cache:
536	* -# Call ring-0 and request it to be mapped and supply
537	* a chunk to be unmapped if the cache is maxed out already.
538	* -# Insert the new mapping into the AVL tree (id + R3 address).
539	* -# Update the relevant lookaside entry and return the mapping address.
540	* -# Do the read/write according to monitoring flags and everything.
541	* -# Leave the critsect.
542	*
543	*
544	* @section sec_pgmPhys_Fallback Fallback
545	*
546	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
547	* API and thus require a fallback.
548	*
549	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
550	* will return to the ring-3 caller (and later ring-0) and asking it to seed
551	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
552	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
553	* "SeededAllocPages" call to ring-0.
554	*
555	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
556	* all page sharing (zero page detection will continue). It will also force
557	* all allocations to come from the VM which seeded the page. Both these
558	* measures are taken to make sure that there will never be any need for
559	* mapping anything into ring-3 - everything will be mapped already.
560	*
561	* Whether we'll continue to use the current MM locked memory management
562	* for this I don't quite know (I'd prefer not to and just ditch that all
563	* together), we'll see what's simplest to do.
564	*
565	*
566	*
567	* @section sec_pgmPhys_Changes Changes
568	*
569	* Breakdown of the changes involved?
570	*/
571
572	/*******************************************************************************
573	* Header Files *
574	*******************************************************************************/
575	#define LOG_GROUP LOG_GROUP_PGM
576	#include <VBox/vmm/dbgf.h>
577	#include <VBox/vmm/pgm.h>
578	#include <VBox/vmm/cpum.h>
579	#include <VBox/vmm/iom.h>
580	#include <VBox/sup.h>
581	#include <VBox/vmm/mm.h>
582	#include <VBox/vmm/em.h>
583	#include <VBox/vmm/stam.h>
584	#ifdef VBOX_WITH_REM
585	# include <VBox/vmm/rem.h>
586	#endif
587	#include <VBox/vmm/selm.h>
588	#include <VBox/vmm/ssm.h>
589	#include <VBox/vmm/hwaccm.h>
590	#include "PGMInternal.h"
591	#include <VBox/vmm/vm.h>
592	#include "PGMInline.h"
593
594	#include <VBox/dbg.h>
595	#include <VBox/param.h>
596	#include <VBox/err.h>
597
598	#include <iprt/asm.h>
599	#include <iprt/asm-amd64-x86.h>
600	#include <iprt/assert.h>
601	#include <iprt/env.h>
602	#include <iprt/mem.h>
603	#include <iprt/file.h>
604	#include <iprt/string.h>
605	#include <iprt/thread.h>
606
607
608	/*******************************************************************************
609	* Internal Functions *
610	*******************************************************************************/
611	static int pgmR3InitPaging(PVM pVM);
612	static int pgmR3InitStats(PVM pVM);
613	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
615	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
616	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
617	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
618	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
619	#ifdef VBOX_STRICT
620	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
621	#endif
622	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
623	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
624	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
625
626	#ifdef VBOX_WITH_DEBUGGER
627	/** @todo Convert the first two commands to 'info' items. */
628	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
629	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
630	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
631	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
632	# ifdef VBOX_STRICT
633	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
634	# endif
635	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
636	#endif
637
638
639	/*******************************************************************************
640	* Global Variables *
641	*******************************************************************************/
642	#ifdef VBOX_WITH_DEBUGGER
643	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
644	static const DBGCVARDESC g_aPgmErrorArgs[] =
645	{
646	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
647	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
648	};
649
650	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
651	{
652	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
653	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
654	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
655	};
656
657	# ifdef DEBUG_sandervl
658	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
659	{
660	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
661	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
662	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
663	};
664	# endif
665
666	/** Command descriptors. */
667	static const DBGCCMD g_aCmds[] =
668	{
669	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
670	{ "pgmram", 0, 0, NULL, 0, 0, pgmR3CmdRam, "", "Display the ram ranges." },
671	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
672	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
673	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
674	# ifdef VBOX_STRICT
675	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
676	# ifdef VBOX_WITH_PAGE_SHARING
677	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
678	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
679	# endif
680	# endif
681	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
682	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
683	};
684	#endif
685
686
687
688
689	/*
690	* Shadow - 32-bit mode
691	*/
692	#define PGM_SHW_TYPE PGM_TYPE_32BIT
693	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
694	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
695	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
696	#include "PGMShw.h"
697
698	/* Guest - real mode */
699	#define PGM_GST_TYPE PGM_TYPE_REAL
700	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
701	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
702	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
703	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
704	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
705	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
706	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
707	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
708	#include "PGMBth.h"
709	#include "PGMGstDefs.h"
710	#include "PGMGst.h"
711	#undef BTH_PGMPOOLKIND_PT_FOR_PT
712	#undef BTH_PGMPOOLKIND_ROOT
713	#undef PGM_BTH_NAME
714	#undef PGM_BTH_NAME_RC_STR
715	#undef PGM_BTH_NAME_R0_STR
716	#undef PGM_GST_TYPE
717	#undef PGM_GST_NAME
718	#undef PGM_GST_NAME_RC_STR
719	#undef PGM_GST_NAME_R0_STR
720
721	/* Guest - protected mode */
722	#define PGM_GST_TYPE PGM_TYPE_PROT
723	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
724	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
725	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
726	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
727	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
728	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
729	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
730	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
731	#include "PGMBth.h"
732	#include "PGMGstDefs.h"
733	#include "PGMGst.h"
734	#undef BTH_PGMPOOLKIND_PT_FOR_PT
735	#undef BTH_PGMPOOLKIND_ROOT
736	#undef PGM_BTH_NAME
737	#undef PGM_BTH_NAME_RC_STR
738	#undef PGM_BTH_NAME_R0_STR
739	#undef PGM_GST_TYPE
740	#undef PGM_GST_NAME
741	#undef PGM_GST_NAME_RC_STR
742	#undef PGM_GST_NAME_R0_STR
743
744	/* Guest - 32-bit mode */
745	#define PGM_GST_TYPE PGM_TYPE_32BIT
746	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
747	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
748	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
749	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
750	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
751	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
752	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
753	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
754	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
755	#include "PGMBth.h"
756	#include "PGMGstDefs.h"
757	#include "PGMGst.h"
758	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
759	#undef BTH_PGMPOOLKIND_PT_FOR_PT
760	#undef BTH_PGMPOOLKIND_ROOT
761	#undef PGM_BTH_NAME
762	#undef PGM_BTH_NAME_RC_STR
763	#undef PGM_BTH_NAME_R0_STR
764	#undef PGM_GST_TYPE
765	#undef PGM_GST_NAME
766	#undef PGM_GST_NAME_RC_STR
767	#undef PGM_GST_NAME_R0_STR
768
769	#undef PGM_SHW_TYPE
770	#undef PGM_SHW_NAME
771	#undef PGM_SHW_NAME_RC_STR
772	#undef PGM_SHW_NAME_R0_STR
773
774
775	/*
776	* Shadow - PAE mode
777	*/
778	#define PGM_SHW_TYPE PGM_TYPE_PAE
779	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
780	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
781	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
782	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
783	#include "PGMShw.h"
784
785	/* Guest - real mode */
786	#define PGM_GST_TYPE PGM_TYPE_REAL
787	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
788	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
789	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
790	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
791	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
792	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
793	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
794	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
795	#include "PGMGstDefs.h"
796	#include "PGMBth.h"
797	#undef BTH_PGMPOOLKIND_PT_FOR_PT
798	#undef BTH_PGMPOOLKIND_ROOT
799	#undef PGM_BTH_NAME
800	#undef PGM_BTH_NAME_RC_STR
801	#undef PGM_BTH_NAME_R0_STR
802	#undef PGM_GST_TYPE
803	#undef PGM_GST_NAME
804	#undef PGM_GST_NAME_RC_STR
805	#undef PGM_GST_NAME_R0_STR
806
807	/* Guest - protected mode */
808	#define PGM_GST_TYPE PGM_TYPE_PROT
809	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
810	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
811	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
812	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
813	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
814	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
815	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
816	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
817	#include "PGMGstDefs.h"
818	#include "PGMBth.h"
819	#undef BTH_PGMPOOLKIND_PT_FOR_PT
820	#undef BTH_PGMPOOLKIND_ROOT
821	#undef PGM_BTH_NAME
822	#undef PGM_BTH_NAME_RC_STR
823	#undef PGM_BTH_NAME_R0_STR
824	#undef PGM_GST_TYPE
825	#undef PGM_GST_NAME
826	#undef PGM_GST_NAME_RC_STR
827	#undef PGM_GST_NAME_R0_STR
828
829	/* Guest - 32-bit mode */
830	#define PGM_GST_TYPE PGM_TYPE_32BIT
831	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
832	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
833	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
834	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
835	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
836	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
837	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
838	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
839	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
840	#include "PGMGstDefs.h"
841	#include "PGMBth.h"
842	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
843	#undef BTH_PGMPOOLKIND_PT_FOR_PT
844	#undef BTH_PGMPOOLKIND_ROOT
845	#undef PGM_BTH_NAME
846	#undef PGM_BTH_NAME_RC_STR
847	#undef PGM_BTH_NAME_R0_STR
848	#undef PGM_GST_TYPE
849	#undef PGM_GST_NAME
850	#undef PGM_GST_NAME_RC_STR
851	#undef PGM_GST_NAME_R0_STR
852
853	/* Guest - PAE mode */
854	#define PGM_GST_TYPE PGM_TYPE_PAE
855	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
856	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
857	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
858	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
859	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
860	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
861	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
862	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
863	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
864	#include "PGMBth.h"
865	#include "PGMGstDefs.h"
866	#include "PGMGst.h"
867	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
868	#undef BTH_PGMPOOLKIND_PT_FOR_PT
869	#undef BTH_PGMPOOLKIND_ROOT
870	#undef PGM_BTH_NAME
871	#undef PGM_BTH_NAME_RC_STR
872	#undef PGM_BTH_NAME_R0_STR
873	#undef PGM_GST_TYPE
874	#undef PGM_GST_NAME
875	#undef PGM_GST_NAME_RC_STR
876	#undef PGM_GST_NAME_R0_STR
877
878	#undef PGM_SHW_TYPE
879	#undef PGM_SHW_NAME
880	#undef PGM_SHW_NAME_RC_STR
881	#undef PGM_SHW_NAME_R0_STR
882
883
884	/*
885	* Shadow - AMD64 mode
886	*/
887	#define PGM_SHW_TYPE PGM_TYPE_AMD64
888	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
889	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
890	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
891	#include "PGMShw.h"
892
893	#ifdef VBOX_WITH_64_BITS_GUESTS
894	/* Guest - AMD64 mode */
895	# define PGM_GST_TYPE PGM_TYPE_AMD64
896	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
897	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
898	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
899	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
900	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
901	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
902	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
903	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
904	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
905	# include "PGMBth.h"
906	# include "PGMGstDefs.h"
907	# include "PGMGst.h"
908	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
909	# undef BTH_PGMPOOLKIND_PT_FOR_PT
910	# undef BTH_PGMPOOLKIND_ROOT
911	# undef PGM_BTH_NAME
912	# undef PGM_BTH_NAME_RC_STR
913	# undef PGM_BTH_NAME_R0_STR
914	# undef PGM_GST_TYPE
915	# undef PGM_GST_NAME
916	# undef PGM_GST_NAME_RC_STR
917	# undef PGM_GST_NAME_R0_STR
918	#endif /* VBOX_WITH_64_BITS_GUESTS */
919
920	#undef PGM_SHW_TYPE
921	#undef PGM_SHW_NAME
922	#undef PGM_SHW_NAME_RC_STR
923	#undef PGM_SHW_NAME_R0_STR
924
925
926	/*
927	* Shadow - Nested paging mode
928	*/
929	#define PGM_SHW_TYPE PGM_TYPE_NESTED
930	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
931	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
932	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
933	#include "PGMShw.h"
934
935	/* Guest - real mode */
936	#define PGM_GST_TYPE PGM_TYPE_REAL
937	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
938	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
939	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
940	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
941	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
942	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
943	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
944	#include "PGMGstDefs.h"
945	#include "PGMBth.h"
946	#undef BTH_PGMPOOLKIND_PT_FOR_PT
947	#undef PGM_BTH_NAME
948	#undef PGM_BTH_NAME_RC_STR
949	#undef PGM_BTH_NAME_R0_STR
950	#undef PGM_GST_TYPE
951	#undef PGM_GST_NAME
952	#undef PGM_GST_NAME_RC_STR
953	#undef PGM_GST_NAME_R0_STR
954
955	/* Guest - protected mode */
956	#define PGM_GST_TYPE PGM_TYPE_PROT
957	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
958	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
959	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
960	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
961	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
962	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
963	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
964	#include "PGMGstDefs.h"
965	#include "PGMBth.h"
966	#undef BTH_PGMPOOLKIND_PT_FOR_PT
967	#undef PGM_BTH_NAME
968	#undef PGM_BTH_NAME_RC_STR
969	#undef PGM_BTH_NAME_R0_STR
970	#undef PGM_GST_TYPE
971	#undef PGM_GST_NAME
972	#undef PGM_GST_NAME_RC_STR
973	#undef PGM_GST_NAME_R0_STR
974
975	/* Guest - 32-bit mode */
976	#define PGM_GST_TYPE PGM_TYPE_32BIT
977	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
978	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
979	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
980	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
981	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
982	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
983	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
984	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
985	#include "PGMGstDefs.h"
986	#include "PGMBth.h"
987	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
988	#undef BTH_PGMPOOLKIND_PT_FOR_PT
989	#undef PGM_BTH_NAME
990	#undef PGM_BTH_NAME_RC_STR
991	#undef PGM_BTH_NAME_R0_STR
992	#undef PGM_GST_TYPE
993	#undef PGM_GST_NAME
994	#undef PGM_GST_NAME_RC_STR
995	#undef PGM_GST_NAME_R0_STR
996
997	/* Guest - PAE mode */
998	#define PGM_GST_TYPE PGM_TYPE_PAE
999	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1000	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1001	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1002	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1003	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1004	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1005	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1006	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1007	#include "PGMGstDefs.h"
1008	#include "PGMBth.h"
1009	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1010	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1011	#undef PGM_BTH_NAME
1012	#undef PGM_BTH_NAME_RC_STR
1013	#undef PGM_BTH_NAME_R0_STR
1014	#undef PGM_GST_TYPE
1015	#undef PGM_GST_NAME
1016	#undef PGM_GST_NAME_RC_STR
1017	#undef PGM_GST_NAME_R0_STR
1018
1019	#ifdef VBOX_WITH_64_BITS_GUESTS
1020	/* Guest - AMD64 mode */
1021	# define PGM_GST_TYPE PGM_TYPE_AMD64
1022	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1023	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1024	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1025	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1026	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1027	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1028	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1029	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1030	# include "PGMGstDefs.h"
1031	# include "PGMBth.h"
1032	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1033	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1034	# undef PGM_BTH_NAME
1035	# undef PGM_BTH_NAME_RC_STR
1036	# undef PGM_BTH_NAME_R0_STR
1037	# undef PGM_GST_TYPE
1038	# undef PGM_GST_NAME
1039	# undef PGM_GST_NAME_RC_STR
1040	# undef PGM_GST_NAME_R0_STR
1041	#endif /* VBOX_WITH_64_BITS_GUESTS */
1042
1043	#undef PGM_SHW_TYPE
1044	#undef PGM_SHW_NAME
1045	#undef PGM_SHW_NAME_RC_STR
1046	#undef PGM_SHW_NAME_R0_STR
1047
1048
1049	/*
1050	* Shadow - EPT
1051	*/
1052	#define PGM_SHW_TYPE PGM_TYPE_EPT
1053	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1054	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1055	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1056	#include "PGMShw.h"
1057
1058	/* Guest - real mode */
1059	#define PGM_GST_TYPE PGM_TYPE_REAL
1060	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1061	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1062	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1063	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1064	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1065	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1066	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1067	#include "PGMGstDefs.h"
1068	#include "PGMBth.h"
1069	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1070	#undef PGM_BTH_NAME
1071	#undef PGM_BTH_NAME_RC_STR
1072	#undef PGM_BTH_NAME_R0_STR
1073	#undef PGM_GST_TYPE
1074	#undef PGM_GST_NAME
1075	#undef PGM_GST_NAME_RC_STR
1076	#undef PGM_GST_NAME_R0_STR
1077
1078	/* Guest - protected mode */
1079	#define PGM_GST_TYPE PGM_TYPE_PROT
1080	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1081	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1082	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1083	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1084	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1085	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1086	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1087	#include "PGMGstDefs.h"
1088	#include "PGMBth.h"
1089	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1090	#undef PGM_BTH_NAME
1091	#undef PGM_BTH_NAME_RC_STR
1092	#undef PGM_BTH_NAME_R0_STR
1093	#undef PGM_GST_TYPE
1094	#undef PGM_GST_NAME
1095	#undef PGM_GST_NAME_RC_STR
1096	#undef PGM_GST_NAME_R0_STR
1097
1098	/* Guest - 32-bit mode */
1099	#define PGM_GST_TYPE PGM_TYPE_32BIT
1100	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1101	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1102	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1103	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1104	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1105	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1106	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1107	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1108	#include "PGMGstDefs.h"
1109	#include "PGMBth.h"
1110	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1111	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1112	#undef PGM_BTH_NAME
1113	#undef PGM_BTH_NAME_RC_STR
1114	#undef PGM_BTH_NAME_R0_STR
1115	#undef PGM_GST_TYPE
1116	#undef PGM_GST_NAME
1117	#undef PGM_GST_NAME_RC_STR
1118	#undef PGM_GST_NAME_R0_STR
1119
1120	/* Guest - PAE mode */
1121	#define PGM_GST_TYPE PGM_TYPE_PAE
1122	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1123	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1124	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1125	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1126	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1127	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1128	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1129	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1130	#include "PGMGstDefs.h"
1131	#include "PGMBth.h"
1132	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1133	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1134	#undef PGM_BTH_NAME
1135	#undef PGM_BTH_NAME_RC_STR
1136	#undef PGM_BTH_NAME_R0_STR
1137	#undef PGM_GST_TYPE
1138	#undef PGM_GST_NAME
1139	#undef PGM_GST_NAME_RC_STR
1140	#undef PGM_GST_NAME_R0_STR
1141
1142	#ifdef VBOX_WITH_64_BITS_GUESTS
1143	/* Guest - AMD64 mode */
1144	# define PGM_GST_TYPE PGM_TYPE_AMD64
1145	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1146	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1147	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1148	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1149	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1150	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1151	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1152	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1153	# include "PGMGstDefs.h"
1154	# include "PGMBth.h"
1155	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1156	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1157	# undef PGM_BTH_NAME
1158	# undef PGM_BTH_NAME_RC_STR
1159	# undef PGM_BTH_NAME_R0_STR
1160	# undef PGM_GST_TYPE
1161	# undef PGM_GST_NAME
1162	# undef PGM_GST_NAME_RC_STR
1163	# undef PGM_GST_NAME_R0_STR
1164	#endif /* VBOX_WITH_64_BITS_GUESTS */
1165
1166	#undef PGM_SHW_TYPE
1167	#undef PGM_SHW_NAME
1168	#undef PGM_SHW_NAME_RC_STR
1169	#undef PGM_SHW_NAME_R0_STR
1170
1171
1172
1173	/**
1174	* Initiates the paging of VM.
1175	*
1176	* @returns VBox status code.
1177	* @param pVM Pointer to VM structure.
1178	*/
1179	VMMR3DECL(int) PGMR3Init(PVM pVM)
1180	{
1181	LogFlow(("PGMR3Init:\n"));
1182	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1183	int rc;
1184
1185	/*
1186	* Assert alignment and sizes.
1187	*/
1188	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1189	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1190	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1191
1192	/*
1193	* Init the structure.
1194	*/
1195	#ifdef PGM_WITHOUT_MAPPINGS
1196	pVM->pgm.s.fMappingsDisabled = true;
1197	#endif
1198	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1199	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1200
1201	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1202	{
1203	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1204	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1205	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1206	}
1207
1208	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1209	{
1210	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1211	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1212	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1213	}
1214
1215	/* Init the per-CPU part. */
1216	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1217	{
1218	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1219	PPGMCPU pPGM = &pVCpu->pgm.s;
1220
1221	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1222	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1223	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1224
1225	pPGM->enmShadowMode = PGMMODE_INVALID;
1226	pPGM->enmGuestMode = PGMMODE_INVALID;
1227
1228	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1229
1230	pPGM->pGst32BitPdR3 = NULL;
1231	pPGM->pGstPaePdptR3 = NULL;
1232	pPGM->pGstAmd64Pml4R3 = NULL;
1233	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1234	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1235	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1236	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1237	#endif
1238	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1239	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1240	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1241	{
1242	pPGM->apGstPaePDsR3[i] = NULL;
1243	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1244	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1245	#endif
1246	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1247	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1248	pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1249	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1250	}
1251
1252	pPGM->fA20Enabled = true;
1253	pPGM->GCPhysA20Mask = ~(RTGCPHYS)(!pPGM->fA20Enabled << 20);
1254	}
1255
1256	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1257	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1258	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1259
1260	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1261	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1262	true
1263	#else
1264	false
1265	#endif
1266	);
1267	AssertLogRelRCReturn(rc, rc);
1268
1269	#if HC_ARCH_BITS == 32
1270	# ifdef RT_OS_DARWIN
1271	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1272	# else
1273	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1274	# endif
1275	#else
1276	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1277	#endif
1278	AssertLogRelRCReturn(rc, rc);
1279	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1280	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1281
1282	/*
1283	* Get the configured RAM size - to estimate saved state size.
1284	*/
1285	uint64_t cbRam;
1286	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1287	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1288	cbRam = 0;
1289	else if (RT_SUCCESS(rc))
1290	{
1291	if (cbRam < PAGE_SIZE)
1292	cbRam = 0;
1293	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1294	}
1295	else
1296	{
1297	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1298	return rc;
1299	}
1300
1301	/*
1302	* Check for PCI pass-through.
1303	*/
1304	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1305	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1306	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1307
1308	#ifdef VBOX_WITH_STATISTICS
1309	/*
1310	* Allocate memory for the statistics before someone tries to use them.
1311	*/
1312	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1313	void *pv;
1314	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1315	AssertRCReturn(rc, rc);
1316
1317	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1318	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1319	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1320	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1321
1322	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1323	{
1324	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1325	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1326	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1327
1328	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1329	}
1330	#endif /* VBOX_WITH_STATISTICS */
1331
1332	/*
1333	* Register callbacks, string formatters and the saved state data unit.
1334	*/
1335	#ifdef VBOX_STRICT
1336	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1337	#endif
1338	PGMRegisterStringFormatTypes();
1339
1340	rc = pgmR3InitSavedState(pVM, cbRam);
1341	if (RT_FAILURE(rc))
1342	return rc;
1343
1344	/*
1345	* Initialize the PGM critical section and flush the phys TLBs
1346	*/
1347	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1348	AssertRCReturn(rc, rc);
1349
1350	PGMR3PhysChunkInvalidateTLB(pVM);
1351	pgmPhysInvalidatePageMapTLB(pVM);
1352
1353	/*
1354	* For the time being we sport a full set of handy pages in addition to the base
1355	* memory to simplify things.
1356	*/
1357	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1358	AssertRCReturn(rc, rc);
1359
1360	/*
1361	* Trees
1362	*/
1363	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1364	if (RT_SUCCESS(rc))
1365	{
1366	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1367	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1368
1369	/*
1370	* Allocate the zero page.
1371	*/
1372	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1373	}
1374	if (RT_SUCCESS(rc))
1375	{
1376	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1377	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1378	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1379	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1380
1381	/*
1382	* Allocate the invalid MMIO page.
1383	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1384	*/
1385	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1386	}
1387	if (RT_SUCCESS(rc))
1388	{
1389	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1390	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1391	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1392	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1393
1394	/*
1395	* Init the paging.
1396	*/
1397	rc = pgmR3InitPaging(pVM);
1398	}
1399	if (RT_SUCCESS(rc))
1400	{
1401	/*
1402	* Init the page pool.
1403	*/
1404	rc = pgmR3PoolInit(pVM);
1405	}
1406	if (RT_SUCCESS(rc))
1407	{
1408	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1409	{
1410	PVMCPU pVCpu = &pVM->aCpus[i];
1411	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1412	if (RT_FAILURE(rc))
1413	break;
1414	}
1415	}
1416
1417	if (RT_SUCCESS(rc))
1418	{
1419	/*
1420	* Info & statistics
1421	*/
1422	DBGFR3InfoRegisterInternal(pVM, "mode",
1423	"Shows the current paging mode. "
1424	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1425	pgmR3InfoMode);
1426	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1427	"Dumps all the entries in the top level paging table. No arguments.",
1428	pgmR3InfoCr3);
1429	DBGFR3InfoRegisterInternal(pVM, "phys",
1430	"Dumps all the physical address ranges. No arguments.",
1431	pgmR3PhysInfo);
1432	DBGFR3InfoRegisterInternal(pVM, "handlers",
1433	"Dumps physical, virtual and hyper virtual handlers. "
1434	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1435	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1436	pgmR3InfoHandlers);
1437	DBGFR3InfoRegisterInternal(pVM, "mappings",
1438	"Dumps guest mappings.",
1439	pgmR3MapInfo);
1440
1441	pgmR3InitStats(pVM);
1442
1443	#ifdef VBOX_WITH_DEBUGGER
1444	/*
1445	* Debugger commands.
1446	*/
1447	static bool s_fRegisteredCmds = false;
1448	if (!s_fRegisteredCmds)
1449	{
1450	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1451	if (RT_SUCCESS(rc2))
1452	s_fRegisteredCmds = true;
1453	}
1454	#endif
1455	return VINF_SUCCESS;
1456	}
1457
1458	/* Almost no cleanup necessary, MM frees all memory. */
1459	PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1460
1461	return rc;
1462	}
1463
1464
1465	/**
1466	* Init paging.
1467	*
1468	* Since we need to check what mode the host is operating in before we can choose
1469	* the right paging functions for the host we have to delay this until R0 has
1470	* been initialized.
1471	*
1472	* @returns VBox status code.
1473	* @param pVM VM handle.
1474	*/
1475	static int pgmR3InitPaging(PVM pVM)
1476	{
1477	/*
1478	* Force a recalculation of modes and switcher so everyone gets notified.
1479	*/
1480	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1481	{
1482	PVMCPU pVCpu = &pVM->aCpus[i];
1483
1484	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1485	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1486	}
1487
1488	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1489
1490	/*
1491	* Allocate static mapping space for whatever the cr3 register
1492	* points to and in the case of PAE mode to the 4 PDs.
1493	*/
1494	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1495	if (RT_FAILURE(rc))
1496	{
1497	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1498	return rc;
1499	}
1500	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1501
1502	/*
1503	* Allocate pages for the three possible intermediate contexts
1504	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1505	* for the sake of simplicity. The AMD64 uses the PAE for the
1506	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1507	*
1508	* We assume that two page tables will be enought for the core code
1509	* mappings (HC virtual and identity).
1510	*/
1511	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1512	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1513	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1514	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1515	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1516	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1517	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1518	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1519	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1520	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1521	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1522	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1523
1524	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1525	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1526	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1527	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1528	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1529	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1530
1531	/*
1532	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1533	*/
1534	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1535	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1536	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1537
1538	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1539	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1540
1541	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1542	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1543	{
1544	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1545	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1546	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1547	}
1548
1549	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1550	{
1551	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1552	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1553	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1554	}
1555
1556	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1557	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1558	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1559	\| HCPhysInterPaePDPT64;
1560
1561	/*
1562	* Initialize paging workers and mode from current host mode
1563	* and the guest running in real mode.
1564	*/
1565	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1566	switch (pVM->pgm.s.enmHostMode)
1567	{
1568	case SUPPAGINGMODE_32_BIT:
1569	case SUPPAGINGMODE_32_BIT_GLOBAL:
1570	case SUPPAGINGMODE_PAE:
1571	case SUPPAGINGMODE_PAE_GLOBAL:
1572	case SUPPAGINGMODE_PAE_NX:
1573	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1574	break;
1575
1576	case SUPPAGINGMODE_AMD64:
1577	case SUPPAGINGMODE_AMD64_GLOBAL:
1578	case SUPPAGINGMODE_AMD64_NX:
1579	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1580	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1581	if (ARCH_BITS != 64)
1582	{
1583	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1584	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1585	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1586	}
1587	#endif
1588	break;
1589	default:
1590	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1591	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1592	}
1593	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1594	if (RT_SUCCESS(rc))
1595	{
1596	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1597	#if HC_ARCH_BITS == 64
1598	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1599	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1600	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1601	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1602	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1603	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1604	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1605	#endif
1606
1607	/*
1608	* Log the host paging mode. It may come in handy.
1609	*/
1610	const char *pszHostMode;
1611	switch (pVM->pgm.s.enmHostMode)
1612	{
1613	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1614	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1615	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1616	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1617	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1618	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1619	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1620	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1621	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1622	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1623	default: pszHostMode = "???"; break;
1624	}
1625	LogRel(("Host paging mode: %s\n", pszHostMode));
1626
1627	return VINF_SUCCESS;
1628	}
1629
1630	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1631	return rc;
1632	}
1633
1634
1635	/**
1636	* Init statistics
1637	* @returns VBox status code.
1638	*/
1639	static int pgmR3InitStats(PVM pVM)
1640	{
1641	PPGM pPGM = &pVM->pgm.s;
1642	int rc;
1643
1644	/*
1645	* Release statistics.
1646	*/
1647	/* Common - misc variables */
1648	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1649	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1650	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1651	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1652	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1653	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1654	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1655	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1656	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1657	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1658	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1659	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1660	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1661	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1662	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1663	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1664	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1665	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1666	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1667
1668	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1669	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1670	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1671
1672	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1673
1674	/* Live save */
1675	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1676	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1677	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1678	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1679	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1680	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1681	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1682	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1683	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1684	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1685	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1686	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1687	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1688	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1689	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1690	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1691	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1692	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1693
1694	#ifdef VBOX_WITH_STATISTICS
1695
1696	# define PGM_REG_COUNTER(a, b, c) \
1697	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1698	AssertRC(rc);
1699
1700	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1701	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1702	AssertRC(rc);
1703
1704	# define PGM_REG_PROFILE(a, b, c) \
1705	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1706	AssertRC(rc);
1707
1708	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1709
1710	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1711	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1712	PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1713	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1714	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1715
1716	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1717	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1718	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1719	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1720	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1721	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1722	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1723	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1724	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1725	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1726
1727	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1728	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1729	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1730	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1731	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1732	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1733
1734	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1735	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1736	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1737	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1738	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1739	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1740	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1741	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1742
1743	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1744	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1745	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1746	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1747
1748	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1749	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1750	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1751	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1752
1753	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1754	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1755	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1756	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1757	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1758	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1759	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1760	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1761
1762	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1763	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1764	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1765	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1766	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1767	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1768
1769	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1770	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1771	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1772	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1773	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1774	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1775	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1776	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1777
1778	/* GC only: */
1779	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1780	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1781
1782	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1783	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1784	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1785	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1786	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1787	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1788	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1789	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1790
1791	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1792	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1793	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1794	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1795	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1796	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1797	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1798
1799	# undef PGM_REG_COUNTER
1800	# undef PGM_REG_PROFILE
1801	#endif
1802
1803	/*
1804	* Note! The layout below matches the member layout exactly!
1805	*/
1806
1807	/*
1808	* Common - stats
1809	*/
1810	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1811	{
1812	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1813
1814	#define PGM_REG_COUNTER(a, b, c) \
1815	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1816	AssertRC(rc);
1817	#define PGM_REG_PROFILE(a, b, c) \
1818	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1819	AssertRC(rc);
1820
1821	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1822
1823	#ifdef VBOX_WITH_STATISTICS
1824	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1825
1826	# if 0 /* rarely useful; leave for debugging. */
1827	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1828	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1829	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1830	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1831	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1832	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1833	# endif
1834	/* R0 only: */
1835	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1836	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1837
1838	/* RZ only: */
1839	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1840	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1841	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1842	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1843	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1844	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1845	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1846	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1847	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1848	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1849	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1850	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1851	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1852	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1853	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1854	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1855	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1856	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1857	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1858	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1859	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1860	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1861	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1862	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1863	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1864	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1865	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1866	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1867	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1868	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1869	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1870	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1871	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1872	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1873	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1874	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1875	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1876	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1877	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1878	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1879	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1880	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1881	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1882	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1883	#if 0 /* rarely useful; leave for debugging. */
1884	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1885	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1886	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1887	#endif
1888	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1889	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1890	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1891	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1892	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1893
1894	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1895	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1896	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1897	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1898	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1899	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1900	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1901	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1902	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1903	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1904	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1905	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1906	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1907	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1908	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1909	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1910	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1911	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1912	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1913	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1914	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1915	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1916	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1917	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1918	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1919	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1920	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1921	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1922	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1923	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1924	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1925	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1926	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1927	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1928	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1929	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1930
1931	/* HC only: */
1932
1933	/* RZ & R3: */
1934	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1935	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1936	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1937	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1938	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1939	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1940	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1941	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1942	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1943	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1944	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1945	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1946	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1947	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1948	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1949	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1950	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1951	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1952	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1953	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1954	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1955	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1956	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1957	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1958	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1959	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1960	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1961	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1962	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1963	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1964	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1965	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1966	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1967	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1968	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1969	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1970	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1971	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1972	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1973	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1974	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1975	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1976	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1977	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1978	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1979	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1980	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1981
1982	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1983	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1984	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1985	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1986	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1987	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1988	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1989	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1990	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1991	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1992	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1993	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1994	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1995	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1996	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1997	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1998	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1999	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2000	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2001	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2002	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2003	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2004	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2005	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2006	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2007	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2008	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2009	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2010	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2011	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2012	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2013	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2014	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2015	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2016	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2017	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2018	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2019	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2020	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2021	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2022	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2023	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2024	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2025	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2026	#endif /* VBOX_WITH_STATISTICS */
2027
2028	#undef PGM_REG_PROFILE
2029	#undef PGM_REG_COUNTER
2030
2031	}
2032
2033	return VINF_SUCCESS;
2034	}
2035
2036
2037	/**
2038	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2039	*
2040	* The dynamic mapping area will also be allocated and initialized at this
2041	* time. We could allocate it during PGMR3Init of course, but the mapping
2042	* wouldn't be allocated at that time preventing us from setting up the
2043	* page table entries with the dummy page.
2044	*
2045	* @returns VBox status code.
2046	* @param pVM VM handle.
2047	*/
2048	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2049	{
2050	RTGCPTR GCPtr;
2051	int rc;
2052
2053	/*
2054	* Reserve space for the dynamic mappings.
2055	*/
2056	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2057	if (RT_SUCCESS(rc))
2058	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2059
2060	if ( RT_SUCCESS(rc)
2061	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2062	{
2063	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2064	if (RT_SUCCESS(rc))
2065	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2066	}
2067	if (RT_SUCCESS(rc))
2068	{
2069	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2070	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2071	}
2072	return rc;
2073	}
2074
2075
2076	/**
2077	* Ring-3 init finalizing.
2078	*
2079	* @returns VBox status code.
2080	* @param pVM The VM handle.
2081	*/
2082	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2083	{
2084	int rc;
2085
2086	/*
2087	* Reserve space for the dynamic mappings.
2088	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2089	*/
2090	/* get the pointer to the page table entries. */
2091	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2092	AssertRelease(pMapping);
2093	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2094	const unsigned iPT = off >> X86_PD_SHIFT;
2095	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2096	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2097	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2098
2099	/* init cache area */
2100	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2101	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2102	{
2103	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2104	AssertRCReturn(rc, rc);
2105	}
2106
2107	/*
2108	* Determine the max physical address width (MAXPHYADDR) and apply it to
2109	* all the mask members and stuff.
2110	*/
2111	uint32_t cMaxPhysAddrWidth;
2112	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2113	if ( uMaxExtLeaf >= 0x80000008
2114	&& uMaxExtLeaf <= 0x80000fff)
2115	{
2116	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2117	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2118	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2119	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2120	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2121	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2122	}
2123	else
2124	{
2125	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2126	cMaxPhysAddrWidth = 48;
2127	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2128	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2129	}
2130
2131	pVM->pgm.s.GCPhysInvAddrMask = 0;
2132	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2133	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2134
2135	/*
2136	* Initialize the invalid paging entry masks, assuming NX is disabled.
2137	*/
2138	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2139	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2140	{
2141	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2142
2143	/** @todo The manuals are not entirely clear whether the physical
2144	* address width is relevant. See table 5-9 in the intel
2145	* manual vs the PDE4M descriptions. Write testcase (NP). */
2146	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2147	\| X86_PDE4M_MBZ_MASK;
2148
2149	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2150	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2151	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2152	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2153
2154	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2155	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2156	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2157	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2158	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2159	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2160
2161	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
2162	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
2163	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
2164	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2165	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
2166	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
2167	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
2168	}
2169
2170	/*
2171	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2172	* Intel only goes up to 36 bits, so we stick to 36 as well.
2173	* Update: More recent intel manuals specifies 40 bits just like AMD.
2174	*/
2175	uint32_t u32Dummy, u32Features;
2176	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2177	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2178	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2179	else
2180	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2181
2182	/*
2183	* Allocate memory if we're supposed to do that.
2184	*/
2185	if (pVM->pgm.s.fRamPreAlloc)
2186	rc = pgmR3PhysRamPreAllocate(pVM);
2187
2188	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2189	return rc;
2190	}
2191
2192
2193	/**
2194	* Init phase completed callback.
2195	*
2196	* @returns VBox status code.
2197	* @param pVM The VM handle.
2198	* @param enmWhat What has been completed.
2199	* @thread EMT(0)
2200	*/
2201	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2202	{
2203	switch (enmWhat)
2204	{
2205	case VMINITCOMPLETED_HWACCM:
2206	#ifdef VBOX_WITH_PCI_PASSTHROUGH
2207	if (pVM->pgm.s.fPciPassthrough)
2208	{
2209	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2210	AssertLogRelReturn(HWACCMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HWACCM);
2211	AssertLogRelReturn(HWACCMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2212
2213	/*
2214	* Report assignments to the IOMMU (hope that's good enough for now).
2215	*/
2216	if (pVM->pgm.s.fPciPassthrough)
2217	{
2218	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2219	AssertRCReturn(rc, rc);
2220	}
2221	}
2222	#else
2223	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2224	#endif
2225	break;
2226
2227	default:
2228	/* shut up gcc */
2229	break;
2230	}
2231
2232	return VINF_SUCCESS;
2233	}
2234
2235
2236	/**
2237	* Applies relocations to data and code managed by this component.
2238	*
2239	* This function will be called at init and whenever the VMM need to relocate it
2240	* self inside the GC.
2241	*
2242	* @param pVM The VM.
2243	* @param offDelta Relocation delta relative to old location.
2244	*/
2245	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2246	{
2247	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2248
2249	/*
2250	* Paging stuff.
2251	*/
2252	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2253
2254	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2255
2256	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2257	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2258	{
2259	PVMCPU pVCpu = &pVM->aCpus[i];
2260
2261	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2262
2263	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2264	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2265	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2266	}
2267
2268	/*
2269	* Trees.
2270	*/
2271	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2272
2273	/*
2274	* Ram ranges.
2275	*/
2276	if (pVM->pgm.s.pRamRangesXR3)
2277	{
2278	/* Update the pSelfRC pointers and relink them. */
2279	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2280	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2281	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2282	pgmR3PhysRelinkRamRanges(pVM);
2283
2284	/* Flush the RC TLB. */
2285	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2286	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2287	}
2288
2289	/*
2290	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2291	* be mapped and thus not included in the above exercise.
2292	*/
2293	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2294	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2295	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2296
2297	/*
2298	* Update the two page directories with all page table mappings.
2299	* (One or more of them have changed, that's why we're here.)
2300	*/
2301	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2302	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2303	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2304
2305	/* Relocate GC addresses of Page Tables. */
2306	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2307	{
2308	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2309	{
2310	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2311	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2312	}
2313	}
2314
2315	/*
2316	* Dynamic page mapping area.
2317	*/
2318	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2319	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2320	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2321
2322	if (pVM->pgm.s.pRCDynMap)
2323	{
2324	pVM->pgm.s.pRCDynMap += offDelta;
2325	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2326
2327	pDynMap->paPages += offDelta;
2328	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2329
2330	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2331	{
2332	paPages[iPage].pvPage += offDelta;
2333	paPages[iPage].uPte.pLegacy += offDelta;
2334	paPages[iPage].uPte.pPae += offDelta;
2335	}
2336	}
2337
2338	/*
2339	* The Zero page.
2340	*/
2341	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2342	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2343	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2344	#else
2345	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2346	#endif
2347
2348	/*
2349	* Physical and virtual handlers.
2350	*/
2351	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2352	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2353	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2354	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2355
2356	/*
2357	* The page pool.
2358	*/
2359	pgmR3PoolRelocate(pVM);
2360
2361	#ifdef VBOX_WITH_STATISTICS
2362	/*
2363	* Statistics.
2364	*/
2365	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2366	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2367	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2368	#endif
2369	}
2370
2371
2372	/**
2373	* Callback function for relocating a physical access handler.
2374	*
2375	* @returns 0 (continue enum)
2376	* @param pNode Pointer to a PGMPHYSHANDLER node.
2377	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2378	* not certain the delta will fit in a void pointer for all possible configs.
2379	*/
2380	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2381	{
2382	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2383	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2384	if (pHandler->pfnHandlerRC)
2385	pHandler->pfnHandlerRC += offDelta;
2386	if (pHandler->pvUserRC >= 0x10000)
2387	pHandler->pvUserRC += offDelta;
2388	return 0;
2389	}
2390
2391
2392	/**
2393	* Callback function for relocating a virtual access handler.
2394	*
2395	* @returns 0 (continue enum)
2396	* @param pNode Pointer to a PGMVIRTHANDLER node.
2397	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2398	* not certain the delta will fit in a void pointer for all possible configs.
2399	*/
2400	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2401	{
2402	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2403	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2404	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2405	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2406	Assert(pHandler->pfnHandlerRC);
2407	pHandler->pfnHandlerRC += offDelta;
2408	return 0;
2409	}
2410
2411
2412	/**
2413	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2414	*
2415	* @returns 0 (continue enum)
2416	* @param pNode Pointer to a PGMVIRTHANDLER node.
2417	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2418	* not certain the delta will fit in a void pointer for all possible configs.
2419	*/
2420	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2421	{
2422	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2423	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2424	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2425	Assert(pHandler->pfnHandlerRC);
2426	pHandler->pfnHandlerRC += offDelta;
2427	return 0;
2428	}
2429
2430
2431	/**
2432	* Resets a virtual CPU when unplugged.
2433	*
2434	* @param pVM The VM handle.
2435	* @param pVCpu The virtual CPU handle.
2436	*/
2437	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2438	{
2439	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2440	AssertRC(rc);
2441
2442	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2443	AssertRC(rc);
2444
2445	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2446
2447	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2448
2449	/*
2450	* Re-init other members.
2451	*/
2452	pVCpu->pgm.s.fA20Enabled = true;
2453
2454	/*
2455	* Clear the FFs PGM owns.
2456	*/
2457	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2458	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2459	}
2460
2461
2462	/**
2463	* The VM is being reset.
2464	*
2465	* For the PGM component this means that any PD write monitors
2466	* needs to be removed.
2467	*
2468	* @param pVM VM handle.
2469	*/
2470	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2471	{
2472	int rc;
2473
2474	LogFlow(("PGMR3Reset:\n"));
2475	VM_ASSERT_EMT(pVM);
2476
2477	pgmLock(pVM);
2478
2479	/*
2480	* Unfix any fixed mappings and disable CR3 monitoring.
2481	*/
2482	pVM->pgm.s.fMappingsFixed = false;
2483	pVM->pgm.s.fMappingsFixedRestored = false;
2484	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2485	pVM->pgm.s.cbMappingFixed = 0;
2486
2487	/*
2488	* Exit the guest paging mode before the pgm pool gets reset.
2489	* Important to clean up the amd64 case.
2490	*/
2491	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2492	{
2493	PVMCPU pVCpu = &pVM->aCpus[i];
2494	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2495	AssertRC(rc);
2496	}
2497
2498	#ifdef DEBUG
2499	DBGFR3InfoLog(pVM, "mappings", NULL);
2500	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2501	#endif
2502
2503	/*
2504	* Switch mode back to real mode. (before resetting the pgm pool!)
2505	*/
2506	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2507	{
2508	PVMCPU pVCpu = &pVM->aCpus[i];
2509
2510	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2511	AssertRC(rc);
2512
2513	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2514	}
2515
2516	/*
2517	* Reset the shadow page pool.
2518	*/
2519	pgmR3PoolReset(pVM);
2520
2521	/*
2522	* Re-init various other members and clear the FFs that PGM owns.
2523	*/
2524	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2525	{
2526	PVMCPU pVCpu = &pVM->aCpus[i];
2527
2528	pVCpu->pgm.s.fA20Enabled = true;
2529	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2530	PGMNotifyNxeChanged(pVCpu, false);
2531
2532	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2533	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2534	}
2535
2536	/*
2537	* Reset (zero) RAM and shadow ROM pages.
2538	*/
2539	rc = pgmR3PhysRamReset(pVM);
2540	if (RT_SUCCESS(rc))
2541	rc = pgmR3PhysRomReset(pVM);
2542
2543
2544	pgmUnlock(pVM);
2545	AssertReleaseRC(rc);
2546	}
2547
2548
2549	#ifdef VBOX_STRICT
2550	/**
2551	* VM state change callback for clearing fNoMorePhysWrites after
2552	* a snapshot has been created.
2553	*/
2554	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2555	{
2556	if ( enmState == VMSTATE_RUNNING
2557	\|\| enmState == VMSTATE_RESUMING)
2558	pVM->pgm.s.fNoMorePhysWrites = false;
2559	NOREF(enmOldState); NOREF(pvUser);
2560	}
2561	#endif
2562
2563	/**
2564	* Private API to reset fNoMorePhysWrites.
2565	*/
2566	VMMR3DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2567	{
2568	pVM->pgm.s.fNoMorePhysWrites = false;
2569	}
2570
2571	/**
2572	* Terminates the PGM.
2573	*
2574	* @returns VBox status code.
2575	* @param pVM Pointer to VM structure.
2576	*/
2577	VMMR3DECL(int) PGMR3Term(PVM pVM)
2578	{
2579	/* Must free shared pages here. */
2580	pgmLock(pVM);
2581	pgmR3PhysRamTerm(pVM);
2582	pgmR3PhysRomTerm(pVM);
2583	pgmUnlock(pVM);
2584
2585	PGMDeregisterStringFormatTypes();
2586	return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2587	}
2588
2589
2590	/**
2591	* Show paging mode.
2592	*
2593	* @param pVM VM Handle.
2594	* @param pHlp The info helpers.
2595	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2596	*/
2597	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2598	{
2599	/* digest argument. */
2600	bool fGuest, fShadow, fHost;
2601	if (pszArgs)
2602	pszArgs = RTStrStripL(pszArgs);
2603	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2604	fShadow = fHost = fGuest = true;
2605	else
2606	{
2607	fShadow = fHost = fGuest = false;
2608	if (strstr(pszArgs, "guest"))
2609	fGuest = true;
2610	if (strstr(pszArgs, "shadow"))
2611	fShadow = true;
2612	if (strstr(pszArgs, "host"))
2613	fHost = true;
2614	}
2615
2616	/** @todo SMP support! */
2617	/* print info. */
2618	if (fGuest)
2619	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2620	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2621	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2622	if (fShadow)
2623	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2624	if (fHost)
2625	{
2626	const char *psz;
2627	switch (pVM->pgm.s.enmHostMode)
2628	{
2629	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2630	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2631	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2632	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2633	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2634	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2635	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2636	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2637	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2638	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2639	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2640	default: psz = "unknown"; break;
2641	}
2642	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2643	}
2644	}
2645
2646
2647	/**
2648	* Dump registered MMIO ranges to the log.
2649	*
2650	* @param pVM VM Handle.
2651	* @param pHlp The info helpers.
2652	* @param pszArgs Arguments, ignored.
2653	*/
2654	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2655	{
2656	NOREF(pszArgs);
2657	pHlp->pfnPrintf(pHlp,
2658	"RAM ranges (pVM=%p)\n"
2659	"%.s %.s\n",
2660	pVM,
2661	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2662	sizeof(RTHCPTR) * 2, "pvHC ");
2663
2664	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2665	pHlp->pfnPrintf(pHlp,
2666	"%RGp-%RGp %RHv %s\n",
2667	pCur->GCPhys,
2668	pCur->GCPhysLast,
2669	pCur->pvR3,
2670	pCur->pszDesc);
2671	}
2672
2673	/**
2674	* Dump the page directory to the log.
2675	*
2676	* @param pVM VM Handle.
2677	* @param pHlp The info helpers.
2678	* @param pszArgs Arguments, ignored.
2679	*/
2680	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2681	{
2682	/** @todo SMP support!! */
2683	PVMCPU pVCpu = &pVM->aCpus[0];
2684
2685	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2686	/* Big pages supported? */
2687	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2688
2689	/* Global pages supported? */
2690	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2691
2692	NOREF(pszArgs);
2693
2694	/*
2695	* Get page directory addresses.
2696	*/
2697	pgmLock(pVM);
2698	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2699	Assert(pPDSrc);
2700
2701	/*
2702	* Iterate the page directory.
2703	*/
2704	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2705	{
2706	X86PDE PdeSrc = pPDSrc->a[iPD];
2707	if (PdeSrc.n.u1Present)
2708	{
2709	if (PdeSrc.b.u1Size && fPSE)
2710	pHlp->pfnPrintf(pHlp,
2711	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2712	iPD,
2713	pgmGstGet4MBPhysPage(pVM, PdeSrc),
2714	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2715	else
2716	pHlp->pfnPrintf(pHlp,
2717	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2718	iPD,
2719	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2720	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2721	}
2722	}
2723	pgmUnlock(pVM);
2724	}
2725
2726
2727	/**
2728	* Service a VMMCALLRING3_PGM_LOCK call.
2729	*
2730	* @returns VBox status code.
2731	* @param pVM The VM handle.
2732	*/
2733	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2734	{
2735	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2736	AssertRC(rc);
2737	return rc;
2738	}
2739
2740
2741	/**
2742	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2743	*
2744	* @returns PGM_TYPE_*.
2745	* @param pgmMode The mode value to convert.
2746	*/
2747	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2748	{
2749	switch (pgmMode)
2750	{
2751	case PGMMODE_REAL: return PGM_TYPE_REAL;
2752	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2753	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2754	case PGMMODE_PAE:
2755	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2756	case PGMMODE_AMD64:
2757	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2758	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2759	case PGMMODE_EPT: return PGM_TYPE_EPT;
2760	default:
2761	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2762	}
2763	}
2764
2765
2766	/**
2767	* Gets the index into the paging mode data array of a SHW+GST mode.
2768	*
2769	* @returns PGM::paPagingData index.
2770	* @param uShwType The shadow paging mode type.
2771	* @param uGstType The guest paging mode type.
2772	*/
2773	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2774	{
2775	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2776	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2777	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2778	+ (uGstType - PGM_TYPE_REAL);
2779	}
2780
2781
2782	/**
2783	* Gets the index into the paging mode data array of a SHW+GST mode.
2784	*
2785	* @returns PGM::paPagingData index.
2786	* @param enmShw The shadow paging mode.
2787	* @param enmGst The guest paging mode.
2788	*/
2789	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2790	{
2791	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2792	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2793	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2794	}
2795
2796
2797	/**
2798	* Calculates the max data index.
2799	* @returns The number of entries in the paging data array.
2800	*/
2801	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2802	{
2803	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2804	}
2805
2806
2807	/**
2808	* Initializes the paging mode data kept in PGM::paModeData.
2809	*
2810	* @param pVM The VM handle.
2811	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2812	* This is used early in the init process to avoid trouble with PDM
2813	* not being initialized yet.
2814	*/
2815	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2816	{
2817	PPGMMODEDATA pModeData;
2818	int rc;
2819
2820	/*
2821	* Allocate the array on the first call.
2822	*/
2823	if (!pVM->pgm.s.paModeData)
2824	{
2825	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2826	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2827	}
2828
2829	/*
2830	* Initialize the array entries.
2831	*/
2832	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2833	pModeData->uShwType = PGM_TYPE_32BIT;
2834	pModeData->uGstType = PGM_TYPE_REAL;
2835	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2836	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2837	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2838
2839	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2840	pModeData->uShwType = PGM_TYPE_32BIT;
2841	pModeData->uGstType = PGM_TYPE_PROT;
2842	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2843	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2844	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2845
2846	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2847	pModeData->uShwType = PGM_TYPE_32BIT;
2848	pModeData->uGstType = PGM_TYPE_32BIT;
2849	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2850	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2851	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2852
2853	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2854	pModeData->uShwType = PGM_TYPE_PAE;
2855	pModeData->uGstType = PGM_TYPE_REAL;
2856	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2857	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2858	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2859
2860	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2861	pModeData->uShwType = PGM_TYPE_PAE;
2862	pModeData->uGstType = PGM_TYPE_PROT;
2863	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2864	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2865	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2866
2867	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2868	pModeData->uShwType = PGM_TYPE_PAE;
2869	pModeData->uGstType = PGM_TYPE_32BIT;
2870	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2871	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2872	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2873
2874	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2875	pModeData->uShwType = PGM_TYPE_PAE;
2876	pModeData->uGstType = PGM_TYPE_PAE;
2877	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2878	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2879	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2880
2881	#ifdef VBOX_WITH_64_BITS_GUESTS
2882	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2883	pModeData->uShwType = PGM_TYPE_AMD64;
2884	pModeData->uGstType = PGM_TYPE_AMD64;
2885	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2886	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2887	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2888	#endif
2889
2890	/* The nested paging mode. */
2891	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2892	pModeData->uShwType = PGM_TYPE_NESTED;
2893	pModeData->uGstType = PGM_TYPE_REAL;
2894	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896
2897	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2898	pModeData->uShwType = PGM_TYPE_NESTED;
2899	pModeData->uGstType = PGM_TYPE_PROT;
2900	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902
2903	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2904	pModeData->uShwType = PGM_TYPE_NESTED;
2905	pModeData->uGstType = PGM_TYPE_32BIT;
2906	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2907	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2908
2909	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2910	pModeData->uShwType = PGM_TYPE_NESTED;
2911	pModeData->uGstType = PGM_TYPE_PAE;
2912	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2913	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2914
2915	#ifdef VBOX_WITH_64_BITS_GUESTS
2916	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2917	pModeData->uShwType = PGM_TYPE_NESTED;
2918	pModeData->uGstType = PGM_TYPE_AMD64;
2919	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2920	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2921	#endif
2922
2923	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2924	switch (pVM->pgm.s.enmHostMode)
2925	{
2926	#if HC_ARCH_BITS == 32
2927	case SUPPAGINGMODE_32_BIT:
2928	case SUPPAGINGMODE_32_BIT_GLOBAL:
2929	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2930	{
2931	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2932	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2933	}
2934	# ifdef VBOX_WITH_64_BITS_GUESTS
2935	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2936	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2937	# endif
2938	break;
2939
2940	case SUPPAGINGMODE_PAE:
2941	case SUPPAGINGMODE_PAE_NX:
2942	case SUPPAGINGMODE_PAE_GLOBAL:
2943	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2944	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2945	{
2946	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2947	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2948	}
2949	# ifdef VBOX_WITH_64_BITS_GUESTS
2950	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2951	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2952	# endif
2953	break;
2954	#endif /* HC_ARCH_BITS == 32 */
2955
2956	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2957	case SUPPAGINGMODE_AMD64:
2958	case SUPPAGINGMODE_AMD64_GLOBAL:
2959	case SUPPAGINGMODE_AMD64_NX:
2960	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2961	# ifdef VBOX_WITH_64_BITS_GUESTS
2962	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2963	# else
2964	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2965	# endif
2966	{
2967	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2968	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2969	}
2970	break;
2971	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2972
2973	default:
2974	AssertFailed();
2975	break;
2976	}
2977
2978	/* Extended paging (EPT) / Intel VT-x */
2979	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2980	pModeData->uShwType = PGM_TYPE_EPT;
2981	pModeData->uGstType = PGM_TYPE_REAL;
2982	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2983	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2984	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2985
2986	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2987	pModeData->uShwType = PGM_TYPE_EPT;
2988	pModeData->uGstType = PGM_TYPE_PROT;
2989	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2990	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2991	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2992
2993	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2994	pModeData->uShwType = PGM_TYPE_EPT;
2995	pModeData->uGstType = PGM_TYPE_32BIT;
2996	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2997	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2998	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2999
3000	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3001	pModeData->uShwType = PGM_TYPE_EPT;
3002	pModeData->uGstType = PGM_TYPE_PAE;
3003	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3004	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3005	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3006
3007	#ifdef VBOX_WITH_64_BITS_GUESTS
3008	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3009	pModeData->uShwType = PGM_TYPE_EPT;
3010	pModeData->uGstType = PGM_TYPE_AMD64;
3011	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3012	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3013	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3014	#endif
3015	return VINF_SUCCESS;
3016	}
3017
3018
3019	/**
3020	* Switch to different (or relocated in the relocate case) mode data.
3021	*
3022	* @param pVM The VM handle.
3023	* @param pVCpu The VMCPU to operate on.
3024	* @param enmShw The the shadow paging mode.
3025	* @param enmGst The the guest paging mode.
3026	*/
3027	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3028	{
3029	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3030
3031	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3032	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3033
3034	/* shadow */
3035	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3036	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3037	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3038	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3039	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3040
3041	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3042	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3043
3044	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3045	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3046
3047
3048	/* guest */
3049	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3050	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3051	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3052	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3053	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3054	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3055	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3056	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3057	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3058	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3059	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3060	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3061
3062	/* both */
3063	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3064	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3065	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3066	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3067	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3068	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3069	#ifdef VBOX_STRICT
3070	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3071	#endif
3072	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3073	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3074
3075	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3076	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3077	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3078	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3079	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3080	#ifdef VBOX_STRICT
3081	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3082	#endif
3083	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3084	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3085
3086	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3087	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3088	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3089	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3090	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3091	#ifdef VBOX_STRICT
3092	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3093	#endif
3094	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3095	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3096	}
3097
3098
3099	/**
3100	* Calculates the shadow paging mode.
3101	*
3102	* @returns The shadow paging mode.
3103	* @param pVM VM handle.
3104	* @param enmGuestMode The guest mode.
3105	* @param enmHostMode The host mode.
3106	* @param enmShadowMode The current shadow mode.
3107	* @param penmSwitcher Where to store the switcher to use.
3108	* VMMSWITCHER_INVALID means no change.
3109	*/
3110	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3111	{
3112	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3113	switch (enmGuestMode)
3114	{
3115	/*
3116	* When switching to real or protected mode we don't change
3117	* anything since it's likely that we'll switch back pretty soon.
3118	*
3119	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3120	* and is supposed to determine which shadow paging and switcher to
3121	* use during init.
3122	*/
3123	case PGMMODE_REAL:
3124	case PGMMODE_PROTECTED:
3125	if ( enmShadowMode != PGMMODE_INVALID
3126	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3127	break; /* (no change) */
3128
3129	switch (enmHostMode)
3130	{
3131	case SUPPAGINGMODE_32_BIT:
3132	case SUPPAGINGMODE_32_BIT_GLOBAL:
3133	enmShadowMode = PGMMODE_32_BIT;
3134	enmSwitcher = VMMSWITCHER_32_TO_32;
3135	break;
3136
3137	case SUPPAGINGMODE_PAE:
3138	case SUPPAGINGMODE_PAE_NX:
3139	case SUPPAGINGMODE_PAE_GLOBAL:
3140	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3141	enmShadowMode = PGMMODE_PAE;
3142	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3143	#ifdef DEBUG_bird
3144	if (RTEnvExist("VBOX_32BIT"))
3145	{
3146	enmShadowMode = PGMMODE_32_BIT;
3147	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3148	}
3149	#endif
3150	break;
3151
3152	case SUPPAGINGMODE_AMD64:
3153	case SUPPAGINGMODE_AMD64_GLOBAL:
3154	case SUPPAGINGMODE_AMD64_NX:
3155	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3156	enmShadowMode = PGMMODE_PAE;
3157	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3158	#ifdef DEBUG_bird
3159	if (RTEnvExist("VBOX_32BIT"))
3160	{
3161	enmShadowMode = PGMMODE_32_BIT;
3162	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3163	}
3164	#endif
3165	break;
3166
3167	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3168	}
3169	break;
3170
3171	case PGMMODE_32_BIT:
3172	switch (enmHostMode)
3173	{
3174	case SUPPAGINGMODE_32_BIT:
3175	case SUPPAGINGMODE_32_BIT_GLOBAL:
3176	enmShadowMode = PGMMODE_32_BIT;
3177	enmSwitcher = VMMSWITCHER_32_TO_32;
3178	break;
3179
3180	case SUPPAGINGMODE_PAE:
3181	case SUPPAGINGMODE_PAE_NX:
3182	case SUPPAGINGMODE_PAE_GLOBAL:
3183	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3184	enmShadowMode = PGMMODE_PAE;
3185	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3186	#ifdef DEBUG_bird
3187	if (RTEnvExist("VBOX_32BIT"))
3188	{
3189	enmShadowMode = PGMMODE_32_BIT;
3190	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3191	}
3192	#endif
3193	break;
3194
3195	case SUPPAGINGMODE_AMD64:
3196	case SUPPAGINGMODE_AMD64_GLOBAL:
3197	case SUPPAGINGMODE_AMD64_NX:
3198	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3199	enmShadowMode = PGMMODE_PAE;
3200	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3201	#ifdef DEBUG_bird
3202	if (RTEnvExist("VBOX_32BIT"))
3203	{
3204	enmShadowMode = PGMMODE_32_BIT;
3205	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3206	}
3207	#endif
3208	break;
3209
3210	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3211	}
3212	break;
3213
3214	case PGMMODE_PAE:
3215	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3216	switch (enmHostMode)
3217	{
3218	case SUPPAGINGMODE_32_BIT:
3219	case SUPPAGINGMODE_32_BIT_GLOBAL:
3220	enmShadowMode = PGMMODE_PAE;
3221	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3222	break;
3223
3224	case SUPPAGINGMODE_PAE:
3225	case SUPPAGINGMODE_PAE_NX:
3226	case SUPPAGINGMODE_PAE_GLOBAL:
3227	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3228	enmShadowMode = PGMMODE_PAE;
3229	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3230	break;
3231
3232	case SUPPAGINGMODE_AMD64:
3233	case SUPPAGINGMODE_AMD64_GLOBAL:
3234	case SUPPAGINGMODE_AMD64_NX:
3235	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3236	enmShadowMode = PGMMODE_PAE;
3237	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3238	break;
3239
3240	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3241	}
3242	break;
3243
3244	case PGMMODE_AMD64:
3245	case PGMMODE_AMD64_NX:
3246	switch (enmHostMode)
3247	{
3248	case SUPPAGINGMODE_32_BIT:
3249	case SUPPAGINGMODE_32_BIT_GLOBAL:
3250	enmShadowMode = PGMMODE_AMD64;
3251	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3252	break;
3253
3254	case SUPPAGINGMODE_PAE:
3255	case SUPPAGINGMODE_PAE_NX:
3256	case SUPPAGINGMODE_PAE_GLOBAL:
3257	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3258	enmShadowMode = PGMMODE_AMD64;
3259	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3260	break;
3261
3262	case SUPPAGINGMODE_AMD64:
3263	case SUPPAGINGMODE_AMD64_GLOBAL:
3264	case SUPPAGINGMODE_AMD64_NX:
3265	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3266	enmShadowMode = PGMMODE_AMD64;
3267	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3268	break;
3269
3270	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3271	}
3272	break;
3273
3274
3275	default:
3276	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3277	*penmSwitcher = VMMSWITCHER_INVALID;
3278	return PGMMODE_INVALID;
3279	}
3280	/* Override the shadow mode is nested paging is active. */
3281	pVM->pgm.s.fNestedPaging = HWACCMIsNestedPagingActive(pVM);
3282	if (pVM->pgm.s.fNestedPaging)
3283	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3284
3285	*penmSwitcher = enmSwitcher;
3286	return enmShadowMode;
3287	}
3288
3289
3290	/**
3291	* Performs the actual mode change.
3292	* This is called by PGMChangeMode and pgmR3InitPaging().
3293	*
3294	* @returns VBox status code. May suspend or power off the VM on error, but this
3295	* will trigger using FFs and not status codes.
3296	*
3297	* @param pVM VM handle.
3298	* @param pVCpu The VMCPU to operate on.
3299	* @param enmGuestMode The new guest mode. This is assumed to be different from
3300	* the current mode.
3301	*/
3302	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3303	{
3304	#if HC_ARCH_BITS == 32
3305	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3306	#endif
3307	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3308
3309	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3310	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3311
3312	/*
3313	* Calc the shadow mode and switcher.
3314	*/
3315	VMMSWITCHER enmSwitcher;
3316	PGMMODE enmShadowMode;
3317	enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3318
3319	#ifdef VBOX_WITH_RAW_MODE
3320	if (enmSwitcher != VMMSWITCHER_INVALID)
3321	{
3322	/*
3323	* Select new switcher.
3324	*/
3325	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3326	if (RT_FAILURE(rc))
3327	{
3328	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3329	return rc;
3330	}
3331	}
3332	#endif
3333
3334	/*
3335	* Exit old mode(s).
3336	*/
3337	#if HC_ARCH_BITS == 32
3338	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3339	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3340	&& enmShadowMode == PGMMODE_NESTED);
3341	#else
3342	const bool fForceShwEnterExit = false;
3343	#endif
3344	/* shadow */
3345	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3346	\|\| fForceShwEnterExit)
3347	{
3348	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3349	if (PGM_SHW_PFN(Exit, pVCpu))
3350	{
3351	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3352	if (RT_FAILURE(rc))
3353	{
3354	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3355	return rc;
3356	}
3357	}
3358
3359	}
3360	else
3361	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3362
3363	/* guest */
3364	if (PGM_GST_PFN(Exit, pVCpu))
3365	{
3366	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3367	if (RT_FAILURE(rc))
3368	{
3369	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3370	return rc;
3371	}
3372	}
3373
3374	/*
3375	* Load new paging mode data.
3376	*/
3377	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3378
3379	/*
3380	* Enter new shadow mode (if changed).
3381	*/
3382	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3383	\|\| fForceShwEnterExit)
3384	{
3385	int rc;
3386	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3387	switch (enmShadowMode)
3388	{
3389	case PGMMODE_32_BIT:
3390	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3391	break;
3392	case PGMMODE_PAE:
3393	case PGMMODE_PAE_NX:
3394	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3395	break;
3396	case PGMMODE_AMD64:
3397	case PGMMODE_AMD64_NX:
3398	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3399	break;
3400	case PGMMODE_NESTED:
3401	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3402	break;
3403	case PGMMODE_EPT:
3404	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3405	break;
3406	case PGMMODE_REAL:
3407	case PGMMODE_PROTECTED:
3408	default:
3409	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3410	return VERR_INTERNAL_ERROR;
3411	}
3412	if (RT_FAILURE(rc))
3413	{
3414	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3415	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3416	return rc;
3417	}
3418	}
3419
3420	/*
3421	* Always flag the necessary updates
3422	*/
3423	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3424
3425	/*
3426	* Enter the new guest and shadow+guest modes.
3427	*/
3428	int rc = -1;
3429	int rc2 = -1;
3430	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3431	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3432	switch (enmGuestMode)
3433	{
3434	case PGMMODE_REAL:
3435	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3436	switch (pVCpu->pgm.s.enmShadowMode)
3437	{
3438	case PGMMODE_32_BIT:
3439	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3440	break;
3441	case PGMMODE_PAE:
3442	case PGMMODE_PAE_NX:
3443	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3444	break;
3445	case PGMMODE_NESTED:
3446	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3447	break;
3448	case PGMMODE_EPT:
3449	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3450	break;
3451	case PGMMODE_AMD64:
3452	case PGMMODE_AMD64_NX:
3453	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3454	default: AssertFailed(); break;
3455	}
3456	break;
3457
3458	case PGMMODE_PROTECTED:
3459	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3460	switch (pVCpu->pgm.s.enmShadowMode)
3461	{
3462	case PGMMODE_32_BIT:
3463	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3464	break;
3465	case PGMMODE_PAE:
3466	case PGMMODE_PAE_NX:
3467	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3468	break;
3469	case PGMMODE_NESTED:
3470	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3471	break;
3472	case PGMMODE_EPT:
3473	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3474	break;
3475	case PGMMODE_AMD64:
3476	case PGMMODE_AMD64_NX:
3477	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3478	default: AssertFailed(); break;
3479	}
3480	break;
3481
3482	case PGMMODE_32_BIT:
3483	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3484	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3485	switch (pVCpu->pgm.s.enmShadowMode)
3486	{
3487	case PGMMODE_32_BIT:
3488	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3489	break;
3490	case PGMMODE_PAE:
3491	case PGMMODE_PAE_NX:
3492	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3493	break;
3494	case PGMMODE_NESTED:
3495	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3496	break;
3497	case PGMMODE_EPT:
3498	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3499	break;
3500	case PGMMODE_AMD64:
3501	case PGMMODE_AMD64_NX:
3502	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3503	default: AssertFailed(); break;
3504	}
3505	break;
3506
3507	case PGMMODE_PAE_NX:
3508	case PGMMODE_PAE:
3509	{
3510	uint32_t u32Dummy, u32Features;
3511
3512	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3513	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3514	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3515	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3516
3517	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3518	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3519	switch (pVCpu->pgm.s.enmShadowMode)
3520	{
3521	case PGMMODE_PAE:
3522	case PGMMODE_PAE_NX:
3523	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3524	break;
3525	case PGMMODE_NESTED:
3526	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3527	break;
3528	case PGMMODE_EPT:
3529	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3530	break;
3531	case PGMMODE_32_BIT:
3532	case PGMMODE_AMD64:
3533	case PGMMODE_AMD64_NX:
3534	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3535	default: AssertFailed(); break;
3536	}
3537	break;
3538	}
3539
3540	#ifdef VBOX_WITH_64_BITS_GUESTS
3541	case PGMMODE_AMD64_NX:
3542	case PGMMODE_AMD64:
3543	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3544	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3545	switch (pVCpu->pgm.s.enmShadowMode)
3546	{
3547	case PGMMODE_AMD64:
3548	case PGMMODE_AMD64_NX:
3549	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3550	break;
3551	case PGMMODE_NESTED:
3552	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3553	break;
3554	case PGMMODE_EPT:
3555	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3556	break;
3557	case PGMMODE_32_BIT:
3558	case PGMMODE_PAE:
3559	case PGMMODE_PAE_NX:
3560	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3561	default: AssertFailed(); break;
3562	}
3563	break;
3564	#endif
3565
3566	default:
3567	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3568	rc = VERR_NOT_IMPLEMENTED;
3569	break;
3570	}
3571
3572	/* status codes. */
3573	AssertRC(rc);
3574	AssertRC(rc2);
3575	if (RT_SUCCESS(rc))
3576	{
3577	rc = rc2;
3578	if (RT_SUCCESS(rc)) /* no informational status codes. */
3579	rc = VINF_SUCCESS;
3580	}
3581
3582	/* Notify HWACCM as well. */
3583	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3584	return rc;
3585	}
3586
3587
3588	/**
3589	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3590	*
3591	* @returns VBox status code, fully asserted.
3592	* @param pVCpu The VMCPU to operate on.
3593	*/
3594	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3595	{
3596	/* Unmap the old CR3 value before flushing everything. */
3597	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3598	AssertRC(rc);
3599
3600	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3601	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3602	AssertRC(rc);
3603	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3604	return rc;
3605	}
3606
3607
3608	/**
3609	* Called by pgmPoolFlushAllInt after flushing the pool.
3610	*
3611	* @returns VBox status code, fully asserted.
3612	* @param pVM The VM handle.
3613	* @param pVCpu The VMCPU to operate on.
3614	*/
3615	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3616	{
3617	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3618	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3619	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3620	AssertRCReturn(rc, rc);
3621	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3622
3623	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3624	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3625	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3626	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3627	return rc;
3628	}
3629
3630	#ifdef VBOX_WITH_DEBUGGER
3631
3632	/**
3633	* The '.pgmram' command.
3634	*
3635	* @returns VBox status.
3636	* @param pCmd Pointer to the command descriptor (as registered).
3637	* @param pCmdHlp Pointer to command helper functions.
3638	* @param pVM Pointer to the current VM (if any).
3639	* @param paArgs Pointer to (readonly) array of arguments.
3640	* @param cArgs Number of arguments in the array.
3641	*/
3642	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3643	{
3644	/*
3645	* Validate input.
3646	*/
3647	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3648	if (!pVM)
3649	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3650	if (!pVM->pgm.s.pRamRangesXR3)
3651	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3652
3653	/*
3654	* Dump the ranges.
3655	*/
3656	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3657	PPGMRAMRANGE pRam;
3658	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
3659	{
3660	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3661	"%RGp - %RGp %p\n",
3662	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
3663	if (RT_FAILURE(rc))
3664	return rc;
3665	}
3666
3667	return VINF_SUCCESS;
3668	}
3669
3670
3671	/**
3672	* The '.pgmerror' and '.pgmerroroff' commands.
3673	*
3674	* @returns VBox status.
3675	* @param pCmd Pointer to the command descriptor (as registered).
3676	* @param pCmdHlp Pointer to command helper functions.
3677	* @param pVM Pointer to the current VM (if any).
3678	* @param paArgs Pointer to (readonly) array of arguments.
3679	* @param cArgs Number of arguments in the array.
3680	*/
3681	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3682	{
3683	/*
3684	* Validate input.
3685	*/
3686	if (!pVM)
3687	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3688	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
3689	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
3690
3691	if (!cArgs)
3692	{
3693	/*
3694	* Print the list of error injection locations with status.
3695	*/
3696	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
3697	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3698	}
3699	else
3700	{
3701
3702	/*
3703	* String switch on where to inject the error.
3704	*/
3705	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
3706	const char *pszWhere = paArgs[0].u.pszString;
3707	if (!strcmp(pszWhere, "handy"))
3708	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
3709	else
3710	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
3711	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
3712	}
3713	return VINF_SUCCESS;
3714	}
3715
3716
3717	/**
3718	* The '.pgmsync' command.
3719	*
3720	* @returns VBox status.
3721	* @param pCmd Pointer to the command descriptor (as registered).
3722	* @param pCmdHlp Pointer to command helper functions.
3723	* @param pVM Pointer to the current VM (if any).
3724	* @param paArgs Pointer to (readonly) array of arguments.
3725	* @param cArgs Number of arguments in the array.
3726	*/
3727	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3728	{
3729	/** @todo SMP support */
3730
3731	/*
3732	* Validate input.
3733	*/
3734	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3735	if (!pVM)
3736	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3737
3738	PVMCPU pVCpu = &pVM->aCpus[0];
3739
3740	/*
3741	* Force page directory sync.
3742	*/
3743	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3744
3745	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3746	if (RT_FAILURE(rc))
3747	return rc;
3748
3749	return VINF_SUCCESS;
3750	}
3751
3752
3753	#ifdef VBOX_STRICT
3754	/**
3755	* The '.pgmassertcr3' command.
3756	*
3757	* @returns VBox status.
3758	* @param pCmd Pointer to the command descriptor (as registered).
3759	* @param pCmdHlp Pointer to command helper functions.
3760	* @param pVM Pointer to the current VM (if any).
3761	* @param paArgs Pointer to (readonly) array of arguments.
3762	* @param cArgs Number of arguments in the array.
3763	*/
3764	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3765	{
3766	/** @todo SMP support!! */
3767
3768	/*
3769	* Validate input.
3770	*/
3771	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3772	if (!pVM)
3773	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3774
3775	PVMCPU pVCpu = &pVM->aCpus[0];
3776
3777	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
3778	if (RT_FAILURE(rc))
3779	return rc;
3780
3781	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
3782
3783	return VINF_SUCCESS;
3784	}
3785	#endif /* VBOX_STRICT */
3786
3787
3788	/**
3789	* The '.pgmsyncalways' command.
3790	*
3791	* @returns VBox status.
3792	* @param pCmd Pointer to the command descriptor (as registered).
3793	* @param pCmdHlp Pointer to command helper functions.
3794	* @param pVM Pointer to the current VM (if any).
3795	* @param paArgs Pointer to (readonly) array of arguments.
3796	* @param cArgs Number of arguments in the array.
3797	*/
3798	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3799	{
3800	/** @todo SMP support!! */
3801	PVMCPU pVCpu = &pVM->aCpus[0];
3802
3803	/*
3804	* Validate input.
3805	*/
3806	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3807	if (!pVM)
3808	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3809
3810	/*
3811	* Force page directory sync.
3812	*/
3813	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3814	{
3815	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3816	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3817	}
3818	else
3819	{
3820	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3821	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3822	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3823	}
3824	}
3825
3826
3827	/**
3828	* The '.pgmphystofile' command.
3829	*
3830	* @returns VBox status.
3831	* @param pCmd Pointer to the command descriptor (as registered).
3832	* @param pCmdHlp Pointer to command helper functions.
3833	* @param pVM Pointer to the current VM (if any).
3834	* @param paArgs Pointer to (readonly) array of arguments.
3835	* @param cArgs Number of arguments in the array.
3836	*/
3837	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3838	{
3839	/*
3840	* Validate input.
3841	*/
3842	NOREF(pCmd);
3843	if (!pVM)
3844	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3845	if ( cArgs < 1
3846	\|\| cArgs > 2
3847	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
3848	\|\| ( cArgs > 1
3849	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
3850	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
3851	if ( cArgs >= 2
3852	&& strcmp(paArgs[1].u.pszString, "nozero"))
3853	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
3854	bool fIncZeroPgs = cArgs < 2;
3855
3856	/*
3857	* Open the output file and get the ram parameters.
3858	*/
3859	RTFILE hFile;
3860	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
3861	if (RT_FAILURE(rc))
3862	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
3863
3864	uint32_t cbRamHole = 0;
3865	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
3866	uint64_t cbRam = 0;
3867	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
3868	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
3869
3870	/*
3871	* Dump the physical memory, page by page.
3872	*/
3873	RTGCPHYS GCPhys = 0;
3874	char abZeroPg[PAGE_SIZE];
3875	RT_ZERO(abZeroPg);
3876
3877	pgmLock(pVM);
3878	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3879	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
3880	pRam = pRam->pNextR3)
3881	{
3882	/* fill the gap */
3883	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
3884	{
3885	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
3886	{
3887	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3888	GCPhys += PAGE_SIZE;
3889	}
3890	}
3891
3892	PCPGMPAGE pPage = &pRam->aPages[0];
3893	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
3894	{
3895	if ( PGM_PAGE_IS_ZERO(pPage)
3896	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3897	{
3898	if (fIncZeroPgs)
3899	{
3900	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3901	if (RT_FAILURE(rc))
3902	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3903	}
3904	}
3905	else
3906	{
3907	switch (PGM_PAGE_GET_TYPE(pPage))
3908	{
3909	case PGMPAGETYPE_RAM:
3910	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
3911	case PGMPAGETYPE_ROM:
3912	case PGMPAGETYPE_MMIO2:
3913	{
3914	void const *pvPage;
3915	PGMPAGEMAPLOCK Lock;
3916	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
3917	if (RT_SUCCESS(rc))
3918	{
3919	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
3920	PGMPhysReleasePageMappingLock(pVM, &Lock);
3921	if (RT_FAILURE(rc))
3922	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3923	}
3924	else
3925	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3926	break;
3927	}
3928
3929	default:
3930	AssertFailed();
3931	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3932	case PGMPAGETYPE_MMIO:
3933	if (fIncZeroPgs)
3934	{
3935	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3936	if (RT_FAILURE(rc))
3937	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3938	}
3939	break;
3940	}
3941	}
3942
3943
3944	/* advance */
3945	GCPhys += PAGE_SIZE;
3946	pPage++;
3947	}
3948	}
3949	pgmUnlock(pVM);
3950
3951	RTFileClose(hFile);
3952	if (RT_SUCCESS(rc))
3953	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
3954	return VINF_SUCCESS;
3955	}
3956
3957	#endif /* VBOX_WITH_DEBUGGER */
3958
3959	/**
3960	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3961	*/
3962	typedef struct PGMCHECKINTARGS
3963	{
3964	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3965	PPGMPHYSHANDLER pPrevPhys;
3966	PPGMVIRTHANDLER pPrevVirt;
3967	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3968	PVM pVM;
3969	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3970
3971	/**
3972	* Validate a node in the physical handler tree.
3973	*
3974	* @returns 0 on if ok, other wise 1.
3975	* @param pNode The handler node.
3976	* @param pvUser pVM.
3977	*/
3978	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3979	{
3980	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3981	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3982	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3983	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3984	AssertReleaseMsg( !pArgs->pPrevPhys
3985	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3986	("pPrevPhys=%p %RGp-%RGp %s\n"
3987	" pCur=%p %RGp-%RGp %s\n",
3988	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3989	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3990	pArgs->pPrevPhys = pCur;
3991	return 0;
3992	}
3993
3994
3995	/**
3996	* Validate a node in the virtual handler tree.
3997	*
3998	* @returns 0 on if ok, other wise 1.
3999	* @param pNode The handler node.
4000	* @param pvUser pVM.
4001	*/
4002	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4003	{
4004	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4005	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4006	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4007	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4008	AssertReleaseMsg( !pArgs->pPrevVirt
4009	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4010	("pPrevVirt=%p %RGv-%RGv %s\n"
4011	" pCur=%p %RGv-%RGv %s\n",
4012	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4013	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4014	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4015	{
4016	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4017	("pCur=%p %RGv-%RGv %s\n"
4018	"iPage=%d offVirtHandle=%#x expected %#x\n",
4019	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4020	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4021	}
4022	pArgs->pPrevVirt = pCur;
4023	return 0;
4024	}
4025
4026
4027	/**
4028	* Validate a node in the virtual handler tree.
4029	*
4030	* @returns 0 on if ok, other wise 1.
4031	* @param pNode The handler node.
4032	* @param pvUser pVM.
4033	*/
4034	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4035	{
4036	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4037	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4038	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4039	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4040	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4041	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4042	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4043	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4044	" pCur=%p %RGp-%RGp\n",
4045	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4046	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4047	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4048	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4049	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4050	" pCur=%p %RGp-%RGp\n",
4051	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4052	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4053	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4054	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4055	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4056	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4057	{
4058	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4059	for (;;)
4060	{
4061	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4062	AssertReleaseMsg(pCur2 != pCur,
4063	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4064	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4065	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4066	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4067	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4068	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4069	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4070	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4071	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4072	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4073	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4074	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4075	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4076	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4077	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4078	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4079	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4080	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4081	break;
4082	}
4083	}
4084
4085	pArgs->pPrevPhys2Virt = pCur;
4086	return 0;
4087	}
4088
4089
4090	/**
4091	* Perform an integrity check on the PGM component.
4092	*
4093	* @returns VINF_SUCCESS if everything is fine.
4094	* @returns VBox error status after asserting on integrity breach.
4095	* @param pVM The VM handle.
4096	*/
4097	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4098	{
4099	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4100
4101	/*
4102	* Check the trees.
4103	*/
4104	int cErrors = 0;
4105	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4106	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4107	PGMCHECKINTARGS Args = s_LeftToRight;
4108	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4109	Args = s_RightToLeft;
4110	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4111	Args = s_LeftToRight;
4112	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4113	Args = s_RightToLeft;
4114	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4115	Args = s_LeftToRight;
4116	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4117	Args = s_RightToLeft;
4118	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4119	Args = s_LeftToRight;
4120	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4121	Args = s_RightToLeft;
4122	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4123
4124	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4125	}
4126

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 41393

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