PGM.cpp@ 41468

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PGM.cpp: A couple of words about the A20 implementation.
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1	/* $Id: PGM.cpp 41468 2012-05-28 22:55:35Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred
30	* to as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	*
99	* @subsection sec_pgm_misc_A20 The A20 Gate
100	*
101	* PGM implements the A20 gate masking when translating a virtual guest address
102	* into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
103	* the code reading the guest page table entries during shadowing.
104	*
105	* The A20 gate implementation is per CPU core. It can be configured on a per
106	* core basis via the keyboard device and PC architecture device. This is
107	* probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
108	* guest OSes try pushing things anyway, so who cares.
109	*
110	* The keyboard device and the PC architecture device doesn't OR their A20
111	* config bits together, rather they are currently implemented such that they
112	* mirror the CPU state. So, flipping the bit in either of them will change the
113	* A20 state.
114	*
115	* The A20 state will change immediately, transmeta fashion. There is no delays
116	* due to buses, wiring or other physical stuff.
117	*
118	* @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
119	*
120	*
121	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
122	*
123	* The differences between legacy PAE and long mode PAE are:
124	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
125	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
126	* usual meanings while 6 is ignored (AMD). This means that upon switching to
127	* legacy PAE mode we'll have to clear these bits and when going to long mode
128	* they must be set. This applies to both intermediate and shadow contexts,
129	* however we don't need to do it for the intermediate one since we're
130	* executing with CR0.WP at that time.
131	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
132	* a page aligned one is required.
133	*
134	*
135	* @section sec_pgm_handlers Access Handlers
136	*
137	* Placeholder.
138	*
139	*
140	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
141	*
142	* Placeholder.
143	*
144	*
145	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
146	*
147	* We currently implement three types of virtual access handlers: ALL, WRITE
148	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
149	*
150	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
151	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
152	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
153	* rest of this section is going to be about these handlers.
154	*
155	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
156	* how successful this is gonna be...
157	*
158	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
159	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
160	* and create a new node that is inserted into the AVL tree (range key). Then
161	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
162	*
163	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
164	*
165	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
166	* via the current guest CR3 and update the physical page -> virtual handler
167	* translation. Needless to say, this doesn't exactly scale very well. If any changes
168	* are detected, it will flag a virtual bit update just like we did on registration.
169	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
170	*
171	* 2b. The virtual bit update process will iterate all the pages covered by all the
172	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
173	* virtual handlers on that page.
174	*
175	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
176	* we don't miss any alias mappings of the monitored pages.
177	*
178	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
179	*
180	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
181	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
182	* will call the handlers like in the next step. If the physical mapping has
183	* changed we will - some time in the future - perform a handler callback
184	* (optional) and update the physical -> virtual handler cache.
185	*
186	* 4. \#PF(,write) on a page in the range. This will cause the handler to
187	* be invoked.
188	*
189	* 5. The guest invalidates the page and changes the physical backing or
190	* unmaps it. This should cause the invalidation callback to be invoked
191	* (it might not yet be 100% perfect). Exactly what happens next... is
192	* this where we mess up and end up out of sync for a while?
193	*
194	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
195	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
196	* this handler to NONE and trigger a full PGM resync (basically the same
197	* as int step 1). Which means 2 is executed again.
198	*
199	*
200	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
201	*
202	* There is a bunch of things that needs to be done to make the virtual handlers
203	* work 100% correctly and work more efficiently.
204	*
205	* The first bit hasn't been implemented yet because it's going to slow the
206	* whole mess down even more, and besides it seems to be working reliably for
207	* our current uses. OTOH, some of the optimizations might end up more or less
208	* implementing the missing bits, so we'll see.
209	*
210	* On the optimization side, the first thing to do is to try avoid unnecessary
211	* cache flushing. Then try team up with the shadowing code to track changes
212	* in mappings by means of access to them (shadow in), updates to shadows pages,
213	* invlpg, and shadow PT discarding (perhaps).
214	*
215	* Some idea that have popped up for optimization for current and new features:
216	* - bitmap indicating where there are virtual handlers installed.
217	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
218	* - Further optimize this by min/max (needs min/max avl getters).
219	* - Shadow page table entry bit (if any left)?
220	*
221	*/
222
223
224	/** @page pg_pgm_phys PGM Physical Guest Memory Management
225	*
226	*
227	* Objectives:
228	* - Guest RAM over-commitment using memory ballooning,
229	* zero pages and general page sharing.
230	* - Moving or mirroring a VM onto a different physical machine.
231	*
232	*
233	* @subsection subsec_pgmPhys_Definitions Definitions
234	*
235	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
236	* machinery associated with it.
237	*
238	*
239	*
240	*
241	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
242	*
243	* Initially we map all guest memory to the (per VM) zero page, which
244	* means that none of the read functions will cause pages to be allocated.
245	*
246	* Exception, access bit in page tables that have been shared. This must
247	* be handled, but we must also make sure PGMGst*Modify doesn't make
248	* unnecessary modifications.
249	*
250	* Allocation points:
251	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
252	* - Replacing a zero page mapping at \#PF.
253	* - Replacing a shared page mapping at \#PF.
254	* - ROM registration (currently MMR3RomRegister).
255	* - VM restore (pgmR3Load).
256	*
257	* For the first three it would make sense to keep a few pages handy
258	* until we've reached the max memory commitment for the VM.
259	*
260	* For the ROM registration, we know exactly how many pages we need
261	* and will request these from ring-0. For restore, we will save
262	* the number of non-zero pages in the saved state and allocate
263	* them up front. This would allow the ring-0 component to refuse
264	* the request if the isn't sufficient memory available for VM use.
265	*
266	* Btw. for both ROM and restore allocations we won't be requiring
267	* zeroed pages as they are going to be filled instantly.
268	*
269	*
270	* @subsection subsec_pgmPhys_FreePage Freeing a page
271	*
272	* There are a few points where a page can be freed:
273	* - After being replaced by the zero page.
274	* - After being replaced by a shared page.
275	* - After being ballooned by the guest additions.
276	* - At reset.
277	* - At restore.
278	*
279	* When freeing one or more pages they will be returned to the ring-0
280	* component and replaced by the zero page.
281	*
282	* The reasoning for clearing out all the pages on reset is that it will
283	* return us to the exact same state as on power on, and may thereby help
284	* us reduce the memory load on the system. Further it might have a
285	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
286	*
287	* On restore, as mention under the allocation topic, pages should be
288	* freed / allocated depending on how many is actually required by the
289	* new VM state. The simplest approach is to do like on reset, and free
290	* all non-ROM pages and then allocate what we need.
291	*
292	* A measure to prevent some fragmentation, would be to let each allocation
293	* chunk have some affinity towards the VM having allocated the most pages
294	* from it. Also, try make sure to allocate from allocation chunks that
295	* are almost full. Admittedly, both these measures might work counter to
296	* our intentions and its probably not worth putting a lot of effort,
297	* cpu time or memory into this.
298	*
299	*
300	* @subsection subsec_pgmPhys_SharePage Sharing a page
301	*
302	* The basic idea is that there there will be a idle priority kernel
303	* thread walking the non-shared VM pages hashing them and looking for
304	* pages with the same checksum. If such pages are found, it will compare
305	* them byte-by-byte to see if they actually are identical. If found to be
306	* identical it will allocate a shared page, copy the content, check that
307	* the page didn't change while doing this, and finally request both the
308	* VMs to use the shared page instead. If the page is all zeros (special
309	* checksum and byte-by-byte check) it will request the VM that owns it
310	* to replace it with the zero page.
311	*
312	* To make this efficient, we will have to make sure not to try share a page
313	* that will change its contents soon. This part requires the most work.
314	* A simple idea would be to request the VM to write monitor the page for
315	* a while to make sure it isn't modified any time soon. Also, it may
316	* make sense to skip pages that are being write monitored since this
317	* information is readily available to the thread if it works on the
318	* per-VM guest memory structures (presently called PGMRAMRANGE).
319	*
320	*
321	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
322	*
323	* The pages are organized in allocation chunks in ring-0, this is a necessity
324	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
325	* could easily work on a page-by-page basis if we liked. Whether this is possible
326	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
327	* become a problem as part of the idea here is that we wish to return memory to
328	* the host system.
329	*
330	* For instance, starting two VMs at the same time, they will both allocate the
331	* guest memory on-demand and if permitted their page allocations will be
332	* intermixed. Shut down one of the two VMs and it will be difficult to return
333	* any memory to the host system because the page allocation for the two VMs are
334	* mixed up in the same allocation chunks.
335	*
336	* To further complicate matters, when pages are freed because they have been
337	* ballooned or become shared/zero the whole idea is that the page is supposed
338	* to be reused by another VM or returned to the host system. This will cause
339	* allocation chunks to contain pages belonging to different VMs and prevent
340	* returning memory to the host when one of those VM shuts down.
341	*
342	* The only way to really deal with this problem is to move pages. This can
343	* either be done at VM shutdown and or by the idle priority worker thread
344	* that will be responsible for finding sharable/zero pages. The mechanisms
345	* involved for coercing a VM to move a page (or to do it for it) will be
346	* the same as when telling it to share/zero a page.
347	*
348	*
349	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
350	*
351	* There's a difficult balance between keeping the per-page tracking structures
352	* (global and guest page) easy to use and keeping them from eating too much
353	* memory. We have limited virtual memory resources available when operating in
354	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
355	* tracking structures will be attempted designed such that we can deal with up
356	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
357	*
358	*
359	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
360	*
361	* @see pg_GMM
362	*
363	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
364	*
365	* Fixed info is the physical address of the page (HCPhys) and the page id
366	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
367	* Today we've restricting ourselves to 40(-12) bits because this is the current
368	* restrictions of all AMD64 implementations (I think Barcelona will up this
369	* to 48(-12) bits, not that it really matters) and I needed the bits for
370	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
371	* decent range for the page id: 2^(28+12) = 1024TB.
372	*
373	* In additions to these, we'll have to keep maintaining the page flags as we
374	* currently do. Although it wouldn't harm to optimize these quite a bit, like
375	* for instance the ROM shouldn't depend on having a write handler installed
376	* in order for it to become read-only. A RO/RW bit should be considered so
377	* that the page syncing code doesn't have to mess about checking multiple
378	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
379	* figure out how to setup a shadow PTE. But this of course, is second
380	* priority at present. Current this requires 12 bits, but could probably
381	* be optimized to ~8.
382	*
383	* Then there's the 24 bits used to track which shadow page tables are
384	* currently mapping a page for the purpose of speeding up physical
385	* access handlers, and thereby the page pool cache. More bit for this
386	* purpose wouldn't hurt IIRC.
387	*
388	* Then there is a new bit in which we need to record what kind of page
389	* this is, shared, zero, normal or write-monitored-normal. This'll
390	* require 2 bits. One bit might be needed for indicating whether a
391	* write monitored page has been written to. And yet another one or
392	* two for tracking migration status. 3-4 bits total then.
393	*
394	* Whatever is left will can be used to record the sharabilitiy of a
395	* page. The page checksum will not be stored in the per-VM table as
396	* the idle thread will not be permitted to do modifications to it.
397	* It will instead have to keep its own working set of potentially
398	* shareable pages and their check sums and stuff.
399	*
400	* For the present we'll keep the current packing of the
401	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
402	* we'll have to change it to a struct with a total of 128-bits at
403	* our disposal.
404	*
405	* The initial layout will be like this:
406	* @verbatim
407	RTHCPHYS HCPhys; The current stuff.
408	63:40 Current shadow PT tracking stuff.
409	39:12 The physical page frame number.
410	11:0 The current flags.
411	uint32_t u28PageId : 28; The page id.
412	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
413	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
414	uint32_t u1Reserved : 1; Reserved for later.
415	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
416	@endverbatim
417	*
418	* The final layout will be something like this:
419	* @verbatim
420	RTHCPHYS HCPhys; The current stuff.
421	63:48 High page id (12+).
422	47:12 The physical page frame number.
423	11:0 Low page id.
424	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
425	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
426	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
427	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
428	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
429	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
430	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
431	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
432	@endverbatim
433	*
434	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
435	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
436	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
437	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
438	*
439	* A couple of cost examples for the total cost per-VM + kernel.
440	* 32-bit Windows and 32-bit linux:
441	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
442	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
443	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
444	* 64-bit Windows and 64-bit linux:
445	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
446	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
447	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
448	*
449	* UPDATE - 2007-09-27:
450	* Will need a ballooned flag/state too because we cannot
451	* trust the guest 100% and reporting the same page as ballooned more
452	* than once will put the GMM off balance.
453	*
454	*
455	* @subsection subsec_pgmPhys_Serializing Serializing Access
456	*
457	* Initially, we'll try a simple scheme:
458	*
459	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
460	* by the EMT thread of that VM while in the pgm critsect.
461	* - Other threads in the VM process that needs to make reliable use of
462	* the per-VM RAM tracking structures will enter the critsect.
463	* - No process external thread or kernel thread will ever try enter
464	* the pgm critical section, as that just won't work.
465	* - The idle thread (and similar threads) doesn't not need 100% reliable
466	* data when performing it tasks as the EMT thread will be the one to
467	* do the actual changes later anyway. So, as long as it only accesses
468	* the main ram range, it can do so by somehow preventing the VM from
469	* being destroyed while it works on it...
470	*
471	* - The over-commitment management, including the allocating/freeing
472	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
473	* more mundane mutex implementation is broken on Linux).
474	* - A separate mutex is protecting the set of allocation chunks so
475	* that pages can be shared or/and freed up while some other VM is
476	* allocating more chunks. This mutex can be take from under the other
477	* one, but not the other way around.
478	*
479	*
480	* @subsection subsec_pgmPhys_Request VM Request interface
481	*
482	* When in ring-0 it will become necessary to send requests to a VM so it can
483	* for instance move a page while defragmenting during VM destroy. The idle
484	* thread will make use of this interface to request VMs to setup shared
485	* pages and to perform write monitoring of pages.
486	*
487	* I would propose an interface similar to the current VMReq interface, similar
488	* in that it doesn't require locking and that the one sending the request may
489	* wait for completion if it wishes to. This shouldn't be very difficult to
490	* realize.
491	*
492	* The requests themselves are also pretty simple. They are basically:
493	* -# Check that some precondition is still true.
494	* -# Do the update.
495	* -# Update all shadow page tables involved with the page.
496	*
497	* The 3rd step is identical to what we're already doing when updating a
498	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
499	*
500	*
501	*
502	* @section sec_pgmPhys_MappingCaches Mapping Caches
503	*
504	* In order to be able to map in and out memory and to be able to support
505	* guest with more RAM than we've got virtual address space, we'll employing
506	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
507	* however on 32-bit darwin the ring-0 code is running in a different memory
508	* context and therefore needs a separate cache. In raw-mode context we also
509	* need a separate cache. The 32-bit darwin mapping cache and the one for
510	* raw-mode context share a lot of code, see PGMRZDYNMAP.
511	*
512	*
513	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
514	*
515	* We've considered implementing the ring-3 mapping cache page based but found
516	* that this was bother some when one had to take into account TLBs+SMP and
517	* portability (missing the necessary APIs on several platforms). There were
518	* also some performance concerns with this approach which hadn't quite been
519	* worked out.
520	*
521	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
522	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
523	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
524	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
525	* costly than a single page, although how much more costly is uncertain. We'll
526	* try address this by using a very big cache, preferably bigger than the actual
527	* VM RAM size if possible. The current VM RAM sizes should give some idea for
528	* 32-bit boxes, while on 64-bit we can probably get away with employing an
529	* unlimited cache.
530	*
531	* The cache have to parts, as already indicated, the ring-3 side and the
532	* ring-0 side.
533	*
534	* The ring-0 will be tied to the page allocator since it will operate on the
535	* memory objects it contains. It will therefore require the first ring-0 mutex
536	* discussed in @ref subsec_pgmPhys_Serializing. We
537	* some double house keeping wrt to who has mapped what I think, since both
538	* VMMR0.r0 and RTR0MemObj will keep track of mapping relations
539	*
540	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
541	* require anyone that desires to do changes to the mapping cache to do that
542	* from within this critsect. Alternatively, we could employ a separate critsect
543	* for serializing changes to the mapping cache as this would reduce potential
544	* contention with other threads accessing mappings unrelated to the changes
545	* that are in process. We can see about this later, contention will show
546	* up in the statistics anyway, so it'll be simple to tell.
547	*
548	* The organization of the ring-3 part will be very much like how the allocation
549	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
550	* having to walk the tree all the time, we'll have a couple of lookaside entries
551	* like in we do for I/O ports and MMIO in IOM.
552	*
553	* The simplified flow of a PGMPhysRead/Write function:
554	* -# Enter the PGM critsect.
555	* -# Lookup GCPhys in the ram ranges and get the Page ID.
556	* -# Calc the Allocation Chunk ID from the Page ID.
557	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
558	* If not found in cache:
559	* -# Call ring-0 and request it to be mapped and supply
560	* a chunk to be unmapped if the cache is maxed out already.
561	* -# Insert the new mapping into the AVL tree (id + R3 address).
562	* -# Update the relevant lookaside entry and return the mapping address.
563	* -# Do the read/write according to monitoring flags and everything.
564	* -# Leave the critsect.
565	*
566	*
567	* @section sec_pgmPhys_Fallback Fallback
568	*
569	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
570	* API and thus require a fallback.
571	*
572	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
573	* will return to the ring-3 caller (and later ring-0) and asking it to seed
574	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
575	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
576	* "SeededAllocPages" call to ring-0.
577	*
578	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
579	* all page sharing (zero page detection will continue). It will also force
580	* all allocations to come from the VM which seeded the page. Both these
581	* measures are taken to make sure that there will never be any need for
582	* mapping anything into ring-3 - everything will be mapped already.
583	*
584	* Whether we'll continue to use the current MM locked memory management
585	* for this I don't quite know (I'd prefer not to and just ditch that all
586	* together), we'll see what's simplest to do.
587	*
588	*
589	*
590	* @section sec_pgmPhys_Changes Changes
591	*
592	* Breakdown of the changes involved?
593	*/
594
595	/*******************************************************************************
596	* Header Files *
597	*******************************************************************************/
598	#define LOG_GROUP LOG_GROUP_PGM
599	#include <VBox/vmm/dbgf.h>
600	#include <VBox/vmm/pgm.h>
601	#include <VBox/vmm/cpum.h>
602	#include <VBox/vmm/iom.h>
603	#include <VBox/sup.h>
604	#include <VBox/vmm/mm.h>
605	#include <VBox/vmm/em.h>
606	#include <VBox/vmm/stam.h>
607	#ifdef VBOX_WITH_REM
608	# include <VBox/vmm/rem.h>
609	#endif
610	#include <VBox/vmm/selm.h>
611	#include <VBox/vmm/ssm.h>
612	#include <VBox/vmm/hwaccm.h>
613	#include "PGMInternal.h"
614	#include <VBox/vmm/vm.h>
615	#include "PGMInline.h"
616
617	#include <VBox/dbg.h>
618	#include <VBox/param.h>
619	#include <VBox/err.h>
620
621	#include <iprt/asm.h>
622	#include <iprt/asm-amd64-x86.h>
623	#include <iprt/assert.h>
624	#include <iprt/env.h>
625	#include <iprt/mem.h>
626	#include <iprt/file.h>
627	#include <iprt/string.h>
628	#include <iprt/thread.h>
629
630
631	/*******************************************************************************
632	* Internal Functions *
633	*******************************************************************************/
634	static int pgmR3InitPaging(PVM pVM);
635	static int pgmR3InitStats(PVM pVM);
636	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
637	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
638	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
639	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
640	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
641	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
642	#ifdef VBOX_STRICT
643	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
644	#endif
645	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
646	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
647	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
648
649	#ifdef VBOX_WITH_DEBUGGER
650	/** @todo Convert the first two commands to 'info' items. */
651	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
652	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
653	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
654	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
655	# ifdef VBOX_STRICT
656	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
657	# endif
658	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
659	#endif
660
661
662	/*******************************************************************************
663	* Global Variables *
664	*******************************************************************************/
665	#ifdef VBOX_WITH_DEBUGGER
666	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
667	static const DBGCVARDESC g_aPgmErrorArgs[] =
668	{
669	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
670	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
671	};
672
673	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
674	{
675	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
676	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
677	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
678	};
679
680	# ifdef DEBUG_sandervl
681	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
682	{
683	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
684	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
685	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
686	};
687	# endif
688
689	/** Command descriptors. */
690	static const DBGCCMD g_aCmds[] =
691	{
692	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
693	{ "pgmram", 0, 0, NULL, 0, 0, pgmR3CmdRam, "", "Display the ram ranges." },
694	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
695	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
696	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
697	# ifdef VBOX_STRICT
698	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
699	# ifdef VBOX_WITH_PAGE_SHARING
700	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
701	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
702	# endif
703	# endif
704	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
705	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
706	};
707	#endif
708
709
710
711
712	/*
713	* Shadow - 32-bit mode
714	*/
715	#define PGM_SHW_TYPE PGM_TYPE_32BIT
716	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
717	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
718	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
719	#include "PGMShw.h"
720
721	/* Guest - real mode */
722	#define PGM_GST_TYPE PGM_TYPE_REAL
723	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
724	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
725	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
726	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
727	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
728	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
729	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
730	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
731	#include "PGMBth.h"
732	#include "PGMGstDefs.h"
733	#include "PGMGst.h"
734	#undef BTH_PGMPOOLKIND_PT_FOR_PT
735	#undef BTH_PGMPOOLKIND_ROOT
736	#undef PGM_BTH_NAME
737	#undef PGM_BTH_NAME_RC_STR
738	#undef PGM_BTH_NAME_R0_STR
739	#undef PGM_GST_TYPE
740	#undef PGM_GST_NAME
741	#undef PGM_GST_NAME_RC_STR
742	#undef PGM_GST_NAME_R0_STR
743
744	/* Guest - protected mode */
745	#define PGM_GST_TYPE PGM_TYPE_PROT
746	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
747	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
748	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
749	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
750	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
751	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
752	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
753	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
754	#include "PGMBth.h"
755	#include "PGMGstDefs.h"
756	#include "PGMGst.h"
757	#undef BTH_PGMPOOLKIND_PT_FOR_PT
758	#undef BTH_PGMPOOLKIND_ROOT
759	#undef PGM_BTH_NAME
760	#undef PGM_BTH_NAME_RC_STR
761	#undef PGM_BTH_NAME_R0_STR
762	#undef PGM_GST_TYPE
763	#undef PGM_GST_NAME
764	#undef PGM_GST_NAME_RC_STR
765	#undef PGM_GST_NAME_R0_STR
766
767	/* Guest - 32-bit mode */
768	#define PGM_GST_TYPE PGM_TYPE_32BIT
769	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
770	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
771	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
772	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
773	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
774	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
775	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
776	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
777	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
778	#include "PGMBth.h"
779	#include "PGMGstDefs.h"
780	#include "PGMGst.h"
781	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
782	#undef BTH_PGMPOOLKIND_PT_FOR_PT
783	#undef BTH_PGMPOOLKIND_ROOT
784	#undef PGM_BTH_NAME
785	#undef PGM_BTH_NAME_RC_STR
786	#undef PGM_BTH_NAME_R0_STR
787	#undef PGM_GST_TYPE
788	#undef PGM_GST_NAME
789	#undef PGM_GST_NAME_RC_STR
790	#undef PGM_GST_NAME_R0_STR
791
792	#undef PGM_SHW_TYPE
793	#undef PGM_SHW_NAME
794	#undef PGM_SHW_NAME_RC_STR
795	#undef PGM_SHW_NAME_R0_STR
796
797
798	/*
799	* Shadow - PAE mode
800	*/
801	#define PGM_SHW_TYPE PGM_TYPE_PAE
802	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
803	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
804	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
805	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
806	#include "PGMShw.h"
807
808	/* Guest - real mode */
809	#define PGM_GST_TYPE PGM_TYPE_REAL
810	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
811	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
812	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
813	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
814	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
815	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
816	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
817	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
818	#include "PGMGstDefs.h"
819	#include "PGMBth.h"
820	#undef BTH_PGMPOOLKIND_PT_FOR_PT
821	#undef BTH_PGMPOOLKIND_ROOT
822	#undef PGM_BTH_NAME
823	#undef PGM_BTH_NAME_RC_STR
824	#undef PGM_BTH_NAME_R0_STR
825	#undef PGM_GST_TYPE
826	#undef PGM_GST_NAME
827	#undef PGM_GST_NAME_RC_STR
828	#undef PGM_GST_NAME_R0_STR
829
830	/* Guest - protected mode */
831	#define PGM_GST_TYPE PGM_TYPE_PROT
832	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
833	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
834	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
835	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
836	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
837	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
838	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
839	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
840	#include "PGMGstDefs.h"
841	#include "PGMBth.h"
842	#undef BTH_PGMPOOLKIND_PT_FOR_PT
843	#undef BTH_PGMPOOLKIND_ROOT
844	#undef PGM_BTH_NAME
845	#undef PGM_BTH_NAME_RC_STR
846	#undef PGM_BTH_NAME_R0_STR
847	#undef PGM_GST_TYPE
848	#undef PGM_GST_NAME
849	#undef PGM_GST_NAME_RC_STR
850	#undef PGM_GST_NAME_R0_STR
851
852	/* Guest - 32-bit mode */
853	#define PGM_GST_TYPE PGM_TYPE_32BIT
854	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
855	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
856	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
857	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
858	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
859	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
860	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
861	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
862	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
863	#include "PGMGstDefs.h"
864	#include "PGMBth.h"
865	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
866	#undef BTH_PGMPOOLKIND_PT_FOR_PT
867	#undef BTH_PGMPOOLKIND_ROOT
868	#undef PGM_BTH_NAME
869	#undef PGM_BTH_NAME_RC_STR
870	#undef PGM_BTH_NAME_R0_STR
871	#undef PGM_GST_TYPE
872	#undef PGM_GST_NAME
873	#undef PGM_GST_NAME_RC_STR
874	#undef PGM_GST_NAME_R0_STR
875
876	/* Guest - PAE mode */
877	#define PGM_GST_TYPE PGM_TYPE_PAE
878	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
879	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
880	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
881	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
882	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
883	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
884	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
885	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
886	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
887	#include "PGMBth.h"
888	#include "PGMGstDefs.h"
889	#include "PGMGst.h"
890	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
891	#undef BTH_PGMPOOLKIND_PT_FOR_PT
892	#undef BTH_PGMPOOLKIND_ROOT
893	#undef PGM_BTH_NAME
894	#undef PGM_BTH_NAME_RC_STR
895	#undef PGM_BTH_NAME_R0_STR
896	#undef PGM_GST_TYPE
897	#undef PGM_GST_NAME
898	#undef PGM_GST_NAME_RC_STR
899	#undef PGM_GST_NAME_R0_STR
900
901	#undef PGM_SHW_TYPE
902	#undef PGM_SHW_NAME
903	#undef PGM_SHW_NAME_RC_STR
904	#undef PGM_SHW_NAME_R0_STR
905
906
907	/*
908	* Shadow - AMD64 mode
909	*/
910	#define PGM_SHW_TYPE PGM_TYPE_AMD64
911	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
912	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
913	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
914	#include "PGMShw.h"
915
916	#ifdef VBOX_WITH_64_BITS_GUESTS
917	/* Guest - AMD64 mode */
918	# define PGM_GST_TYPE PGM_TYPE_AMD64
919	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
920	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
921	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
922	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
923	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
924	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
925	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
926	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
927	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
928	# include "PGMBth.h"
929	# include "PGMGstDefs.h"
930	# include "PGMGst.h"
931	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
932	# undef BTH_PGMPOOLKIND_PT_FOR_PT
933	# undef BTH_PGMPOOLKIND_ROOT
934	# undef PGM_BTH_NAME
935	# undef PGM_BTH_NAME_RC_STR
936	# undef PGM_BTH_NAME_R0_STR
937	# undef PGM_GST_TYPE
938	# undef PGM_GST_NAME
939	# undef PGM_GST_NAME_RC_STR
940	# undef PGM_GST_NAME_R0_STR
941	#endif /* VBOX_WITH_64_BITS_GUESTS */
942
943	#undef PGM_SHW_TYPE
944	#undef PGM_SHW_NAME
945	#undef PGM_SHW_NAME_RC_STR
946	#undef PGM_SHW_NAME_R0_STR
947
948
949	/*
950	* Shadow - Nested paging mode
951	*/
952	#define PGM_SHW_TYPE PGM_TYPE_NESTED
953	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
954	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
955	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
956	#include "PGMShw.h"
957
958	/* Guest - real mode */
959	#define PGM_GST_TYPE PGM_TYPE_REAL
960	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
961	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
962	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
963	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
964	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
965	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
966	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
967	#include "PGMGstDefs.h"
968	#include "PGMBth.h"
969	#undef BTH_PGMPOOLKIND_PT_FOR_PT
970	#undef PGM_BTH_NAME
971	#undef PGM_BTH_NAME_RC_STR
972	#undef PGM_BTH_NAME_R0_STR
973	#undef PGM_GST_TYPE
974	#undef PGM_GST_NAME
975	#undef PGM_GST_NAME_RC_STR
976	#undef PGM_GST_NAME_R0_STR
977
978	/* Guest - protected mode */
979	#define PGM_GST_TYPE PGM_TYPE_PROT
980	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
981	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
982	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
983	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
984	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
985	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
986	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
987	#include "PGMGstDefs.h"
988	#include "PGMBth.h"
989	#undef BTH_PGMPOOLKIND_PT_FOR_PT
990	#undef PGM_BTH_NAME
991	#undef PGM_BTH_NAME_RC_STR
992	#undef PGM_BTH_NAME_R0_STR
993	#undef PGM_GST_TYPE
994	#undef PGM_GST_NAME
995	#undef PGM_GST_NAME_RC_STR
996	#undef PGM_GST_NAME_R0_STR
997
998	/* Guest - 32-bit mode */
999	#define PGM_GST_TYPE PGM_TYPE_32BIT
1000	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1001	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1002	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1003	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
1004	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
1005	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
1006	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1007	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1008	#include "PGMGstDefs.h"
1009	#include "PGMBth.h"
1010	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1011	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1012	#undef PGM_BTH_NAME
1013	#undef PGM_BTH_NAME_RC_STR
1014	#undef PGM_BTH_NAME_R0_STR
1015	#undef PGM_GST_TYPE
1016	#undef PGM_GST_NAME
1017	#undef PGM_GST_NAME_RC_STR
1018	#undef PGM_GST_NAME_R0_STR
1019
1020	/* Guest - PAE mode */
1021	#define PGM_GST_TYPE PGM_TYPE_PAE
1022	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1023	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1024	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1025	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1026	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1027	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1028	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1029	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1030	#include "PGMGstDefs.h"
1031	#include "PGMBth.h"
1032	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1033	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1034	#undef PGM_BTH_NAME
1035	#undef PGM_BTH_NAME_RC_STR
1036	#undef PGM_BTH_NAME_R0_STR
1037	#undef PGM_GST_TYPE
1038	#undef PGM_GST_NAME
1039	#undef PGM_GST_NAME_RC_STR
1040	#undef PGM_GST_NAME_R0_STR
1041
1042	#ifdef VBOX_WITH_64_BITS_GUESTS
1043	/* Guest - AMD64 mode */
1044	# define PGM_GST_TYPE PGM_TYPE_AMD64
1045	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1046	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1047	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1048	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1049	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1050	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1051	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1052	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1053	# include "PGMGstDefs.h"
1054	# include "PGMBth.h"
1055	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1056	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1057	# undef PGM_BTH_NAME
1058	# undef PGM_BTH_NAME_RC_STR
1059	# undef PGM_BTH_NAME_R0_STR
1060	# undef PGM_GST_TYPE
1061	# undef PGM_GST_NAME
1062	# undef PGM_GST_NAME_RC_STR
1063	# undef PGM_GST_NAME_R0_STR
1064	#endif /* VBOX_WITH_64_BITS_GUESTS */
1065
1066	#undef PGM_SHW_TYPE
1067	#undef PGM_SHW_NAME
1068	#undef PGM_SHW_NAME_RC_STR
1069	#undef PGM_SHW_NAME_R0_STR
1070
1071
1072	/*
1073	* Shadow - EPT
1074	*/
1075	#define PGM_SHW_TYPE PGM_TYPE_EPT
1076	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1077	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1078	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1079	#include "PGMShw.h"
1080
1081	/* Guest - real mode */
1082	#define PGM_GST_TYPE PGM_TYPE_REAL
1083	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1084	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1085	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1086	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1087	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1088	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1089	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1090	#include "PGMGstDefs.h"
1091	#include "PGMBth.h"
1092	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1093	#undef PGM_BTH_NAME
1094	#undef PGM_BTH_NAME_RC_STR
1095	#undef PGM_BTH_NAME_R0_STR
1096	#undef PGM_GST_TYPE
1097	#undef PGM_GST_NAME
1098	#undef PGM_GST_NAME_RC_STR
1099	#undef PGM_GST_NAME_R0_STR
1100
1101	/* Guest - protected mode */
1102	#define PGM_GST_TYPE PGM_TYPE_PROT
1103	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1104	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1105	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1106	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1107	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1108	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1109	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1110	#include "PGMGstDefs.h"
1111	#include "PGMBth.h"
1112	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1113	#undef PGM_BTH_NAME
1114	#undef PGM_BTH_NAME_RC_STR
1115	#undef PGM_BTH_NAME_R0_STR
1116	#undef PGM_GST_TYPE
1117	#undef PGM_GST_NAME
1118	#undef PGM_GST_NAME_RC_STR
1119	#undef PGM_GST_NAME_R0_STR
1120
1121	/* Guest - 32-bit mode */
1122	#define PGM_GST_TYPE PGM_TYPE_32BIT
1123	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1124	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1125	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1126	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1127	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1128	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1129	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1130	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1131	#include "PGMGstDefs.h"
1132	#include "PGMBth.h"
1133	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1134	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1135	#undef PGM_BTH_NAME
1136	#undef PGM_BTH_NAME_RC_STR
1137	#undef PGM_BTH_NAME_R0_STR
1138	#undef PGM_GST_TYPE
1139	#undef PGM_GST_NAME
1140	#undef PGM_GST_NAME_RC_STR
1141	#undef PGM_GST_NAME_R0_STR
1142
1143	/* Guest - PAE mode */
1144	#define PGM_GST_TYPE PGM_TYPE_PAE
1145	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1146	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1147	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1148	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1149	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1150	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1151	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1152	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1153	#include "PGMGstDefs.h"
1154	#include "PGMBth.h"
1155	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1156	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1157	#undef PGM_BTH_NAME
1158	#undef PGM_BTH_NAME_RC_STR
1159	#undef PGM_BTH_NAME_R0_STR
1160	#undef PGM_GST_TYPE
1161	#undef PGM_GST_NAME
1162	#undef PGM_GST_NAME_RC_STR
1163	#undef PGM_GST_NAME_R0_STR
1164
1165	#ifdef VBOX_WITH_64_BITS_GUESTS
1166	/* Guest - AMD64 mode */
1167	# define PGM_GST_TYPE PGM_TYPE_AMD64
1168	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1169	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1170	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1171	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1172	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1173	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1174	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1175	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1176	# include "PGMGstDefs.h"
1177	# include "PGMBth.h"
1178	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1179	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1180	# undef PGM_BTH_NAME
1181	# undef PGM_BTH_NAME_RC_STR
1182	# undef PGM_BTH_NAME_R0_STR
1183	# undef PGM_GST_TYPE
1184	# undef PGM_GST_NAME
1185	# undef PGM_GST_NAME_RC_STR
1186	# undef PGM_GST_NAME_R0_STR
1187	#endif /* VBOX_WITH_64_BITS_GUESTS */
1188
1189	#undef PGM_SHW_TYPE
1190	#undef PGM_SHW_NAME
1191	#undef PGM_SHW_NAME_RC_STR
1192	#undef PGM_SHW_NAME_R0_STR
1193
1194
1195
1196	/**
1197	* Initiates the paging of VM.
1198	*
1199	* @returns VBox status code.
1200	* @param pVM Pointer to VM structure.
1201	*/
1202	VMMR3DECL(int) PGMR3Init(PVM pVM)
1203	{
1204	LogFlow(("PGMR3Init:\n"));
1205	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1206	int rc;
1207
1208	/*
1209	* Assert alignment and sizes.
1210	*/
1211	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1212	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1213	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1214
1215	/*
1216	* Init the structure.
1217	*/
1218	#ifdef PGM_WITHOUT_MAPPINGS
1219	pVM->pgm.s.fMappingsDisabled = true;
1220	#endif
1221	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1222	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1223
1224	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1225	{
1226	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1227	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1228	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1229	}
1230
1231	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1232	{
1233	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1234	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1235	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1236	}
1237
1238	/* Init the per-CPU part. */
1239	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1240	{
1241	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1242	PPGMCPU pPGM = &pVCpu->pgm.s;
1243
1244	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1245	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1246	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1247
1248	pPGM->enmShadowMode = PGMMODE_INVALID;
1249	pPGM->enmGuestMode = PGMMODE_INVALID;
1250
1251	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1252
1253	pPGM->pGst32BitPdR3 = NULL;
1254	pPGM->pGstPaePdptR3 = NULL;
1255	pPGM->pGstAmd64Pml4R3 = NULL;
1256	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1257	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1258	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1259	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1260	#endif
1261	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1262	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1263	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1264	{
1265	pPGM->apGstPaePDsR3[i] = NULL;
1266	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1267	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1268	#endif
1269	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1270	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1271	pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1272	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1273	}
1274
1275	pPGM->fA20Enabled = true;
1276	pPGM->GCPhysA20Mask = ~(RTGCPHYS)(!pPGM->fA20Enabled << 20);
1277	}
1278
1279	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1280	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1281	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1282
1283	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1284	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1285	true
1286	#else
1287	false
1288	#endif
1289	);
1290	AssertLogRelRCReturn(rc, rc);
1291
1292	#if HC_ARCH_BITS == 32
1293	# ifdef RT_OS_DARWIN
1294	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1295	# else
1296	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1297	# endif
1298	#else
1299	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1300	#endif
1301	AssertLogRelRCReturn(rc, rc);
1302	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1303	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1304
1305	/*
1306	* Get the configured RAM size - to estimate saved state size.
1307	*/
1308	uint64_t cbRam;
1309	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1310	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1311	cbRam = 0;
1312	else if (RT_SUCCESS(rc))
1313	{
1314	if (cbRam < PAGE_SIZE)
1315	cbRam = 0;
1316	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1317	}
1318	else
1319	{
1320	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1321	return rc;
1322	}
1323
1324	/*
1325	* Check for PCI pass-through.
1326	*/
1327	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1328	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1329	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1330
1331	#ifdef VBOX_WITH_STATISTICS
1332	/*
1333	* Allocate memory for the statistics before someone tries to use them.
1334	*/
1335	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1336	void *pv;
1337	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1338	AssertRCReturn(rc, rc);
1339
1340	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1341	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1342	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1343	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1344
1345	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1346	{
1347	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1348	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1349	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1350
1351	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1352	}
1353	#endif /* VBOX_WITH_STATISTICS */
1354
1355	/*
1356	* Register callbacks, string formatters and the saved state data unit.
1357	*/
1358	#ifdef VBOX_STRICT
1359	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1360	#endif
1361	PGMRegisterStringFormatTypes();
1362
1363	rc = pgmR3InitSavedState(pVM, cbRam);
1364	if (RT_FAILURE(rc))
1365	return rc;
1366
1367	/*
1368	* Initialize the PGM critical section and flush the phys TLBs
1369	*/
1370	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1371	AssertRCReturn(rc, rc);
1372
1373	PGMR3PhysChunkInvalidateTLB(pVM);
1374	pgmPhysInvalidatePageMapTLB(pVM);
1375
1376	/*
1377	* For the time being we sport a full set of handy pages in addition to the base
1378	* memory to simplify things.
1379	*/
1380	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1381	AssertRCReturn(rc, rc);
1382
1383	/*
1384	* Trees
1385	*/
1386	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1387	if (RT_SUCCESS(rc))
1388	{
1389	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1390	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1391
1392	/*
1393	* Allocate the zero page.
1394	*/
1395	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1396	}
1397	if (RT_SUCCESS(rc))
1398	{
1399	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1400	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1401	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1402	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1403
1404	/*
1405	* Allocate the invalid MMIO page.
1406	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1407	*/
1408	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1409	}
1410	if (RT_SUCCESS(rc))
1411	{
1412	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1413	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1414	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1415	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1416
1417	/*
1418	* Init the paging.
1419	*/
1420	rc = pgmR3InitPaging(pVM);
1421	}
1422	if (RT_SUCCESS(rc))
1423	{
1424	/*
1425	* Init the page pool.
1426	*/
1427	rc = pgmR3PoolInit(pVM);
1428	}
1429	if (RT_SUCCESS(rc))
1430	{
1431	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1432	{
1433	PVMCPU pVCpu = &pVM->aCpus[i];
1434	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1435	if (RT_FAILURE(rc))
1436	break;
1437	}
1438	}
1439
1440	if (RT_SUCCESS(rc))
1441	{
1442	/*
1443	* Info & statistics
1444	*/
1445	DBGFR3InfoRegisterInternal(pVM, "mode",
1446	"Shows the current paging mode. "
1447	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1448	pgmR3InfoMode);
1449	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1450	"Dumps all the entries in the top level paging table. No arguments.",
1451	pgmR3InfoCr3);
1452	DBGFR3InfoRegisterInternal(pVM, "phys",
1453	"Dumps all the physical address ranges. No arguments.",
1454	pgmR3PhysInfo);
1455	DBGFR3InfoRegisterInternal(pVM, "handlers",
1456	"Dumps physical, virtual and hyper virtual handlers. "
1457	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1458	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1459	pgmR3InfoHandlers);
1460	DBGFR3InfoRegisterInternal(pVM, "mappings",
1461	"Dumps guest mappings.",
1462	pgmR3MapInfo);
1463
1464	pgmR3InitStats(pVM);
1465
1466	#ifdef VBOX_WITH_DEBUGGER
1467	/*
1468	* Debugger commands.
1469	*/
1470	static bool s_fRegisteredCmds = false;
1471	if (!s_fRegisteredCmds)
1472	{
1473	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1474	if (RT_SUCCESS(rc2))
1475	s_fRegisteredCmds = true;
1476	}
1477	#endif
1478	return VINF_SUCCESS;
1479	}
1480
1481	/* Almost no cleanup necessary, MM frees all memory. */
1482	PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1483
1484	return rc;
1485	}
1486
1487
1488	/**
1489	* Init paging.
1490	*
1491	* Since we need to check what mode the host is operating in before we can choose
1492	* the right paging functions for the host we have to delay this until R0 has
1493	* been initialized.
1494	*
1495	* @returns VBox status code.
1496	* @param pVM VM handle.
1497	*/
1498	static int pgmR3InitPaging(PVM pVM)
1499	{
1500	/*
1501	* Force a recalculation of modes and switcher so everyone gets notified.
1502	*/
1503	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1504	{
1505	PVMCPU pVCpu = &pVM->aCpus[i];
1506
1507	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1508	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1509	}
1510
1511	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1512
1513	/*
1514	* Allocate static mapping space for whatever the cr3 register
1515	* points to and in the case of PAE mode to the 4 PDs.
1516	*/
1517	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1518	if (RT_FAILURE(rc))
1519	{
1520	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1521	return rc;
1522	}
1523	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1524
1525	/*
1526	* Allocate pages for the three possible intermediate contexts
1527	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1528	* for the sake of simplicity. The AMD64 uses the PAE for the
1529	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1530	*
1531	* We assume that two page tables will be enought for the core code
1532	* mappings (HC virtual and identity).
1533	*/
1534	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1535	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1536	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1537	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1538	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1539	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1540	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1541	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1542	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1543	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1544	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1545	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1546
1547	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1548	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1549	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1550	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1551	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1552	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1553
1554	/*
1555	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1556	*/
1557	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1558	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1559	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1560
1561	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1562	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1563
1564	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1565	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1566	{
1567	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1568	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1569	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1570	}
1571
1572	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1573	{
1574	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1575	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1576	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1577	}
1578
1579	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1580	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1581	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1582	\| HCPhysInterPaePDPT64;
1583
1584	/*
1585	* Initialize paging workers and mode from current host mode
1586	* and the guest running in real mode.
1587	*/
1588	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1589	switch (pVM->pgm.s.enmHostMode)
1590	{
1591	case SUPPAGINGMODE_32_BIT:
1592	case SUPPAGINGMODE_32_BIT_GLOBAL:
1593	case SUPPAGINGMODE_PAE:
1594	case SUPPAGINGMODE_PAE_GLOBAL:
1595	case SUPPAGINGMODE_PAE_NX:
1596	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1597	break;
1598
1599	case SUPPAGINGMODE_AMD64:
1600	case SUPPAGINGMODE_AMD64_GLOBAL:
1601	case SUPPAGINGMODE_AMD64_NX:
1602	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1603	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1604	if (ARCH_BITS != 64)
1605	{
1606	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1607	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1608	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1609	}
1610	#endif
1611	break;
1612	default:
1613	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1614	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1615	}
1616	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1617	if (RT_SUCCESS(rc))
1618	{
1619	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1620	#if HC_ARCH_BITS == 64
1621	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1622	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1623	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1624	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1625	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1626	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1627	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1628	#endif
1629
1630	/*
1631	* Log the host paging mode. It may come in handy.
1632	*/
1633	const char *pszHostMode;
1634	switch (pVM->pgm.s.enmHostMode)
1635	{
1636	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1637	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1638	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1639	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1640	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1641	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1642	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1643	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1644	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1645	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1646	default: pszHostMode = "???"; break;
1647	}
1648	LogRel(("Host paging mode: %s\n", pszHostMode));
1649
1650	return VINF_SUCCESS;
1651	}
1652
1653	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1654	return rc;
1655	}
1656
1657
1658	/**
1659	* Init statistics
1660	* @returns VBox status code.
1661	*/
1662	static int pgmR3InitStats(PVM pVM)
1663	{
1664	PPGM pPGM = &pVM->pgm.s;
1665	int rc;
1666
1667	/*
1668	* Release statistics.
1669	*/
1670	/* Common - misc variables */
1671	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1672	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1673	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1674	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1675	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1676	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1677	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1678	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1679	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1680	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1681	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1682	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1683	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1684	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1685	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1686	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1687	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1688	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1689	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1690
1691	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1692	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1693	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1694
1695	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1696
1697	/* Live save */
1698	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1699	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1700	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1701	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1702	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1703	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1704	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1705	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1706	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1707	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1708	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1709	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1710	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1711	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1712	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1713	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1714	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1715	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1716
1717	#ifdef VBOX_WITH_STATISTICS
1718
1719	# define PGM_REG_COUNTER(a, b, c) \
1720	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1721	AssertRC(rc);
1722
1723	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1724	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1725	AssertRC(rc);
1726
1727	# define PGM_REG_PROFILE(a, b, c) \
1728	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1729	AssertRC(rc);
1730
1731	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1732
1733	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1734	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1735	PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1736	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1737	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1738
1739	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1740	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1741	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1742	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1743	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1744	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1745	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1746	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1747	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1748	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1749
1750	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1751	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1752	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1753	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1754	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1755	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1756
1757	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1758	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1759	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1760	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1761	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1762	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1763	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1764	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1765
1766	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1767	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1768	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1769	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1770
1771	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1772	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1773	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1774	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1775
1776	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1777	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1778	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1779	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1780	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1781	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1782	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1783	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1784
1785	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1786	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1787	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1788	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1789	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1790	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1791
1792	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1793	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1794	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1795	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1796	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1797	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1798	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1799	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1800
1801	/* GC only: */
1802	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1803	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1804
1805	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1806	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1807	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1808	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1809	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1810	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1811	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1812	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1813
1814	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1815	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1816	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1817	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1818	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1819	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1820	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1821
1822	# undef PGM_REG_COUNTER
1823	# undef PGM_REG_PROFILE
1824	#endif
1825
1826	/*
1827	* Note! The layout below matches the member layout exactly!
1828	*/
1829
1830	/*
1831	* Common - stats
1832	*/
1833	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1834	{
1835	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1836
1837	#define PGM_REG_COUNTER(a, b, c) \
1838	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1839	AssertRC(rc);
1840	#define PGM_REG_PROFILE(a, b, c) \
1841	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1842	AssertRC(rc);
1843
1844	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1845	PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1846
1847	#ifdef VBOX_WITH_STATISTICS
1848	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1849
1850	# if 0 /* rarely useful; leave for debugging. */
1851	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1852	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1853	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1854	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1855	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1856	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1857	# endif
1858	/* R0 only: */
1859	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1860	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1861
1862	/* RZ only: */
1863	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1864	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1865	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1866	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1867	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1868	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1869	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1870	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1871	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1872	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1873	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1874	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1875	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1876	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1877	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1878	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1879	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1880	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1881	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1882	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1883	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1884	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1885	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1886	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1887	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1888	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1889	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1890	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1891	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1892	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1893	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1894	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1895	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1896	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1897	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1898	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1899	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1900	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1901	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1902	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1903	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1904	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1905	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1906	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1907	#if 0 /* rarely useful; leave for debugging. */
1908	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1909	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1910	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1911	#endif
1912	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1913	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1914	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1915	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1916	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1917
1918	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1919	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1920	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1921	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1922	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1923	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1924	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1925	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1926	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1927	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1928	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1929	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1930	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1931	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1932	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1933	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1934	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1935	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1936	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1937	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1938	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1939	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1940	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1941	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1942	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1943	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1944	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1945	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1946	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1947	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1948	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1949	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1950	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1951	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1952	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1953	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1954
1955	/* HC only: */
1956
1957	/* RZ & R3: */
1958	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1959	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1960	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1961	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1962	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1963	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1964	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1965	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1966	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1967	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1968	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1969	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1970	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1971	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1972	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1973	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1974	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1975	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1976	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1977	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1978	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1979	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1980	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1981	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1982	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1983	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1984	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1985	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1986	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1987	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1988	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1989	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1990	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1991	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1992	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1993	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1994	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1995	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1996	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1997	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1998	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1999	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2000	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2001	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2002	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2003	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2004	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2005
2006	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2007	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2008	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
2009	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2010	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2011	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2012	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2013	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2014	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2015	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2016	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
2017	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2018	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
2019	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
2020	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2021	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2022	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2023	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2024	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2025	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2026	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2027	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2028	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2029	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2030	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2031	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2032	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2033	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2034	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2035	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2036	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2037	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2038	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2039	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2040	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2041	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2042	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2043	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2044	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2045	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2046	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2047	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2048	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2049	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2050	#endif /* VBOX_WITH_STATISTICS */
2051
2052	#undef PGM_REG_PROFILE
2053	#undef PGM_REG_COUNTER
2054
2055	}
2056
2057	return VINF_SUCCESS;
2058	}
2059
2060
2061	/**
2062	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2063	*
2064	* The dynamic mapping area will also be allocated and initialized at this
2065	* time. We could allocate it during PGMR3Init of course, but the mapping
2066	* wouldn't be allocated at that time preventing us from setting up the
2067	* page table entries with the dummy page.
2068	*
2069	* @returns VBox status code.
2070	* @param pVM VM handle.
2071	*/
2072	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2073	{
2074	RTGCPTR GCPtr;
2075	int rc;
2076
2077	/*
2078	* Reserve space for the dynamic mappings.
2079	*/
2080	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2081	if (RT_SUCCESS(rc))
2082	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2083
2084	if ( RT_SUCCESS(rc)
2085	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2086	{
2087	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2088	if (RT_SUCCESS(rc))
2089	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2090	}
2091	if (RT_SUCCESS(rc))
2092	{
2093	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2094	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2095	}
2096	return rc;
2097	}
2098
2099
2100	/**
2101	* Ring-3 init finalizing.
2102	*
2103	* @returns VBox status code.
2104	* @param pVM The VM handle.
2105	*/
2106	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2107	{
2108	int rc;
2109
2110	/*
2111	* Reserve space for the dynamic mappings.
2112	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2113	*/
2114	/* get the pointer to the page table entries. */
2115	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2116	AssertRelease(pMapping);
2117	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2118	const unsigned iPT = off >> X86_PD_SHIFT;
2119	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2120	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2121	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2122
2123	/* init cache area */
2124	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2125	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2126	{
2127	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2128	AssertRCReturn(rc, rc);
2129	}
2130
2131	/*
2132	* Determine the max physical address width (MAXPHYADDR) and apply it to
2133	* all the mask members and stuff.
2134	*/
2135	uint32_t cMaxPhysAddrWidth;
2136	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2137	if ( uMaxExtLeaf >= 0x80000008
2138	&& uMaxExtLeaf <= 0x80000fff)
2139	{
2140	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2141	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2142	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2143	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2144	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2145	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2146	}
2147	else
2148	{
2149	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2150	cMaxPhysAddrWidth = 48;
2151	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2152	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2153	}
2154
2155	pVM->pgm.s.GCPhysInvAddrMask = 0;
2156	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2157	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2158
2159	/*
2160	* Initialize the invalid paging entry masks, assuming NX is disabled.
2161	*/
2162	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2163	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2164	{
2165	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2166
2167	/** @todo The manuals are not entirely clear whether the physical
2168	* address width is relevant. See table 5-9 in the intel
2169	* manual vs the PDE4M descriptions. Write testcase (NP). */
2170	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2171	\| X86_PDE4M_MBZ_MASK;
2172
2173	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2174	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2175	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2176	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2177
2178	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2179	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2180	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2181	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2182	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2183	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2184
2185	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
2186	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
2187	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
2188	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2189	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
2190	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
2191	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
2192	}
2193
2194	/*
2195	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2196	* Intel only goes up to 36 bits, so we stick to 36 as well.
2197	* Update: More recent intel manuals specifies 40 bits just like AMD.
2198	*/
2199	uint32_t u32Dummy, u32Features;
2200	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2201	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2202	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2203	else
2204	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2205
2206	/*
2207	* Allocate memory if we're supposed to do that.
2208	*/
2209	if (pVM->pgm.s.fRamPreAlloc)
2210	rc = pgmR3PhysRamPreAllocate(pVM);
2211
2212	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2213	return rc;
2214	}
2215
2216
2217	/**
2218	* Init phase completed callback.
2219	*
2220	* @returns VBox status code.
2221	* @param pVM The VM handle.
2222	* @param enmWhat What has been completed.
2223	* @thread EMT(0)
2224	*/
2225	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2226	{
2227	switch (enmWhat)
2228	{
2229	case VMINITCOMPLETED_HWACCM:
2230	#ifdef VBOX_WITH_PCI_PASSTHROUGH
2231	if (pVM->pgm.s.fPciPassthrough)
2232	{
2233	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2234	AssertLogRelReturn(HWACCMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HWACCM);
2235	AssertLogRelReturn(HWACCMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2236
2237	/*
2238	* Report assignments to the IOMMU (hope that's good enough for now).
2239	*/
2240	if (pVM->pgm.s.fPciPassthrough)
2241	{
2242	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2243	AssertRCReturn(rc, rc);
2244	}
2245	}
2246	#else
2247	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2248	#endif
2249	break;
2250
2251	default:
2252	/* shut up gcc */
2253	break;
2254	}
2255
2256	return VINF_SUCCESS;
2257	}
2258
2259
2260	/**
2261	* Applies relocations to data and code managed by this component.
2262	*
2263	* This function will be called at init and whenever the VMM need to relocate it
2264	* self inside the GC.
2265	*
2266	* @param pVM The VM.
2267	* @param offDelta Relocation delta relative to old location.
2268	*/
2269	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2270	{
2271	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2272
2273	/*
2274	* Paging stuff.
2275	*/
2276	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2277
2278	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2279
2280	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2281	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2282	{
2283	PVMCPU pVCpu = &pVM->aCpus[i];
2284
2285	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2286
2287	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2288	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2289	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2290	}
2291
2292	/*
2293	* Trees.
2294	*/
2295	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2296
2297	/*
2298	* Ram ranges.
2299	*/
2300	if (pVM->pgm.s.pRamRangesXR3)
2301	{
2302	/* Update the pSelfRC pointers and relink them. */
2303	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2304	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2305	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2306	pgmR3PhysRelinkRamRanges(pVM);
2307
2308	/* Flush the RC TLB. */
2309	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2310	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2311	}
2312
2313	/*
2314	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2315	* be mapped and thus not included in the above exercise.
2316	*/
2317	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2318	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2319	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2320
2321	/*
2322	* Update the two page directories with all page table mappings.
2323	* (One or more of them have changed, that's why we're here.)
2324	*/
2325	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2326	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2327	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2328
2329	/* Relocate GC addresses of Page Tables. */
2330	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2331	{
2332	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2333	{
2334	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2335	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2336	}
2337	}
2338
2339	/*
2340	* Dynamic page mapping area.
2341	*/
2342	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2343	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2344	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2345
2346	if (pVM->pgm.s.pRCDynMap)
2347	{
2348	pVM->pgm.s.pRCDynMap += offDelta;
2349	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2350
2351	pDynMap->paPages += offDelta;
2352	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2353
2354	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2355	{
2356	paPages[iPage].pvPage += offDelta;
2357	paPages[iPage].uPte.pLegacy += offDelta;
2358	paPages[iPage].uPte.pPae += offDelta;
2359	}
2360	}
2361
2362	/*
2363	* The Zero page.
2364	*/
2365	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2366	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2367	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2368	#else
2369	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2370	#endif
2371
2372	/*
2373	* Physical and virtual handlers.
2374	*/
2375	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2376	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2377	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2378	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2379
2380	/*
2381	* The page pool.
2382	*/
2383	pgmR3PoolRelocate(pVM);
2384
2385	#ifdef VBOX_WITH_STATISTICS
2386	/*
2387	* Statistics.
2388	*/
2389	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2390	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2391	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2392	#endif
2393	}
2394
2395
2396	/**
2397	* Callback function for relocating a physical access handler.
2398	*
2399	* @returns 0 (continue enum)
2400	* @param pNode Pointer to a PGMPHYSHANDLER node.
2401	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2402	* not certain the delta will fit in a void pointer for all possible configs.
2403	*/
2404	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2405	{
2406	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2407	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2408	if (pHandler->pfnHandlerRC)
2409	pHandler->pfnHandlerRC += offDelta;
2410	if (pHandler->pvUserRC >= 0x10000)
2411	pHandler->pvUserRC += offDelta;
2412	return 0;
2413	}
2414
2415
2416	/**
2417	* Callback function for relocating a virtual access handler.
2418	*
2419	* @returns 0 (continue enum)
2420	* @param pNode Pointer to a PGMVIRTHANDLER node.
2421	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2422	* not certain the delta will fit in a void pointer for all possible configs.
2423	*/
2424	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2425	{
2426	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2427	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2428	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2429	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2430	Assert(pHandler->pfnHandlerRC);
2431	pHandler->pfnHandlerRC += offDelta;
2432	return 0;
2433	}
2434
2435
2436	/**
2437	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2438	*
2439	* @returns 0 (continue enum)
2440	* @param pNode Pointer to a PGMVIRTHANDLER node.
2441	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2442	* not certain the delta will fit in a void pointer for all possible configs.
2443	*/
2444	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2445	{
2446	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2447	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2448	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2449	Assert(pHandler->pfnHandlerRC);
2450	pHandler->pfnHandlerRC += offDelta;
2451	return 0;
2452	}
2453
2454
2455	/**
2456	* Resets a virtual CPU when unplugged.
2457	*
2458	* @param pVM The VM handle.
2459	* @param pVCpu The virtual CPU handle.
2460	*/
2461	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2462	{
2463	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2464	AssertRC(rc);
2465
2466	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2467	AssertRC(rc);
2468
2469	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2470
2471	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2472
2473	/*
2474	* Re-init other members.
2475	*/
2476	pVCpu->pgm.s.fA20Enabled = true;
2477
2478	/*
2479	* Clear the FFs PGM owns.
2480	*/
2481	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2482	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2483	}
2484
2485
2486	/**
2487	* The VM is being reset.
2488	*
2489	* For the PGM component this means that any PD write monitors
2490	* needs to be removed.
2491	*
2492	* @param pVM VM handle.
2493	*/
2494	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2495	{
2496	int rc;
2497
2498	LogFlow(("PGMR3Reset:\n"));
2499	VM_ASSERT_EMT(pVM);
2500
2501	pgmLock(pVM);
2502
2503	/*
2504	* Unfix any fixed mappings and disable CR3 monitoring.
2505	*/
2506	pVM->pgm.s.fMappingsFixed = false;
2507	pVM->pgm.s.fMappingsFixedRestored = false;
2508	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2509	pVM->pgm.s.cbMappingFixed = 0;
2510
2511	/*
2512	* Exit the guest paging mode before the pgm pool gets reset.
2513	* Important to clean up the amd64 case.
2514	*/
2515	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2516	{
2517	PVMCPU pVCpu = &pVM->aCpus[i];
2518	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2519	AssertRC(rc);
2520	}
2521
2522	#ifdef DEBUG
2523	DBGFR3InfoLog(pVM, "mappings", NULL);
2524	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2525	#endif
2526
2527	/*
2528	* Switch mode back to real mode. (before resetting the pgm pool!)
2529	*/
2530	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2531	{
2532	PVMCPU pVCpu = &pVM->aCpus[i];
2533
2534	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2535	AssertRC(rc);
2536
2537	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2538	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2539	}
2540
2541	/*
2542	* Reset the shadow page pool.
2543	*/
2544	pgmR3PoolReset(pVM);
2545
2546	/*
2547	* Re-init various other members and clear the FFs that PGM owns.
2548	*/
2549	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2550	{
2551	PVMCPU pVCpu = &pVM->aCpus[i];
2552
2553	pVCpu->pgm.s.fA20Enabled = true;
2554	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2555	PGMNotifyNxeChanged(pVCpu, false);
2556
2557	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2558	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2559	}
2560
2561	/*
2562	* Reset (zero) RAM and shadow ROM pages.
2563	*/
2564	rc = pgmR3PhysRamReset(pVM);
2565	if (RT_SUCCESS(rc))
2566	rc = pgmR3PhysRomReset(pVM);
2567
2568
2569	pgmUnlock(pVM);
2570	AssertReleaseRC(rc);
2571	}
2572
2573
2574	#ifdef VBOX_STRICT
2575	/**
2576	* VM state change callback for clearing fNoMorePhysWrites after
2577	* a snapshot has been created.
2578	*/
2579	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2580	{
2581	if ( enmState == VMSTATE_RUNNING
2582	\|\| enmState == VMSTATE_RESUMING)
2583	pVM->pgm.s.fNoMorePhysWrites = false;
2584	NOREF(enmOldState); NOREF(pvUser);
2585	}
2586	#endif
2587
2588	/**
2589	* Private API to reset fNoMorePhysWrites.
2590	*/
2591	VMMR3DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2592	{
2593	pVM->pgm.s.fNoMorePhysWrites = false;
2594	}
2595
2596	/**
2597	* Terminates the PGM.
2598	*
2599	* @returns VBox status code.
2600	* @param pVM Pointer to VM structure.
2601	*/
2602	VMMR3DECL(int) PGMR3Term(PVM pVM)
2603	{
2604	/* Must free shared pages here. */
2605	pgmLock(pVM);
2606	pgmR3PhysRamTerm(pVM);
2607	pgmR3PhysRomTerm(pVM);
2608	pgmUnlock(pVM);
2609
2610	PGMDeregisterStringFormatTypes();
2611	return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2612	}
2613
2614
2615	/**
2616	* Show paging mode.
2617	*
2618	* @param pVM VM Handle.
2619	* @param pHlp The info helpers.
2620	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2621	*/
2622	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2623	{
2624	/* digest argument. */
2625	bool fGuest, fShadow, fHost;
2626	if (pszArgs)
2627	pszArgs = RTStrStripL(pszArgs);
2628	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2629	fShadow = fHost = fGuest = true;
2630	else
2631	{
2632	fShadow = fHost = fGuest = false;
2633	if (strstr(pszArgs, "guest"))
2634	fGuest = true;
2635	if (strstr(pszArgs, "shadow"))
2636	fShadow = true;
2637	if (strstr(pszArgs, "host"))
2638	fHost = true;
2639	}
2640
2641	/** @todo SMP support! */
2642	/* print info. */
2643	if (fGuest)
2644	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2645	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2646	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled", pVM->aCpus[0].pgm.s.cA20Changes.c);
2647	if (fShadow)
2648	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2649	if (fHost)
2650	{
2651	const char *psz;
2652	switch (pVM->pgm.s.enmHostMode)
2653	{
2654	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2655	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2656	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2657	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2658	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2659	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2660	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2661	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2662	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2663	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2664	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2665	default: psz = "unknown"; break;
2666	}
2667	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2668	}
2669	}
2670
2671
2672	/**
2673	* Dump registered MMIO ranges to the log.
2674	*
2675	* @param pVM VM Handle.
2676	* @param pHlp The info helpers.
2677	* @param pszArgs Arguments, ignored.
2678	*/
2679	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2680	{
2681	NOREF(pszArgs);
2682	pHlp->pfnPrintf(pHlp,
2683	"RAM ranges (pVM=%p)\n"
2684	"%.s %.s\n",
2685	pVM,
2686	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2687	sizeof(RTHCPTR) * 2, "pvHC ");
2688
2689	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2690	pHlp->pfnPrintf(pHlp,
2691	"%RGp-%RGp %RHv %s\n",
2692	pCur->GCPhys,
2693	pCur->GCPhysLast,
2694	pCur->pvR3,
2695	pCur->pszDesc);
2696	}
2697
2698	/**
2699	* Dump the page directory to the log.
2700	*
2701	* @param pVM VM Handle.
2702	* @param pHlp The info helpers.
2703	* @param pszArgs Arguments, ignored.
2704	*/
2705	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2706	{
2707	/** @todo SMP support!! */
2708	PVMCPU pVCpu = &pVM->aCpus[0];
2709
2710	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2711	/* Big pages supported? */
2712	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2713
2714	/* Global pages supported? */
2715	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2716
2717	NOREF(pszArgs);
2718
2719	/*
2720	* Get page directory addresses.
2721	*/
2722	pgmLock(pVM);
2723	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2724	Assert(pPDSrc);
2725
2726	/*
2727	* Iterate the page directory.
2728	*/
2729	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2730	{
2731	X86PDE PdeSrc = pPDSrc->a[iPD];
2732	if (PdeSrc.n.u1Present)
2733	{
2734	if (PdeSrc.b.u1Size && fPSE)
2735	pHlp->pfnPrintf(pHlp,
2736	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2737	iPD,
2738	pgmGstGet4MBPhysPage(pVM, PdeSrc),
2739	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2740	else
2741	pHlp->pfnPrintf(pHlp,
2742	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2743	iPD,
2744	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2745	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2746	}
2747	}
2748	pgmUnlock(pVM);
2749	}
2750
2751
2752	/**
2753	* Service a VMMCALLRING3_PGM_LOCK call.
2754	*
2755	* @returns VBox status code.
2756	* @param pVM The VM handle.
2757	*/
2758	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2759	{
2760	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2761	AssertRC(rc);
2762	return rc;
2763	}
2764
2765
2766	/**
2767	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2768	*
2769	* @returns PGM_TYPE_*.
2770	* @param pgmMode The mode value to convert.
2771	*/
2772	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2773	{
2774	switch (pgmMode)
2775	{
2776	case PGMMODE_REAL: return PGM_TYPE_REAL;
2777	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2778	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2779	case PGMMODE_PAE:
2780	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2781	case PGMMODE_AMD64:
2782	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2783	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2784	case PGMMODE_EPT: return PGM_TYPE_EPT;
2785	default:
2786	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2787	}
2788	}
2789
2790
2791	/**
2792	* Gets the index into the paging mode data array of a SHW+GST mode.
2793	*
2794	* @returns PGM::paPagingData index.
2795	* @param uShwType The shadow paging mode type.
2796	* @param uGstType The guest paging mode type.
2797	*/
2798	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2799	{
2800	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2801	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2802	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2803	+ (uGstType - PGM_TYPE_REAL);
2804	}
2805
2806
2807	/**
2808	* Gets the index into the paging mode data array of a SHW+GST mode.
2809	*
2810	* @returns PGM::paPagingData index.
2811	* @param enmShw The shadow paging mode.
2812	* @param enmGst The guest paging mode.
2813	*/
2814	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2815	{
2816	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2817	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2818	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2819	}
2820
2821
2822	/**
2823	* Calculates the max data index.
2824	* @returns The number of entries in the paging data array.
2825	*/
2826	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2827	{
2828	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2829	}
2830
2831
2832	/**
2833	* Initializes the paging mode data kept in PGM::paModeData.
2834	*
2835	* @param pVM The VM handle.
2836	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2837	* This is used early in the init process to avoid trouble with PDM
2838	* not being initialized yet.
2839	*/
2840	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2841	{
2842	PPGMMODEDATA pModeData;
2843	int rc;
2844
2845	/*
2846	* Allocate the array on the first call.
2847	*/
2848	if (!pVM->pgm.s.paModeData)
2849	{
2850	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2851	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2852	}
2853
2854	/*
2855	* Initialize the array entries.
2856	*/
2857	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2858	pModeData->uShwType = PGM_TYPE_32BIT;
2859	pModeData->uGstType = PGM_TYPE_REAL;
2860	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2861	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2862	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2863
2864	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2865	pModeData->uShwType = PGM_TYPE_32BIT;
2866	pModeData->uGstType = PGM_TYPE_PROT;
2867	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2868	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2869	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2870
2871	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2872	pModeData->uShwType = PGM_TYPE_32BIT;
2873	pModeData->uGstType = PGM_TYPE_32BIT;
2874	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2875	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2876	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2877
2878	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2879	pModeData->uShwType = PGM_TYPE_PAE;
2880	pModeData->uGstType = PGM_TYPE_REAL;
2881	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2882	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2883	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2884
2885	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2886	pModeData->uShwType = PGM_TYPE_PAE;
2887	pModeData->uGstType = PGM_TYPE_PROT;
2888	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2889	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2890	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2891
2892	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2893	pModeData->uShwType = PGM_TYPE_PAE;
2894	pModeData->uGstType = PGM_TYPE_32BIT;
2895	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2897	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2898
2899	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2900	pModeData->uShwType = PGM_TYPE_PAE;
2901	pModeData->uGstType = PGM_TYPE_PAE;
2902	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2904	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2905
2906	#ifdef VBOX_WITH_64_BITS_GUESTS
2907	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2908	pModeData->uShwType = PGM_TYPE_AMD64;
2909	pModeData->uGstType = PGM_TYPE_AMD64;
2910	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2911	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2912	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2913	#endif
2914
2915	/* The nested paging mode. */
2916	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2917	pModeData->uShwType = PGM_TYPE_NESTED;
2918	pModeData->uGstType = PGM_TYPE_REAL;
2919	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2920	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2921
2922	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2923	pModeData->uShwType = PGM_TYPE_NESTED;
2924	pModeData->uGstType = PGM_TYPE_PROT;
2925	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2926	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2927
2928	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2929	pModeData->uShwType = PGM_TYPE_NESTED;
2930	pModeData->uGstType = PGM_TYPE_32BIT;
2931	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2932	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2933
2934	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2935	pModeData->uShwType = PGM_TYPE_NESTED;
2936	pModeData->uGstType = PGM_TYPE_PAE;
2937	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2938	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2939
2940	#ifdef VBOX_WITH_64_BITS_GUESTS
2941	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2942	pModeData->uShwType = PGM_TYPE_NESTED;
2943	pModeData->uGstType = PGM_TYPE_AMD64;
2944	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2945	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2946	#endif
2947
2948	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2949	switch (pVM->pgm.s.enmHostMode)
2950	{
2951	#if HC_ARCH_BITS == 32
2952	case SUPPAGINGMODE_32_BIT:
2953	case SUPPAGINGMODE_32_BIT_GLOBAL:
2954	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2955	{
2956	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2957	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2958	}
2959	# ifdef VBOX_WITH_64_BITS_GUESTS
2960	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2961	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2962	# endif
2963	break;
2964
2965	case SUPPAGINGMODE_PAE:
2966	case SUPPAGINGMODE_PAE_NX:
2967	case SUPPAGINGMODE_PAE_GLOBAL:
2968	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2969	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2970	{
2971	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2972	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2973	}
2974	# ifdef VBOX_WITH_64_BITS_GUESTS
2975	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2976	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2977	# endif
2978	break;
2979	#endif /* HC_ARCH_BITS == 32 */
2980
2981	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2982	case SUPPAGINGMODE_AMD64:
2983	case SUPPAGINGMODE_AMD64_GLOBAL:
2984	case SUPPAGINGMODE_AMD64_NX:
2985	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2986	# ifdef VBOX_WITH_64_BITS_GUESTS
2987	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2988	# else
2989	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2990	# endif
2991	{
2992	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2993	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2994	}
2995	break;
2996	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2997
2998	default:
2999	AssertFailed();
3000	break;
3001	}
3002
3003	/* Extended paging (EPT) / Intel VT-x */
3004	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3005	pModeData->uShwType = PGM_TYPE_EPT;
3006	pModeData->uGstType = PGM_TYPE_REAL;
3007	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3008	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3009	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3010
3011	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3012	pModeData->uShwType = PGM_TYPE_EPT;
3013	pModeData->uGstType = PGM_TYPE_PROT;
3014	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3015	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3016	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3017
3018	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3019	pModeData->uShwType = PGM_TYPE_EPT;
3020	pModeData->uGstType = PGM_TYPE_32BIT;
3021	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3022	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3023	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3024
3025	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3026	pModeData->uShwType = PGM_TYPE_EPT;
3027	pModeData->uGstType = PGM_TYPE_PAE;
3028	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3029	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3030	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3031
3032	#ifdef VBOX_WITH_64_BITS_GUESTS
3033	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3034	pModeData->uShwType = PGM_TYPE_EPT;
3035	pModeData->uGstType = PGM_TYPE_AMD64;
3036	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3037	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3038	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3039	#endif
3040	return VINF_SUCCESS;
3041	}
3042
3043
3044	/**
3045	* Switch to different (or relocated in the relocate case) mode data.
3046	*
3047	* @param pVM The VM handle.
3048	* @param pVCpu The VMCPU to operate on.
3049	* @param enmShw The the shadow paging mode.
3050	* @param enmGst The the guest paging mode.
3051	*/
3052	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3053	{
3054	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3055
3056	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3057	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3058
3059	/* shadow */
3060	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3061	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3062	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3063	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3064	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3065
3066	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3067	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3068
3069	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3070	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3071
3072
3073	/* guest */
3074	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3075	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3076	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3077	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3078	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3079	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3080	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3081	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3082	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3083	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3084	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3085	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3086
3087	/* both */
3088	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3089	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3090	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3091	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3092	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3093	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3094	#ifdef VBOX_STRICT
3095	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3096	#endif
3097	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3098	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3099
3100	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3101	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3102	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3103	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3104	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3105	#ifdef VBOX_STRICT
3106	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3107	#endif
3108	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3109	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3110
3111	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3112	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3113	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3114	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3115	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3116	#ifdef VBOX_STRICT
3117	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3118	#endif
3119	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3120	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3121	}
3122
3123
3124	/**
3125	* Calculates the shadow paging mode.
3126	*
3127	* @returns The shadow paging mode.
3128	* @param pVM VM handle.
3129	* @param enmGuestMode The guest mode.
3130	* @param enmHostMode The host mode.
3131	* @param enmShadowMode The current shadow mode.
3132	* @param penmSwitcher Where to store the switcher to use.
3133	* VMMSWITCHER_INVALID means no change.
3134	*/
3135	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3136	{
3137	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3138	switch (enmGuestMode)
3139	{
3140	/*
3141	* When switching to real or protected mode we don't change
3142	* anything since it's likely that we'll switch back pretty soon.
3143	*
3144	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3145	* and is supposed to determine which shadow paging and switcher to
3146	* use during init.
3147	*/
3148	case PGMMODE_REAL:
3149	case PGMMODE_PROTECTED:
3150	if ( enmShadowMode != PGMMODE_INVALID
3151	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3152	break; /* (no change) */
3153
3154	switch (enmHostMode)
3155	{
3156	case SUPPAGINGMODE_32_BIT:
3157	case SUPPAGINGMODE_32_BIT_GLOBAL:
3158	enmShadowMode = PGMMODE_32_BIT;
3159	enmSwitcher = VMMSWITCHER_32_TO_32;
3160	break;
3161
3162	case SUPPAGINGMODE_PAE:
3163	case SUPPAGINGMODE_PAE_NX:
3164	case SUPPAGINGMODE_PAE_GLOBAL:
3165	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3166	enmShadowMode = PGMMODE_PAE;
3167	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3168	#ifdef DEBUG_bird
3169	if (RTEnvExist("VBOX_32BIT"))
3170	{
3171	enmShadowMode = PGMMODE_32_BIT;
3172	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3173	}
3174	#endif
3175	break;
3176
3177	case SUPPAGINGMODE_AMD64:
3178	case SUPPAGINGMODE_AMD64_GLOBAL:
3179	case SUPPAGINGMODE_AMD64_NX:
3180	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3181	enmShadowMode = PGMMODE_PAE;
3182	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3183	#ifdef DEBUG_bird
3184	if (RTEnvExist("VBOX_32BIT"))
3185	{
3186	enmShadowMode = PGMMODE_32_BIT;
3187	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3188	}
3189	#endif
3190	break;
3191
3192	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3193	}
3194	break;
3195
3196	case PGMMODE_32_BIT:
3197	switch (enmHostMode)
3198	{
3199	case SUPPAGINGMODE_32_BIT:
3200	case SUPPAGINGMODE_32_BIT_GLOBAL:
3201	enmShadowMode = PGMMODE_32_BIT;
3202	enmSwitcher = VMMSWITCHER_32_TO_32;
3203	break;
3204
3205	case SUPPAGINGMODE_PAE:
3206	case SUPPAGINGMODE_PAE_NX:
3207	case SUPPAGINGMODE_PAE_GLOBAL:
3208	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3209	enmShadowMode = PGMMODE_PAE;
3210	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3211	#ifdef DEBUG_bird
3212	if (RTEnvExist("VBOX_32BIT"))
3213	{
3214	enmShadowMode = PGMMODE_32_BIT;
3215	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3216	}
3217	#endif
3218	break;
3219
3220	case SUPPAGINGMODE_AMD64:
3221	case SUPPAGINGMODE_AMD64_GLOBAL:
3222	case SUPPAGINGMODE_AMD64_NX:
3223	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3224	enmShadowMode = PGMMODE_PAE;
3225	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3226	#ifdef DEBUG_bird
3227	if (RTEnvExist("VBOX_32BIT"))
3228	{
3229	enmShadowMode = PGMMODE_32_BIT;
3230	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3231	}
3232	#endif
3233	break;
3234
3235	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3236	}
3237	break;
3238
3239	case PGMMODE_PAE:
3240	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3241	switch (enmHostMode)
3242	{
3243	case SUPPAGINGMODE_32_BIT:
3244	case SUPPAGINGMODE_32_BIT_GLOBAL:
3245	enmShadowMode = PGMMODE_PAE;
3246	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3247	break;
3248
3249	case SUPPAGINGMODE_PAE:
3250	case SUPPAGINGMODE_PAE_NX:
3251	case SUPPAGINGMODE_PAE_GLOBAL:
3252	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3253	enmShadowMode = PGMMODE_PAE;
3254	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3255	break;
3256
3257	case SUPPAGINGMODE_AMD64:
3258	case SUPPAGINGMODE_AMD64_GLOBAL:
3259	case SUPPAGINGMODE_AMD64_NX:
3260	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3261	enmShadowMode = PGMMODE_PAE;
3262	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3263	break;
3264
3265	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3266	}
3267	break;
3268
3269	case PGMMODE_AMD64:
3270	case PGMMODE_AMD64_NX:
3271	switch (enmHostMode)
3272	{
3273	case SUPPAGINGMODE_32_BIT:
3274	case SUPPAGINGMODE_32_BIT_GLOBAL:
3275	enmShadowMode = PGMMODE_AMD64;
3276	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3277	break;
3278
3279	case SUPPAGINGMODE_PAE:
3280	case SUPPAGINGMODE_PAE_NX:
3281	case SUPPAGINGMODE_PAE_GLOBAL:
3282	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3283	enmShadowMode = PGMMODE_AMD64;
3284	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3285	break;
3286
3287	case SUPPAGINGMODE_AMD64:
3288	case SUPPAGINGMODE_AMD64_GLOBAL:
3289	case SUPPAGINGMODE_AMD64_NX:
3290	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3291	enmShadowMode = PGMMODE_AMD64;
3292	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3293	break;
3294
3295	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3296	}
3297	break;
3298
3299
3300	default:
3301	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3302	*penmSwitcher = VMMSWITCHER_INVALID;
3303	return PGMMODE_INVALID;
3304	}
3305	/* Override the shadow mode is nested paging is active. */
3306	pVM->pgm.s.fNestedPaging = HWACCMIsNestedPagingActive(pVM);
3307	if (pVM->pgm.s.fNestedPaging)
3308	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3309
3310	*penmSwitcher = enmSwitcher;
3311	return enmShadowMode;
3312	}
3313
3314
3315	/**
3316	* Performs the actual mode change.
3317	* This is called by PGMChangeMode and pgmR3InitPaging().
3318	*
3319	* @returns VBox status code. May suspend or power off the VM on error, but this
3320	* will trigger using FFs and not status codes.
3321	*
3322	* @param pVM VM handle.
3323	* @param pVCpu The VMCPU to operate on.
3324	* @param enmGuestMode The new guest mode. This is assumed to be different from
3325	* the current mode.
3326	*/
3327	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3328	{
3329	#if HC_ARCH_BITS == 32
3330	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3331	#endif
3332	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3333
3334	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3335	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3336
3337	/*
3338	* Calc the shadow mode and switcher.
3339	*/
3340	VMMSWITCHER enmSwitcher;
3341	PGMMODE enmShadowMode;
3342	enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3343
3344	#ifdef VBOX_WITH_RAW_MODE
3345	if (enmSwitcher != VMMSWITCHER_INVALID)
3346	{
3347	/*
3348	* Select new switcher.
3349	*/
3350	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3351	if (RT_FAILURE(rc))
3352	{
3353	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3354	return rc;
3355	}
3356	}
3357	#endif
3358
3359	/*
3360	* Exit old mode(s).
3361	*/
3362	#if HC_ARCH_BITS == 32
3363	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3364	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3365	&& enmShadowMode == PGMMODE_NESTED);
3366	#else
3367	const bool fForceShwEnterExit = false;
3368	#endif
3369	/* shadow */
3370	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3371	\|\| fForceShwEnterExit)
3372	{
3373	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3374	if (PGM_SHW_PFN(Exit, pVCpu))
3375	{
3376	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3377	if (RT_FAILURE(rc))
3378	{
3379	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3380	return rc;
3381	}
3382	}
3383
3384	}
3385	else
3386	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3387
3388	/* guest */
3389	if (PGM_GST_PFN(Exit, pVCpu))
3390	{
3391	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3392	if (RT_FAILURE(rc))
3393	{
3394	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3395	return rc;
3396	}
3397	}
3398
3399	/*
3400	* Load new paging mode data.
3401	*/
3402	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3403
3404	/*
3405	* Enter new shadow mode (if changed).
3406	*/
3407	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3408	\|\| fForceShwEnterExit)
3409	{
3410	int rc;
3411	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3412	switch (enmShadowMode)
3413	{
3414	case PGMMODE_32_BIT:
3415	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3416	break;
3417	case PGMMODE_PAE:
3418	case PGMMODE_PAE_NX:
3419	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3420	break;
3421	case PGMMODE_AMD64:
3422	case PGMMODE_AMD64_NX:
3423	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3424	break;
3425	case PGMMODE_NESTED:
3426	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3427	break;
3428	case PGMMODE_EPT:
3429	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3430	break;
3431	case PGMMODE_REAL:
3432	case PGMMODE_PROTECTED:
3433	default:
3434	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3435	return VERR_INTERNAL_ERROR;
3436	}
3437	if (RT_FAILURE(rc))
3438	{
3439	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3440	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3441	return rc;
3442	}
3443	}
3444
3445	/*
3446	* Always flag the necessary updates
3447	*/
3448	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3449
3450	/*
3451	* Enter the new guest and shadow+guest modes.
3452	*/
3453	int rc = -1;
3454	int rc2 = -1;
3455	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3456	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3457	switch (enmGuestMode)
3458	{
3459	case PGMMODE_REAL:
3460	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3461	switch (pVCpu->pgm.s.enmShadowMode)
3462	{
3463	case PGMMODE_32_BIT:
3464	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3465	break;
3466	case PGMMODE_PAE:
3467	case PGMMODE_PAE_NX:
3468	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3469	break;
3470	case PGMMODE_NESTED:
3471	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3472	break;
3473	case PGMMODE_EPT:
3474	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3475	break;
3476	case PGMMODE_AMD64:
3477	case PGMMODE_AMD64_NX:
3478	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3479	default: AssertFailed(); break;
3480	}
3481	break;
3482
3483	case PGMMODE_PROTECTED:
3484	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3485	switch (pVCpu->pgm.s.enmShadowMode)
3486	{
3487	case PGMMODE_32_BIT:
3488	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3489	break;
3490	case PGMMODE_PAE:
3491	case PGMMODE_PAE_NX:
3492	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3493	break;
3494	case PGMMODE_NESTED:
3495	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3496	break;
3497	case PGMMODE_EPT:
3498	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3499	break;
3500	case PGMMODE_AMD64:
3501	case PGMMODE_AMD64_NX:
3502	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3503	default: AssertFailed(); break;
3504	}
3505	break;
3506
3507	case PGMMODE_32_BIT:
3508	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3509	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3510	switch (pVCpu->pgm.s.enmShadowMode)
3511	{
3512	case PGMMODE_32_BIT:
3513	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3514	break;
3515	case PGMMODE_PAE:
3516	case PGMMODE_PAE_NX:
3517	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3518	break;
3519	case PGMMODE_NESTED:
3520	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3521	break;
3522	case PGMMODE_EPT:
3523	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3524	break;
3525	case PGMMODE_AMD64:
3526	case PGMMODE_AMD64_NX:
3527	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3528	default: AssertFailed(); break;
3529	}
3530	break;
3531
3532	case PGMMODE_PAE_NX:
3533	case PGMMODE_PAE:
3534	{
3535	uint32_t u32Dummy, u32Features;
3536
3537	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3538	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3539	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3540	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3541
3542	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3543	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3544	switch (pVCpu->pgm.s.enmShadowMode)
3545	{
3546	case PGMMODE_PAE:
3547	case PGMMODE_PAE_NX:
3548	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3549	break;
3550	case PGMMODE_NESTED:
3551	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3552	break;
3553	case PGMMODE_EPT:
3554	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3555	break;
3556	case PGMMODE_32_BIT:
3557	case PGMMODE_AMD64:
3558	case PGMMODE_AMD64_NX:
3559	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3560	default: AssertFailed(); break;
3561	}
3562	break;
3563	}
3564
3565	#ifdef VBOX_WITH_64_BITS_GUESTS
3566	case PGMMODE_AMD64_NX:
3567	case PGMMODE_AMD64:
3568	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3569	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3570	switch (pVCpu->pgm.s.enmShadowMode)
3571	{
3572	case PGMMODE_AMD64:
3573	case PGMMODE_AMD64_NX:
3574	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3575	break;
3576	case PGMMODE_NESTED:
3577	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3578	break;
3579	case PGMMODE_EPT:
3580	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3581	break;
3582	case PGMMODE_32_BIT:
3583	case PGMMODE_PAE:
3584	case PGMMODE_PAE_NX:
3585	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3586	default: AssertFailed(); break;
3587	}
3588	break;
3589	#endif
3590
3591	default:
3592	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3593	rc = VERR_NOT_IMPLEMENTED;
3594	break;
3595	}
3596
3597	/* status codes. */
3598	AssertRC(rc);
3599	AssertRC(rc2);
3600	if (RT_SUCCESS(rc))
3601	{
3602	rc = rc2;
3603	if (RT_SUCCESS(rc)) /* no informational status codes. */
3604	rc = VINF_SUCCESS;
3605	}
3606
3607	/* Notify HWACCM as well. */
3608	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3609	return rc;
3610	}
3611
3612
3613	/**
3614	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3615	*
3616	* @returns VBox status code, fully asserted.
3617	* @param pVCpu The VMCPU to operate on.
3618	*/
3619	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3620	{
3621	/* Unmap the old CR3 value before flushing everything. */
3622	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3623	AssertRC(rc);
3624
3625	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3626	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3627	AssertRC(rc);
3628	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3629	return rc;
3630	}
3631
3632
3633	/**
3634	* Called by pgmPoolFlushAllInt after flushing the pool.
3635	*
3636	* @returns VBox status code, fully asserted.
3637	* @param pVM The VM handle.
3638	* @param pVCpu The VMCPU to operate on.
3639	*/
3640	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3641	{
3642	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3643	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3644	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3645	AssertRCReturn(rc, rc);
3646	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3647
3648	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3649	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3650	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3651	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3652	return rc;
3653	}
3654
3655
3656	/**
3657	* Called by PGMR3PhysSetA20 after changing the A20 state.
3658	*
3659	* @param pVCpu The VMCPU to operate on.
3660	*/
3661	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
3662	{
3663	/** @todo Probably doing a bit too much here. */
3664	int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
3665	AssertReleaseRC(rc);
3666	rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
3667	AssertReleaseRC(rc);
3668	}
3669
3670
3671	#ifdef VBOX_WITH_DEBUGGER
3672
3673	/**
3674	* The '.pgmram' command.
3675	*
3676	* @returns VBox status.
3677	* @param pCmd Pointer to the command descriptor (as registered).
3678	* @param pCmdHlp Pointer to command helper functions.
3679	* @param pVM Pointer to the current VM (if any).
3680	* @param paArgs Pointer to (readonly) array of arguments.
3681	* @param cArgs Number of arguments in the array.
3682	*/
3683	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3684	{
3685	/*
3686	* Validate input.
3687	*/
3688	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3689	if (!pVM)
3690	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3691	if (!pVM->pgm.s.pRamRangesXR3)
3692	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3693
3694	/*
3695	* Dump the ranges.
3696	*/
3697	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3698	PPGMRAMRANGE pRam;
3699	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
3700	{
3701	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3702	"%RGp - %RGp %p\n",
3703	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
3704	if (RT_FAILURE(rc))
3705	return rc;
3706	}
3707
3708	return VINF_SUCCESS;
3709	}
3710
3711
3712	/**
3713	* The '.pgmerror' and '.pgmerroroff' commands.
3714	*
3715	* @returns VBox status.
3716	* @param pCmd Pointer to the command descriptor (as registered).
3717	* @param pCmdHlp Pointer to command helper functions.
3718	* @param pVM Pointer to the current VM (if any).
3719	* @param paArgs Pointer to (readonly) array of arguments.
3720	* @param cArgs Number of arguments in the array.
3721	*/
3722	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3723	{
3724	/*
3725	* Validate input.
3726	*/
3727	if (!pVM)
3728	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3729	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
3730	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
3731
3732	if (!cArgs)
3733	{
3734	/*
3735	* Print the list of error injection locations with status.
3736	*/
3737	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
3738	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3739	}
3740	else
3741	{
3742
3743	/*
3744	* String switch on where to inject the error.
3745	*/
3746	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
3747	const char *pszWhere = paArgs[0].u.pszString;
3748	if (!strcmp(pszWhere, "handy"))
3749	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
3750	else
3751	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
3752	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
3753	}
3754	return VINF_SUCCESS;
3755	}
3756
3757
3758	/**
3759	* The '.pgmsync' command.
3760	*
3761	* @returns VBox status.
3762	* @param pCmd Pointer to the command descriptor (as registered).
3763	* @param pCmdHlp Pointer to command helper functions.
3764	* @param pVM Pointer to the current VM (if any).
3765	* @param paArgs Pointer to (readonly) array of arguments.
3766	* @param cArgs Number of arguments in the array.
3767	*/
3768	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3769	{
3770	/** @todo SMP support */
3771
3772	/*
3773	* Validate input.
3774	*/
3775	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3776	if (!pVM)
3777	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3778
3779	PVMCPU pVCpu = &pVM->aCpus[0];
3780
3781	/*
3782	* Force page directory sync.
3783	*/
3784	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3785
3786	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3787	if (RT_FAILURE(rc))
3788	return rc;
3789
3790	return VINF_SUCCESS;
3791	}
3792
3793
3794	#ifdef VBOX_STRICT
3795	/**
3796	* The '.pgmassertcr3' command.
3797	*
3798	* @returns VBox status.
3799	* @param pCmd Pointer to the command descriptor (as registered).
3800	* @param pCmdHlp Pointer to command helper functions.
3801	* @param pVM Pointer to the current VM (if any).
3802	* @param paArgs Pointer to (readonly) array of arguments.
3803	* @param cArgs Number of arguments in the array.
3804	*/
3805	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3806	{
3807	/** @todo SMP support!! */
3808
3809	/*
3810	* Validate input.
3811	*/
3812	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3813	if (!pVM)
3814	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3815
3816	PVMCPU pVCpu = &pVM->aCpus[0];
3817
3818	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
3819	if (RT_FAILURE(rc))
3820	return rc;
3821
3822	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
3823
3824	return VINF_SUCCESS;
3825	}
3826	#endif /* VBOX_STRICT */
3827
3828
3829	/**
3830	* The '.pgmsyncalways' command.
3831	*
3832	* @returns VBox status.
3833	* @param pCmd Pointer to the command descriptor (as registered).
3834	* @param pCmdHlp Pointer to command helper functions.
3835	* @param pVM Pointer to the current VM (if any).
3836	* @param paArgs Pointer to (readonly) array of arguments.
3837	* @param cArgs Number of arguments in the array.
3838	*/
3839	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3840	{
3841	/** @todo SMP support!! */
3842	PVMCPU pVCpu = &pVM->aCpus[0];
3843
3844	/*
3845	* Validate input.
3846	*/
3847	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3848	if (!pVM)
3849	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3850
3851	/*
3852	* Force page directory sync.
3853	*/
3854	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3855	{
3856	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3857	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3858	}
3859	else
3860	{
3861	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3862	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3863	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3864	}
3865	}
3866
3867
3868	/**
3869	* The '.pgmphystofile' command.
3870	*
3871	* @returns VBox status.
3872	* @param pCmd Pointer to the command descriptor (as registered).
3873	* @param pCmdHlp Pointer to command helper functions.
3874	* @param pVM Pointer to the current VM (if any).
3875	* @param paArgs Pointer to (readonly) array of arguments.
3876	* @param cArgs Number of arguments in the array.
3877	*/
3878	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3879	{
3880	/*
3881	* Validate input.
3882	*/
3883	NOREF(pCmd);
3884	if (!pVM)
3885	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3886	if ( cArgs < 1
3887	\|\| cArgs > 2
3888	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
3889	\|\| ( cArgs > 1
3890	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
3891	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
3892	if ( cArgs >= 2
3893	&& strcmp(paArgs[1].u.pszString, "nozero"))
3894	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
3895	bool fIncZeroPgs = cArgs < 2;
3896
3897	/*
3898	* Open the output file and get the ram parameters.
3899	*/
3900	RTFILE hFile;
3901	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
3902	if (RT_FAILURE(rc))
3903	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
3904
3905	uint32_t cbRamHole = 0;
3906	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
3907	uint64_t cbRam = 0;
3908	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
3909	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
3910
3911	/*
3912	* Dump the physical memory, page by page.
3913	*/
3914	RTGCPHYS GCPhys = 0;
3915	char abZeroPg[PAGE_SIZE];
3916	RT_ZERO(abZeroPg);
3917
3918	pgmLock(pVM);
3919	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3920	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
3921	pRam = pRam->pNextR3)
3922	{
3923	/* fill the gap */
3924	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
3925	{
3926	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
3927	{
3928	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3929	GCPhys += PAGE_SIZE;
3930	}
3931	}
3932
3933	PCPGMPAGE pPage = &pRam->aPages[0];
3934	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
3935	{
3936	if ( PGM_PAGE_IS_ZERO(pPage)
3937	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3938	{
3939	if (fIncZeroPgs)
3940	{
3941	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3942	if (RT_FAILURE(rc))
3943	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3944	}
3945	}
3946	else
3947	{
3948	switch (PGM_PAGE_GET_TYPE(pPage))
3949	{
3950	case PGMPAGETYPE_RAM:
3951	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
3952	case PGMPAGETYPE_ROM:
3953	case PGMPAGETYPE_MMIO2:
3954	{
3955	void const *pvPage;
3956	PGMPAGEMAPLOCK Lock;
3957	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
3958	if (RT_SUCCESS(rc))
3959	{
3960	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
3961	PGMPhysReleasePageMappingLock(pVM, &Lock);
3962	if (RT_FAILURE(rc))
3963	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3964	}
3965	else
3966	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3967	break;
3968	}
3969
3970	default:
3971	AssertFailed();
3972	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3973	case PGMPAGETYPE_MMIO:
3974	if (fIncZeroPgs)
3975	{
3976	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3977	if (RT_FAILURE(rc))
3978	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3979	}
3980	break;
3981	}
3982	}
3983
3984
3985	/* advance */
3986	GCPhys += PAGE_SIZE;
3987	pPage++;
3988	}
3989	}
3990	pgmUnlock(pVM);
3991
3992	RTFileClose(hFile);
3993	if (RT_SUCCESS(rc))
3994	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
3995	return VINF_SUCCESS;
3996	}
3997
3998	#endif /* VBOX_WITH_DEBUGGER */
3999
4000	/**
4001	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4002	*/
4003	typedef struct PGMCHECKINTARGS
4004	{
4005	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4006	PPGMPHYSHANDLER pPrevPhys;
4007	PPGMVIRTHANDLER pPrevVirt;
4008	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4009	PVM pVM;
4010	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4011
4012	/**
4013	* Validate a node in the physical handler tree.
4014	*
4015	* @returns 0 on if ok, other wise 1.
4016	* @param pNode The handler node.
4017	* @param pvUser pVM.
4018	*/
4019	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4020	{
4021	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4022	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4023	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4024	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4025	AssertReleaseMsg( !pArgs->pPrevPhys
4026	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4027	("pPrevPhys=%p %RGp-%RGp %s\n"
4028	" pCur=%p %RGp-%RGp %s\n",
4029	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4030	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4031	pArgs->pPrevPhys = pCur;
4032	return 0;
4033	}
4034
4035
4036	/**
4037	* Validate a node in the virtual handler tree.
4038	*
4039	* @returns 0 on if ok, other wise 1.
4040	* @param pNode The handler node.
4041	* @param pvUser pVM.
4042	*/
4043	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4044	{
4045	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4046	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4047	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4048	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4049	AssertReleaseMsg( !pArgs->pPrevVirt
4050	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4051	("pPrevVirt=%p %RGv-%RGv %s\n"
4052	" pCur=%p %RGv-%RGv %s\n",
4053	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4054	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4055	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4056	{
4057	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4058	("pCur=%p %RGv-%RGv %s\n"
4059	"iPage=%d offVirtHandle=%#x expected %#x\n",
4060	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4061	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4062	}
4063	pArgs->pPrevVirt = pCur;
4064	return 0;
4065	}
4066
4067
4068	/**
4069	* Validate a node in the virtual handler tree.
4070	*
4071	* @returns 0 on if ok, other wise 1.
4072	* @param pNode The handler node.
4073	* @param pvUser pVM.
4074	*/
4075	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4076	{
4077	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4078	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4079	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4080	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4081	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4082	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4083	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4084	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4085	" pCur=%p %RGp-%RGp\n",
4086	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4087	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4088	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4089	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4090	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4091	" pCur=%p %RGp-%RGp\n",
4092	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4093	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4094	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4095	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4096	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4097	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4098	{
4099	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4100	for (;;)
4101	{
4102	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4103	AssertReleaseMsg(pCur2 != pCur,
4104	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4105	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4106	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4107	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4108	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4109	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4110	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4111	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4112	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4113	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4114	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4115	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4116	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4117	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4118	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4119	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4120	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4121	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4122	break;
4123	}
4124	}
4125
4126	pArgs->pPrevPhys2Virt = pCur;
4127	return 0;
4128	}
4129
4130
4131	/**
4132	* Perform an integrity check on the PGM component.
4133	*
4134	* @returns VINF_SUCCESS if everything is fine.
4135	* @returns VBox error status after asserting on integrity breach.
4136	* @param pVM The VM handle.
4137	*/
4138	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4139	{
4140	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4141
4142	/*
4143	* Check the trees.
4144	*/
4145	int cErrors = 0;
4146	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4147	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4148	PGMCHECKINTARGS Args = s_LeftToRight;
4149	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4150	Args = s_RightToLeft;
4151	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4152	Args = s_LeftToRight;
4153	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4154	Args = s_RightToLeft;
4155	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4156	Args = s_LeftToRight;
4157	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4158	Args = s_RightToLeft;
4159	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4160	Args = s_LeftToRight;
4161	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4162	Args = s_RightToLeft;
4163	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4164
4165	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4166	}
4167

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 41468

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