PGM.cpp@ 41783

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1	/* $Id: PGM.cpp 41783 2012-06-16 19:24:15Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred
30	* to as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	*
99	* @subsection sec_pgm_misc_A20 The A20 Gate
100	*
101	* PGM implements the A20 gate masking when translating a virtual guest address
102	* into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
103	* the code reading the guest page table entries during shadowing. The masking
104	* is done consistenly for all CPU modes, paged ones included. Large pages are
105	* also masked correctly. (On current CPUs, experiments indicates that AMD does
106	* not apply A20M in paged modes and intel only does it for the 2nd MB of
107	* memory.)
108	*
109	* The A20 gate implementation is per CPU core. It can be configured on a per
110	* core basis via the keyboard device and PC architecture device. This is
111	* probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
112	* guest OSes try pushing things anyway, so who cares. (On current real systems
113	* the A20M signal is probably only sent to the boot CPU and it affects all
114	* thread and probably all cores in that package.)
115	*
116	* The keyboard device and the PC architecture device doesn't OR their A20
117	* config bits together, rather they are currently implemented such that they
118	* mirror the CPU state. So, flipping the bit in either of them will change the
119	* A20 state. (On real hardware the bits of the two devices should probably be
120	* ORed together to indicate enabled, i.e. both needs to be cleared to disable
121	* A20 masking.)
122	*
123	* The A20 state will change immediately, transmeta fashion. There is no delays
124	* due to buses, wiring or other physical stuff. (On real hardware there are
125	* normally delays, the delays differs between the two devices and probably also
126	* between chipsets and CPU generations. Note that it's said that transmeta CPUs
127	* does the change immediately like us, they apparently intercept/handles the
128	* port accesses in microcode. Neat.)
129	*
130	* @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
131	*
132	*
133	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
134	*
135	* The differences between legacy PAE and long mode PAE are:
136	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
137	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
138	* usual meanings while 6 is ignored (AMD). This means that upon switching to
139	* legacy PAE mode we'll have to clear these bits and when going to long mode
140	* they must be set. This applies to both intermediate and shadow contexts,
141	* however we don't need to do it for the intermediate one since we're
142	* executing with CR0.WP at that time.
143	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
144	* a page aligned one is required.
145	*
146	*
147	* @section sec_pgm_handlers Access Handlers
148	*
149	* Placeholder.
150	*
151	*
152	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
153	*
154	* Placeholder.
155	*
156	*
157	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
158	*
159	* We currently implement three types of virtual access handlers: ALL, WRITE
160	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
161	*
162	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
163	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
164	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
165	* rest of this section is going to be about these handlers.
166	*
167	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
168	* how successful this is gonna be...
169	*
170	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
171	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
172	* and create a new node that is inserted into the AVL tree (range key). Then
173	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
174	*
175	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
176	*
177	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
178	* via the current guest CR3 and update the physical page -> virtual handler
179	* translation. Needless to say, this doesn't exactly scale very well. If any changes
180	* are detected, it will flag a virtual bit update just like we did on registration.
181	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
182	*
183	* 2b. The virtual bit update process will iterate all the pages covered by all the
184	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
185	* virtual handlers on that page.
186	*
187	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
188	* we don't miss any alias mappings of the monitored pages.
189	*
190	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
191	*
192	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
193	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
194	* will call the handlers like in the next step. If the physical mapping has
195	* changed we will - some time in the future - perform a handler callback
196	* (optional) and update the physical -> virtual handler cache.
197	*
198	* 4. \#PF(,write) on a page in the range. This will cause the handler to
199	* be invoked.
200	*
201	* 5. The guest invalidates the page and changes the physical backing or
202	* unmaps it. This should cause the invalidation callback to be invoked
203	* (it might not yet be 100% perfect). Exactly what happens next... is
204	* this where we mess up and end up out of sync for a while?
205	*
206	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
207	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
208	* this handler to NONE and trigger a full PGM resync (basically the same
209	* as int step 1). Which means 2 is executed again.
210	*
211	*
212	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
213	*
214	* There is a bunch of things that needs to be done to make the virtual handlers
215	* work 100% correctly and work more efficiently.
216	*
217	* The first bit hasn't been implemented yet because it's going to slow the
218	* whole mess down even more, and besides it seems to be working reliably for
219	* our current uses. OTOH, some of the optimizations might end up more or less
220	* implementing the missing bits, so we'll see.
221	*
222	* On the optimization side, the first thing to do is to try avoid unnecessary
223	* cache flushing. Then try team up with the shadowing code to track changes
224	* in mappings by means of access to them (shadow in), updates to shadows pages,
225	* invlpg, and shadow PT discarding (perhaps).
226	*
227	* Some idea that have popped up for optimization for current and new features:
228	* - bitmap indicating where there are virtual handlers installed.
229	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
230	* - Further optimize this by min/max (needs min/max avl getters).
231	* - Shadow page table entry bit (if any left)?
232	*
233	*/
234
235
236	/** @page pg_pgm_phys PGM Physical Guest Memory Management
237	*
238	*
239	* Objectives:
240	* - Guest RAM over-commitment using memory ballooning,
241	* zero pages and general page sharing.
242	* - Moving or mirroring a VM onto a different physical machine.
243	*
244	*
245	* @subsection subsec_pgmPhys_Definitions Definitions
246	*
247	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
248	* machinery associated with it.
249	*
250	*
251	*
252	*
253	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
254	*
255	* Initially we map all guest memory to the (per VM) zero page, which
256	* means that none of the read functions will cause pages to be allocated.
257	*
258	* Exception, access bit in page tables that have been shared. This must
259	* be handled, but we must also make sure PGMGst*Modify doesn't make
260	* unnecessary modifications.
261	*
262	* Allocation points:
263	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
264	* - Replacing a zero page mapping at \#PF.
265	* - Replacing a shared page mapping at \#PF.
266	* - ROM registration (currently MMR3RomRegister).
267	* - VM restore (pgmR3Load).
268	*
269	* For the first three it would make sense to keep a few pages handy
270	* until we've reached the max memory commitment for the VM.
271	*
272	* For the ROM registration, we know exactly how many pages we need
273	* and will request these from ring-0. For restore, we will save
274	* the number of non-zero pages in the saved state and allocate
275	* them up front. This would allow the ring-0 component to refuse
276	* the request if the isn't sufficient memory available for VM use.
277	*
278	* Btw. for both ROM and restore allocations we won't be requiring
279	* zeroed pages as they are going to be filled instantly.
280	*
281	*
282	* @subsection subsec_pgmPhys_FreePage Freeing a page
283	*
284	* There are a few points where a page can be freed:
285	* - After being replaced by the zero page.
286	* - After being replaced by a shared page.
287	* - After being ballooned by the guest additions.
288	* - At reset.
289	* - At restore.
290	*
291	* When freeing one or more pages they will be returned to the ring-0
292	* component and replaced by the zero page.
293	*
294	* The reasoning for clearing out all the pages on reset is that it will
295	* return us to the exact same state as on power on, and may thereby help
296	* us reduce the memory load on the system. Further it might have a
297	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
298	*
299	* On restore, as mention under the allocation topic, pages should be
300	* freed / allocated depending on how many is actually required by the
301	* new VM state. The simplest approach is to do like on reset, and free
302	* all non-ROM pages and then allocate what we need.
303	*
304	* A measure to prevent some fragmentation, would be to let each allocation
305	* chunk have some affinity towards the VM having allocated the most pages
306	* from it. Also, try make sure to allocate from allocation chunks that
307	* are almost full. Admittedly, both these measures might work counter to
308	* our intentions and its probably not worth putting a lot of effort,
309	* cpu time or memory into this.
310	*
311	*
312	* @subsection subsec_pgmPhys_SharePage Sharing a page
313	*
314	* The basic idea is that there there will be a idle priority kernel
315	* thread walking the non-shared VM pages hashing them and looking for
316	* pages with the same checksum. If such pages are found, it will compare
317	* them byte-by-byte to see if they actually are identical. If found to be
318	* identical it will allocate a shared page, copy the content, check that
319	* the page didn't change while doing this, and finally request both the
320	* VMs to use the shared page instead. If the page is all zeros (special
321	* checksum and byte-by-byte check) it will request the VM that owns it
322	* to replace it with the zero page.
323	*
324	* To make this efficient, we will have to make sure not to try share a page
325	* that will change its contents soon. This part requires the most work.
326	* A simple idea would be to request the VM to write monitor the page for
327	* a while to make sure it isn't modified any time soon. Also, it may
328	* make sense to skip pages that are being write monitored since this
329	* information is readily available to the thread if it works on the
330	* per-VM guest memory structures (presently called PGMRAMRANGE).
331	*
332	*
333	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
334	*
335	* The pages are organized in allocation chunks in ring-0, this is a necessity
336	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
337	* could easily work on a page-by-page basis if we liked. Whether this is possible
338	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
339	* become a problem as part of the idea here is that we wish to return memory to
340	* the host system.
341	*
342	* For instance, starting two VMs at the same time, they will both allocate the
343	* guest memory on-demand and if permitted their page allocations will be
344	* intermixed. Shut down one of the two VMs and it will be difficult to return
345	* any memory to the host system because the page allocation for the two VMs are
346	* mixed up in the same allocation chunks.
347	*
348	* To further complicate matters, when pages are freed because they have been
349	* ballooned or become shared/zero the whole idea is that the page is supposed
350	* to be reused by another VM or returned to the host system. This will cause
351	* allocation chunks to contain pages belonging to different VMs and prevent
352	* returning memory to the host when one of those VM shuts down.
353	*
354	* The only way to really deal with this problem is to move pages. This can
355	* either be done at VM shutdown and or by the idle priority worker thread
356	* that will be responsible for finding sharable/zero pages. The mechanisms
357	* involved for coercing a VM to move a page (or to do it for it) will be
358	* the same as when telling it to share/zero a page.
359	*
360	*
361	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
362	*
363	* There's a difficult balance between keeping the per-page tracking structures
364	* (global and guest page) easy to use and keeping them from eating too much
365	* memory. We have limited virtual memory resources available when operating in
366	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
367	* tracking structures will be attempted designed such that we can deal with up
368	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
369	*
370	*
371	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
372	*
373	* @see pg_GMM
374	*
375	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
376	*
377	* Fixed info is the physical address of the page (HCPhys) and the page id
378	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
379	* Today we've restricting ourselves to 40(-12) bits because this is the current
380	* restrictions of all AMD64 implementations (I think Barcelona will up this
381	* to 48(-12) bits, not that it really matters) and I needed the bits for
382	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
383	* decent range for the page id: 2^(28+12) = 1024TB.
384	*
385	* In additions to these, we'll have to keep maintaining the page flags as we
386	* currently do. Although it wouldn't harm to optimize these quite a bit, like
387	* for instance the ROM shouldn't depend on having a write handler installed
388	* in order for it to become read-only. A RO/RW bit should be considered so
389	* that the page syncing code doesn't have to mess about checking multiple
390	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
391	* figure out how to setup a shadow PTE. But this of course, is second
392	* priority at present. Current this requires 12 bits, but could probably
393	* be optimized to ~8.
394	*
395	* Then there's the 24 bits used to track which shadow page tables are
396	* currently mapping a page for the purpose of speeding up physical
397	* access handlers, and thereby the page pool cache. More bit for this
398	* purpose wouldn't hurt IIRC.
399	*
400	* Then there is a new bit in which we need to record what kind of page
401	* this is, shared, zero, normal or write-monitored-normal. This'll
402	* require 2 bits. One bit might be needed for indicating whether a
403	* write monitored page has been written to. And yet another one or
404	* two for tracking migration status. 3-4 bits total then.
405	*
406	* Whatever is left will can be used to record the sharabilitiy of a
407	* page. The page checksum will not be stored in the per-VM table as
408	* the idle thread will not be permitted to do modifications to it.
409	* It will instead have to keep its own working set of potentially
410	* shareable pages and their check sums and stuff.
411	*
412	* For the present we'll keep the current packing of the
413	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
414	* we'll have to change it to a struct with a total of 128-bits at
415	* our disposal.
416	*
417	* The initial layout will be like this:
418	* @verbatim
419	RTHCPHYS HCPhys; The current stuff.
420	63:40 Current shadow PT tracking stuff.
421	39:12 The physical page frame number.
422	11:0 The current flags.
423	uint32_t u28PageId : 28; The page id.
424	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
425	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
426	uint32_t u1Reserved : 1; Reserved for later.
427	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
428	@endverbatim
429	*
430	* The final layout will be something like this:
431	* @verbatim
432	RTHCPHYS HCPhys; The current stuff.
433	63:48 High page id (12+).
434	47:12 The physical page frame number.
435	11:0 Low page id.
436	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
437	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
438	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
439	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
440	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
441	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
442	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
443	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
444	@endverbatim
445	*
446	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
447	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
448	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
449	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
450	*
451	* A couple of cost examples for the total cost per-VM + kernel.
452	* 32-bit Windows and 32-bit linux:
453	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
454	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
455	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
456	* 64-bit Windows and 64-bit linux:
457	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
458	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
459	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
460	*
461	* UPDATE - 2007-09-27:
462	* Will need a ballooned flag/state too because we cannot
463	* trust the guest 100% and reporting the same page as ballooned more
464	* than once will put the GMM off balance.
465	*
466	*
467	* @subsection subsec_pgmPhys_Serializing Serializing Access
468	*
469	* Initially, we'll try a simple scheme:
470	*
471	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
472	* by the EMT thread of that VM while in the pgm critsect.
473	* - Other threads in the VM process that needs to make reliable use of
474	* the per-VM RAM tracking structures will enter the critsect.
475	* - No process external thread or kernel thread will ever try enter
476	* the pgm critical section, as that just won't work.
477	* - The idle thread (and similar threads) doesn't not need 100% reliable
478	* data when performing it tasks as the EMT thread will be the one to
479	* do the actual changes later anyway. So, as long as it only accesses
480	* the main ram range, it can do so by somehow preventing the VM from
481	* being destroyed while it works on it...
482	*
483	* - The over-commitment management, including the allocating/freeing
484	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
485	* more mundane mutex implementation is broken on Linux).
486	* - A separate mutex is protecting the set of allocation chunks so
487	* that pages can be shared or/and freed up while some other VM is
488	* allocating more chunks. This mutex can be take from under the other
489	* one, but not the other way around.
490	*
491	*
492	* @subsection subsec_pgmPhys_Request VM Request interface
493	*
494	* When in ring-0 it will become necessary to send requests to a VM so it can
495	* for instance move a page while defragmenting during VM destroy. The idle
496	* thread will make use of this interface to request VMs to setup shared
497	* pages and to perform write monitoring of pages.
498	*
499	* I would propose an interface similar to the current VMReq interface, similar
500	* in that it doesn't require locking and that the one sending the request may
501	* wait for completion if it wishes to. This shouldn't be very difficult to
502	* realize.
503	*
504	* The requests themselves are also pretty simple. They are basically:
505	* -# Check that some precondition is still true.
506	* -# Do the update.
507	* -# Update all shadow page tables involved with the page.
508	*
509	* The 3rd step is identical to what we're already doing when updating a
510	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
511	*
512	*
513	*
514	* @section sec_pgmPhys_MappingCaches Mapping Caches
515	*
516	* In order to be able to map in and out memory and to be able to support
517	* guest with more RAM than we've got virtual address space, we'll employing
518	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
519	* however on 32-bit darwin the ring-0 code is running in a different memory
520	* context and therefore needs a separate cache. In raw-mode context we also
521	* need a separate cache. The 32-bit darwin mapping cache and the one for
522	* raw-mode context share a lot of code, see PGMRZDYNMAP.
523	*
524	*
525	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
526	*
527	* We've considered implementing the ring-3 mapping cache page based but found
528	* that this was bother some when one had to take into account TLBs+SMP and
529	* portability (missing the necessary APIs on several platforms). There were
530	* also some performance concerns with this approach which hadn't quite been
531	* worked out.
532	*
533	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
534	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
535	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
536	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
537	* costly than a single page, although how much more costly is uncertain. We'll
538	* try address this by using a very big cache, preferably bigger than the actual
539	* VM RAM size if possible. The current VM RAM sizes should give some idea for
540	* 32-bit boxes, while on 64-bit we can probably get away with employing an
541	* unlimited cache.
542	*
543	* The cache have to parts, as already indicated, the ring-3 side and the
544	* ring-0 side.
545	*
546	* The ring-0 will be tied to the page allocator since it will operate on the
547	* memory objects it contains. It will therefore require the first ring-0 mutex
548	* discussed in @ref subsec_pgmPhys_Serializing. We
549	* some double house keeping wrt to who has mapped what I think, since both
550	* VMMR0.r0 and RTR0MemObj will keep track of mapping relations
551	*
552	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
553	* require anyone that desires to do changes to the mapping cache to do that
554	* from within this critsect. Alternatively, we could employ a separate critsect
555	* for serializing changes to the mapping cache as this would reduce potential
556	* contention with other threads accessing mappings unrelated to the changes
557	* that are in process. We can see about this later, contention will show
558	* up in the statistics anyway, so it'll be simple to tell.
559	*
560	* The organization of the ring-3 part will be very much like how the allocation
561	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
562	* having to walk the tree all the time, we'll have a couple of lookaside entries
563	* like in we do for I/O ports and MMIO in IOM.
564	*
565	* The simplified flow of a PGMPhysRead/Write function:
566	* -# Enter the PGM critsect.
567	* -# Lookup GCPhys in the ram ranges and get the Page ID.
568	* -# Calc the Allocation Chunk ID from the Page ID.
569	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
570	* If not found in cache:
571	* -# Call ring-0 and request it to be mapped and supply
572	* a chunk to be unmapped if the cache is maxed out already.
573	* -# Insert the new mapping into the AVL tree (id + R3 address).
574	* -# Update the relevant lookaside entry and return the mapping address.
575	* -# Do the read/write according to monitoring flags and everything.
576	* -# Leave the critsect.
577	*
578	*
579	* @section sec_pgmPhys_Fallback Fallback
580	*
581	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
582	* API and thus require a fallback.
583	*
584	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
585	* will return to the ring-3 caller (and later ring-0) and asking it to seed
586	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
587	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
588	* "SeededAllocPages" call to ring-0.
589	*
590	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
591	* all page sharing (zero page detection will continue). It will also force
592	* all allocations to come from the VM which seeded the page. Both these
593	* measures are taken to make sure that there will never be any need for
594	* mapping anything into ring-3 - everything will be mapped already.
595	*
596	* Whether we'll continue to use the current MM locked memory management
597	* for this I don't quite know (I'd prefer not to and just ditch that all
598	* together), we'll see what's simplest to do.
599	*
600	*
601	*
602	* @section sec_pgmPhys_Changes Changes
603	*
604	* Breakdown of the changes involved?
605	*/
606
607	/*******************************************************************************
608	* Header Files *
609	*******************************************************************************/
610	#define LOG_GROUP LOG_GROUP_PGM
611	#include <VBox/vmm/dbgf.h>
612	#include <VBox/vmm/pgm.h>
613	#include <VBox/vmm/cpum.h>
614	#include <VBox/vmm/iom.h>
615	#include <VBox/sup.h>
616	#include <VBox/vmm/mm.h>
617	#include <VBox/vmm/em.h>
618	#include <VBox/vmm/stam.h>
619	#ifdef VBOX_WITH_REM
620	# include <VBox/vmm/rem.h>
621	#endif
622	#include <VBox/vmm/selm.h>
623	#include <VBox/vmm/ssm.h>
624	#include <VBox/vmm/hwaccm.h>
625	#include "PGMInternal.h"
626	#include <VBox/vmm/vm.h>
627	#include "PGMInline.h"
628
629	#include <VBox/dbg.h>
630	#include <VBox/param.h>
631	#include <VBox/err.h>
632
633	#include <iprt/asm.h>
634	#include <iprt/asm-amd64-x86.h>
635	#include <iprt/assert.h>
636	#include <iprt/env.h>
637	#include <iprt/mem.h>
638	#include <iprt/file.h>
639	#include <iprt/string.h>
640	#include <iprt/thread.h>
641
642
643	/*******************************************************************************
644	* Internal Functions *
645	*******************************************************************************/
646	static int pgmR3InitPaging(PVM pVM);
647	static int pgmR3InitStats(PVM pVM);
648	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
649	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
650	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
651	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
652	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
653	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
654	#ifdef VBOX_STRICT
655	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
656	#endif
657	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
658	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
659	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
660
661	#ifdef VBOX_WITH_DEBUGGER
662	/** @todo Convert the first two commands to 'info' items. */
663	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
664	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
665	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
666	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
667	# ifdef VBOX_STRICT
668	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
669	# endif
670	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
671	#endif
672
673
674	/*******************************************************************************
675	* Global Variables *
676	*******************************************************************************/
677	#ifdef VBOX_WITH_DEBUGGER
678	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
679	static const DBGCVARDESC g_aPgmErrorArgs[] =
680	{
681	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
682	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
683	};
684
685	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
686	{
687	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
688	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
689	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
690	};
691
692	# ifdef DEBUG_sandervl
693	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
694	{
695	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
696	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
697	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
698	};
699	# endif
700
701	/** Command descriptors. */
702	static const DBGCCMD g_aCmds[] =
703	{
704	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
705	{ "pgmram", 0, 0, NULL, 0, 0, pgmR3CmdRam, "", "Display the ram ranges." },
706	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
707	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
708	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
709	# ifdef VBOX_STRICT
710	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
711	# ifdef VBOX_WITH_PAGE_SHARING
712	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
713	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
714	# endif
715	# endif
716	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
717	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
718	};
719	#endif
720
721
722
723
724	/*
725	* Shadow - 32-bit mode
726	*/
727	#define PGM_SHW_TYPE PGM_TYPE_32BIT
728	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
729	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
730	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
731	#include "PGMShw.h"
732
733	/* Guest - real mode */
734	#define PGM_GST_TYPE PGM_TYPE_REAL
735	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
736	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
737	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
738	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
739	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
740	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
741	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
742	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
743	#include "PGMBth.h"
744	#include "PGMGstDefs.h"
745	#include "PGMGst.h"
746	#undef BTH_PGMPOOLKIND_PT_FOR_PT
747	#undef BTH_PGMPOOLKIND_ROOT
748	#undef PGM_BTH_NAME
749	#undef PGM_BTH_NAME_RC_STR
750	#undef PGM_BTH_NAME_R0_STR
751	#undef PGM_GST_TYPE
752	#undef PGM_GST_NAME
753	#undef PGM_GST_NAME_RC_STR
754	#undef PGM_GST_NAME_R0_STR
755
756	/* Guest - protected mode */
757	#define PGM_GST_TYPE PGM_TYPE_PROT
758	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
759	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
760	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
761	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
762	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
763	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
764	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
765	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
766	#include "PGMBth.h"
767	#include "PGMGstDefs.h"
768	#include "PGMGst.h"
769	#undef BTH_PGMPOOLKIND_PT_FOR_PT
770	#undef BTH_PGMPOOLKIND_ROOT
771	#undef PGM_BTH_NAME
772	#undef PGM_BTH_NAME_RC_STR
773	#undef PGM_BTH_NAME_R0_STR
774	#undef PGM_GST_TYPE
775	#undef PGM_GST_NAME
776	#undef PGM_GST_NAME_RC_STR
777	#undef PGM_GST_NAME_R0_STR
778
779	/* Guest - 32-bit mode */
780	#define PGM_GST_TYPE PGM_TYPE_32BIT
781	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
782	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
783	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
784	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
785	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
786	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
787	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
788	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
789	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
790	#include "PGMBth.h"
791	#include "PGMGstDefs.h"
792	#include "PGMGst.h"
793	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
794	#undef BTH_PGMPOOLKIND_PT_FOR_PT
795	#undef BTH_PGMPOOLKIND_ROOT
796	#undef PGM_BTH_NAME
797	#undef PGM_BTH_NAME_RC_STR
798	#undef PGM_BTH_NAME_R0_STR
799	#undef PGM_GST_TYPE
800	#undef PGM_GST_NAME
801	#undef PGM_GST_NAME_RC_STR
802	#undef PGM_GST_NAME_R0_STR
803
804	#undef PGM_SHW_TYPE
805	#undef PGM_SHW_NAME
806	#undef PGM_SHW_NAME_RC_STR
807	#undef PGM_SHW_NAME_R0_STR
808
809
810	/*
811	* Shadow - PAE mode
812	*/
813	#define PGM_SHW_TYPE PGM_TYPE_PAE
814	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
815	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
816	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
817	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
818	#include "PGMShw.h"
819
820	/* Guest - real mode */
821	#define PGM_GST_TYPE PGM_TYPE_REAL
822	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
823	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
824	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
825	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
826	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
827	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
828	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
829	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
830	#include "PGMGstDefs.h"
831	#include "PGMBth.h"
832	#undef BTH_PGMPOOLKIND_PT_FOR_PT
833	#undef BTH_PGMPOOLKIND_ROOT
834	#undef PGM_BTH_NAME
835	#undef PGM_BTH_NAME_RC_STR
836	#undef PGM_BTH_NAME_R0_STR
837	#undef PGM_GST_TYPE
838	#undef PGM_GST_NAME
839	#undef PGM_GST_NAME_RC_STR
840	#undef PGM_GST_NAME_R0_STR
841
842	/* Guest - protected mode */
843	#define PGM_GST_TYPE PGM_TYPE_PROT
844	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
845	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
846	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
847	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
848	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
849	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
850	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
851	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
852	#include "PGMGstDefs.h"
853	#include "PGMBth.h"
854	#undef BTH_PGMPOOLKIND_PT_FOR_PT
855	#undef BTH_PGMPOOLKIND_ROOT
856	#undef PGM_BTH_NAME
857	#undef PGM_BTH_NAME_RC_STR
858	#undef PGM_BTH_NAME_R0_STR
859	#undef PGM_GST_TYPE
860	#undef PGM_GST_NAME
861	#undef PGM_GST_NAME_RC_STR
862	#undef PGM_GST_NAME_R0_STR
863
864	/* Guest - 32-bit mode */
865	#define PGM_GST_TYPE PGM_TYPE_32BIT
866	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
867	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
868	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
869	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
870	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
871	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
872	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
873	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
874	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
875	#include "PGMGstDefs.h"
876	#include "PGMBth.h"
877	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
878	#undef BTH_PGMPOOLKIND_PT_FOR_PT
879	#undef BTH_PGMPOOLKIND_ROOT
880	#undef PGM_BTH_NAME
881	#undef PGM_BTH_NAME_RC_STR
882	#undef PGM_BTH_NAME_R0_STR
883	#undef PGM_GST_TYPE
884	#undef PGM_GST_NAME
885	#undef PGM_GST_NAME_RC_STR
886	#undef PGM_GST_NAME_R0_STR
887
888	/* Guest - PAE mode */
889	#define PGM_GST_TYPE PGM_TYPE_PAE
890	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
891	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
892	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
893	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
894	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
895	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
896	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
897	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
898	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
899	#include "PGMBth.h"
900	#include "PGMGstDefs.h"
901	#include "PGMGst.h"
902	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
903	#undef BTH_PGMPOOLKIND_PT_FOR_PT
904	#undef BTH_PGMPOOLKIND_ROOT
905	#undef PGM_BTH_NAME
906	#undef PGM_BTH_NAME_RC_STR
907	#undef PGM_BTH_NAME_R0_STR
908	#undef PGM_GST_TYPE
909	#undef PGM_GST_NAME
910	#undef PGM_GST_NAME_RC_STR
911	#undef PGM_GST_NAME_R0_STR
912
913	#undef PGM_SHW_TYPE
914	#undef PGM_SHW_NAME
915	#undef PGM_SHW_NAME_RC_STR
916	#undef PGM_SHW_NAME_R0_STR
917
918
919	/*
920	* Shadow - AMD64 mode
921	*/
922	#define PGM_SHW_TYPE PGM_TYPE_AMD64
923	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
924	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
925	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
926	#include "PGMShw.h"
927
928	#ifdef VBOX_WITH_64_BITS_GUESTS
929	/* Guest - AMD64 mode */
930	# define PGM_GST_TYPE PGM_TYPE_AMD64
931	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
932	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
933	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
934	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
935	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
936	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
937	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
938	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
939	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
940	# include "PGMBth.h"
941	# include "PGMGstDefs.h"
942	# include "PGMGst.h"
943	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
944	# undef BTH_PGMPOOLKIND_PT_FOR_PT
945	# undef BTH_PGMPOOLKIND_ROOT
946	# undef PGM_BTH_NAME
947	# undef PGM_BTH_NAME_RC_STR
948	# undef PGM_BTH_NAME_R0_STR
949	# undef PGM_GST_TYPE
950	# undef PGM_GST_NAME
951	# undef PGM_GST_NAME_RC_STR
952	# undef PGM_GST_NAME_R0_STR
953	#endif /* VBOX_WITH_64_BITS_GUESTS */
954
955	#undef PGM_SHW_TYPE
956	#undef PGM_SHW_NAME
957	#undef PGM_SHW_NAME_RC_STR
958	#undef PGM_SHW_NAME_R0_STR
959
960
961	/*
962	* Shadow - Nested paging mode
963	*/
964	#define PGM_SHW_TYPE PGM_TYPE_NESTED
965	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
966	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
967	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
968	#include "PGMShw.h"
969
970	/* Guest - real mode */
971	#define PGM_GST_TYPE PGM_TYPE_REAL
972	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
973	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
974	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
975	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
976	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
977	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
978	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
979	#include "PGMGstDefs.h"
980	#include "PGMBth.h"
981	#undef BTH_PGMPOOLKIND_PT_FOR_PT
982	#undef PGM_BTH_NAME
983	#undef PGM_BTH_NAME_RC_STR
984	#undef PGM_BTH_NAME_R0_STR
985	#undef PGM_GST_TYPE
986	#undef PGM_GST_NAME
987	#undef PGM_GST_NAME_RC_STR
988	#undef PGM_GST_NAME_R0_STR
989
990	/* Guest - protected mode */
991	#define PGM_GST_TYPE PGM_TYPE_PROT
992	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
993	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
994	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
995	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
996	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
997	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
998	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
999	#include "PGMGstDefs.h"
1000	#include "PGMBth.h"
1001	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1002	#undef PGM_BTH_NAME
1003	#undef PGM_BTH_NAME_RC_STR
1004	#undef PGM_BTH_NAME_R0_STR
1005	#undef PGM_GST_TYPE
1006	#undef PGM_GST_NAME
1007	#undef PGM_GST_NAME_RC_STR
1008	#undef PGM_GST_NAME_R0_STR
1009
1010	/* Guest - 32-bit mode */
1011	#define PGM_GST_TYPE PGM_TYPE_32BIT
1012	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1013	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1014	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1015	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
1016	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
1017	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
1018	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1019	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1020	#include "PGMGstDefs.h"
1021	#include "PGMBth.h"
1022	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1023	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1024	#undef PGM_BTH_NAME
1025	#undef PGM_BTH_NAME_RC_STR
1026	#undef PGM_BTH_NAME_R0_STR
1027	#undef PGM_GST_TYPE
1028	#undef PGM_GST_NAME
1029	#undef PGM_GST_NAME_RC_STR
1030	#undef PGM_GST_NAME_R0_STR
1031
1032	/* Guest - PAE mode */
1033	#define PGM_GST_TYPE PGM_TYPE_PAE
1034	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1035	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1036	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1037	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1038	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1039	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1040	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1041	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1042	#include "PGMGstDefs.h"
1043	#include "PGMBth.h"
1044	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1045	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1046	#undef PGM_BTH_NAME
1047	#undef PGM_BTH_NAME_RC_STR
1048	#undef PGM_BTH_NAME_R0_STR
1049	#undef PGM_GST_TYPE
1050	#undef PGM_GST_NAME
1051	#undef PGM_GST_NAME_RC_STR
1052	#undef PGM_GST_NAME_R0_STR
1053
1054	#ifdef VBOX_WITH_64_BITS_GUESTS
1055	/* Guest - AMD64 mode */
1056	# define PGM_GST_TYPE PGM_TYPE_AMD64
1057	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1058	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1059	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1060	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1061	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1062	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1063	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1064	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1065	# include "PGMGstDefs.h"
1066	# include "PGMBth.h"
1067	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1068	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1069	# undef PGM_BTH_NAME
1070	# undef PGM_BTH_NAME_RC_STR
1071	# undef PGM_BTH_NAME_R0_STR
1072	# undef PGM_GST_TYPE
1073	# undef PGM_GST_NAME
1074	# undef PGM_GST_NAME_RC_STR
1075	# undef PGM_GST_NAME_R0_STR
1076	#endif /* VBOX_WITH_64_BITS_GUESTS */
1077
1078	#undef PGM_SHW_TYPE
1079	#undef PGM_SHW_NAME
1080	#undef PGM_SHW_NAME_RC_STR
1081	#undef PGM_SHW_NAME_R0_STR
1082
1083
1084	/*
1085	* Shadow - EPT
1086	*/
1087	#define PGM_SHW_TYPE PGM_TYPE_EPT
1088	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1089	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1090	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1091	#include "PGMShw.h"
1092
1093	/* Guest - real mode */
1094	#define PGM_GST_TYPE PGM_TYPE_REAL
1095	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1096	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1097	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1098	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1099	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1100	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1101	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1102	#include "PGMGstDefs.h"
1103	#include "PGMBth.h"
1104	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1105	#undef PGM_BTH_NAME
1106	#undef PGM_BTH_NAME_RC_STR
1107	#undef PGM_BTH_NAME_R0_STR
1108	#undef PGM_GST_TYPE
1109	#undef PGM_GST_NAME
1110	#undef PGM_GST_NAME_RC_STR
1111	#undef PGM_GST_NAME_R0_STR
1112
1113	/* Guest - protected mode */
1114	#define PGM_GST_TYPE PGM_TYPE_PROT
1115	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1116	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1117	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1118	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1119	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1120	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1121	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1122	#include "PGMGstDefs.h"
1123	#include "PGMBth.h"
1124	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1125	#undef PGM_BTH_NAME
1126	#undef PGM_BTH_NAME_RC_STR
1127	#undef PGM_BTH_NAME_R0_STR
1128	#undef PGM_GST_TYPE
1129	#undef PGM_GST_NAME
1130	#undef PGM_GST_NAME_RC_STR
1131	#undef PGM_GST_NAME_R0_STR
1132
1133	/* Guest - 32-bit mode */
1134	#define PGM_GST_TYPE PGM_TYPE_32BIT
1135	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1136	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1137	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1138	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1139	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1140	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1141	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1142	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1143	#include "PGMGstDefs.h"
1144	#include "PGMBth.h"
1145	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1146	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1147	#undef PGM_BTH_NAME
1148	#undef PGM_BTH_NAME_RC_STR
1149	#undef PGM_BTH_NAME_R0_STR
1150	#undef PGM_GST_TYPE
1151	#undef PGM_GST_NAME
1152	#undef PGM_GST_NAME_RC_STR
1153	#undef PGM_GST_NAME_R0_STR
1154
1155	/* Guest - PAE mode */
1156	#define PGM_GST_TYPE PGM_TYPE_PAE
1157	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1158	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1159	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1160	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1161	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1162	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1163	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1164	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1165	#include "PGMGstDefs.h"
1166	#include "PGMBth.h"
1167	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1168	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1169	#undef PGM_BTH_NAME
1170	#undef PGM_BTH_NAME_RC_STR
1171	#undef PGM_BTH_NAME_R0_STR
1172	#undef PGM_GST_TYPE
1173	#undef PGM_GST_NAME
1174	#undef PGM_GST_NAME_RC_STR
1175	#undef PGM_GST_NAME_R0_STR
1176
1177	#ifdef VBOX_WITH_64_BITS_GUESTS
1178	/* Guest - AMD64 mode */
1179	# define PGM_GST_TYPE PGM_TYPE_AMD64
1180	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1181	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1182	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1183	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1184	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1185	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1186	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1187	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1188	# include "PGMGstDefs.h"
1189	# include "PGMBth.h"
1190	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1191	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1192	# undef PGM_BTH_NAME
1193	# undef PGM_BTH_NAME_RC_STR
1194	# undef PGM_BTH_NAME_R0_STR
1195	# undef PGM_GST_TYPE
1196	# undef PGM_GST_NAME
1197	# undef PGM_GST_NAME_RC_STR
1198	# undef PGM_GST_NAME_R0_STR
1199	#endif /* VBOX_WITH_64_BITS_GUESTS */
1200
1201	#undef PGM_SHW_TYPE
1202	#undef PGM_SHW_NAME
1203	#undef PGM_SHW_NAME_RC_STR
1204	#undef PGM_SHW_NAME_R0_STR
1205
1206
1207
1208	/**
1209	* Initiates the paging of VM.
1210	*
1211	* @returns VBox status code.
1212	* @param pVM Pointer to VM structure.
1213	*/
1214	VMMR3DECL(int) PGMR3Init(PVM pVM)
1215	{
1216	LogFlow(("PGMR3Init:\n"));
1217	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1218	int rc;
1219
1220	/*
1221	* Assert alignment and sizes.
1222	*/
1223	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1224	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1225	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1226
1227	/*
1228	* Init the structure.
1229	*/
1230	#ifdef PGM_WITHOUT_MAPPINGS
1231	pVM->pgm.s.fMappingsDisabled = true;
1232	#endif
1233	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1234	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1235
1236	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1237	{
1238	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1239	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1240	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1241	}
1242
1243	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1244	{
1245	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1246	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1247	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1248	}
1249
1250	/* Init the per-CPU part. */
1251	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1252	{
1253	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1254	PPGMCPU pPGM = &pVCpu->pgm.s;
1255
1256	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1257	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1258	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1259
1260	pPGM->enmShadowMode = PGMMODE_INVALID;
1261	pPGM->enmGuestMode = PGMMODE_INVALID;
1262
1263	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1264
1265	pPGM->pGst32BitPdR3 = NULL;
1266	pPGM->pGstPaePdptR3 = NULL;
1267	pPGM->pGstAmd64Pml4R3 = NULL;
1268	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1269	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1270	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1271	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1272	#endif
1273	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1274	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1275	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1276	{
1277	pPGM->apGstPaePDsR3[i] = NULL;
1278	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1279	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1280	#endif
1281	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1282	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1283	pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1284	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1285	}
1286
1287	pPGM->fA20Enabled = true;
1288	pPGM->GCPhysA20Mask = ~(RTGCPHYS)(!pPGM->fA20Enabled << 20);
1289	}
1290
1291	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1292	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1293	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1294
1295	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1296	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1297	true
1298	#else
1299	false
1300	#endif
1301	);
1302	AssertLogRelRCReturn(rc, rc);
1303
1304	#if HC_ARCH_BITS == 32
1305	# ifdef RT_OS_DARWIN
1306	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1307	# else
1308	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1309	# endif
1310	#else
1311	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1312	#endif
1313	AssertLogRelRCReturn(rc, rc);
1314	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1315	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1316
1317	/*
1318	* Get the configured RAM size - to estimate saved state size.
1319	*/
1320	uint64_t cbRam;
1321	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1322	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1323	cbRam = 0;
1324	else if (RT_SUCCESS(rc))
1325	{
1326	if (cbRam < PAGE_SIZE)
1327	cbRam = 0;
1328	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1329	}
1330	else
1331	{
1332	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1333	return rc;
1334	}
1335
1336	/*
1337	* Check for PCI pass-through.
1338	*/
1339	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1340	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1341	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1342
1343	#ifdef VBOX_WITH_STATISTICS
1344	/*
1345	* Allocate memory for the statistics before someone tries to use them.
1346	*/
1347	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1348	void *pv;
1349	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1350	AssertRCReturn(rc, rc);
1351
1352	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1353	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1354	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1355	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1356
1357	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1358	{
1359	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1360	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1361	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1362
1363	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1364	}
1365	#endif /* VBOX_WITH_STATISTICS */
1366
1367	/*
1368	* Register callbacks, string formatters and the saved state data unit.
1369	*/
1370	#ifdef VBOX_STRICT
1371	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1372	#endif
1373	PGMRegisterStringFormatTypes();
1374
1375	rc = pgmR3InitSavedState(pVM, cbRam);
1376	if (RT_FAILURE(rc))
1377	return rc;
1378
1379	/*
1380	* Initialize the PGM critical section and flush the phys TLBs
1381	*/
1382	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1383	AssertRCReturn(rc, rc);
1384
1385	PGMR3PhysChunkInvalidateTLB(pVM);
1386	pgmPhysInvalidatePageMapTLB(pVM);
1387
1388	/*
1389	* For the time being we sport a full set of handy pages in addition to the base
1390	* memory to simplify things.
1391	*/
1392	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1393	AssertRCReturn(rc, rc);
1394
1395	/*
1396	* Trees
1397	*/
1398	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1399	if (RT_SUCCESS(rc))
1400	{
1401	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1402	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1403
1404	/*
1405	* Allocate the zero page.
1406	*/
1407	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1408	}
1409	if (RT_SUCCESS(rc))
1410	{
1411	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1412	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1413	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1414	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1415
1416	/*
1417	* Allocate the invalid MMIO page.
1418	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1419	*/
1420	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1421	}
1422	if (RT_SUCCESS(rc))
1423	{
1424	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1425	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1426	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1427	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1428
1429	/*
1430	* Init the paging.
1431	*/
1432	rc = pgmR3InitPaging(pVM);
1433	}
1434	if (RT_SUCCESS(rc))
1435	{
1436	/*
1437	* Init the page pool.
1438	*/
1439	rc = pgmR3PoolInit(pVM);
1440	}
1441	if (RT_SUCCESS(rc))
1442	{
1443	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1444	{
1445	PVMCPU pVCpu = &pVM->aCpus[i];
1446	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1447	if (RT_FAILURE(rc))
1448	break;
1449	}
1450	}
1451
1452	if (RT_SUCCESS(rc))
1453	{
1454	/*
1455	* Info & statistics
1456	*/
1457	DBGFR3InfoRegisterInternal(pVM, "mode",
1458	"Shows the current paging mode. "
1459	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1460	pgmR3InfoMode);
1461	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1462	"Dumps all the entries in the top level paging table. No arguments.",
1463	pgmR3InfoCr3);
1464	DBGFR3InfoRegisterInternal(pVM, "phys",
1465	"Dumps all the physical address ranges. No arguments.",
1466	pgmR3PhysInfo);
1467	DBGFR3InfoRegisterInternal(pVM, "handlers",
1468	"Dumps physical, virtual and hyper virtual handlers. "
1469	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1470	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1471	pgmR3InfoHandlers);
1472	DBGFR3InfoRegisterInternal(pVM, "mappings",
1473	"Dumps guest mappings.",
1474	pgmR3MapInfo);
1475
1476	pgmR3InitStats(pVM);
1477
1478	#ifdef VBOX_WITH_DEBUGGER
1479	/*
1480	* Debugger commands.
1481	*/
1482	static bool s_fRegisteredCmds = false;
1483	if (!s_fRegisteredCmds)
1484	{
1485	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1486	if (RT_SUCCESS(rc2))
1487	s_fRegisteredCmds = true;
1488	}
1489	#endif
1490	return VINF_SUCCESS;
1491	}
1492
1493	/* Almost no cleanup necessary, MM frees all memory. */
1494	PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1495
1496	return rc;
1497	}
1498
1499
1500	/**
1501	* Init paging.
1502	*
1503	* Since we need to check what mode the host is operating in before we can choose
1504	* the right paging functions for the host we have to delay this until R0 has
1505	* been initialized.
1506	*
1507	* @returns VBox status code.
1508	* @param pVM VM handle.
1509	*/
1510	static int pgmR3InitPaging(PVM pVM)
1511	{
1512	/*
1513	* Force a recalculation of modes and switcher so everyone gets notified.
1514	*/
1515	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1516	{
1517	PVMCPU pVCpu = &pVM->aCpus[i];
1518
1519	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1520	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1521	}
1522
1523	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1524
1525	/*
1526	* Allocate static mapping space for whatever the cr3 register
1527	* points to and in the case of PAE mode to the 4 PDs.
1528	*/
1529	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1530	if (RT_FAILURE(rc))
1531	{
1532	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1533	return rc;
1534	}
1535	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1536
1537	/*
1538	* Allocate pages for the three possible intermediate contexts
1539	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1540	* for the sake of simplicity. The AMD64 uses the PAE for the
1541	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1542	*
1543	* We assume that two page tables will be enought for the core code
1544	* mappings (HC virtual and identity).
1545	*/
1546	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1547	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1548	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1549	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1550	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1551	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1552	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1553	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1554	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1555	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1556	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1557	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1558
1559	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1560	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1561	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1562	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1563	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1564	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1565
1566	/*
1567	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1568	*/
1569	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1570	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1571	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1572
1573	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1574	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1575
1576	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1577	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1578	{
1579	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1580	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1581	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1582	}
1583
1584	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1585	{
1586	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1587	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1588	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1589	}
1590
1591	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1592	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1593	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1594	\| HCPhysInterPaePDPT64;
1595
1596	/*
1597	* Initialize paging workers and mode from current host mode
1598	* and the guest running in real mode.
1599	*/
1600	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1601	switch (pVM->pgm.s.enmHostMode)
1602	{
1603	case SUPPAGINGMODE_32_BIT:
1604	case SUPPAGINGMODE_32_BIT_GLOBAL:
1605	case SUPPAGINGMODE_PAE:
1606	case SUPPAGINGMODE_PAE_GLOBAL:
1607	case SUPPAGINGMODE_PAE_NX:
1608	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1609	break;
1610
1611	case SUPPAGINGMODE_AMD64:
1612	case SUPPAGINGMODE_AMD64_GLOBAL:
1613	case SUPPAGINGMODE_AMD64_NX:
1614	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1615	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1616	if (ARCH_BITS != 64)
1617	{
1618	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1619	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1620	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1621	}
1622	#endif
1623	break;
1624	default:
1625	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1626	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1627	}
1628	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1629	if (RT_SUCCESS(rc))
1630	{
1631	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1632	#if HC_ARCH_BITS == 64
1633	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1634	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1635	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1636	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1637	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1638	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1639	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1640	#endif
1641
1642	/*
1643	* Log the host paging mode. It may come in handy.
1644	*/
1645	const char *pszHostMode;
1646	switch (pVM->pgm.s.enmHostMode)
1647	{
1648	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1649	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1650	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1651	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1652	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1653	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1654	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1655	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1656	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1657	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1658	default: pszHostMode = "???"; break;
1659	}
1660	LogRel(("Host paging mode: %s\n", pszHostMode));
1661
1662	return VINF_SUCCESS;
1663	}
1664
1665	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1666	return rc;
1667	}
1668
1669
1670	/**
1671	* Init statistics
1672	* @returns VBox status code.
1673	*/
1674	static int pgmR3InitStats(PVM pVM)
1675	{
1676	PPGM pPGM = &pVM->pgm.s;
1677	int rc;
1678
1679	/*
1680	* Release statistics.
1681	*/
1682	/* Common - misc variables */
1683	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1684	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1685	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1686	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1687	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1688	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1689	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1690	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1691	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1692	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1693	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1694	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1695	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1696	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1697	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1698	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1699	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1700	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1701	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1702
1703	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1704	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1705	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1706
1707	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1708
1709	/* Live save */
1710	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1711	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1712	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1713	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1714	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1715	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1716	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1717	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1718	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1719	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1720	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1721	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1722	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1723	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1724	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1725	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1726	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1727	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1728
1729	#ifdef VBOX_WITH_STATISTICS
1730
1731	# define PGM_REG_COUNTER(a, b, c) \
1732	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1733	AssertRC(rc);
1734
1735	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1736	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1737	AssertRC(rc);
1738
1739	# define PGM_REG_PROFILE(a, b, c) \
1740	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1741	AssertRC(rc);
1742
1743	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1744
1745	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1746	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1747	PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1748	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1749	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1750
1751	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1752	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1753	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1754	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1755	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1756	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1757	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1758	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1759	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1760	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1761
1762	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1763	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1764	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1765	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1766	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1767	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1768
1769	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1770	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1771	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1772	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1773	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1774	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1775	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1776	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1777
1778	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1779	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1780	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1781	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1782
1783	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1784	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1785	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1786	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1787
1788	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1789	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1790	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1791	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1792	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1793	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1794	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1795	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1796
1797	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1798	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1799	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1800	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1801	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1802	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1803
1804	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1805	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1806	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1807	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1808	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1809	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1810	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1811	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1812
1813	/* GC only: */
1814	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1815	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1816
1817	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1818	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1819	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1820	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1821	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1822	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1823	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1824	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1825
1826	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1827	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1828	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1829	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1830	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1831	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1832	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1833
1834	# undef PGM_REG_COUNTER
1835	# undef PGM_REG_PROFILE
1836	#endif
1837
1838	/*
1839	* Note! The layout below matches the member layout exactly!
1840	*/
1841
1842	/*
1843	* Common - stats
1844	*/
1845	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1846	{
1847	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1848
1849	#define PGM_REG_COUNTER(a, b, c) \
1850	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1851	AssertRC(rc);
1852	#define PGM_REG_PROFILE(a, b, c) \
1853	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1854	AssertRC(rc);
1855
1856	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1857	PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1858
1859	#ifdef VBOX_WITH_STATISTICS
1860	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1861
1862	# if 0 /* rarely useful; leave for debugging. */
1863	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1864	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1865	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1866	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1867	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1868	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1869	# endif
1870	/* R0 only: */
1871	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1872	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1873
1874	/* RZ only: */
1875	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1876	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1877	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1878	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1879	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1880	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1881	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1882	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1883	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1884	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1885	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1886	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1887	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1888	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1889	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1890	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1891	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1892	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1893	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1894	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1895	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1896	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1897	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1898	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1899	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1900	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1901	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1902	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1903	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1904	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1905	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1906	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1907	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1908	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1909	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1910	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1911	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1912	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1913	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1914	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1915	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1916	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1917	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1918	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1919	#if 0 /* rarely useful; leave for debugging. */
1920	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1921	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1922	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1923	#endif
1924	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1925	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1926	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1927	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1928	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1929
1930	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1931	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1932	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1933	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1934	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1935	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1936	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1937	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1938	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1939	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1940	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1941	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1942	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1943	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1944	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1945	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1946	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1947	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1948	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1949	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1950	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1951	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1952	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1953	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1954	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1955	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1956	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1957	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1958	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1959	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1960	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1961	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1962	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1963	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1964	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1965	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1966
1967	/* HC only: */
1968
1969	/* RZ & R3: */
1970	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1971	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1972	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1973	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1974	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1975	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1976	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1977	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1978	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1979	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1980	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1981	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1982	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1983	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1984	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1985	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1986	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1987	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1988	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1989	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1990	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1991	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1992	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1993	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1994	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1995	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1996	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1997	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1998	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1999	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2000	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2001	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2002	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2003	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2004	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2005	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2006	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2007	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2008	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2009	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2010	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
2011	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2012	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2013	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2014	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2015	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2016	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2017
2018	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2019	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2020	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
2021	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2022	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2023	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2024	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2025	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2026	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2027	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2028	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
2029	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2030	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
2031	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
2032	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2033	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2034	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2035	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2036	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2037	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2038	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2039	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2040	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2041	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2042	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2043	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2044	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2045	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2046	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2047	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2048	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2049	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2050	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2051	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2052	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2053	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2054	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2055	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2056	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2057	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2058	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2059	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2060	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2061	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2062	#endif /* VBOX_WITH_STATISTICS */
2063
2064	#undef PGM_REG_PROFILE
2065	#undef PGM_REG_COUNTER
2066
2067	}
2068
2069	return VINF_SUCCESS;
2070	}
2071
2072
2073	/**
2074	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2075	*
2076	* The dynamic mapping area will also be allocated and initialized at this
2077	* time. We could allocate it during PGMR3Init of course, but the mapping
2078	* wouldn't be allocated at that time preventing us from setting up the
2079	* page table entries with the dummy page.
2080	*
2081	* @returns VBox status code.
2082	* @param pVM VM handle.
2083	*/
2084	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2085	{
2086	RTGCPTR GCPtr;
2087	int rc;
2088
2089	/*
2090	* Reserve space for the dynamic mappings.
2091	*/
2092	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2093	if (RT_SUCCESS(rc))
2094	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2095
2096	if ( RT_SUCCESS(rc)
2097	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2098	{
2099	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2100	if (RT_SUCCESS(rc))
2101	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2102	}
2103	if (RT_SUCCESS(rc))
2104	{
2105	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2106	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2107	}
2108	return rc;
2109	}
2110
2111
2112	/**
2113	* Ring-3 init finalizing.
2114	*
2115	* @returns VBox status code.
2116	* @param pVM Pointer to the VM.
2117	*/
2118	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2119	{
2120	int rc;
2121
2122	/*
2123	* Reserve space for the dynamic mappings.
2124	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2125	*/
2126	/* get the pointer to the page table entries. */
2127	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2128	AssertRelease(pMapping);
2129	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2130	const unsigned iPT = off >> X86_PD_SHIFT;
2131	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2132	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2133	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2134
2135	/* init cache area */
2136	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2137	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2138	{
2139	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2140	AssertRCReturn(rc, rc);
2141	}
2142
2143	/*
2144	* Determine the max physical address width (MAXPHYADDR) and apply it to
2145	* all the mask members and stuff.
2146	*/
2147	uint32_t cMaxPhysAddrWidth;
2148	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2149	if ( uMaxExtLeaf >= 0x80000008
2150	&& uMaxExtLeaf <= 0x80000fff)
2151	{
2152	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2153	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2154	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2155	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2156	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2157	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2158	}
2159	else
2160	{
2161	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2162	cMaxPhysAddrWidth = 48;
2163	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2164	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2165	}
2166
2167	pVM->pgm.s.GCPhysInvAddrMask = 0;
2168	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2169	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2170
2171	/*
2172	* Initialize the invalid paging entry masks, assuming NX is disabled.
2173	*/
2174	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2175	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2176	{
2177	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2178
2179	/** @todo The manuals are not entirely clear whether the physical
2180	* address width is relevant. See table 5-9 in the intel
2181	* manual vs the PDE4M descriptions. Write testcase (NP). */
2182	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2183	\| X86_PDE4M_MBZ_MASK;
2184
2185	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2186	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2187	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2188	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2189
2190	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2191	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2192	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2193	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2194	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2195	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2196
2197	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
2198	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
2199	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
2200	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2201	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
2202	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
2203	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
2204	}
2205
2206	/*
2207	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2208	* Intel only goes up to 36 bits, so we stick to 36 as well.
2209	* Update: More recent intel manuals specifies 40 bits just like AMD.
2210	*/
2211	uint32_t u32Dummy, u32Features;
2212	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2213	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2214	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2215	else
2216	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2217
2218	/*
2219	* Allocate memory if we're supposed to do that.
2220	*/
2221	if (pVM->pgm.s.fRamPreAlloc)
2222	rc = pgmR3PhysRamPreAllocate(pVM);
2223
2224	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2225	return rc;
2226	}
2227
2228
2229	/**
2230	* Init phase completed callback.
2231	*
2232	* @returns VBox status code.
2233	* @param pVM Pointer to the VM.
2234	* @param enmWhat What has been completed.
2235	* @thread EMT(0)
2236	*/
2237	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2238	{
2239	switch (enmWhat)
2240	{
2241	case VMINITCOMPLETED_HWACCM:
2242	#ifdef VBOX_WITH_PCI_PASSTHROUGH
2243	if (pVM->pgm.s.fPciPassthrough)
2244	{
2245	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2246	AssertLogRelReturn(HWACCMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HWACCM);
2247	AssertLogRelReturn(HWACCMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2248
2249	/*
2250	* Report assignments to the IOMMU (hope that's good enough for now).
2251	*/
2252	if (pVM->pgm.s.fPciPassthrough)
2253	{
2254	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2255	AssertRCReturn(rc, rc);
2256	}
2257	}
2258	#else
2259	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2260	#endif
2261	break;
2262
2263	default:
2264	/* shut up gcc */
2265	break;
2266	}
2267
2268	return VINF_SUCCESS;
2269	}
2270
2271
2272	/**
2273	* Applies relocations to data and code managed by this component.
2274	*
2275	* This function will be called at init and whenever the VMM need to relocate it
2276	* self inside the GC.
2277	*
2278	* @param pVM The VM.
2279	* @param offDelta Relocation delta relative to old location.
2280	*/
2281	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2282	{
2283	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2284
2285	/*
2286	* Paging stuff.
2287	*/
2288	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2289
2290	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2291
2292	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2293	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2294	{
2295	PVMCPU pVCpu = &pVM->aCpus[i];
2296
2297	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2298
2299	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2300	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2301	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2302	}
2303
2304	/*
2305	* Trees.
2306	*/
2307	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2308
2309	/*
2310	* Ram ranges.
2311	*/
2312	if (pVM->pgm.s.pRamRangesXR3)
2313	{
2314	/* Update the pSelfRC pointers and relink them. */
2315	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2316	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2317	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2318	pgmR3PhysRelinkRamRanges(pVM);
2319
2320	/* Flush the RC TLB. */
2321	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2322	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2323	}
2324
2325	/*
2326	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2327	* be mapped and thus not included in the above exercise.
2328	*/
2329	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2330	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2331	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2332
2333	/*
2334	* Update the two page directories with all page table mappings.
2335	* (One or more of them have changed, that's why we're here.)
2336	*/
2337	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2338	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2339	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2340
2341	/* Relocate GC addresses of Page Tables. */
2342	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2343	{
2344	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2345	{
2346	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2347	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2348	}
2349	}
2350
2351	/*
2352	* Dynamic page mapping area.
2353	*/
2354	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2355	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2356	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2357
2358	if (pVM->pgm.s.pRCDynMap)
2359	{
2360	pVM->pgm.s.pRCDynMap += offDelta;
2361	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2362
2363	pDynMap->paPages += offDelta;
2364	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2365
2366	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2367	{
2368	paPages[iPage].pvPage += offDelta;
2369	paPages[iPage].uPte.pLegacy += offDelta;
2370	paPages[iPage].uPte.pPae += offDelta;
2371	}
2372	}
2373
2374	/*
2375	* The Zero page.
2376	*/
2377	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2378	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2379	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2380	#else
2381	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2382	#endif
2383
2384	/*
2385	* Physical and virtual handlers.
2386	*/
2387	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2388	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2389	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2390	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2391
2392	/*
2393	* The page pool.
2394	*/
2395	pgmR3PoolRelocate(pVM);
2396
2397	#ifdef VBOX_WITH_STATISTICS
2398	/*
2399	* Statistics.
2400	*/
2401	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2402	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2403	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2404	#endif
2405	}
2406
2407
2408	/**
2409	* Callback function for relocating a physical access handler.
2410	*
2411	* @returns 0 (continue enum)
2412	* @param pNode Pointer to a PGMPHYSHANDLER node.
2413	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2414	* not certain the delta will fit in a void pointer for all possible configs.
2415	*/
2416	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2417	{
2418	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2419	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2420	if (pHandler->pfnHandlerRC)
2421	pHandler->pfnHandlerRC += offDelta;
2422	if (pHandler->pvUserRC >= 0x10000)
2423	pHandler->pvUserRC += offDelta;
2424	return 0;
2425	}
2426
2427
2428	/**
2429	* Callback function for relocating a virtual access handler.
2430	*
2431	* @returns 0 (continue enum)
2432	* @param pNode Pointer to a PGMVIRTHANDLER node.
2433	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2434	* not certain the delta will fit in a void pointer for all possible configs.
2435	*/
2436	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2437	{
2438	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2439	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2440	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2441	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2442	Assert(pHandler->pfnHandlerRC);
2443	pHandler->pfnHandlerRC += offDelta;
2444	return 0;
2445	}
2446
2447
2448	/**
2449	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2450	*
2451	* @returns 0 (continue enum)
2452	* @param pNode Pointer to a PGMVIRTHANDLER node.
2453	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2454	* not certain the delta will fit in a void pointer for all possible configs.
2455	*/
2456	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2457	{
2458	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2459	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2460	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2461	Assert(pHandler->pfnHandlerRC);
2462	pHandler->pfnHandlerRC += offDelta;
2463	return 0;
2464	}
2465
2466
2467	/**
2468	* Resets a virtual CPU when unplugged.
2469	*
2470	* @param pVM Pointer to the VM.
2471	* @param pVCpu The virtual CPU handle.
2472	*/
2473	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2474	{
2475	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2476	AssertRC(rc);
2477
2478	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2479	AssertRC(rc);
2480
2481	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2482
2483	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2484
2485	/*
2486	* Re-init other members.
2487	*/
2488	pVCpu->pgm.s.fA20Enabled = true;
2489
2490	/*
2491	* Clear the FFs PGM owns.
2492	*/
2493	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2494	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2495	}
2496
2497
2498	/**
2499	* The VM is being reset.
2500	*
2501	* For the PGM component this means that any PD write monitors
2502	* needs to be removed.
2503	*
2504	* @param pVM VM handle.
2505	*/
2506	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2507	{
2508	int rc;
2509
2510	LogFlow(("PGMR3Reset:\n"));
2511	VM_ASSERT_EMT(pVM);
2512
2513	pgmLock(pVM);
2514
2515	/*
2516	* Unfix any fixed mappings and disable CR3 monitoring.
2517	*/
2518	pVM->pgm.s.fMappingsFixed = false;
2519	pVM->pgm.s.fMappingsFixedRestored = false;
2520	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2521	pVM->pgm.s.cbMappingFixed = 0;
2522
2523	/*
2524	* Exit the guest paging mode before the pgm pool gets reset.
2525	* Important to clean up the amd64 case.
2526	*/
2527	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2528	{
2529	PVMCPU pVCpu = &pVM->aCpus[i];
2530	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2531	AssertRC(rc);
2532	}
2533
2534	#ifdef DEBUG
2535	DBGFR3InfoLog(pVM, "mappings", NULL);
2536	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2537	#endif
2538
2539	/*
2540	* Switch mode back to real mode. (before resetting the pgm pool!)
2541	*/
2542	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2543	{
2544	PVMCPU pVCpu = &pVM->aCpus[i];
2545
2546	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2547	AssertRC(rc);
2548
2549	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2550	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2551	}
2552
2553	/*
2554	* Reset the shadow page pool.
2555	*/
2556	pgmR3PoolReset(pVM);
2557
2558	/*
2559	* Re-init various other members and clear the FFs that PGM owns.
2560	*/
2561	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2562	{
2563	PVMCPU pVCpu = &pVM->aCpus[i];
2564
2565	pVCpu->pgm.s.fA20Enabled = true;
2566	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2567	PGMNotifyNxeChanged(pVCpu, false);
2568
2569	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2570	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2571	}
2572
2573	/*
2574	* Reset (zero) RAM and shadow ROM pages.
2575	*/
2576	rc = pgmR3PhysRamReset(pVM);
2577	if (RT_SUCCESS(rc))
2578	rc = pgmR3PhysRomReset(pVM);
2579
2580
2581	pgmUnlock(pVM);
2582	AssertReleaseRC(rc);
2583	}
2584
2585
2586	#ifdef VBOX_STRICT
2587	/**
2588	* VM state change callback for clearing fNoMorePhysWrites after
2589	* a snapshot has been created.
2590	*/
2591	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2592	{
2593	if ( enmState == VMSTATE_RUNNING
2594	\|\| enmState == VMSTATE_RESUMING)
2595	pVM->pgm.s.fNoMorePhysWrites = false;
2596	NOREF(enmOldState); NOREF(pvUser);
2597	}
2598	#endif
2599
2600	/**
2601	* Private API to reset fNoMorePhysWrites.
2602	*/
2603	VMMR3DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2604	{
2605	pVM->pgm.s.fNoMorePhysWrites = false;
2606	}
2607
2608	/**
2609	* Terminates the PGM.
2610	*
2611	* @returns VBox status code.
2612	* @param pVM Pointer to VM structure.
2613	*/
2614	VMMR3DECL(int) PGMR3Term(PVM pVM)
2615	{
2616	/* Must free shared pages here. */
2617	pgmLock(pVM);
2618	pgmR3PhysRamTerm(pVM);
2619	pgmR3PhysRomTerm(pVM);
2620	pgmUnlock(pVM);
2621
2622	PGMDeregisterStringFormatTypes();
2623	return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2624	}
2625
2626
2627	/**
2628	* Show paging mode.
2629	*
2630	* @param pVM VM Handle.
2631	* @param pHlp The info helpers.
2632	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2633	*/
2634	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2635	{
2636	/* digest argument. */
2637	bool fGuest, fShadow, fHost;
2638	if (pszArgs)
2639	pszArgs = RTStrStripL(pszArgs);
2640	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2641	fShadow = fHost = fGuest = true;
2642	else
2643	{
2644	fShadow = fHost = fGuest = false;
2645	if (strstr(pszArgs, "guest"))
2646	fGuest = true;
2647	if (strstr(pszArgs, "shadow"))
2648	fShadow = true;
2649	if (strstr(pszArgs, "host"))
2650	fHost = true;
2651	}
2652
2653	/** @todo SMP support! */
2654	/* print info. */
2655	if (fGuest)
2656	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2657	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2658	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled", pVM->aCpus[0].pgm.s.cA20Changes.c);
2659	if (fShadow)
2660	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2661	if (fHost)
2662	{
2663	const char *psz;
2664	switch (pVM->pgm.s.enmHostMode)
2665	{
2666	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2667	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2668	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2669	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2670	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2671	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2672	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2673	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2674	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2675	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2676	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2677	default: psz = "unknown"; break;
2678	}
2679	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2680	}
2681	}
2682
2683
2684	/**
2685	* Dump registered MMIO ranges to the log.
2686	*
2687	* @param pVM VM Handle.
2688	* @param pHlp The info helpers.
2689	* @param pszArgs Arguments, ignored.
2690	*/
2691	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2692	{
2693	NOREF(pszArgs);
2694	pHlp->pfnPrintf(pHlp,
2695	"RAM ranges (pVM=%p)\n"
2696	"%.s %.s\n",
2697	pVM,
2698	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2699	sizeof(RTHCPTR) * 2, "pvHC ");
2700
2701	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2702	pHlp->pfnPrintf(pHlp,
2703	"%RGp-%RGp %RHv %s\n",
2704	pCur->GCPhys,
2705	pCur->GCPhysLast,
2706	pCur->pvR3,
2707	pCur->pszDesc);
2708	}
2709
2710	/**
2711	* Dump the page directory to the log.
2712	*
2713	* @param pVM VM Handle.
2714	* @param pHlp The info helpers.
2715	* @param pszArgs Arguments, ignored.
2716	*/
2717	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2718	{
2719	/** @todo SMP support!! */
2720	PVMCPU pVCpu = &pVM->aCpus[0];
2721
2722	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2723	/* Big pages supported? */
2724	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2725
2726	/* Global pages supported? */
2727	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2728
2729	NOREF(pszArgs);
2730
2731	/*
2732	* Get page directory addresses.
2733	*/
2734	pgmLock(pVM);
2735	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2736	Assert(pPDSrc);
2737
2738	/*
2739	* Iterate the page directory.
2740	*/
2741	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2742	{
2743	X86PDE PdeSrc = pPDSrc->a[iPD];
2744	if (PdeSrc.n.u1Present)
2745	{
2746	if (PdeSrc.b.u1Size && fPSE)
2747	pHlp->pfnPrintf(pHlp,
2748	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2749	iPD,
2750	pgmGstGet4MBPhysPage(pVM, PdeSrc),
2751	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2752	else
2753	pHlp->pfnPrintf(pHlp,
2754	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2755	iPD,
2756	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2757	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2758	}
2759	}
2760	pgmUnlock(pVM);
2761	}
2762
2763
2764	/**
2765	* Service a VMMCALLRING3_PGM_LOCK call.
2766	*
2767	* @returns VBox status code.
2768	* @param pVM Pointer to the VM.
2769	*/
2770	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2771	{
2772	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2773	AssertRC(rc);
2774	return rc;
2775	}
2776
2777
2778	/**
2779	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2780	*
2781	* @returns PGM_TYPE_*.
2782	* @param pgmMode The mode value to convert.
2783	*/
2784	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2785	{
2786	switch (pgmMode)
2787	{
2788	case PGMMODE_REAL: return PGM_TYPE_REAL;
2789	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2790	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2791	case PGMMODE_PAE:
2792	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2793	case PGMMODE_AMD64:
2794	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2795	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2796	case PGMMODE_EPT: return PGM_TYPE_EPT;
2797	default:
2798	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2799	}
2800	}
2801
2802
2803	/**
2804	* Gets the index into the paging mode data array of a SHW+GST mode.
2805	*
2806	* @returns PGM::paPagingData index.
2807	* @param uShwType The shadow paging mode type.
2808	* @param uGstType The guest paging mode type.
2809	*/
2810	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2811	{
2812	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2813	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2814	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2815	+ (uGstType - PGM_TYPE_REAL);
2816	}
2817
2818
2819	/**
2820	* Gets the index into the paging mode data array of a SHW+GST mode.
2821	*
2822	* @returns PGM::paPagingData index.
2823	* @param enmShw The shadow paging mode.
2824	* @param enmGst The guest paging mode.
2825	*/
2826	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2827	{
2828	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2829	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2830	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2831	}
2832
2833
2834	/**
2835	* Calculates the max data index.
2836	* @returns The number of entries in the paging data array.
2837	*/
2838	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2839	{
2840	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2841	}
2842
2843
2844	/**
2845	* Initializes the paging mode data kept in PGM::paModeData.
2846	*
2847	* @param pVM Pointer to the VM.
2848	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2849	* This is used early in the init process to avoid trouble with PDM
2850	* not being initialized yet.
2851	*/
2852	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2853	{
2854	PPGMMODEDATA pModeData;
2855	int rc;
2856
2857	/*
2858	* Allocate the array on the first call.
2859	*/
2860	if (!pVM->pgm.s.paModeData)
2861	{
2862	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2863	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2864	}
2865
2866	/*
2867	* Initialize the array entries.
2868	*/
2869	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2870	pModeData->uShwType = PGM_TYPE_32BIT;
2871	pModeData->uGstType = PGM_TYPE_REAL;
2872	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2873	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2874	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2875
2876	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2877	pModeData->uShwType = PGM_TYPE_32BIT;
2878	pModeData->uGstType = PGM_TYPE_PROT;
2879	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2880	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2881	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2882
2883	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2884	pModeData->uShwType = PGM_TYPE_32BIT;
2885	pModeData->uGstType = PGM_TYPE_32BIT;
2886	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2887	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2888	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2889
2890	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2891	pModeData->uShwType = PGM_TYPE_PAE;
2892	pModeData->uGstType = PGM_TYPE_REAL;
2893	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2894	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896
2897	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2898	pModeData->uShwType = PGM_TYPE_PAE;
2899	pModeData->uGstType = PGM_TYPE_PROT;
2900	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903
2904	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2905	pModeData->uShwType = PGM_TYPE_PAE;
2906	pModeData->uGstType = PGM_TYPE_32BIT;
2907	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2908	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2909	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910
2911	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2912	pModeData->uShwType = PGM_TYPE_PAE;
2913	pModeData->uGstType = PGM_TYPE_PAE;
2914	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2915	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2916	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917
2918	#ifdef VBOX_WITH_64_BITS_GUESTS
2919	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2920	pModeData->uShwType = PGM_TYPE_AMD64;
2921	pModeData->uGstType = PGM_TYPE_AMD64;
2922	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2923	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2924	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2925	#endif
2926
2927	/* The nested paging mode. */
2928	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2929	pModeData->uShwType = PGM_TYPE_NESTED;
2930	pModeData->uGstType = PGM_TYPE_REAL;
2931	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2932	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2933
2934	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2935	pModeData->uShwType = PGM_TYPE_NESTED;
2936	pModeData->uGstType = PGM_TYPE_PROT;
2937	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2938	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2939
2940	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2941	pModeData->uShwType = PGM_TYPE_NESTED;
2942	pModeData->uGstType = PGM_TYPE_32BIT;
2943	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2944	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2945
2946	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2947	pModeData->uShwType = PGM_TYPE_NESTED;
2948	pModeData->uGstType = PGM_TYPE_PAE;
2949	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2950	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2951
2952	#ifdef VBOX_WITH_64_BITS_GUESTS
2953	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2954	pModeData->uShwType = PGM_TYPE_NESTED;
2955	pModeData->uGstType = PGM_TYPE_AMD64;
2956	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2957	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2958	#endif
2959
2960	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2961	switch (pVM->pgm.s.enmHostMode)
2962	{
2963	#if HC_ARCH_BITS == 32
2964	case SUPPAGINGMODE_32_BIT:
2965	case SUPPAGINGMODE_32_BIT_GLOBAL:
2966	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2967	{
2968	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2969	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2970	}
2971	# ifdef VBOX_WITH_64_BITS_GUESTS
2972	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2973	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2974	# endif
2975	break;
2976
2977	case SUPPAGINGMODE_PAE:
2978	case SUPPAGINGMODE_PAE_NX:
2979	case SUPPAGINGMODE_PAE_GLOBAL:
2980	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2981	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2982	{
2983	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2984	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2985	}
2986	# ifdef VBOX_WITH_64_BITS_GUESTS
2987	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2988	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2989	# endif
2990	break;
2991	#endif /* HC_ARCH_BITS == 32 */
2992
2993	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2994	case SUPPAGINGMODE_AMD64:
2995	case SUPPAGINGMODE_AMD64_GLOBAL:
2996	case SUPPAGINGMODE_AMD64_NX:
2997	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2998	# ifdef VBOX_WITH_64_BITS_GUESTS
2999	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3000	# else
3001	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3002	# endif
3003	{
3004	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3005	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3006	}
3007	break;
3008	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3009
3010	default:
3011	AssertFailed();
3012	break;
3013	}
3014
3015	/* Extended paging (EPT) / Intel VT-x */
3016	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3017	pModeData->uShwType = PGM_TYPE_EPT;
3018	pModeData->uGstType = PGM_TYPE_REAL;
3019	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3020	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3021	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3022
3023	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3024	pModeData->uShwType = PGM_TYPE_EPT;
3025	pModeData->uGstType = PGM_TYPE_PROT;
3026	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3027	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3028	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3029
3030	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3031	pModeData->uShwType = PGM_TYPE_EPT;
3032	pModeData->uGstType = PGM_TYPE_32BIT;
3033	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3034	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3035	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3036
3037	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3038	pModeData->uShwType = PGM_TYPE_EPT;
3039	pModeData->uGstType = PGM_TYPE_PAE;
3040	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3041	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3042	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3043
3044	#ifdef VBOX_WITH_64_BITS_GUESTS
3045	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3046	pModeData->uShwType = PGM_TYPE_EPT;
3047	pModeData->uGstType = PGM_TYPE_AMD64;
3048	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3049	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3050	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3051	#endif
3052	return VINF_SUCCESS;
3053	}
3054
3055
3056	/**
3057	* Switch to different (or relocated in the relocate case) mode data.
3058	*
3059	* @param pVM Pointer to the VM.
3060	* @param pVCpu The VMCPU to operate on.
3061	* @param enmShw The shadow paging mode.
3062	* @param enmGst The guest paging mode.
3063	*/
3064	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3065	{
3066	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3067
3068	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3069	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3070
3071	/* shadow */
3072	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3073	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3074	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3075	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3076	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3077
3078	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3079	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3080
3081	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3082	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3083
3084
3085	/* guest */
3086	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3087	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3088	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3089	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3090	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3091	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3092	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3093	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3094	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3095	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3096	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3097	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3098
3099	/* both */
3100	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3101	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3102	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3103	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3104	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3105	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3106	#ifdef VBOX_STRICT
3107	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3108	#endif
3109	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3110	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3111
3112	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3113	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3114	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3115	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3116	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3117	#ifdef VBOX_STRICT
3118	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3119	#endif
3120	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3121	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3122
3123	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3124	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3125	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3126	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3127	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3128	#ifdef VBOX_STRICT
3129	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3130	#endif
3131	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3132	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3133	}
3134
3135
3136	/**
3137	* Calculates the shadow paging mode.
3138	*
3139	* @returns The shadow paging mode.
3140	* @param pVM VM handle.
3141	* @param enmGuestMode The guest mode.
3142	* @param enmHostMode The host mode.
3143	* @param enmShadowMode The current shadow mode.
3144	* @param penmSwitcher Where to store the switcher to use.
3145	* VMMSWITCHER_INVALID means no change.
3146	*/
3147	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3148	{
3149	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3150	switch (enmGuestMode)
3151	{
3152	/*
3153	* When switching to real or protected mode we don't change
3154	* anything since it's likely that we'll switch back pretty soon.
3155	*
3156	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3157	* and is supposed to determine which shadow paging and switcher to
3158	* use during init.
3159	*/
3160	case PGMMODE_REAL:
3161	case PGMMODE_PROTECTED:
3162	if ( enmShadowMode != PGMMODE_INVALID
3163	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3164	break; /* (no change) */
3165
3166	switch (enmHostMode)
3167	{
3168	case SUPPAGINGMODE_32_BIT:
3169	case SUPPAGINGMODE_32_BIT_GLOBAL:
3170	enmShadowMode = PGMMODE_32_BIT;
3171	enmSwitcher = VMMSWITCHER_32_TO_32;
3172	break;
3173
3174	case SUPPAGINGMODE_PAE:
3175	case SUPPAGINGMODE_PAE_NX:
3176	case SUPPAGINGMODE_PAE_GLOBAL:
3177	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3178	enmShadowMode = PGMMODE_PAE;
3179	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3180	#ifdef DEBUG_bird
3181	if (RTEnvExist("VBOX_32BIT"))
3182	{
3183	enmShadowMode = PGMMODE_32_BIT;
3184	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3185	}
3186	#endif
3187	break;
3188
3189	case SUPPAGINGMODE_AMD64:
3190	case SUPPAGINGMODE_AMD64_GLOBAL:
3191	case SUPPAGINGMODE_AMD64_NX:
3192	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3193	enmShadowMode = PGMMODE_PAE;
3194	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3195	#ifdef DEBUG_bird
3196	if (RTEnvExist("VBOX_32BIT"))
3197	{
3198	enmShadowMode = PGMMODE_32_BIT;
3199	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3200	}
3201	#endif
3202	break;
3203
3204	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3205	}
3206	break;
3207
3208	case PGMMODE_32_BIT:
3209	switch (enmHostMode)
3210	{
3211	case SUPPAGINGMODE_32_BIT:
3212	case SUPPAGINGMODE_32_BIT_GLOBAL:
3213	enmShadowMode = PGMMODE_32_BIT;
3214	enmSwitcher = VMMSWITCHER_32_TO_32;
3215	break;
3216
3217	case SUPPAGINGMODE_PAE:
3218	case SUPPAGINGMODE_PAE_NX:
3219	case SUPPAGINGMODE_PAE_GLOBAL:
3220	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3221	enmShadowMode = PGMMODE_PAE;
3222	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3223	#ifdef DEBUG_bird
3224	if (RTEnvExist("VBOX_32BIT"))
3225	{
3226	enmShadowMode = PGMMODE_32_BIT;
3227	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3228	}
3229	#endif
3230	break;
3231
3232	case SUPPAGINGMODE_AMD64:
3233	case SUPPAGINGMODE_AMD64_GLOBAL:
3234	case SUPPAGINGMODE_AMD64_NX:
3235	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3236	enmShadowMode = PGMMODE_PAE;
3237	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3238	#ifdef DEBUG_bird
3239	if (RTEnvExist("VBOX_32BIT"))
3240	{
3241	enmShadowMode = PGMMODE_32_BIT;
3242	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3243	}
3244	#endif
3245	break;
3246
3247	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3248	}
3249	break;
3250
3251	case PGMMODE_PAE:
3252	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3253	switch (enmHostMode)
3254	{
3255	case SUPPAGINGMODE_32_BIT:
3256	case SUPPAGINGMODE_32_BIT_GLOBAL:
3257	enmShadowMode = PGMMODE_PAE;
3258	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3259	break;
3260
3261	case SUPPAGINGMODE_PAE:
3262	case SUPPAGINGMODE_PAE_NX:
3263	case SUPPAGINGMODE_PAE_GLOBAL:
3264	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3265	enmShadowMode = PGMMODE_PAE;
3266	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3267	break;
3268
3269	case SUPPAGINGMODE_AMD64:
3270	case SUPPAGINGMODE_AMD64_GLOBAL:
3271	case SUPPAGINGMODE_AMD64_NX:
3272	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3273	enmShadowMode = PGMMODE_PAE;
3274	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3275	break;
3276
3277	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3278	}
3279	break;
3280
3281	case PGMMODE_AMD64:
3282	case PGMMODE_AMD64_NX:
3283	switch (enmHostMode)
3284	{
3285	case SUPPAGINGMODE_32_BIT:
3286	case SUPPAGINGMODE_32_BIT_GLOBAL:
3287	enmShadowMode = PGMMODE_AMD64;
3288	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3289	break;
3290
3291	case SUPPAGINGMODE_PAE:
3292	case SUPPAGINGMODE_PAE_NX:
3293	case SUPPAGINGMODE_PAE_GLOBAL:
3294	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3295	enmShadowMode = PGMMODE_AMD64;
3296	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3297	break;
3298
3299	case SUPPAGINGMODE_AMD64:
3300	case SUPPAGINGMODE_AMD64_GLOBAL:
3301	case SUPPAGINGMODE_AMD64_NX:
3302	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3303	enmShadowMode = PGMMODE_AMD64;
3304	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3305	break;
3306
3307	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3308	}
3309	break;
3310
3311
3312	default:
3313	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3314	*penmSwitcher = VMMSWITCHER_INVALID;
3315	return PGMMODE_INVALID;
3316	}
3317	/* Override the shadow mode is nested paging is active. */
3318	pVM->pgm.s.fNestedPaging = HWACCMIsNestedPagingActive(pVM);
3319	if (pVM->pgm.s.fNestedPaging)
3320	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3321
3322	*penmSwitcher = enmSwitcher;
3323	return enmShadowMode;
3324	}
3325
3326
3327	/**
3328	* Performs the actual mode change.
3329	* This is called by PGMChangeMode and pgmR3InitPaging().
3330	*
3331	* @returns VBox status code. May suspend or power off the VM on error, but this
3332	* will trigger using FFs and not status codes.
3333	*
3334	* @param pVM VM handle.
3335	* @param pVCpu The VMCPU to operate on.
3336	* @param enmGuestMode The new guest mode. This is assumed to be different from
3337	* the current mode.
3338	*/
3339	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3340	{
3341	#if HC_ARCH_BITS == 32
3342	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3343	#endif
3344	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3345
3346	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3347	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3348
3349	/*
3350	* Calc the shadow mode and switcher.
3351	*/
3352	VMMSWITCHER enmSwitcher;
3353	PGMMODE enmShadowMode;
3354	enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3355
3356	#ifdef VBOX_WITH_RAW_MODE
3357	if (enmSwitcher != VMMSWITCHER_INVALID)
3358	{
3359	/*
3360	* Select new switcher.
3361	*/
3362	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3363	if (RT_FAILURE(rc))
3364	{
3365	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3366	return rc;
3367	}
3368	}
3369	#endif
3370
3371	/*
3372	* Exit old mode(s).
3373	*/
3374	#if HC_ARCH_BITS == 32
3375	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3376	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3377	&& enmShadowMode == PGMMODE_NESTED);
3378	#else
3379	const bool fForceShwEnterExit = false;
3380	#endif
3381	/* shadow */
3382	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3383	\|\| fForceShwEnterExit)
3384	{
3385	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3386	if (PGM_SHW_PFN(Exit, pVCpu))
3387	{
3388	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3389	if (RT_FAILURE(rc))
3390	{
3391	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3392	return rc;
3393	}
3394	}
3395
3396	}
3397	else
3398	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3399
3400	/* guest */
3401	if (PGM_GST_PFN(Exit, pVCpu))
3402	{
3403	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3404	if (RT_FAILURE(rc))
3405	{
3406	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3407	return rc;
3408	}
3409	}
3410
3411	/*
3412	* Load new paging mode data.
3413	*/
3414	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3415
3416	/*
3417	* Enter new shadow mode (if changed).
3418	*/
3419	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3420	\|\| fForceShwEnterExit)
3421	{
3422	int rc;
3423	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3424	switch (enmShadowMode)
3425	{
3426	case PGMMODE_32_BIT:
3427	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3428	break;
3429	case PGMMODE_PAE:
3430	case PGMMODE_PAE_NX:
3431	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3432	break;
3433	case PGMMODE_AMD64:
3434	case PGMMODE_AMD64_NX:
3435	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3436	break;
3437	case PGMMODE_NESTED:
3438	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3439	break;
3440	case PGMMODE_EPT:
3441	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3442	break;
3443	case PGMMODE_REAL:
3444	case PGMMODE_PROTECTED:
3445	default:
3446	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3447	return VERR_INTERNAL_ERROR;
3448	}
3449	if (RT_FAILURE(rc))
3450	{
3451	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3452	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3453	return rc;
3454	}
3455	}
3456
3457	/*
3458	* Always flag the necessary updates
3459	*/
3460	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3461
3462	/*
3463	* Enter the new guest and shadow+guest modes.
3464	*/
3465	int rc = -1;
3466	int rc2 = -1;
3467	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3468	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3469	switch (enmGuestMode)
3470	{
3471	case PGMMODE_REAL:
3472	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3473	switch (pVCpu->pgm.s.enmShadowMode)
3474	{
3475	case PGMMODE_32_BIT:
3476	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3477	break;
3478	case PGMMODE_PAE:
3479	case PGMMODE_PAE_NX:
3480	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3481	break;
3482	case PGMMODE_NESTED:
3483	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3484	break;
3485	case PGMMODE_EPT:
3486	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3487	break;
3488	case PGMMODE_AMD64:
3489	case PGMMODE_AMD64_NX:
3490	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3491	default: AssertFailed(); break;
3492	}
3493	break;
3494
3495	case PGMMODE_PROTECTED:
3496	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3497	switch (pVCpu->pgm.s.enmShadowMode)
3498	{
3499	case PGMMODE_32_BIT:
3500	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3501	break;
3502	case PGMMODE_PAE:
3503	case PGMMODE_PAE_NX:
3504	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3505	break;
3506	case PGMMODE_NESTED:
3507	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3508	break;
3509	case PGMMODE_EPT:
3510	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3511	break;
3512	case PGMMODE_AMD64:
3513	case PGMMODE_AMD64_NX:
3514	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3515	default: AssertFailed(); break;
3516	}
3517	break;
3518
3519	case PGMMODE_32_BIT:
3520	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3521	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3522	switch (pVCpu->pgm.s.enmShadowMode)
3523	{
3524	case PGMMODE_32_BIT:
3525	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3526	break;
3527	case PGMMODE_PAE:
3528	case PGMMODE_PAE_NX:
3529	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3530	break;
3531	case PGMMODE_NESTED:
3532	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3533	break;
3534	case PGMMODE_EPT:
3535	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3536	break;
3537	case PGMMODE_AMD64:
3538	case PGMMODE_AMD64_NX:
3539	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3540	default: AssertFailed(); break;
3541	}
3542	break;
3543
3544	case PGMMODE_PAE_NX:
3545	case PGMMODE_PAE:
3546	{
3547	uint32_t u32Dummy, u32Features;
3548
3549	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3550	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3551	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3552	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3553
3554	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3555	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3556	switch (pVCpu->pgm.s.enmShadowMode)
3557	{
3558	case PGMMODE_PAE:
3559	case PGMMODE_PAE_NX:
3560	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3561	break;
3562	case PGMMODE_NESTED:
3563	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3564	break;
3565	case PGMMODE_EPT:
3566	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3567	break;
3568	case PGMMODE_32_BIT:
3569	case PGMMODE_AMD64:
3570	case PGMMODE_AMD64_NX:
3571	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3572	default: AssertFailed(); break;
3573	}
3574	break;
3575	}
3576
3577	#ifdef VBOX_WITH_64_BITS_GUESTS
3578	case PGMMODE_AMD64_NX:
3579	case PGMMODE_AMD64:
3580	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3581	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3582	switch (pVCpu->pgm.s.enmShadowMode)
3583	{
3584	case PGMMODE_AMD64:
3585	case PGMMODE_AMD64_NX:
3586	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3587	break;
3588	case PGMMODE_NESTED:
3589	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3590	break;
3591	case PGMMODE_EPT:
3592	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3593	break;
3594	case PGMMODE_32_BIT:
3595	case PGMMODE_PAE:
3596	case PGMMODE_PAE_NX:
3597	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3598	default: AssertFailed(); break;
3599	}
3600	break;
3601	#endif
3602
3603	default:
3604	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3605	rc = VERR_NOT_IMPLEMENTED;
3606	break;
3607	}
3608
3609	/* status codes. */
3610	AssertRC(rc);
3611	AssertRC(rc2);
3612	if (RT_SUCCESS(rc))
3613	{
3614	rc = rc2;
3615	if (RT_SUCCESS(rc)) /* no informational status codes. */
3616	rc = VINF_SUCCESS;
3617	}
3618
3619	/* Notify HWACCM as well. */
3620	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3621	return rc;
3622	}
3623
3624
3625	/**
3626	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3627	*
3628	* @returns VBox status code, fully asserted.
3629	* @param pVCpu The VMCPU to operate on.
3630	*/
3631	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3632	{
3633	/* Unmap the old CR3 value before flushing everything. */
3634	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3635	AssertRC(rc);
3636
3637	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3638	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3639	AssertRC(rc);
3640	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3641	return rc;
3642	}
3643
3644
3645	/**
3646	* Called by pgmPoolFlushAllInt after flushing the pool.
3647	*
3648	* @returns VBox status code, fully asserted.
3649	* @param pVM Pointer to the VM.
3650	* @param pVCpu The VMCPU to operate on.
3651	*/
3652	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3653	{
3654	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3655	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3656	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3657	AssertRCReturn(rc, rc);
3658	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3659
3660	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3661	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3662	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3663	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3664	return rc;
3665	}
3666
3667
3668	/**
3669	* Called by PGMR3PhysSetA20 after changing the A20 state.
3670	*
3671	* @param pVCpu The VMCPU to operate on.
3672	*/
3673	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
3674	{
3675	/** @todo Probably doing a bit too much here. */
3676	int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
3677	AssertReleaseRC(rc);
3678	rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
3679	AssertReleaseRC(rc);
3680	}
3681
3682
3683	#ifdef VBOX_WITH_DEBUGGER
3684
3685	/**
3686	* The '.pgmram' command.
3687	*
3688	* @returns VBox status.
3689	* @param pCmd Pointer to the command descriptor (as registered).
3690	* @param pCmdHlp Pointer to command helper functions.
3691	* @param pVM Pointer to the current VM (if any).
3692	* @param paArgs Pointer to (readonly) array of arguments.
3693	* @param cArgs Number of arguments in the array.
3694	*/
3695	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3696	{
3697	/*
3698	* Validate input.
3699	*/
3700	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3701	if (!pVM)
3702	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3703	if (!pVM->pgm.s.pRamRangesXR3)
3704	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3705
3706	/*
3707	* Dump the ranges.
3708	*/
3709	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3710	PPGMRAMRANGE pRam;
3711	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
3712	{
3713	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3714	"%RGp - %RGp %p\n",
3715	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
3716	if (RT_FAILURE(rc))
3717	return rc;
3718	}
3719
3720	return VINF_SUCCESS;
3721	}
3722
3723
3724	/**
3725	* The '.pgmerror' and '.pgmerroroff' commands.
3726	*
3727	* @returns VBox status.
3728	* @param pCmd Pointer to the command descriptor (as registered).
3729	* @param pCmdHlp Pointer to command helper functions.
3730	* @param pVM Pointer to the current VM (if any).
3731	* @param paArgs Pointer to (readonly) array of arguments.
3732	* @param cArgs Number of arguments in the array.
3733	*/
3734	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3735	{
3736	/*
3737	* Validate input.
3738	*/
3739	if (!pVM)
3740	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3741	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
3742	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
3743
3744	if (!cArgs)
3745	{
3746	/*
3747	* Print the list of error injection locations with status.
3748	*/
3749	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
3750	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3751	}
3752	else
3753	{
3754
3755	/*
3756	* String switch on where to inject the error.
3757	*/
3758	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
3759	const char *pszWhere = paArgs[0].u.pszString;
3760	if (!strcmp(pszWhere, "handy"))
3761	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
3762	else
3763	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
3764	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
3765	}
3766	return VINF_SUCCESS;
3767	}
3768
3769
3770	/**
3771	* The '.pgmsync' command.
3772	*
3773	* @returns VBox status.
3774	* @param pCmd Pointer to the command descriptor (as registered).
3775	* @param pCmdHlp Pointer to command helper functions.
3776	* @param pVM Pointer to the current VM (if any).
3777	* @param paArgs Pointer to (readonly) array of arguments.
3778	* @param cArgs Number of arguments in the array.
3779	*/
3780	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3781	{
3782	/** @todo SMP support */
3783
3784	/*
3785	* Validate input.
3786	*/
3787	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3788	if (!pVM)
3789	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3790
3791	PVMCPU pVCpu = &pVM->aCpus[0];
3792
3793	/*
3794	* Force page directory sync.
3795	*/
3796	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3797
3798	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3799	if (RT_FAILURE(rc))
3800	return rc;
3801
3802	return VINF_SUCCESS;
3803	}
3804
3805
3806	#ifdef VBOX_STRICT
3807	/**
3808	* The '.pgmassertcr3' command.
3809	*
3810	* @returns VBox status.
3811	* @param pCmd Pointer to the command descriptor (as registered).
3812	* @param pCmdHlp Pointer to command helper functions.
3813	* @param pVM Pointer to the current VM (if any).
3814	* @param paArgs Pointer to (readonly) array of arguments.
3815	* @param cArgs Number of arguments in the array.
3816	*/
3817	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3818	{
3819	/** @todo SMP support!! */
3820
3821	/*
3822	* Validate input.
3823	*/
3824	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3825	if (!pVM)
3826	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3827
3828	PVMCPU pVCpu = &pVM->aCpus[0];
3829
3830	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
3831	if (RT_FAILURE(rc))
3832	return rc;
3833
3834	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
3835
3836	return VINF_SUCCESS;
3837	}
3838	#endif /* VBOX_STRICT */
3839
3840
3841	/**
3842	* The '.pgmsyncalways' command.
3843	*
3844	* @returns VBox status.
3845	* @param pCmd Pointer to the command descriptor (as registered).
3846	* @param pCmdHlp Pointer to command helper functions.
3847	* @param pVM Pointer to the current VM (if any).
3848	* @param paArgs Pointer to (readonly) array of arguments.
3849	* @param cArgs Number of arguments in the array.
3850	*/
3851	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3852	{
3853	/** @todo SMP support!! */
3854	PVMCPU pVCpu = &pVM->aCpus[0];
3855
3856	/*
3857	* Validate input.
3858	*/
3859	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3860	if (!pVM)
3861	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3862
3863	/*
3864	* Force page directory sync.
3865	*/
3866	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3867	{
3868	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3869	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3870	}
3871	else
3872	{
3873	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3874	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3875	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3876	}
3877	}
3878
3879
3880	/**
3881	* The '.pgmphystofile' command.
3882	*
3883	* @returns VBox status.
3884	* @param pCmd Pointer to the command descriptor (as registered).
3885	* @param pCmdHlp Pointer to command helper functions.
3886	* @param pVM Pointer to the current VM (if any).
3887	* @param paArgs Pointer to (readonly) array of arguments.
3888	* @param cArgs Number of arguments in the array.
3889	*/
3890	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs)
3891	{
3892	/*
3893	* Validate input.
3894	*/
3895	NOREF(pCmd);
3896	if (!pVM)
3897	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3898	if ( cArgs < 1
3899	\|\| cArgs > 2
3900	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
3901	\|\| ( cArgs > 1
3902	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
3903	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
3904	if ( cArgs >= 2
3905	&& strcmp(paArgs[1].u.pszString, "nozero"))
3906	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
3907	bool fIncZeroPgs = cArgs < 2;
3908
3909	/*
3910	* Open the output file and get the ram parameters.
3911	*/
3912	RTFILE hFile;
3913	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
3914	if (RT_FAILURE(rc))
3915	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
3916
3917	uint32_t cbRamHole = 0;
3918	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
3919	uint64_t cbRam = 0;
3920	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
3921	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
3922
3923	/*
3924	* Dump the physical memory, page by page.
3925	*/
3926	RTGCPHYS GCPhys = 0;
3927	char abZeroPg[PAGE_SIZE];
3928	RT_ZERO(abZeroPg);
3929
3930	pgmLock(pVM);
3931	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3932	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
3933	pRam = pRam->pNextR3)
3934	{
3935	/* fill the gap */
3936	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
3937	{
3938	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
3939	{
3940	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3941	GCPhys += PAGE_SIZE;
3942	}
3943	}
3944
3945	PCPGMPAGE pPage = &pRam->aPages[0];
3946	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
3947	{
3948	if ( PGM_PAGE_IS_ZERO(pPage)
3949	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3950	{
3951	if (fIncZeroPgs)
3952	{
3953	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3954	if (RT_FAILURE(rc))
3955	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3956	}
3957	}
3958	else
3959	{
3960	switch (PGM_PAGE_GET_TYPE(pPage))
3961	{
3962	case PGMPAGETYPE_RAM:
3963	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
3964	case PGMPAGETYPE_ROM:
3965	case PGMPAGETYPE_MMIO2:
3966	{
3967	void const *pvPage;
3968	PGMPAGEMAPLOCK Lock;
3969	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
3970	if (RT_SUCCESS(rc))
3971	{
3972	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
3973	PGMPhysReleasePageMappingLock(pVM, &Lock);
3974	if (RT_FAILURE(rc))
3975	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3976	}
3977	else
3978	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3979	break;
3980	}
3981
3982	default:
3983	AssertFailed();
3984	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3985	case PGMPAGETYPE_MMIO:
3986	if (fIncZeroPgs)
3987	{
3988	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3989	if (RT_FAILURE(rc))
3990	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3991	}
3992	break;
3993	}
3994	}
3995
3996
3997	/* advance */
3998	GCPhys += PAGE_SIZE;
3999	pPage++;
4000	}
4001	}
4002	pgmUnlock(pVM);
4003
4004	RTFileClose(hFile);
4005	if (RT_SUCCESS(rc))
4006	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4007	return VINF_SUCCESS;
4008	}
4009
4010	#endif /* VBOX_WITH_DEBUGGER */
4011
4012	/**
4013	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4014	*/
4015	typedef struct PGMCHECKINTARGS
4016	{
4017	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4018	PPGMPHYSHANDLER pPrevPhys;
4019	PPGMVIRTHANDLER pPrevVirt;
4020	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4021	PVM pVM;
4022	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4023
4024	/**
4025	* Validate a node in the physical handler tree.
4026	*
4027	* @returns 0 on if ok, other wise 1.
4028	* @param pNode The handler node.
4029	* @param pvUser pVM.
4030	*/
4031	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4032	{
4033	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4034	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4035	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4036	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4037	AssertReleaseMsg( !pArgs->pPrevPhys
4038	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4039	("pPrevPhys=%p %RGp-%RGp %s\n"
4040	" pCur=%p %RGp-%RGp %s\n",
4041	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4042	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4043	pArgs->pPrevPhys = pCur;
4044	return 0;
4045	}
4046
4047
4048	/**
4049	* Validate a node in the virtual handler tree.
4050	*
4051	* @returns 0 on if ok, other wise 1.
4052	* @param pNode The handler node.
4053	* @param pvUser pVM.
4054	*/
4055	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4056	{
4057	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4058	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4059	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4060	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4061	AssertReleaseMsg( !pArgs->pPrevVirt
4062	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4063	("pPrevVirt=%p %RGv-%RGv %s\n"
4064	" pCur=%p %RGv-%RGv %s\n",
4065	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4066	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4067	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4068	{
4069	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4070	("pCur=%p %RGv-%RGv %s\n"
4071	"iPage=%d offVirtHandle=%#x expected %#x\n",
4072	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4073	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4074	}
4075	pArgs->pPrevVirt = pCur;
4076	return 0;
4077	}
4078
4079
4080	/**
4081	* Validate a node in the virtual handler tree.
4082	*
4083	* @returns 0 on if ok, other wise 1.
4084	* @param pNode The handler node.
4085	* @param pvUser pVM.
4086	*/
4087	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4088	{
4089	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4090	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4091	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4092	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4093	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4094	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4095	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4096	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4097	" pCur=%p %RGp-%RGp\n",
4098	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4099	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4100	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4101	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4102	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4103	" pCur=%p %RGp-%RGp\n",
4104	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4105	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4106	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4107	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4108	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4109	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4110	{
4111	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4112	for (;;)
4113	{
4114	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4115	AssertReleaseMsg(pCur2 != pCur,
4116	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4117	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4118	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4119	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4120	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4121	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4122	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4123	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4124	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4125	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4126	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4127	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4128	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4129	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4130	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4131	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4132	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4133	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4134	break;
4135	}
4136	}
4137
4138	pArgs->pPrevPhys2Virt = pCur;
4139	return 0;
4140	}
4141
4142
4143	/**
4144	* Perform an integrity check on the PGM component.
4145	*
4146	* @returns VINF_SUCCESS if everything is fine.
4147	* @returns VBox error status after asserting on integrity breach.
4148	* @param pVM Pointer to the VM.
4149	*/
4150	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4151	{
4152	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4153
4154	/*
4155	* Check the trees.
4156	*/
4157	int cErrors = 0;
4158	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4159	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4160	PGMCHECKINTARGS Args = s_LeftToRight;
4161	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4162	Args = s_RightToLeft;
4163	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4164	Args = s_LeftToRight;
4165	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4166	Args = s_RightToLeft;
4167	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4168	Args = s_LeftToRight;
4169	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4170	Args = s_RightToLeft;
4171	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4172	Args = s_LeftToRight;
4173	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4174	Args = s_RightToLeft;
4175	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4176
4177	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4178	}
4179

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 41783

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