PGM.cpp@ 55808

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1	/* $Id: PGM.cpp 55503 2015-04-29 08:11:26Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred
30	* to as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	* Note! The intermediate memory context is also used for 64-bit guest
85	* execution on 32-bit hosts. Because we need to load 64-bit registers
86	* prior to switching to guest context, we need to be in 64-bit mode
87	* first. So, HM has some 64-bit worker routines in VMMRC.rc that get
88	* invoked via the special world switcher code in LegacyToAMD64.asm.
89	*
90	*
91	* @subsection subsec_pgm_int_gc Guest Context Mappings
92	*
93	* During assignment and relocation of a guest context mapping the intermediate
94	* memory context is used to verify the new location.
95	*
96	* Guest context mappings are currently restricted to below 4GB, for reasons
97	* of simplicity. This may change when we implement AMD64 support.
98	*
99	*
100	*
101	*
102	* @section sec_pgm_misc Misc
103	*
104	*
105	* @subsection sec_pgm_misc_A20 The A20 Gate
106	*
107	* PGM implements the A20 gate masking when translating a virtual guest address
108	* into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
109	* the code reading the guest page table entries during shadowing. The masking
110	* is done consistenly for all CPU modes, paged ones included. Large pages are
111	* also masked correctly. (On current CPUs, experiments indicates that AMD does
112	* not apply A20M in paged modes and intel only does it for the 2nd MB of
113	* memory.)
114	*
115	* The A20 gate implementation is per CPU core. It can be configured on a per
116	* core basis via the keyboard device and PC architecture device. This is
117	* probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
118	* guest OSes try pushing things anyway, so who cares. (On current real systems
119	* the A20M signal is probably only sent to the boot CPU and it affects all
120	* thread and probably all cores in that package.)
121	*
122	* The keyboard device and the PC architecture device doesn't OR their A20
123	* config bits together, rather they are currently implemented such that they
124	* mirror the CPU state. So, flipping the bit in either of them will change the
125	* A20 state. (On real hardware the bits of the two devices should probably be
126	* ORed together to indicate enabled, i.e. both needs to be cleared to disable
127	* A20 masking.)
128	*
129	* The A20 state will change immediately, transmeta fashion. There is no delays
130	* due to buses, wiring or other physical stuff. (On real hardware there are
131	* normally delays, the delays differs between the two devices and probably also
132	* between chipsets and CPU generations. Note that it's said that transmeta CPUs
133	* does the change immediately like us, they apparently intercept/handles the
134	* port accesses in microcode. Neat.)
135	*
136	* @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
137	*
138	*
139	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
140	*
141	* The differences between legacy PAE and long mode PAE are:
142	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
143	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
144	* usual meanings while 6 is ignored (AMD). This means that upon switching to
145	* legacy PAE mode we'll have to clear these bits and when going to long mode
146	* they must be set. This applies to both intermediate and shadow contexts,
147	* however we don't need to do it for the intermediate one since we're
148	* executing with CR0.WP at that time.
149	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
150	* a page aligned one is required.
151	*
152	*
153	* @section sec_pgm_handlers Access Handlers
154	*
155	* Placeholder.
156	*
157	*
158	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
159	*
160	* Placeholder.
161	*
162	*
163	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
164	*
165	* We currently implement three types of virtual access handlers: ALL, WRITE
166	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
167	*
168	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
169	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
170	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
171	* rest of this section is going to be about these handlers.
172	*
173	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
174	* how successful this is gonna be...
175	*
176	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
177	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
178	* and create a new node that is inserted into the AVL tree (range key). Then
179	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
180	*
181	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
182	*
183	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
184	* via the current guest CR3 and update the physical page -> virtual handler
185	* translation. Needless to say, this doesn't exactly scale very well. If any changes
186	* are detected, it will flag a virtual bit update just like we did on registration.
187	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
188	*
189	* 2b. The virtual bit update process will iterate all the pages covered by all the
190	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
191	* virtual handlers on that page.
192	*
193	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
194	* we don't miss any alias mappings of the monitored pages.
195	*
196	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
197	*
198	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
199	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
200	* will call the handlers like in the next step. If the physical mapping has
201	* changed we will - some time in the future - perform a handler callback
202	* (optional) and update the physical -> virtual handler cache.
203	*
204	* 4. \#PF(,write) on a page in the range. This will cause the handler to
205	* be invoked.
206	*
207	* 5. The guest invalidates the page and changes the physical backing or
208	* unmaps it. This should cause the invalidation callback to be invoked
209	* (it might not yet be 100% perfect). Exactly what happens next... is
210	* this where we mess up and end up out of sync for a while?
211	*
212	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
213	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
214	* this handler to NONE and trigger a full PGM resync (basically the same
215	* as int step 1). Which means 2 is executed again.
216	*
217	*
218	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
219	*
220	* There is a bunch of things that needs to be done to make the virtual handlers
221	* work 100% correctly and work more efficiently.
222	*
223	* The first bit hasn't been implemented yet because it's going to slow the
224	* whole mess down even more, and besides it seems to be working reliably for
225	* our current uses. OTOH, some of the optimizations might end up more or less
226	* implementing the missing bits, so we'll see.
227	*
228	* On the optimization side, the first thing to do is to try avoid unnecessary
229	* cache flushing. Then try team up with the shadowing code to track changes
230	* in mappings by means of access to them (shadow in), updates to shadows pages,
231	* invlpg, and shadow PT discarding (perhaps).
232	*
233	* Some idea that have popped up for optimization for current and new features:
234	* - bitmap indicating where there are virtual handlers installed.
235	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
236	* - Further optimize this by min/max (needs min/max avl getters).
237	* - Shadow page table entry bit (if any left)?
238	*
239	*/
240
241
242	/** @page pg_pgm_phys PGM Physical Guest Memory Management
243	*
244	*
245	* Objectives:
246	* - Guest RAM over-commitment using memory ballooning,
247	* zero pages and general page sharing.
248	* - Moving or mirroring a VM onto a different physical machine.
249	*
250	*
251	* @subsection subsec_pgmPhys_Definitions Definitions
252	*
253	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
254	* machinery associated with it.
255	*
256	*
257	*
258	*
259	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
260	*
261	* Initially we map all guest memory to the (per VM) zero page, which
262	* means that none of the read functions will cause pages to be allocated.
263	*
264	* Exception, access bit in page tables that have been shared. This must
265	* be handled, but we must also make sure PGMGst*Modify doesn't make
266	* unnecessary modifications.
267	*
268	* Allocation points:
269	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
270	* - Replacing a zero page mapping at \#PF.
271	* - Replacing a shared page mapping at \#PF.
272	* - ROM registration (currently MMR3RomRegister).
273	* - VM restore (pgmR3Load).
274	*
275	* For the first three it would make sense to keep a few pages handy
276	* until we've reached the max memory commitment for the VM.
277	*
278	* For the ROM registration, we know exactly how many pages we need
279	* and will request these from ring-0. For restore, we will save
280	* the number of non-zero pages in the saved state and allocate
281	* them up front. This would allow the ring-0 component to refuse
282	* the request if the isn't sufficient memory available for VM use.
283	*
284	* Btw. for both ROM and restore allocations we won't be requiring
285	* zeroed pages as they are going to be filled instantly.
286	*
287	*
288	* @subsection subsec_pgmPhys_FreePage Freeing a page
289	*
290	* There are a few points where a page can be freed:
291	* - After being replaced by the zero page.
292	* - After being replaced by a shared page.
293	* - After being ballooned by the guest additions.
294	* - At reset.
295	* - At restore.
296	*
297	* When freeing one or more pages they will be returned to the ring-0
298	* component and replaced by the zero page.
299	*
300	* The reasoning for clearing out all the pages on reset is that it will
301	* return us to the exact same state as on power on, and may thereby help
302	* us reduce the memory load on the system. Further it might have a
303	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
304	*
305	* On restore, as mention under the allocation topic, pages should be
306	* freed / allocated depending on how many is actually required by the
307	* new VM state. The simplest approach is to do like on reset, and free
308	* all non-ROM pages and then allocate what we need.
309	*
310	* A measure to prevent some fragmentation, would be to let each allocation
311	* chunk have some affinity towards the VM having allocated the most pages
312	* from it. Also, try make sure to allocate from allocation chunks that
313	* are almost full. Admittedly, both these measures might work counter to
314	* our intentions and its probably not worth putting a lot of effort,
315	* cpu time or memory into this.
316	*
317	*
318	* @subsection subsec_pgmPhys_SharePage Sharing a page
319	*
320	* The basic idea is that there there will be a idle priority kernel
321	* thread walking the non-shared VM pages hashing them and looking for
322	* pages with the same checksum. If such pages are found, it will compare
323	* them byte-by-byte to see if they actually are identical. If found to be
324	* identical it will allocate a shared page, copy the content, check that
325	* the page didn't change while doing this, and finally request both the
326	* VMs to use the shared page instead. If the page is all zeros (special
327	* checksum and byte-by-byte check) it will request the VM that owns it
328	* to replace it with the zero page.
329	*
330	* To make this efficient, we will have to make sure not to try share a page
331	* that will change its contents soon. This part requires the most work.
332	* A simple idea would be to request the VM to write monitor the page for
333	* a while to make sure it isn't modified any time soon. Also, it may
334	* make sense to skip pages that are being write monitored since this
335	* information is readily available to the thread if it works on the
336	* per-VM guest memory structures (presently called PGMRAMRANGE).
337	*
338	*
339	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
340	*
341	* The pages are organized in allocation chunks in ring-0, this is a necessity
342	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
343	* could easily work on a page-by-page basis if we liked. Whether this is possible
344	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
345	* become a problem as part of the idea here is that we wish to return memory to
346	* the host system.
347	*
348	* For instance, starting two VMs at the same time, they will both allocate the
349	* guest memory on-demand and if permitted their page allocations will be
350	* intermixed. Shut down one of the two VMs and it will be difficult to return
351	* any memory to the host system because the page allocation for the two VMs are
352	* mixed up in the same allocation chunks.
353	*
354	* To further complicate matters, when pages are freed because they have been
355	* ballooned or become shared/zero the whole idea is that the page is supposed
356	* to be reused by another VM or returned to the host system. This will cause
357	* allocation chunks to contain pages belonging to different VMs and prevent
358	* returning memory to the host when one of those VM shuts down.
359	*
360	* The only way to really deal with this problem is to move pages. This can
361	* either be done at VM shutdown and or by the idle priority worker thread
362	* that will be responsible for finding sharable/zero pages. The mechanisms
363	* involved for coercing a VM to move a page (or to do it for it) will be
364	* the same as when telling it to share/zero a page.
365	*
366	*
367	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
368	*
369	* There's a difficult balance between keeping the per-page tracking structures
370	* (global and guest page) easy to use and keeping them from eating too much
371	* memory. We have limited virtual memory resources available when operating in
372	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
373	* tracking structures will be attempted designed such that we can deal with up
374	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
375	*
376	*
377	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
378	*
379	* @see pg_GMM
380	*
381	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
382	*
383	* Fixed info is the physical address of the page (HCPhys) and the page id
384	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
385	* Today we've restricting ourselves to 40(-12) bits because this is the current
386	* restrictions of all AMD64 implementations (I think Barcelona will up this
387	* to 48(-12) bits, not that it really matters) and I needed the bits for
388	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
389	* decent range for the page id: 2^(28+12) = 1024TB.
390	*
391	* In additions to these, we'll have to keep maintaining the page flags as we
392	* currently do. Although it wouldn't harm to optimize these quite a bit, like
393	* for instance the ROM shouldn't depend on having a write handler installed
394	* in order for it to become read-only. A RO/RW bit should be considered so
395	* that the page syncing code doesn't have to mess about checking multiple
396	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
397	* figure out how to setup a shadow PTE. But this of course, is second
398	* priority at present. Current this requires 12 bits, but could probably
399	* be optimized to ~8.
400	*
401	* Then there's the 24 bits used to track which shadow page tables are
402	* currently mapping a page for the purpose of speeding up physical
403	* access handlers, and thereby the page pool cache. More bit for this
404	* purpose wouldn't hurt IIRC.
405	*
406	* Then there is a new bit in which we need to record what kind of page
407	* this is, shared, zero, normal or write-monitored-normal. This'll
408	* require 2 bits. One bit might be needed for indicating whether a
409	* write monitored page has been written to. And yet another one or
410	* two for tracking migration status. 3-4 bits total then.
411	*
412	* Whatever is left will can be used to record the sharabilitiy of a
413	* page. The page checksum will not be stored in the per-VM table as
414	* the idle thread will not be permitted to do modifications to it.
415	* It will instead have to keep its own working set of potentially
416	* shareable pages and their check sums and stuff.
417	*
418	* For the present we'll keep the current packing of the
419	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
420	* we'll have to change it to a struct with a total of 128-bits at
421	* our disposal.
422	*
423	* The initial layout will be like this:
424	* @verbatim
425	RTHCPHYS HCPhys; The current stuff.
426	63:40 Current shadow PT tracking stuff.
427	39:12 The physical page frame number.
428	11:0 The current flags.
429	uint32_t u28PageId : 28; The page id.
430	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
431	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
432	uint32_t u1Reserved : 1; Reserved for later.
433	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
434	@endverbatim
435	*
436	* The final layout will be something like this:
437	* @verbatim
438	RTHCPHYS HCPhys; The current stuff.
439	63:48 High page id (12+).
440	47:12 The physical page frame number.
441	11:0 Low page id.
442	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
443	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
444	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
445	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
446	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
447	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
448	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
449	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
450	@endverbatim
451	*
452	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
453	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
454	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
455	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
456	*
457	* A couple of cost examples for the total cost per-VM + kernel.
458	* 32-bit Windows and 32-bit linux:
459	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
460	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
461	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
462	* 64-bit Windows and 64-bit linux:
463	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
464	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
465	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
466	*
467	* UPDATE - 2007-09-27:
468	* Will need a ballooned flag/state too because we cannot
469	* trust the guest 100% and reporting the same page as ballooned more
470	* than once will put the GMM off balance.
471	*
472	*
473	* @subsection subsec_pgmPhys_Serializing Serializing Access
474	*
475	* Initially, we'll try a simple scheme:
476	*
477	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
478	* by the EMT thread of that VM while in the pgm critsect.
479	* - Other threads in the VM process that needs to make reliable use of
480	* the per-VM RAM tracking structures will enter the critsect.
481	* - No process external thread or kernel thread will ever try enter
482	* the pgm critical section, as that just won't work.
483	* - The idle thread (and similar threads) doesn't not need 100% reliable
484	* data when performing it tasks as the EMT thread will be the one to
485	* do the actual changes later anyway. So, as long as it only accesses
486	* the main ram range, it can do so by somehow preventing the VM from
487	* being destroyed while it works on it...
488	*
489	* - The over-commitment management, including the allocating/freeing
490	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
491	* more mundane mutex implementation is broken on Linux).
492	* - A separate mutex is protecting the set of allocation chunks so
493	* that pages can be shared or/and freed up while some other VM is
494	* allocating more chunks. This mutex can be take from under the other
495	* one, but not the other way around.
496	*
497	*
498	* @subsection subsec_pgmPhys_Request VM Request interface
499	*
500	* When in ring-0 it will become necessary to send requests to a VM so it can
501	* for instance move a page while defragmenting during VM destroy. The idle
502	* thread will make use of this interface to request VMs to setup shared
503	* pages and to perform write monitoring of pages.
504	*
505	* I would propose an interface similar to the current VMReq interface, similar
506	* in that it doesn't require locking and that the one sending the request may
507	* wait for completion if it wishes to. This shouldn't be very difficult to
508	* realize.
509	*
510	* The requests themselves are also pretty simple. They are basically:
511	* -# Check that some precondition is still true.
512	* -# Do the update.
513	* -# Update all shadow page tables involved with the page.
514	*
515	* The 3rd step is identical to what we're already doing when updating a
516	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
517	*
518	*
519	*
520	* @section sec_pgmPhys_MappingCaches Mapping Caches
521	*
522	* In order to be able to map in and out memory and to be able to support
523	* guest with more RAM than we've got virtual address space, we'll employing
524	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
525	* however on 32-bit darwin the ring-0 code is running in a different memory
526	* context and therefore needs a separate cache. In raw-mode context we also
527	* need a separate cache. The 32-bit darwin mapping cache and the one for
528	* raw-mode context share a lot of code, see PGMRZDYNMAP.
529	*
530	*
531	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
532	*
533	* We've considered implementing the ring-3 mapping cache page based but found
534	* that this was bother some when one had to take into account TLBs+SMP and
535	* portability (missing the necessary APIs on several platforms). There were
536	* also some performance concerns with this approach which hadn't quite been
537	* worked out.
538	*
539	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
540	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
541	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
542	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
543	* costly than a single page, although how much more costly is uncertain. We'll
544	* try address this by using a very big cache, preferably bigger than the actual
545	* VM RAM size if possible. The current VM RAM sizes should give some idea for
546	* 32-bit boxes, while on 64-bit we can probably get away with employing an
547	* unlimited cache.
548	*
549	* The cache have to parts, as already indicated, the ring-3 side and the
550	* ring-0 side.
551	*
552	* The ring-0 will be tied to the page allocator since it will operate on the
553	* memory objects it contains. It will therefore require the first ring-0 mutex
554	* discussed in @ref subsec_pgmPhys_Serializing. We
555	* some double house keeping wrt to who has mapped what I think, since both
556	* VMMR0.r0 and RTR0MemObj will keep track of mapping relations
557	*
558	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
559	* require anyone that desires to do changes to the mapping cache to do that
560	* from within this critsect. Alternatively, we could employ a separate critsect
561	* for serializing changes to the mapping cache as this would reduce potential
562	* contention with other threads accessing mappings unrelated to the changes
563	* that are in process. We can see about this later, contention will show
564	* up in the statistics anyway, so it'll be simple to tell.
565	*
566	* The organization of the ring-3 part will be very much like how the allocation
567	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
568	* having to walk the tree all the time, we'll have a couple of lookaside entries
569	* like in we do for I/O ports and MMIO in IOM.
570	*
571	* The simplified flow of a PGMPhysRead/Write function:
572	* -# Enter the PGM critsect.
573	* -# Lookup GCPhys in the ram ranges and get the Page ID.
574	* -# Calc the Allocation Chunk ID from the Page ID.
575	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
576	* If not found in cache:
577	* -# Call ring-0 and request it to be mapped and supply
578	* a chunk to be unmapped if the cache is maxed out already.
579	* -# Insert the new mapping into the AVL tree (id + R3 address).
580	* -# Update the relevant lookaside entry and return the mapping address.
581	* -# Do the read/write according to monitoring flags and everything.
582	* -# Leave the critsect.
583	*
584	*
585	* @section sec_pgmPhys_Fallback Fallback
586	*
587	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
588	* API and thus require a fallback.
589	*
590	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
591	* will return to the ring-3 caller (and later ring-0) and asking it to seed
592	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
593	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
594	* "SeededAllocPages" call to ring-0.
595	*
596	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
597	* all page sharing (zero page detection will continue). It will also force
598	* all allocations to come from the VM which seeded the page. Both these
599	* measures are taken to make sure that there will never be any need for
600	* mapping anything into ring-3 - everything will be mapped already.
601	*
602	* Whether we'll continue to use the current MM locked memory management
603	* for this I don't quite know (I'd prefer not to and just ditch that all
604	* together), we'll see what's simplest to do.
605	*
606	*
607	*
608	* @section sec_pgmPhys_Changes Changes
609	*
610	* Breakdown of the changes involved?
611	*/
612
613	/*******************************************************************************
614	* Header Files *
615	*******************************************************************************/
616	#define LOG_GROUP LOG_GROUP_PGM
617	#include <VBox/vmm/dbgf.h>
618	#include <VBox/vmm/pgm.h>
619	#include <VBox/vmm/cpum.h>
620	#include <VBox/vmm/iom.h>
621	#include <VBox/sup.h>
622	#include <VBox/vmm/mm.h>
623	#include <VBox/vmm/em.h>
624	#include <VBox/vmm/stam.h>
625	#ifdef VBOX_WITH_REM
626	# include <VBox/vmm/rem.h>
627	#endif
628	#include <VBox/vmm/selm.h>
629	#include <VBox/vmm/ssm.h>
630	#include <VBox/vmm/hm.h>
631	#include "PGMInternal.h"
632	#include <VBox/vmm/vm.h>
633	#include <VBox/vmm/uvm.h>
634	#include "PGMInline.h"
635
636	#include <VBox/dbg.h>
637	#include <VBox/param.h>
638	#include <VBox/err.h>
639
640	#include <iprt/asm.h>
641	#include <iprt/asm-amd64-x86.h>
642	#include <iprt/assert.h>
643	#include <iprt/env.h>
644	#include <iprt/mem.h>
645	#include <iprt/file.h>
646	#include <iprt/string.h>
647	#include <iprt/thread.h>
648
649
650	/*******************************************************************************
651	* Internal Functions *
652	*******************************************************************************/
653	static int pgmR3InitPaging(PVM pVM);
654	static int pgmR3InitStats(PVM pVM);
655	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
656	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
657	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
658	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
659	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
660	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
661	#ifdef VBOX_STRICT
662	static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
663	#endif
664	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
665	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
666	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
667
668	#ifdef VBOX_WITH_DEBUGGER
669	static FNDBGCCMD pgmR3CmdError;
670	static FNDBGCCMD pgmR3CmdSync;
671	static FNDBGCCMD pgmR3CmdSyncAlways;
672	# ifdef VBOX_STRICT
673	static FNDBGCCMD pgmR3CmdAssertCR3;
674	# endif
675	static FNDBGCCMD pgmR3CmdPhysToFile;
676	#endif
677
678
679	/*******************************************************************************
680	* Global Variables *
681	*******************************************************************************/
682	#ifdef VBOX_WITH_DEBUGGER
683	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
684	static const DBGCVARDESC g_aPgmErrorArgs[] =
685	{
686	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
687	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
688	};
689
690	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
691	{
692	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
693	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
694	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
695	};
696
697	# ifdef DEBUG_sandervl
698	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
699	{
700	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
701	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
702	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
703	};
704	# endif
705
706	/** Command descriptors. */
707	static const DBGCCMD g_aCmds[] =
708	{
709	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
710	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
711	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
712	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
713	# ifdef VBOX_STRICT
714	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
715	# ifdef VBOX_WITH_PAGE_SHARING
716	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
717	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
718	# endif
719	# endif
720	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
721	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
722	};
723	#endif
724
725
726
727
728	/*
729	* Shadow - 32-bit mode
730	*/
731	#define PGM_SHW_TYPE PGM_TYPE_32BIT
732	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
733	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
734	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
735	#include "PGMShw.h"
736
737	/* Guest - real mode */
738	#define PGM_GST_TYPE PGM_TYPE_REAL
739	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
740	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
741	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
742	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
743	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
744	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
745	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
746	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
747	#include "PGMBth.h"
748	#include "PGMGstDefs.h"
749	#include "PGMGst.h"
750	#undef BTH_PGMPOOLKIND_PT_FOR_PT
751	#undef BTH_PGMPOOLKIND_ROOT
752	#undef PGM_BTH_NAME
753	#undef PGM_BTH_NAME_RC_STR
754	#undef PGM_BTH_NAME_R0_STR
755	#undef PGM_GST_TYPE
756	#undef PGM_GST_NAME
757	#undef PGM_GST_NAME_RC_STR
758	#undef PGM_GST_NAME_R0_STR
759
760	/* Guest - protected mode */
761	#define PGM_GST_TYPE PGM_TYPE_PROT
762	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
763	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
764	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
765	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
766	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
767	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
768	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
769	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
770	#include "PGMBth.h"
771	#include "PGMGstDefs.h"
772	#include "PGMGst.h"
773	#undef BTH_PGMPOOLKIND_PT_FOR_PT
774	#undef BTH_PGMPOOLKIND_ROOT
775	#undef PGM_BTH_NAME
776	#undef PGM_BTH_NAME_RC_STR
777	#undef PGM_BTH_NAME_R0_STR
778	#undef PGM_GST_TYPE
779	#undef PGM_GST_NAME
780	#undef PGM_GST_NAME_RC_STR
781	#undef PGM_GST_NAME_R0_STR
782
783	/* Guest - 32-bit mode */
784	#define PGM_GST_TYPE PGM_TYPE_32BIT
785	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
786	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
787	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
788	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
789	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
790	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
791	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
792	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
793	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
794	#include "PGMBth.h"
795	#include "PGMGstDefs.h"
796	#include "PGMGst.h"
797	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
798	#undef BTH_PGMPOOLKIND_PT_FOR_PT
799	#undef BTH_PGMPOOLKIND_ROOT
800	#undef PGM_BTH_NAME
801	#undef PGM_BTH_NAME_RC_STR
802	#undef PGM_BTH_NAME_R0_STR
803	#undef PGM_GST_TYPE
804	#undef PGM_GST_NAME
805	#undef PGM_GST_NAME_RC_STR
806	#undef PGM_GST_NAME_R0_STR
807
808	#undef PGM_SHW_TYPE
809	#undef PGM_SHW_NAME
810	#undef PGM_SHW_NAME_RC_STR
811	#undef PGM_SHW_NAME_R0_STR
812
813
814	/*
815	* Shadow - PAE mode
816	*/
817	#define PGM_SHW_TYPE PGM_TYPE_PAE
818	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
819	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
820	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
821	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
822	#include "PGMShw.h"
823
824	/* Guest - real mode */
825	#define PGM_GST_TYPE PGM_TYPE_REAL
826	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
827	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
828	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
829	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
830	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
831	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
832	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
833	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
834	#include "PGMGstDefs.h"
835	#include "PGMBth.h"
836	#undef BTH_PGMPOOLKIND_PT_FOR_PT
837	#undef BTH_PGMPOOLKIND_ROOT
838	#undef PGM_BTH_NAME
839	#undef PGM_BTH_NAME_RC_STR
840	#undef PGM_BTH_NAME_R0_STR
841	#undef PGM_GST_TYPE
842	#undef PGM_GST_NAME
843	#undef PGM_GST_NAME_RC_STR
844	#undef PGM_GST_NAME_R0_STR
845
846	/* Guest - protected mode */
847	#define PGM_GST_TYPE PGM_TYPE_PROT
848	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
849	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
850	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
851	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
852	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
853	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
854	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
855	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
856	#include "PGMGstDefs.h"
857	#include "PGMBth.h"
858	#undef BTH_PGMPOOLKIND_PT_FOR_PT
859	#undef BTH_PGMPOOLKIND_ROOT
860	#undef PGM_BTH_NAME
861	#undef PGM_BTH_NAME_RC_STR
862	#undef PGM_BTH_NAME_R0_STR
863	#undef PGM_GST_TYPE
864	#undef PGM_GST_NAME
865	#undef PGM_GST_NAME_RC_STR
866	#undef PGM_GST_NAME_R0_STR
867
868	/* Guest - 32-bit mode */
869	#define PGM_GST_TYPE PGM_TYPE_32BIT
870	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
871	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
872	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
873	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
874	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
875	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
876	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
877	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
878	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
879	#include "PGMGstDefs.h"
880	#include "PGMBth.h"
881	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
882	#undef BTH_PGMPOOLKIND_PT_FOR_PT
883	#undef BTH_PGMPOOLKIND_ROOT
884	#undef PGM_BTH_NAME
885	#undef PGM_BTH_NAME_RC_STR
886	#undef PGM_BTH_NAME_R0_STR
887	#undef PGM_GST_TYPE
888	#undef PGM_GST_NAME
889	#undef PGM_GST_NAME_RC_STR
890	#undef PGM_GST_NAME_R0_STR
891
892	/* Guest - PAE mode */
893	#define PGM_GST_TYPE PGM_TYPE_PAE
894	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
895	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
896	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
897	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
898	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
899	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
900	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
901	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
902	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
903	#include "PGMBth.h"
904	#include "PGMGstDefs.h"
905	#include "PGMGst.h"
906	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
907	#undef BTH_PGMPOOLKIND_PT_FOR_PT
908	#undef BTH_PGMPOOLKIND_ROOT
909	#undef PGM_BTH_NAME
910	#undef PGM_BTH_NAME_RC_STR
911	#undef PGM_BTH_NAME_R0_STR
912	#undef PGM_GST_TYPE
913	#undef PGM_GST_NAME
914	#undef PGM_GST_NAME_RC_STR
915	#undef PGM_GST_NAME_R0_STR
916
917	#undef PGM_SHW_TYPE
918	#undef PGM_SHW_NAME
919	#undef PGM_SHW_NAME_RC_STR
920	#undef PGM_SHW_NAME_R0_STR
921
922
923	/*
924	* Shadow - AMD64 mode
925	*/
926	#define PGM_SHW_TYPE PGM_TYPE_AMD64
927	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
928	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
929	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
930	#include "PGMShw.h"
931
932	#ifdef VBOX_WITH_64_BITS_GUESTS
933	/* Guest - AMD64 mode */
934	# define PGM_GST_TYPE PGM_TYPE_AMD64
935	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
936	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
937	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
938	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
939	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
940	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
941	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
942	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
943	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
944	# include "PGMBth.h"
945	# include "PGMGstDefs.h"
946	# include "PGMGst.h"
947	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
948	# undef BTH_PGMPOOLKIND_PT_FOR_PT
949	# undef BTH_PGMPOOLKIND_ROOT
950	# undef PGM_BTH_NAME
951	# undef PGM_BTH_NAME_RC_STR
952	# undef PGM_BTH_NAME_R0_STR
953	# undef PGM_GST_TYPE
954	# undef PGM_GST_NAME
955	# undef PGM_GST_NAME_RC_STR
956	# undef PGM_GST_NAME_R0_STR
957	#endif /* VBOX_WITH_64_BITS_GUESTS */
958
959	#undef PGM_SHW_TYPE
960	#undef PGM_SHW_NAME
961	#undef PGM_SHW_NAME_RC_STR
962	#undef PGM_SHW_NAME_R0_STR
963
964
965	/*
966	* Shadow - Nested paging mode
967	*/
968	#define PGM_SHW_TYPE PGM_TYPE_NESTED
969	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
970	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
971	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
972	#include "PGMShw.h"
973
974	/* Guest - real mode */
975	#define PGM_GST_TYPE PGM_TYPE_REAL
976	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
977	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
978	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
979	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
980	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
981	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
982	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
983	#include "PGMGstDefs.h"
984	#include "PGMBth.h"
985	#undef BTH_PGMPOOLKIND_PT_FOR_PT
986	#undef PGM_BTH_NAME
987	#undef PGM_BTH_NAME_RC_STR
988	#undef PGM_BTH_NAME_R0_STR
989	#undef PGM_GST_TYPE
990	#undef PGM_GST_NAME
991	#undef PGM_GST_NAME_RC_STR
992	#undef PGM_GST_NAME_R0_STR
993
994	/* Guest - protected mode */
995	#define PGM_GST_TYPE PGM_TYPE_PROT
996	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
997	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
998	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
999	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
1000	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
1001	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
1002	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1003	#include "PGMGstDefs.h"
1004	#include "PGMBth.h"
1005	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1006	#undef PGM_BTH_NAME
1007	#undef PGM_BTH_NAME_RC_STR
1008	#undef PGM_BTH_NAME_R0_STR
1009	#undef PGM_GST_TYPE
1010	#undef PGM_GST_NAME
1011	#undef PGM_GST_NAME_RC_STR
1012	#undef PGM_GST_NAME_R0_STR
1013
1014	/* Guest - 32-bit mode */
1015	#define PGM_GST_TYPE PGM_TYPE_32BIT
1016	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1017	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1018	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1019	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
1020	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
1021	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
1022	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1023	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1024	#include "PGMGstDefs.h"
1025	#include "PGMBth.h"
1026	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1027	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1028	#undef PGM_BTH_NAME
1029	#undef PGM_BTH_NAME_RC_STR
1030	#undef PGM_BTH_NAME_R0_STR
1031	#undef PGM_GST_TYPE
1032	#undef PGM_GST_NAME
1033	#undef PGM_GST_NAME_RC_STR
1034	#undef PGM_GST_NAME_R0_STR
1035
1036	/* Guest - PAE mode */
1037	#define PGM_GST_TYPE PGM_TYPE_PAE
1038	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1039	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1040	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1041	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1042	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1043	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1044	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1045	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1046	#include "PGMGstDefs.h"
1047	#include "PGMBth.h"
1048	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1049	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1050	#undef PGM_BTH_NAME
1051	#undef PGM_BTH_NAME_RC_STR
1052	#undef PGM_BTH_NAME_R0_STR
1053	#undef PGM_GST_TYPE
1054	#undef PGM_GST_NAME
1055	#undef PGM_GST_NAME_RC_STR
1056	#undef PGM_GST_NAME_R0_STR
1057
1058	#ifdef VBOX_WITH_64_BITS_GUESTS
1059	/* Guest - AMD64 mode */
1060	# define PGM_GST_TYPE PGM_TYPE_AMD64
1061	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1062	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1063	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1064	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1065	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1066	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1067	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1068	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1069	# include "PGMGstDefs.h"
1070	# include "PGMBth.h"
1071	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1072	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1073	# undef PGM_BTH_NAME
1074	# undef PGM_BTH_NAME_RC_STR
1075	# undef PGM_BTH_NAME_R0_STR
1076	# undef PGM_GST_TYPE
1077	# undef PGM_GST_NAME
1078	# undef PGM_GST_NAME_RC_STR
1079	# undef PGM_GST_NAME_R0_STR
1080	#endif /* VBOX_WITH_64_BITS_GUESTS */
1081
1082	#undef PGM_SHW_TYPE
1083	#undef PGM_SHW_NAME
1084	#undef PGM_SHW_NAME_RC_STR
1085	#undef PGM_SHW_NAME_R0_STR
1086
1087
1088	/*
1089	* Shadow - EPT
1090	*/
1091	#define PGM_SHW_TYPE PGM_TYPE_EPT
1092	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1093	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1094	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1095	#include "PGMShw.h"
1096
1097	/* Guest - real mode */
1098	#define PGM_GST_TYPE PGM_TYPE_REAL
1099	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1100	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1101	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1102	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1103	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1104	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1105	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1106	#include "PGMGstDefs.h"
1107	#include "PGMBth.h"
1108	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1109	#undef PGM_BTH_NAME
1110	#undef PGM_BTH_NAME_RC_STR
1111	#undef PGM_BTH_NAME_R0_STR
1112	#undef PGM_GST_TYPE
1113	#undef PGM_GST_NAME
1114	#undef PGM_GST_NAME_RC_STR
1115	#undef PGM_GST_NAME_R0_STR
1116
1117	/* Guest - protected mode */
1118	#define PGM_GST_TYPE PGM_TYPE_PROT
1119	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1120	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1121	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1122	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1123	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1124	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1125	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1126	#include "PGMGstDefs.h"
1127	#include "PGMBth.h"
1128	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1129	#undef PGM_BTH_NAME
1130	#undef PGM_BTH_NAME_RC_STR
1131	#undef PGM_BTH_NAME_R0_STR
1132	#undef PGM_GST_TYPE
1133	#undef PGM_GST_NAME
1134	#undef PGM_GST_NAME_RC_STR
1135	#undef PGM_GST_NAME_R0_STR
1136
1137	/* Guest - 32-bit mode */
1138	#define PGM_GST_TYPE PGM_TYPE_32BIT
1139	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1140	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1141	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1142	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1143	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1144	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1145	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1146	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1147	#include "PGMGstDefs.h"
1148	#include "PGMBth.h"
1149	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1150	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1151	#undef PGM_BTH_NAME
1152	#undef PGM_BTH_NAME_RC_STR
1153	#undef PGM_BTH_NAME_R0_STR
1154	#undef PGM_GST_TYPE
1155	#undef PGM_GST_NAME
1156	#undef PGM_GST_NAME_RC_STR
1157	#undef PGM_GST_NAME_R0_STR
1158
1159	/* Guest - PAE mode */
1160	#define PGM_GST_TYPE PGM_TYPE_PAE
1161	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1162	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1163	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1164	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1165	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1166	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1167	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1168	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1169	#include "PGMGstDefs.h"
1170	#include "PGMBth.h"
1171	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1172	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1173	#undef PGM_BTH_NAME
1174	#undef PGM_BTH_NAME_RC_STR
1175	#undef PGM_BTH_NAME_R0_STR
1176	#undef PGM_GST_TYPE
1177	#undef PGM_GST_NAME
1178	#undef PGM_GST_NAME_RC_STR
1179	#undef PGM_GST_NAME_R0_STR
1180
1181	#ifdef VBOX_WITH_64_BITS_GUESTS
1182	/* Guest - AMD64 mode */
1183	# define PGM_GST_TYPE PGM_TYPE_AMD64
1184	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1185	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1186	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1187	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1188	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1189	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1190	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1191	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1192	# include "PGMGstDefs.h"
1193	# include "PGMBth.h"
1194	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1195	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1196	# undef PGM_BTH_NAME
1197	# undef PGM_BTH_NAME_RC_STR
1198	# undef PGM_BTH_NAME_R0_STR
1199	# undef PGM_GST_TYPE
1200	# undef PGM_GST_NAME
1201	# undef PGM_GST_NAME_RC_STR
1202	# undef PGM_GST_NAME_R0_STR
1203	#endif /* VBOX_WITH_64_BITS_GUESTS */
1204
1205	#undef PGM_SHW_TYPE
1206	#undef PGM_SHW_NAME
1207	#undef PGM_SHW_NAME_RC_STR
1208	#undef PGM_SHW_NAME_R0_STR
1209
1210
1211
1212	/**
1213	* Initiates the paging of VM.
1214	*
1215	* @returns VBox status code.
1216	* @param pVM Pointer to VM structure.
1217	*/
1218	VMMR3DECL(int) PGMR3Init(PVM pVM)
1219	{
1220	LogFlow(("PGMR3Init:\n"));
1221	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1222	int rc;
1223
1224	/*
1225	* Assert alignment and sizes.
1226	*/
1227	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1228	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1229	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1230
1231	/*
1232	* Init the structure.
1233	*/
1234	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1235	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1236
1237	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1238	{
1239	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1240	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1241	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1242	}
1243
1244	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1245	{
1246	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1247	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1248	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1249	}
1250
1251	/* Init the per-CPU part. */
1252	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1253	{
1254	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1255	PPGMCPU pPGM = &pVCpu->pgm.s;
1256
1257	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1258	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1259	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1260
1261	pPGM->enmShadowMode = PGMMODE_INVALID;
1262	pPGM->enmGuestMode = PGMMODE_INVALID;
1263
1264	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1265
1266	pPGM->pGst32BitPdR3 = NULL;
1267	pPGM->pGstPaePdptR3 = NULL;
1268	pPGM->pGstAmd64Pml4R3 = NULL;
1269	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1270	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1271	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1272	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1273	#endif
1274	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1275	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1276	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1277	{
1278	pPGM->apGstPaePDsR3[i] = NULL;
1279	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1280	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1281	#endif
1282	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1283	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1284	pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1285	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1286	}
1287
1288	pPGM->fA20Enabled = true;
1289	pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
1290	}
1291
1292	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1293	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1294	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1295
1296	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1297	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1298	true
1299	#else
1300	false
1301	#endif
1302	);
1303	AssertLogRelRCReturn(rc, rc);
1304
1305	#if HC_ARCH_BITS == 32
1306	# ifdef RT_OS_DARWIN
1307	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1308	# else
1309	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1310	# endif
1311	#else
1312	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1313	#endif
1314	AssertLogRelRCReturn(rc, rc);
1315	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1316	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1317
1318	/*
1319	* Get the configured RAM size - to estimate saved state size.
1320	*/
1321	uint64_t cbRam;
1322	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1323	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1324	cbRam = 0;
1325	else if (RT_SUCCESS(rc))
1326	{
1327	if (cbRam < PAGE_SIZE)
1328	cbRam = 0;
1329	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1330	}
1331	else
1332	{
1333	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1334	return rc;
1335	}
1336
1337	/*
1338	* Check for PCI pass-through.
1339	*/
1340	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1341	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1342	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1343
1344	#ifdef VBOX_WITH_STATISTICS
1345	/*
1346	* Allocate memory for the statistics before someone tries to use them.
1347	*/
1348	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1349	void *pv;
1350	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1351	AssertRCReturn(rc, rc);
1352
1353	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1354	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1355	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1356	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1357
1358	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1359	{
1360	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1361	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1362	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1363
1364	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1365	}
1366	#endif /* VBOX_WITH_STATISTICS */
1367
1368	/*
1369	* Register callbacks, string formatters and the saved state data unit.
1370	*/
1371	#ifdef VBOX_STRICT
1372	VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1373	#endif
1374	PGMRegisterStringFormatTypes();
1375
1376	rc = pgmR3InitSavedState(pVM, cbRam);
1377	if (RT_FAILURE(rc))
1378	return rc;
1379
1380	/*
1381	* Initialize the PGM critical section and flush the phys TLBs
1382	*/
1383	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1384	AssertRCReturn(rc, rc);
1385
1386	PGMR3PhysChunkInvalidateTLB(pVM);
1387	pgmPhysInvalidatePageMapTLB(pVM);
1388
1389	/*
1390	* For the time being we sport a full set of handy pages in addition to the base
1391	* memory to simplify things.
1392	*/
1393	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1394	AssertRCReturn(rc, rc);
1395
1396	/*
1397	* Trees
1398	*/
1399	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1400	if (RT_SUCCESS(rc))
1401	{
1402	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1403	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1404	}
1405
1406	/*
1407	* Allocate the zero page.
1408	*/
1409	if (RT_SUCCESS(rc))
1410	{
1411	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1412	if (RT_SUCCESS(rc))
1413	{
1414	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1415	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1416	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1417	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1418	}
1419	}
1420
1421	/*
1422	* Allocate the invalid MMIO page.
1423	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1424	*/
1425	if (RT_SUCCESS(rc))
1426	{
1427	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1428	if (RT_SUCCESS(rc))
1429	{
1430	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1431	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1432	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1433	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1434	}
1435	}
1436
1437	/*
1438	* Register the physical access handler protecting ROMs.
1439	*/
1440	if (RT_SUCCESS(rc))
1441	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE,
1442	pgmR3PhysRomWriteHandler,
1443	NULL, "pgmPhysRomWriteHandler",
1444	NULL, "pgmPhysRomWriteHandler",
1445	"ROM write protection",
1446	&pVM->pgm.s.hRomPhysHandlerType);
1447
1448	/*
1449	* Init the paging.
1450	*/
1451	if (RT_SUCCESS(rc))
1452	rc = pgmR3InitPaging(pVM);
1453
1454	/*
1455	* Init the page pool.
1456	*/
1457	if (RT_SUCCESS(rc))
1458	rc = pgmR3PoolInit(pVM);
1459
1460	if (RT_SUCCESS(rc))
1461	{
1462	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1463	{
1464	PVMCPU pVCpu = &pVM->aCpus[i];
1465	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1466	if (RT_FAILURE(rc))
1467	break;
1468	}
1469	}
1470
1471	if (RT_SUCCESS(rc))
1472	{
1473	/*
1474	* Info & statistics
1475	*/
1476	DBGFR3InfoRegisterInternal(pVM, "mode",
1477	"Shows the current paging mode. "
1478	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1479	pgmR3InfoMode);
1480	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1481	"Dumps all the entries in the top level paging table. No arguments.",
1482	pgmR3InfoCr3);
1483	DBGFR3InfoRegisterInternal(pVM, "phys",
1484	"Dumps all the physical address ranges. No arguments.",
1485	pgmR3PhysInfo);
1486	DBGFR3InfoRegisterInternal(pVM, "handlers",
1487	"Dumps physical, virtual and hyper virtual handlers. "
1488	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1489	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1490	pgmR3InfoHandlers);
1491	DBGFR3InfoRegisterInternal(pVM, "mappings",
1492	"Dumps guest mappings.",
1493	pgmR3MapInfo);
1494
1495	pgmR3InitStats(pVM);
1496
1497	#ifdef VBOX_WITH_DEBUGGER
1498	/*
1499	* Debugger commands.
1500	*/
1501	static bool s_fRegisteredCmds = false;
1502	if (!s_fRegisteredCmds)
1503	{
1504	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1505	if (RT_SUCCESS(rc2))
1506	s_fRegisteredCmds = true;
1507	}
1508	#endif
1509	return VINF_SUCCESS;
1510	}
1511
1512	/* Almost no cleanup necessary, MM frees all memory. */
1513	PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1514
1515	return rc;
1516	}
1517
1518
1519	/**
1520	* Init paging.
1521	*
1522	* Since we need to check what mode the host is operating in before we can choose
1523	* the right paging functions for the host we have to delay this until R0 has
1524	* been initialized.
1525	*
1526	* @returns VBox status code.
1527	* @param pVM Pointer to the VM.
1528	*/
1529	static int pgmR3InitPaging(PVM pVM)
1530	{
1531	/*
1532	* Force a recalculation of modes and switcher so everyone gets notified.
1533	*/
1534	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1535	{
1536	PVMCPU pVCpu = &pVM->aCpus[i];
1537
1538	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1539	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1540	}
1541
1542	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1543
1544	/*
1545	* Allocate static mapping space for whatever the cr3 register
1546	* points to and in the case of PAE mode to the 4 PDs.
1547	*/
1548	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1549	if (RT_FAILURE(rc))
1550	{
1551	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1552	return rc;
1553	}
1554	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1555
1556	/*
1557	* Allocate pages for the three possible intermediate contexts
1558	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1559	* for the sake of simplicity. The AMD64 uses the PAE for the
1560	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1561	*
1562	* We assume that two page tables will be enought for the core code
1563	* mappings (HC virtual and identity).
1564	*/
1565	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1566	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1567	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1568	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1569	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1570	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1571	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1572	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1573	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1574	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1575	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1576	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1577
1578	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1579	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1580	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1581	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1582	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1583	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1584
1585	/*
1586	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1587	*/
1588	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1589	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1590	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1591
1592	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1593	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1594
1595	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1596	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1597	{
1598	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1599	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1600	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1601	}
1602
1603	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1604	{
1605	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1606	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1607	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1608	}
1609
1610	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1611	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1612	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1613	\| HCPhysInterPaePDPT64;
1614
1615	/*
1616	* Initialize paging workers and mode from current host mode
1617	* and the guest running in real mode.
1618	*/
1619	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1620	switch (pVM->pgm.s.enmHostMode)
1621	{
1622	case SUPPAGINGMODE_32_BIT:
1623	case SUPPAGINGMODE_32_BIT_GLOBAL:
1624	case SUPPAGINGMODE_PAE:
1625	case SUPPAGINGMODE_PAE_GLOBAL:
1626	case SUPPAGINGMODE_PAE_NX:
1627	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1628	break;
1629
1630	case SUPPAGINGMODE_AMD64:
1631	case SUPPAGINGMODE_AMD64_GLOBAL:
1632	case SUPPAGINGMODE_AMD64_NX:
1633	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1634	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1635	if (ARCH_BITS != 64)
1636	{
1637	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1638	LogRel(("PGM: Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1639	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1640	}
1641	#endif
1642	break;
1643	default:
1644	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1645	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1646	}
1647	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1648	if (RT_SUCCESS(rc))
1649	{
1650	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1651	#if HC_ARCH_BITS == 64
1652	LogRel(("PGM: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1653	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1654	LogRel(("PGM: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1655	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1656	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1657	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1658	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1659	#endif
1660
1661	/*
1662	* Log the host paging mode. It may come in handy.
1663	*/
1664	const char *pszHostMode;
1665	switch (pVM->pgm.s.enmHostMode)
1666	{
1667	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1668	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1669	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1670	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1671	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1672	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1673	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1674	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1675	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1676	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1677	default: pszHostMode = "???"; break;
1678	}
1679	LogRel(("PGM: Host paging mode: %s\n", pszHostMode));
1680
1681	return VINF_SUCCESS;
1682	}
1683
1684	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1685	return rc;
1686	}
1687
1688
1689	/**
1690	* Init statistics
1691	* @returns VBox status code.
1692	*/
1693	static int pgmR3InitStats(PVM pVM)
1694	{
1695	PPGM pPGM = &pVM->pgm.s;
1696	int rc;
1697
1698	/*
1699	* Release statistics.
1700	*/
1701	/* Common - misc variables */
1702	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1703	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1704	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1705	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1706	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1707	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1708	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1709	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1710	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1711	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1712	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1713	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1714	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1715	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1716	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1717	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1718	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1719	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1720	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1721
1722	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1723	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1724	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1725
1726	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1727
1728	/* Live save */
1729	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1730	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1731	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1732	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1733	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1734	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1735	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1736	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1737	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1738	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1739	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1740	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1741	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1742	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1743	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1744	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1745	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1746	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1747
1748	#ifdef VBOX_WITH_STATISTICS
1749
1750	# define PGM_REG_COUNTER(a, b, c) \
1751	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1752	AssertRC(rc);
1753
1754	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1755	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1756	AssertRC(rc);
1757
1758	# define PGM_REG_PROFILE(a, b, c) \
1759	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1760	AssertRC(rc);
1761
1762	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1763
1764	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1765	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1766	PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1767	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1768	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1769
1770	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1771	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1772	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1773	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1774	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1775	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1776	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1777	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1778	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1779	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1780
1781	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1782	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1783	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1784	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1785	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1786	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1787
1788	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1789	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1790	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1791	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1792	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1793	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1794	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1795	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1796
1797	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1798	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1799	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1800	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1801
1802	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1803	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1804	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1805	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1806
1807	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1808	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1809	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1810	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1811	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1812	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1813	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1814	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1815
1816	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1817	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1818	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1819	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1820	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1821	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1822
1823	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1824	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1825	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1826	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1827	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1828	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1829	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1830	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1831
1832	/* GC only: */
1833	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1834	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1835
1836	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1837	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1838	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1839	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1840	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1841	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1842	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1843	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1844
1845	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1846	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1847	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1848	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1849	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1850	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1851	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1852
1853	# undef PGM_REG_COUNTER
1854	# undef PGM_REG_PROFILE
1855	#endif
1856
1857	/*
1858	* Note! The layout below matches the member layout exactly!
1859	*/
1860
1861	/*
1862	* Common - stats
1863	*/
1864	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1865	{
1866	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1867
1868	#define PGM_REG_COUNTER(a, b, c) \
1869	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1870	AssertRC(rc);
1871	#define PGM_REG_PROFILE(a, b, c) \
1872	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1873	AssertRC(rc);
1874
1875	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1876	PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1877
1878	#ifdef VBOX_WITH_STATISTICS
1879	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1880
1881	# if 0 /* rarely useful; leave for debugging. */
1882	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1883	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1884	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1885	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1886	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1887	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1888	# endif
1889	/* R0 only: */
1890	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1891	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1892
1893	/* RZ only: */
1894	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1895	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1896	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1897	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1898	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1899	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1900	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1901	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1902	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1903	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1904	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1905	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1906	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1907	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1908	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1909	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1910	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1911	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1912	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsHack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USHack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled.");
1913	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsUnhack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USUnhack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled.");
1914	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1915	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1916	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1917	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1918	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1919	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1920	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1921	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1922	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1923	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1924	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1925	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1926	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1927	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1928	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1929	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1930	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1931	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1932	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1933	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1934	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1935	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1936	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1937	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1938	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1939	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1940	#if 0 /* rarely useful; leave for debugging. */
1941	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1942	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1943	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1944	#endif
1945	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1946	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1947	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1948	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1949	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1950
1951	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1952	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1953	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1954	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1955	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1956	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1957	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1958	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1959	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1960	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1961	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1962	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1963	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1964	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1965	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1966	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1967	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1968	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1969	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1970	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1971	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1972	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1973	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1974	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1975	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1976	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1977	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1978	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1979	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1980	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1981	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1982	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1983	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1984	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1985	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1986	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1987
1988	/* HC only: */
1989
1990	/* RZ & R3: */
1991	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1992	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1993	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1994	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1995	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1996	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1997	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1998	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1999	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2000	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2001	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
2002	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2003	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
2004	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
2005	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2006	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2007	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2008	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2009	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2010	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2011	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2012	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2013	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
2014	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2015	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2016	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2017	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
2018	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2019	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2020	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2021	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2022	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2023	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2024	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2025	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2026	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2027	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2028	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2029	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2030	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2031	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
2032	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2033	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2034	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2035	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2036	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2037	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2038
2039	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2040	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2041	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
2042	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2043	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2044	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2045	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2046	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2047	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2048	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2049	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
2050	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2051	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
2052	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
2053	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2054	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2055	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2056	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2057	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2058	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2059	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2060	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2061	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2062	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2063	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2064	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2065	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2066	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2067	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2068	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2069	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2070	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2071	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2072	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2073	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2074	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2075	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2076	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2077	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2078	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2079	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2080	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2081	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2082	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2083	#endif /* VBOX_WITH_STATISTICS */
2084
2085	#undef PGM_REG_PROFILE
2086	#undef PGM_REG_COUNTER
2087
2088	}
2089
2090	return VINF_SUCCESS;
2091	}
2092
2093
2094	/**
2095	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2096	*
2097	* The dynamic mapping area will also be allocated and initialized at this
2098	* time. We could allocate it during PGMR3Init of course, but the mapping
2099	* wouldn't be allocated at that time preventing us from setting up the
2100	* page table entries with the dummy page.
2101	*
2102	* @returns VBox status code.
2103	* @param pVM Pointer to the VM.
2104	*/
2105	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2106	{
2107	RTGCPTR GCPtr;
2108	int rc;
2109
2110	/*
2111	* Reserve space for the dynamic mappings.
2112	*/
2113	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2114	if (RT_SUCCESS(rc))
2115	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2116
2117	if ( RT_SUCCESS(rc)
2118	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2119	{
2120	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2121	if (RT_SUCCESS(rc))
2122	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2123	}
2124	if (RT_SUCCESS(rc))
2125	{
2126	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2127	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2128	}
2129	return rc;
2130	}
2131
2132
2133	/**
2134	* Ring-3 init finalizing.
2135	*
2136	* @returns VBox status code.
2137	* @param pVM Pointer to the VM.
2138	*/
2139	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2140	{
2141	int rc;
2142
2143	/*
2144	* Reserve space for the dynamic mappings.
2145	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2146	*/
2147	/* get the pointer to the page table entries. */
2148	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2149	AssertRelease(pMapping);
2150	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2151	const unsigned iPT = off >> X86_PD_SHIFT;
2152	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2153	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2154	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2155
2156	/* init cache area */
2157	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2158	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2159	{
2160	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2161	AssertRCReturn(rc, rc);
2162	}
2163
2164	/*
2165	* Determine the max physical address width (MAXPHYADDR) and apply it to
2166	* all the mask members and stuff.
2167	*/
2168	uint32_t cMaxPhysAddrWidth;
2169	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2170	if ( uMaxExtLeaf >= 0x80000008
2171	&& uMaxExtLeaf <= 0x80000fff)
2172	{
2173	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2174	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2175	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2176	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2177	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2178	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2179	}
2180	else
2181	{
2182	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2183	cMaxPhysAddrWidth = 48;
2184	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2185	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2186	}
2187
2188	/** @todo query from CPUM. */
2189	pVM->pgm.s.GCPhysInvAddrMask = 0;
2190	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2191	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2192
2193	/*
2194	* Initialize the invalid paging entry masks, assuming NX is disabled.
2195	*/
2196	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2197	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2198	{
2199	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2200
2201	/** @todo The manuals are not entirely clear whether the physical
2202	* address width is relevant. See table 5-9 in the intel
2203	* manual vs the PDE4M descriptions. Write testcase (NP). */
2204	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2205	\| X86_PDE4M_MBZ_MASK;
2206
2207	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2208	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2209	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2210	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2211
2212	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2213	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2214	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2215	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2216	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2217	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2218
2219	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
2220	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
2221	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
2222	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2223	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
2224	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
2225	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
2226	}
2227
2228	/*
2229	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2230	* Intel only goes up to 36 bits, so we stick to 36 as well.
2231	* Update: More recent intel manuals specifies 40 bits just like AMD.
2232	*/
2233	uint32_t u32Dummy, u32Features;
2234	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2235	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2236	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2237	else
2238	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2239
2240	/*
2241	* Allocate memory if we're supposed to do that.
2242	*/
2243	if (pVM->pgm.s.fRamPreAlloc)
2244	rc = pgmR3PhysRamPreAllocate(pVM);
2245
2246	LogRel(("PGM: PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2247	return rc;
2248	}
2249
2250
2251	/**
2252	* Init phase completed callback.
2253	*
2254	* @returns VBox status code.
2255	* @param pVM Pointer to the VM.
2256	* @param enmWhat What has been completed.
2257	* @thread EMT(0)
2258	*/
2259	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2260	{
2261	switch (enmWhat)
2262	{
2263	case VMINITCOMPLETED_HM:
2264	#ifdef VBOX_WITH_PCI_PASSTHROUGH
2265	if (pVM->pgm.s.fPciPassthrough)
2266	{
2267	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2268	AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
2269	AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2270
2271	/*
2272	* Report assignments to the IOMMU (hope that's good enough for now).
2273	*/
2274	if (pVM->pgm.s.fPciPassthrough)
2275	{
2276	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2277	AssertRCReturn(rc, rc);
2278	}
2279	}
2280	#else
2281	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2282	#endif
2283	break;
2284
2285	default:
2286	/* shut up gcc */
2287	break;
2288	}
2289
2290	return VINF_SUCCESS;
2291	}
2292
2293
2294	/**
2295	* Applies relocations to data and code managed by this component.
2296	*
2297	* This function will be called at init and whenever the VMM need to relocate it
2298	* self inside the GC.
2299	*
2300	* @param pVM The VM.
2301	* @param offDelta Relocation delta relative to old location.
2302	*/
2303	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2304	{
2305	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2306
2307	/*
2308	* Paging stuff.
2309	*/
2310	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2311
2312	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2313
2314	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2315	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2316	{
2317	PVMCPU pVCpu = &pVM->aCpus[i];
2318
2319	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2320
2321	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2322	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2323	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2324	}
2325
2326	/*
2327	* Trees.
2328	*/
2329	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2330
2331	/*
2332	* Ram ranges.
2333	*/
2334	if (pVM->pgm.s.pRamRangesXR3)
2335	{
2336	/* Update the pSelfRC pointers and relink them. */
2337	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2338	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2339	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2340	pgmR3PhysRelinkRamRanges(pVM);
2341
2342	/* Flush the RC TLB. */
2343	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2344	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2345	}
2346
2347	/*
2348	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2349	* be mapped and thus not included in the above exercise.
2350	*/
2351	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2352	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2353	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2354
2355	/*
2356	* Update the two page directories with all page table mappings.
2357	* (One or more of them have changed, that's why we're here.)
2358	*/
2359	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2360	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2361	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2362
2363	/* Relocate GC addresses of Page Tables. */
2364	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2365	{
2366	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2367	{
2368	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2369	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2370	}
2371	}
2372
2373	/*
2374	* Dynamic page mapping area.
2375	*/
2376	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2377	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2378	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2379
2380	if (pVM->pgm.s.pRCDynMap)
2381	{
2382	pVM->pgm.s.pRCDynMap += offDelta;
2383	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2384
2385	pDynMap->paPages += offDelta;
2386	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2387
2388	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2389	{
2390	paPages[iPage].pvPage += offDelta;
2391	paPages[iPage].uPte.pLegacy += offDelta;
2392	paPages[iPage].uPte.pPae += offDelta;
2393	}
2394	}
2395
2396	/*
2397	* The Zero page.
2398	*/
2399	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2400	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2401	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
2402	#else
2403	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2404	#endif
2405
2406	/*
2407	* Physical and virtual handlers.
2408	*/
2409	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2410	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2411
2412	PPGMPHYSHANDLERTYPEINT pCurPhysType;
2413	RTListOff32ForEach(&pVM->pgm.s.pTreesR3->HeadPhysHandlerTypes, pCurPhysType, PGMPHYSHANDLERTYPEINT, ListNode)
2414	{
2415	if (pCurPhysType->pfnHandlerRC)
2416	pCurPhysType->pfnHandlerRC += offDelta;
2417	}
2418
2419	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2420	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2421
2422	/*
2423	* The page pool.
2424	*/
2425	pgmR3PoolRelocate(pVM);
2426
2427	#ifdef VBOX_WITH_STATISTICS
2428	/*
2429	* Statistics.
2430	*/
2431	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2432	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2433	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2434	#endif
2435	}
2436
2437
2438	/**
2439	* Callback function for relocating a physical access handler.
2440	*
2441	* @returns 0 (continue enum)
2442	* @param pNode Pointer to a PGMPHYSHANDLER node.
2443	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2444	* not certain the delta will fit in a void pointer for all possible configs.
2445	*/
2446	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2447	{
2448	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2449	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2450	if (pHandler->pvUserRC >= 0x10000)
2451	pHandler->pvUserRC += offDelta;
2452	return 0;
2453	}
2454
2455
2456	/**
2457	* Callback function for relocating a virtual access handler.
2458	*
2459	* @returns 0 (continue enum)
2460	* @param pNode Pointer to a PGMVIRTHANDLER node.
2461	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2462	* not certain the delta will fit in a void pointer for all possible configs.
2463	*/
2464	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2465	{
2466	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2467	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2468	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2469	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2470	Assert(pHandler->pfnHandlerRC);
2471	pHandler->pfnHandlerRC += offDelta;
2472	return 0;
2473	}
2474
2475
2476	/**
2477	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2478	*
2479	* @returns 0 (continue enum)
2480	* @param pNode Pointer to a PGMVIRTHANDLER node.
2481	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2482	* not certain the delta will fit in a void pointer for all possible configs.
2483	*/
2484	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2485	{
2486	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2487	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2488	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2489	Assert(pHandler->pfnHandlerRC);
2490	pHandler->pfnHandlerRC += offDelta;
2491	return 0;
2492	}
2493
2494
2495	/**
2496	* Resets a virtual CPU when unplugged.
2497	*
2498	* @param pVM Pointer to the VM.
2499	* @param pVCpu Pointer to the VMCPU.
2500	*/
2501	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2502	{
2503	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2504	AssertRC(rc);
2505
2506	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2507	AssertRC(rc);
2508
2509	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2510
2511	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2512
2513	/*
2514	* Re-init other members.
2515	*/
2516	pVCpu->pgm.s.fA20Enabled = true;
2517	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2518
2519	/*
2520	* Clear the FFs PGM owns.
2521	*/
2522	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2523	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2524	}
2525
2526
2527	/**
2528	* The VM is being reset.
2529	*
2530	* For the PGM component this means that any PD write monitors
2531	* needs to be removed.
2532	*
2533	* @param pVM Pointer to the VM.
2534	*/
2535	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
2536	{
2537	LogFlow(("PGMR3Reset:\n"));
2538	VM_ASSERT_EMT(pVM);
2539
2540	pgmLock(pVM);
2541
2542	/*
2543	* Unfix any fixed mappings and disable CR3 monitoring.
2544	*/
2545	pVM->pgm.s.fMappingsFixed = false;
2546	pVM->pgm.s.fMappingsFixedRestored = false;
2547	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2548	pVM->pgm.s.cbMappingFixed = 0;
2549
2550	/*
2551	* Exit the guest paging mode before the pgm pool gets reset.
2552	* Important to clean up the amd64 case.
2553	*/
2554	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2555	{
2556	PVMCPU pVCpu = &pVM->aCpus[i];
2557	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2558	AssertReleaseRC(rc);
2559	}
2560
2561	#ifdef DEBUG
2562	DBGFR3_INFO_LOG(pVM, "mappings", NULL);
2563	DBGFR3_INFO_LOG(pVM, "handlers", "all nostat");
2564	#endif
2565
2566	/*
2567	* Switch mode back to real mode. (before resetting the pgm pool!)
2568	*/
2569	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2570	{
2571	PVMCPU pVCpu = &pVM->aCpus[i];
2572
2573	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2574	AssertReleaseRC(rc);
2575
2576	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2577	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2578	}
2579
2580	/*
2581	* Reset the shadow page pool.
2582	*/
2583	pgmR3PoolReset(pVM);
2584
2585	/*
2586	* Re-init various other members and clear the FFs that PGM owns.
2587	*/
2588	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2589	{
2590	PVMCPU pVCpu = &pVM->aCpus[i];
2591
2592	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2593	PGMNotifyNxeChanged(pVCpu, false);
2594
2595	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2596	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2597
2598	if (!pVCpu->pgm.s.fA20Enabled)
2599	{
2600	pVCpu->pgm.s.fA20Enabled = true;
2601	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2602	#ifdef PGM_WITH_A20
2603	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2605	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
2606	HMFlushTLB(pVCpu);
2607	#endif
2608	}
2609	}
2610
2611	pgmUnlock(pVM);
2612	}
2613
2614
2615	/**
2616	* Memory setup after VM construction or reset.
2617	*
2618	* @param pVM Pointer to the VM.
2619	* @param fAtReset Indicates the context, after reset if @c true or after
2620	* construction if @c false.
2621	*/
2622	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
2623	{
2624	if (fAtReset)
2625	{
2626	pgmLock(pVM);
2627
2628	int rc = pgmR3PhysRamZeroAll(pVM);
2629	AssertReleaseRC(rc);
2630
2631	rc = pgmR3PhysRomReset(pVM);
2632	AssertReleaseRC(rc);
2633
2634	pgmUnlock(pVM);
2635	}
2636	}
2637
2638
2639	#ifdef VBOX_STRICT
2640	/**
2641	* VM state change callback for clearing fNoMorePhysWrites after
2642	* a snapshot has been created.
2643	*/
2644	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2645	{
2646	if ( enmState == VMSTATE_RUNNING
2647	\|\| enmState == VMSTATE_RESUMING)
2648	pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2649	NOREF(enmOldState); NOREF(pvUser);
2650	}
2651	#endif
2652
2653	/**
2654	* Private API to reset fNoMorePhysWrites.
2655	*/
2656	VMMR3DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2657	{
2658	pVM->pgm.s.fNoMorePhysWrites = false;
2659	}
2660
2661	/**
2662	* Terminates the PGM.
2663	*
2664	* @returns VBox status code.
2665	* @param pVM Pointer to VM structure.
2666	*/
2667	VMMR3DECL(int) PGMR3Term(PVM pVM)
2668	{
2669	/* Must free shared pages here. */
2670	pgmLock(pVM);
2671	pgmR3PhysRamTerm(pVM);
2672	pgmR3PhysRomTerm(pVM);
2673	pgmUnlock(pVM);
2674
2675	PGMDeregisterStringFormatTypes();
2676	return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2677	}
2678
2679
2680	/**
2681	* Show paging mode.
2682	*
2683	* @param pVM Pointer to the VM.
2684	* @param pHlp The info helpers.
2685	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2686	*/
2687	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2688	{
2689	/* digest argument. */
2690	bool fGuest, fShadow, fHost;
2691	if (pszArgs)
2692	pszArgs = RTStrStripL(pszArgs);
2693	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2694	fShadow = fHost = fGuest = true;
2695	else
2696	{
2697	fShadow = fHost = fGuest = false;
2698	if (strstr(pszArgs, "guest"))
2699	fGuest = true;
2700	if (strstr(pszArgs, "shadow"))
2701	fShadow = true;
2702	if (strstr(pszArgs, "host"))
2703	fHost = true;
2704	}
2705
2706	/** @todo SMP support! */
2707	/* print info. */
2708	if (fGuest)
2709	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2710	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2711	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled", pVM->aCpus[0].pgm.s.cA20Changes.c);
2712	if (fShadow)
2713	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2714	if (fHost)
2715	{
2716	const char *psz;
2717	switch (pVM->pgm.s.enmHostMode)
2718	{
2719	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2720	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2721	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2722	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2723	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2724	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2725	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2726	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2727	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2728	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2729	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2730	default: psz = "unknown"; break;
2731	}
2732	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2733	}
2734	}
2735
2736
2737	/**
2738	* Dump registered MMIO ranges to the log.
2739	*
2740	* @param pVM Pointer to the VM.
2741	* @param pHlp The info helpers.
2742	* @param pszArgs Arguments, ignored.
2743	*/
2744	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2745	{
2746	NOREF(pszArgs);
2747	pHlp->pfnPrintf(pHlp,
2748	"RAM ranges (pVM=%p)\n"
2749	"%.s %.s\n",
2750	pVM,
2751	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2752	sizeof(RTHCPTR) * 2, "pvHC ");
2753
2754	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2755	pHlp->pfnPrintf(pHlp,
2756	"%RGp-%RGp %RHv %s\n",
2757	pCur->GCPhys,
2758	pCur->GCPhysLast,
2759	pCur->pvR3,
2760	pCur->pszDesc);
2761	}
2762
2763
2764	/**
2765	* Dump the page directory to the log.
2766	*
2767	* @param pVM Pointer to the VM.
2768	* @param pHlp The info helpers.
2769	* @param pszArgs Arguments, ignored.
2770	*/
2771	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2772	{
2773	/** @todo SMP support!! */
2774	PVMCPU pVCpu = &pVM->aCpus[0];
2775
2776	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2777	/* Big pages supported? */
2778	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2779
2780	/* Global pages supported? */
2781	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2782
2783	NOREF(pszArgs);
2784
2785	/*
2786	* Get page directory addresses.
2787	*/
2788	pgmLock(pVM);
2789	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2790	Assert(pPDSrc);
2791
2792	/*
2793	* Iterate the page directory.
2794	*/
2795	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2796	{
2797	X86PDE PdeSrc = pPDSrc->a[iPD];
2798	if (PdeSrc.n.u1Present)
2799	{
2800	if (PdeSrc.b.u1Size && fPSE)
2801	pHlp->pfnPrintf(pHlp,
2802	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2803	iPD,
2804	pgmGstGet4MBPhysPage(pVM, PdeSrc),
2805	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2806	else
2807	pHlp->pfnPrintf(pHlp,
2808	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2809	iPD,
2810	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2811	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2812	}
2813	}
2814	pgmUnlock(pVM);
2815	}
2816
2817
2818	/**
2819	* Service a VMMCALLRING3_PGM_LOCK call.
2820	*
2821	* @returns VBox status code.
2822	* @param pVM Pointer to the VM.
2823	*/
2824	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2825	{
2826	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2827	AssertRC(rc);
2828	return rc;
2829	}
2830
2831
2832	/**
2833	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2834	*
2835	* @returns PGM_TYPE_*.
2836	* @param pgmMode The mode value to convert.
2837	*/
2838	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2839	{
2840	switch (pgmMode)
2841	{
2842	case PGMMODE_REAL: return PGM_TYPE_REAL;
2843	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2844	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2845	case PGMMODE_PAE:
2846	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2847	case PGMMODE_AMD64:
2848	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2849	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2850	case PGMMODE_EPT: return PGM_TYPE_EPT;
2851	default:
2852	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2853	}
2854	}
2855
2856
2857	/**
2858	* Gets the index into the paging mode data array of a SHW+GST mode.
2859	*
2860	* @returns PGM::paPagingData index.
2861	* @param uShwType The shadow paging mode type.
2862	* @param uGstType The guest paging mode type.
2863	*/
2864	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2865	{
2866	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2867	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2868	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2869	+ (uGstType - PGM_TYPE_REAL);
2870	}
2871
2872
2873	/**
2874	* Gets the index into the paging mode data array of a SHW+GST mode.
2875	*
2876	* @returns PGM::paPagingData index.
2877	* @param enmShw The shadow paging mode.
2878	* @param enmGst The guest paging mode.
2879	*/
2880	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2881	{
2882	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2883	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2884	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2885	}
2886
2887
2888	/**
2889	* Calculates the max data index.
2890	* @returns The number of entries in the paging data array.
2891	*/
2892	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2893	{
2894	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2895	}
2896
2897
2898	/**
2899	* Initializes the paging mode data kept in PGM::paModeData.
2900	*
2901	* @param pVM Pointer to the VM.
2902	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2903	* This is used early in the init process to avoid trouble with PDM
2904	* not being initialized yet.
2905	*/
2906	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2907	{
2908	PPGMMODEDATA pModeData;
2909	int rc;
2910
2911	/*
2912	* Allocate the array on the first call.
2913	*/
2914	if (!pVM->pgm.s.paModeData)
2915	{
2916	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2917	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2918	}
2919
2920	/*
2921	* Initialize the array entries.
2922	*/
2923	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2924	pModeData->uShwType = PGM_TYPE_32BIT;
2925	pModeData->uGstType = PGM_TYPE_REAL;
2926	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2927	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2928	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2929
2930	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2931	pModeData->uShwType = PGM_TYPE_32BIT;
2932	pModeData->uGstType = PGM_TYPE_PROT;
2933	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2934	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2935	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2936
2937	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2938	pModeData->uShwType = PGM_TYPE_32BIT;
2939	pModeData->uGstType = PGM_TYPE_32BIT;
2940	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2941	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2942	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2943
2944	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2945	pModeData->uShwType = PGM_TYPE_PAE;
2946	pModeData->uGstType = PGM_TYPE_REAL;
2947	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2948	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2949	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2950
2951	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2952	pModeData->uShwType = PGM_TYPE_PAE;
2953	pModeData->uGstType = PGM_TYPE_PROT;
2954	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2955	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2956	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2957
2958	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2959	pModeData->uShwType = PGM_TYPE_PAE;
2960	pModeData->uGstType = PGM_TYPE_32BIT;
2961	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2962	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2963	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2964
2965	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2966	pModeData->uShwType = PGM_TYPE_PAE;
2967	pModeData->uGstType = PGM_TYPE_PAE;
2968	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2969	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2970	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2971
2972	#ifdef VBOX_WITH_64_BITS_GUESTS
2973	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2974	pModeData->uShwType = PGM_TYPE_AMD64;
2975	pModeData->uGstType = PGM_TYPE_AMD64;
2976	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2977	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2978	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2979	#endif
2980
2981	/* The nested paging mode. */
2982	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2983	pModeData->uShwType = PGM_TYPE_NESTED;
2984	pModeData->uGstType = PGM_TYPE_REAL;
2985	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2986	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2987
2988	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2989	pModeData->uShwType = PGM_TYPE_NESTED;
2990	pModeData->uGstType = PGM_TYPE_PROT;
2991	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2992	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2993
2994	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2995	pModeData->uShwType = PGM_TYPE_NESTED;
2996	pModeData->uGstType = PGM_TYPE_32BIT;
2997	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2998	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2999
3000	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3001	pModeData->uShwType = PGM_TYPE_NESTED;
3002	pModeData->uGstType = PGM_TYPE_PAE;
3003	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3004	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3005
3006	#ifdef VBOX_WITH_64_BITS_GUESTS
3007	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3008	pModeData->uShwType = PGM_TYPE_NESTED;
3009	pModeData->uGstType = PGM_TYPE_AMD64;
3010	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3011	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3012	#endif
3013
3014	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3015	switch (pVM->pgm.s.enmHostMode)
3016	{
3017	#if HC_ARCH_BITS == 32
3018	case SUPPAGINGMODE_32_BIT:
3019	case SUPPAGINGMODE_32_BIT_GLOBAL:
3020	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3021	{
3022	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3023	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3024	}
3025	# ifdef VBOX_WITH_64_BITS_GUESTS
3026	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3027	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3028	# endif
3029	break;
3030
3031	case SUPPAGINGMODE_PAE:
3032	case SUPPAGINGMODE_PAE_NX:
3033	case SUPPAGINGMODE_PAE_GLOBAL:
3034	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3035	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3036	{
3037	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3038	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3039	}
3040	# ifdef VBOX_WITH_64_BITS_GUESTS
3041	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3042	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3043	# endif
3044	break;
3045	#endif /* HC_ARCH_BITS == 32 */
3046
3047	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3048	case SUPPAGINGMODE_AMD64:
3049	case SUPPAGINGMODE_AMD64_GLOBAL:
3050	case SUPPAGINGMODE_AMD64_NX:
3051	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3052	# ifdef VBOX_WITH_64_BITS_GUESTS
3053	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3054	# else
3055	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3056	# endif
3057	{
3058	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3059	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3060	}
3061	break;
3062	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3063
3064	default:
3065	AssertFailed();
3066	break;
3067	}
3068
3069	/* Extended paging (EPT) / Intel VT-x */
3070	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3071	pModeData->uShwType = PGM_TYPE_EPT;
3072	pModeData->uGstType = PGM_TYPE_REAL;
3073	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3074	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3075	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3076
3077	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3078	pModeData->uShwType = PGM_TYPE_EPT;
3079	pModeData->uGstType = PGM_TYPE_PROT;
3080	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3081	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3082	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3083
3084	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3085	pModeData->uShwType = PGM_TYPE_EPT;
3086	pModeData->uGstType = PGM_TYPE_32BIT;
3087	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3088	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3089	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3090
3091	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3092	pModeData->uShwType = PGM_TYPE_EPT;
3093	pModeData->uGstType = PGM_TYPE_PAE;
3094	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3095	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3096	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3097
3098	#ifdef VBOX_WITH_64_BITS_GUESTS
3099	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3100	pModeData->uShwType = PGM_TYPE_EPT;
3101	pModeData->uGstType = PGM_TYPE_AMD64;
3102	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3103	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3104	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3105	#endif
3106	return VINF_SUCCESS;
3107	}
3108
3109
3110	/**
3111	* Switch to different (or relocated in the relocate case) mode data.
3112	*
3113	* @param pVM Pointer to the VM.
3114	* @param pVCpu Pointer to the VMCPU.
3115	* @param enmShw The shadow paging mode.
3116	* @param enmGst The guest paging mode.
3117	*/
3118	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3119	{
3120	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3121
3122	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3123	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3124
3125	/* shadow */
3126	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3127	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3128	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3129	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3130	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3131
3132	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3133	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3134
3135	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3136	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3137
3138
3139	/* guest */
3140	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3141	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3142	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3143	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3144	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3145	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3146	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3147	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3148	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3149	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3150	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3151	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3152
3153	/* both */
3154	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3155	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3156	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3157	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3158	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3159	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3160	#ifdef VBOX_STRICT
3161	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3162	#endif
3163	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3164	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3165
3166	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3167	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3168	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3169	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3170	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3171	#ifdef VBOX_STRICT
3172	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3173	#endif
3174	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3175	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3176
3177	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3178	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3179	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3180	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3181	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3182	#ifdef VBOX_STRICT
3183	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3184	#endif
3185	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3186	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3187	}
3188
3189
3190	/**
3191	* Calculates the shadow paging mode.
3192	*
3193	* @returns The shadow paging mode.
3194	* @param pVM Pointer to the VM.
3195	* @param enmGuestMode The guest mode.
3196	* @param enmHostMode The host mode.
3197	* @param enmShadowMode The current shadow mode.
3198	* @param penmSwitcher Where to store the switcher to use.
3199	* VMMSWITCHER_INVALID means no change.
3200	*/
3201	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3202	{
3203	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3204	switch (enmGuestMode)
3205	{
3206	/*
3207	* When switching to real or protected mode we don't change
3208	* anything since it's likely that we'll switch back pretty soon.
3209	*
3210	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3211	* and is supposed to determine which shadow paging and switcher to
3212	* use during init.
3213	*/
3214	case PGMMODE_REAL:
3215	case PGMMODE_PROTECTED:
3216	if ( enmShadowMode != PGMMODE_INVALID
3217	&& !HMIsEnabled(pVM) /* always switch in hm mode! */)
3218	break; /* (no change) */
3219
3220	switch (enmHostMode)
3221	{
3222	case SUPPAGINGMODE_32_BIT:
3223	case SUPPAGINGMODE_32_BIT_GLOBAL:
3224	enmShadowMode = PGMMODE_32_BIT;
3225	enmSwitcher = VMMSWITCHER_32_TO_32;
3226	break;
3227
3228	case SUPPAGINGMODE_PAE:
3229	case SUPPAGINGMODE_PAE_NX:
3230	case SUPPAGINGMODE_PAE_GLOBAL:
3231	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3232	enmShadowMode = PGMMODE_PAE;
3233	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3234	#ifdef DEBUG_bird
3235	if (RTEnvExist("VBOX_32BIT"))
3236	{
3237	enmShadowMode = PGMMODE_32_BIT;
3238	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3239	}
3240	#endif
3241	break;
3242
3243	case SUPPAGINGMODE_AMD64:
3244	case SUPPAGINGMODE_AMD64_GLOBAL:
3245	case SUPPAGINGMODE_AMD64_NX:
3246	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3247	enmShadowMode = PGMMODE_PAE;
3248	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3249	#ifdef DEBUG_bird
3250	if (RTEnvExist("VBOX_32BIT"))
3251	{
3252	enmShadowMode = PGMMODE_32_BIT;
3253	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3254	}
3255	#endif
3256	break;
3257
3258	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3259	}
3260	break;
3261
3262	case PGMMODE_32_BIT:
3263	switch (enmHostMode)
3264	{
3265	case SUPPAGINGMODE_32_BIT:
3266	case SUPPAGINGMODE_32_BIT_GLOBAL:
3267	enmShadowMode = PGMMODE_32_BIT;
3268	enmSwitcher = VMMSWITCHER_32_TO_32;
3269	break;
3270
3271	case SUPPAGINGMODE_PAE:
3272	case SUPPAGINGMODE_PAE_NX:
3273	case SUPPAGINGMODE_PAE_GLOBAL:
3274	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3275	enmShadowMode = PGMMODE_PAE;
3276	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3277	#ifdef DEBUG_bird
3278	if (RTEnvExist("VBOX_32BIT"))
3279	{
3280	enmShadowMode = PGMMODE_32_BIT;
3281	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3282	}
3283	#endif
3284	break;
3285
3286	case SUPPAGINGMODE_AMD64:
3287	case SUPPAGINGMODE_AMD64_GLOBAL:
3288	case SUPPAGINGMODE_AMD64_NX:
3289	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3290	enmShadowMode = PGMMODE_PAE;
3291	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3292	#ifdef DEBUG_bird
3293	if (RTEnvExist("VBOX_32BIT"))
3294	{
3295	enmShadowMode = PGMMODE_32_BIT;
3296	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3297	}
3298	#endif
3299	break;
3300
3301	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3302	}
3303	break;
3304
3305	case PGMMODE_PAE:
3306	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3307	switch (enmHostMode)
3308	{
3309	case SUPPAGINGMODE_32_BIT:
3310	case SUPPAGINGMODE_32_BIT_GLOBAL:
3311	enmShadowMode = PGMMODE_PAE;
3312	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3313	break;
3314
3315	case SUPPAGINGMODE_PAE:
3316	case SUPPAGINGMODE_PAE_NX:
3317	case SUPPAGINGMODE_PAE_GLOBAL:
3318	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3319	enmShadowMode = PGMMODE_PAE;
3320	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3321	break;
3322
3323	case SUPPAGINGMODE_AMD64:
3324	case SUPPAGINGMODE_AMD64_GLOBAL:
3325	case SUPPAGINGMODE_AMD64_NX:
3326	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3327	enmShadowMode = PGMMODE_PAE;
3328	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3329	break;
3330
3331	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3332	}
3333	break;
3334
3335	case PGMMODE_AMD64:
3336	case PGMMODE_AMD64_NX:
3337	switch (enmHostMode)
3338	{
3339	case SUPPAGINGMODE_32_BIT:
3340	case SUPPAGINGMODE_32_BIT_GLOBAL:
3341	enmShadowMode = PGMMODE_AMD64;
3342	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3343	break;
3344
3345	case SUPPAGINGMODE_PAE:
3346	case SUPPAGINGMODE_PAE_NX:
3347	case SUPPAGINGMODE_PAE_GLOBAL:
3348	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3349	enmShadowMode = PGMMODE_AMD64;
3350	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3351	break;
3352
3353	case SUPPAGINGMODE_AMD64:
3354	case SUPPAGINGMODE_AMD64_GLOBAL:
3355	case SUPPAGINGMODE_AMD64_NX:
3356	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3357	enmShadowMode = PGMMODE_AMD64;
3358	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3359	break;
3360
3361	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3362	}
3363	break;
3364
3365
3366	default:
3367	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3368	*penmSwitcher = VMMSWITCHER_INVALID;
3369	return PGMMODE_INVALID;
3370	}
3371	/* Override the shadow mode is nested paging is active. */
3372	pVM->pgm.s.fNestedPaging = HMIsNestedPagingActive(pVM);
3373	if (pVM->pgm.s.fNestedPaging)
3374	enmShadowMode = HMGetShwPagingMode(pVM);
3375
3376	*penmSwitcher = enmSwitcher;
3377	return enmShadowMode;
3378	}
3379
3380
3381	/**
3382	* Performs the actual mode change.
3383	* This is called by PGMChangeMode and pgmR3InitPaging().
3384	*
3385	* @returns VBox status code. May suspend or power off the VM on error, but this
3386	* will trigger using FFs and not status codes.
3387	*
3388	* @param pVM Pointer to the VM.
3389	* @param pVCpu Pointer to the VMCPU.
3390	* @param enmGuestMode The new guest mode. This is assumed to be different from
3391	* the current mode.
3392	*/
3393	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3394	{
3395	#if HC_ARCH_BITS == 32
3396	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3397	#endif
3398	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3399
3400	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3401	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3402
3403	/*
3404	* Calc the shadow mode and switcher.
3405	*/
3406	VMMSWITCHER enmSwitcher;
3407	PGMMODE enmShadowMode;
3408	enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3409
3410	#ifdef VBOX_WITH_RAW_MODE
3411	if ( enmSwitcher != VMMSWITCHER_INVALID
3412	&& !HMIsEnabled(pVM))
3413	{
3414	/*
3415	* Select new switcher.
3416	*/
3417	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3418	if (RT_FAILURE(rc))
3419	{
3420	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3421	return rc;
3422	}
3423	}
3424	#endif
3425
3426	/*
3427	* Exit old mode(s).
3428	*/
3429	#if HC_ARCH_BITS == 32
3430	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3431	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3432	&& enmShadowMode == PGMMODE_NESTED);
3433	#else
3434	const bool fForceShwEnterExit = false;
3435	#endif
3436	/* shadow */
3437	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3438	\|\| fForceShwEnterExit)
3439	{
3440	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3441	if (PGM_SHW_PFN(Exit, pVCpu))
3442	{
3443	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3444	if (RT_FAILURE(rc))
3445	{
3446	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3447	return rc;
3448	}
3449	}
3450
3451	}
3452	else
3453	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3454
3455	/* guest */
3456	if (PGM_GST_PFN(Exit, pVCpu))
3457	{
3458	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3459	if (RT_FAILURE(rc))
3460	{
3461	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3462	return rc;
3463	}
3464	}
3465
3466	/*
3467	* Load new paging mode data.
3468	*/
3469	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3470
3471	/*
3472	* Enter new shadow mode (if changed).
3473	*/
3474	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3475	\|\| fForceShwEnterExit)
3476	{
3477	int rc;
3478	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3479	switch (enmShadowMode)
3480	{
3481	case PGMMODE_32_BIT:
3482	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3483	break;
3484	case PGMMODE_PAE:
3485	case PGMMODE_PAE_NX:
3486	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3487	break;
3488	case PGMMODE_AMD64:
3489	case PGMMODE_AMD64_NX:
3490	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3491	break;
3492	case PGMMODE_NESTED:
3493	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3494	break;
3495	case PGMMODE_EPT:
3496	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3497	break;
3498	case PGMMODE_REAL:
3499	case PGMMODE_PROTECTED:
3500	default:
3501	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3502	return VERR_INTERNAL_ERROR;
3503	}
3504	if (RT_FAILURE(rc))
3505	{
3506	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3507	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3508	return rc;
3509	}
3510	}
3511
3512	/*
3513	* Always flag the necessary updates
3514	*/
3515	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3516
3517	/*
3518	* Enter the new guest and shadow+guest modes.
3519	*/
3520	int rc = -1;
3521	int rc2 = -1;
3522	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3523	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3524	switch (enmGuestMode)
3525	{
3526	case PGMMODE_REAL:
3527	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3528	switch (pVCpu->pgm.s.enmShadowMode)
3529	{
3530	case PGMMODE_32_BIT:
3531	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3532	break;
3533	case PGMMODE_PAE:
3534	case PGMMODE_PAE_NX:
3535	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3536	break;
3537	case PGMMODE_NESTED:
3538	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3539	break;
3540	case PGMMODE_EPT:
3541	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3542	break;
3543	case PGMMODE_AMD64:
3544	case PGMMODE_AMD64_NX:
3545	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3546	default: AssertFailed(); break;
3547	}
3548	break;
3549
3550	case PGMMODE_PROTECTED:
3551	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3552	switch (pVCpu->pgm.s.enmShadowMode)
3553	{
3554	case PGMMODE_32_BIT:
3555	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3556	break;
3557	case PGMMODE_PAE:
3558	case PGMMODE_PAE_NX:
3559	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3560	break;
3561	case PGMMODE_NESTED:
3562	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3563	break;
3564	case PGMMODE_EPT:
3565	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3566	break;
3567	case PGMMODE_AMD64:
3568	case PGMMODE_AMD64_NX:
3569	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3570	default: AssertFailed(); break;
3571	}
3572	break;
3573
3574	case PGMMODE_32_BIT:
3575	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3576	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3577	switch (pVCpu->pgm.s.enmShadowMode)
3578	{
3579	case PGMMODE_32_BIT:
3580	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3581	break;
3582	case PGMMODE_PAE:
3583	case PGMMODE_PAE_NX:
3584	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3585	break;
3586	case PGMMODE_NESTED:
3587	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3588	break;
3589	case PGMMODE_EPT:
3590	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3591	break;
3592	case PGMMODE_AMD64:
3593	case PGMMODE_AMD64_NX:
3594	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3595	default: AssertFailed(); break;
3596	}
3597	break;
3598
3599	case PGMMODE_PAE_NX:
3600	case PGMMODE_PAE:
3601	{
3602	uint32_t u32Dummy, u32Features;
3603
3604	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3605	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3606	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3607	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (System/Processor)"));
3608
3609	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3610	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3611	switch (pVCpu->pgm.s.enmShadowMode)
3612	{
3613	case PGMMODE_PAE:
3614	case PGMMODE_PAE_NX:
3615	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3616	break;
3617	case PGMMODE_NESTED:
3618	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3619	break;
3620	case PGMMODE_EPT:
3621	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3622	break;
3623	case PGMMODE_32_BIT:
3624	case PGMMODE_AMD64:
3625	case PGMMODE_AMD64_NX:
3626	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3627	default: AssertFailed(); break;
3628	}
3629	break;
3630	}
3631
3632	#ifdef VBOX_WITH_64_BITS_GUESTS
3633	case PGMMODE_AMD64_NX:
3634	case PGMMODE_AMD64:
3635	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3636	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3637	switch (pVCpu->pgm.s.enmShadowMode)
3638	{
3639	case PGMMODE_AMD64:
3640	case PGMMODE_AMD64_NX:
3641	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3642	break;
3643	case PGMMODE_NESTED:
3644	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3645	break;
3646	case PGMMODE_EPT:
3647	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3648	break;
3649	case PGMMODE_32_BIT:
3650	case PGMMODE_PAE:
3651	case PGMMODE_PAE_NX:
3652	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3653	default: AssertFailed(); break;
3654	}
3655	break;
3656	#endif
3657
3658	default:
3659	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3660	rc = VERR_NOT_IMPLEMENTED;
3661	break;
3662	}
3663
3664	/* status codes. */
3665	AssertRC(rc);
3666	AssertRC(rc2);
3667	if (RT_SUCCESS(rc))
3668	{
3669	rc = rc2;
3670	if (RT_SUCCESS(rc)) /* no informational status codes. */
3671	rc = VINF_SUCCESS;
3672	}
3673
3674	/* Notify HM as well. */
3675	HMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3676	return rc;
3677	}
3678
3679
3680	/**
3681	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3682	*
3683	* @returns VBox status code, fully asserted.
3684	* @param pVCpu Pointer to the VMCPU.
3685	*/
3686	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3687	{
3688	/* Unmap the old CR3 value before flushing everything. */
3689	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3690	AssertRC(rc);
3691
3692	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3693	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3694	AssertRC(rc);
3695	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3696	return rc;
3697	}
3698
3699
3700	/**
3701	* Called by pgmPoolFlushAllInt after flushing the pool.
3702	*
3703	* @returns VBox status code, fully asserted.
3704	* @param pVM Pointer to the VM.
3705	* @param pVCpu Pointer to the VMCPU.
3706	*/
3707	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3708	{
3709	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3710	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3711	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3712	AssertRCReturn(rc, rc);
3713	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3714
3715	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3716	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3717	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3718	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3719	return rc;
3720	}
3721
3722
3723	/**
3724	* Called by PGMR3PhysSetA20 after changing the A20 state.
3725	*
3726	* @param pVCpu Pointer to the VMCPU.
3727	*/
3728	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
3729	{
3730	/** @todo Probably doing a bit too much here. */
3731	int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
3732	AssertReleaseRC(rc);
3733	rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
3734	AssertReleaseRC(rc);
3735	}
3736
3737
3738	#ifdef VBOX_WITH_DEBUGGER
3739
3740	/**
3741	* @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
3742	*/
3743	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3744	{
3745	/*
3746	* Validate input.
3747	*/
3748	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3749	PVM pVM = pUVM->pVM;
3750	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
3751
3752	if (!cArgs)
3753	{
3754	/*
3755	* Print the list of error injection locations with status.
3756	*/
3757	DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
3758	DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3759	}
3760	else
3761	{
3762	/*
3763	* String switch on where to inject the error.
3764	*/
3765	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
3766	const char *pszWhere = paArgs[0].u.pszString;
3767	if (!strcmp(pszWhere, "handy"))
3768	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
3769	else
3770	return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
3771	DBGCCmdHlpPrintf(pCmdHlp, "done\n");
3772	}
3773	return VINF_SUCCESS;
3774	}
3775
3776
3777	/**
3778	* @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
3779	*/
3780	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3781	{
3782	/*
3783	* Validate input.
3784	*/
3785	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3786	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3787	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3788	if (!pVCpu)
3789	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3790
3791	/*
3792	* Force page directory sync.
3793	*/
3794	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3795
3796	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
3797	if (RT_FAILURE(rc))
3798	return rc;
3799
3800	return VINF_SUCCESS;
3801	}
3802
3803	#ifdef VBOX_STRICT
3804
3805	/**
3806	* EMT callback for pgmR3CmdAssertCR3.
3807	*
3808	* @returns VBox status code.
3809	* @param pUVM The user mode VM handle.
3810	* @param pcErrors Where to return the error count.
3811	*/
3812	static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
3813	{
3814	PVM pVM = pUVM->pVM;
3815	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3816	PVMCPU pVCpu = VMMGetCpu(pVM);
3817
3818	*pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
3819
3820	return VINF_SUCCESS;
3821	}
3822
3823
3824	/**
3825	* @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
3826	*/
3827	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3828	{
3829	/*
3830	* Validate input.
3831	*/
3832	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3833	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3834
3835	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
3836	if (RT_FAILURE(rc))
3837	return rc;
3838
3839	unsigned cErrors = 0;
3840	rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
3841	if (RT_FAILURE(rc))
3842	return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
3843	if (cErrors > 0)
3844	return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
3845	return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
3846	}
3847
3848	#endif /* VBOX_STRICT */
3849
3850	/**
3851	* @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
3852	*/
3853	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3854	{
3855	/*
3856	* Validate input.
3857	*/
3858	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3859	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3860	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3861	if (!pVCpu)
3862	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3863
3864	/*
3865	* Force page directory sync.
3866	*/
3867	int rc;
3868	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3869	{
3870	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3871	rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
3872	}
3873	else
3874	{
3875	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3876	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3877	rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
3878	}
3879	return rc;
3880	}
3881
3882
3883	/**
3884	* @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
3885	*/
3886	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3887	{
3888	/*
3889	* Validate input.
3890	*/
3891	NOREF(pCmd);
3892	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3893	PVM pVM = pUVM->pVM;
3894	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 \|\| cArgs == 2);
3895	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType == DBGCVAR_TYPE_STRING);
3896	if (cArgs == 2)
3897	{
3898	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[1].enmType == DBGCVAR_TYPE_STRING);
3899	if (strcmp(paArgs[1].u.pszString, "nozero"))
3900	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
3901	}
3902	bool fIncZeroPgs = cArgs < 2;
3903
3904	/*
3905	* Open the output file and get the ram parameters.
3906	*/
3907	RTFILE hFile;
3908	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
3909	if (RT_FAILURE(rc))
3910	return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
3911
3912	uint32_t cbRamHole = 0;
3913	CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
3914	uint64_t cbRam = 0;
3915	CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
3916	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
3917
3918	/*
3919	* Dump the physical memory, page by page.
3920	*/
3921	RTGCPHYS GCPhys = 0;
3922	char abZeroPg[PAGE_SIZE];
3923	RT_ZERO(abZeroPg);
3924
3925	pgmLock(pVM);
3926	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3927	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
3928	pRam = pRam->pNextR3)
3929	{
3930	/* fill the gap */
3931	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
3932	{
3933	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
3934	{
3935	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3936	GCPhys += PAGE_SIZE;
3937	}
3938	}
3939
3940	PCPGMPAGE pPage = &pRam->aPages[0];
3941	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
3942	{
3943	if ( PGM_PAGE_IS_ZERO(pPage)
3944	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3945	{
3946	if (fIncZeroPgs)
3947	{
3948	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3949	if (RT_FAILURE(rc))
3950	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3951	}
3952	}
3953	else
3954	{
3955	switch (PGM_PAGE_GET_TYPE(pPage))
3956	{
3957	case PGMPAGETYPE_RAM:
3958	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
3959	case PGMPAGETYPE_ROM:
3960	case PGMPAGETYPE_MMIO2:
3961	{
3962	void const *pvPage;
3963	PGMPAGEMAPLOCK Lock;
3964	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
3965	if (RT_SUCCESS(rc))
3966	{
3967	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
3968	PGMPhysReleasePageMappingLock(pVM, &Lock);
3969	if (RT_FAILURE(rc))
3970	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3971	}
3972	else
3973	DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3974	break;
3975	}
3976
3977	default:
3978	AssertFailed();
3979	case PGMPAGETYPE_MMIO:
3980	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3981	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
3982	if (fIncZeroPgs)
3983	{
3984	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3985	if (RT_FAILURE(rc))
3986	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3987	}
3988	break;
3989	}
3990	}
3991
3992
3993	/* advance */
3994	GCPhys += PAGE_SIZE;
3995	pPage++;
3996	}
3997	}
3998	pgmUnlock(pVM);
3999
4000	RTFileClose(hFile);
4001	if (RT_SUCCESS(rc))
4002	return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4003	return VINF_SUCCESS;
4004	}
4005
4006	#endif /* VBOX_WITH_DEBUGGER */
4007
4008	/**
4009	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4010	*/
4011	typedef struct PGMCHECKINTARGS
4012	{
4013	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4014	PPGMPHYSHANDLER pPrevPhys;
4015	PPGMVIRTHANDLER pPrevVirt;
4016	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4017	PVM pVM;
4018	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4019
4020	/**
4021	* Validate a node in the physical handler tree.
4022	*
4023	* @returns 0 on if ok, other wise 1.
4024	* @param pNode The handler node.
4025	* @param pvUser pVM.
4026	*/
4027	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4028	{
4029	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4030	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4031	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4032	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,
4033	("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4034	AssertReleaseMsg( !pArgs->pPrevPhys
4035	\|\| ( pArgs->fLeftToRight
4036	? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key
4037	: pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4038	("pPrevPhys=%p %RGp-%RGp %s\n"
4039	" pCur=%p %RGp-%RGp %s\n",
4040	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4041	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4042	pArgs->pPrevPhys = pCur;
4043	return 0;
4044	}
4045
4046
4047	/**
4048	* Validate a node in the virtual handler tree.
4049	*
4050	* @returns 0 on if ok, other wise 1.
4051	* @param pNode The handler node.
4052	* @param pvUser pVM.
4053	*/
4054	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4055	{
4056	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4057	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4058	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4059	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4060	AssertReleaseMsg( !pArgs->pPrevVirt
4061	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4062	("pPrevVirt=%p %RGv-%RGv %s\n"
4063	" pCur=%p %RGv-%RGv %s\n",
4064	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4065	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4066	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4067	{
4068	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4069	("pCur=%p %RGv-%RGv %s\n"
4070	"iPage=%d offVirtHandle=%#x expected %#x\n",
4071	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4072	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4073	}
4074	pArgs->pPrevVirt = pCur;
4075	return 0;
4076	}
4077
4078
4079	/**
4080	* Validate a node in the virtual handler tree.
4081	*
4082	* @returns 0 on if ok, other wise 1.
4083	* @param pNode The handler node.
4084	* @param pvUser pVM.
4085	*/
4086	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4087	{
4088	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4089	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4090	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4091	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4092	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4093	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4094	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4095	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4096	" pCur=%p %RGp-%RGp\n",
4097	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4098	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4099	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4100	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4101	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4102	" pCur=%p %RGp-%RGp\n",
4103	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4104	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4105	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4106	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4107	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4108	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4109	{
4110	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4111	for (;;)
4112	{
4113	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4114	AssertReleaseMsg(pCur2 != pCur,
4115	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4116	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4117	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4118	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4119	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4120	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4121	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4122	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4123	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4124	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4125	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4126	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4127	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4128	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4129	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4130	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4131	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4132	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4133	break;
4134	}
4135	}
4136
4137	pArgs->pPrevPhys2Virt = pCur;
4138	return 0;
4139	}
4140
4141
4142	/**
4143	* Perform an integrity check on the PGM component.
4144	*
4145	* @returns VINF_SUCCESS if everything is fine.
4146	* @returns VBox error status after asserting on integrity breach.
4147	* @param pVM Pointer to the VM.
4148	*/
4149	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4150	{
4151	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4152
4153	/*
4154	* Check the trees.
4155	*/
4156	int cErrors = 0;
4157	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4158	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4159	PGMCHECKINTARGS Args = s_LeftToRight;
4160	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4161	Args = s_RightToLeft;
4162	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4163	Args = s_LeftToRight;
4164	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4165	Args = s_RightToLeft;
4166	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4167	Args = s_LeftToRight;
4168	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4169	Args = s_RightToLeft;
4170	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4171	Args = s_LeftToRight;
4172	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4173	Args = s_RightToLeft;
4174	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4175
4176	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4177	}
4178

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 55808

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