PGM.cpp@ 55890

Last change on this file since 55890 was 55889, checked in by vboxsync, 10 years ago
VMM: Split up virtual handlers just like the physical ones, such that the kind+callbacks are stored seprately from the actual handler registration. This should hopefully save a byte or two when adding more callbacks. Implemented the pvUser for ring-3 callbacks.
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1	/* $Id: PGM.cpp 55889 2015-05-17 18:01:37Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred
30	* to as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	* Note! The intermediate memory context is also used for 64-bit guest
85	* execution on 32-bit hosts. Because we need to load 64-bit registers
86	* prior to switching to guest context, we need to be in 64-bit mode
87	* first. So, HM has some 64-bit worker routines in VMMRC.rc that get
88	* invoked via the special world switcher code in LegacyToAMD64.asm.
89	*
90	*
91	* @subsection subsec_pgm_int_gc Guest Context Mappings
92	*
93	* During assignment and relocation of a guest context mapping the intermediate
94	* memory context is used to verify the new location.
95	*
96	* Guest context mappings are currently restricted to below 4GB, for reasons
97	* of simplicity. This may change when we implement AMD64 support.
98	*
99	*
100	*
101	*
102	* @section sec_pgm_misc Misc
103	*
104	*
105	* @subsection sec_pgm_misc_A20 The A20 Gate
106	*
107	* PGM implements the A20 gate masking when translating a virtual guest address
108	* into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
109	* the code reading the guest page table entries during shadowing. The masking
110	* is done consistenly for all CPU modes, paged ones included. Large pages are
111	* also masked correctly. (On current CPUs, experiments indicates that AMD does
112	* not apply A20M in paged modes and intel only does it for the 2nd MB of
113	* memory.)
114	*
115	* The A20 gate implementation is per CPU core. It can be configured on a per
116	* core basis via the keyboard device and PC architecture device. This is
117	* probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
118	* guest OSes try pushing things anyway, so who cares. (On current real systems
119	* the A20M signal is probably only sent to the boot CPU and it affects all
120	* thread and probably all cores in that package.)
121	*
122	* The keyboard device and the PC architecture device doesn't OR their A20
123	* config bits together, rather they are currently implemented such that they
124	* mirror the CPU state. So, flipping the bit in either of them will change the
125	* A20 state. (On real hardware the bits of the two devices should probably be
126	* ORed together to indicate enabled, i.e. both needs to be cleared to disable
127	* A20 masking.)
128	*
129	* The A20 state will change immediately, transmeta fashion. There is no delays
130	* due to buses, wiring or other physical stuff. (On real hardware there are
131	* normally delays, the delays differs between the two devices and probably also
132	* between chipsets and CPU generations. Note that it's said that transmeta CPUs
133	* does the change immediately like us, they apparently intercept/handles the
134	* port accesses in microcode. Neat.)
135	*
136	* @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
137	*
138	*
139	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
140	*
141	* The differences between legacy PAE and long mode PAE are:
142	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
143	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
144	* usual meanings while 6 is ignored (AMD). This means that upon switching to
145	* legacy PAE mode we'll have to clear these bits and when going to long mode
146	* they must be set. This applies to both intermediate and shadow contexts,
147	* however we don't need to do it for the intermediate one since we're
148	* executing with CR0.WP at that time.
149	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
150	* a page aligned one is required.
151	*
152	*
153	* @section sec_pgm_handlers Access Handlers
154	*
155	* Placeholder.
156	*
157	*
158	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
159	*
160	* Placeholder.
161	*
162	*
163	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
164	*
165	* We currently implement three types of virtual access handlers: ALL, WRITE
166	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERKIND for some more details.
167	*
168	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
169	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
170	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
171	* rest of this section is going to be about these handlers.
172	*
173	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
174	* how successful this is gonna be...
175	*
176	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
177	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
178	* and create a new node that is inserted into the AVL tree (range key). Then
179	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
180	*
181	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
182	*
183	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
184	* via the current guest CR3 and update the physical page -> virtual handler
185	* translation. Needless to say, this doesn't exactly scale very well. If any changes
186	* are detected, it will flag a virtual bit update just like we did on registration.
187	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
188	*
189	* 2b. The virtual bit update process will iterate all the pages covered by all the
190	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
191	* virtual handlers on that page.
192	*
193	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
194	* we don't miss any alias mappings of the monitored pages.
195	*
196	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
197	*
198	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
199	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
200	* will call the handlers like in the next step. If the physical mapping has
201	* changed we will - some time in the future - perform a handler callback
202	* (optional) and update the physical -> virtual handler cache.
203	*
204	* 4. \#PF(,write) on a page in the range. This will cause the handler to
205	* be invoked.
206	*
207	* 5. The guest invalidates the page and changes the physical backing or
208	* unmaps it. This should cause the invalidation callback to be invoked
209	* (it might not yet be 100% perfect). Exactly what happens next... is
210	* this where we mess up and end up out of sync for a while?
211	*
212	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
213	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
214	* this handler to NONE and trigger a full PGM resync (basically the same
215	* as int step 1). Which means 2 is executed again.
216	*
217	*
218	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
219	*
220	* There is a bunch of things that needs to be done to make the virtual handlers
221	* work 100% correctly and work more efficiently.
222	*
223	* The first bit hasn't been implemented yet because it's going to slow the
224	* whole mess down even more, and besides it seems to be working reliably for
225	* our current uses. OTOH, some of the optimizations might end up more or less
226	* implementing the missing bits, so we'll see.
227	*
228	* On the optimization side, the first thing to do is to try avoid unnecessary
229	* cache flushing. Then try team up with the shadowing code to track changes
230	* in mappings by means of access to them (shadow in), updates to shadows pages,
231	* invlpg, and shadow PT discarding (perhaps).
232	*
233	* Some idea that have popped up for optimization for current and new features:
234	* - bitmap indicating where there are virtual handlers installed.
235	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
236	* - Further optimize this by min/max (needs min/max avl getters).
237	* - Shadow page table entry bit (if any left)?
238	*
239	*/
240
241
242	/** @page pg_pgm_phys PGM Physical Guest Memory Management
243	*
244	*
245	* Objectives:
246	* - Guest RAM over-commitment using memory ballooning,
247	* zero pages and general page sharing.
248	* - Moving or mirroring a VM onto a different physical machine.
249	*
250	*
251	* @subsection subsec_pgmPhys_Definitions Definitions
252	*
253	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
254	* machinery associated with it.
255	*
256	*
257	*
258	*
259	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
260	*
261	* Initially we map all guest memory to the (per VM) zero page, which
262	* means that none of the read functions will cause pages to be allocated.
263	*
264	* Exception, access bit in page tables that have been shared. This must
265	* be handled, but we must also make sure PGMGst*Modify doesn't make
266	* unnecessary modifications.
267	*
268	* Allocation points:
269	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
270	* - Replacing a zero page mapping at \#PF.
271	* - Replacing a shared page mapping at \#PF.
272	* - ROM registration (currently MMR3RomRegister).
273	* - VM restore (pgmR3Load).
274	*
275	* For the first three it would make sense to keep a few pages handy
276	* until we've reached the max memory commitment for the VM.
277	*
278	* For the ROM registration, we know exactly how many pages we need
279	* and will request these from ring-0. For restore, we will save
280	* the number of non-zero pages in the saved state and allocate
281	* them up front. This would allow the ring-0 component to refuse
282	* the request if the isn't sufficient memory available for VM use.
283	*
284	* Btw. for both ROM and restore allocations we won't be requiring
285	* zeroed pages as they are going to be filled instantly.
286	*
287	*
288	* @subsection subsec_pgmPhys_FreePage Freeing a page
289	*
290	* There are a few points where a page can be freed:
291	* - After being replaced by the zero page.
292	* - After being replaced by a shared page.
293	* - After being ballooned by the guest additions.
294	* - At reset.
295	* - At restore.
296	*
297	* When freeing one or more pages they will be returned to the ring-0
298	* component and replaced by the zero page.
299	*
300	* The reasoning for clearing out all the pages on reset is that it will
301	* return us to the exact same state as on power on, and may thereby help
302	* us reduce the memory load on the system. Further it might have a
303	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
304	*
305	* On restore, as mention under the allocation topic, pages should be
306	* freed / allocated depending on how many is actually required by the
307	* new VM state. The simplest approach is to do like on reset, and free
308	* all non-ROM pages and then allocate what we need.
309	*
310	* A measure to prevent some fragmentation, would be to let each allocation
311	* chunk have some affinity towards the VM having allocated the most pages
312	* from it. Also, try make sure to allocate from allocation chunks that
313	* are almost full. Admittedly, both these measures might work counter to
314	* our intentions and its probably not worth putting a lot of effort,
315	* cpu time or memory into this.
316	*
317	*
318	* @subsection subsec_pgmPhys_SharePage Sharing a page
319	*
320	* The basic idea is that there there will be a idle priority kernel
321	* thread walking the non-shared VM pages hashing them and looking for
322	* pages with the same checksum. If such pages are found, it will compare
323	* them byte-by-byte to see if they actually are identical. If found to be
324	* identical it will allocate a shared page, copy the content, check that
325	* the page didn't change while doing this, and finally request both the
326	* VMs to use the shared page instead. If the page is all zeros (special
327	* checksum and byte-by-byte check) it will request the VM that owns it
328	* to replace it with the zero page.
329	*
330	* To make this efficient, we will have to make sure not to try share a page
331	* that will change its contents soon. This part requires the most work.
332	* A simple idea would be to request the VM to write monitor the page for
333	* a while to make sure it isn't modified any time soon. Also, it may
334	* make sense to skip pages that are being write monitored since this
335	* information is readily available to the thread if it works on the
336	* per-VM guest memory structures (presently called PGMRAMRANGE).
337	*
338	*
339	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
340	*
341	* The pages are organized in allocation chunks in ring-0, this is a necessity
342	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
343	* could easily work on a page-by-page basis if we liked. Whether this is possible
344	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
345	* become a problem as part of the idea here is that we wish to return memory to
346	* the host system.
347	*
348	* For instance, starting two VMs at the same time, they will both allocate the
349	* guest memory on-demand and if permitted their page allocations will be
350	* intermixed. Shut down one of the two VMs and it will be difficult to return
351	* any memory to the host system because the page allocation for the two VMs are
352	* mixed up in the same allocation chunks.
353	*
354	* To further complicate matters, when pages are freed because they have been
355	* ballooned or become shared/zero the whole idea is that the page is supposed
356	* to be reused by another VM or returned to the host system. This will cause
357	* allocation chunks to contain pages belonging to different VMs and prevent
358	* returning memory to the host when one of those VM shuts down.
359	*
360	* The only way to really deal with this problem is to move pages. This can
361	* either be done at VM shutdown and or by the idle priority worker thread
362	* that will be responsible for finding sharable/zero pages. The mechanisms
363	* involved for coercing a VM to move a page (or to do it for it) will be
364	* the same as when telling it to share/zero a page.
365	*
366	*
367	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
368	*
369	* There's a difficult balance between keeping the per-page tracking structures
370	* (global and guest page) easy to use and keeping them from eating too much
371	* memory. We have limited virtual memory resources available when operating in
372	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
373	* tracking structures will be attempted designed such that we can deal with up
374	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
375	*
376	*
377	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
378	*
379	* @see pg_GMM
380	*
381	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
382	*
383	* Fixed info is the physical address of the page (HCPhys) and the page id
384	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
385	* Today we've restricting ourselves to 40(-12) bits because this is the current
386	* restrictions of all AMD64 implementations (I think Barcelona will up this
387	* to 48(-12) bits, not that it really matters) and I needed the bits for
388	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
389	* decent range for the page id: 2^(28+12) = 1024TB.
390	*
391	* In additions to these, we'll have to keep maintaining the page flags as we
392	* currently do. Although it wouldn't harm to optimize these quite a bit, like
393	* for instance the ROM shouldn't depend on having a write handler installed
394	* in order for it to become read-only. A RO/RW bit should be considered so
395	* that the page syncing code doesn't have to mess about checking multiple
396	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
397	* figure out how to setup a shadow PTE. But this of course, is second
398	* priority at present. Current this requires 12 bits, but could probably
399	* be optimized to ~8.
400	*
401	* Then there's the 24 bits used to track which shadow page tables are
402	* currently mapping a page for the purpose of speeding up physical
403	* access handlers, and thereby the page pool cache. More bit for this
404	* purpose wouldn't hurt IIRC.
405	*
406	* Then there is a new bit in which we need to record what kind of page
407	* this is, shared, zero, normal or write-monitored-normal. This'll
408	* require 2 bits. One bit might be needed for indicating whether a
409	* write monitored page has been written to. And yet another one or
410	* two for tracking migration status. 3-4 bits total then.
411	*
412	* Whatever is left will can be used to record the sharabilitiy of a
413	* page. The page checksum will not be stored in the per-VM table as
414	* the idle thread will not be permitted to do modifications to it.
415	* It will instead have to keep its own working set of potentially
416	* shareable pages and their check sums and stuff.
417	*
418	* For the present we'll keep the current packing of the
419	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
420	* we'll have to change it to a struct with a total of 128-bits at
421	* our disposal.
422	*
423	* The initial layout will be like this:
424	* @verbatim
425	RTHCPHYS HCPhys; The current stuff.
426	63:40 Current shadow PT tracking stuff.
427	39:12 The physical page frame number.
428	11:0 The current flags.
429	uint32_t u28PageId : 28; The page id.
430	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
431	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
432	uint32_t u1Reserved : 1; Reserved for later.
433	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
434	@endverbatim
435	*
436	* The final layout will be something like this:
437	* @verbatim
438	RTHCPHYS HCPhys; The current stuff.
439	63:48 High page id (12+).
440	47:12 The physical page frame number.
441	11:0 Low page id.
442	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
443	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
444	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
445	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
446	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
447	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
448	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
449	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
450	@endverbatim
451	*
452	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
453	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
454	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
455	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
456	*
457	* A couple of cost examples for the total cost per-VM + kernel.
458	* 32-bit Windows and 32-bit linux:
459	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
460	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
461	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
462	* 64-bit Windows and 64-bit linux:
463	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
464	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
465	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
466	*
467	* UPDATE - 2007-09-27:
468	* Will need a ballooned flag/state too because we cannot
469	* trust the guest 100% and reporting the same page as ballooned more
470	* than once will put the GMM off balance.
471	*
472	*
473	* @subsection subsec_pgmPhys_Serializing Serializing Access
474	*
475	* Initially, we'll try a simple scheme:
476	*
477	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
478	* by the EMT thread of that VM while in the pgm critsect.
479	* - Other threads in the VM process that needs to make reliable use of
480	* the per-VM RAM tracking structures will enter the critsect.
481	* - No process external thread or kernel thread will ever try enter
482	* the pgm critical section, as that just won't work.
483	* - The idle thread (and similar threads) doesn't not need 100% reliable
484	* data when performing it tasks as the EMT thread will be the one to
485	* do the actual changes later anyway. So, as long as it only accesses
486	* the main ram range, it can do so by somehow preventing the VM from
487	* being destroyed while it works on it...
488	*
489	* - The over-commitment management, including the allocating/freeing
490	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
491	* more mundane mutex implementation is broken on Linux).
492	* - A separate mutex is protecting the set of allocation chunks so
493	* that pages can be shared or/and freed up while some other VM is
494	* allocating more chunks. This mutex can be take from under the other
495	* one, but not the other way around.
496	*
497	*
498	* @subsection subsec_pgmPhys_Request VM Request interface
499	*
500	* When in ring-0 it will become necessary to send requests to a VM so it can
501	* for instance move a page while defragmenting during VM destroy. The idle
502	* thread will make use of this interface to request VMs to setup shared
503	* pages and to perform write monitoring of pages.
504	*
505	* I would propose an interface similar to the current VMReq interface, similar
506	* in that it doesn't require locking and that the one sending the request may
507	* wait for completion if it wishes to. This shouldn't be very difficult to
508	* realize.
509	*
510	* The requests themselves are also pretty simple. They are basically:
511	* -# Check that some precondition is still true.
512	* -# Do the update.
513	* -# Update all shadow page tables involved with the page.
514	*
515	* The 3rd step is identical to what we're already doing when updating a
516	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
517	*
518	*
519	*
520	* @section sec_pgmPhys_MappingCaches Mapping Caches
521	*
522	* In order to be able to map in and out memory and to be able to support
523	* guest with more RAM than we've got virtual address space, we'll employing
524	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
525	* however on 32-bit darwin the ring-0 code is running in a different memory
526	* context and therefore needs a separate cache. In raw-mode context we also
527	* need a separate cache. The 32-bit darwin mapping cache and the one for
528	* raw-mode context share a lot of code, see PGMRZDYNMAP.
529	*
530	*
531	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
532	*
533	* We've considered implementing the ring-3 mapping cache page based but found
534	* that this was bother some when one had to take into account TLBs+SMP and
535	* portability (missing the necessary APIs on several platforms). There were
536	* also some performance concerns with this approach which hadn't quite been
537	* worked out.
538	*
539	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
540	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
541	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
542	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
543	* costly than a single page, although how much more costly is uncertain. We'll
544	* try address this by using a very big cache, preferably bigger than the actual
545	* VM RAM size if possible. The current VM RAM sizes should give some idea for
546	* 32-bit boxes, while on 64-bit we can probably get away with employing an
547	* unlimited cache.
548	*
549	* The cache have to parts, as already indicated, the ring-3 side and the
550	* ring-0 side.
551	*
552	* The ring-0 will be tied to the page allocator since it will operate on the
553	* memory objects it contains. It will therefore require the first ring-0 mutex
554	* discussed in @ref subsec_pgmPhys_Serializing. We
555	* some double house keeping wrt to who has mapped what I think, since both
556	* VMMR0.r0 and RTR0MemObj will keep track of mapping relations
557	*
558	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
559	* require anyone that desires to do changes to the mapping cache to do that
560	* from within this critsect. Alternatively, we could employ a separate critsect
561	* for serializing changes to the mapping cache as this would reduce potential
562	* contention with other threads accessing mappings unrelated to the changes
563	* that are in process. We can see about this later, contention will show
564	* up in the statistics anyway, so it'll be simple to tell.
565	*
566	* The organization of the ring-3 part will be very much like how the allocation
567	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
568	* having to walk the tree all the time, we'll have a couple of lookaside entries
569	* like in we do for I/O ports and MMIO in IOM.
570	*
571	* The simplified flow of a PGMPhysRead/Write function:
572	* -# Enter the PGM critsect.
573	* -# Lookup GCPhys in the ram ranges and get the Page ID.
574	* -# Calc the Allocation Chunk ID from the Page ID.
575	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
576	* If not found in cache:
577	* -# Call ring-0 and request it to be mapped and supply
578	* a chunk to be unmapped if the cache is maxed out already.
579	* -# Insert the new mapping into the AVL tree (id + R3 address).
580	* -# Update the relevant lookaside entry and return the mapping address.
581	* -# Do the read/write according to monitoring flags and everything.
582	* -# Leave the critsect.
583	*
584	*
585	* @section sec_pgmPhys_Fallback Fallback
586	*
587	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
588	* API and thus require a fallback.
589	*
590	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
591	* will return to the ring-3 caller (and later ring-0) and asking it to seed
592	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
593	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
594	* "SeededAllocPages" call to ring-0.
595	*
596	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
597	* all page sharing (zero page detection will continue). It will also force
598	* all allocations to come from the VM which seeded the page. Both these
599	* measures are taken to make sure that there will never be any need for
600	* mapping anything into ring-3 - everything will be mapped already.
601	*
602	* Whether we'll continue to use the current MM locked memory management
603	* for this I don't quite know (I'd prefer not to and just ditch that all
604	* together), we'll see what's simplest to do.
605	*
606	*
607	*
608	* @section sec_pgmPhys_Changes Changes
609	*
610	* Breakdown of the changes involved?
611	*/
612
613	/*******************************************************************************
614	* Header Files *
615	*******************************************************************************/
616	#define LOG_GROUP LOG_GROUP_PGM
617	#include <VBox/vmm/dbgf.h>
618	#include <VBox/vmm/pgm.h>
619	#include <VBox/vmm/cpum.h>
620	#include <VBox/vmm/iom.h>
621	#include <VBox/sup.h>
622	#include <VBox/vmm/mm.h>
623	#include <VBox/vmm/em.h>
624	#include <VBox/vmm/stam.h>
625	#ifdef VBOX_WITH_REM
626	# include <VBox/vmm/rem.h>
627	#endif
628	#include <VBox/vmm/selm.h>
629	#include <VBox/vmm/ssm.h>
630	#include <VBox/vmm/hm.h>
631	#include "PGMInternal.h"
632	#include <VBox/vmm/vm.h>
633	#include <VBox/vmm/uvm.h>
634	#include "PGMInline.h"
635
636	#include <VBox/dbg.h>
637	#include <VBox/param.h>
638	#include <VBox/err.h>
639
640	#include <iprt/asm.h>
641	#include <iprt/asm-amd64-x86.h>
642	#include <iprt/assert.h>
643	#include <iprt/env.h>
644	#include <iprt/mem.h>
645	#include <iprt/file.h>
646	#include <iprt/string.h>
647	#include <iprt/thread.h>
648
649
650	/*******************************************************************************
651	* Structures and Typedefs *
652	*******************************************************************************/
653	/**
654	* Argument package for pgmR3RElocatePhysHnadler, pgmR3RelocateVirtHandler and
655	* pgmR3RelocateHyperVirtHandler.
656	*/
657	typedef struct PGMRELOCHANDLERARGS
658	{
659	RTGCINTPTR offDelta;
660	PVM pVM;
661	} PGMRELOCHANDLERARGS;
662	/** Pointer to a page access handlere relocation argument package. */
663	typedef PGMRELOCHANDLERARGS const *PCPGMRELOCHANDLERARGS;
664
665
666	/*******************************************************************************
667	* Internal Functions *
668	*******************************************************************************/
669	static int pgmR3InitPaging(PVM pVM);
670	static int pgmR3InitStats(PVM pVM);
671	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
672	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
673	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
674	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
675	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
676	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
677	#ifdef VBOX_STRICT
678	static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
679	#endif
680	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
681	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
682	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
683
684	#ifdef VBOX_WITH_DEBUGGER
685	static FNDBGCCMD pgmR3CmdError;
686	static FNDBGCCMD pgmR3CmdSync;
687	static FNDBGCCMD pgmR3CmdSyncAlways;
688	# ifdef VBOX_STRICT
689	static FNDBGCCMD pgmR3CmdAssertCR3;
690	# endif
691	static FNDBGCCMD pgmR3CmdPhysToFile;
692	#endif
693
694
695	/*******************************************************************************
696	* Global Variables *
697	*******************************************************************************/
698	#ifdef VBOX_WITH_DEBUGGER
699	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
700	static const DBGCVARDESC g_aPgmErrorArgs[] =
701	{
702	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
703	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
704	};
705
706	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
707	{
708	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
709	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
710	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
711	};
712
713	# ifdef DEBUG_sandervl
714	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
715	{
716	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
717	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
718	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
719	};
720	# endif
721
722	/** Command descriptors. */
723	static const DBGCCMD g_aCmds[] =
724	{
725	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
726	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
727	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
728	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
729	# ifdef VBOX_STRICT
730	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
731	# ifdef VBOX_WITH_PAGE_SHARING
732	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
733	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
734	# endif
735	# endif
736	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
737	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
738	};
739	#endif
740
741
742
743
744	/*
745	* Shadow - 32-bit mode
746	*/
747	#define PGM_SHW_TYPE PGM_TYPE_32BIT
748	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
749	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
750	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
751	#include "PGMShw.h"
752
753	/* Guest - real mode */
754	#define PGM_GST_TYPE PGM_TYPE_REAL
755	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
756	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
757	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
758	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
759	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
760	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
761	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
762	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
763	#include "PGMBth.h"
764	#include "PGMGstDefs.h"
765	#include "PGMGst.h"
766	#undef BTH_PGMPOOLKIND_PT_FOR_PT
767	#undef BTH_PGMPOOLKIND_ROOT
768	#undef PGM_BTH_NAME
769	#undef PGM_BTH_NAME_RC_STR
770	#undef PGM_BTH_NAME_R0_STR
771	#undef PGM_GST_TYPE
772	#undef PGM_GST_NAME
773	#undef PGM_GST_NAME_RC_STR
774	#undef PGM_GST_NAME_R0_STR
775
776	/* Guest - protected mode */
777	#define PGM_GST_TYPE PGM_TYPE_PROT
778	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
779	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
780	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
781	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
782	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
783	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
784	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
785	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
786	#include "PGMBth.h"
787	#include "PGMGstDefs.h"
788	#include "PGMGst.h"
789	#undef BTH_PGMPOOLKIND_PT_FOR_PT
790	#undef BTH_PGMPOOLKIND_ROOT
791	#undef PGM_BTH_NAME
792	#undef PGM_BTH_NAME_RC_STR
793	#undef PGM_BTH_NAME_R0_STR
794	#undef PGM_GST_TYPE
795	#undef PGM_GST_NAME
796	#undef PGM_GST_NAME_RC_STR
797	#undef PGM_GST_NAME_R0_STR
798
799	/* Guest - 32-bit mode */
800	#define PGM_GST_TYPE PGM_TYPE_32BIT
801	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
802	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
803	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
804	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
805	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
806	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
807	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
808	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
809	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
810	#include "PGMBth.h"
811	#include "PGMGstDefs.h"
812	#include "PGMGst.h"
813	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
814	#undef BTH_PGMPOOLKIND_PT_FOR_PT
815	#undef BTH_PGMPOOLKIND_ROOT
816	#undef PGM_BTH_NAME
817	#undef PGM_BTH_NAME_RC_STR
818	#undef PGM_BTH_NAME_R0_STR
819	#undef PGM_GST_TYPE
820	#undef PGM_GST_NAME
821	#undef PGM_GST_NAME_RC_STR
822	#undef PGM_GST_NAME_R0_STR
823
824	#undef PGM_SHW_TYPE
825	#undef PGM_SHW_NAME
826	#undef PGM_SHW_NAME_RC_STR
827	#undef PGM_SHW_NAME_R0_STR
828
829
830	/*
831	* Shadow - PAE mode
832	*/
833	#define PGM_SHW_TYPE PGM_TYPE_PAE
834	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
835	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
836	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
837	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
838	#include "PGMShw.h"
839
840	/* Guest - real mode */
841	#define PGM_GST_TYPE PGM_TYPE_REAL
842	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
843	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
844	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
845	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
846	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
847	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
848	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
849	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
850	#include "PGMGstDefs.h"
851	#include "PGMBth.h"
852	#undef BTH_PGMPOOLKIND_PT_FOR_PT
853	#undef BTH_PGMPOOLKIND_ROOT
854	#undef PGM_BTH_NAME
855	#undef PGM_BTH_NAME_RC_STR
856	#undef PGM_BTH_NAME_R0_STR
857	#undef PGM_GST_TYPE
858	#undef PGM_GST_NAME
859	#undef PGM_GST_NAME_RC_STR
860	#undef PGM_GST_NAME_R0_STR
861
862	/* Guest - protected mode */
863	#define PGM_GST_TYPE PGM_TYPE_PROT
864	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
865	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
866	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
867	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
868	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
869	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
870	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
871	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
872	#include "PGMGstDefs.h"
873	#include "PGMBth.h"
874	#undef BTH_PGMPOOLKIND_PT_FOR_PT
875	#undef BTH_PGMPOOLKIND_ROOT
876	#undef PGM_BTH_NAME
877	#undef PGM_BTH_NAME_RC_STR
878	#undef PGM_BTH_NAME_R0_STR
879	#undef PGM_GST_TYPE
880	#undef PGM_GST_NAME
881	#undef PGM_GST_NAME_RC_STR
882	#undef PGM_GST_NAME_R0_STR
883
884	/* Guest - 32-bit mode */
885	#define PGM_GST_TYPE PGM_TYPE_32BIT
886	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
887	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
888	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
889	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
890	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
891	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
892	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
893	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
894	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
895	#include "PGMGstDefs.h"
896	#include "PGMBth.h"
897	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
898	#undef BTH_PGMPOOLKIND_PT_FOR_PT
899	#undef BTH_PGMPOOLKIND_ROOT
900	#undef PGM_BTH_NAME
901	#undef PGM_BTH_NAME_RC_STR
902	#undef PGM_BTH_NAME_R0_STR
903	#undef PGM_GST_TYPE
904	#undef PGM_GST_NAME
905	#undef PGM_GST_NAME_RC_STR
906	#undef PGM_GST_NAME_R0_STR
907
908	/* Guest - PAE mode */
909	#define PGM_GST_TYPE PGM_TYPE_PAE
910	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
911	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
912	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
913	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
914	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
915	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
916	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
917	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
918	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
919	#include "PGMBth.h"
920	#include "PGMGstDefs.h"
921	#include "PGMGst.h"
922	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
923	#undef BTH_PGMPOOLKIND_PT_FOR_PT
924	#undef BTH_PGMPOOLKIND_ROOT
925	#undef PGM_BTH_NAME
926	#undef PGM_BTH_NAME_RC_STR
927	#undef PGM_BTH_NAME_R0_STR
928	#undef PGM_GST_TYPE
929	#undef PGM_GST_NAME
930	#undef PGM_GST_NAME_RC_STR
931	#undef PGM_GST_NAME_R0_STR
932
933	#undef PGM_SHW_TYPE
934	#undef PGM_SHW_NAME
935	#undef PGM_SHW_NAME_RC_STR
936	#undef PGM_SHW_NAME_R0_STR
937
938
939	/*
940	* Shadow - AMD64 mode
941	*/
942	#define PGM_SHW_TYPE PGM_TYPE_AMD64
943	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
944	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
945	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
946	#include "PGMShw.h"
947
948	#ifdef VBOX_WITH_64_BITS_GUESTS
949	/* Guest - AMD64 mode */
950	# define PGM_GST_TYPE PGM_TYPE_AMD64
951	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
952	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
953	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
954	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
955	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
956	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
957	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
958	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
959	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
960	# include "PGMBth.h"
961	# include "PGMGstDefs.h"
962	# include "PGMGst.h"
963	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
964	# undef BTH_PGMPOOLKIND_PT_FOR_PT
965	# undef BTH_PGMPOOLKIND_ROOT
966	# undef PGM_BTH_NAME
967	# undef PGM_BTH_NAME_RC_STR
968	# undef PGM_BTH_NAME_R0_STR
969	# undef PGM_GST_TYPE
970	# undef PGM_GST_NAME
971	# undef PGM_GST_NAME_RC_STR
972	# undef PGM_GST_NAME_R0_STR
973	#endif /* VBOX_WITH_64_BITS_GUESTS */
974
975	#undef PGM_SHW_TYPE
976	#undef PGM_SHW_NAME
977	#undef PGM_SHW_NAME_RC_STR
978	#undef PGM_SHW_NAME_R0_STR
979
980
981	/*
982	* Shadow - Nested paging mode
983	*/
984	#define PGM_SHW_TYPE PGM_TYPE_NESTED
985	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
986	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
987	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
988	#include "PGMShw.h"
989
990	/* Guest - real mode */
991	#define PGM_GST_TYPE PGM_TYPE_REAL
992	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
993	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
994	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
995	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
996	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
997	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
998	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
999	#include "PGMGstDefs.h"
1000	#include "PGMBth.h"
1001	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1002	#undef PGM_BTH_NAME
1003	#undef PGM_BTH_NAME_RC_STR
1004	#undef PGM_BTH_NAME_R0_STR
1005	#undef PGM_GST_TYPE
1006	#undef PGM_GST_NAME
1007	#undef PGM_GST_NAME_RC_STR
1008	#undef PGM_GST_NAME_R0_STR
1009
1010	/* Guest - protected mode */
1011	#define PGM_GST_TYPE PGM_TYPE_PROT
1012	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1013	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1014	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1015	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
1016	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
1017	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
1018	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1019	#include "PGMGstDefs.h"
1020	#include "PGMBth.h"
1021	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1022	#undef PGM_BTH_NAME
1023	#undef PGM_BTH_NAME_RC_STR
1024	#undef PGM_BTH_NAME_R0_STR
1025	#undef PGM_GST_TYPE
1026	#undef PGM_GST_NAME
1027	#undef PGM_GST_NAME_RC_STR
1028	#undef PGM_GST_NAME_R0_STR
1029
1030	/* Guest - 32-bit mode */
1031	#define PGM_GST_TYPE PGM_TYPE_32BIT
1032	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1033	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1034	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1035	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
1036	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
1037	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
1038	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1039	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1040	#include "PGMGstDefs.h"
1041	#include "PGMBth.h"
1042	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1043	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1044	#undef PGM_BTH_NAME
1045	#undef PGM_BTH_NAME_RC_STR
1046	#undef PGM_BTH_NAME_R0_STR
1047	#undef PGM_GST_TYPE
1048	#undef PGM_GST_NAME
1049	#undef PGM_GST_NAME_RC_STR
1050	#undef PGM_GST_NAME_R0_STR
1051
1052	/* Guest - PAE mode */
1053	#define PGM_GST_TYPE PGM_TYPE_PAE
1054	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1055	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1056	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1057	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1058	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1059	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1060	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1061	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1062	#include "PGMGstDefs.h"
1063	#include "PGMBth.h"
1064	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1065	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1066	#undef PGM_BTH_NAME
1067	#undef PGM_BTH_NAME_RC_STR
1068	#undef PGM_BTH_NAME_R0_STR
1069	#undef PGM_GST_TYPE
1070	#undef PGM_GST_NAME
1071	#undef PGM_GST_NAME_RC_STR
1072	#undef PGM_GST_NAME_R0_STR
1073
1074	#ifdef VBOX_WITH_64_BITS_GUESTS
1075	/* Guest - AMD64 mode */
1076	# define PGM_GST_TYPE PGM_TYPE_AMD64
1077	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1078	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1079	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1080	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1081	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1082	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1083	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1084	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1085	# include "PGMGstDefs.h"
1086	# include "PGMBth.h"
1087	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1088	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1089	# undef PGM_BTH_NAME
1090	# undef PGM_BTH_NAME_RC_STR
1091	# undef PGM_BTH_NAME_R0_STR
1092	# undef PGM_GST_TYPE
1093	# undef PGM_GST_NAME
1094	# undef PGM_GST_NAME_RC_STR
1095	# undef PGM_GST_NAME_R0_STR
1096	#endif /* VBOX_WITH_64_BITS_GUESTS */
1097
1098	#undef PGM_SHW_TYPE
1099	#undef PGM_SHW_NAME
1100	#undef PGM_SHW_NAME_RC_STR
1101	#undef PGM_SHW_NAME_R0_STR
1102
1103
1104	/*
1105	* Shadow - EPT
1106	*/
1107	#define PGM_SHW_TYPE PGM_TYPE_EPT
1108	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1109	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1110	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1111	#include "PGMShw.h"
1112
1113	/* Guest - real mode */
1114	#define PGM_GST_TYPE PGM_TYPE_REAL
1115	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1116	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1117	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1118	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1119	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1120	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1121	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1122	#include "PGMGstDefs.h"
1123	#include "PGMBth.h"
1124	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1125	#undef PGM_BTH_NAME
1126	#undef PGM_BTH_NAME_RC_STR
1127	#undef PGM_BTH_NAME_R0_STR
1128	#undef PGM_GST_TYPE
1129	#undef PGM_GST_NAME
1130	#undef PGM_GST_NAME_RC_STR
1131	#undef PGM_GST_NAME_R0_STR
1132
1133	/* Guest - protected mode */
1134	#define PGM_GST_TYPE PGM_TYPE_PROT
1135	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1136	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1137	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1138	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1139	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1140	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1141	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1142	#include "PGMGstDefs.h"
1143	#include "PGMBth.h"
1144	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1145	#undef PGM_BTH_NAME
1146	#undef PGM_BTH_NAME_RC_STR
1147	#undef PGM_BTH_NAME_R0_STR
1148	#undef PGM_GST_TYPE
1149	#undef PGM_GST_NAME
1150	#undef PGM_GST_NAME_RC_STR
1151	#undef PGM_GST_NAME_R0_STR
1152
1153	/* Guest - 32-bit mode */
1154	#define PGM_GST_TYPE PGM_TYPE_32BIT
1155	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1156	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1157	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1158	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1159	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1160	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1161	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1162	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1163	#include "PGMGstDefs.h"
1164	#include "PGMBth.h"
1165	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1166	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1167	#undef PGM_BTH_NAME
1168	#undef PGM_BTH_NAME_RC_STR
1169	#undef PGM_BTH_NAME_R0_STR
1170	#undef PGM_GST_TYPE
1171	#undef PGM_GST_NAME
1172	#undef PGM_GST_NAME_RC_STR
1173	#undef PGM_GST_NAME_R0_STR
1174
1175	/* Guest - PAE mode */
1176	#define PGM_GST_TYPE PGM_TYPE_PAE
1177	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1178	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1179	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1180	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1181	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1182	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1183	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1184	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1185	#include "PGMGstDefs.h"
1186	#include "PGMBth.h"
1187	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1188	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1189	#undef PGM_BTH_NAME
1190	#undef PGM_BTH_NAME_RC_STR
1191	#undef PGM_BTH_NAME_R0_STR
1192	#undef PGM_GST_TYPE
1193	#undef PGM_GST_NAME
1194	#undef PGM_GST_NAME_RC_STR
1195	#undef PGM_GST_NAME_R0_STR
1196
1197	#ifdef VBOX_WITH_64_BITS_GUESTS
1198	/* Guest - AMD64 mode */
1199	# define PGM_GST_TYPE PGM_TYPE_AMD64
1200	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1201	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1202	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1203	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1204	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1205	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1206	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1207	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1208	# include "PGMGstDefs.h"
1209	# include "PGMBth.h"
1210	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1211	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1212	# undef PGM_BTH_NAME
1213	# undef PGM_BTH_NAME_RC_STR
1214	# undef PGM_BTH_NAME_R0_STR
1215	# undef PGM_GST_TYPE
1216	# undef PGM_GST_NAME
1217	# undef PGM_GST_NAME_RC_STR
1218	# undef PGM_GST_NAME_R0_STR
1219	#endif /* VBOX_WITH_64_BITS_GUESTS */
1220
1221	#undef PGM_SHW_TYPE
1222	#undef PGM_SHW_NAME
1223	#undef PGM_SHW_NAME_RC_STR
1224	#undef PGM_SHW_NAME_R0_STR
1225
1226
1227
1228	/**
1229	* Initiates the paging of VM.
1230	*
1231	* @returns VBox status code.
1232	* @param pVM Pointer to VM structure.
1233	*/
1234	VMMR3DECL(int) PGMR3Init(PVM pVM)
1235	{
1236	LogFlow(("PGMR3Init:\n"));
1237	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1238	int rc;
1239
1240	/*
1241	* Assert alignment and sizes.
1242	*/
1243	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1244	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1245	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1246
1247	/*
1248	* Init the structure.
1249	*/
1250	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1251	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1252
1253	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1254	{
1255	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1256	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1257	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1258	}
1259
1260	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1261	{
1262	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1263	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1264	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1265	}
1266
1267	/* Init the per-CPU part. */
1268	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1269	{
1270	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1271	PPGMCPU pPGM = &pVCpu->pgm.s;
1272
1273	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1274	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1275	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1276
1277	pPGM->enmShadowMode = PGMMODE_INVALID;
1278	pPGM->enmGuestMode = PGMMODE_INVALID;
1279
1280	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1281
1282	pPGM->pGst32BitPdR3 = NULL;
1283	pPGM->pGstPaePdptR3 = NULL;
1284	pPGM->pGstAmd64Pml4R3 = NULL;
1285	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1286	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1287	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1288	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1289	#endif
1290	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1291	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1292	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1293	{
1294	pPGM->apGstPaePDsR3[i] = NULL;
1295	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1296	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1297	#endif
1298	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1299	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1300	pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1301	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1302	}
1303
1304	pPGM->fA20Enabled = true;
1305	pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
1306	}
1307
1308	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1309	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1310	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1311
1312	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1313	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1314	true
1315	#else
1316	false
1317	#endif
1318	);
1319	AssertLogRelRCReturn(rc, rc);
1320
1321	#if HC_ARCH_BITS == 32
1322	# ifdef RT_OS_DARWIN
1323	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1324	# else
1325	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1326	# endif
1327	#else
1328	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1329	#endif
1330	AssertLogRelRCReturn(rc, rc);
1331	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1332	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1333
1334	/*
1335	* Get the configured RAM size - to estimate saved state size.
1336	*/
1337	uint64_t cbRam;
1338	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1339	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1340	cbRam = 0;
1341	else if (RT_SUCCESS(rc))
1342	{
1343	if (cbRam < PAGE_SIZE)
1344	cbRam = 0;
1345	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1346	}
1347	else
1348	{
1349	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1350	return rc;
1351	}
1352
1353	/*
1354	* Check for PCI pass-through.
1355	*/
1356	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1357	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1358	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1359
1360	#ifdef VBOX_WITH_STATISTICS
1361	/*
1362	* Allocate memory for the statistics before someone tries to use them.
1363	*/
1364	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1365	void *pv;
1366	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1367	AssertRCReturn(rc, rc);
1368
1369	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1370	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1371	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1372	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1373
1374	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1375	{
1376	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1377	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1378	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1379
1380	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1381	}
1382	#endif /* VBOX_WITH_STATISTICS */
1383
1384	/*
1385	* Register callbacks, string formatters and the saved state data unit.
1386	*/
1387	#ifdef VBOX_STRICT
1388	VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1389	#endif
1390	PGMRegisterStringFormatTypes();
1391
1392	rc = pgmR3InitSavedState(pVM, cbRam);
1393	if (RT_FAILURE(rc))
1394	return rc;
1395
1396	/*
1397	* Initialize the PGM critical section and flush the phys TLBs
1398	*/
1399	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1400	AssertRCReturn(rc, rc);
1401
1402	PGMR3PhysChunkInvalidateTLB(pVM);
1403	pgmPhysInvalidatePageMapTLB(pVM);
1404
1405	/*
1406	* For the time being we sport a full set of handy pages in addition to the base
1407	* memory to simplify things.
1408	*/
1409	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1410	AssertRCReturn(rc, rc);
1411
1412	/*
1413	* Trees
1414	*/
1415	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1416	if (RT_SUCCESS(rc))
1417	{
1418	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1419	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1420	}
1421
1422	/*
1423	* Allocate the zero page.
1424	*/
1425	if (RT_SUCCESS(rc))
1426	{
1427	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1428	if (RT_SUCCESS(rc))
1429	{
1430	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1431	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1432	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1433	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1434	}
1435	}
1436
1437	/*
1438	* Allocate the invalid MMIO page.
1439	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1440	*/
1441	if (RT_SUCCESS(rc))
1442	{
1443	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1444	if (RT_SUCCESS(rc))
1445	{
1446	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1447	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1448	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1449	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1450	}
1451	}
1452
1453	/*
1454	* Register the physical access handler protecting ROMs.
1455	*/
1456	if (RT_SUCCESS(rc))
1457	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE,
1458	pgmR3PhysRomWriteHandler,
1459	NULL, "pgmPhysRomWriteHandler",
1460	NULL, "pgmPhysRomWriteHandler",
1461	"ROM write protection",
1462	&pVM->pgm.s.hRomPhysHandlerType);
1463
1464	/*
1465	* Init the paging.
1466	*/
1467	if (RT_SUCCESS(rc))
1468	rc = pgmR3InitPaging(pVM);
1469
1470	/*
1471	* Init the page pool.
1472	*/
1473	if (RT_SUCCESS(rc))
1474	rc = pgmR3PoolInit(pVM);
1475
1476	if (RT_SUCCESS(rc))
1477	{
1478	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1479	{
1480	PVMCPU pVCpu = &pVM->aCpus[i];
1481	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1482	if (RT_FAILURE(rc))
1483	break;
1484	}
1485	}
1486
1487	if (RT_SUCCESS(rc))
1488	{
1489	/*
1490	* Info & statistics
1491	*/
1492	DBGFR3InfoRegisterInternal(pVM, "mode",
1493	"Shows the current paging mode. "
1494	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1495	pgmR3InfoMode);
1496	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1497	"Dumps all the entries in the top level paging table. No arguments.",
1498	pgmR3InfoCr3);
1499	DBGFR3InfoRegisterInternal(pVM, "phys",
1500	"Dumps all the physical address ranges. No arguments.",
1501	pgmR3PhysInfo);
1502	DBGFR3InfoRegisterInternal(pVM, "handlers",
1503	"Dumps physical, virtual and hyper virtual handlers. "
1504	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1505	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1506	pgmR3InfoHandlers);
1507	DBGFR3InfoRegisterInternal(pVM, "mappings",
1508	"Dumps guest mappings.",
1509	pgmR3MapInfo);
1510
1511	pgmR3InitStats(pVM);
1512
1513	#ifdef VBOX_WITH_DEBUGGER
1514	/*
1515	* Debugger commands.
1516	*/
1517	static bool s_fRegisteredCmds = false;
1518	if (!s_fRegisteredCmds)
1519	{
1520	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1521	if (RT_SUCCESS(rc2))
1522	s_fRegisteredCmds = true;
1523	}
1524	#endif
1525	return VINF_SUCCESS;
1526	}
1527
1528	/* Almost no cleanup necessary, MM frees all memory. */
1529	PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1530
1531	return rc;
1532	}
1533
1534
1535	/**
1536	* Init paging.
1537	*
1538	* Since we need to check what mode the host is operating in before we can choose
1539	* the right paging functions for the host we have to delay this until R0 has
1540	* been initialized.
1541	*
1542	* @returns VBox status code.
1543	* @param pVM Pointer to the VM.
1544	*/
1545	static int pgmR3InitPaging(PVM pVM)
1546	{
1547	/*
1548	* Force a recalculation of modes and switcher so everyone gets notified.
1549	*/
1550	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1551	{
1552	PVMCPU pVCpu = &pVM->aCpus[i];
1553
1554	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1555	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1556	}
1557
1558	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1559
1560	/*
1561	* Allocate static mapping space for whatever the cr3 register
1562	* points to and in the case of PAE mode to the 4 PDs.
1563	*/
1564	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1565	if (RT_FAILURE(rc))
1566	{
1567	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1568	return rc;
1569	}
1570	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1571
1572	/*
1573	* Allocate pages for the three possible intermediate contexts
1574	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1575	* for the sake of simplicity. The AMD64 uses the PAE for the
1576	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1577	*
1578	* We assume that two page tables will be enought for the core code
1579	* mappings (HC virtual and identity).
1580	*/
1581	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1582	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1583	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1584	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1585	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1586	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1587	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1588	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1589	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1590	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1591	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1592	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1593
1594	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1595	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1596	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1597	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1598	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1599	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1600
1601	/*
1602	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1603	*/
1604	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1605	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1606	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1607
1608	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1609	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1610
1611	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1612	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1613	{
1614	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1615	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1616	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1617	}
1618
1619	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1620	{
1621	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1622	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1623	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1624	}
1625
1626	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1627	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1628	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1629	\| HCPhysInterPaePDPT64;
1630
1631	/*
1632	* Initialize paging workers and mode from current host mode
1633	* and the guest running in real mode.
1634	*/
1635	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1636	switch (pVM->pgm.s.enmHostMode)
1637	{
1638	case SUPPAGINGMODE_32_BIT:
1639	case SUPPAGINGMODE_32_BIT_GLOBAL:
1640	case SUPPAGINGMODE_PAE:
1641	case SUPPAGINGMODE_PAE_GLOBAL:
1642	case SUPPAGINGMODE_PAE_NX:
1643	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1644	break;
1645
1646	case SUPPAGINGMODE_AMD64:
1647	case SUPPAGINGMODE_AMD64_GLOBAL:
1648	case SUPPAGINGMODE_AMD64_NX:
1649	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1650	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1651	if (ARCH_BITS != 64)
1652	{
1653	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1654	LogRel(("PGM: Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1655	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1656	}
1657	#endif
1658	break;
1659	default:
1660	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1661	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1662	}
1663	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1664	if (RT_SUCCESS(rc))
1665	{
1666	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1667	#if HC_ARCH_BITS == 64
1668	LogRel(("PGM: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1669	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1670	LogRel(("PGM: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1671	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1672	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1673	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1674	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1675	#endif
1676
1677	/*
1678	* Log the host paging mode. It may come in handy.
1679	*/
1680	const char *pszHostMode;
1681	switch (pVM->pgm.s.enmHostMode)
1682	{
1683	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1684	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1685	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1686	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1687	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1688	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1689	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1690	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1691	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1692	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1693	default: pszHostMode = "???"; break;
1694	}
1695	LogRel(("PGM: Host paging mode: %s\n", pszHostMode));
1696
1697	return VINF_SUCCESS;
1698	}
1699
1700	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1701	return rc;
1702	}
1703
1704
1705	/**
1706	* Init statistics
1707	* @returns VBox status code.
1708	*/
1709	static int pgmR3InitStats(PVM pVM)
1710	{
1711	PPGM pPGM = &pVM->pgm.s;
1712	int rc;
1713
1714	/*
1715	* Release statistics.
1716	*/
1717	/* Common - misc variables */
1718	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1719	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1720	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1721	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1722	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1723	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1724	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1725	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1726	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1727	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1728	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1729	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1730	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1731	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1732	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1733	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1734	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1735	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1736	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1737
1738	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1739	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1740	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1741
1742	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1743
1744	/* Live save */
1745	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1746	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1747	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1748	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1749	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1750	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1751	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1752	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1753	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1754	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1755	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1756	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1757	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1758	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1759	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1760	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1761	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1762	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1763
1764	#ifdef VBOX_WITH_STATISTICS
1765
1766	# define PGM_REG_COUNTER(a, b, c) \
1767	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1768	AssertRC(rc);
1769
1770	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1771	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1772	AssertRC(rc);
1773
1774	# define PGM_REG_PROFILE(a, b, c) \
1775	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1776	AssertRC(rc);
1777
1778	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1779
1780	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1781	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1782	PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1783	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1784	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1785
1786	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1787	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1788	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1789	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1790	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1791	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1792	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1793	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1794	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1795	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1796
1797	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1798	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1799	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1800	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1801	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1802	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1803
1804	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1805	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1806	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1807	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1808	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1809	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1810	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1811	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1812
1813	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1814	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1815	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1816	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1817
1818	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1819	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1820	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1821	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1822
1823	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1824	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1825	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1826	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1827	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1828	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1829	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1830	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1831
1832	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1833	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1834	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1835	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1836	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1837	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1838
1839	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1840	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1841	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1842	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1843	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1844	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1845	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1846	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1847
1848	/* GC only: */
1849	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1850	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1851
1852	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1853	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1854	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1855	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1856	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1857	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1858	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1859	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1860
1861	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1862	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1863	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1864	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1865	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1866	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1867	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1868
1869	# undef PGM_REG_COUNTER
1870	# undef PGM_REG_PROFILE
1871	#endif
1872
1873	/*
1874	* Note! The layout below matches the member layout exactly!
1875	*/
1876
1877	/*
1878	* Common - stats
1879	*/
1880	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1881	{
1882	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1883
1884	#define PGM_REG_COUNTER(a, b, c) \
1885	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1886	AssertRC(rc);
1887	#define PGM_REG_PROFILE(a, b, c) \
1888	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1889	AssertRC(rc);
1890
1891	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1892	PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1893
1894	#ifdef VBOX_WITH_STATISTICS
1895	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1896
1897	# if 0 /* rarely useful; leave for debugging. */
1898	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1899	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1900	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1901	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1902	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1903	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1904	# endif
1905	/* R0 only: */
1906	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1907	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1908
1909	/* RZ only: */
1910	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1911	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1912	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1913	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1914	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1915	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1916	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1917	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1918	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1919	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1920	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1921	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1922	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1923	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1924	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1925	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1926	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1927	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1928	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsHack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USHack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled.");
1929	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsUnhack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USUnhack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled.");
1930	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1931	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1932	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1933	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1934	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1935	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1936	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1937	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1938	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1939	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1940	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1941	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1942	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1943	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1944	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1945	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1946	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1947	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1948	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1949	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1950	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1951	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1952	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1953	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1954	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1955	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1956	#if 0 /* rarely useful; leave for debugging. */
1957	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1958	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1959	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1960	#endif
1961	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1962	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1963	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1964	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1965	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1966
1967	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1968	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1969	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1970	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1971	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1972	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1973	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1974	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1975	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1976	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1977	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1978	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1979	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1980	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1981	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1982	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1983	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1984	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1985	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1986	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1987	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1988	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1989	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1990	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1991	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1992	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1993	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1994	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1995	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1996	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1997	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1998	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1999	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
2000	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
2001	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
2002	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
2003
2004	/* HC only: */
2005
2006	/* RZ & R3: */
2007	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2008	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2009	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
2010	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2011	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2012	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2013	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2014	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2015	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2016	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2017	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
2018	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2019	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
2020	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
2021	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2022	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2023	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2024	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2025	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2026	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2027	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2028	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2029	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
2030	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2031	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2032	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2033	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
2034	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2035	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2036	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2037	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2038	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2039	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2040	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2041	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2042	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2043	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2044	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2045	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2046	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2047	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
2048	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2049	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2050	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2051	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2052	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2053	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2054
2055	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2056	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2057	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
2058	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2059	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2060	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2061	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2062	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2063	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2064	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2065	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
2066	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2067	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
2068	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
2069	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2070	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2071	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2072	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2073	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2074	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2075	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2076	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2077	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2078	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2079	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2080	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2081	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2082	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2083	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2084	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2085	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2086	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2087	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2088	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2089	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2090	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2091	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2092	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2093	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2094	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2095	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2096	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2097	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2098	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2099	#endif /* VBOX_WITH_STATISTICS */
2100
2101	#undef PGM_REG_PROFILE
2102	#undef PGM_REG_COUNTER
2103
2104	}
2105
2106	return VINF_SUCCESS;
2107	}
2108
2109
2110	/**
2111	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2112	*
2113	* The dynamic mapping area will also be allocated and initialized at this
2114	* time. We could allocate it during PGMR3Init of course, but the mapping
2115	* wouldn't be allocated at that time preventing us from setting up the
2116	* page table entries with the dummy page.
2117	*
2118	* @returns VBox status code.
2119	* @param pVM Pointer to the VM.
2120	*/
2121	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2122	{
2123	RTGCPTR GCPtr;
2124	int rc;
2125
2126	/*
2127	* Reserve space for the dynamic mappings.
2128	*/
2129	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2130	if (RT_SUCCESS(rc))
2131	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2132
2133	if ( RT_SUCCESS(rc)
2134	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2135	{
2136	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2137	if (RT_SUCCESS(rc))
2138	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2139	}
2140	if (RT_SUCCESS(rc))
2141	{
2142	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2143	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2144	}
2145	return rc;
2146	}
2147
2148
2149	/**
2150	* Ring-3 init finalizing.
2151	*
2152	* @returns VBox status code.
2153	* @param pVM Pointer to the VM.
2154	*/
2155	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2156	{
2157	int rc;
2158
2159	/*
2160	* Reserve space for the dynamic mappings.
2161	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2162	*/
2163	/* get the pointer to the page table entries. */
2164	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2165	AssertRelease(pMapping);
2166	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2167	const unsigned iPT = off >> X86_PD_SHIFT;
2168	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2169	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2170	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2171
2172	/* init cache area */
2173	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2174	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2175	{
2176	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2177	AssertRCReturn(rc, rc);
2178	}
2179
2180	/*
2181	* Determine the max physical address width (MAXPHYADDR) and apply it to
2182	* all the mask members and stuff.
2183	*/
2184	uint32_t cMaxPhysAddrWidth;
2185	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2186	if ( uMaxExtLeaf >= 0x80000008
2187	&& uMaxExtLeaf <= 0x80000fff)
2188	{
2189	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2190	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2191	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2192	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2193	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2194	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2195	}
2196	else
2197	{
2198	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2199	cMaxPhysAddrWidth = 48;
2200	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2201	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2202	}
2203
2204	/** @todo query from CPUM. */
2205	pVM->pgm.s.GCPhysInvAddrMask = 0;
2206	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2207	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2208
2209	/*
2210	* Initialize the invalid paging entry masks, assuming NX is disabled.
2211	*/
2212	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2213	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2214	{
2215	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2216
2217	/** @todo The manuals are not entirely clear whether the physical
2218	* address width is relevant. See table 5-9 in the intel
2219	* manual vs the PDE4M descriptions. Write testcase (NP). */
2220	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2221	\| X86_PDE4M_MBZ_MASK;
2222
2223	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2224	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2225	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2226	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2227
2228	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2229	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2230	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2231	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2232	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2233	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2234
2235	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
2236	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
2237	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
2238	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2239	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
2240	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
2241	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
2242	}
2243
2244	/*
2245	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2246	* Intel only goes up to 36 bits, so we stick to 36 as well.
2247	* Update: More recent intel manuals specifies 40 bits just like AMD.
2248	*/
2249	uint32_t u32Dummy, u32Features;
2250	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2251	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2252	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2253	else
2254	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2255
2256	/*
2257	* Allocate memory if we're supposed to do that.
2258	*/
2259	if (pVM->pgm.s.fRamPreAlloc)
2260	rc = pgmR3PhysRamPreAllocate(pVM);
2261
2262	LogRel(("PGM: PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2263	return rc;
2264	}
2265
2266
2267	/**
2268	* Init phase completed callback.
2269	*
2270	* @returns VBox status code.
2271	* @param pVM Pointer to the VM.
2272	* @param enmWhat What has been completed.
2273	* @thread EMT(0)
2274	*/
2275	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2276	{
2277	switch (enmWhat)
2278	{
2279	case VMINITCOMPLETED_HM:
2280	#ifdef VBOX_WITH_PCI_PASSTHROUGH
2281	if (pVM->pgm.s.fPciPassthrough)
2282	{
2283	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2284	AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
2285	AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2286
2287	/*
2288	* Report assignments to the IOMMU (hope that's good enough for now).
2289	*/
2290	if (pVM->pgm.s.fPciPassthrough)
2291	{
2292	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2293	AssertRCReturn(rc, rc);
2294	}
2295	}
2296	#else
2297	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2298	#endif
2299	break;
2300
2301	default:
2302	/* shut up gcc */
2303	break;
2304	}
2305
2306	return VINF_SUCCESS;
2307	}
2308
2309
2310	/**
2311	* Applies relocations to data and code managed by this component.
2312	*
2313	* This function will be called at init and whenever the VMM need to relocate it
2314	* self inside the GC.
2315	*
2316	* @param pVM The VM.
2317	* @param offDelta Relocation delta relative to old location.
2318	*/
2319	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2320	{
2321	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2322
2323	/*
2324	* Paging stuff.
2325	*/
2326	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2327
2328	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2329
2330	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2331	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2332	{
2333	PVMCPU pVCpu = &pVM->aCpus[i];
2334
2335	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2336
2337	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2338	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2339	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2340	}
2341
2342	/*
2343	* Trees.
2344	*/
2345	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2346
2347	/*
2348	* Ram ranges.
2349	*/
2350	if (pVM->pgm.s.pRamRangesXR3)
2351	{
2352	/* Update the pSelfRC pointers and relink them. */
2353	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2354	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2355	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2356	pgmR3PhysRelinkRamRanges(pVM);
2357
2358	/* Flush the RC TLB. */
2359	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2360	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2361	}
2362
2363	/*
2364	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2365	* be mapped and thus not included in the above exercise.
2366	*/
2367	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2368	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2369	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2370
2371	/*
2372	* Update the two page directories with all page table mappings.
2373	* (One or more of them have changed, that's why we're here.)
2374	*/
2375	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2376	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2377	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2378
2379	/* Relocate GC addresses of Page Tables. */
2380	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2381	{
2382	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2383	{
2384	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2385	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2386	}
2387	}
2388
2389	/*
2390	* Dynamic page mapping area.
2391	*/
2392	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2393	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2394	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2395
2396	if (pVM->pgm.s.pRCDynMap)
2397	{
2398	pVM->pgm.s.pRCDynMap += offDelta;
2399	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2400
2401	pDynMap->paPages += offDelta;
2402	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2403
2404	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2405	{
2406	paPages[iPage].pvPage += offDelta;
2407	paPages[iPage].uPte.pLegacy += offDelta;
2408	paPages[iPage].uPte.pPae += offDelta;
2409	}
2410	}
2411
2412	/*
2413	* The Zero page.
2414	*/
2415	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2416	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2417	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
2418	#else
2419	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2420	#endif
2421
2422	/*
2423	* Physical and virtual handlers.
2424	*/
2425	PGMRELOCHANDLERARGS Args = { offDelta, pVM };
2426	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &Args);
2427	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2428
2429	PPGMPHYSHANDLERTYPEINT pCurPhysType;
2430	RTListOff32ForEach(&pVM->pgm.s.pTreesR3->HeadPhysHandlerTypes, pCurPhysType, PGMPHYSHANDLERTYPEINT, ListNode)
2431	{
2432	if (pCurPhysType->pfnHandlerRC != NIL_RTRCPTR)
2433	pCurPhysType->pfnHandlerRC += offDelta;
2434	}
2435
2436	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &Args);
2437	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &Args);
2438
2439	PPGMVIRTHANDLERTYPEINT pCurVirtType;
2440	RTListOff32ForEach(&pVM->pgm.s.pTreesR3->HeadVirtHandlerTypes, pCurVirtType, PGMVIRTHANDLERTYPEINT, ListNode)
2441	{
2442	if (pCurVirtType->pfnHandlerRC != NIL_RTRCPTR)
2443	pCurVirtType->pfnHandlerRC += offDelta;
2444	}
2445
2446	/*
2447	* The page pool.
2448	*/
2449	pgmR3PoolRelocate(pVM);
2450
2451	#ifdef VBOX_WITH_STATISTICS
2452	/*
2453	* Statistics.
2454	*/
2455	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2456	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2457	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2458	#endif
2459	}
2460
2461
2462	/**
2463	* Callback function for relocating a physical access handler.
2464	*
2465	* @returns 0 (continue enum)
2466	* @param pNode Pointer to a PGMPHYSHANDLER node.
2467	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2468	*/
2469	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2470	{
2471	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2472	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2473	if (pHandler->pvUserRC >= 0x10000)
2474	pHandler->pvUserRC += pArgs->offDelta;
2475	return 0;
2476	}
2477
2478
2479	/**
2480	* Callback function for relocating a virtual access handler.
2481	*
2482	* @returns 0 (continue enum)
2483	* @param pNode Pointer to a PGMVIRTHANDLER node.
2484	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2485	*/
2486	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2487	{
2488	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2489	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2490	Assert(PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->enmKind != PGMVIRTHANDLERKIND_HYPERVISOR);
2491
2492	if ( pHandler->pvUserRC != NIL_RTRCPTR
2493	&& PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->fRelocUserRC)
2494	pHandler->pvUserRC += pArgs->offDelta;
2495	return 0;
2496	}
2497
2498
2499	/**
2500	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2501	*
2502	* @returns 0 (continue enum)
2503	* @param pNode Pointer to a PGMVIRTHANDLER node.
2504	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2505	*/
2506	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2507	{
2508	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2509	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2510	Assert(PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->enmKind == PGMVIRTHANDLERKIND_HYPERVISOR);
2511
2512	if ( pHandler->pvUserRC != NIL_RTRCPTR
2513	&& PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->fRelocUserRC)
2514	pHandler->pvUserRC += pArgs->offDelta;
2515	return 0;
2516	}
2517
2518
2519	/**
2520	* Resets a virtual CPU when unplugged.
2521	*
2522	* @param pVM Pointer to the VM.
2523	* @param pVCpu Pointer to the VMCPU.
2524	*/
2525	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2526	{
2527	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2528	AssertRC(rc);
2529
2530	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2531	AssertRC(rc);
2532
2533	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2534
2535	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2536
2537	/*
2538	* Re-init other members.
2539	*/
2540	pVCpu->pgm.s.fA20Enabled = true;
2541	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2542
2543	/*
2544	* Clear the FFs PGM owns.
2545	*/
2546	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2547	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2548	}
2549
2550
2551	/**
2552	* The VM is being reset.
2553	*
2554	* For the PGM component this means that any PD write monitors
2555	* needs to be removed.
2556	*
2557	* @param pVM Pointer to the VM.
2558	*/
2559	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
2560	{
2561	LogFlow(("PGMR3Reset:\n"));
2562	VM_ASSERT_EMT(pVM);
2563
2564	pgmLock(pVM);
2565
2566	/*
2567	* Unfix any fixed mappings and disable CR3 monitoring.
2568	*/
2569	pVM->pgm.s.fMappingsFixed = false;
2570	pVM->pgm.s.fMappingsFixedRestored = false;
2571	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2572	pVM->pgm.s.cbMappingFixed = 0;
2573
2574	/*
2575	* Exit the guest paging mode before the pgm pool gets reset.
2576	* Important to clean up the amd64 case.
2577	*/
2578	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2579	{
2580	PVMCPU pVCpu = &pVM->aCpus[i];
2581	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2582	AssertReleaseRC(rc);
2583	}
2584
2585	#ifdef DEBUG
2586	DBGFR3_INFO_LOG(pVM, "mappings", NULL);
2587	DBGFR3_INFO_LOG(pVM, "handlers", "all nostat");
2588	#endif
2589
2590	/*
2591	* Switch mode back to real mode. (before resetting the pgm pool!)
2592	*/
2593	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2594	{
2595	PVMCPU pVCpu = &pVM->aCpus[i];
2596
2597	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2598	AssertReleaseRC(rc);
2599
2600	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2601	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2602	}
2603
2604	/*
2605	* Reset the shadow page pool.
2606	*/
2607	pgmR3PoolReset(pVM);
2608
2609	/*
2610	* Re-init various other members and clear the FFs that PGM owns.
2611	*/
2612	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2613	{
2614	PVMCPU pVCpu = &pVM->aCpus[i];
2615
2616	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2617	PGMNotifyNxeChanged(pVCpu, false);
2618
2619	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2620	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2621
2622	if (!pVCpu->pgm.s.fA20Enabled)
2623	{
2624	pVCpu->pgm.s.fA20Enabled = true;
2625	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2626	#ifdef PGM_WITH_A20
2627	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2628	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2629	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
2630	HMFlushTLB(pVCpu);
2631	#endif
2632	}
2633	}
2634
2635	pgmUnlock(pVM);
2636	}
2637
2638
2639	/**
2640	* Memory setup after VM construction or reset.
2641	*
2642	* @param pVM Pointer to the VM.
2643	* @param fAtReset Indicates the context, after reset if @c true or after
2644	* construction if @c false.
2645	*/
2646	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
2647	{
2648	if (fAtReset)
2649	{
2650	pgmLock(pVM);
2651
2652	int rc = pgmR3PhysRamZeroAll(pVM);
2653	AssertReleaseRC(rc);
2654
2655	rc = pgmR3PhysRomReset(pVM);
2656	AssertReleaseRC(rc);
2657
2658	pgmUnlock(pVM);
2659	}
2660	}
2661
2662
2663	#ifdef VBOX_STRICT
2664	/**
2665	* VM state change callback for clearing fNoMorePhysWrites after
2666	* a snapshot has been created.
2667	*/
2668	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2669	{
2670	if ( enmState == VMSTATE_RUNNING
2671	\|\| enmState == VMSTATE_RESUMING)
2672	pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2673	NOREF(enmOldState); NOREF(pvUser);
2674	}
2675	#endif
2676
2677	/**
2678	* Private API to reset fNoMorePhysWrites.
2679	*/
2680	VMMR3DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2681	{
2682	pVM->pgm.s.fNoMorePhysWrites = false;
2683	}
2684
2685	/**
2686	* Terminates the PGM.
2687	*
2688	* @returns VBox status code.
2689	* @param pVM Pointer to VM structure.
2690	*/
2691	VMMR3DECL(int) PGMR3Term(PVM pVM)
2692	{
2693	/* Must free shared pages here. */
2694	pgmLock(pVM);
2695	pgmR3PhysRamTerm(pVM);
2696	pgmR3PhysRomTerm(pVM);
2697	pgmUnlock(pVM);
2698
2699	PGMDeregisterStringFormatTypes();
2700	return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2701	}
2702
2703
2704	/**
2705	* Show paging mode.
2706	*
2707	* @param pVM Pointer to the VM.
2708	* @param pHlp The info helpers.
2709	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2710	*/
2711	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2712	{
2713	/* digest argument. */
2714	bool fGuest, fShadow, fHost;
2715	if (pszArgs)
2716	pszArgs = RTStrStripL(pszArgs);
2717	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2718	fShadow = fHost = fGuest = true;
2719	else
2720	{
2721	fShadow = fHost = fGuest = false;
2722	if (strstr(pszArgs, "guest"))
2723	fGuest = true;
2724	if (strstr(pszArgs, "shadow"))
2725	fShadow = true;
2726	if (strstr(pszArgs, "host"))
2727	fHost = true;
2728	}
2729
2730	/** @todo SMP support! */
2731	/* print info. */
2732	if (fGuest)
2733	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2734	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2735	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled", pVM->aCpus[0].pgm.s.cA20Changes.c);
2736	if (fShadow)
2737	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2738	if (fHost)
2739	{
2740	const char *psz;
2741	switch (pVM->pgm.s.enmHostMode)
2742	{
2743	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2744	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2745	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2746	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2747	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2748	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2749	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2750	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2751	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2752	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2753	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2754	default: psz = "unknown"; break;
2755	}
2756	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2757	}
2758	}
2759
2760
2761	/**
2762	* Dump registered MMIO ranges to the log.
2763	*
2764	* @param pVM Pointer to the VM.
2765	* @param pHlp The info helpers.
2766	* @param pszArgs Arguments, ignored.
2767	*/
2768	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2769	{
2770	NOREF(pszArgs);
2771	pHlp->pfnPrintf(pHlp,
2772	"RAM ranges (pVM=%p)\n"
2773	"%.s %.s\n",
2774	pVM,
2775	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2776	sizeof(RTHCPTR) * 2, "pvHC ");
2777
2778	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2779	pHlp->pfnPrintf(pHlp,
2780	"%RGp-%RGp %RHv %s\n",
2781	pCur->GCPhys,
2782	pCur->GCPhysLast,
2783	pCur->pvR3,
2784	pCur->pszDesc);
2785	}
2786
2787
2788	/**
2789	* Dump the page directory to the log.
2790	*
2791	* @param pVM Pointer to the VM.
2792	* @param pHlp The info helpers.
2793	* @param pszArgs Arguments, ignored.
2794	*/
2795	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2796	{
2797	/** @todo SMP support!! */
2798	PVMCPU pVCpu = &pVM->aCpus[0];
2799
2800	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2801	/* Big pages supported? */
2802	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2803
2804	/* Global pages supported? */
2805	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2806
2807	NOREF(pszArgs);
2808
2809	/*
2810	* Get page directory addresses.
2811	*/
2812	pgmLock(pVM);
2813	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2814	Assert(pPDSrc);
2815
2816	/*
2817	* Iterate the page directory.
2818	*/
2819	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2820	{
2821	X86PDE PdeSrc = pPDSrc->a[iPD];
2822	if (PdeSrc.n.u1Present)
2823	{
2824	if (PdeSrc.b.u1Size && fPSE)
2825	pHlp->pfnPrintf(pHlp,
2826	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2827	iPD,
2828	pgmGstGet4MBPhysPage(pVM, PdeSrc),
2829	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2830	else
2831	pHlp->pfnPrintf(pHlp,
2832	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2833	iPD,
2834	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2835	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2836	}
2837	}
2838	pgmUnlock(pVM);
2839	}
2840
2841
2842	/**
2843	* Service a VMMCALLRING3_PGM_LOCK call.
2844	*
2845	* @returns VBox status code.
2846	* @param pVM Pointer to the VM.
2847	*/
2848	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2849	{
2850	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2851	AssertRC(rc);
2852	return rc;
2853	}
2854
2855
2856	/**
2857	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2858	*
2859	* @returns PGM_TYPE_*.
2860	* @param pgmMode The mode value to convert.
2861	*/
2862	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2863	{
2864	switch (pgmMode)
2865	{
2866	case PGMMODE_REAL: return PGM_TYPE_REAL;
2867	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2868	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2869	case PGMMODE_PAE:
2870	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2871	case PGMMODE_AMD64:
2872	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2873	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2874	case PGMMODE_EPT: return PGM_TYPE_EPT;
2875	default:
2876	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2877	}
2878	}
2879
2880
2881	/**
2882	* Gets the index into the paging mode data array of a SHW+GST mode.
2883	*
2884	* @returns PGM::paPagingData index.
2885	* @param uShwType The shadow paging mode type.
2886	* @param uGstType The guest paging mode type.
2887	*/
2888	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2889	{
2890	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2891	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2892	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2893	+ (uGstType - PGM_TYPE_REAL);
2894	}
2895
2896
2897	/**
2898	* Gets the index into the paging mode data array of a SHW+GST mode.
2899	*
2900	* @returns PGM::paPagingData index.
2901	* @param enmShw The shadow paging mode.
2902	* @param enmGst The guest paging mode.
2903	*/
2904	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2905	{
2906	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2907	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2908	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2909	}
2910
2911
2912	/**
2913	* Calculates the max data index.
2914	* @returns The number of entries in the paging data array.
2915	*/
2916	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2917	{
2918	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2919	}
2920
2921
2922	/**
2923	* Initializes the paging mode data kept in PGM::paModeData.
2924	*
2925	* @param pVM Pointer to the VM.
2926	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2927	* This is used early in the init process to avoid trouble with PDM
2928	* not being initialized yet.
2929	*/
2930	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2931	{
2932	PPGMMODEDATA pModeData;
2933	int rc;
2934
2935	/*
2936	* Allocate the array on the first call.
2937	*/
2938	if (!pVM->pgm.s.paModeData)
2939	{
2940	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2941	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2942	}
2943
2944	/*
2945	* Initialize the array entries.
2946	*/
2947	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2948	pModeData->uShwType = PGM_TYPE_32BIT;
2949	pModeData->uGstType = PGM_TYPE_REAL;
2950	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2951	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2952	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2953
2954	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2955	pModeData->uShwType = PGM_TYPE_32BIT;
2956	pModeData->uGstType = PGM_TYPE_PROT;
2957	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2958	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2959	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2960
2961	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2962	pModeData->uShwType = PGM_TYPE_32BIT;
2963	pModeData->uGstType = PGM_TYPE_32BIT;
2964	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2965	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2966	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2967
2968	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2969	pModeData->uShwType = PGM_TYPE_PAE;
2970	pModeData->uGstType = PGM_TYPE_REAL;
2971	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2972	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2973	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2974
2975	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2976	pModeData->uShwType = PGM_TYPE_PAE;
2977	pModeData->uGstType = PGM_TYPE_PROT;
2978	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2979	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2980	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2981
2982	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2983	pModeData->uShwType = PGM_TYPE_PAE;
2984	pModeData->uGstType = PGM_TYPE_32BIT;
2985	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2986	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2987	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2988
2989	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2990	pModeData->uShwType = PGM_TYPE_PAE;
2991	pModeData->uGstType = PGM_TYPE_PAE;
2992	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2993	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2994	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2995
2996	#ifdef VBOX_WITH_64_BITS_GUESTS
2997	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2998	pModeData->uShwType = PGM_TYPE_AMD64;
2999	pModeData->uGstType = PGM_TYPE_AMD64;
3000	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3001	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3002	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3003	#endif
3004
3005	/* The nested paging mode. */
3006	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3007	pModeData->uShwType = PGM_TYPE_NESTED;
3008	pModeData->uGstType = PGM_TYPE_REAL;
3009	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3010	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3011
3012	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3013	pModeData->uShwType = PGM_TYPE_NESTED;
3014	pModeData->uGstType = PGM_TYPE_PROT;
3015	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3016	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3017
3018	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3019	pModeData->uShwType = PGM_TYPE_NESTED;
3020	pModeData->uGstType = PGM_TYPE_32BIT;
3021	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3022	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3023
3024	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3025	pModeData->uShwType = PGM_TYPE_NESTED;
3026	pModeData->uGstType = PGM_TYPE_PAE;
3027	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3028	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3029
3030	#ifdef VBOX_WITH_64_BITS_GUESTS
3031	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3032	pModeData->uShwType = PGM_TYPE_NESTED;
3033	pModeData->uGstType = PGM_TYPE_AMD64;
3034	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3035	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3036	#endif
3037
3038	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3039	switch (pVM->pgm.s.enmHostMode)
3040	{
3041	#if HC_ARCH_BITS == 32
3042	case SUPPAGINGMODE_32_BIT:
3043	case SUPPAGINGMODE_32_BIT_GLOBAL:
3044	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3045	{
3046	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3047	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3048	}
3049	# ifdef VBOX_WITH_64_BITS_GUESTS
3050	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3051	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3052	# endif
3053	break;
3054
3055	case SUPPAGINGMODE_PAE:
3056	case SUPPAGINGMODE_PAE_NX:
3057	case SUPPAGINGMODE_PAE_GLOBAL:
3058	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3059	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3060	{
3061	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3062	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3063	}
3064	# ifdef VBOX_WITH_64_BITS_GUESTS
3065	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3066	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3067	# endif
3068	break;
3069	#endif /* HC_ARCH_BITS == 32 */
3070
3071	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3072	case SUPPAGINGMODE_AMD64:
3073	case SUPPAGINGMODE_AMD64_GLOBAL:
3074	case SUPPAGINGMODE_AMD64_NX:
3075	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3076	# ifdef VBOX_WITH_64_BITS_GUESTS
3077	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3078	# else
3079	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3080	# endif
3081	{
3082	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3083	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3084	}
3085	break;
3086	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3087
3088	default:
3089	AssertFailed();
3090	break;
3091	}
3092
3093	/* Extended paging (EPT) / Intel VT-x */
3094	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3095	pModeData->uShwType = PGM_TYPE_EPT;
3096	pModeData->uGstType = PGM_TYPE_REAL;
3097	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3098	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3099	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3100
3101	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3102	pModeData->uShwType = PGM_TYPE_EPT;
3103	pModeData->uGstType = PGM_TYPE_PROT;
3104	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3105	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3106	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3107
3108	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3109	pModeData->uShwType = PGM_TYPE_EPT;
3110	pModeData->uGstType = PGM_TYPE_32BIT;
3111	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3112	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3113	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3114
3115	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3116	pModeData->uShwType = PGM_TYPE_EPT;
3117	pModeData->uGstType = PGM_TYPE_PAE;
3118	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3119	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3120	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3121
3122	#ifdef VBOX_WITH_64_BITS_GUESTS
3123	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3124	pModeData->uShwType = PGM_TYPE_EPT;
3125	pModeData->uGstType = PGM_TYPE_AMD64;
3126	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3127	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3128	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3129	#endif
3130	return VINF_SUCCESS;
3131	}
3132
3133
3134	/**
3135	* Switch to different (or relocated in the relocate case) mode data.
3136	*
3137	* @param pVM Pointer to the VM.
3138	* @param pVCpu Pointer to the VMCPU.
3139	* @param enmShw The shadow paging mode.
3140	* @param enmGst The guest paging mode.
3141	*/
3142	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3143	{
3144	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3145
3146	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3147	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3148
3149	/* shadow */
3150	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3151	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3152	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3153	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3154	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3155
3156	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3157	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3158
3159	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3160	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3161
3162
3163	/* guest */
3164	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3165	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3166	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3167	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3168	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3169	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3170	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3171	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3172	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3173	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3174	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3175	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3176
3177	/* both */
3178	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3179	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3180	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3181	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3182	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3183	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3184	#ifdef VBOX_STRICT
3185	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3186	#endif
3187	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3188	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3189
3190	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3191	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3192	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3193	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3194	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3195	#ifdef VBOX_STRICT
3196	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3197	#endif
3198	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3199	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3200
3201	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3202	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3203	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3204	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3205	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3206	#ifdef VBOX_STRICT
3207	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3208	#endif
3209	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3210	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3211	}
3212
3213
3214	/**
3215	* Calculates the shadow paging mode.
3216	*
3217	* @returns The shadow paging mode.
3218	* @param pVM Pointer to the VM.
3219	* @param enmGuestMode The guest mode.
3220	* @param enmHostMode The host mode.
3221	* @param enmShadowMode The current shadow mode.
3222	* @param penmSwitcher Where to store the switcher to use.
3223	* VMMSWITCHER_INVALID means no change.
3224	*/
3225	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3226	{
3227	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3228	switch (enmGuestMode)
3229	{
3230	/*
3231	* When switching to real or protected mode we don't change
3232	* anything since it's likely that we'll switch back pretty soon.
3233	*
3234	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3235	* and is supposed to determine which shadow paging and switcher to
3236	* use during init.
3237	*/
3238	case PGMMODE_REAL:
3239	case PGMMODE_PROTECTED:
3240	if ( enmShadowMode != PGMMODE_INVALID
3241	&& !HMIsEnabled(pVM) /* always switch in hm mode! */)
3242	break; /* (no change) */
3243
3244	switch (enmHostMode)
3245	{
3246	case SUPPAGINGMODE_32_BIT:
3247	case SUPPAGINGMODE_32_BIT_GLOBAL:
3248	enmShadowMode = PGMMODE_32_BIT;
3249	enmSwitcher = VMMSWITCHER_32_TO_32;
3250	break;
3251
3252	case SUPPAGINGMODE_PAE:
3253	case SUPPAGINGMODE_PAE_NX:
3254	case SUPPAGINGMODE_PAE_GLOBAL:
3255	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3256	enmShadowMode = PGMMODE_PAE;
3257	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3258	#ifdef DEBUG_bird
3259	if (RTEnvExist("VBOX_32BIT"))
3260	{
3261	enmShadowMode = PGMMODE_32_BIT;
3262	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3263	}
3264	#endif
3265	break;
3266
3267	case SUPPAGINGMODE_AMD64:
3268	case SUPPAGINGMODE_AMD64_GLOBAL:
3269	case SUPPAGINGMODE_AMD64_NX:
3270	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3271	enmShadowMode = PGMMODE_PAE;
3272	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3273	#ifdef DEBUG_bird
3274	if (RTEnvExist("VBOX_32BIT"))
3275	{
3276	enmShadowMode = PGMMODE_32_BIT;
3277	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3278	}
3279	#endif
3280	break;
3281
3282	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3283	}
3284	break;
3285
3286	case PGMMODE_32_BIT:
3287	switch (enmHostMode)
3288	{
3289	case SUPPAGINGMODE_32_BIT:
3290	case SUPPAGINGMODE_32_BIT_GLOBAL:
3291	enmShadowMode = PGMMODE_32_BIT;
3292	enmSwitcher = VMMSWITCHER_32_TO_32;
3293	break;
3294
3295	case SUPPAGINGMODE_PAE:
3296	case SUPPAGINGMODE_PAE_NX:
3297	case SUPPAGINGMODE_PAE_GLOBAL:
3298	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3299	enmShadowMode = PGMMODE_PAE;
3300	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3301	#ifdef DEBUG_bird
3302	if (RTEnvExist("VBOX_32BIT"))
3303	{
3304	enmShadowMode = PGMMODE_32_BIT;
3305	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3306	}
3307	#endif
3308	break;
3309
3310	case SUPPAGINGMODE_AMD64:
3311	case SUPPAGINGMODE_AMD64_GLOBAL:
3312	case SUPPAGINGMODE_AMD64_NX:
3313	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3314	enmShadowMode = PGMMODE_PAE;
3315	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3316	#ifdef DEBUG_bird
3317	if (RTEnvExist("VBOX_32BIT"))
3318	{
3319	enmShadowMode = PGMMODE_32_BIT;
3320	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3321	}
3322	#endif
3323	break;
3324
3325	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3326	}
3327	break;
3328
3329	case PGMMODE_PAE:
3330	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3331	switch (enmHostMode)
3332	{
3333	case SUPPAGINGMODE_32_BIT:
3334	case SUPPAGINGMODE_32_BIT_GLOBAL:
3335	enmShadowMode = PGMMODE_PAE;
3336	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3337	break;
3338
3339	case SUPPAGINGMODE_PAE:
3340	case SUPPAGINGMODE_PAE_NX:
3341	case SUPPAGINGMODE_PAE_GLOBAL:
3342	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3343	enmShadowMode = PGMMODE_PAE;
3344	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3345	break;
3346
3347	case SUPPAGINGMODE_AMD64:
3348	case SUPPAGINGMODE_AMD64_GLOBAL:
3349	case SUPPAGINGMODE_AMD64_NX:
3350	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3351	enmShadowMode = PGMMODE_PAE;
3352	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3353	break;
3354
3355	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3356	}
3357	break;
3358
3359	case PGMMODE_AMD64:
3360	case PGMMODE_AMD64_NX:
3361	switch (enmHostMode)
3362	{
3363	case SUPPAGINGMODE_32_BIT:
3364	case SUPPAGINGMODE_32_BIT_GLOBAL:
3365	enmShadowMode = PGMMODE_AMD64;
3366	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3367	break;
3368
3369	case SUPPAGINGMODE_PAE:
3370	case SUPPAGINGMODE_PAE_NX:
3371	case SUPPAGINGMODE_PAE_GLOBAL:
3372	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3373	enmShadowMode = PGMMODE_AMD64;
3374	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3375	break;
3376
3377	case SUPPAGINGMODE_AMD64:
3378	case SUPPAGINGMODE_AMD64_GLOBAL:
3379	case SUPPAGINGMODE_AMD64_NX:
3380	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3381	enmShadowMode = PGMMODE_AMD64;
3382	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3383	break;
3384
3385	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3386	}
3387	break;
3388
3389
3390	default:
3391	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3392	*penmSwitcher = VMMSWITCHER_INVALID;
3393	return PGMMODE_INVALID;
3394	}
3395	/* Override the shadow mode is nested paging is active. */
3396	pVM->pgm.s.fNestedPaging = HMIsNestedPagingActive(pVM);
3397	if (pVM->pgm.s.fNestedPaging)
3398	enmShadowMode = HMGetShwPagingMode(pVM);
3399
3400	*penmSwitcher = enmSwitcher;
3401	return enmShadowMode;
3402	}
3403
3404
3405	/**
3406	* Performs the actual mode change.
3407	* This is called by PGMChangeMode and pgmR3InitPaging().
3408	*
3409	* @returns VBox status code. May suspend or power off the VM on error, but this
3410	* will trigger using FFs and not status codes.
3411	*
3412	* @param pVM Pointer to the VM.
3413	* @param pVCpu Pointer to the VMCPU.
3414	* @param enmGuestMode The new guest mode. This is assumed to be different from
3415	* the current mode.
3416	*/
3417	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3418	{
3419	#if HC_ARCH_BITS == 32
3420	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3421	#endif
3422	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3423
3424	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3425	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3426
3427	/*
3428	* Calc the shadow mode and switcher.
3429	*/
3430	VMMSWITCHER enmSwitcher;
3431	PGMMODE enmShadowMode;
3432	enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3433
3434	#ifdef VBOX_WITH_RAW_MODE
3435	if ( enmSwitcher != VMMSWITCHER_INVALID
3436	&& !HMIsEnabled(pVM))
3437	{
3438	/*
3439	* Select new switcher.
3440	*/
3441	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3442	if (RT_FAILURE(rc))
3443	{
3444	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3445	return rc;
3446	}
3447	}
3448	#endif
3449
3450	/*
3451	* Exit old mode(s).
3452	*/
3453	#if HC_ARCH_BITS == 32
3454	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3455	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3456	&& enmShadowMode == PGMMODE_NESTED);
3457	#else
3458	const bool fForceShwEnterExit = false;
3459	#endif
3460	/* shadow */
3461	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3462	\|\| fForceShwEnterExit)
3463	{
3464	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3465	if (PGM_SHW_PFN(Exit, pVCpu))
3466	{
3467	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3468	if (RT_FAILURE(rc))
3469	{
3470	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3471	return rc;
3472	}
3473	}
3474
3475	}
3476	else
3477	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3478
3479	/* guest */
3480	if (PGM_GST_PFN(Exit, pVCpu))
3481	{
3482	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3483	if (RT_FAILURE(rc))
3484	{
3485	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3486	return rc;
3487	}
3488	}
3489
3490	/*
3491	* Load new paging mode data.
3492	*/
3493	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3494
3495	/*
3496	* Enter new shadow mode (if changed).
3497	*/
3498	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3499	\|\| fForceShwEnterExit)
3500	{
3501	int rc;
3502	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3503	switch (enmShadowMode)
3504	{
3505	case PGMMODE_32_BIT:
3506	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3507	break;
3508	case PGMMODE_PAE:
3509	case PGMMODE_PAE_NX:
3510	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3511	break;
3512	case PGMMODE_AMD64:
3513	case PGMMODE_AMD64_NX:
3514	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3515	break;
3516	case PGMMODE_NESTED:
3517	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3518	break;
3519	case PGMMODE_EPT:
3520	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3521	break;
3522	case PGMMODE_REAL:
3523	case PGMMODE_PROTECTED:
3524	default:
3525	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3526	return VERR_INTERNAL_ERROR;
3527	}
3528	if (RT_FAILURE(rc))
3529	{
3530	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3531	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3532	return rc;
3533	}
3534	}
3535
3536	/*
3537	* Always flag the necessary updates
3538	*/
3539	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3540
3541	/*
3542	* Enter the new guest and shadow+guest modes.
3543	*/
3544	int rc = -1;
3545	int rc2 = -1;
3546	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3547	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3548	switch (enmGuestMode)
3549	{
3550	case PGMMODE_REAL:
3551	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3552	switch (pVCpu->pgm.s.enmShadowMode)
3553	{
3554	case PGMMODE_32_BIT:
3555	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3556	break;
3557	case PGMMODE_PAE:
3558	case PGMMODE_PAE_NX:
3559	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3560	break;
3561	case PGMMODE_NESTED:
3562	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3563	break;
3564	case PGMMODE_EPT:
3565	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3566	break;
3567	case PGMMODE_AMD64:
3568	case PGMMODE_AMD64_NX:
3569	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3570	default: AssertFailed(); break;
3571	}
3572	break;
3573
3574	case PGMMODE_PROTECTED:
3575	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3576	switch (pVCpu->pgm.s.enmShadowMode)
3577	{
3578	case PGMMODE_32_BIT:
3579	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3580	break;
3581	case PGMMODE_PAE:
3582	case PGMMODE_PAE_NX:
3583	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3584	break;
3585	case PGMMODE_NESTED:
3586	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3587	break;
3588	case PGMMODE_EPT:
3589	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3590	break;
3591	case PGMMODE_AMD64:
3592	case PGMMODE_AMD64_NX:
3593	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3594	default: AssertFailed(); break;
3595	}
3596	break;
3597
3598	case PGMMODE_32_BIT:
3599	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3600	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3601	switch (pVCpu->pgm.s.enmShadowMode)
3602	{
3603	case PGMMODE_32_BIT:
3604	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3605	break;
3606	case PGMMODE_PAE:
3607	case PGMMODE_PAE_NX:
3608	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3609	break;
3610	case PGMMODE_NESTED:
3611	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3612	break;
3613	case PGMMODE_EPT:
3614	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3615	break;
3616	case PGMMODE_AMD64:
3617	case PGMMODE_AMD64_NX:
3618	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3619	default: AssertFailed(); break;
3620	}
3621	break;
3622
3623	case PGMMODE_PAE_NX:
3624	case PGMMODE_PAE:
3625	{
3626	uint32_t u32Dummy, u32Features;
3627
3628	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3629	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3630	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3631	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (System/Processor)"));
3632
3633	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3634	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3635	switch (pVCpu->pgm.s.enmShadowMode)
3636	{
3637	case PGMMODE_PAE:
3638	case PGMMODE_PAE_NX:
3639	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3640	break;
3641	case PGMMODE_NESTED:
3642	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3643	break;
3644	case PGMMODE_EPT:
3645	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3646	break;
3647	case PGMMODE_32_BIT:
3648	case PGMMODE_AMD64:
3649	case PGMMODE_AMD64_NX:
3650	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3651	default: AssertFailed(); break;
3652	}
3653	break;
3654	}
3655
3656	#ifdef VBOX_WITH_64_BITS_GUESTS
3657	case PGMMODE_AMD64_NX:
3658	case PGMMODE_AMD64:
3659	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3660	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3661	switch (pVCpu->pgm.s.enmShadowMode)
3662	{
3663	case PGMMODE_AMD64:
3664	case PGMMODE_AMD64_NX:
3665	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3666	break;
3667	case PGMMODE_NESTED:
3668	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3669	break;
3670	case PGMMODE_EPT:
3671	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3672	break;
3673	case PGMMODE_32_BIT:
3674	case PGMMODE_PAE:
3675	case PGMMODE_PAE_NX:
3676	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3677	default: AssertFailed(); break;
3678	}
3679	break;
3680	#endif
3681
3682	default:
3683	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3684	rc = VERR_NOT_IMPLEMENTED;
3685	break;
3686	}
3687
3688	/* status codes. */
3689	AssertRC(rc);
3690	AssertRC(rc2);
3691	if (RT_SUCCESS(rc))
3692	{
3693	rc = rc2;
3694	if (RT_SUCCESS(rc)) /* no informational status codes. */
3695	rc = VINF_SUCCESS;
3696	}
3697
3698	/* Notify HM as well. */
3699	HMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3700	return rc;
3701	}
3702
3703
3704	/**
3705	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3706	*
3707	* @returns VBox status code, fully asserted.
3708	* @param pVCpu Pointer to the VMCPU.
3709	*/
3710	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3711	{
3712	/* Unmap the old CR3 value before flushing everything. */
3713	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3714	AssertRC(rc);
3715
3716	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3717	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3718	AssertRC(rc);
3719	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3720	return rc;
3721	}
3722
3723
3724	/**
3725	* Called by pgmPoolFlushAllInt after flushing the pool.
3726	*
3727	* @returns VBox status code, fully asserted.
3728	* @param pVM Pointer to the VM.
3729	* @param pVCpu Pointer to the VMCPU.
3730	*/
3731	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3732	{
3733	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3734	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3735	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3736	AssertRCReturn(rc, rc);
3737	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3738
3739	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3740	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3741	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3742	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3743	return rc;
3744	}
3745
3746
3747	/**
3748	* Called by PGMR3PhysSetA20 after changing the A20 state.
3749	*
3750	* @param pVCpu Pointer to the VMCPU.
3751	*/
3752	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
3753	{
3754	/** @todo Probably doing a bit too much here. */
3755	int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
3756	AssertReleaseRC(rc);
3757	rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
3758	AssertReleaseRC(rc);
3759	}
3760
3761
3762	#ifdef VBOX_WITH_DEBUGGER
3763
3764	/**
3765	* @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
3766	*/
3767	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3768	{
3769	/*
3770	* Validate input.
3771	*/
3772	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3773	PVM pVM = pUVM->pVM;
3774	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
3775
3776	if (!cArgs)
3777	{
3778	/*
3779	* Print the list of error injection locations with status.
3780	*/
3781	DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
3782	DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3783	}
3784	else
3785	{
3786	/*
3787	* String switch on where to inject the error.
3788	*/
3789	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
3790	const char *pszWhere = paArgs[0].u.pszString;
3791	if (!strcmp(pszWhere, "handy"))
3792	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
3793	else
3794	return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
3795	DBGCCmdHlpPrintf(pCmdHlp, "done\n");
3796	}
3797	return VINF_SUCCESS;
3798	}
3799
3800
3801	/**
3802	* @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
3803	*/
3804	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3805	{
3806	/*
3807	* Validate input.
3808	*/
3809	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3810	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3811	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3812	if (!pVCpu)
3813	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3814
3815	/*
3816	* Force page directory sync.
3817	*/
3818	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3819
3820	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
3821	if (RT_FAILURE(rc))
3822	return rc;
3823
3824	return VINF_SUCCESS;
3825	}
3826
3827	#ifdef VBOX_STRICT
3828
3829	/**
3830	* EMT callback for pgmR3CmdAssertCR3.
3831	*
3832	* @returns VBox status code.
3833	* @param pUVM The user mode VM handle.
3834	* @param pcErrors Where to return the error count.
3835	*/
3836	static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
3837	{
3838	PVM pVM = pUVM->pVM;
3839	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3840	PVMCPU pVCpu = VMMGetCpu(pVM);
3841
3842	*pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
3843
3844	return VINF_SUCCESS;
3845	}
3846
3847
3848	/**
3849	* @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
3850	*/
3851	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3852	{
3853	/*
3854	* Validate input.
3855	*/
3856	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3857	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3858
3859	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
3860	if (RT_FAILURE(rc))
3861	return rc;
3862
3863	unsigned cErrors = 0;
3864	rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
3865	if (RT_FAILURE(rc))
3866	return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
3867	if (cErrors > 0)
3868	return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
3869	return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
3870	}
3871
3872	#endif /* VBOX_STRICT */
3873
3874	/**
3875	* @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
3876	*/
3877	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3878	{
3879	/*
3880	* Validate input.
3881	*/
3882	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3883	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3884	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3885	if (!pVCpu)
3886	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3887
3888	/*
3889	* Force page directory sync.
3890	*/
3891	int rc;
3892	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3893	{
3894	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3895	rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
3896	}
3897	else
3898	{
3899	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3900	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3901	rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
3902	}
3903	return rc;
3904	}
3905
3906
3907	/**
3908	* @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
3909	*/
3910	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3911	{
3912	/*
3913	* Validate input.
3914	*/
3915	NOREF(pCmd);
3916	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3917	PVM pVM = pUVM->pVM;
3918	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 \|\| cArgs == 2);
3919	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType == DBGCVAR_TYPE_STRING);
3920	if (cArgs == 2)
3921	{
3922	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[1].enmType == DBGCVAR_TYPE_STRING);
3923	if (strcmp(paArgs[1].u.pszString, "nozero"))
3924	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
3925	}
3926	bool fIncZeroPgs = cArgs < 2;
3927
3928	/*
3929	* Open the output file and get the ram parameters.
3930	*/
3931	RTFILE hFile;
3932	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
3933	if (RT_FAILURE(rc))
3934	return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
3935
3936	uint32_t cbRamHole = 0;
3937	CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
3938	uint64_t cbRam = 0;
3939	CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
3940	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
3941
3942	/*
3943	* Dump the physical memory, page by page.
3944	*/
3945	RTGCPHYS GCPhys = 0;
3946	char abZeroPg[PAGE_SIZE];
3947	RT_ZERO(abZeroPg);
3948
3949	pgmLock(pVM);
3950	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3951	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
3952	pRam = pRam->pNextR3)
3953	{
3954	/* fill the gap */
3955	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
3956	{
3957	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
3958	{
3959	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3960	GCPhys += PAGE_SIZE;
3961	}
3962	}
3963
3964	PCPGMPAGE pPage = &pRam->aPages[0];
3965	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
3966	{
3967	if ( PGM_PAGE_IS_ZERO(pPage)
3968	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3969	{
3970	if (fIncZeroPgs)
3971	{
3972	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3973	if (RT_FAILURE(rc))
3974	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3975	}
3976	}
3977	else
3978	{
3979	switch (PGM_PAGE_GET_TYPE(pPage))
3980	{
3981	case PGMPAGETYPE_RAM:
3982	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
3983	case PGMPAGETYPE_ROM:
3984	case PGMPAGETYPE_MMIO2:
3985	{
3986	void const *pvPage;
3987	PGMPAGEMAPLOCK Lock;
3988	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
3989	if (RT_SUCCESS(rc))
3990	{
3991	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
3992	PGMPhysReleasePageMappingLock(pVM, &Lock);
3993	if (RT_FAILURE(rc))
3994	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3995	}
3996	else
3997	DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3998	break;
3999	}
4000
4001	default:
4002	AssertFailed();
4003	case PGMPAGETYPE_MMIO:
4004	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4005	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
4006	if (fIncZeroPgs)
4007	{
4008	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4009	if (RT_FAILURE(rc))
4010	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4011	}
4012	break;
4013	}
4014	}
4015
4016
4017	/* advance */
4018	GCPhys += PAGE_SIZE;
4019	pPage++;
4020	}
4021	}
4022	pgmUnlock(pVM);
4023
4024	RTFileClose(hFile);
4025	if (RT_SUCCESS(rc))
4026	return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4027	return VINF_SUCCESS;
4028	}
4029
4030	#endif /* VBOX_WITH_DEBUGGER */
4031
4032	/**
4033	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4034	*/
4035	typedef struct PGMCHECKINTARGS
4036	{
4037	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4038	PPGMPHYSHANDLER pPrevPhys;
4039	PPGMVIRTHANDLER pPrevVirt;
4040	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4041	PVM pVM;
4042	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4043
4044	/**
4045	* Validate a node in the physical handler tree.
4046	*
4047	* @returns 0 on if ok, other wise 1.
4048	* @param pNode The handler node.
4049	* @param pvUser pVM.
4050	*/
4051	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4052	{
4053	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4054	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4055	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4056	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,
4057	("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4058	AssertReleaseMsg( !pArgs->pPrevPhys
4059	\|\| ( pArgs->fLeftToRight
4060	? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key
4061	: pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4062	("pPrevPhys=%p %RGp-%RGp %s\n"
4063	" pCur=%p %RGp-%RGp %s\n",
4064	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4065	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4066	pArgs->pPrevPhys = pCur;
4067	return 0;
4068	}
4069
4070
4071	/**
4072	* Validate a node in the virtual handler tree.
4073	*
4074	* @returns 0 on if ok, other wise 1.
4075	* @param pNode The handler node.
4076	* @param pvUser pVM.
4077	*/
4078	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4079	{
4080	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4081	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4082	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4083	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4084	AssertReleaseMsg( !pArgs->pPrevVirt
4085	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4086	("pPrevVirt=%p %RGv-%RGv %s\n"
4087	" pCur=%p %RGv-%RGv %s\n",
4088	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4089	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4090	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4091	{
4092	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4093	("pCur=%p %RGv-%RGv %s\n"
4094	"iPage=%d offVirtHandle=%#x expected %#x\n",
4095	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4096	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4097	}
4098	pArgs->pPrevVirt = pCur;
4099	return 0;
4100	}
4101
4102
4103	/**
4104	* Validate a node in the virtual handler tree.
4105	*
4106	* @returns 0 on if ok, other wise 1.
4107	* @param pNode The handler node.
4108	* @param pvUser pVM.
4109	*/
4110	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4111	{
4112	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4113	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4114	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4115	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4116	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4117	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4118	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4119	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4120	" pCur=%p %RGp-%RGp\n",
4121	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4122	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4123	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4124	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4125	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4126	" pCur=%p %RGp-%RGp\n",
4127	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4128	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4129	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4130	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4131	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4132	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4133	{
4134	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4135	for (;;)
4136	{
4137	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4138	AssertReleaseMsg(pCur2 != pCur,
4139	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4140	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4141	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4142	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4143	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4144	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4145	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4146	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4147	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4148	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4149	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4150	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4151	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4152	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4153	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4154	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4155	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4156	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4157	break;
4158	}
4159	}
4160
4161	pArgs->pPrevPhys2Virt = pCur;
4162	return 0;
4163	}
4164
4165
4166	/**
4167	* Perform an integrity check on the PGM component.
4168	*
4169	* @returns VINF_SUCCESS if everything is fine.
4170	* @returns VBox error status after asserting on integrity breach.
4171	* @param pVM Pointer to the VM.
4172	*/
4173	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4174	{
4175	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4176
4177	/*
4178	* Check the trees.
4179	*/
4180	int cErrors = 0;
4181	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4182	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4183	PGMCHECKINTARGS Args = s_LeftToRight;
4184	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4185	Args = s_RightToLeft;
4186	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4187	Args = s_LeftToRight;
4188	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4189	Args = s_RightToLeft;
4190	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4191	Args = s_LeftToRight;
4192	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4193	Args = s_RightToLeft;
4194	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4195	Args = s_LeftToRight;
4196	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4197	Args = s_RightToLeft;
4198	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4199
4200	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4201	}
4202

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 55890

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