PGM.cpp@ 73250

Last change on this file since 73250 was 73250, checked in by vboxsync, 6 years ago
PGM: Working on eliminating PGMMODEDATA and the corresponding PGMCPU section so we can do mode switching in ring-0. This forth part dealing with shadow+guest paging pointers and finally removing the PGMMODEDATA type. bugref:9044
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1	/* $Id: PGM.cpp 73250 2018-07-19 17:57:31Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @sa @ref grp_pgm
22	* @subpage pg_pgm_pool
23	* @subpage pg_pgm_phys
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred
30	* to as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	* Note! The intermediate memory context is also used for 64-bit guest
85	* execution on 32-bit hosts. Because we need to load 64-bit registers
86	* prior to switching to guest context, we need to be in 64-bit mode
87	* first. So, HM has some 64-bit worker routines in VMMRC.rc that get
88	* invoked via the special world switcher code in LegacyToAMD64.asm.
89	*
90	*
91	* @subsection subsec_pgm_int_gc Guest Context Mappings
92	*
93	* During assignment and relocation of a guest context mapping the intermediate
94	* memory context is used to verify the new location.
95	*
96	* Guest context mappings are currently restricted to below 4GB, for reasons
97	* of simplicity. This may change when we implement AMD64 support.
98	*
99	*
100	*
101	*
102	* @section sec_pgm_misc Misc
103	*
104	*
105	* @subsection sec_pgm_misc_A20 The A20 Gate
106	*
107	* PGM implements the A20 gate masking when translating a virtual guest address
108	* into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
109	* the code reading the guest page table entries during shadowing. The masking
110	* is done consistenly for all CPU modes, paged ones included. Large pages are
111	* also masked correctly. (On current CPUs, experiments indicates that AMD does
112	* not apply A20M in paged modes and intel only does it for the 2nd MB of
113	* memory.)
114	*
115	* The A20 gate implementation is per CPU core. It can be configured on a per
116	* core basis via the keyboard device and PC architecture device. This is
117	* probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
118	* guest OSes try pushing things anyway, so who cares. (On current real systems
119	* the A20M signal is probably only sent to the boot CPU and it affects all
120	* thread and probably all cores in that package.)
121	*
122	* The keyboard device and the PC architecture device doesn't OR their A20
123	* config bits together, rather they are currently implemented such that they
124	* mirror the CPU state. So, flipping the bit in either of them will change the
125	* A20 state. (On real hardware the bits of the two devices should probably be
126	* ORed together to indicate enabled, i.e. both needs to be cleared to disable
127	* A20 masking.)
128	*
129	* The A20 state will change immediately, transmeta fashion. There is no delays
130	* due to buses, wiring or other physical stuff. (On real hardware there are
131	* normally delays, the delays differs between the two devices and probably also
132	* between chipsets and CPU generations. Note that it's said that transmeta CPUs
133	* does the change immediately like us, they apparently intercept/handles the
134	* port accesses in microcode. Neat.)
135	*
136	* @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
137	*
138	*
139	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
140	*
141	* The differences between legacy PAE and long mode PAE are:
142	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
143	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
144	* usual meanings while 6 is ignored (AMD). This means that upon switching to
145	* legacy PAE mode we'll have to clear these bits and when going to long mode
146	* they must be set. This applies to both intermediate and shadow contexts,
147	* however we don't need to do it for the intermediate one since we're
148	* executing with CR0.WP at that time.
149	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
150	* a page aligned one is required.
151	*
152	*
153	* @section sec_pgm_handlers Access Handlers
154	*
155	* Placeholder.
156	*
157	*
158	* @subsection sec_pgm_handlers_phys Physical Access Handlers
159	*
160	* Placeholder.
161	*
162	*
163	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
164	*
165	* We currently implement three types of virtual access handlers: ALL, WRITE
166	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERKIND for some more details.
167	*
168	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
169	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
170	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
171	* rest of this section is going to be about these handlers.
172	*
173	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
174	* how successful this is gonna be...
175	*
176	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
177	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
178	* and create a new node that is inserted into the AVL tree (range key). Then
179	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
180	*
181	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
182	*
183	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
184	* via the current guest CR3 and update the physical page -> virtual handler
185	* translation. Needless to say, this doesn't exactly scale very well. If any changes
186	* are detected, it will flag a virtual bit update just like we did on registration.
187	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
188	*
189	* 2b. The virtual bit update process will iterate all the pages covered by all the
190	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
191	* virtual handlers on that page.
192	*
193	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
194	* we don't miss any alias mappings of the monitored pages.
195	*
196	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
197	*
198	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
199	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
200	* will call the handlers like in the next step. If the physical mapping has
201	* changed we will - some time in the future - perform a handler callback
202	* (optional) and update the physical -> virtual handler cache.
203	*
204	* 4. \#PF(,write) on a page in the range. This will cause the handler to
205	* be invoked.
206	*
207	* 5. The guest invalidates the page and changes the physical backing or
208	* unmaps it. This should cause the invalidation callback to be invoked
209	* (it might not yet be 100% perfect). Exactly what happens next... is
210	* this where we mess up and end up out of sync for a while?
211	*
212	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
213	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
214	* this handler to NONE and trigger a full PGM resync (basically the same
215	* as int step 1). Which means 2 is executed again.
216	*
217	*
218	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
219	*
220	* There is a bunch of things that needs to be done to make the virtual handlers
221	* work 100% correctly and work more efficiently.
222	*
223	* The first bit hasn't been implemented yet because it's going to slow the
224	* whole mess down even more, and besides it seems to be working reliably for
225	* our current uses. OTOH, some of the optimizations might end up more or less
226	* implementing the missing bits, so we'll see.
227	*
228	* On the optimization side, the first thing to do is to try avoid unnecessary
229	* cache flushing. Then try team up with the shadowing code to track changes
230	* in mappings by means of access to them (shadow in), updates to shadows pages,
231	* invlpg, and shadow PT discarding (perhaps).
232	*
233	* Some idea that have popped up for optimization for current and new features:
234	* - bitmap indicating where there are virtual handlers installed.
235	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
236	* - Further optimize this by min/max (needs min/max avl getters).
237	* - Shadow page table entry bit (if any left)?
238	*
239	*/
240
241
242	/** @page pg_pgm_phys PGM Physical Guest Memory Management
243	*
244	*
245	* Objectives:
246	* - Guest RAM over-commitment using memory ballooning,
247	* zero pages and general page sharing.
248	* - Moving or mirroring a VM onto a different physical machine.
249	*
250	*
251	* @section sec_pgmPhys_Definitions Definitions
252	*
253	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
254	* machinery associated with it.
255	*
256	*
257	*
258	*
259	* @section sec_pgmPhys_AllocPage Allocating a page.
260	*
261	* Initially we map all guest memory to the (per VM) zero page, which
262	* means that none of the read functions will cause pages to be allocated.
263	*
264	* Exception, access bit in page tables that have been shared. This must
265	* be handled, but we must also make sure PGMGst*Modify doesn't make
266	* unnecessary modifications.
267	*
268	* Allocation points:
269	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
270	* - Replacing a zero page mapping at \#PF.
271	* - Replacing a shared page mapping at \#PF.
272	* - ROM registration (currently MMR3RomRegister).
273	* - VM restore (pgmR3Load).
274	*
275	* For the first three it would make sense to keep a few pages handy
276	* until we've reached the max memory commitment for the VM.
277	*
278	* For the ROM registration, we know exactly how many pages we need
279	* and will request these from ring-0. For restore, we will save
280	* the number of non-zero pages in the saved state and allocate
281	* them up front. This would allow the ring-0 component to refuse
282	* the request if the isn't sufficient memory available for VM use.
283	*
284	* Btw. for both ROM and restore allocations we won't be requiring
285	* zeroed pages as they are going to be filled instantly.
286	*
287	*
288	* @section sec_pgmPhys_FreePage Freeing a page
289	*
290	* There are a few points where a page can be freed:
291	* - After being replaced by the zero page.
292	* - After being replaced by a shared page.
293	* - After being ballooned by the guest additions.
294	* - At reset.
295	* - At restore.
296	*
297	* When freeing one or more pages they will be returned to the ring-0
298	* component and replaced by the zero page.
299	*
300	* The reasoning for clearing out all the pages on reset is that it will
301	* return us to the exact same state as on power on, and may thereby help
302	* us reduce the memory load on the system. Further it might have a
303	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
304	*
305	* On restore, as mention under the allocation topic, pages should be
306	* freed / allocated depending on how many is actually required by the
307	* new VM state. The simplest approach is to do like on reset, and free
308	* all non-ROM pages and then allocate what we need.
309	*
310	* A measure to prevent some fragmentation, would be to let each allocation
311	* chunk have some affinity towards the VM having allocated the most pages
312	* from it. Also, try make sure to allocate from allocation chunks that
313	* are almost full. Admittedly, both these measures might work counter to
314	* our intentions and its probably not worth putting a lot of effort,
315	* cpu time or memory into this.
316	*
317	*
318	* @section sec_pgmPhys_SharePage Sharing a page
319	*
320	* The basic idea is that there there will be a idle priority kernel
321	* thread walking the non-shared VM pages hashing them and looking for
322	* pages with the same checksum. If such pages are found, it will compare
323	* them byte-by-byte to see if they actually are identical. If found to be
324	* identical it will allocate a shared page, copy the content, check that
325	* the page didn't change while doing this, and finally request both the
326	* VMs to use the shared page instead. If the page is all zeros (special
327	* checksum and byte-by-byte check) it will request the VM that owns it
328	* to replace it with the zero page.
329	*
330	* To make this efficient, we will have to make sure not to try share a page
331	* that will change its contents soon. This part requires the most work.
332	* A simple idea would be to request the VM to write monitor the page for
333	* a while to make sure it isn't modified any time soon. Also, it may
334	* make sense to skip pages that are being write monitored since this
335	* information is readily available to the thread if it works on the
336	* per-VM guest memory structures (presently called PGMRAMRANGE).
337	*
338	*
339	* @section sec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
340	*
341	* The pages are organized in allocation chunks in ring-0, this is a necessity
342	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
343	* could easily work on a page-by-page basis if we liked. Whether this is possible
344	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
345	* become a problem as part of the idea here is that we wish to return memory to
346	* the host system.
347	*
348	* For instance, starting two VMs at the same time, they will both allocate the
349	* guest memory on-demand and if permitted their page allocations will be
350	* intermixed. Shut down one of the two VMs and it will be difficult to return
351	* any memory to the host system because the page allocation for the two VMs are
352	* mixed up in the same allocation chunks.
353	*
354	* To further complicate matters, when pages are freed because they have been
355	* ballooned or become shared/zero the whole idea is that the page is supposed
356	* to be reused by another VM or returned to the host system. This will cause
357	* allocation chunks to contain pages belonging to different VMs and prevent
358	* returning memory to the host when one of those VM shuts down.
359	*
360	* The only way to really deal with this problem is to move pages. This can
361	* either be done at VM shutdown and or by the idle priority worker thread
362	* that will be responsible for finding sharable/zero pages. The mechanisms
363	* involved for coercing a VM to move a page (or to do it for it) will be
364	* the same as when telling it to share/zero a page.
365	*
366	*
367	* @section sec_pgmPhys_Tracking Tracking Structures And Their Cost
368	*
369	* There's a difficult balance between keeping the per-page tracking structures
370	* (global and guest page) easy to use and keeping them from eating too much
371	* memory. We have limited virtual memory resources available when operating in
372	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
373	* tracking structures will be attempted designed such that we can deal with up
374	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
375	*
376	*
377	* @subsection subsec_pgmPhys_Tracking_Kernel Kernel Space
378	*
379	* @see pg_GMM
380	*
381	* @subsection subsec_pgmPhys_Tracking_PerVM Per-VM
382	*
383	* Fixed info is the physical address of the page (HCPhys) and the page id
384	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
385	* Today we've restricting ourselves to 40(-12) bits because this is the current
386	* restrictions of all AMD64 implementations (I think Barcelona will up this
387	* to 48(-12) bits, not that it really matters) and I needed the bits for
388	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
389	* decent range for the page id: 2^(28+12) = 1024TB.
390	*
391	* In additions to these, we'll have to keep maintaining the page flags as we
392	* currently do. Although it wouldn't harm to optimize these quite a bit, like
393	* for instance the ROM shouldn't depend on having a write handler installed
394	* in order for it to become read-only. A RO/RW bit should be considered so
395	* that the page syncing code doesn't have to mess about checking multiple
396	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
397	* figure out how to setup a shadow PTE. But this of course, is second
398	* priority at present. Current this requires 12 bits, but could probably
399	* be optimized to ~8.
400	*
401	* Then there's the 24 bits used to track which shadow page tables are
402	* currently mapping a page for the purpose of speeding up physical
403	* access handlers, and thereby the page pool cache. More bit for this
404	* purpose wouldn't hurt IIRC.
405	*
406	* Then there is a new bit in which we need to record what kind of page
407	* this is, shared, zero, normal or write-monitored-normal. This'll
408	* require 2 bits. One bit might be needed for indicating whether a
409	* write monitored page has been written to. And yet another one or
410	* two for tracking migration status. 3-4 bits total then.
411	*
412	* Whatever is left will can be used to record the sharabilitiy of a
413	* page. The page checksum will not be stored in the per-VM table as
414	* the idle thread will not be permitted to do modifications to it.
415	* It will instead have to keep its own working set of potentially
416	* shareable pages and their check sums and stuff.
417	*
418	* For the present we'll keep the current packing of the
419	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
420	* we'll have to change it to a struct with a total of 128-bits at
421	* our disposal.
422	*
423	* The initial layout will be like this:
424	* @verbatim
425	RTHCPHYS HCPhys; The current stuff.
426	63:40 Current shadow PT tracking stuff.
427	39:12 The physical page frame number.
428	11:0 The current flags.
429	uint32_t u28PageId : 28; The page id.
430	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
431	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
432	uint32_t u1Reserved : 1; Reserved for later.
433	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
434	@endverbatim
435	*
436	* The final layout will be something like this:
437	* @verbatim
438	RTHCPHYS HCPhys; The current stuff.
439	63:48 High page id (12+).
440	47:12 The physical page frame number.
441	11:0 Low page id.
442	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
443	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
444	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
445	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
446	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
447	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
448	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
449	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
450	@endverbatim
451	*
452	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
453	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
454	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
455	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
456	*
457	* A couple of cost examples for the total cost per-VM + kernel.
458	* 32-bit Windows and 32-bit linux:
459	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
460	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
461	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
462	* 64-bit Windows and 64-bit linux:
463	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
464	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
465	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
466	*
467	* UPDATE - 2007-09-27:
468	* Will need a ballooned flag/state too because we cannot
469	* trust the guest 100% and reporting the same page as ballooned more
470	* than once will put the GMM off balance.
471	*
472	*
473	* @section sec_pgmPhys_Serializing Serializing Access
474	*
475	* Initially, we'll try a simple scheme:
476	*
477	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
478	* by the EMT thread of that VM while in the pgm critsect.
479	* - Other threads in the VM process that needs to make reliable use of
480	* the per-VM RAM tracking structures will enter the critsect.
481	* - No process external thread or kernel thread will ever try enter
482	* the pgm critical section, as that just won't work.
483	* - The idle thread (and similar threads) doesn't not need 100% reliable
484	* data when performing it tasks as the EMT thread will be the one to
485	* do the actual changes later anyway. So, as long as it only accesses
486	* the main ram range, it can do so by somehow preventing the VM from
487	* being destroyed while it works on it...
488	*
489	* - The over-commitment management, including the allocating/freeing
490	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
491	* more mundane mutex implementation is broken on Linux).
492	* - A separate mutex is protecting the set of allocation chunks so
493	* that pages can be shared or/and freed up while some other VM is
494	* allocating more chunks. This mutex can be take from under the other
495	* one, but not the other way around.
496	*
497	*
498	* @section sec_pgmPhys_Request VM Request interface
499	*
500	* When in ring-0 it will become necessary to send requests to a VM so it can
501	* for instance move a page while defragmenting during VM destroy. The idle
502	* thread will make use of this interface to request VMs to setup shared
503	* pages and to perform write monitoring of pages.
504	*
505	* I would propose an interface similar to the current VMReq interface, similar
506	* in that it doesn't require locking and that the one sending the request may
507	* wait for completion if it wishes to. This shouldn't be very difficult to
508	* realize.
509	*
510	* The requests themselves are also pretty simple. They are basically:
511	* -# Check that some precondition is still true.
512	* -# Do the update.
513	* -# Update all shadow page tables involved with the page.
514	*
515	* The 3rd step is identical to what we're already doing when updating a
516	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
517	*
518	*
519	*
520	* @section sec_pgmPhys_MappingCaches Mapping Caches
521	*
522	* In order to be able to map in and out memory and to be able to support
523	* guest with more RAM than we've got virtual address space, we'll employing
524	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
525	* however on 32-bit darwin the ring-0 code is running in a different memory
526	* context and therefore needs a separate cache. In raw-mode context we also
527	* need a separate cache. The 32-bit darwin mapping cache and the one for
528	* raw-mode context share a lot of code, see PGMRZDYNMAP.
529	*
530	*
531	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
532	*
533	* We've considered implementing the ring-3 mapping cache page based but found
534	* that this was bother some when one had to take into account TLBs+SMP and
535	* portability (missing the necessary APIs on several platforms). There were
536	* also some performance concerns with this approach which hadn't quite been
537	* worked out.
538	*
539	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
540	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
541	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
542	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
543	* costly than a single page, although how much more costly is uncertain. We'll
544	* try address this by using a very big cache, preferably bigger than the actual
545	* VM RAM size if possible. The current VM RAM sizes should give some idea for
546	* 32-bit boxes, while on 64-bit we can probably get away with employing an
547	* unlimited cache.
548	*
549	* The cache have to parts, as already indicated, the ring-3 side and the
550	* ring-0 side.
551	*
552	* The ring-0 will be tied to the page allocator since it will operate on the
553	* memory objects it contains. It will therefore require the first ring-0 mutex
554	* discussed in @ref sec_pgmPhys_Serializing. We some double house keeping wrt
555	* to who has mapped what I think, since both VMMR0.r0 and RTR0MemObj will keep
556	* track of mapping relations
557	*
558	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
559	* require anyone that desires to do changes to the mapping cache to do that
560	* from within this critsect. Alternatively, we could employ a separate critsect
561	* for serializing changes to the mapping cache as this would reduce potential
562	* contention with other threads accessing mappings unrelated to the changes
563	* that are in process. We can see about this later, contention will show
564	* up in the statistics anyway, so it'll be simple to tell.
565	*
566	* The organization of the ring-3 part will be very much like how the allocation
567	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
568	* having to walk the tree all the time, we'll have a couple of lookaside entries
569	* like in we do for I/O ports and MMIO in IOM.
570	*
571	* The simplified flow of a PGMPhysRead/Write function:
572	* -# Enter the PGM critsect.
573	* -# Lookup GCPhys in the ram ranges and get the Page ID.
574	* -# Calc the Allocation Chunk ID from the Page ID.
575	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
576	* If not found in cache:
577	* -# Call ring-0 and request it to be mapped and supply
578	* a chunk to be unmapped if the cache is maxed out already.
579	* -# Insert the new mapping into the AVL tree (id + R3 address).
580	* -# Update the relevant lookaside entry and return the mapping address.
581	* -# Do the read/write according to monitoring flags and everything.
582	* -# Leave the critsect.
583	*
584	*
585	* @section sec_pgmPhys_Fallback Fallback
586	*
587	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
588	* API and thus require a fallback.
589	*
590	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
591	* will return to the ring-3 caller (and later ring-0) and asking it to seed
592	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
593	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
594	* "SeededAllocPages" call to ring-0.
595	*
596	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
597	* all page sharing (zero page detection will continue). It will also force
598	* all allocations to come from the VM which seeded the page. Both these
599	* measures are taken to make sure that there will never be any need for
600	* mapping anything into ring-3 - everything will be mapped already.
601	*
602	* Whether we'll continue to use the current MM locked memory management
603	* for this I don't quite know (I'd prefer not to and just ditch that all
604	* together), we'll see what's simplest to do.
605	*
606	*
607	*
608	* @section sec_pgmPhys_Changes Changes
609	*
610	* Breakdown of the changes involved?
611	*/
612
613
614	/*********************************************************************************************************************************
615	* Header Files *
616	*********************************************************************************************************************************/
617	#define LOG_GROUP LOG_GROUP_PGM
618	#include <VBox/vmm/dbgf.h>
619	#include <VBox/vmm/pgm.h>
620	#include <VBox/vmm/cpum.h>
621	#include <VBox/vmm/iom.h>
622	#include <VBox/sup.h>
623	#include <VBox/vmm/mm.h>
624	#include <VBox/vmm/em.h>
625	#include <VBox/vmm/stam.h>
626	#ifdef VBOX_WITH_REM
627	# include <VBox/vmm/rem.h>
628	#endif
629	#include <VBox/vmm/selm.h>
630	#include <VBox/vmm/ssm.h>
631	#include <VBox/vmm/hm.h>
632	#include "PGMInternal.h"
633	#include <VBox/vmm/vm.h>
634	#include <VBox/vmm/uvm.h>
635	#include "PGMInline.h"
636
637	#include <VBox/dbg.h>
638	#include <VBox/param.h>
639	#include <VBox/err.h>
640
641	#include <iprt/asm.h>
642	#include <iprt/asm-amd64-x86.h>
643	#include <iprt/assert.h>
644	#include <iprt/env.h>
645	#include <iprt/mem.h>
646	#include <iprt/file.h>
647	#include <iprt/string.h>
648	#include <iprt/thread.h>
649
650
651	/*********************************************************************************************************************************
652	* Structures and Typedefs *
653	*********************************************************************************************************************************/
654	/**
655	* Argument package for pgmR3RElocatePhysHnadler, pgmR3RelocateVirtHandler and
656	* pgmR3RelocateHyperVirtHandler.
657	*/
658	typedef struct PGMRELOCHANDLERARGS
659	{
660	RTGCINTPTR offDelta;
661	PVM pVM;
662	} PGMRELOCHANDLERARGS;
663	/** Pointer to a page access handlere relocation argument package. */
664	typedef PGMRELOCHANDLERARGS const *PCPGMRELOCHANDLERARGS;
665
666
667	/*********************************************************************************************************************************
668	* Internal Functions *
669	*********************************************************************************************************************************/
670	static int pgmR3InitPaging(PVM pVM);
671	static int pgmR3InitStats(PVM pVM);
672	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
673	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
674	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
675	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
676	#ifdef VBOX_WITH_RAW_MODE
677	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
678	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
679	#endif /* VBOX_WITH_RAW_MODE */
680	#ifdef VBOX_STRICT
681	static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
682	#endif
683	static void pgmR3ModeDataSwitch(PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
684	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
685
686	#ifdef VBOX_WITH_DEBUGGER
687	static FNDBGCCMD pgmR3CmdError;
688	static FNDBGCCMD pgmR3CmdSync;
689	static FNDBGCCMD pgmR3CmdSyncAlways;
690	# ifdef VBOX_STRICT
691	static FNDBGCCMD pgmR3CmdAssertCR3;
692	# endif
693	static FNDBGCCMD pgmR3CmdPhysToFile;
694	#endif
695
696
697	/*********************************************************************************************************************************
698	* Global Variables *
699	*********************************************************************************************************************************/
700	#ifdef VBOX_WITH_DEBUGGER
701	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
702	static const DBGCVARDESC g_aPgmErrorArgs[] =
703	{
704	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
705	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
706	};
707
708	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
709	{
710	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
711	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
712	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
713	};
714
715	# ifdef DEBUG_sandervl
716	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
717	{
718	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
719	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
720	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
721	};
722	# endif
723
724	/** Command descriptors. */
725	static const DBGCCMD g_aCmds[] =
726	{
727	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
728	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
729	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
730	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
731	# ifdef VBOX_STRICT
732	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
733	# ifdef VBOX_WITH_PAGE_SHARING
734	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
735	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
736	# endif
737	# endif
738	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
739	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
740	};
741	#endif
742
743
744
745
746	/*
747	* Shadow - 32-bit mode
748	*/
749	#define PGM_SHW_TYPE PGM_TYPE_32BIT
750	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
751	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
752	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
753	#include "PGMShw.h"
754
755	/* Guest - real mode */
756	#define PGM_GST_TYPE PGM_TYPE_REAL
757	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
758	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
759	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
760	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
761	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
762	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
763	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
764	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
765	#include "PGMBth.h"
766	#include "PGMGstDefs.h"
767	#include "PGMGst.h"
768	#undef BTH_PGMPOOLKIND_PT_FOR_PT
769	#undef BTH_PGMPOOLKIND_ROOT
770	#undef PGM_BTH_NAME
771	#undef PGM_BTH_NAME_RC_STR
772	#undef PGM_BTH_NAME_R0_STR
773	#undef PGM_GST_TYPE
774	#undef PGM_GST_NAME
775	#undef PGM_GST_NAME_RC_STR
776	#undef PGM_GST_NAME_R0_STR
777
778	/* Guest - protected mode */
779	#define PGM_GST_TYPE PGM_TYPE_PROT
780	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
781	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
782	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
783	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
784	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
785	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
786	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
787	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
788	#include "PGMBth.h"
789	#include "PGMGstDefs.h"
790	#include "PGMGst.h"
791	#undef BTH_PGMPOOLKIND_PT_FOR_PT
792	#undef BTH_PGMPOOLKIND_ROOT
793	#undef PGM_BTH_NAME
794	#undef PGM_BTH_NAME_RC_STR
795	#undef PGM_BTH_NAME_R0_STR
796	#undef PGM_GST_TYPE
797	#undef PGM_GST_NAME
798	#undef PGM_GST_NAME_RC_STR
799	#undef PGM_GST_NAME_R0_STR
800
801	/* Guest - 32-bit mode */
802	#define PGM_GST_TYPE PGM_TYPE_32BIT
803	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
804	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
805	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
806	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
807	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
808	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
809	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
810	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
811	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
812	#include "PGMBth.h"
813	#include "PGMGstDefs.h"
814	#include "PGMGst.h"
815	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
816	#undef BTH_PGMPOOLKIND_PT_FOR_PT
817	#undef BTH_PGMPOOLKIND_ROOT
818	#undef PGM_BTH_NAME
819	#undef PGM_BTH_NAME_RC_STR
820	#undef PGM_BTH_NAME_R0_STR
821	#undef PGM_GST_TYPE
822	#undef PGM_GST_NAME
823	#undef PGM_GST_NAME_RC_STR
824	#undef PGM_GST_NAME_R0_STR
825
826	#undef PGM_SHW_TYPE
827	#undef PGM_SHW_NAME
828	#undef PGM_SHW_NAME_RC_STR
829	#undef PGM_SHW_NAME_R0_STR
830
831
832	/*
833	* Shadow - PAE mode
834	*/
835	#define PGM_SHW_TYPE PGM_TYPE_PAE
836	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
837	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
838	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
839	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
840	#include "PGMShw.h"
841
842	/* Guest - real mode */
843	#define PGM_GST_TYPE PGM_TYPE_REAL
844	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
845	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
846	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
847	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
848	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
849	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
850	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
851	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
852	#include "PGMGstDefs.h"
853	#include "PGMBth.h"
854	#undef BTH_PGMPOOLKIND_PT_FOR_PT
855	#undef BTH_PGMPOOLKIND_ROOT
856	#undef PGM_BTH_NAME
857	#undef PGM_BTH_NAME_RC_STR
858	#undef PGM_BTH_NAME_R0_STR
859	#undef PGM_GST_TYPE
860	#undef PGM_GST_NAME
861	#undef PGM_GST_NAME_RC_STR
862	#undef PGM_GST_NAME_R0_STR
863
864	/* Guest - protected mode */
865	#define PGM_GST_TYPE PGM_TYPE_PROT
866	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
867	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
868	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
869	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
870	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
871	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
872	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
873	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
874	#include "PGMGstDefs.h"
875	#include "PGMBth.h"
876	#undef BTH_PGMPOOLKIND_PT_FOR_PT
877	#undef BTH_PGMPOOLKIND_ROOT
878	#undef PGM_BTH_NAME
879	#undef PGM_BTH_NAME_RC_STR
880	#undef PGM_BTH_NAME_R0_STR
881	#undef PGM_GST_TYPE
882	#undef PGM_GST_NAME
883	#undef PGM_GST_NAME_RC_STR
884	#undef PGM_GST_NAME_R0_STR
885
886	/* Guest - 32-bit mode */
887	#define PGM_GST_TYPE PGM_TYPE_32BIT
888	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
889	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
890	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
891	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
892	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
893	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
894	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
895	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
896	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
897	#include "PGMGstDefs.h"
898	#include "PGMBth.h"
899	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
900	#undef BTH_PGMPOOLKIND_PT_FOR_PT
901	#undef BTH_PGMPOOLKIND_ROOT
902	#undef PGM_BTH_NAME
903	#undef PGM_BTH_NAME_RC_STR
904	#undef PGM_BTH_NAME_R0_STR
905	#undef PGM_GST_TYPE
906	#undef PGM_GST_NAME
907	#undef PGM_GST_NAME_RC_STR
908	#undef PGM_GST_NAME_R0_STR
909
910	/* Guest - PAE mode */
911	#define PGM_GST_TYPE PGM_TYPE_PAE
912	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
913	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
914	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
915	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
916	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
917	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
918	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
919	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
920	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
921	#include "PGMBth.h"
922	#include "PGMGstDefs.h"
923	#include "PGMGst.h"
924	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
925	#undef BTH_PGMPOOLKIND_PT_FOR_PT
926	#undef BTH_PGMPOOLKIND_ROOT
927	#undef PGM_BTH_NAME
928	#undef PGM_BTH_NAME_RC_STR
929	#undef PGM_BTH_NAME_R0_STR
930	#undef PGM_GST_TYPE
931	#undef PGM_GST_NAME
932	#undef PGM_GST_NAME_RC_STR
933	#undef PGM_GST_NAME_R0_STR
934
935	#undef PGM_SHW_TYPE
936	#undef PGM_SHW_NAME
937	#undef PGM_SHW_NAME_RC_STR
938	#undef PGM_SHW_NAME_R0_STR
939
940
941	/*
942	* Shadow - AMD64 mode
943	*/
944	#define PGM_SHW_TYPE PGM_TYPE_AMD64
945	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
946	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
947	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
948	#include "PGMShw.h"
949
950	#ifdef VBOX_WITH_64_BITS_GUESTS
951	/* Guest - AMD64 mode */
952	# define PGM_GST_TYPE PGM_TYPE_AMD64
953	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
954	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
955	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
956	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
957	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
958	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
959	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
960	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
961	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
962	# include "PGMBth.h"
963	# include "PGMGstDefs.h"
964	# include "PGMGst.h"
965	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
966	# undef BTH_PGMPOOLKIND_PT_FOR_PT
967	# undef BTH_PGMPOOLKIND_ROOT
968	# undef PGM_BTH_NAME
969	# undef PGM_BTH_NAME_RC_STR
970	# undef PGM_BTH_NAME_R0_STR
971	# undef PGM_GST_TYPE
972	# undef PGM_GST_NAME
973	# undef PGM_GST_NAME_RC_STR
974	# undef PGM_GST_NAME_R0_STR
975	#endif /* VBOX_WITH_64_BITS_GUESTS */
976
977	#undef PGM_SHW_TYPE
978	#undef PGM_SHW_NAME
979	#undef PGM_SHW_NAME_RC_STR
980	#undef PGM_SHW_NAME_R0_STR
981
982
983	/*
984	* Shadow - 32-bit nested paging mode
985	*/
986	#define PGM_SHW_TYPE PGM_TYPE_NESTED_32BIT
987	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_32BIT(name)
988	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_32BIT_STR(name)
989	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_32BIT_STR(name)
990	#include "PGMShw.h"
991
992	/* Guest - real mode */
993	#define PGM_GST_TYPE PGM_TYPE_REAL
994	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
995	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
996	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
997	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_REAL(name)
998	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name)
999	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name)
1000	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1001	#include "PGMGstDefs.h"
1002	#include "PGMBth.h"
1003	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1004	#undef PGM_BTH_NAME
1005	#undef PGM_BTH_NAME_RC_STR
1006	#undef PGM_BTH_NAME_R0_STR
1007	#undef PGM_GST_TYPE
1008	#undef PGM_GST_NAME
1009	#undef PGM_GST_NAME_RC_STR
1010	#undef PGM_GST_NAME_R0_STR
1011
1012	/* Guest - protected mode */
1013	#define PGM_GST_TYPE PGM_TYPE_PROT
1014	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1015	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1016	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1017	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PROT(name)
1018	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name)
1019	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name)
1020	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1021	#include "PGMGstDefs.h"
1022	#include "PGMBth.h"
1023	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1024	#undef PGM_BTH_NAME
1025	#undef PGM_BTH_NAME_RC_STR
1026	#undef PGM_BTH_NAME_R0_STR
1027	#undef PGM_GST_TYPE
1028	#undef PGM_GST_NAME
1029	#undef PGM_GST_NAME_RC_STR
1030	#undef PGM_GST_NAME_R0_STR
1031
1032	/* Guest - 32-bit mode */
1033	#define PGM_GST_TYPE PGM_TYPE_32BIT
1034	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1035	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1036	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1037	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_32BIT(name)
1038	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name)
1039	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name)
1040	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1041	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1042	#include "PGMGstDefs.h"
1043	#include "PGMBth.h"
1044	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1045	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1046	#undef PGM_BTH_NAME
1047	#undef PGM_BTH_NAME_RC_STR
1048	#undef PGM_BTH_NAME_R0_STR
1049	#undef PGM_GST_TYPE
1050	#undef PGM_GST_NAME
1051	#undef PGM_GST_NAME_RC_STR
1052	#undef PGM_GST_NAME_R0_STR
1053
1054	/* Guest - PAE mode */
1055	#define PGM_GST_TYPE PGM_TYPE_PAE
1056	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1057	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1058	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1059	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PAE(name)
1060	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name)
1061	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name)
1062	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1063	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1064	#include "PGMGstDefs.h"
1065	#include "PGMBth.h"
1066	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1067	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1068	#undef PGM_BTH_NAME
1069	#undef PGM_BTH_NAME_RC_STR
1070	#undef PGM_BTH_NAME_R0_STR
1071	#undef PGM_GST_TYPE
1072	#undef PGM_GST_NAME
1073	#undef PGM_GST_NAME_RC_STR
1074	#undef PGM_GST_NAME_R0_STR
1075
1076	#ifdef VBOX_WITH_64_BITS_GUESTS
1077	/* Guest - AMD64 mode */
1078	# define PGM_GST_TYPE PGM_TYPE_AMD64
1079	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1080	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1081	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1082	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_AMD64(name)
1083	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name)
1084	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name)
1085	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1086	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1087	# include "PGMGstDefs.h"
1088	# include "PGMBth.h"
1089	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1090	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1091	# undef PGM_BTH_NAME
1092	# undef PGM_BTH_NAME_RC_STR
1093	# undef PGM_BTH_NAME_R0_STR
1094	# undef PGM_GST_TYPE
1095	# undef PGM_GST_NAME
1096	# undef PGM_GST_NAME_RC_STR
1097	# undef PGM_GST_NAME_R0_STR
1098	#endif /* VBOX_WITH_64_BITS_GUESTS */
1099
1100	#undef PGM_SHW_TYPE
1101	#undef PGM_SHW_NAME
1102	#undef PGM_SHW_NAME_RC_STR
1103	#undef PGM_SHW_NAME_R0_STR
1104
1105
1106	/*
1107	* Shadow - PAE nested paging mode
1108	*/
1109	#define PGM_SHW_TYPE PGM_TYPE_NESTED_PAE
1110	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_PAE(name)
1111	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_PAE_STR(name)
1112	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_PAE_STR(name)
1113	#include "PGMShw.h"
1114
1115	/* Guest - real mode */
1116	#define PGM_GST_TYPE PGM_TYPE_REAL
1117	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1118	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1119	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1120	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_REAL(name)
1121	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name)
1122	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name)
1123	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1124	#include "PGMGstDefs.h"
1125	#include "PGMBth.h"
1126	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1127	#undef PGM_BTH_NAME
1128	#undef PGM_BTH_NAME_RC_STR
1129	#undef PGM_BTH_NAME_R0_STR
1130	#undef PGM_GST_TYPE
1131	#undef PGM_GST_NAME
1132	#undef PGM_GST_NAME_RC_STR
1133	#undef PGM_GST_NAME_R0_STR
1134
1135	/* Guest - protected mode */
1136	#define PGM_GST_TYPE PGM_TYPE_PROT
1137	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1138	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1139	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1140	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PROT(name)
1141	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name)
1142	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name)
1143	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1144	#include "PGMGstDefs.h"
1145	#include "PGMBth.h"
1146	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1147	#undef PGM_BTH_NAME
1148	#undef PGM_BTH_NAME_RC_STR
1149	#undef PGM_BTH_NAME_R0_STR
1150	#undef PGM_GST_TYPE
1151	#undef PGM_GST_NAME
1152	#undef PGM_GST_NAME_RC_STR
1153	#undef PGM_GST_NAME_R0_STR
1154
1155	/* Guest - 32-bit mode */
1156	#define PGM_GST_TYPE PGM_TYPE_32BIT
1157	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1158	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1159	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1160	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_32BIT(name)
1161	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name)
1162	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name)
1163	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1164	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1165	#include "PGMGstDefs.h"
1166	#include "PGMBth.h"
1167	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1168	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1169	#undef PGM_BTH_NAME
1170	#undef PGM_BTH_NAME_RC_STR
1171	#undef PGM_BTH_NAME_R0_STR
1172	#undef PGM_GST_TYPE
1173	#undef PGM_GST_NAME
1174	#undef PGM_GST_NAME_RC_STR
1175	#undef PGM_GST_NAME_R0_STR
1176
1177	/* Guest - PAE mode */
1178	#define PGM_GST_TYPE PGM_TYPE_PAE
1179	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1180	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1181	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1182	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PAE(name)
1183	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name)
1184	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name)
1185	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1186	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1187	#include "PGMGstDefs.h"
1188	#include "PGMBth.h"
1189	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1190	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1191	#undef PGM_BTH_NAME
1192	#undef PGM_BTH_NAME_RC_STR
1193	#undef PGM_BTH_NAME_R0_STR
1194	#undef PGM_GST_TYPE
1195	#undef PGM_GST_NAME
1196	#undef PGM_GST_NAME_RC_STR
1197	#undef PGM_GST_NAME_R0_STR
1198
1199	#ifdef VBOX_WITH_64_BITS_GUESTS
1200	/* Guest - AMD64 mode */
1201	# define PGM_GST_TYPE PGM_TYPE_AMD64
1202	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1203	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1204	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1205	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_AMD64(name)
1206	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name)
1207	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name)
1208	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1209	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1210	# include "PGMGstDefs.h"
1211	# include "PGMBth.h"
1212	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1213	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1214	# undef PGM_BTH_NAME
1215	# undef PGM_BTH_NAME_RC_STR
1216	# undef PGM_BTH_NAME_R0_STR
1217	# undef PGM_GST_TYPE
1218	# undef PGM_GST_NAME
1219	# undef PGM_GST_NAME_RC_STR
1220	# undef PGM_GST_NAME_R0_STR
1221	#endif /* VBOX_WITH_64_BITS_GUESTS */
1222
1223	#undef PGM_SHW_TYPE
1224	#undef PGM_SHW_NAME
1225	#undef PGM_SHW_NAME_RC_STR
1226	#undef PGM_SHW_NAME_R0_STR
1227
1228
1229	/*
1230	* Shadow - AMD64 nested paging mode
1231	*/
1232	#define PGM_SHW_TYPE PGM_TYPE_NESTED_AMD64
1233	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_AMD64(name)
1234	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_AMD64_STR(name)
1235	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_AMD64_STR(name)
1236	#include "PGMShw.h"
1237
1238	/* Guest - real mode */
1239	#define PGM_GST_TYPE PGM_TYPE_REAL
1240	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1241	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1242	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1243	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_REAL(name)
1244	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name)
1245	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name)
1246	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1247	#include "PGMGstDefs.h"
1248	#include "PGMBth.h"
1249	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1250	#undef PGM_BTH_NAME
1251	#undef PGM_BTH_NAME_RC_STR
1252	#undef PGM_BTH_NAME_R0_STR
1253	#undef PGM_GST_TYPE
1254	#undef PGM_GST_NAME
1255	#undef PGM_GST_NAME_RC_STR
1256	#undef PGM_GST_NAME_R0_STR
1257
1258	/* Guest - protected mode */
1259	#define PGM_GST_TYPE PGM_TYPE_PROT
1260	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1261	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1262	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1263	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PROT(name)
1264	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name)
1265	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name)
1266	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1267	#include "PGMGstDefs.h"
1268	#include "PGMBth.h"
1269	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1270	#undef PGM_BTH_NAME
1271	#undef PGM_BTH_NAME_RC_STR
1272	#undef PGM_BTH_NAME_R0_STR
1273	#undef PGM_GST_TYPE
1274	#undef PGM_GST_NAME
1275	#undef PGM_GST_NAME_RC_STR
1276	#undef PGM_GST_NAME_R0_STR
1277
1278	/* Guest - 32-bit mode */
1279	#define PGM_GST_TYPE PGM_TYPE_32BIT
1280	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1281	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1282	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1283	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_32BIT(name)
1284	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name)
1285	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name)
1286	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1287	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1288	#include "PGMGstDefs.h"
1289	#include "PGMBth.h"
1290	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1291	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1292	#undef PGM_BTH_NAME
1293	#undef PGM_BTH_NAME_RC_STR
1294	#undef PGM_BTH_NAME_R0_STR
1295	#undef PGM_GST_TYPE
1296	#undef PGM_GST_NAME
1297	#undef PGM_GST_NAME_RC_STR
1298	#undef PGM_GST_NAME_R0_STR
1299
1300	/* Guest - PAE mode */
1301	#define PGM_GST_TYPE PGM_TYPE_PAE
1302	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1303	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1304	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1305	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PAE(name)
1306	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name)
1307	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name)
1308	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1309	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1310	#include "PGMGstDefs.h"
1311	#include "PGMBth.h"
1312	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1313	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1314	#undef PGM_BTH_NAME
1315	#undef PGM_BTH_NAME_RC_STR
1316	#undef PGM_BTH_NAME_R0_STR
1317	#undef PGM_GST_TYPE
1318	#undef PGM_GST_NAME
1319	#undef PGM_GST_NAME_RC_STR
1320	#undef PGM_GST_NAME_R0_STR
1321
1322	#ifdef VBOX_WITH_64_BITS_GUESTS
1323	/* Guest - AMD64 mode */
1324	# define PGM_GST_TYPE PGM_TYPE_AMD64
1325	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1326	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1327	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1328	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_AMD64(name)
1329	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name)
1330	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name)
1331	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1332	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1333	# include "PGMGstDefs.h"
1334	# include "PGMBth.h"
1335	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1336	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1337	# undef PGM_BTH_NAME
1338	# undef PGM_BTH_NAME_RC_STR
1339	# undef PGM_BTH_NAME_R0_STR
1340	# undef PGM_GST_TYPE
1341	# undef PGM_GST_NAME
1342	# undef PGM_GST_NAME_RC_STR
1343	# undef PGM_GST_NAME_R0_STR
1344	#endif /* VBOX_WITH_64_BITS_GUESTS */
1345
1346	#undef PGM_SHW_TYPE
1347	#undef PGM_SHW_NAME
1348	#undef PGM_SHW_NAME_RC_STR
1349	#undef PGM_SHW_NAME_R0_STR
1350
1351
1352	/*
1353	* Shadow - EPT
1354	*/
1355	#define PGM_SHW_TYPE PGM_TYPE_EPT
1356	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1357	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1358	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1359	#include "PGMShw.h"
1360
1361	/* Guest - real mode */
1362	#define PGM_GST_TYPE PGM_TYPE_REAL
1363	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1364	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1365	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1366	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1367	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1368	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1369	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1370	#include "PGMGstDefs.h"
1371	#include "PGMBth.h"
1372	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1373	#undef PGM_BTH_NAME
1374	#undef PGM_BTH_NAME_RC_STR
1375	#undef PGM_BTH_NAME_R0_STR
1376	#undef PGM_GST_TYPE
1377	#undef PGM_GST_NAME
1378	#undef PGM_GST_NAME_RC_STR
1379	#undef PGM_GST_NAME_R0_STR
1380
1381	/* Guest - protected mode */
1382	#define PGM_GST_TYPE PGM_TYPE_PROT
1383	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1384	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1385	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1386	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1387	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1388	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1389	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1390	#include "PGMGstDefs.h"
1391	#include "PGMBth.h"
1392	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1393	#undef PGM_BTH_NAME
1394	#undef PGM_BTH_NAME_RC_STR
1395	#undef PGM_BTH_NAME_R0_STR
1396	#undef PGM_GST_TYPE
1397	#undef PGM_GST_NAME
1398	#undef PGM_GST_NAME_RC_STR
1399	#undef PGM_GST_NAME_R0_STR
1400
1401	/* Guest - 32-bit mode */
1402	#define PGM_GST_TYPE PGM_TYPE_32BIT
1403	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1404	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1405	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1406	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1407	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1408	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1409	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1410	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1411	#include "PGMGstDefs.h"
1412	#include "PGMBth.h"
1413	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1414	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1415	#undef PGM_BTH_NAME
1416	#undef PGM_BTH_NAME_RC_STR
1417	#undef PGM_BTH_NAME_R0_STR
1418	#undef PGM_GST_TYPE
1419	#undef PGM_GST_NAME
1420	#undef PGM_GST_NAME_RC_STR
1421	#undef PGM_GST_NAME_R0_STR
1422
1423	/* Guest - PAE mode */
1424	#define PGM_GST_TYPE PGM_TYPE_PAE
1425	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1426	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1427	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1428	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1429	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1430	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1431	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1432	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1433	#include "PGMGstDefs.h"
1434	#include "PGMBth.h"
1435	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1436	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1437	#undef PGM_BTH_NAME
1438	#undef PGM_BTH_NAME_RC_STR
1439	#undef PGM_BTH_NAME_R0_STR
1440	#undef PGM_GST_TYPE
1441	#undef PGM_GST_NAME
1442	#undef PGM_GST_NAME_RC_STR
1443	#undef PGM_GST_NAME_R0_STR
1444
1445	#ifdef VBOX_WITH_64_BITS_GUESTS
1446	/* Guest - AMD64 mode */
1447	# define PGM_GST_TYPE PGM_TYPE_AMD64
1448	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1449	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1450	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1451	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1452	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1453	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1454	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1455	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1456	# include "PGMGstDefs.h"
1457	# include "PGMBth.h"
1458	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1459	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1460	# undef PGM_BTH_NAME
1461	# undef PGM_BTH_NAME_RC_STR
1462	# undef PGM_BTH_NAME_R0_STR
1463	# undef PGM_GST_TYPE
1464	# undef PGM_GST_NAME
1465	# undef PGM_GST_NAME_RC_STR
1466	# undef PGM_GST_NAME_R0_STR
1467	#endif /* VBOX_WITH_64_BITS_GUESTS */
1468
1469	#undef PGM_SHW_TYPE
1470	#undef PGM_SHW_NAME
1471	#undef PGM_SHW_NAME_RC_STR
1472	#undef PGM_SHW_NAME_R0_STR
1473
1474
1475
1476	/**
1477	* Initiates the paging of VM.
1478	*
1479	* @returns VBox status code.
1480	* @param pVM The cross context VM structure.
1481	*/
1482	VMMR3DECL(int) PGMR3Init(PVM pVM)
1483	{
1484	LogFlow(("PGMR3Init:\n"));
1485	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1486	int rc;
1487
1488	/*
1489	* Assert alignment and sizes.
1490	*/
1491	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1492	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1493	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1494
1495	/*
1496	* Init the structure.
1497	*/
1498	pVM->pgm.s.offVM = RT_UOFFSETOF(VM, pgm.s);
1499	pVM->pgm.s.offVCpuPGM = RT_UOFFSETOF(VMCPU, pgm.s);
1500	/pVM->pgm.s.fRestoreRomPagesAtReset = false;/
1501
1502	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1503	{
1504	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1505	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1506	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1507	}
1508
1509	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1510	{
1511	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1512	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1513	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1514	}
1515
1516	/* Init the per-CPU part. */
1517	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1518	{
1519	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1520	PPGMCPU pPGM = &pVCpu->pgm.s;
1521
1522	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1523	pPGM->offVCpu = RT_UOFFSETOF(VMCPU, pgm.s);
1524	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1525
1526	pPGM->enmShadowMode = PGMMODE_INVALID;
1527	pPGM->enmGuestMode = PGMMODE_INVALID;
1528	pPGM->idxGuestModeData = UINT8_MAX;
1529	pPGM->idxShadowModeData = UINT8_MAX;
1530	pPGM->idxBothModeData = UINT8_MAX;
1531
1532	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1533
1534	pPGM->pGst32BitPdR3 = NULL;
1535	pPGM->pGstPaePdptR3 = NULL;
1536	pPGM->pGstAmd64Pml4R3 = NULL;
1537	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1538	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1539	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1540	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1541	#endif
1542	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1543	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1544	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1545	{
1546	pPGM->apGstPaePDsR3[i] = NULL;
1547	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1548	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1549	#endif
1550	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1551	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1552	pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1553	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1554	}
1555
1556	pPGM->fA20Enabled = true;
1557	pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
1558	}
1559
1560	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1561	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1562	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1563
1564	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1565	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1566	true
1567	#else
1568	false
1569	#endif
1570	);
1571	AssertLogRelRCReturn(rc, rc);
1572
1573	#if HC_ARCH_BITS == 32
1574	# ifdef RT_OS_DARWIN
1575	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1576	# else
1577	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1578	# endif
1579	#else
1580	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1581	#endif
1582	AssertLogRelRCReturn(rc, rc);
1583	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1584	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1585
1586	/*
1587	* Get the configured RAM size - to estimate saved state size.
1588	*/
1589	uint64_t cbRam;
1590	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1591	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1592	cbRam = 0;
1593	else if (RT_SUCCESS(rc))
1594	{
1595	if (cbRam < PAGE_SIZE)
1596	cbRam = 0;
1597	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1598	}
1599	else
1600	{
1601	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1602	return rc;
1603	}
1604
1605	/*
1606	* Check for PCI pass-through and other configurables.
1607	*/
1608	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1609	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1610	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1611
1612	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "PageFusionAllowed", &pVM->pgm.s.fPageFusionAllowed, false);
1613	AssertLogRelRCReturn(rc, rc);
1614
1615	/** @cfgm{/PGM/ZeroRamPagesOnReset, boolean, true}
1616	* Whether to clear RAM pages on (hard) reset. */
1617	rc = CFGMR3QueryBoolDef(pCfgPGM, "ZeroRamPagesOnReset", &pVM->pgm.s.fZeroRamPagesOnReset, true);
1618	AssertLogRelRCReturn(rc, rc);
1619
1620	#ifdef VBOX_WITH_STATISTICS
1621	/*
1622	* Allocate memory for the statistics before someone tries to use them.
1623	*/
1624	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1625	void *pv;
1626	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1627	AssertRCReturn(rc, rc);
1628
1629	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1630	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1631	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1632	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1633
1634	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1635	{
1636	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1637	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1638	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1639
1640	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1641	}
1642	#endif /* VBOX_WITH_STATISTICS */
1643
1644	/*
1645	* Register callbacks, string formatters and the saved state data unit.
1646	*/
1647	#ifdef VBOX_STRICT
1648	VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1649	#endif
1650	PGMRegisterStringFormatTypes();
1651
1652	rc = pgmR3InitSavedState(pVM, cbRam);
1653	if (RT_FAILURE(rc))
1654	return rc;
1655
1656	/*
1657	* Initialize the PGM critical section and flush the phys TLBs
1658	*/
1659	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1660	AssertRCReturn(rc, rc);
1661
1662	PGMR3PhysChunkInvalidateTLB(pVM);
1663	pgmPhysInvalidatePageMapTLB(pVM);
1664
1665	/*
1666	* For the time being we sport a full set of handy pages in addition to the base
1667	* memory to simplify things.
1668	*/
1669	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1670	AssertRCReturn(rc, rc);
1671
1672	/*
1673	* Trees
1674	*/
1675	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1676	if (RT_SUCCESS(rc))
1677	{
1678	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1679	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1680	}
1681
1682	/*
1683	* Allocate the zero page.
1684	*/
1685	if (RT_SUCCESS(rc))
1686	{
1687	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1688	if (RT_SUCCESS(rc))
1689	{
1690	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1691	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1692	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1693	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1694	}
1695	}
1696
1697	/*
1698	* Allocate the invalid MMIO page.
1699	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1700	*/
1701	if (RT_SUCCESS(rc))
1702	{
1703	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1704	if (RT_SUCCESS(rc))
1705	{
1706	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1707	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1708	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1709	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1710	}
1711	}
1712
1713	/*
1714	* Register the physical access handler protecting ROMs.
1715	*/
1716	if (RT_SUCCESS(rc))
1717	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE,
1718	pgmPhysRomWriteHandler,
1719	NULL, NULL, "pgmPhysRomWritePfHandler",
1720	NULL, NULL, "pgmPhysRomWritePfHandler",
1721	"ROM write protection",
1722	&pVM->pgm.s.hRomPhysHandlerType);
1723
1724	/*
1725	* Init the paging.
1726	*/
1727	if (RT_SUCCESS(rc))
1728	rc = pgmR3InitPaging(pVM);
1729
1730	/*
1731	* Init the page pool.
1732	*/
1733	if (RT_SUCCESS(rc))
1734	rc = pgmR3PoolInit(pVM);
1735
1736	if (RT_SUCCESS(rc))
1737	{
1738	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1739	{
1740	PVMCPU pVCpu = &pVM->aCpus[i];
1741	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1742	if (RT_FAILURE(rc))
1743	break;
1744	}
1745	}
1746
1747	if (RT_SUCCESS(rc))
1748	{
1749	/*
1750	* Info & statistics
1751	*/
1752	DBGFR3InfoRegisterInternalEx(pVM, "mode",
1753	"Shows the current paging mode. "
1754	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1755	pgmR3InfoMode,
1756	DBGFINFO_FLAGS_ALL_EMTS);
1757	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1758	"Dumps all the entries in the top level paging table. No arguments.",
1759	pgmR3InfoCr3);
1760	DBGFR3InfoRegisterInternal(pVM, "phys",
1761	"Dumps all the physical address ranges. Pass 'verbose' to get more details.",
1762	pgmR3PhysInfo);
1763	DBGFR3InfoRegisterInternal(pVM, "handlers",
1764	"Dumps physical, virtual and hyper virtual handlers. "
1765	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1766	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1767	pgmR3InfoHandlers);
1768	DBGFR3InfoRegisterInternal(pVM, "mappings",
1769	"Dumps guest mappings.",
1770	pgmR3MapInfo);
1771
1772	pgmR3InitStats(pVM);
1773
1774	#ifdef VBOX_WITH_DEBUGGER
1775	/*
1776	* Debugger commands.
1777	*/
1778	static bool s_fRegisteredCmds = false;
1779	if (!s_fRegisteredCmds)
1780	{
1781	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1782	if (RT_SUCCESS(rc2))
1783	s_fRegisteredCmds = true;
1784	}
1785	#endif
1786	return VINF_SUCCESS;
1787	}
1788
1789	/* Almost no cleanup necessary, MM frees all memory. */
1790	PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1791
1792	return rc;
1793	}
1794
1795
1796	/**
1797	* Init paging.
1798	*
1799	* Since we need to check what mode the host is operating in before we can choose
1800	* the right paging functions for the host we have to delay this until R0 has
1801	* been initialized.
1802	*
1803	* @returns VBox status code.
1804	* @param pVM The cross context VM structure.
1805	*/
1806	static int pgmR3InitPaging(PVM pVM)
1807	{
1808	/*
1809	* Force a recalculation of modes and switcher so everyone gets notified.
1810	*/
1811	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1812	{
1813	PVMCPU pVCpu = &pVM->aCpus[i];
1814
1815	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1816	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1817	pVCpu->pgm.s.idxGuestModeData = UINT8_MAX;
1818	pVCpu->pgm.s.idxShadowModeData = UINT8_MAX;
1819	pVCpu->pgm.s.idxBothModeData = UINT8_MAX;
1820	}
1821
1822	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1823
1824	/*
1825	* Allocate static mapping space for whatever the cr3 register
1826	* points to and in the case of PAE mode to the 4 PDs.
1827	*/
1828	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1829	if (RT_FAILURE(rc))
1830	{
1831	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1832	return rc;
1833	}
1834	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1835
1836	/*
1837	* Allocate pages for the three possible intermediate contexts
1838	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1839	* for the sake of simplicity. The AMD64 uses the PAE for the
1840	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1841	*
1842	* We assume that two page tables will be enought for the core code
1843	* mappings (HC virtual and identity).
1844	*/
1845	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1846	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1847	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1848	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1849	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1850	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1851	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1852	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1853	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1854	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1855	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1856	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1857
1858	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1859	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1860	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1861	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1862	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1863	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1864
1865	/*
1866	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1867	*/
1868	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1869	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1870	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1871
1872	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1873	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1874
1875	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1876	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1877	{
1878	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1879	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1880	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1881	}
1882
1883	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1884	{
1885	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1886	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1887	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1888	}
1889
1890	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1891	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1892	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1893	\| HCPhysInterPaePDPT64;
1894
1895	/*
1896	* Initialize paging workers and mode from current host mode
1897	* and the guest running in real mode.
1898	*/
1899	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1900	switch (pVM->pgm.s.enmHostMode)
1901	{
1902	case SUPPAGINGMODE_32_BIT:
1903	case SUPPAGINGMODE_32_BIT_GLOBAL:
1904	case SUPPAGINGMODE_PAE:
1905	case SUPPAGINGMODE_PAE_GLOBAL:
1906	case SUPPAGINGMODE_PAE_NX:
1907	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1908	break;
1909
1910	case SUPPAGINGMODE_AMD64:
1911	case SUPPAGINGMODE_AMD64_GLOBAL:
1912	case SUPPAGINGMODE_AMD64_NX:
1913	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1914	if (ARCH_BITS != 64)
1915	{
1916	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1917	LogRel(("PGM: Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1918	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1919	}
1920	break;
1921	default:
1922	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1923	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1924	}
1925
1926	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1927	#if HC_ARCH_BITS == 64
1928	LogRel(("PGM: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1929	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1930	LogRel(("PGM: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1931	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1932	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1933	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1934	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1935	#endif
1936
1937	/*
1938	* Log the host paging mode. It may come in handy.
1939	*/
1940	const char *pszHostMode;
1941	switch (pVM->pgm.s.enmHostMode)
1942	{
1943	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1944	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1945	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1946	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1947	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1948	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1949	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1950	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1951	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1952	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1953	default: pszHostMode = "???"; break;
1954	}
1955	LogRel(("PGM: Host paging mode: %s\n", pszHostMode));
1956
1957	return VINF_SUCCESS;
1958	}
1959
1960
1961	/**
1962	* Init statistics
1963	* @returns VBox status code.
1964	*/
1965	static int pgmR3InitStats(PVM pVM)
1966	{
1967	PPGM pPGM = &pVM->pgm.s;
1968	int rc;
1969
1970	/*
1971	* Release statistics.
1972	*/
1973	/* Common - misc variables */
1974	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1975	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1976	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1977	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1978	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1979	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1980	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1981	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1982	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1983	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1984	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1985	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1986	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1987	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1988	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1989	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1990	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1991	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1992	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1993
1994	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1995	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1996	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1997
1998	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1999
2000	/* Live save */
2001	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
2002	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
2003	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
2004	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
2005	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
2006	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
2007	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
2008	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
2009	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
2010	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
2011	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
2012	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
2013	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
2014	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
2015	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
2016	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
2017	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
2018	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
2019
2020	#ifdef VBOX_WITH_STATISTICS
2021
2022	# define PGM_REG_COUNTER(a, b, c) \
2023	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
2024	AssertRC(rc);
2025
2026	# define PGM_REG_COUNTER_BYTES(a, b, c) \
2027	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
2028	AssertRC(rc);
2029
2030	# define PGM_REG_PROFILE(a, b, c) \
2031	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
2032	AssertRC(rc);
2033
2034	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
2035
2036	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
2037	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
2038	PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
2039	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
2040	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
2041
2042	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
2043	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
2044	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
2045	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
2046	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
2047	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
2048	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
2049	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
2050	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
2051	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
2052
2053	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
2054	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
2055	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
2056	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
2057	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
2058	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
2059
2060	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
2061	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
2062	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
2063	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
2064	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
2065	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
2066	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
2067	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
2068
2069	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
2070	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
2071	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
2072	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
2073
2074	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
2075	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
2076	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
2077	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
2078
2079	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
2080	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
2081	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
2082	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
2083	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
2084	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
2085	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
2086	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
2087
2088	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
2089	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
2090	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
2091	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
2092	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
2093	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
2094
2095	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
2096	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
2097	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
2098	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
2099	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
2100	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
2101	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
2102	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
2103
2104	/* GC only: */
2105	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
2106	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
2107
2108	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
2109	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
2110	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
2111	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
2112	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
2113	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
2114	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
2115	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
2116
2117	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
2118	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
2119	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
2120	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
2121	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
2122	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
2123	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
2124
2125	# undef PGM_REG_COUNTER
2126	# undef PGM_REG_PROFILE
2127	#endif
2128
2129	/*
2130	* Note! The layout below matches the member layout exactly!
2131	*/
2132
2133	/*
2134	* Common - stats
2135	*/
2136	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2137	{
2138	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
2139
2140	#define PGM_REG_COUNTER(a, b, c) \
2141	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
2142	AssertRC(rc);
2143	#define PGM_REG_PROFILE(a, b, c) \
2144	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
2145	AssertRC(rc);
2146
2147	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
2148	PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
2149
2150	#ifdef VBOX_WITH_STATISTICS
2151	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
2152
2153	# if 0 /* rarely useful; leave for debugging. */
2154	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
2155	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
2156	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
2157	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
2158	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
2159	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
2160	# endif
2161	/* R0 only: */
2162	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
2163	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
2164
2165	/* RZ only: */
2166	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
2167	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
2168	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
2169	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
2170	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
2171	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
2172	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
2173	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
2174	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
2175	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
2176	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
2177	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
2178	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
2179	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
2180	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
2181	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
2182	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
2183	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
2184	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsHack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USHack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled.");
2185	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsUnhack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USUnhack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled.");
2186	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
2187	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
2188	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
2189	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
2190	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
2191	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
2192	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
2193	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
2194	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
2195	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
2196	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
2197	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
2198	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
2199	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
2200	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
2201	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
2202	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
2203	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
2204	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
2205	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
2206	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
2207	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
2208	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
2209	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
2210	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
2211	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
2212	#if 0 /* rarely useful; leave for debugging. */
2213	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
2214	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
2215	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
2216	#endif
2217	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
2218	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
2219	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
2220	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
2221	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
2222
2223	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
2224	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
2225	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
2226	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
2227	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
2228	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
2229	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
2230	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
2231	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
2232	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
2233	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
2234	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
2235	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
2236	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
2237	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
2238	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
2239	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
2240	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
2241	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
2242	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
2243	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
2244	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
2245	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
2246	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
2247	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
2248	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
2249	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
2250	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
2251	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
2252	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
2253	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
2254	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
2255	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
2256	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
2257	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
2258	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
2259
2260	/* HC only: */
2261
2262	/* RZ & R3: */
2263	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2264	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2265	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
2266	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2267	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2268	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2269	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2270	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2271	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2272	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2273	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
2274	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2275	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
2276	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
2277	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2278	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2279	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2280	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2281	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2282	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2283	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2284	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2285	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
2286	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2287	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2288	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2289	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
2290	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2291	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2292	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2293	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2294	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2295	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2296	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2297	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSizeChanges, "/PGM/CPU%u/RZ/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
2298	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2299	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2300	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2301	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2302	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2303	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2304	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
2305	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2306	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2307	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2308	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2309	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2310	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2311
2312	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2313	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2314	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
2315	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2316	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2317	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2318	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2319	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2320	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2321	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2322	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
2323	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2324	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
2325	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
2326	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2327	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2328	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2329	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2330	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2331	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2332	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2333	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2334	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2335	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2336	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2337	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2338	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2339	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2340	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2341	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2342	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2343	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2344	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2345	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSizeChanges, "/PGM/CPU%u/R3/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
2346	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2347	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2348	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2349	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2350	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2351	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2352	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2353	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2354	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2355	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2356	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2357	#endif /* VBOX_WITH_STATISTICS */
2358
2359	#undef PGM_REG_PROFILE
2360	#undef PGM_REG_COUNTER
2361
2362	}
2363
2364	return VINF_SUCCESS;
2365	}
2366
2367
2368	/**
2369	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2370	*
2371	* The dynamic mapping area will also be allocated and initialized at this
2372	* time. We could allocate it during PGMR3Init of course, but the mapping
2373	* wouldn't be allocated at that time preventing us from setting up the
2374	* page table entries with the dummy page.
2375	*
2376	* @returns VBox status code.
2377	* @param pVM The cross context VM structure.
2378	*/
2379	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2380	{
2381	RTGCPTR GCPtr;
2382	int rc;
2383
2384	/*
2385	* Reserve space for the dynamic mappings.
2386	*/
2387	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2388	if (RT_SUCCESS(rc))
2389	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2390
2391	if ( RT_SUCCESS(rc)
2392	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2393	{
2394	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2395	if (RT_SUCCESS(rc))
2396	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2397	}
2398	if (RT_SUCCESS(rc))
2399	{
2400	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2401	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2402	}
2403	return rc;
2404	}
2405
2406
2407	/**
2408	* Ring-3 init finalizing.
2409	*
2410	* @returns VBox status code.
2411	* @param pVM The cross context VM structure.
2412	*/
2413	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2414	{
2415	int rc = VERR_IPE_UNINITIALIZED_STATUS; /* (MSC incorrectly thinks it can be usused uninitialized) */
2416
2417	/*
2418	* Reserve space for the dynamic mappings.
2419	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2420	*/
2421	/* get the pointer to the page table entries. */
2422	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2423	AssertRelease(pMapping);
2424	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2425	const unsigned iPT = off >> X86_PD_SHIFT;
2426	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2427	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2428	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2429
2430	/* init cache area */
2431	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2432	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2433	{
2434	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2435	AssertRCReturn(rc, rc);
2436	}
2437
2438	/*
2439	* Determine the max physical address width (MAXPHYADDR) and apply it to
2440	* all the mask members and stuff.
2441	*/
2442	uint32_t cMaxPhysAddrWidth;
2443	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2444	if ( uMaxExtLeaf >= 0x80000008
2445	&& uMaxExtLeaf <= 0x80000fff)
2446	{
2447	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2448	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2449	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2450	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2451	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2452	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2453	}
2454	else
2455	{
2456	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2457	cMaxPhysAddrWidth = 48;
2458	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2459	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2460	}
2461
2462	/** @todo query from CPUM. */
2463	pVM->pgm.s.GCPhysInvAddrMask = 0;
2464	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2465	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2466
2467	/*
2468	* Initialize the invalid paging entry masks, assuming NX is disabled.
2469	*/
2470	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2471	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2472	{
2473	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2474
2475	/** @todo The manuals are not entirely clear whether the physical
2476	* address width is relevant. See table 5-9 in the intel
2477	* manual vs the PDE4M descriptions. Write testcase (NP). */
2478	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2479	\| X86_PDE4M_MBZ_MASK;
2480
2481	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2482	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2483	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2484	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2485
2486	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2487	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2488	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2489	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2490	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2491	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2492
2493	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
2494	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
2495	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
2496	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2497	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
2498	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
2499	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
2500	}
2501
2502	/*
2503	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2504	* Intel only goes up to 36 bits, so we stick to 36 as well.
2505	* Update: More recent intel manuals specifies 40 bits just like AMD.
2506	*/
2507	uint32_t u32Dummy, u32Features;
2508	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2509	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2510	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2511	else
2512	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2513
2514	/*
2515	* Allocate memory if we're supposed to do that.
2516	*/
2517	if (pVM->pgm.s.fRamPreAlloc)
2518	rc = pgmR3PhysRamPreAllocate(pVM);
2519
2520	//pgmLogState(pVM);
2521	LogRel(("PGM: PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2522	return rc;
2523	}
2524
2525
2526	/**
2527	* Init phase completed callback.
2528	*
2529	* @returns VBox status code.
2530	* @param pVM The cross context VM structure.
2531	* @param enmWhat What has been completed.
2532	* @thread EMT(0)
2533	*/
2534	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2535	{
2536	switch (enmWhat)
2537	{
2538	case VMINITCOMPLETED_HM:
2539	#ifdef VBOX_WITH_PCI_PASSTHROUGH
2540	if (pVM->pgm.s.fPciPassthrough)
2541	{
2542	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2543	AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
2544	AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2545
2546	/*
2547	* Report assignments to the IOMMU (hope that's good enough for now).
2548	*/
2549	if (pVM->pgm.s.fPciPassthrough)
2550	{
2551	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2552	AssertRCReturn(rc, rc);
2553	}
2554	}
2555	#else
2556	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2557	#endif
2558	break;
2559
2560	default:
2561	/* shut up gcc */
2562	break;
2563	}
2564
2565	return VINF_SUCCESS;
2566	}
2567
2568
2569	/**
2570	* Applies relocations to data and code managed by this component.
2571	*
2572	* This function will be called at init and whenever the VMM need to relocate it
2573	* self inside the GC.
2574	*
2575	* @param pVM The cross context VM structure.
2576	* @param offDelta Relocation delta relative to old location.
2577	*/
2578	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2579	{
2580	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2581
2582	/*
2583	* Paging stuff.
2584	*/
2585	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2586
2587	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2588	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2589	{
2590	PVMCPU pVCpu = &pVM->aCpus[i];
2591
2592	pgmR3ModeDataSwitch(pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2593
2594	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
2595	if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
2596	&& g_aPgmShadowModeData[idxShw].pfnRelocate)
2597	g_aPgmShadowModeData[idxShw].pfnRelocate(pVCpu, offDelta);
2598
2599	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
2600	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
2601	&& g_aPgmGuestModeData[idxGst].pfnRelocate)
2602	g_aPgmGuestModeData[idxGst].pfnRelocate(pVCpu, offDelta);
2603
2604	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
2605	if ( idxBth < RT_ELEMENTS(g_aPgmBothModeData)
2606	&& g_aPgmBothModeData[idxBth].pfnRelocate)
2607	g_aPgmBothModeData[idxBth].pfnRelocate(pVCpu, offDelta);
2608	}
2609
2610	/*
2611	* Trees.
2612	*/
2613	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2614
2615	/*
2616	* Ram ranges.
2617	*/
2618	if (pVM->pgm.s.pRamRangesXR3)
2619	{
2620	/* Update the pSelfRC pointers and relink them. */
2621	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2622	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2623	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2624	pgmR3PhysRelinkRamRanges(pVM);
2625
2626	/* Flush the RC TLB. */
2627	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2628	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2629	}
2630
2631	/*
2632	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2633	* be mapped and thus not included in the above exercise.
2634	*/
2635	for (PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2636	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2637	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2638
2639	/*
2640	* Update the two page directories with all page table mappings.
2641	* (One or more of them have changed, that's why we're here.)
2642	*/
2643	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2644	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2645	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2646
2647	/* Relocate GC addresses of Page Tables. */
2648	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2649	{
2650	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2651	{
2652	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2653	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2654	}
2655	}
2656
2657	/*
2658	* Dynamic page mapping area.
2659	*/
2660	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2661	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2662	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2663
2664	if (pVM->pgm.s.pRCDynMap)
2665	{
2666	pVM->pgm.s.pRCDynMap += offDelta;
2667	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2668
2669	pDynMap->paPages += offDelta;
2670	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2671
2672	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2673	{
2674	paPages[iPage].pvPage += offDelta;
2675	paPages[iPage].uPte.pLegacy += offDelta;
2676	paPages[iPage].uPte.pPae += offDelta;
2677	}
2678	}
2679
2680	/*
2681	* The Zero page.
2682	*/
2683	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2684	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2685	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| VM_IS_RAW_MODE_ENABLED(pVM));
2686	#else
2687	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2688	#endif
2689
2690	/*
2691	* Physical and virtual handlers.
2692	*/
2693	PGMRELOCHANDLERARGS Args = { offDelta, pVM };
2694	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &Args);
2695	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2696
2697	PPGMPHYSHANDLERTYPEINT pCurPhysType;
2698	RTListOff32ForEach(&pVM->pgm.s.pTreesR3->HeadPhysHandlerTypes, pCurPhysType, PGMPHYSHANDLERTYPEINT, ListNode)
2699	{
2700	if (pCurPhysType->pfnHandlerRC != NIL_RTRCPTR)
2701	pCurPhysType->pfnHandlerRC += offDelta;
2702	if (pCurPhysType->pfnPfHandlerRC != NIL_RTRCPTR)
2703	pCurPhysType->pfnPfHandlerRC += offDelta;
2704	}
2705
2706	#ifdef VBOX_WITH_RAW_MODE
2707	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &Args);
2708	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &Args);
2709
2710	PPGMVIRTHANDLERTYPEINT pCurVirtType;
2711	RTListOff32ForEach(&pVM->pgm.s.pTreesR3->HeadVirtHandlerTypes, pCurVirtType, PGMVIRTHANDLERTYPEINT, ListNode)
2712	{
2713	if (pCurVirtType->pfnHandlerRC != NIL_RTRCPTR)
2714	pCurVirtType->pfnHandlerRC += offDelta;
2715	if (pCurVirtType->pfnPfHandlerRC != NIL_RTRCPTR)
2716	pCurVirtType->pfnPfHandlerRC += offDelta;
2717	}
2718	#endif
2719
2720	/*
2721	* The page pool.
2722	*/
2723	pgmR3PoolRelocate(pVM);
2724
2725	#ifdef VBOX_WITH_STATISTICS
2726	/*
2727	* Statistics.
2728	*/
2729	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2730	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2731	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2732	#endif
2733	}
2734
2735
2736	/**
2737	* Callback function for relocating a physical access handler.
2738	*
2739	* @returns 0 (continue enum)
2740	* @param pNode Pointer to a PGMPHYSHANDLER node.
2741	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2742	*/
2743	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2744	{
2745	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2746	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2747	if (pHandler->pvUserRC >= 0x10000)
2748	pHandler->pvUserRC += pArgs->offDelta;
2749	return 0;
2750	}
2751
2752	#ifdef VBOX_WITH_RAW_MODE
2753
2754	/**
2755	* Callback function for relocating a virtual access handler.
2756	*
2757	* @returns 0 (continue enum)
2758	* @param pNode Pointer to a PGMVIRTHANDLER node.
2759	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2760	*/
2761	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2762	{
2763	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2764	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2765	Assert(PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->enmKind != PGMVIRTHANDLERKIND_HYPERVISOR);
2766
2767	if ( pHandler->pvUserRC != NIL_RTRCPTR
2768	&& PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->fRelocUserRC)
2769	pHandler->pvUserRC += pArgs->offDelta;
2770	return 0;
2771	}
2772
2773
2774	/**
2775	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2776	*
2777	* @returns 0 (continue enum)
2778	* @param pNode Pointer to a PGMVIRTHANDLER node.
2779	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2780	*/
2781	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2782	{
2783	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2784	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2785	Assert(PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->enmKind == PGMVIRTHANDLERKIND_HYPERVISOR);
2786
2787	if ( pHandler->pvUserRC != NIL_RTRCPTR
2788	&& PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->fRelocUserRC)
2789	pHandler->pvUserRC += pArgs->offDelta;
2790	return 0;
2791	}
2792
2793	#endif /* VBOX_WITH_RAW_MODE */
2794
2795	/**
2796	* Resets a virtual CPU when unplugged.
2797	*
2798	* @param pVM The cross context VM structure.
2799	* @param pVCpu The cross context virtual CPU structure.
2800	*/
2801	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2802	{
2803	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
2804	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
2805	&& g_aPgmGuestModeData[idxGst].pfnExit)
2806	{
2807	int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
2808	AssertReleaseRC(rc);
2809	}
2810	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2811
2812	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2813	AssertReleaseRC(rc);
2814
2815	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2816
2817	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2818
2819	/*
2820	* Re-init other members.
2821	*/
2822	pVCpu->pgm.s.fA20Enabled = true;
2823	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2824
2825	/*
2826	* Clear the FFs PGM owns.
2827	*/
2828	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2829	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2830	}
2831
2832
2833	/**
2834	* The VM is being reset.
2835	*
2836	* For the PGM component this means that any PD write monitors
2837	* needs to be removed.
2838	*
2839	* @param pVM The cross context VM structure.
2840	*/
2841	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
2842	{
2843	LogFlow(("PGMR3Reset:\n"));
2844	VM_ASSERT_EMT(pVM);
2845
2846	pgmLock(pVM);
2847
2848	/*
2849	* Unfix any fixed mappings and disable CR3 monitoring.
2850	*/
2851	pVM->pgm.s.fMappingsFixed = false;
2852	pVM->pgm.s.fMappingsFixedRestored = false;
2853	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2854	pVM->pgm.s.cbMappingFixed = 0;
2855
2856	/*
2857	* Exit the guest paging mode before the pgm pool gets reset.
2858	* Important to clean up the amd64 case.
2859	*/
2860	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2861	{
2862	PVMCPU pVCpu = &pVM->aCpus[i];
2863	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
2864	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
2865	&& g_aPgmGuestModeData[idxGst].pfnExit)
2866	{
2867	int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
2868	AssertReleaseRC(rc);
2869	}
2870	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2871	}
2872
2873	#ifdef DEBUG
2874	DBGFR3_INFO_LOG_SAFE(pVM, "mappings", NULL);
2875	DBGFR3_INFO_LOG_SAFE(pVM, "handlers", "all nostat");
2876	#endif
2877
2878	/*
2879	* Switch mode back to real mode. (Before resetting the pgm pool!)
2880	*/
2881	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2882	{
2883	PVMCPU pVCpu = &pVM->aCpus[i];
2884
2885	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2886	AssertReleaseRC(rc);
2887
2888	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2889	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2890	}
2891
2892	/*
2893	* Reset the shadow page pool.
2894	*/
2895	pgmR3PoolReset(pVM);
2896
2897	/*
2898	* Re-init various other members and clear the FFs that PGM owns.
2899	*/
2900	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2901	{
2902	PVMCPU pVCpu = &pVM->aCpus[i];
2903
2904	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2905	PGMNotifyNxeChanged(pVCpu, false);
2906
2907	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2908	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2909
2910	if (!pVCpu->pgm.s.fA20Enabled)
2911	{
2912	pVCpu->pgm.s.fA20Enabled = true;
2913	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2914	#ifdef PGM_WITH_A20
2915	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2916	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2917	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
2918	HMFlushTLB(pVCpu);
2919	#endif
2920	}
2921	}
2922
2923	//pgmLogState(pVM);
2924	pgmUnlock(pVM);
2925	}
2926
2927
2928	/**
2929	* Memory setup after VM construction or reset.
2930	*
2931	* @param pVM The cross context VM structure.
2932	* @param fAtReset Indicates the context, after reset if @c true or after
2933	* construction if @c false.
2934	*/
2935	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
2936	{
2937	if (fAtReset)
2938	{
2939	pgmLock(pVM);
2940
2941	int rc = pgmR3PhysRamZeroAll(pVM);
2942	AssertReleaseRC(rc);
2943
2944	rc = pgmR3PhysRomReset(pVM);
2945	AssertReleaseRC(rc);
2946
2947	pgmUnlock(pVM);
2948	}
2949	}
2950
2951
2952	#ifdef VBOX_STRICT
2953	/**
2954	* VM state change callback for clearing fNoMorePhysWrites after
2955	* a snapshot has been created.
2956	*/
2957	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2958	{
2959	if ( enmState == VMSTATE_RUNNING
2960	\|\| enmState == VMSTATE_RESUMING)
2961	pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2962	NOREF(enmOldState); NOREF(pvUser);
2963	}
2964	#endif
2965
2966	/**
2967	* Private API to reset fNoMorePhysWrites.
2968	*/
2969	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2970	{
2971	pVM->pgm.s.fNoMorePhysWrites = false;
2972	}
2973
2974	/**
2975	* Terminates the PGM.
2976	*
2977	* @returns VBox status code.
2978	* @param pVM The cross context VM structure.
2979	*/
2980	VMMR3DECL(int) PGMR3Term(PVM pVM)
2981	{
2982	/* Must free shared pages here. */
2983	pgmLock(pVM);
2984	pgmR3PhysRamTerm(pVM);
2985	pgmR3PhysRomTerm(pVM);
2986	pgmUnlock(pVM);
2987
2988	PGMDeregisterStringFormatTypes();
2989	return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2990	}
2991
2992
2993	/**
2994	* Show paging mode.
2995	*
2996	* @param pVM The cross context VM structure.
2997	* @param pHlp The info helpers.
2998	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2999	*/
3000	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3001	{
3002	/* digest argument. */
3003	bool fGuest, fShadow, fHost;
3004	if (pszArgs)
3005	pszArgs = RTStrStripL(pszArgs);
3006	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3007	fShadow = fHost = fGuest = true;
3008	else
3009	{
3010	fShadow = fHost = fGuest = false;
3011	if (strstr(pszArgs, "guest"))
3012	fGuest = true;
3013	if (strstr(pszArgs, "shadow"))
3014	fShadow = true;
3015	if (strstr(pszArgs, "host"))
3016	fHost = true;
3017	}
3018
3019	PVMCPU pVCpu = VMMGetCpu(pVM);
3020	if (!pVCpu)
3021	pVCpu = &pVM->aCpus[0];
3022
3023
3024	/* print info. */
3025	if (fGuest)
3026	pHlp->pfnPrintf(pHlp, "Guest paging mode (VCPU #%u): %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
3027	pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmGuestMode), pVCpu->pgm.s.cGuestModeChanges.c,
3028	pVCpu->pgm.s.fA20Enabled ? "enabled" : "disabled", pVCpu->pgm.s.cA20Changes.c);
3029	if (fShadow)
3030	pHlp->pfnPrintf(pHlp, "Shadow paging mode (VCPU #%u): %s\n", pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmShadowMode));
3031	if (fHost)
3032	{
3033	const char *psz;
3034	switch (pVM->pgm.s.enmHostMode)
3035	{
3036	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3037	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3038	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3039	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3040	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3041	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3042	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3043	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3044	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3045	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3046	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3047	default: psz = "unknown"; break;
3048	}
3049	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3050	}
3051	}
3052
3053
3054	/**
3055	* Dump registered MMIO ranges to the log.
3056	*
3057	* @param pVM The cross context VM structure.
3058	* @param pHlp The info helpers.
3059	* @param pszArgs Arguments, ignored.
3060	*/
3061	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3062	{
3063	bool const fVerbose = pszArgs && strstr(pszArgs, "verbose") != NULL;
3064
3065	pHlp->pfnPrintf(pHlp,
3066	"RAM ranges (pVM=%p)\n"
3067	"%.s %.s\n",
3068	pVM,
3069	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3070	sizeof(RTHCPTR) * 2, "pvHC ");
3071
3072	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
3073	{
3074	pHlp->pfnPrintf(pHlp,
3075	"%RGp-%RGp %RHv %s\n",
3076	pCur->GCPhys,
3077	pCur->GCPhysLast,
3078	pCur->pvR3,
3079	pCur->pszDesc);
3080	if (fVerbose)
3081	{
3082	RTGCPHYS const cPages = pCur->cb >> X86_PAGE_SHIFT;
3083	RTGCPHYS iPage = 0;
3084	while (iPage < cPages)
3085	{
3086	RTGCPHYS const iFirstPage = iPage;
3087	PGMPAGETYPE const enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]);
3088	do
3089	iPage++;
3090	while (iPage < cPages && (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == enmType);
3091	const char *pszType;
3092	const char *pszMore = NULL;
3093	switch (enmType)
3094	{
3095	case PGMPAGETYPE_RAM:
3096	pszType = "RAM";
3097	break;
3098
3099	case PGMPAGETYPE_MMIO2:
3100	pszType = "MMIO2";
3101	break;
3102
3103	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3104	pszType = "MMIO2-alias-MMIO";
3105	break;
3106
3107	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
3108	pszType = "special-alias-MMIO";
3109	break;
3110
3111	case PGMPAGETYPE_ROM_SHADOW:
3112	case PGMPAGETYPE_ROM:
3113	{
3114	pszType = enmType == PGMPAGETYPE_ROM_SHADOW ? "ROM-shadowed" : "ROM";
3115
3116	RTGCPHYS const GCPhysFirstPg = iFirstPage * X86_PAGE_SIZE;
3117	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
3118	while (pRom && GCPhysFirstPg > pRom->GCPhysLast)
3119	pRom = pRom->pNextR3;
3120	if (pRom && GCPhysFirstPg - pRom->GCPhys < pRom->cb)
3121	pszMore = pRom->pszDesc;
3122	break;
3123	}
3124
3125	case PGMPAGETYPE_MMIO:
3126	{
3127	pszType = "MMIO";
3128	pgmLock(pVM);
3129	PPGMPHYSHANDLER pHandler = pgmHandlerPhysicalLookup(pVM, iFirstPage * X86_PAGE_SIZE);
3130	if (pHandler)
3131	pszMore = pHandler->pszDesc;
3132	pgmUnlock(pVM);
3133	break;
3134	}
3135
3136	case PGMPAGETYPE_INVALID:
3137	pszType = "invalid";
3138	break;
3139
3140	default:
3141	pszType = "bad";
3142	break;
3143	}
3144	if (pszMore)
3145	pHlp->pfnPrintf(pHlp, " %RGp-%RGp %-20s %s\n",
3146	pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
3147	pCur->GCPhys + iPage * X86_PAGE_SIZE,
3148	pszType, pszMore);
3149	else
3150	pHlp->pfnPrintf(pHlp, " %RGp-%RGp %s\n",
3151	pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
3152	pCur->GCPhys + iPage * X86_PAGE_SIZE,
3153	pszType);
3154
3155	}
3156	}
3157	}
3158	}
3159
3160
3161	/**
3162	* Dump the page directory to the log.
3163	*
3164	* @param pVM The cross context VM structure.
3165	* @param pHlp The info helpers.
3166	* @param pszArgs Arguments, ignored.
3167	*/
3168	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3169	{
3170	/** @todo SMP support!! */
3171	PVMCPU pVCpu = &pVM->aCpus[0];
3172
3173	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3174	/* Big pages supported? */
3175	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3176
3177	/* Global pages supported? */
3178	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3179
3180	NOREF(pszArgs);
3181
3182	/*
3183	* Get page directory addresses.
3184	*/
3185	pgmLock(pVM);
3186	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3187	Assert(pPDSrc);
3188
3189	/*
3190	* Iterate the page directory.
3191	*/
3192	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3193	{
3194	X86PDE PdeSrc = pPDSrc->a[iPD];
3195	if (PdeSrc.n.u1Present)
3196	{
3197	if (PdeSrc.b.u1Size && fPSE)
3198	pHlp->pfnPrintf(pHlp,
3199	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3200	iPD,
3201	pgmGstGet4MBPhysPage(pVM, PdeSrc),
3202	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3203	else
3204	pHlp->pfnPrintf(pHlp,
3205	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3206	iPD,
3207	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3208	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3209	}
3210	}
3211	pgmUnlock(pVM);
3212	}
3213
3214
3215	/**
3216	* Service a VMMCALLRING3_PGM_LOCK call.
3217	*
3218	* @returns VBox status code.
3219	* @param pVM The cross context VM structure.
3220	*/
3221	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3222	{
3223	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
3224	AssertRC(rc);
3225	return rc;
3226	}
3227
3228
3229	/**
3230	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3231	*
3232	* @returns PGM_TYPE_*.
3233	* @param pgmMode The mode value to convert.
3234	*/
3235	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3236	{
3237	switch (pgmMode)
3238	{
3239	case PGMMODE_REAL: return PGM_TYPE_REAL;
3240	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3241	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3242	case PGMMODE_PAE:
3243	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3244	case PGMMODE_AMD64:
3245	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3246	case PGMMODE_NESTED_32BIT: return PGM_TYPE_NESTED_32BIT;
3247	case PGMMODE_NESTED_PAE: return PGM_TYPE_NESTED_PAE;
3248	case PGMMODE_NESTED_AMD64: return PGM_TYPE_NESTED_AMD64;
3249	case PGMMODE_EPT: return PGM_TYPE_EPT;
3250	default:
3251	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3252	}
3253	}
3254
3255
3256	/**
3257	* Gets the index into the paging mode data array of a SHW+GST mode.
3258	*
3259	* @returns PGM::paPagingData index.
3260	* @param uShwType The shadow paging mode type.
3261	* @param uGstType The guest paging mode type.
3262	*/
3263	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3264	{
3265	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3266	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3267	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3268	+ (uGstType - PGM_TYPE_REAL);
3269	}
3270
3271
3272	/**
3273	* Gets the index into the paging mode data array of a SHW+GST mode.
3274	*
3275	* @returns PGM::paPagingData index.
3276	* @param enmShw The shadow paging mode.
3277	* @param enmGst The guest paging mode.
3278	*/
3279	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3280	{
3281	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3282	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3283	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3284	}
3285
3286
3287	/**
3288	* Calculates the max data index.
3289	* @returns The number of entries in the paging data array.
3290	*/
3291	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3292	{
3293	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3294	}
3295
3296
3297	/**
3298	* Switch to different (or relocated in the relocate case) mode data.
3299	*
3300	* @param pVCpu The cross context virtual CPU structure.
3301	* @param enmShw The shadow paging mode.
3302	* @param enmGst The guest paging mode.
3303	*/
3304	static void pgmR3ModeDataSwitch(PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3305	{
3306	/*
3307	* Update the indexes.
3308	*/
3309	uintptr_t idxGst = pVCpu->pgm.s.idxGuestModeData = pgmModeToType(enmGst);
3310	Assert(g_aPgmGuestModeData[idxGst].uType == idxGst);
3311	AssertPtr(g_aPgmGuestModeData[idxGst].pfnGetPage);
3312	AssertPtr(g_aPgmGuestModeData[idxGst].pfnModifyPage);
3313	AssertPtr(g_aPgmGuestModeData[idxGst].pfnGetPDE);
3314	AssertPtr(g_aPgmGuestModeData[idxGst].pfnExit);
3315	AssertPtr(g_aPgmGuestModeData[idxGst].pfnEnter);
3316	AssertPtr(g_aPgmGuestModeData[idxGst].pfnRelocate);
3317	NOREF(idxGst);
3318
3319	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData = pgmModeToType(enmShw);
3320	Assert(g_aPgmShadowModeData[idxShw].uType == idxShw);
3321	AssertPtr(g_aPgmShadowModeData[idxShw].pfnGetPage);
3322	AssertPtr(g_aPgmShadowModeData[idxShw].pfnModifyPage);
3323	AssertPtr(g_aPgmShadowModeData[idxShw].pfnExit);
3324	AssertPtr(g_aPgmShadowModeData[idxShw].pfnEnter);
3325	AssertPtr(g_aPgmShadowModeData[idxShw].pfnRelocate);
3326	NOREF(idxShw);
3327
3328	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData = (idxShw - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END + idxGst;
3329	Assert(g_aPgmBothModeData[idxBth].uShwType == idxShw);
3330	Assert(g_aPgmBothModeData[idxBth].uGstType == idxGst);
3331	AssertPtr(g_aPgmBothModeData[idxBth].pfnInvalidatePage);
3332	AssertPtr(g_aPgmBothModeData[idxBth].pfnSyncCR3);
3333	AssertPtr(g_aPgmBothModeData[idxBth].pfnPrefetchPage);
3334	AssertPtr(g_aPgmBothModeData[idxBth].pfnVerifyAccessSyncPage);
3335	AssertPtr(g_aPgmBothModeData[idxBth].pfnMapCR3);
3336	AssertPtr(g_aPgmBothModeData[idxBth].pfnUnmapCR3);
3337	AssertPtr(g_aPgmBothModeData[idxBth].pfnEnter);
3338	AssertPtr(g_aPgmBothModeData[idxBth].pfnRelocate);
3339	#ifdef VBOX_STRICT
3340	AssertPtr(g_aPgmBothModeData[idxBth].pfnAssertCR3);
3341	#endif
3342	NOREF(idxBth);
3343	}
3344
3345
3346	/**
3347	* Calculates the shadow paging mode.
3348	*
3349	* @returns The shadow paging mode.
3350	* @param pVM The cross context VM structure.
3351	* @param enmGuestMode The guest mode.
3352	* @param enmHostMode The host mode.
3353	* @param enmShadowMode The current shadow mode.
3354	* @param penmSwitcher Where to store the switcher to use.
3355	* VMMSWITCHER_INVALID means no change.
3356	*/
3357	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3358	{
3359	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3360	switch (enmGuestMode)
3361	{
3362	/*
3363	* When switching to real or protected mode we don't change
3364	* anything since it's likely that we'll switch back pretty soon.
3365	*
3366	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3367	* and is supposed to determine which shadow paging and switcher to
3368	* use during init.
3369	*/
3370	case PGMMODE_REAL:
3371	case PGMMODE_PROTECTED:
3372	if ( enmShadowMode != PGMMODE_INVALID
3373	&& VM_IS_RAW_MODE_ENABLED(pVM) /* always switch in hm and nem modes! */)
3374	break; /* (no change) */
3375
3376	switch (enmHostMode)
3377	{
3378	case SUPPAGINGMODE_32_BIT:
3379	case SUPPAGINGMODE_32_BIT_GLOBAL:
3380	enmShadowMode = PGMMODE_32_BIT;
3381	enmSwitcher = VMMSWITCHER_32_TO_32;
3382	break;
3383
3384	case SUPPAGINGMODE_PAE:
3385	case SUPPAGINGMODE_PAE_NX:
3386	case SUPPAGINGMODE_PAE_GLOBAL:
3387	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3388	enmShadowMode = PGMMODE_PAE;
3389	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3390	#ifdef DEBUG_bird
3391	if (RTEnvExist("VBOX_32BIT"))
3392	{
3393	enmShadowMode = PGMMODE_32_BIT;
3394	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3395	}
3396	#endif
3397	break;
3398
3399	case SUPPAGINGMODE_AMD64:
3400	case SUPPAGINGMODE_AMD64_GLOBAL:
3401	case SUPPAGINGMODE_AMD64_NX:
3402	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3403	enmShadowMode = PGMMODE_PAE;
3404	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3405	#ifdef DEBUG_bird
3406	if (RTEnvExist("VBOX_32BIT"))
3407	{
3408	enmShadowMode = PGMMODE_32_BIT;
3409	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3410	}
3411	#endif
3412	break;
3413
3414	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3415	}
3416	break;
3417
3418	case PGMMODE_32_BIT:
3419	switch (enmHostMode)
3420	{
3421	case SUPPAGINGMODE_32_BIT:
3422	case SUPPAGINGMODE_32_BIT_GLOBAL:
3423	enmShadowMode = PGMMODE_32_BIT;
3424	enmSwitcher = VMMSWITCHER_32_TO_32;
3425	break;
3426
3427	case SUPPAGINGMODE_PAE:
3428	case SUPPAGINGMODE_PAE_NX:
3429	case SUPPAGINGMODE_PAE_GLOBAL:
3430	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3431	enmShadowMode = PGMMODE_PAE;
3432	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3433	#ifdef DEBUG_bird
3434	if (RTEnvExist("VBOX_32BIT"))
3435	{
3436	enmShadowMode = PGMMODE_32_BIT;
3437	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3438	}
3439	#endif
3440	break;
3441
3442	case SUPPAGINGMODE_AMD64:
3443	case SUPPAGINGMODE_AMD64_GLOBAL:
3444	case SUPPAGINGMODE_AMD64_NX:
3445	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3446	enmShadowMode = PGMMODE_PAE;
3447	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3448	#ifdef DEBUG_bird
3449	if (RTEnvExist("VBOX_32BIT"))
3450	{
3451	enmShadowMode = PGMMODE_32_BIT;
3452	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3453	}
3454	#endif
3455	break;
3456
3457	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3458	}
3459	break;
3460
3461	case PGMMODE_PAE:
3462	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3463	switch (enmHostMode)
3464	{
3465	case SUPPAGINGMODE_32_BIT:
3466	case SUPPAGINGMODE_32_BIT_GLOBAL:
3467	enmShadowMode = PGMMODE_PAE;
3468	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3469	break;
3470
3471	case SUPPAGINGMODE_PAE:
3472	case SUPPAGINGMODE_PAE_NX:
3473	case SUPPAGINGMODE_PAE_GLOBAL:
3474	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3475	enmShadowMode = PGMMODE_PAE;
3476	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3477	break;
3478
3479	case SUPPAGINGMODE_AMD64:
3480	case SUPPAGINGMODE_AMD64_GLOBAL:
3481	case SUPPAGINGMODE_AMD64_NX:
3482	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3483	enmShadowMode = PGMMODE_PAE;
3484	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3485	break;
3486
3487	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3488	}
3489	break;
3490
3491	case PGMMODE_AMD64:
3492	case PGMMODE_AMD64_NX:
3493	switch (enmHostMode)
3494	{
3495	case SUPPAGINGMODE_32_BIT:
3496	case SUPPAGINGMODE_32_BIT_GLOBAL:
3497	enmShadowMode = PGMMODE_AMD64;
3498	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3499	break;
3500
3501	case SUPPAGINGMODE_PAE:
3502	case SUPPAGINGMODE_PAE_NX:
3503	case SUPPAGINGMODE_PAE_GLOBAL:
3504	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3505	enmShadowMode = PGMMODE_AMD64;
3506	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3507	break;
3508
3509	case SUPPAGINGMODE_AMD64:
3510	case SUPPAGINGMODE_AMD64_GLOBAL:
3511	case SUPPAGINGMODE_AMD64_NX:
3512	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3513	enmShadowMode = PGMMODE_AMD64;
3514	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3515	break;
3516
3517	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3518	}
3519	break;
3520
3521
3522	default:
3523	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3524	*penmSwitcher = VMMSWITCHER_INVALID;
3525	return PGMMODE_INVALID;
3526	}
3527
3528	/*
3529	* Override the shadow mode when NEM or nested paging is active.
3530	*/
3531	if (VM_IS_NEM_ENABLED(pVM))
3532	{
3533	pVM->pgm.s.fNestedPaging = true;
3534	enmShadowMode = PGMMODE_EPT; /* whatever harmless... */
3535	}
3536	else
3537	{
3538	bool fNestedPaging = HMIsNestedPagingActive(pVM);
3539	pVM->pgm.s.fNestedPaging = fNestedPaging;
3540	if (fNestedPaging)
3541	{
3542	if (HMIsVmxActive(pVM))
3543	enmShadowMode = PGMMODE_EPT;
3544	else
3545	{
3546	/* The nested SVM paging depends on the host one. */
3547	Assert(HMIsSvmActive(pVM));
3548	if ( enmGuestMode == PGMMODE_AMD64
3549	\|\| enmGuestMode == PGMMODE_AMD64_NX)
3550	enmShadowMode = PGMMODE_NESTED_AMD64;
3551	else
3552	switch (pVM->pgm.s.enmHostMode)
3553	{
3554	case SUPPAGINGMODE_32_BIT:
3555	case SUPPAGINGMODE_32_BIT_GLOBAL:
3556	enmShadowMode = PGMMODE_NESTED_32BIT;
3557	break;
3558
3559	case SUPPAGINGMODE_PAE:
3560	case SUPPAGINGMODE_PAE_GLOBAL:
3561	case SUPPAGINGMODE_PAE_NX:
3562	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3563	enmShadowMode = PGMMODE_NESTED_PAE;
3564	break;
3565
3566	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3567	case SUPPAGINGMODE_AMD64:
3568	case SUPPAGINGMODE_AMD64_GLOBAL:
3569	case SUPPAGINGMODE_AMD64_NX:
3570	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3571	enmShadowMode = PGMMODE_NESTED_AMD64;
3572	break;
3573	#endif
3574	default:
3575	AssertLogRelFailedReturn(PGMMODE_INVALID);
3576	}
3577	}
3578	}
3579	}
3580
3581	*penmSwitcher = enmSwitcher;
3582	return enmShadowMode;
3583	}
3584
3585
3586	/**
3587	* Performs the actual mode change.
3588	* This is called by PGMChangeMode and pgmR3InitPaging().
3589	*
3590	* @returns VBox status code. May suspend or power off the VM on error, but this
3591	* will trigger using FFs and not status codes.
3592	*
3593	* @param pVM The cross context VM structure.
3594	* @param pVCpu The cross context virtual CPU structure.
3595	* @param enmGuestMode The new guest mode. This is assumed to be different from
3596	* the current mode.
3597	*/
3598	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3599	{
3600	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3601	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3602
3603	/*
3604	* Calc the shadow mode and switcher.
3605	*/
3606	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3607	PGMMODE enmShadowMode = PGMMODE_INVALID;
3608	enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3609
3610	#ifdef VBOX_WITH_RAW_MODE
3611	if ( enmSwitcher != VMMSWITCHER_INVALID
3612	&& VM_IS_RAW_MODE_ENABLED(pVM))
3613	{
3614	/*
3615	* Select new switcher.
3616	*/
3617	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3618	if (RT_FAILURE(rc))
3619	{
3620	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3621	return rc;
3622	}
3623	}
3624	#endif
3625
3626	/*
3627	* Exit old mode(s).
3628	*/
3629	/* shadow */
3630	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3631	{
3632	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3633	uintptr_t idxOldShw = pVCpu->pgm.s.idxShadowModeData;
3634	if ( idxOldShw < RT_ELEMENTS(g_aPgmShadowModeData)
3635	&& g_aPgmShadowModeData[idxOldShw].pfnExit)
3636	{
3637	int rc = g_aPgmShadowModeData[idxOldShw].pfnExit(pVCpu);
3638	AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
3639	}
3640	}
3641	else
3642	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3643
3644	/* guest */
3645	uintptr_t const idxOldGst = pVCpu->pgm.s.idxGuestModeData;
3646	if ( idxOldGst < RT_ELEMENTS(g_aPgmGuestModeData)
3647	&& g_aPgmGuestModeData[idxOldGst].pfnExit)
3648	{
3649	int rc = g_aPgmGuestModeData[idxOldGst].pfnExit(pVCpu);
3650	AssertMsgReturn(RT_SUCCESS(rc), ("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc), rc);
3651	}
3652	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
3653
3654	/*
3655	* Load new paging mode data.
3656	*/
3657	pgmR3ModeDataSwitch(pVCpu, enmShadowMode, enmGuestMode);
3658
3659	/*
3660	* Enter new shadow mode (if changed).
3661	*/
3662	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3663	{
3664	int rc;
3665	bool const fIsNewGuestPagingMode64Bits = enmGuestMode >= PGMMODE_AMD64;
3666	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3667	switch (enmShadowMode)
3668	{
3669	case PGMMODE_32_BIT:
3670	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3671	break;
3672	case PGMMODE_PAE:
3673	case PGMMODE_PAE_NX:
3674	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3675	break;
3676	case PGMMODE_AMD64:
3677	case PGMMODE_AMD64_NX:
3678	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3679	break;
3680	case PGMMODE_NESTED_32BIT:
3681	rc = PGM_SHW_NAME_NESTED_32BIT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3682	break;
3683	case PGMMODE_NESTED_PAE:
3684	rc = PGM_SHW_NAME_NESTED_PAE(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3685	break;
3686	case PGMMODE_NESTED_AMD64:
3687	rc = PGM_SHW_NAME_NESTED_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3688	break;
3689	case PGMMODE_EPT:
3690	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3691	break;
3692	case PGMMODE_REAL:
3693	case PGMMODE_PROTECTED:
3694	default:
3695	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3696	return VERR_INTERNAL_ERROR;
3697	}
3698	if (RT_FAILURE(rc))
3699	{
3700	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3701	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3702	return rc;
3703	}
3704	}
3705
3706	/*
3707	* Always flag the necessary updates
3708	*/
3709	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3710
3711	/*
3712	* Enter the new guest and shadow+guest modes.
3713	*/
3714	int rc = -1;
3715	int rc2 = -1;
3716	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3717	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3718	switch (enmGuestMode)
3719	{
3720	case PGMMODE_REAL:
3721	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3722	switch (pVCpu->pgm.s.enmShadowMode)
3723	{
3724	case PGMMODE_32_BIT:
3725	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3726	break;
3727	case PGMMODE_PAE:
3728	case PGMMODE_PAE_NX:
3729	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3730	break;
3731	case PGMMODE_NESTED_32BIT:
3732	rc2 = PGM_BTH_NAME_NESTED_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3733	break;
3734	case PGMMODE_NESTED_PAE:
3735	rc2 = PGM_BTH_NAME_NESTED_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3736	break;
3737	case PGMMODE_NESTED_AMD64:
3738	rc2 = PGM_BTH_NAME_NESTED_AMD64_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3739	break;
3740	case PGMMODE_EPT:
3741	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3742	break;
3743	case PGMMODE_AMD64:
3744	case PGMMODE_AMD64_NX:
3745	AssertMsgFailedBreak(("Should use PAE shadow mode!\n"));
3746	default: AssertFailedBreak();
3747	}
3748	break;
3749
3750	case PGMMODE_PROTECTED:
3751	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3752	switch (pVCpu->pgm.s.enmShadowMode)
3753	{
3754	case PGMMODE_32_BIT:
3755	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3756	break;
3757	case PGMMODE_PAE:
3758	case PGMMODE_PAE_NX:
3759	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3760	break;
3761	case PGMMODE_NESTED_32BIT:
3762	rc2 = PGM_BTH_NAME_NESTED_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3763	break;
3764	case PGMMODE_NESTED_PAE:
3765	rc2 = PGM_BTH_NAME_NESTED_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3766	break;
3767	case PGMMODE_NESTED_AMD64:
3768	rc2 = PGM_BTH_NAME_NESTED_AMD64_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3769	break;
3770	case PGMMODE_EPT:
3771	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3772	break;
3773	case PGMMODE_AMD64:
3774	case PGMMODE_AMD64_NX:
3775	AssertMsgFailedBreak(("Should use PAE shadow mode!\n"));
3776	default: AssertFailedBreak();
3777	}
3778	break;
3779
3780	case PGMMODE_32_BIT:
3781	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3782	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3783	switch (pVCpu->pgm.s.enmShadowMode)
3784	{
3785	case PGMMODE_32_BIT:
3786	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3787	break;
3788	case PGMMODE_PAE:
3789	case PGMMODE_PAE_NX:
3790	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3791	break;
3792	case PGMMODE_NESTED_32BIT:
3793	rc2 = PGM_BTH_NAME_NESTED_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3794	break;
3795	case PGMMODE_NESTED_PAE:
3796	rc2 = PGM_BTH_NAME_NESTED_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3797	break;
3798	case PGMMODE_NESTED_AMD64:
3799	rc2 = PGM_BTH_NAME_NESTED_AMD64_32BIT(Enter)(pVCpu, GCPhysCR3);
3800	break;
3801	case PGMMODE_EPT:
3802	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3803	break;
3804	case PGMMODE_AMD64:
3805	case PGMMODE_AMD64_NX:
3806	AssertMsgFailedBreak(("Should use PAE shadow mode!\n"));
3807	default: AssertFailedBreak();
3808	}
3809	break;
3810
3811	case PGMMODE_PAE_NX:
3812	case PGMMODE_PAE:
3813	{
3814	uint32_t u32Dummy, u32Features;
3815
3816	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3817	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3818	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3819	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (System/Processor)"));
3820
3821	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3822	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3823	switch (pVCpu->pgm.s.enmShadowMode)
3824	{
3825	case PGMMODE_PAE:
3826	case PGMMODE_PAE_NX:
3827	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3828	break;
3829	case PGMMODE_NESTED_32BIT:
3830	rc2 = PGM_BTH_NAME_NESTED_32BIT_PAE(Enter)(pVCpu, GCPhysCR3);
3831	break;
3832	case PGMMODE_NESTED_PAE:
3833	rc2 = PGM_BTH_NAME_NESTED_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3834	break;
3835	case PGMMODE_NESTED_AMD64:
3836	rc2 = PGM_BTH_NAME_NESTED_AMD64_PAE(Enter)(pVCpu, GCPhysCR3);
3837	break;
3838	case PGMMODE_EPT:
3839	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3840	break;
3841	case PGMMODE_32_BIT:
3842	case PGMMODE_AMD64:
3843	case PGMMODE_AMD64_NX:
3844	AssertMsgFailedBreak(("Should use PAE shadow mode!\n"));
3845	default: AssertFailedBreak();
3846	}
3847	break;
3848	}
3849
3850	#ifdef VBOX_WITH_64_BITS_GUESTS
3851	case PGMMODE_AMD64_NX:
3852	case PGMMODE_AMD64:
3853	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_AMD64_PAGE_MASK;
3854	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3855	switch (pVCpu->pgm.s.enmShadowMode)
3856	{
3857	case PGMMODE_AMD64:
3858	case PGMMODE_AMD64_NX:
3859	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3860	break;
3861	case PGMMODE_NESTED_32BIT:
3862	rc2 = PGM_BTH_NAME_NESTED_32BIT_AMD64(Enter)(pVCpu, GCPhysCR3);
3863	break;
3864	case PGMMODE_NESTED_PAE:
3865	rc2 = PGM_BTH_NAME_NESTED_PAE_AMD64(Enter)(pVCpu, GCPhysCR3);
3866	break;
3867	case PGMMODE_NESTED_AMD64:
3868	rc2 = PGM_BTH_NAME_NESTED_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3869	break;
3870	case PGMMODE_EPT:
3871	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3872	break;
3873	case PGMMODE_32_BIT:
3874	case PGMMODE_PAE:
3875	case PGMMODE_PAE_NX:
3876	AssertMsgFailedBreak(("Should use AMD64 shadow mode!\n"));
3877	default: AssertFailedBreak();
3878	}
3879	break;
3880	#endif
3881
3882	default:
3883	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3884	rc = VERR_NOT_IMPLEMENTED;
3885	break;
3886	}
3887
3888	/* Set the new guest CR3. */
3889	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3890
3891	/* status codes. */
3892	AssertRC(rc);
3893	AssertRC(rc2);
3894	if (RT_SUCCESS(rc))
3895	{
3896	rc = rc2;
3897	if (RT_SUCCESS(rc)) /* no informational status codes. */
3898	rc = VINF_SUCCESS;
3899	}
3900
3901	/* Notify HM as well. */
3902	HMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3903	return rc;
3904	}
3905
3906
3907	/**
3908	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3909	*
3910	* @returns VBox status code, fully asserted.
3911	* @param pVCpu The cross context virtual CPU structure.
3912	*/
3913	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3914	{
3915	/* Unmap the old CR3 value before flushing everything. */
3916	int rc = VINF_SUCCESS;
3917	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
3918	if ( idxBth < RT_ELEMENTS(g_aPgmBothModeData)
3919	&& g_aPgmBothModeData[idxBth].pfnMapCR3)
3920	{
3921	rc = g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
3922	AssertRC(rc);
3923	}
3924
3925	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3926	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
3927	if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
3928	&& g_aPgmShadowModeData[idxShw].pfnExit)
3929	{
3930	rc = g_aPgmShadowModeData[idxShw].pfnExit(pVCpu);
3931	AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
3932	}
3933
3934	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3935	return rc;
3936	}
3937
3938
3939	/**
3940	* Called by pgmPoolFlushAllInt after flushing the pool.
3941	*
3942	* @returns VBox status code, fully asserted.
3943	* @param pVM The cross context VM structure.
3944	* @param pVCpu The cross context virtual CPU structure.
3945	*/
3946	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3947	{
3948	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3949	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3950	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3951	AssertRCReturn(rc, rc);
3952	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3953
3954	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3955	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED_32BIT
3956	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3957	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3958	return rc;
3959	}
3960
3961
3962	/**
3963	* Called by PGMR3PhysSetA20 after changing the A20 state.
3964	*
3965	* @param pVCpu The cross context virtual CPU structure.
3966	*/
3967	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
3968	{
3969	/** @todo Probably doing a bit too much here. */
3970	int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
3971	AssertReleaseRC(rc);
3972	rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
3973	AssertReleaseRC(rc);
3974	}
3975
3976
3977	#ifdef VBOX_WITH_DEBUGGER
3978
3979	/**
3980	* @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
3981	*/
3982	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3983	{
3984	/*
3985	* Validate input.
3986	*/
3987	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3988	PVM pVM = pUVM->pVM;
3989	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
3990
3991	if (!cArgs)
3992	{
3993	/*
3994	* Print the list of error injection locations with status.
3995	*/
3996	DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
3997	DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3998	}
3999	else
4000	{
4001	/*
4002	* String switch on where to inject the error.
4003	*/
4004	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4005	const char *pszWhere = paArgs[0].u.pszString;
4006	if (!strcmp(pszWhere, "handy"))
4007	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4008	else
4009	return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
4010	DBGCCmdHlpPrintf(pCmdHlp, "done\n");
4011	}
4012	return VINF_SUCCESS;
4013	}
4014
4015
4016	/**
4017	* @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
4018	*/
4019	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
4020	{
4021	/*
4022	* Validate input.
4023	*/
4024	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
4025	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
4026	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
4027	if (!pVCpu)
4028	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
4029
4030	/*
4031	* Force page directory sync.
4032	*/
4033	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4034
4035	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
4036	if (RT_FAILURE(rc))
4037	return rc;
4038
4039	return VINF_SUCCESS;
4040	}
4041
4042	#ifdef VBOX_STRICT
4043
4044	/**
4045	* EMT callback for pgmR3CmdAssertCR3.
4046	*
4047	* @returns VBox status code.
4048	* @param pUVM The user mode VM handle.
4049	* @param pcErrors Where to return the error count.
4050	*/
4051	static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
4052	{
4053	PVM pVM = pUVM->pVM;
4054	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
4055	PVMCPU pVCpu = VMMGetCpu(pVM);
4056
4057	*pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4058
4059	return VINF_SUCCESS;
4060	}
4061
4062
4063	/**
4064	* @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
4065	*/
4066	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
4067	{
4068	/*
4069	* Validate input.
4070	*/
4071	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
4072	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
4073
4074	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
4075	if (RT_FAILURE(rc))
4076	return rc;
4077
4078	unsigned cErrors = 0;
4079	rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
4080	if (RT_FAILURE(rc))
4081	return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
4082	if (cErrors > 0)
4083	return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
4084	return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
4085	}
4086
4087	#endif /* VBOX_STRICT */
4088
4089	/**
4090	* @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
4091	*/
4092	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
4093	{
4094	/*
4095	* Validate input.
4096	*/
4097	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
4098	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
4099	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
4100	if (!pVCpu)
4101	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
4102
4103	/*
4104	* Force page directory sync.
4105	*/
4106	int rc;
4107	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4108	{
4109	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4110	rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
4111	}
4112	else
4113	{
4114	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4115	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4116	rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
4117	}
4118	return rc;
4119	}
4120
4121
4122	/**
4123	* @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
4124	*/
4125	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
4126	{
4127	/*
4128	* Validate input.
4129	*/
4130	NOREF(pCmd);
4131	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
4132	PVM pVM = pUVM->pVM;
4133	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 \|\| cArgs == 2);
4134	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType == DBGCVAR_TYPE_STRING);
4135	if (cArgs == 2)
4136	{
4137	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[1].enmType == DBGCVAR_TYPE_STRING);
4138	if (strcmp(paArgs[1].u.pszString, "nozero"))
4139	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4140	}
4141	bool fIncZeroPgs = cArgs < 2;
4142
4143	/*
4144	* Open the output file and get the ram parameters.
4145	*/
4146	RTFILE hFile;
4147	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4148	if (RT_FAILURE(rc))
4149	return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4150
4151	uint32_t cbRamHole = 0;
4152	CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4153	uint64_t cbRam = 0;
4154	CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
4155	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4156
4157	/*
4158	* Dump the physical memory, page by page.
4159	*/
4160	RTGCPHYS GCPhys = 0;
4161	char abZeroPg[PAGE_SIZE];
4162	RT_ZERO(abZeroPg);
4163
4164	pgmLock(pVM);
4165	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4166	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4167	pRam = pRam->pNextR3)
4168	{
4169	/* fill the gap */
4170	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4171	{
4172	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4173	{
4174	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4175	GCPhys += PAGE_SIZE;
4176	}
4177	}
4178
4179	PCPGMPAGE pPage = &pRam->aPages[0];
4180	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4181	{
4182	if ( PGM_PAGE_IS_ZERO(pPage)
4183	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4184	{
4185	if (fIncZeroPgs)
4186	{
4187	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4188	if (RT_FAILURE(rc))
4189	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4190	}
4191	}
4192	else
4193	{
4194	switch (PGM_PAGE_GET_TYPE(pPage))
4195	{
4196	case PGMPAGETYPE_RAM:
4197	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4198	case PGMPAGETYPE_ROM:
4199	case PGMPAGETYPE_MMIO2:
4200	{
4201	void const *pvPage;
4202	PGMPAGEMAPLOCK Lock;
4203	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4204	if (RT_SUCCESS(rc))
4205	{
4206	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4207	PGMPhysReleasePageMappingLock(pVM, &Lock);
4208	if (RT_FAILURE(rc))
4209	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4210	}
4211	else
4212	DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4213	break;
4214	}
4215
4216	default:
4217	AssertFailed();
4218	RT_FALL_THRU();
4219	case PGMPAGETYPE_MMIO:
4220	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4221	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
4222	if (fIncZeroPgs)
4223	{
4224	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4225	if (RT_FAILURE(rc))
4226	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4227	}
4228	break;
4229	}
4230	}
4231
4232
4233	/* advance */
4234	GCPhys += PAGE_SIZE;
4235	pPage++;
4236	}
4237	}
4238	pgmUnlock(pVM);
4239
4240	RTFileClose(hFile);
4241	if (RT_SUCCESS(rc))
4242	return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4243	return VINF_SUCCESS;
4244	}
4245
4246	#endif /* VBOX_WITH_DEBUGGER */
4247
4248	/**
4249	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4250	*/
4251	typedef struct PGMCHECKINTARGS
4252	{
4253	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4254	PPGMPHYSHANDLER pPrevPhys;
4255	#ifdef VBOX_WITH_RAW_MODE
4256	PPGMVIRTHANDLER pPrevVirt;
4257	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4258	#else
4259	void pvFiller1, pvFiller2;
4260	#endif
4261	PVM pVM;
4262	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4263
4264	/**
4265	* Validate a node in the physical handler tree.
4266	*
4267	* @returns 0 on if ok, other wise 1.
4268	* @param pNode The handler node.
4269	* @param pvUser pVM.
4270	*/
4271	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4272	{
4273	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4274	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4275	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4276	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,
4277	("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4278	AssertReleaseMsg( !pArgs->pPrevPhys
4279	\|\| ( pArgs->fLeftToRight
4280	? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key
4281	: pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4282	("pPrevPhys=%p %RGp-%RGp %s\n"
4283	" pCur=%p %RGp-%RGp %s\n",
4284	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4285	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4286	pArgs->pPrevPhys = pCur;
4287	return 0;
4288	}
4289
4290	#ifdef VBOX_WITH_RAW_MODE
4291
4292	/**
4293	* Validate a node in the virtual handler tree.
4294	*
4295	* @returns 0 on if ok, other wise 1.
4296	* @param pNode The handler node.
4297	* @param pvUser pVM.
4298	*/
4299	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4300	{
4301	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4302	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4303	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4304	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4305	AssertReleaseMsg( !pArgs->pPrevVirt
4306	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4307	("pPrevVirt=%p %RGv-%RGv %s\n"
4308	" pCur=%p %RGv-%RGv %s\n",
4309	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4310	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4311	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4312	{
4313	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -(intptr_t)RT_UOFFSETOF_DYN(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4314	("pCur=%p %RGv-%RGv %s\n"
4315	"iPage=%d offVirtHandle=%#x expected %#x\n",
4316	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4317	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -(intptr_t)RT_UOFFSETOF_DYN(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4318	}
4319	pArgs->pPrevVirt = pCur;
4320	return 0;
4321	}
4322
4323
4324	/**
4325	* Validate a node in the virtual handler tree.
4326	*
4327	* @returns 0 on if ok, other wise 1.
4328	* @param pNode The handler node.
4329	* @param pvUser pVM.
4330	*/
4331	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4332	{
4333	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4334	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4335	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4336	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4337	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4338	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4339	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4340	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4341	" pCur=%p %RGp-%RGp\n",
4342	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4343	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4344	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4345	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4346	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4347	" pCur=%p %RGp-%RGp\n",
4348	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4349	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4350	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4351	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4352	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4353	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4354	{
4355	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4356	for (;;)
4357	{
4358	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4359	AssertReleaseMsg(pCur2 != pCur,
4360	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4361	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4362	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4363	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4364	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4365	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4366	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4367	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4368	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4369	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4370	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4371	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4372	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4373	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4374	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4375	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4376	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4377	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4378	break;
4379	}
4380	}
4381
4382	pArgs->pPrevPhys2Virt = pCur;
4383	return 0;
4384	}
4385
4386	#endif /* VBOX_WITH_RAW_MODE */
4387
4388	/**
4389	* Perform an integrity check on the PGM component.
4390	*
4391	* @returns VINF_SUCCESS if everything is fine.
4392	* @returns VBox error status after asserting on integrity breach.
4393	* @param pVM The cross context VM structure.
4394	*/
4395	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4396	{
4397	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4398
4399	/*
4400	* Check the trees.
4401	*/
4402	int cErrors = 0;
4403	const PGMCHECKINTARGS LeftToRight = { true, NULL, NULL, NULL, pVM };
4404	const PGMCHECKINTARGS RightToLeft = { false, NULL, NULL, NULL, pVM };
4405	PGMCHECKINTARGS Args = LeftToRight;
4406	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4407	Args = RightToLeft;
4408	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4409	#ifdef VBOX_WITH_RAW_MODE
4410	Args = LeftToRight;
4411	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4412	Args = RightToLeft;
4413	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4414	Args = LeftToRight;
4415	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4416	Args = RightToLeft;
4417	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4418	Args = LeftToRight;
4419	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4420	Args = RightToLeft;
4421	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4422	#endif /* VBOX_WITH_RAW_MODE */
4423
4424	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4425	}
4426

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 73250

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