PGM.cpp@ 73268

Last change on this file since 73268 was 73268, checked in by vboxsync, 7 years ago
PGM: Working on consolidating templated code... bugref:9044
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 186.8 KB

Line
1	/* $Id: PGM.cpp 73268 2018-07-20 14:49:05Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @sa @ref grp_pgm
22	* @subpage pg_pgm_pool
23	* @subpage pg_pgm_phys
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred
30	* to as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	* Note! The intermediate memory context is also used for 64-bit guest
85	* execution on 32-bit hosts. Because we need to load 64-bit registers
86	* prior to switching to guest context, we need to be in 64-bit mode
87	* first. So, HM has some 64-bit worker routines in VMMRC.rc that get
88	* invoked via the special world switcher code in LegacyToAMD64.asm.
89	*
90	*
91	* @subsection subsec_pgm_int_gc Guest Context Mappings
92	*
93	* During assignment and relocation of a guest context mapping the intermediate
94	* memory context is used to verify the new location.
95	*
96	* Guest context mappings are currently restricted to below 4GB, for reasons
97	* of simplicity. This may change when we implement AMD64 support.
98	*
99	*
100	*
101	*
102	* @section sec_pgm_misc Misc
103	*
104	*
105	* @subsection sec_pgm_misc_A20 The A20 Gate
106	*
107	* PGM implements the A20 gate masking when translating a virtual guest address
108	* into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
109	* the code reading the guest page table entries during shadowing. The masking
110	* is done consistenly for all CPU modes, paged ones included. Large pages are
111	* also masked correctly. (On current CPUs, experiments indicates that AMD does
112	* not apply A20M in paged modes and intel only does it for the 2nd MB of
113	* memory.)
114	*
115	* The A20 gate implementation is per CPU core. It can be configured on a per
116	* core basis via the keyboard device and PC architecture device. This is
117	* probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
118	* guest OSes try pushing things anyway, so who cares. (On current real systems
119	* the A20M signal is probably only sent to the boot CPU and it affects all
120	* thread and probably all cores in that package.)
121	*
122	* The keyboard device and the PC architecture device doesn't OR their A20
123	* config bits together, rather they are currently implemented such that they
124	* mirror the CPU state. So, flipping the bit in either of them will change the
125	* A20 state. (On real hardware the bits of the two devices should probably be
126	* ORed together to indicate enabled, i.e. both needs to be cleared to disable
127	* A20 masking.)
128	*
129	* The A20 state will change immediately, transmeta fashion. There is no delays
130	* due to buses, wiring or other physical stuff. (On real hardware there are
131	* normally delays, the delays differs between the two devices and probably also
132	* between chipsets and CPU generations. Note that it's said that transmeta CPUs
133	* does the change immediately like us, they apparently intercept/handles the
134	* port accesses in microcode. Neat.)
135	*
136	* @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
137	*
138	*
139	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
140	*
141	* The differences between legacy PAE and long mode PAE are:
142	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
143	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
144	* usual meanings while 6 is ignored (AMD). This means that upon switching to
145	* legacy PAE mode we'll have to clear these bits and when going to long mode
146	* they must be set. This applies to both intermediate and shadow contexts,
147	* however we don't need to do it for the intermediate one since we're
148	* executing with CR0.WP at that time.
149	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
150	* a page aligned one is required.
151	*
152	*
153	* @section sec_pgm_handlers Access Handlers
154	*
155	* Placeholder.
156	*
157	*
158	* @subsection sec_pgm_handlers_phys Physical Access Handlers
159	*
160	* Placeholder.
161	*
162	*
163	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
164	*
165	* We currently implement three types of virtual access handlers: ALL, WRITE
166	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERKIND for some more details.
167	*
168	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
169	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
170	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
171	* rest of this section is going to be about these handlers.
172	*
173	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
174	* how successful this is gonna be...
175	*
176	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
177	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
178	* and create a new node that is inserted into the AVL tree (range key). Then
179	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
180	*
181	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
182	*
183	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
184	* via the current guest CR3 and update the physical page -> virtual handler
185	* translation. Needless to say, this doesn't exactly scale very well. If any changes
186	* are detected, it will flag a virtual bit update just like we did on registration.
187	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
188	*
189	* 2b. The virtual bit update process will iterate all the pages covered by all the
190	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
191	* virtual handlers on that page.
192	*
193	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
194	* we don't miss any alias mappings of the monitored pages.
195	*
196	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
197	*
198	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
199	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
200	* will call the handlers like in the next step. If the physical mapping has
201	* changed we will - some time in the future - perform a handler callback
202	* (optional) and update the physical -> virtual handler cache.
203	*
204	* 4. \#PF(,write) on a page in the range. This will cause the handler to
205	* be invoked.
206	*
207	* 5. The guest invalidates the page and changes the physical backing or
208	* unmaps it. This should cause the invalidation callback to be invoked
209	* (it might not yet be 100% perfect). Exactly what happens next... is
210	* this where we mess up and end up out of sync for a while?
211	*
212	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
213	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
214	* this handler to NONE and trigger a full PGM resync (basically the same
215	* as int step 1). Which means 2 is executed again.
216	*
217	*
218	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
219	*
220	* There is a bunch of things that needs to be done to make the virtual handlers
221	* work 100% correctly and work more efficiently.
222	*
223	* The first bit hasn't been implemented yet because it's going to slow the
224	* whole mess down even more, and besides it seems to be working reliably for
225	* our current uses. OTOH, some of the optimizations might end up more or less
226	* implementing the missing bits, so we'll see.
227	*
228	* On the optimization side, the first thing to do is to try avoid unnecessary
229	* cache flushing. Then try team up with the shadowing code to track changes
230	* in mappings by means of access to them (shadow in), updates to shadows pages,
231	* invlpg, and shadow PT discarding (perhaps).
232	*
233	* Some idea that have popped up for optimization for current and new features:
234	* - bitmap indicating where there are virtual handlers installed.
235	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
236	* - Further optimize this by min/max (needs min/max avl getters).
237	* - Shadow page table entry bit (if any left)?
238	*
239	*/
240
241
242	/** @page pg_pgm_phys PGM Physical Guest Memory Management
243	*
244	*
245	* Objectives:
246	* - Guest RAM over-commitment using memory ballooning,
247	* zero pages and general page sharing.
248	* - Moving or mirroring a VM onto a different physical machine.
249	*
250	*
251	* @section sec_pgmPhys_Definitions Definitions
252	*
253	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
254	* machinery associated with it.
255	*
256	*
257	*
258	*
259	* @section sec_pgmPhys_AllocPage Allocating a page.
260	*
261	* Initially we map all guest memory to the (per VM) zero page, which
262	* means that none of the read functions will cause pages to be allocated.
263	*
264	* Exception, access bit in page tables that have been shared. This must
265	* be handled, but we must also make sure PGMGst*Modify doesn't make
266	* unnecessary modifications.
267	*
268	* Allocation points:
269	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
270	* - Replacing a zero page mapping at \#PF.
271	* - Replacing a shared page mapping at \#PF.
272	* - ROM registration (currently MMR3RomRegister).
273	* - VM restore (pgmR3Load).
274	*
275	* For the first three it would make sense to keep a few pages handy
276	* until we've reached the max memory commitment for the VM.
277	*
278	* For the ROM registration, we know exactly how many pages we need
279	* and will request these from ring-0. For restore, we will save
280	* the number of non-zero pages in the saved state and allocate
281	* them up front. This would allow the ring-0 component to refuse
282	* the request if the isn't sufficient memory available for VM use.
283	*
284	* Btw. for both ROM and restore allocations we won't be requiring
285	* zeroed pages as they are going to be filled instantly.
286	*
287	*
288	* @section sec_pgmPhys_FreePage Freeing a page
289	*
290	* There are a few points where a page can be freed:
291	* - After being replaced by the zero page.
292	* - After being replaced by a shared page.
293	* - After being ballooned by the guest additions.
294	* - At reset.
295	* - At restore.
296	*
297	* When freeing one or more pages they will be returned to the ring-0
298	* component and replaced by the zero page.
299	*
300	* The reasoning for clearing out all the pages on reset is that it will
301	* return us to the exact same state as on power on, and may thereby help
302	* us reduce the memory load on the system. Further it might have a
303	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
304	*
305	* On restore, as mention under the allocation topic, pages should be
306	* freed / allocated depending on how many is actually required by the
307	* new VM state. The simplest approach is to do like on reset, and free
308	* all non-ROM pages and then allocate what we need.
309	*
310	* A measure to prevent some fragmentation, would be to let each allocation
311	* chunk have some affinity towards the VM having allocated the most pages
312	* from it. Also, try make sure to allocate from allocation chunks that
313	* are almost full. Admittedly, both these measures might work counter to
314	* our intentions and its probably not worth putting a lot of effort,
315	* cpu time or memory into this.
316	*
317	*
318	* @section sec_pgmPhys_SharePage Sharing a page
319	*
320	* The basic idea is that there there will be a idle priority kernel
321	* thread walking the non-shared VM pages hashing them and looking for
322	* pages with the same checksum. If such pages are found, it will compare
323	* them byte-by-byte to see if they actually are identical. If found to be
324	* identical it will allocate a shared page, copy the content, check that
325	* the page didn't change while doing this, and finally request both the
326	* VMs to use the shared page instead. If the page is all zeros (special
327	* checksum and byte-by-byte check) it will request the VM that owns it
328	* to replace it with the zero page.
329	*
330	* To make this efficient, we will have to make sure not to try share a page
331	* that will change its contents soon. This part requires the most work.
332	* A simple idea would be to request the VM to write monitor the page for
333	* a while to make sure it isn't modified any time soon. Also, it may
334	* make sense to skip pages that are being write monitored since this
335	* information is readily available to the thread if it works on the
336	* per-VM guest memory structures (presently called PGMRAMRANGE).
337	*
338	*
339	* @section sec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
340	*
341	* The pages are organized in allocation chunks in ring-0, this is a necessity
342	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
343	* could easily work on a page-by-page basis if we liked. Whether this is possible
344	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
345	* become a problem as part of the idea here is that we wish to return memory to
346	* the host system.
347	*
348	* For instance, starting two VMs at the same time, they will both allocate the
349	* guest memory on-demand and if permitted their page allocations will be
350	* intermixed. Shut down one of the two VMs and it will be difficult to return
351	* any memory to the host system because the page allocation for the two VMs are
352	* mixed up in the same allocation chunks.
353	*
354	* To further complicate matters, when pages are freed because they have been
355	* ballooned or become shared/zero the whole idea is that the page is supposed
356	* to be reused by another VM or returned to the host system. This will cause
357	* allocation chunks to contain pages belonging to different VMs and prevent
358	* returning memory to the host when one of those VM shuts down.
359	*
360	* The only way to really deal with this problem is to move pages. This can
361	* either be done at VM shutdown and or by the idle priority worker thread
362	* that will be responsible for finding sharable/zero pages. The mechanisms
363	* involved for coercing a VM to move a page (or to do it for it) will be
364	* the same as when telling it to share/zero a page.
365	*
366	*
367	* @section sec_pgmPhys_Tracking Tracking Structures And Their Cost
368	*
369	* There's a difficult balance between keeping the per-page tracking structures
370	* (global and guest page) easy to use and keeping them from eating too much
371	* memory. We have limited virtual memory resources available when operating in
372	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
373	* tracking structures will be attempted designed such that we can deal with up
374	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
375	*
376	*
377	* @subsection subsec_pgmPhys_Tracking_Kernel Kernel Space
378	*
379	* @see pg_GMM
380	*
381	* @subsection subsec_pgmPhys_Tracking_PerVM Per-VM
382	*
383	* Fixed info is the physical address of the page (HCPhys) and the page id
384	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
385	* Today we've restricting ourselves to 40(-12) bits because this is the current
386	* restrictions of all AMD64 implementations (I think Barcelona will up this
387	* to 48(-12) bits, not that it really matters) and I needed the bits for
388	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
389	* decent range for the page id: 2^(28+12) = 1024TB.
390	*
391	* In additions to these, we'll have to keep maintaining the page flags as we
392	* currently do. Although it wouldn't harm to optimize these quite a bit, like
393	* for instance the ROM shouldn't depend on having a write handler installed
394	* in order for it to become read-only. A RO/RW bit should be considered so
395	* that the page syncing code doesn't have to mess about checking multiple
396	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
397	* figure out how to setup a shadow PTE. But this of course, is second
398	* priority at present. Current this requires 12 bits, but could probably
399	* be optimized to ~8.
400	*
401	* Then there's the 24 bits used to track which shadow page tables are
402	* currently mapping a page for the purpose of speeding up physical
403	* access handlers, and thereby the page pool cache. More bit for this
404	* purpose wouldn't hurt IIRC.
405	*
406	* Then there is a new bit in which we need to record what kind of page
407	* this is, shared, zero, normal or write-monitored-normal. This'll
408	* require 2 bits. One bit might be needed for indicating whether a
409	* write monitored page has been written to. And yet another one or
410	* two for tracking migration status. 3-4 bits total then.
411	*
412	* Whatever is left will can be used to record the sharabilitiy of a
413	* page. The page checksum will not be stored in the per-VM table as
414	* the idle thread will not be permitted to do modifications to it.
415	* It will instead have to keep its own working set of potentially
416	* shareable pages and their check sums and stuff.
417	*
418	* For the present we'll keep the current packing of the
419	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
420	* we'll have to change it to a struct with a total of 128-bits at
421	* our disposal.
422	*
423	* The initial layout will be like this:
424	* @verbatim
425	RTHCPHYS HCPhys; The current stuff.
426	63:40 Current shadow PT tracking stuff.
427	39:12 The physical page frame number.
428	11:0 The current flags.
429	uint32_t u28PageId : 28; The page id.
430	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
431	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
432	uint32_t u1Reserved : 1; Reserved for later.
433	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
434	@endverbatim
435	*
436	* The final layout will be something like this:
437	* @verbatim
438	RTHCPHYS HCPhys; The current stuff.
439	63:48 High page id (12+).
440	47:12 The physical page frame number.
441	11:0 Low page id.
442	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
443	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
444	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
445	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
446	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
447	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
448	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
449	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
450	@endverbatim
451	*
452	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
453	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
454	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
455	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
456	*
457	* A couple of cost examples for the total cost per-VM + kernel.
458	* 32-bit Windows and 32-bit linux:
459	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
460	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
461	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
462	* 64-bit Windows and 64-bit linux:
463	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
464	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
465	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
466	*
467	* UPDATE - 2007-09-27:
468	* Will need a ballooned flag/state too because we cannot
469	* trust the guest 100% and reporting the same page as ballooned more
470	* than once will put the GMM off balance.
471	*
472	*
473	* @section sec_pgmPhys_Serializing Serializing Access
474	*
475	* Initially, we'll try a simple scheme:
476	*
477	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
478	* by the EMT thread of that VM while in the pgm critsect.
479	* - Other threads in the VM process that needs to make reliable use of
480	* the per-VM RAM tracking structures will enter the critsect.
481	* - No process external thread or kernel thread will ever try enter
482	* the pgm critical section, as that just won't work.
483	* - The idle thread (and similar threads) doesn't not need 100% reliable
484	* data when performing it tasks as the EMT thread will be the one to
485	* do the actual changes later anyway. So, as long as it only accesses
486	* the main ram range, it can do so by somehow preventing the VM from
487	* being destroyed while it works on it...
488	*
489	* - The over-commitment management, including the allocating/freeing
490	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
491	* more mundane mutex implementation is broken on Linux).
492	* - A separate mutex is protecting the set of allocation chunks so
493	* that pages can be shared or/and freed up while some other VM is
494	* allocating more chunks. This mutex can be take from under the other
495	* one, but not the other way around.
496	*
497	*
498	* @section sec_pgmPhys_Request VM Request interface
499	*
500	* When in ring-0 it will become necessary to send requests to a VM so it can
501	* for instance move a page while defragmenting during VM destroy. The idle
502	* thread will make use of this interface to request VMs to setup shared
503	* pages and to perform write monitoring of pages.
504	*
505	* I would propose an interface similar to the current VMReq interface, similar
506	* in that it doesn't require locking and that the one sending the request may
507	* wait for completion if it wishes to. This shouldn't be very difficult to
508	* realize.
509	*
510	* The requests themselves are also pretty simple. They are basically:
511	* -# Check that some precondition is still true.
512	* -# Do the update.
513	* -# Update all shadow page tables involved with the page.
514	*
515	* The 3rd step is identical to what we're already doing when updating a
516	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
517	*
518	*
519	*
520	* @section sec_pgmPhys_MappingCaches Mapping Caches
521	*
522	* In order to be able to map in and out memory and to be able to support
523	* guest with more RAM than we've got virtual address space, we'll employing
524	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
525	* however on 32-bit darwin the ring-0 code is running in a different memory
526	* context and therefore needs a separate cache. In raw-mode context we also
527	* need a separate cache. The 32-bit darwin mapping cache and the one for
528	* raw-mode context share a lot of code, see PGMRZDYNMAP.
529	*
530	*
531	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
532	*
533	* We've considered implementing the ring-3 mapping cache page based but found
534	* that this was bother some when one had to take into account TLBs+SMP and
535	* portability (missing the necessary APIs on several platforms). There were
536	* also some performance concerns with this approach which hadn't quite been
537	* worked out.
538	*
539	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
540	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
541	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
542	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
543	* costly than a single page, although how much more costly is uncertain. We'll
544	* try address this by using a very big cache, preferably bigger than the actual
545	* VM RAM size if possible. The current VM RAM sizes should give some idea for
546	* 32-bit boxes, while on 64-bit we can probably get away with employing an
547	* unlimited cache.
548	*
549	* The cache have to parts, as already indicated, the ring-3 side and the
550	* ring-0 side.
551	*
552	* The ring-0 will be tied to the page allocator since it will operate on the
553	* memory objects it contains. It will therefore require the first ring-0 mutex
554	* discussed in @ref sec_pgmPhys_Serializing. We some double house keeping wrt
555	* to who has mapped what I think, since both VMMR0.r0 and RTR0MemObj will keep
556	* track of mapping relations
557	*
558	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
559	* require anyone that desires to do changes to the mapping cache to do that
560	* from within this critsect. Alternatively, we could employ a separate critsect
561	* for serializing changes to the mapping cache as this would reduce potential
562	* contention with other threads accessing mappings unrelated to the changes
563	* that are in process. We can see about this later, contention will show
564	* up in the statistics anyway, so it'll be simple to tell.
565	*
566	* The organization of the ring-3 part will be very much like how the allocation
567	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
568	* having to walk the tree all the time, we'll have a couple of lookaside entries
569	* like in we do for I/O ports and MMIO in IOM.
570	*
571	* The simplified flow of a PGMPhysRead/Write function:
572	* -# Enter the PGM critsect.
573	* -# Lookup GCPhys in the ram ranges and get the Page ID.
574	* -# Calc the Allocation Chunk ID from the Page ID.
575	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
576	* If not found in cache:
577	* -# Call ring-0 and request it to be mapped and supply
578	* a chunk to be unmapped if the cache is maxed out already.
579	* -# Insert the new mapping into the AVL tree (id + R3 address).
580	* -# Update the relevant lookaside entry and return the mapping address.
581	* -# Do the read/write according to monitoring flags and everything.
582	* -# Leave the critsect.
583	*
584	*
585	* @section sec_pgmPhys_Fallback Fallback
586	*
587	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
588	* API and thus require a fallback.
589	*
590	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
591	* will return to the ring-3 caller (and later ring-0) and asking it to seed
592	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
593	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
594	* "SeededAllocPages" call to ring-0.
595	*
596	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
597	* all page sharing (zero page detection will continue). It will also force
598	* all allocations to come from the VM which seeded the page. Both these
599	* measures are taken to make sure that there will never be any need for
600	* mapping anything into ring-3 - everything will be mapped already.
601	*
602	* Whether we'll continue to use the current MM locked memory management
603	* for this I don't quite know (I'd prefer not to and just ditch that all
604	* together), we'll see what's simplest to do.
605	*
606	*
607	*
608	* @section sec_pgmPhys_Changes Changes
609	*
610	* Breakdown of the changes involved?
611	*/
612
613
614	/*********************************************************************************************************************************
615	* Header Files *
616	*********************************************************************************************************************************/
617	#define LOG_GROUP LOG_GROUP_PGM
618	#include <VBox/vmm/dbgf.h>
619	#include <VBox/vmm/pgm.h>
620	#include <VBox/vmm/cpum.h>
621	#include <VBox/vmm/iom.h>
622	#include <VBox/sup.h>
623	#include <VBox/vmm/mm.h>
624	#include <VBox/vmm/em.h>
625	#include <VBox/vmm/stam.h>
626	#ifdef VBOX_WITH_REM
627	# include <VBox/vmm/rem.h>
628	#endif
629	#include <VBox/vmm/selm.h>
630	#include <VBox/vmm/ssm.h>
631	#include <VBox/vmm/hm.h>
632	#include "PGMInternal.h"
633	#include <VBox/vmm/vm.h>
634	#include <VBox/vmm/uvm.h>
635	#include "PGMInline.h"
636
637	#include <VBox/dbg.h>
638	#include <VBox/param.h>
639	#include <VBox/err.h>
640
641	#include <iprt/asm.h>
642	#include <iprt/asm-amd64-x86.h>
643	#include <iprt/assert.h>
644	#include <iprt/env.h>
645	#include <iprt/mem.h>
646	#include <iprt/file.h>
647	#include <iprt/string.h>
648	#include <iprt/thread.h>
649
650
651	/*********************************************************************************************************************************
652	* Structures and Typedefs *
653	*********************************************************************************************************************************/
654	/**
655	* Argument package for pgmR3RElocatePhysHnadler, pgmR3RelocateVirtHandler and
656	* pgmR3RelocateHyperVirtHandler.
657	*/
658	typedef struct PGMRELOCHANDLERARGS
659	{
660	RTGCINTPTR offDelta;
661	PVM pVM;
662	} PGMRELOCHANDLERARGS;
663	/** Pointer to a page access handlere relocation argument package. */
664	typedef PGMRELOCHANDLERARGS const *PCPGMRELOCHANDLERARGS;
665
666
667	/*********************************************************************************************************************************
668	* Internal Functions *
669	*********************************************************************************************************************************/
670	static int pgmR3InitPaging(PVM pVM);
671	static int pgmR3InitStats(PVM pVM);
672	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
673	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
674	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
675	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
676	#ifdef VBOX_WITH_RAW_MODE
677	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
678	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
679	#endif /* VBOX_WITH_RAW_MODE */
680	#ifdef VBOX_STRICT
681	static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
682	#endif
683
684	#ifdef VBOX_WITH_DEBUGGER
685	static FNDBGCCMD pgmR3CmdError;
686	static FNDBGCCMD pgmR3CmdSync;
687	static FNDBGCCMD pgmR3CmdSyncAlways;
688	# ifdef VBOX_STRICT
689	static FNDBGCCMD pgmR3CmdAssertCR3;
690	# endif
691	static FNDBGCCMD pgmR3CmdPhysToFile;
692	#endif
693
694
695	/*********************************************************************************************************************************
696	* Global Variables *
697	*********************************************************************************************************************************/
698	#ifdef VBOX_WITH_DEBUGGER
699	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
700	static const DBGCVARDESC g_aPgmErrorArgs[] =
701	{
702	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
703	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
704	};
705
706	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
707	{
708	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
709	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
710	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
711	};
712
713	# ifdef DEBUG_sandervl
714	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
715	{
716	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
717	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
718	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
719	};
720	# endif
721
722	/** Command descriptors. */
723	static const DBGCCMD g_aCmds[] =
724	{
725	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
726	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
727	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
728	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
729	# ifdef VBOX_STRICT
730	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
731	# ifdef VBOX_WITH_PAGE_SHARING
732	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
733	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
734	# endif
735	# endif
736	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
737	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
738	};
739	#endif
740
741
742
743
744	/*
745	* Shadow - 32-bit mode
746	*/
747	#define PGM_SHW_TYPE PGM_TYPE_32BIT
748	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
749	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
750	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
751	#include "PGMShw.h"
752
753	/* Guest - real mode */
754	#define PGM_GST_TYPE PGM_TYPE_REAL
755	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
756	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
757	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
758	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
759	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
760	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
761	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
762	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
763	#include "PGMBth.h"
764	#include "PGMGstDefs.h"
765	#include "PGMGst.h"
766	#undef BTH_PGMPOOLKIND_PT_FOR_PT
767	#undef BTH_PGMPOOLKIND_ROOT
768	#undef PGM_BTH_NAME
769	#undef PGM_BTH_NAME_RC_STR
770	#undef PGM_BTH_NAME_R0_STR
771	#undef PGM_GST_TYPE
772	#undef PGM_GST_NAME
773	#undef PGM_GST_NAME_RC_STR
774	#undef PGM_GST_NAME_R0_STR
775
776	/* Guest - protected mode */
777	#define PGM_GST_TYPE PGM_TYPE_PROT
778	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
779	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
780	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
781	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
782	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
783	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
784	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
785	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
786	#include "PGMBth.h"
787	#include "PGMGstDefs.h"
788	#include "PGMGst.h"
789	#undef BTH_PGMPOOLKIND_PT_FOR_PT
790	#undef BTH_PGMPOOLKIND_ROOT
791	#undef PGM_BTH_NAME
792	#undef PGM_BTH_NAME_RC_STR
793	#undef PGM_BTH_NAME_R0_STR
794	#undef PGM_GST_TYPE
795	#undef PGM_GST_NAME
796	#undef PGM_GST_NAME_RC_STR
797	#undef PGM_GST_NAME_R0_STR
798
799	/* Guest - 32-bit mode */
800	#define PGM_GST_TYPE PGM_TYPE_32BIT
801	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
802	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
803	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
804	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
805	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
806	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
807	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
808	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
809	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
810	#include "PGMBth.h"
811	#include "PGMGstDefs.h"
812	#include "PGMGst.h"
813	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
814	#undef BTH_PGMPOOLKIND_PT_FOR_PT
815	#undef BTH_PGMPOOLKIND_ROOT
816	#undef PGM_BTH_NAME
817	#undef PGM_BTH_NAME_RC_STR
818	#undef PGM_BTH_NAME_R0_STR
819	#undef PGM_GST_TYPE
820	#undef PGM_GST_NAME
821	#undef PGM_GST_NAME_RC_STR
822	#undef PGM_GST_NAME_R0_STR
823
824	#undef PGM_SHW_TYPE
825	#undef PGM_SHW_NAME
826	#undef PGM_SHW_NAME_RC_STR
827	#undef PGM_SHW_NAME_R0_STR
828
829
830	/*
831	* Shadow - PAE mode
832	*/
833	#define PGM_SHW_TYPE PGM_TYPE_PAE
834	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
835	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
836	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
837	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
838	#include "PGMShw.h"
839
840	/* Guest - real mode */
841	#define PGM_GST_TYPE PGM_TYPE_REAL
842	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
843	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
844	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
845	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
846	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
847	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
848	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
849	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
850	#include "PGMGstDefs.h"
851	#include "PGMBth.h"
852	#undef BTH_PGMPOOLKIND_PT_FOR_PT
853	#undef BTH_PGMPOOLKIND_ROOT
854	#undef PGM_BTH_NAME
855	#undef PGM_BTH_NAME_RC_STR
856	#undef PGM_BTH_NAME_R0_STR
857	#undef PGM_GST_TYPE
858	#undef PGM_GST_NAME
859	#undef PGM_GST_NAME_RC_STR
860	#undef PGM_GST_NAME_R0_STR
861
862	/* Guest - protected mode */
863	#define PGM_GST_TYPE PGM_TYPE_PROT
864	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
865	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
866	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
867	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
868	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
869	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
870	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
871	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
872	#include "PGMGstDefs.h"
873	#include "PGMBth.h"
874	#undef BTH_PGMPOOLKIND_PT_FOR_PT
875	#undef BTH_PGMPOOLKIND_ROOT
876	#undef PGM_BTH_NAME
877	#undef PGM_BTH_NAME_RC_STR
878	#undef PGM_BTH_NAME_R0_STR
879	#undef PGM_GST_TYPE
880	#undef PGM_GST_NAME
881	#undef PGM_GST_NAME_RC_STR
882	#undef PGM_GST_NAME_R0_STR
883
884	/* Guest - 32-bit mode */
885	#define PGM_GST_TYPE PGM_TYPE_32BIT
886	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
887	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
888	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
889	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
890	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
891	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
892	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
893	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
894	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
895	#include "PGMGstDefs.h"
896	#include "PGMBth.h"
897	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
898	#undef BTH_PGMPOOLKIND_PT_FOR_PT
899	#undef BTH_PGMPOOLKIND_ROOT
900	#undef PGM_BTH_NAME
901	#undef PGM_BTH_NAME_RC_STR
902	#undef PGM_BTH_NAME_R0_STR
903	#undef PGM_GST_TYPE
904	#undef PGM_GST_NAME
905	#undef PGM_GST_NAME_RC_STR
906	#undef PGM_GST_NAME_R0_STR
907
908	/* Guest - PAE mode */
909	#define PGM_GST_TYPE PGM_TYPE_PAE
910	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
911	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
912	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
913	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
914	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
915	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
916	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
917	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
918	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
919	#include "PGMBth.h"
920	#include "PGMGstDefs.h"
921	#include "PGMGst.h"
922	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
923	#undef BTH_PGMPOOLKIND_PT_FOR_PT
924	#undef BTH_PGMPOOLKIND_ROOT
925	#undef PGM_BTH_NAME
926	#undef PGM_BTH_NAME_RC_STR
927	#undef PGM_BTH_NAME_R0_STR
928	#undef PGM_GST_TYPE
929	#undef PGM_GST_NAME
930	#undef PGM_GST_NAME_RC_STR
931	#undef PGM_GST_NAME_R0_STR
932
933	#undef PGM_SHW_TYPE
934	#undef PGM_SHW_NAME
935	#undef PGM_SHW_NAME_RC_STR
936	#undef PGM_SHW_NAME_R0_STR
937
938
939	/*
940	* Shadow - AMD64 mode
941	*/
942	#define PGM_SHW_TYPE PGM_TYPE_AMD64
943	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
944	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
945	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
946	#include "PGMShw.h"
947
948	#ifdef VBOX_WITH_64_BITS_GUESTS
949	/* Guest - AMD64 mode */
950	# define PGM_GST_TYPE PGM_TYPE_AMD64
951	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
952	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
953	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
954	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
955	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
956	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
957	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
958	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
959	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
960	# include "PGMBth.h"
961	# include "PGMGstDefs.h"
962	# include "PGMGst.h"
963	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
964	# undef BTH_PGMPOOLKIND_PT_FOR_PT
965	# undef BTH_PGMPOOLKIND_ROOT
966	# undef PGM_BTH_NAME
967	# undef PGM_BTH_NAME_RC_STR
968	# undef PGM_BTH_NAME_R0_STR
969	# undef PGM_GST_TYPE
970	# undef PGM_GST_NAME
971	# undef PGM_GST_NAME_RC_STR
972	# undef PGM_GST_NAME_R0_STR
973	#endif /* VBOX_WITH_64_BITS_GUESTS */
974
975	#undef PGM_SHW_TYPE
976	#undef PGM_SHW_NAME
977	#undef PGM_SHW_NAME_RC_STR
978	#undef PGM_SHW_NAME_R0_STR
979
980
981	/*
982	* Shadow - 32-bit nested paging mode
983	*/
984	#define PGM_SHW_TYPE PGM_TYPE_NESTED_32BIT
985	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_32BIT(name)
986	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_32BIT_STR(name)
987	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_32BIT_STR(name)
988	#include "PGMShw.h"
989
990	/* Guest - real mode */
991	#define PGM_GST_TYPE PGM_TYPE_REAL
992	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
993	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
994	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
995	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_REAL(name)
996	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name)
997	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name)
998	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
999	#include "PGMGstDefs.h"
1000	#include "PGMBth.h"
1001	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1002	#undef PGM_BTH_NAME
1003	#undef PGM_BTH_NAME_RC_STR
1004	#undef PGM_BTH_NAME_R0_STR
1005	#undef PGM_GST_TYPE
1006	#undef PGM_GST_NAME
1007	#undef PGM_GST_NAME_RC_STR
1008	#undef PGM_GST_NAME_R0_STR
1009
1010	/* Guest - protected mode */
1011	#define PGM_GST_TYPE PGM_TYPE_PROT
1012	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1013	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1014	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1015	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PROT(name)
1016	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name)
1017	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name)
1018	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1019	#include "PGMGstDefs.h"
1020	#include "PGMBth.h"
1021	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1022	#undef PGM_BTH_NAME
1023	#undef PGM_BTH_NAME_RC_STR
1024	#undef PGM_BTH_NAME_R0_STR
1025	#undef PGM_GST_TYPE
1026	#undef PGM_GST_NAME
1027	#undef PGM_GST_NAME_RC_STR
1028	#undef PGM_GST_NAME_R0_STR
1029
1030	/* Guest - 32-bit mode */
1031	#define PGM_GST_TYPE PGM_TYPE_32BIT
1032	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1033	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1034	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1035	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_32BIT(name)
1036	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name)
1037	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name)
1038	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1039	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1040	#include "PGMGstDefs.h"
1041	#include "PGMBth.h"
1042	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1043	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1044	#undef PGM_BTH_NAME
1045	#undef PGM_BTH_NAME_RC_STR
1046	#undef PGM_BTH_NAME_R0_STR
1047	#undef PGM_GST_TYPE
1048	#undef PGM_GST_NAME
1049	#undef PGM_GST_NAME_RC_STR
1050	#undef PGM_GST_NAME_R0_STR
1051
1052	/* Guest - PAE mode */
1053	#define PGM_GST_TYPE PGM_TYPE_PAE
1054	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1055	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1056	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1057	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PAE(name)
1058	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name)
1059	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name)
1060	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1061	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1062	#include "PGMGstDefs.h"
1063	#include "PGMBth.h"
1064	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1065	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1066	#undef PGM_BTH_NAME
1067	#undef PGM_BTH_NAME_RC_STR
1068	#undef PGM_BTH_NAME_R0_STR
1069	#undef PGM_GST_TYPE
1070	#undef PGM_GST_NAME
1071	#undef PGM_GST_NAME_RC_STR
1072	#undef PGM_GST_NAME_R0_STR
1073
1074	#ifdef VBOX_WITH_64_BITS_GUESTS
1075	/* Guest - AMD64 mode */
1076	# define PGM_GST_TYPE PGM_TYPE_AMD64
1077	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1078	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1079	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1080	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_AMD64(name)
1081	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name)
1082	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name)
1083	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1084	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1085	# include "PGMGstDefs.h"
1086	# include "PGMBth.h"
1087	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1088	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1089	# undef PGM_BTH_NAME
1090	# undef PGM_BTH_NAME_RC_STR
1091	# undef PGM_BTH_NAME_R0_STR
1092	# undef PGM_GST_TYPE
1093	# undef PGM_GST_NAME
1094	# undef PGM_GST_NAME_RC_STR
1095	# undef PGM_GST_NAME_R0_STR
1096	#endif /* VBOX_WITH_64_BITS_GUESTS */
1097
1098	#undef PGM_SHW_TYPE
1099	#undef PGM_SHW_NAME
1100	#undef PGM_SHW_NAME_RC_STR
1101	#undef PGM_SHW_NAME_R0_STR
1102
1103
1104	/*
1105	* Shadow - PAE nested paging mode
1106	*/
1107	#define PGM_SHW_TYPE PGM_TYPE_NESTED_PAE
1108	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_PAE(name)
1109	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_PAE_STR(name)
1110	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_PAE_STR(name)
1111	#include "PGMShw.h"
1112
1113	/* Guest - real mode */
1114	#define PGM_GST_TYPE PGM_TYPE_REAL
1115	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1116	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1117	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1118	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_REAL(name)
1119	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name)
1120	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name)
1121	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1122	#include "PGMGstDefs.h"
1123	#include "PGMBth.h"
1124	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1125	#undef PGM_BTH_NAME
1126	#undef PGM_BTH_NAME_RC_STR
1127	#undef PGM_BTH_NAME_R0_STR
1128	#undef PGM_GST_TYPE
1129	#undef PGM_GST_NAME
1130	#undef PGM_GST_NAME_RC_STR
1131	#undef PGM_GST_NAME_R0_STR
1132
1133	/* Guest - protected mode */
1134	#define PGM_GST_TYPE PGM_TYPE_PROT
1135	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1136	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1137	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1138	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PROT(name)
1139	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name)
1140	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name)
1141	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1142	#include "PGMGstDefs.h"
1143	#include "PGMBth.h"
1144	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1145	#undef PGM_BTH_NAME
1146	#undef PGM_BTH_NAME_RC_STR
1147	#undef PGM_BTH_NAME_R0_STR
1148	#undef PGM_GST_TYPE
1149	#undef PGM_GST_NAME
1150	#undef PGM_GST_NAME_RC_STR
1151	#undef PGM_GST_NAME_R0_STR
1152
1153	/* Guest - 32-bit mode */
1154	#define PGM_GST_TYPE PGM_TYPE_32BIT
1155	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1156	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1157	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1158	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_32BIT(name)
1159	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name)
1160	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name)
1161	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1162	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1163	#include "PGMGstDefs.h"
1164	#include "PGMBth.h"
1165	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1166	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1167	#undef PGM_BTH_NAME
1168	#undef PGM_BTH_NAME_RC_STR
1169	#undef PGM_BTH_NAME_R0_STR
1170	#undef PGM_GST_TYPE
1171	#undef PGM_GST_NAME
1172	#undef PGM_GST_NAME_RC_STR
1173	#undef PGM_GST_NAME_R0_STR
1174
1175	/* Guest - PAE mode */
1176	#define PGM_GST_TYPE PGM_TYPE_PAE
1177	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1178	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1179	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1180	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PAE(name)
1181	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name)
1182	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name)
1183	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1184	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1185	#include "PGMGstDefs.h"
1186	#include "PGMBth.h"
1187	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1188	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1189	#undef PGM_BTH_NAME
1190	#undef PGM_BTH_NAME_RC_STR
1191	#undef PGM_BTH_NAME_R0_STR
1192	#undef PGM_GST_TYPE
1193	#undef PGM_GST_NAME
1194	#undef PGM_GST_NAME_RC_STR
1195	#undef PGM_GST_NAME_R0_STR
1196
1197	#ifdef VBOX_WITH_64_BITS_GUESTS
1198	/* Guest - AMD64 mode */
1199	# define PGM_GST_TYPE PGM_TYPE_AMD64
1200	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1201	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1202	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1203	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_AMD64(name)
1204	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name)
1205	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name)
1206	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1207	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1208	# include "PGMGstDefs.h"
1209	# include "PGMBth.h"
1210	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1211	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1212	# undef PGM_BTH_NAME
1213	# undef PGM_BTH_NAME_RC_STR
1214	# undef PGM_BTH_NAME_R0_STR
1215	# undef PGM_GST_TYPE
1216	# undef PGM_GST_NAME
1217	# undef PGM_GST_NAME_RC_STR
1218	# undef PGM_GST_NAME_R0_STR
1219	#endif /* VBOX_WITH_64_BITS_GUESTS */
1220
1221	#undef PGM_SHW_TYPE
1222	#undef PGM_SHW_NAME
1223	#undef PGM_SHW_NAME_RC_STR
1224	#undef PGM_SHW_NAME_R0_STR
1225
1226
1227	/*
1228	* Shadow - AMD64 nested paging mode
1229	*/
1230	#define PGM_SHW_TYPE PGM_TYPE_NESTED_AMD64
1231	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_AMD64(name)
1232	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_AMD64_STR(name)
1233	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_AMD64_STR(name)
1234	#include "PGMShw.h"
1235
1236	/* Guest - real mode */
1237	#define PGM_GST_TYPE PGM_TYPE_REAL
1238	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1239	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1240	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1241	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_REAL(name)
1242	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name)
1243	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name)
1244	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1245	#include "PGMGstDefs.h"
1246	#include "PGMBth.h"
1247	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1248	#undef PGM_BTH_NAME
1249	#undef PGM_BTH_NAME_RC_STR
1250	#undef PGM_BTH_NAME_R0_STR
1251	#undef PGM_GST_TYPE
1252	#undef PGM_GST_NAME
1253	#undef PGM_GST_NAME_RC_STR
1254	#undef PGM_GST_NAME_R0_STR
1255
1256	/* Guest - protected mode */
1257	#define PGM_GST_TYPE PGM_TYPE_PROT
1258	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1259	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1260	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1261	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PROT(name)
1262	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name)
1263	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name)
1264	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1265	#include "PGMGstDefs.h"
1266	#include "PGMBth.h"
1267	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1268	#undef PGM_BTH_NAME
1269	#undef PGM_BTH_NAME_RC_STR
1270	#undef PGM_BTH_NAME_R0_STR
1271	#undef PGM_GST_TYPE
1272	#undef PGM_GST_NAME
1273	#undef PGM_GST_NAME_RC_STR
1274	#undef PGM_GST_NAME_R0_STR
1275
1276	/* Guest - 32-bit mode */
1277	#define PGM_GST_TYPE PGM_TYPE_32BIT
1278	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1279	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1280	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1281	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_32BIT(name)
1282	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name)
1283	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name)
1284	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1285	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1286	#include "PGMGstDefs.h"
1287	#include "PGMBth.h"
1288	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1289	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1290	#undef PGM_BTH_NAME
1291	#undef PGM_BTH_NAME_RC_STR
1292	#undef PGM_BTH_NAME_R0_STR
1293	#undef PGM_GST_TYPE
1294	#undef PGM_GST_NAME
1295	#undef PGM_GST_NAME_RC_STR
1296	#undef PGM_GST_NAME_R0_STR
1297
1298	/* Guest - PAE mode */
1299	#define PGM_GST_TYPE PGM_TYPE_PAE
1300	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1301	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1302	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1303	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PAE(name)
1304	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name)
1305	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name)
1306	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1307	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1308	#include "PGMGstDefs.h"
1309	#include "PGMBth.h"
1310	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1311	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1312	#undef PGM_BTH_NAME
1313	#undef PGM_BTH_NAME_RC_STR
1314	#undef PGM_BTH_NAME_R0_STR
1315	#undef PGM_GST_TYPE
1316	#undef PGM_GST_NAME
1317	#undef PGM_GST_NAME_RC_STR
1318	#undef PGM_GST_NAME_R0_STR
1319
1320	#ifdef VBOX_WITH_64_BITS_GUESTS
1321	/* Guest - AMD64 mode */
1322	# define PGM_GST_TYPE PGM_TYPE_AMD64
1323	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1324	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1325	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1326	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_AMD64(name)
1327	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name)
1328	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name)
1329	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1330	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1331	# include "PGMGstDefs.h"
1332	# include "PGMBth.h"
1333	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1334	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1335	# undef PGM_BTH_NAME
1336	# undef PGM_BTH_NAME_RC_STR
1337	# undef PGM_BTH_NAME_R0_STR
1338	# undef PGM_GST_TYPE
1339	# undef PGM_GST_NAME
1340	# undef PGM_GST_NAME_RC_STR
1341	# undef PGM_GST_NAME_R0_STR
1342	#endif /* VBOX_WITH_64_BITS_GUESTS */
1343
1344	#undef PGM_SHW_TYPE
1345	#undef PGM_SHW_NAME
1346	#undef PGM_SHW_NAME_RC_STR
1347	#undef PGM_SHW_NAME_R0_STR
1348
1349
1350	/*
1351	* Shadow - EPT
1352	*/
1353	#define PGM_SHW_TYPE PGM_TYPE_EPT
1354	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1355	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1356	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1357	#include "PGMShw.h"
1358
1359	/* Guest - real mode */
1360	#define PGM_GST_TYPE PGM_TYPE_REAL
1361	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1362	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1363	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1364	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1365	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1366	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1367	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1368	#include "PGMGstDefs.h"
1369	#include "PGMBth.h"
1370	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1371	#undef PGM_BTH_NAME
1372	#undef PGM_BTH_NAME_RC_STR
1373	#undef PGM_BTH_NAME_R0_STR
1374	#undef PGM_GST_TYPE
1375	#undef PGM_GST_NAME
1376	#undef PGM_GST_NAME_RC_STR
1377	#undef PGM_GST_NAME_R0_STR
1378
1379	/* Guest - protected mode */
1380	#define PGM_GST_TYPE PGM_TYPE_PROT
1381	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1382	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1383	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1384	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1385	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1386	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1387	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1388	#include "PGMGstDefs.h"
1389	#include "PGMBth.h"
1390	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1391	#undef PGM_BTH_NAME
1392	#undef PGM_BTH_NAME_RC_STR
1393	#undef PGM_BTH_NAME_R0_STR
1394	#undef PGM_GST_TYPE
1395	#undef PGM_GST_NAME
1396	#undef PGM_GST_NAME_RC_STR
1397	#undef PGM_GST_NAME_R0_STR
1398
1399	/* Guest - 32-bit mode */
1400	#define PGM_GST_TYPE PGM_TYPE_32BIT
1401	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1402	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1403	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1404	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1405	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1406	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1407	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1408	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1409	#include "PGMGstDefs.h"
1410	#include "PGMBth.h"
1411	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1412	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1413	#undef PGM_BTH_NAME
1414	#undef PGM_BTH_NAME_RC_STR
1415	#undef PGM_BTH_NAME_R0_STR
1416	#undef PGM_GST_TYPE
1417	#undef PGM_GST_NAME
1418	#undef PGM_GST_NAME_RC_STR
1419	#undef PGM_GST_NAME_R0_STR
1420
1421	/* Guest - PAE mode */
1422	#define PGM_GST_TYPE PGM_TYPE_PAE
1423	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1424	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1425	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1426	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1427	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1428	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1429	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1430	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1431	#include "PGMGstDefs.h"
1432	#include "PGMBth.h"
1433	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1434	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1435	#undef PGM_BTH_NAME
1436	#undef PGM_BTH_NAME_RC_STR
1437	#undef PGM_BTH_NAME_R0_STR
1438	#undef PGM_GST_TYPE
1439	#undef PGM_GST_NAME
1440	#undef PGM_GST_NAME_RC_STR
1441	#undef PGM_GST_NAME_R0_STR
1442
1443	#ifdef VBOX_WITH_64_BITS_GUESTS
1444	/* Guest - AMD64 mode */
1445	# define PGM_GST_TYPE PGM_TYPE_AMD64
1446	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1447	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1448	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1449	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1450	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1451	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1452	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1453	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1454	# include "PGMGstDefs.h"
1455	# include "PGMBth.h"
1456	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1457	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1458	# undef PGM_BTH_NAME
1459	# undef PGM_BTH_NAME_RC_STR
1460	# undef PGM_BTH_NAME_R0_STR
1461	# undef PGM_GST_TYPE
1462	# undef PGM_GST_NAME
1463	# undef PGM_GST_NAME_RC_STR
1464	# undef PGM_GST_NAME_R0_STR
1465	#endif /* VBOX_WITH_64_BITS_GUESTS */
1466
1467	#undef PGM_SHW_TYPE
1468	#undef PGM_SHW_NAME
1469	#undef PGM_SHW_NAME_RC_STR
1470	#undef PGM_SHW_NAME_R0_STR
1471
1472
1473
1474	/**
1475	* Initiates the paging of VM.
1476	*
1477	* @returns VBox status code.
1478	* @param pVM The cross context VM structure.
1479	*/
1480	VMMR3DECL(int) PGMR3Init(PVM pVM)
1481	{
1482	LogFlow(("PGMR3Init:\n"));
1483	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1484	int rc;
1485
1486	/*
1487	* Assert alignment and sizes.
1488	*/
1489	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1490	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1491	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1492
1493	/*
1494	* Init the structure.
1495	*/
1496	pVM->pgm.s.offVM = RT_UOFFSETOF(VM, pgm.s);
1497	pVM->pgm.s.offVCpuPGM = RT_UOFFSETOF(VMCPU, pgm.s);
1498	/pVM->pgm.s.fRestoreRomPagesAtReset = false;/
1499
1500	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1501	{
1502	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1503	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1504	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1505	}
1506
1507	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1508	{
1509	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1510	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1511	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1512	}
1513
1514	/* Init the per-CPU part. */
1515	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1516	{
1517	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1518	PPGMCPU pPGM = &pVCpu->pgm.s;
1519
1520	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1521	pPGM->offVCpu = RT_UOFFSETOF(VMCPU, pgm.s);
1522	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1523
1524	pPGM->enmShadowMode = PGMMODE_INVALID;
1525	pPGM->enmGuestMode = PGMMODE_INVALID;
1526	pPGM->idxGuestModeData = UINT8_MAX;
1527	pPGM->idxShadowModeData = UINT8_MAX;
1528	pPGM->idxBothModeData = UINT8_MAX;
1529
1530	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1531
1532	pPGM->pGst32BitPdR3 = NULL;
1533	pPGM->pGstPaePdptR3 = NULL;
1534	pPGM->pGstAmd64Pml4R3 = NULL;
1535	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1536	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1537	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1538	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1539	#endif
1540	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1541	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1542	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1543	{
1544	pPGM->apGstPaePDsR3[i] = NULL;
1545	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1546	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1547	#endif
1548	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1549	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1550	pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1551	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1552	}
1553
1554	pPGM->fA20Enabled = true;
1555	pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
1556	}
1557
1558	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1559	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1560	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1561
1562	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1563	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1564	true
1565	#else
1566	false
1567	#endif
1568	);
1569	AssertLogRelRCReturn(rc, rc);
1570
1571	#if HC_ARCH_BITS == 32
1572	# ifdef RT_OS_DARWIN
1573	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1574	# else
1575	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1576	# endif
1577	#else
1578	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1579	#endif
1580	AssertLogRelRCReturn(rc, rc);
1581	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1582	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1583
1584	/*
1585	* Get the configured RAM size - to estimate saved state size.
1586	*/
1587	uint64_t cbRam;
1588	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1589	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1590	cbRam = 0;
1591	else if (RT_SUCCESS(rc))
1592	{
1593	if (cbRam < PAGE_SIZE)
1594	cbRam = 0;
1595	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1596	}
1597	else
1598	{
1599	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1600	return rc;
1601	}
1602
1603	/*
1604	* Check for PCI pass-through and other configurables.
1605	*/
1606	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1607	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1608	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1609
1610	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "PageFusionAllowed", &pVM->pgm.s.fPageFusionAllowed, false);
1611	AssertLogRelRCReturn(rc, rc);
1612
1613	/** @cfgm{/PGM/ZeroRamPagesOnReset, boolean, true}
1614	* Whether to clear RAM pages on (hard) reset. */
1615	rc = CFGMR3QueryBoolDef(pCfgPGM, "ZeroRamPagesOnReset", &pVM->pgm.s.fZeroRamPagesOnReset, true);
1616	AssertLogRelRCReturn(rc, rc);
1617
1618	#ifdef VBOX_WITH_STATISTICS
1619	/*
1620	* Allocate memory for the statistics before someone tries to use them.
1621	*/
1622	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1623	void *pv;
1624	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1625	AssertRCReturn(rc, rc);
1626
1627	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1628	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1629	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1630	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1631
1632	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1633	{
1634	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1635	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1636	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1637
1638	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1639	}
1640	#endif /* VBOX_WITH_STATISTICS */
1641
1642	/*
1643	* Register callbacks, string formatters and the saved state data unit.
1644	*/
1645	#ifdef VBOX_STRICT
1646	VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1647	#endif
1648	PGMRegisterStringFormatTypes();
1649
1650	rc = pgmR3InitSavedState(pVM, cbRam);
1651	if (RT_FAILURE(rc))
1652	return rc;
1653
1654	/*
1655	* Initialize the PGM critical section and flush the phys TLBs
1656	*/
1657	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1658	AssertRCReturn(rc, rc);
1659
1660	PGMR3PhysChunkInvalidateTLB(pVM);
1661	pgmPhysInvalidatePageMapTLB(pVM);
1662
1663	/*
1664	* For the time being we sport a full set of handy pages in addition to the base
1665	* memory to simplify things.
1666	*/
1667	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1668	AssertRCReturn(rc, rc);
1669
1670	/*
1671	* Trees
1672	*/
1673	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1674	if (RT_SUCCESS(rc))
1675	{
1676	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1677	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1678	}
1679
1680	/*
1681	* Allocate the zero page.
1682	*/
1683	if (RT_SUCCESS(rc))
1684	{
1685	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1686	if (RT_SUCCESS(rc))
1687	{
1688	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1689	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1690	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1691	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1692	}
1693	}
1694
1695	/*
1696	* Allocate the invalid MMIO page.
1697	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1698	*/
1699	if (RT_SUCCESS(rc))
1700	{
1701	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1702	if (RT_SUCCESS(rc))
1703	{
1704	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1705	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1706	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1707	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1708	}
1709	}
1710
1711	/*
1712	* Register the physical access handler protecting ROMs.
1713	*/
1714	if (RT_SUCCESS(rc))
1715	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE,
1716	pgmPhysRomWriteHandler,
1717	NULL, NULL, "pgmPhysRomWritePfHandler",
1718	NULL, NULL, "pgmPhysRomWritePfHandler",
1719	"ROM write protection",
1720	&pVM->pgm.s.hRomPhysHandlerType);
1721
1722	/*
1723	* Init the paging.
1724	*/
1725	if (RT_SUCCESS(rc))
1726	rc = pgmR3InitPaging(pVM);
1727
1728	/*
1729	* Init the page pool.
1730	*/
1731	if (RT_SUCCESS(rc))
1732	rc = pgmR3PoolInit(pVM);
1733
1734	if (RT_SUCCESS(rc))
1735	{
1736	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1737	{
1738	PVMCPU pVCpu = &pVM->aCpus[i];
1739	rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1740	if (RT_FAILURE(rc))
1741	break;
1742	}
1743	}
1744
1745	if (RT_SUCCESS(rc))
1746	{
1747	/*
1748	* Info & statistics
1749	*/
1750	DBGFR3InfoRegisterInternalEx(pVM, "mode",
1751	"Shows the current paging mode. "
1752	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1753	pgmR3InfoMode,
1754	DBGFINFO_FLAGS_ALL_EMTS);
1755	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1756	"Dumps all the entries in the top level paging table. No arguments.",
1757	pgmR3InfoCr3);
1758	DBGFR3InfoRegisterInternal(pVM, "phys",
1759	"Dumps all the physical address ranges. Pass 'verbose' to get more details.",
1760	pgmR3PhysInfo);
1761	DBGFR3InfoRegisterInternal(pVM, "handlers",
1762	"Dumps physical, virtual and hyper virtual handlers. "
1763	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1764	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1765	pgmR3InfoHandlers);
1766	DBGFR3InfoRegisterInternal(pVM, "mappings",
1767	"Dumps guest mappings.",
1768	pgmR3MapInfo);
1769
1770	pgmR3InitStats(pVM);
1771
1772	#ifdef VBOX_WITH_DEBUGGER
1773	/*
1774	* Debugger commands.
1775	*/
1776	static bool s_fRegisteredCmds = false;
1777	if (!s_fRegisteredCmds)
1778	{
1779	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1780	if (RT_SUCCESS(rc2))
1781	s_fRegisteredCmds = true;
1782	}
1783	#endif
1784	return VINF_SUCCESS;
1785	}
1786
1787	/* Almost no cleanup necessary, MM frees all memory. */
1788	PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1789
1790	return rc;
1791	}
1792
1793
1794	/**
1795	* Init paging.
1796	*
1797	* Since we need to check what mode the host is operating in before we can choose
1798	* the right paging functions for the host we have to delay this until R0 has
1799	* been initialized.
1800	*
1801	* @returns VBox status code.
1802	* @param pVM The cross context VM structure.
1803	*/
1804	static int pgmR3InitPaging(PVM pVM)
1805	{
1806	/*
1807	* Force a recalculation of modes and switcher so everyone gets notified.
1808	*/
1809	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1810	{
1811	PVMCPU pVCpu = &pVM->aCpus[i];
1812
1813	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1814	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1815	pVCpu->pgm.s.idxGuestModeData = UINT8_MAX;
1816	pVCpu->pgm.s.idxShadowModeData = UINT8_MAX;
1817	pVCpu->pgm.s.idxBothModeData = UINT8_MAX;
1818	}
1819
1820	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1821
1822	/*
1823	* Allocate static mapping space for whatever the cr3 register
1824	* points to and in the case of PAE mode to the 4 PDs.
1825	*/
1826	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1827	if (RT_FAILURE(rc))
1828	{
1829	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1830	return rc;
1831	}
1832	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1833
1834	/*
1835	* Allocate pages for the three possible intermediate contexts
1836	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1837	* for the sake of simplicity. The AMD64 uses the PAE for the
1838	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1839	*
1840	* We assume that two page tables will be enought for the core code
1841	* mappings (HC virtual and identity).
1842	*/
1843	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1844	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1845	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1846	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1847	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1848	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1849	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1850	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1851	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1852	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1853	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1854	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1855
1856	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1857	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1858	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1859	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1860	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1861	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1862
1863	/*
1864	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1865	*/
1866	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1867	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1868	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1869
1870	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1871	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1872
1873	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1874	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1875	{
1876	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1877	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1878	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1879	}
1880
1881	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1882	{
1883	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1884	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1885	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1886	}
1887
1888	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1889	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1890	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1891	\| HCPhysInterPaePDPT64;
1892
1893	/*
1894	* Initialize paging workers and mode from current host mode
1895	* and the guest running in real mode.
1896	*/
1897	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1898	switch (pVM->pgm.s.enmHostMode)
1899	{
1900	case SUPPAGINGMODE_32_BIT:
1901	case SUPPAGINGMODE_32_BIT_GLOBAL:
1902	case SUPPAGINGMODE_PAE:
1903	case SUPPAGINGMODE_PAE_GLOBAL:
1904	case SUPPAGINGMODE_PAE_NX:
1905	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1906	break;
1907
1908	case SUPPAGINGMODE_AMD64:
1909	case SUPPAGINGMODE_AMD64_GLOBAL:
1910	case SUPPAGINGMODE_AMD64_NX:
1911	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1912	if (ARCH_BITS != 64)
1913	{
1914	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1915	LogRel(("PGM: Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1916	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1917	}
1918	break;
1919	default:
1920	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1921	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1922	}
1923
1924	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1925	#if HC_ARCH_BITS == 64
1926	LogRel(("PGM: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1927	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1928	LogRel(("PGM: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1929	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1930	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1931	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1932	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1933	#endif
1934
1935	/*
1936	* Log the host paging mode. It may come in handy.
1937	*/
1938	const char *pszHostMode;
1939	switch (pVM->pgm.s.enmHostMode)
1940	{
1941	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1942	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1943	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1944	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1945	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1946	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1947	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1948	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1949	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1950	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1951	default: pszHostMode = "???"; break;
1952	}
1953	LogRel(("PGM: Host paging mode: %s\n", pszHostMode));
1954
1955	return VINF_SUCCESS;
1956	}
1957
1958
1959	/**
1960	* Init statistics
1961	* @returns VBox status code.
1962	*/
1963	static int pgmR3InitStats(PVM pVM)
1964	{
1965	PPGM pPGM = &pVM->pgm.s;
1966	int rc;
1967
1968	/*
1969	* Release statistics.
1970	*/
1971	/* Common - misc variables */
1972	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1973	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1974	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1975	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1976	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1977	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1978	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1979	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1980	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1981	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1982	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1983	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1984	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1985	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1986	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1987	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1988	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1989	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1990	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1991
1992	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1993	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1994	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1995
1996	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1997
1998	/* Live save */
1999	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
2000	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
2001	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
2002	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
2003	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
2004	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
2005	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
2006	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
2007	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
2008	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
2009	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
2010	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
2011	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
2012	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
2013	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
2014	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
2015	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
2016	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
2017
2018	#ifdef VBOX_WITH_STATISTICS
2019
2020	# define PGM_REG_COUNTER(a, b, c) \
2021	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
2022	AssertRC(rc);
2023
2024	# define PGM_REG_COUNTER_BYTES(a, b, c) \
2025	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
2026	AssertRC(rc);
2027
2028	# define PGM_REG_PROFILE(a, b, c) \
2029	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
2030	AssertRC(rc);
2031
2032	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
2033
2034	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
2035	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
2036	PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
2037	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
2038	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
2039
2040	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
2041	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
2042	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
2043	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
2044	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
2045	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
2046	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
2047	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
2048	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
2049	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
2050
2051	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
2052	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
2053	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
2054	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
2055	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
2056	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
2057
2058	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
2059	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
2060	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
2061	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
2062	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
2063	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
2064	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
2065	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
2066
2067	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
2068	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
2069	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
2070	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
2071
2072	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
2073	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
2074	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
2075	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
2076
2077	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
2078	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
2079	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
2080	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
2081	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
2082	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
2083	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
2084	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
2085
2086	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
2087	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
2088	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
2089	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
2090	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
2091	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
2092
2093	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
2094	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
2095	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
2096	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
2097	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
2098	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
2099	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
2100	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
2101
2102	/* GC only: */
2103	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
2104	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
2105
2106	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
2107	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
2108	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
2109	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
2110	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
2111	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
2112	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
2113	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
2114
2115	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
2116	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
2117	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
2118	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
2119	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
2120	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
2121	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
2122
2123	# undef PGM_REG_COUNTER
2124	# undef PGM_REG_PROFILE
2125	#endif
2126
2127	/*
2128	* Note! The layout below matches the member layout exactly!
2129	*/
2130
2131	/*
2132	* Common - stats
2133	*/
2134	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2135	{
2136	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
2137
2138	#define PGM_REG_COUNTER(a, b, c) \
2139	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
2140	AssertRC(rc);
2141	#define PGM_REG_PROFILE(a, b, c) \
2142	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
2143	AssertRC(rc);
2144
2145	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
2146	PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
2147
2148	#ifdef VBOX_WITH_STATISTICS
2149	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
2150
2151	# if 0 /* rarely useful; leave for debugging. */
2152	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
2153	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
2154	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
2155	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
2156	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
2157	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
2158	# endif
2159	/* R0 only: */
2160	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
2161	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
2162
2163	/* RZ only: */
2164	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
2165	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
2166	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
2167	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
2168	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
2169	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
2170	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
2171	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
2172	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
2173	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
2174	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
2175	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
2176	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
2177	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
2178	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
2179	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
2180	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
2181	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
2182	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsHack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USHack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled.");
2183	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsUnhack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USUnhack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled.");
2184	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
2185	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
2186	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
2187	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
2188	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
2189	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
2190	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
2191	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
2192	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
2193	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
2194	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
2195	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
2196	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
2197	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
2198	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
2199	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
2200	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
2201	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
2202	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
2203	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
2204	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
2205	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
2206	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
2207	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
2208	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
2209	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
2210	#if 0 /* rarely useful; leave for debugging. */
2211	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
2212	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
2213	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
2214	#endif
2215	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
2216	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
2217	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
2218	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
2219	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
2220
2221	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
2222	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
2223	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
2224	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
2225	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
2226	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
2227	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
2228	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
2229	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
2230	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
2231	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
2232	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
2233	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
2234	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
2235	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
2236	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
2237	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
2238	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
2239	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
2240	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
2241	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
2242	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
2243	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
2244	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
2245	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
2246	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
2247	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
2248	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
2249	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
2250	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
2251	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
2252	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
2253	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
2254	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
2255	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
2256	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
2257
2258	/* HC only: */
2259
2260	/* RZ & R3: */
2261	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2262	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2263	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
2264	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2265	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2266	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2267	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2268	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2269	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2270	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2271	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
2272	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2273	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
2274	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
2275	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2276	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2277	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2278	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2279	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2280	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2281	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2282	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2283	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
2284	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2285	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2286	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2287	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
2288	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2289	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2290	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2291	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2292	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2293	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2294	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2295	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSizeChanges, "/PGM/CPU%u/RZ/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
2296	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2297	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2298	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2299	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2300	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2301	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2302	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
2303	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2304	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2305	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2306	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2307	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2308	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2309
2310	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2311	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2312	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
2313	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2314	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2315	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2316	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2317	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2318	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2319	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2320	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
2321	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2322	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
2323	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
2324	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2325	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2326	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2327	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2328	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2329	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2330	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2331	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2332	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2333	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2334	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2335	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2336	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2337	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2338	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2339	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2340	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2341	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2342	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2343	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSizeChanges, "/PGM/CPU%u/R3/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
2344	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2345	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2346	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2347	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2348	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2349	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2350	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2351	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2352	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2353	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2354	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2355	#endif /* VBOX_WITH_STATISTICS */
2356
2357	#undef PGM_REG_PROFILE
2358	#undef PGM_REG_COUNTER
2359
2360	}
2361
2362	return VINF_SUCCESS;
2363	}
2364
2365
2366	/**
2367	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2368	*
2369	* The dynamic mapping area will also be allocated and initialized at this
2370	* time. We could allocate it during PGMR3Init of course, but the mapping
2371	* wouldn't be allocated at that time preventing us from setting up the
2372	* page table entries with the dummy page.
2373	*
2374	* @returns VBox status code.
2375	* @param pVM The cross context VM structure.
2376	*/
2377	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2378	{
2379	RTGCPTR GCPtr;
2380	int rc;
2381
2382	/*
2383	* Reserve space for the dynamic mappings.
2384	*/
2385	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2386	if (RT_SUCCESS(rc))
2387	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2388
2389	if ( RT_SUCCESS(rc)
2390	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2391	{
2392	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2393	if (RT_SUCCESS(rc))
2394	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2395	}
2396	if (RT_SUCCESS(rc))
2397	{
2398	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2399	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2400	}
2401	return rc;
2402	}
2403
2404
2405	/**
2406	* Ring-3 init finalizing.
2407	*
2408	* @returns VBox status code.
2409	* @param pVM The cross context VM structure.
2410	*/
2411	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2412	{
2413	int rc = VERR_IPE_UNINITIALIZED_STATUS; /* (MSC incorrectly thinks it can be usused uninitialized) */
2414
2415	/*
2416	* Reserve space for the dynamic mappings.
2417	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2418	*/
2419	/* get the pointer to the page table entries. */
2420	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2421	AssertRelease(pMapping);
2422	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2423	const unsigned iPT = off >> X86_PD_SHIFT;
2424	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2425	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2426	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2427
2428	/* init cache area */
2429	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2430	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2431	{
2432	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2433	AssertRCReturn(rc, rc);
2434	}
2435
2436	/*
2437	* Determine the max physical address width (MAXPHYADDR) and apply it to
2438	* all the mask members and stuff.
2439	*/
2440	uint32_t cMaxPhysAddrWidth;
2441	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2442	if ( uMaxExtLeaf >= 0x80000008
2443	&& uMaxExtLeaf <= 0x80000fff)
2444	{
2445	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2446	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2447	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2448	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2449	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2450	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2451	}
2452	else
2453	{
2454	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2455	cMaxPhysAddrWidth = 48;
2456	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2457	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2458	}
2459
2460	/** @todo query from CPUM. */
2461	pVM->pgm.s.GCPhysInvAddrMask = 0;
2462	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2463	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2464
2465	/*
2466	* Initialize the invalid paging entry masks, assuming NX is disabled.
2467	*/
2468	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2469	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2470	{
2471	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2472
2473	/** @todo The manuals are not entirely clear whether the physical
2474	* address width is relevant. See table 5-9 in the intel
2475	* manual vs the PDE4M descriptions. Write testcase (NP). */
2476	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2477	\| X86_PDE4M_MBZ_MASK;
2478
2479	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2480	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2481	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2482	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2483
2484	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2485	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2486	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2487	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2488	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2489	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2490
2491	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
2492	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
2493	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
2494	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2495	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
2496	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
2497	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
2498	}
2499
2500	/*
2501	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2502	* Intel only goes up to 36 bits, so we stick to 36 as well.
2503	* Update: More recent intel manuals specifies 40 bits just like AMD.
2504	*/
2505	uint32_t u32Dummy, u32Features;
2506	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2507	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2508	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2509	else
2510	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2511
2512	/*
2513	* Allocate memory if we're supposed to do that.
2514	*/
2515	if (pVM->pgm.s.fRamPreAlloc)
2516	rc = pgmR3PhysRamPreAllocate(pVM);
2517
2518	//pgmLogState(pVM);
2519	LogRel(("PGM: PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2520	return rc;
2521	}
2522
2523
2524	/**
2525	* Init phase completed callback.
2526	*
2527	* @returns VBox status code.
2528	* @param pVM The cross context VM structure.
2529	* @param enmWhat What has been completed.
2530	* @thread EMT(0)
2531	*/
2532	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2533	{
2534	switch (enmWhat)
2535	{
2536	case VMINITCOMPLETED_HM:
2537	#ifdef VBOX_WITH_PCI_PASSTHROUGH
2538	if (pVM->pgm.s.fPciPassthrough)
2539	{
2540	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2541	AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
2542	AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2543
2544	/*
2545	* Report assignments to the IOMMU (hope that's good enough for now).
2546	*/
2547	if (pVM->pgm.s.fPciPassthrough)
2548	{
2549	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2550	AssertRCReturn(rc, rc);
2551	}
2552	}
2553	#else
2554	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2555	#endif
2556	break;
2557
2558	default:
2559	/* shut up gcc */
2560	break;
2561	}
2562
2563	return VINF_SUCCESS;
2564	}
2565
2566
2567	/**
2568	* Applies relocations to data and code managed by this component.
2569	*
2570	* This function will be called at init and whenever the VMM need to relocate it
2571	* self inside the GC.
2572	*
2573	* @param pVM The cross context VM structure.
2574	* @param offDelta Relocation delta relative to old location.
2575	*/
2576	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2577	{
2578	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2579
2580	/*
2581	* Paging stuff.
2582	*/
2583	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2584
2585	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2586	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2587	{
2588	PVMCPU pVCpu = &pVM->aCpus[i];
2589
2590	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
2591	if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
2592	&& g_aPgmShadowModeData[idxShw].pfnRelocate)
2593	g_aPgmShadowModeData[idxShw].pfnRelocate(pVCpu, offDelta);
2594	else
2595	AssertFailed();
2596
2597	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
2598	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
2599	&& g_aPgmGuestModeData[idxGst].pfnRelocate)
2600	g_aPgmGuestModeData[idxGst].pfnRelocate(pVCpu, offDelta);
2601	else
2602	AssertFailed();
2603	}
2604
2605	/*
2606	* Trees.
2607	*/
2608	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2609
2610	/*
2611	* Ram ranges.
2612	*/
2613	if (pVM->pgm.s.pRamRangesXR3)
2614	{
2615	/* Update the pSelfRC pointers and relink them. */
2616	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2617	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2618	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2619	pgmR3PhysRelinkRamRanges(pVM);
2620
2621	/* Flush the RC TLB. */
2622	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2623	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2624	}
2625
2626	/*
2627	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2628	* be mapped and thus not included in the above exercise.
2629	*/
2630	for (PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2631	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2632	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2633
2634	/*
2635	* Update the two page directories with all page table mappings.
2636	* (One or more of them have changed, that's why we're here.)
2637	*/
2638	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2639	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2640	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2641
2642	/* Relocate GC addresses of Page Tables. */
2643	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2644	{
2645	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2646	{
2647	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2648	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2649	}
2650	}
2651
2652	/*
2653	* Dynamic page mapping area.
2654	*/
2655	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2656	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2657	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2658
2659	if (pVM->pgm.s.pRCDynMap)
2660	{
2661	pVM->pgm.s.pRCDynMap += offDelta;
2662	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2663
2664	pDynMap->paPages += offDelta;
2665	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2666
2667	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2668	{
2669	paPages[iPage].pvPage += offDelta;
2670	paPages[iPage].uPte.pLegacy += offDelta;
2671	paPages[iPage].uPte.pPae += offDelta;
2672	}
2673	}
2674
2675	/*
2676	* The Zero page.
2677	*/
2678	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2679	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2680	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| VM_IS_RAW_MODE_ENABLED(pVM));
2681	#else
2682	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2683	#endif
2684
2685	/*
2686	* Physical and virtual handlers.
2687	*/
2688	PGMRELOCHANDLERARGS Args = { offDelta, pVM };
2689	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &Args);
2690	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2691
2692	PPGMPHYSHANDLERTYPEINT pCurPhysType;
2693	RTListOff32ForEach(&pVM->pgm.s.pTreesR3->HeadPhysHandlerTypes, pCurPhysType, PGMPHYSHANDLERTYPEINT, ListNode)
2694	{
2695	if (pCurPhysType->pfnHandlerRC != NIL_RTRCPTR)
2696	pCurPhysType->pfnHandlerRC += offDelta;
2697	if (pCurPhysType->pfnPfHandlerRC != NIL_RTRCPTR)
2698	pCurPhysType->pfnPfHandlerRC += offDelta;
2699	}
2700
2701	#ifdef VBOX_WITH_RAW_MODE
2702	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &Args);
2703	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &Args);
2704
2705	PPGMVIRTHANDLERTYPEINT pCurVirtType;
2706	RTListOff32ForEach(&pVM->pgm.s.pTreesR3->HeadVirtHandlerTypes, pCurVirtType, PGMVIRTHANDLERTYPEINT, ListNode)
2707	{
2708	if (pCurVirtType->pfnHandlerRC != NIL_RTRCPTR)
2709	pCurVirtType->pfnHandlerRC += offDelta;
2710	if (pCurVirtType->pfnPfHandlerRC != NIL_RTRCPTR)
2711	pCurVirtType->pfnPfHandlerRC += offDelta;
2712	}
2713	#endif
2714
2715	/*
2716	* The page pool.
2717	*/
2718	pgmR3PoolRelocate(pVM);
2719
2720	#ifdef VBOX_WITH_STATISTICS
2721	/*
2722	* Statistics.
2723	*/
2724	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2725	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2726	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2727	#endif
2728	}
2729
2730
2731	/**
2732	* Callback function for relocating a physical access handler.
2733	*
2734	* @returns 0 (continue enum)
2735	* @param pNode Pointer to a PGMPHYSHANDLER node.
2736	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2737	*/
2738	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2739	{
2740	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2741	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2742	if (pHandler->pvUserRC >= 0x10000)
2743	pHandler->pvUserRC += pArgs->offDelta;
2744	return 0;
2745	}
2746
2747	#ifdef VBOX_WITH_RAW_MODE
2748
2749	/**
2750	* Callback function for relocating a virtual access handler.
2751	*
2752	* @returns 0 (continue enum)
2753	* @param pNode Pointer to a PGMVIRTHANDLER node.
2754	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2755	*/
2756	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2757	{
2758	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2759	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2760	Assert(PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->enmKind != PGMVIRTHANDLERKIND_HYPERVISOR);
2761
2762	if ( pHandler->pvUserRC != NIL_RTRCPTR
2763	&& PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->fRelocUserRC)
2764	pHandler->pvUserRC += pArgs->offDelta;
2765	return 0;
2766	}
2767
2768
2769	/**
2770	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2771	*
2772	* @returns 0 (continue enum)
2773	* @param pNode Pointer to a PGMVIRTHANDLER node.
2774	* @param pvUser Pointer to a PGMRELOCHANDLERARGS.
2775	*/
2776	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2777	{
2778	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2779	PCPGMRELOCHANDLERARGS pArgs = (PCPGMRELOCHANDLERARGS)pvUser;
2780	Assert(PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->enmKind == PGMVIRTHANDLERKIND_HYPERVISOR);
2781
2782	if ( pHandler->pvUserRC != NIL_RTRCPTR
2783	&& PGMVIRTANDLER_GET_TYPE(pArgs->pVM, pHandler)->fRelocUserRC)
2784	pHandler->pvUserRC += pArgs->offDelta;
2785	return 0;
2786	}
2787
2788	#endif /* VBOX_WITH_RAW_MODE */
2789
2790	/**
2791	* Resets a virtual CPU when unplugged.
2792	*
2793	* @param pVM The cross context VM structure.
2794	* @param pVCpu The cross context virtual CPU structure.
2795	*/
2796	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2797	{
2798	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
2799	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
2800	&& g_aPgmGuestModeData[idxGst].pfnExit)
2801	{
2802	int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
2803	AssertReleaseRC(rc);
2804	}
2805	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2806
2807	int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
2808	AssertReleaseRC(rc);
2809
2810	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2811
2812	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2813
2814	/*
2815	* Re-init other members.
2816	*/
2817	pVCpu->pgm.s.fA20Enabled = true;
2818	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2819
2820	/*
2821	* Clear the FFs PGM owns.
2822	*/
2823	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2824	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2825	}
2826
2827
2828	/**
2829	* The VM is being reset.
2830	*
2831	* For the PGM component this means that any PD write monitors
2832	* needs to be removed.
2833	*
2834	* @param pVM The cross context VM structure.
2835	*/
2836	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
2837	{
2838	LogFlow(("PGMR3Reset:\n"));
2839	VM_ASSERT_EMT(pVM);
2840
2841	pgmLock(pVM);
2842
2843	/*
2844	* Unfix any fixed mappings and disable CR3 monitoring.
2845	*/
2846	pVM->pgm.s.fMappingsFixed = false;
2847	pVM->pgm.s.fMappingsFixedRestored = false;
2848	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2849	pVM->pgm.s.cbMappingFixed = 0;
2850
2851	/*
2852	* Exit the guest paging mode before the pgm pool gets reset.
2853	* Important to clean up the amd64 case.
2854	*/
2855	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2856	{
2857	PVMCPU pVCpu = &pVM->aCpus[i];
2858	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
2859	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
2860	&& g_aPgmGuestModeData[idxGst].pfnExit)
2861	{
2862	int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
2863	AssertReleaseRC(rc);
2864	}
2865	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2866	}
2867
2868	#ifdef DEBUG
2869	DBGFR3_INFO_LOG_SAFE(pVM, "mappings", NULL);
2870	DBGFR3_INFO_LOG_SAFE(pVM, "handlers", "all nostat");
2871	#endif
2872
2873	/*
2874	* Switch mode back to real mode. (Before resetting the pgm pool!)
2875	*/
2876	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2877	{
2878	PVMCPU pVCpu = &pVM->aCpus[i];
2879
2880	int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
2881	AssertReleaseRC(rc);
2882
2883	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2884	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2885	}
2886
2887	/*
2888	* Reset the shadow page pool.
2889	*/
2890	pgmR3PoolReset(pVM);
2891
2892	/*
2893	* Re-init various other members and clear the FFs that PGM owns.
2894	*/
2895	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2896	{
2897	PVMCPU pVCpu = &pVM->aCpus[i];
2898
2899	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2900	PGMNotifyNxeChanged(pVCpu, false);
2901
2902	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2903	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2904
2905	if (!pVCpu->pgm.s.fA20Enabled)
2906	{
2907	pVCpu->pgm.s.fA20Enabled = true;
2908	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2909	#ifdef PGM_WITH_A20
2910	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2911	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2912	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
2913	HMFlushTLB(pVCpu);
2914	#endif
2915	}
2916	}
2917
2918	//pgmLogState(pVM);
2919	pgmUnlock(pVM);
2920	}
2921
2922
2923	/**
2924	* Memory setup after VM construction or reset.
2925	*
2926	* @param pVM The cross context VM structure.
2927	* @param fAtReset Indicates the context, after reset if @c true or after
2928	* construction if @c false.
2929	*/
2930	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
2931	{
2932	if (fAtReset)
2933	{
2934	pgmLock(pVM);
2935
2936	int rc = pgmR3PhysRamZeroAll(pVM);
2937	AssertReleaseRC(rc);
2938
2939	rc = pgmR3PhysRomReset(pVM);
2940	AssertReleaseRC(rc);
2941
2942	pgmUnlock(pVM);
2943	}
2944	}
2945
2946
2947	#ifdef VBOX_STRICT
2948	/**
2949	* VM state change callback for clearing fNoMorePhysWrites after
2950	* a snapshot has been created.
2951	*/
2952	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2953	{
2954	if ( enmState == VMSTATE_RUNNING
2955	\|\| enmState == VMSTATE_RESUMING)
2956	pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2957	NOREF(enmOldState); NOREF(pvUser);
2958	}
2959	#endif
2960
2961	/**
2962	* Private API to reset fNoMorePhysWrites.
2963	*/
2964	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2965	{
2966	pVM->pgm.s.fNoMorePhysWrites = false;
2967	}
2968
2969	/**
2970	* Terminates the PGM.
2971	*
2972	* @returns VBox status code.
2973	* @param pVM The cross context VM structure.
2974	*/
2975	VMMR3DECL(int) PGMR3Term(PVM pVM)
2976	{
2977	/* Must free shared pages here. */
2978	pgmLock(pVM);
2979	pgmR3PhysRamTerm(pVM);
2980	pgmR3PhysRomTerm(pVM);
2981	pgmUnlock(pVM);
2982
2983	PGMDeregisterStringFormatTypes();
2984	return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2985	}
2986
2987
2988	/**
2989	* Show paging mode.
2990	*
2991	* @param pVM The cross context VM structure.
2992	* @param pHlp The info helpers.
2993	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2994	*/
2995	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2996	{
2997	/* digest argument. */
2998	bool fGuest, fShadow, fHost;
2999	if (pszArgs)
3000	pszArgs = RTStrStripL(pszArgs);
3001	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3002	fShadow = fHost = fGuest = true;
3003	else
3004	{
3005	fShadow = fHost = fGuest = false;
3006	if (strstr(pszArgs, "guest"))
3007	fGuest = true;
3008	if (strstr(pszArgs, "shadow"))
3009	fShadow = true;
3010	if (strstr(pszArgs, "host"))
3011	fHost = true;
3012	}
3013
3014	PVMCPU pVCpu = VMMGetCpu(pVM);
3015	if (!pVCpu)
3016	pVCpu = &pVM->aCpus[0];
3017
3018
3019	/* print info. */
3020	if (fGuest)
3021	pHlp->pfnPrintf(pHlp, "Guest paging mode (VCPU #%u): %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
3022	pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmGuestMode), pVCpu->pgm.s.cGuestModeChanges.c,
3023	pVCpu->pgm.s.fA20Enabled ? "enabled" : "disabled", pVCpu->pgm.s.cA20Changes.c);
3024	if (fShadow)
3025	pHlp->pfnPrintf(pHlp, "Shadow paging mode (VCPU #%u): %s\n", pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmShadowMode));
3026	if (fHost)
3027	{
3028	const char *psz;
3029	switch (pVM->pgm.s.enmHostMode)
3030	{
3031	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3032	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3033	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3034	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3035	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3036	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3037	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3038	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3039	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3040	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3041	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3042	default: psz = "unknown"; break;
3043	}
3044	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3045	}
3046	}
3047
3048
3049	/**
3050	* Dump registered MMIO ranges to the log.
3051	*
3052	* @param pVM The cross context VM structure.
3053	* @param pHlp The info helpers.
3054	* @param pszArgs Arguments, ignored.
3055	*/
3056	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3057	{
3058	bool const fVerbose = pszArgs && strstr(pszArgs, "verbose") != NULL;
3059
3060	pHlp->pfnPrintf(pHlp,
3061	"RAM ranges (pVM=%p)\n"
3062	"%.s %.s\n",
3063	pVM,
3064	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3065	sizeof(RTHCPTR) * 2, "pvHC ");
3066
3067	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
3068	{
3069	pHlp->pfnPrintf(pHlp,
3070	"%RGp-%RGp %RHv %s\n",
3071	pCur->GCPhys,
3072	pCur->GCPhysLast,
3073	pCur->pvR3,
3074	pCur->pszDesc);
3075	if (fVerbose)
3076	{
3077	RTGCPHYS const cPages = pCur->cb >> X86_PAGE_SHIFT;
3078	RTGCPHYS iPage = 0;
3079	while (iPage < cPages)
3080	{
3081	RTGCPHYS const iFirstPage = iPage;
3082	PGMPAGETYPE const enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]);
3083	do
3084	iPage++;
3085	while (iPage < cPages && (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == enmType);
3086	const char *pszType;
3087	const char *pszMore = NULL;
3088	switch (enmType)
3089	{
3090	case PGMPAGETYPE_RAM:
3091	pszType = "RAM";
3092	break;
3093
3094	case PGMPAGETYPE_MMIO2:
3095	pszType = "MMIO2";
3096	break;
3097
3098	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3099	pszType = "MMIO2-alias-MMIO";
3100	break;
3101
3102	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
3103	pszType = "special-alias-MMIO";
3104	break;
3105
3106	case PGMPAGETYPE_ROM_SHADOW:
3107	case PGMPAGETYPE_ROM:
3108	{
3109	pszType = enmType == PGMPAGETYPE_ROM_SHADOW ? "ROM-shadowed" : "ROM";
3110
3111	RTGCPHYS const GCPhysFirstPg = iFirstPage * X86_PAGE_SIZE;
3112	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
3113	while (pRom && GCPhysFirstPg > pRom->GCPhysLast)
3114	pRom = pRom->pNextR3;
3115	if (pRom && GCPhysFirstPg - pRom->GCPhys < pRom->cb)
3116	pszMore = pRom->pszDesc;
3117	break;
3118	}
3119
3120	case PGMPAGETYPE_MMIO:
3121	{
3122	pszType = "MMIO";
3123	pgmLock(pVM);
3124	PPGMPHYSHANDLER pHandler = pgmHandlerPhysicalLookup(pVM, iFirstPage * X86_PAGE_SIZE);
3125	if (pHandler)
3126	pszMore = pHandler->pszDesc;
3127	pgmUnlock(pVM);
3128	break;
3129	}
3130
3131	case PGMPAGETYPE_INVALID:
3132	pszType = "invalid";
3133	break;
3134
3135	default:
3136	pszType = "bad";
3137	break;
3138	}
3139	if (pszMore)
3140	pHlp->pfnPrintf(pHlp, " %RGp-%RGp %-20s %s\n",
3141	pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
3142	pCur->GCPhys + iPage * X86_PAGE_SIZE,
3143	pszType, pszMore);
3144	else
3145	pHlp->pfnPrintf(pHlp, " %RGp-%RGp %s\n",
3146	pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
3147	pCur->GCPhys + iPage * X86_PAGE_SIZE,
3148	pszType);
3149
3150	}
3151	}
3152	}
3153	}
3154
3155
3156	/**
3157	* Dump the page directory to the log.
3158	*
3159	* @param pVM The cross context VM structure.
3160	* @param pHlp The info helpers.
3161	* @param pszArgs Arguments, ignored.
3162	*/
3163	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3164	{
3165	/** @todo SMP support!! */
3166	PVMCPU pVCpu = &pVM->aCpus[0];
3167
3168	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3169	/* Big pages supported? */
3170	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3171
3172	/* Global pages supported? */
3173	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3174
3175	NOREF(pszArgs);
3176
3177	/*
3178	* Get page directory addresses.
3179	*/
3180	pgmLock(pVM);
3181	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3182	Assert(pPDSrc);
3183
3184	/*
3185	* Iterate the page directory.
3186	*/
3187	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3188	{
3189	X86PDE PdeSrc = pPDSrc->a[iPD];
3190	if (PdeSrc.n.u1Present)
3191	{
3192	if (PdeSrc.b.u1Size && fPSE)
3193	pHlp->pfnPrintf(pHlp,
3194	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3195	iPD,
3196	pgmGstGet4MBPhysPage(pVM, PdeSrc),
3197	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3198	else
3199	pHlp->pfnPrintf(pHlp,
3200	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3201	iPD,
3202	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3203	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3204	}
3205	}
3206	pgmUnlock(pVM);
3207	}
3208
3209
3210	/**
3211	* Service a VMMCALLRING3_PGM_LOCK call.
3212	*
3213	* @returns VBox status code.
3214	* @param pVM The cross context VM structure.
3215	*/
3216	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3217	{
3218	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
3219	AssertRC(rc);
3220	return rc;
3221	}
3222
3223
3224	/**
3225	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3226	*
3227	* @returns VBox status code, fully asserted.
3228	* @param pVCpu The cross context virtual CPU structure.
3229	*/
3230	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3231	{
3232	/* Unmap the old CR3 value before flushing everything. */
3233	int rc = VINF_SUCCESS;
3234	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
3235	if ( idxBth < RT_ELEMENTS(g_aPgmBothModeData)
3236	&& g_aPgmBothModeData[idxBth].pfnMapCR3)
3237	{
3238	rc = g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
3239	AssertRC(rc);
3240	}
3241
3242	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3243	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
3244	if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
3245	&& g_aPgmShadowModeData[idxShw].pfnExit)
3246	{
3247	rc = g_aPgmShadowModeData[idxShw].pfnExit(pVCpu);
3248	AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
3249	}
3250
3251	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3252	return rc;
3253	}
3254
3255
3256	/**
3257	* Called by pgmPoolFlushAllInt after flushing the pool.
3258	*
3259	* @returns VBox status code, fully asserted.
3260	* @param pVM The cross context VM structure.
3261	* @param pVCpu The cross context virtual CPU structure.
3262	*/
3263	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3264	{
3265	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3266	int rc = PGMHCChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3267	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3268	AssertRCReturn(rc, rc);
3269	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3270
3271	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3272	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED_32BIT
3273	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3274	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3275	return rc;
3276	}
3277
3278
3279	/**
3280	* Called by PGMR3PhysSetA20 after changing the A20 state.
3281	*
3282	* @param pVCpu The cross context virtual CPU structure.
3283	*/
3284	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
3285	{
3286	/** @todo Probably doing a bit too much here. */
3287	int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
3288	AssertReleaseRC(rc);
3289	rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
3290	AssertReleaseRC(rc);
3291	}
3292
3293
3294	#ifdef VBOX_WITH_DEBUGGER
3295
3296	/**
3297	* @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
3298	*/
3299	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3300	{
3301	/*
3302	* Validate input.
3303	*/
3304	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3305	PVM pVM = pUVM->pVM;
3306	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
3307
3308	if (!cArgs)
3309	{
3310	/*
3311	* Print the list of error injection locations with status.
3312	*/
3313	DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
3314	DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3315	}
3316	else
3317	{
3318	/*
3319	* String switch on where to inject the error.
3320	*/
3321	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
3322	const char *pszWhere = paArgs[0].u.pszString;
3323	if (!strcmp(pszWhere, "handy"))
3324	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
3325	else
3326	return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
3327	DBGCCmdHlpPrintf(pCmdHlp, "done\n");
3328	}
3329	return VINF_SUCCESS;
3330	}
3331
3332
3333	/**
3334	* @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
3335	*/
3336	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3337	{
3338	/*
3339	* Validate input.
3340	*/
3341	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3342	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3343	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3344	if (!pVCpu)
3345	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3346
3347	/*
3348	* Force page directory sync.
3349	*/
3350	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3351
3352	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
3353	if (RT_FAILURE(rc))
3354	return rc;
3355
3356	return VINF_SUCCESS;
3357	}
3358
3359	#ifdef VBOX_STRICT
3360
3361	/**
3362	* EMT callback for pgmR3CmdAssertCR3.
3363	*
3364	* @returns VBox status code.
3365	* @param pUVM The user mode VM handle.
3366	* @param pcErrors Where to return the error count.
3367	*/
3368	static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
3369	{
3370	PVM pVM = pUVM->pVM;
3371	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3372	PVMCPU pVCpu = VMMGetCpu(pVM);
3373
3374	*pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
3375
3376	return VINF_SUCCESS;
3377	}
3378
3379
3380	/**
3381	* @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
3382	*/
3383	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3384	{
3385	/*
3386	* Validate input.
3387	*/
3388	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3389	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3390
3391	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
3392	if (RT_FAILURE(rc))
3393	return rc;
3394
3395	unsigned cErrors = 0;
3396	rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
3397	if (RT_FAILURE(rc))
3398	return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
3399	if (cErrors > 0)
3400	return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
3401	return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
3402	}
3403
3404	#endif /* VBOX_STRICT */
3405
3406	/**
3407	* @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
3408	*/
3409	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3410	{
3411	/*
3412	* Validate input.
3413	*/
3414	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3415	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3416	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3417	if (!pVCpu)
3418	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3419
3420	/*
3421	* Force page directory sync.
3422	*/
3423	int rc;
3424	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3425	{
3426	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3427	rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
3428	}
3429	else
3430	{
3431	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3432	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3433	rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
3434	}
3435	return rc;
3436	}
3437
3438
3439	/**
3440	* @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
3441	*/
3442	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3443	{
3444	/*
3445	* Validate input.
3446	*/
3447	NOREF(pCmd);
3448	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3449	PVM pVM = pUVM->pVM;
3450	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 \|\| cArgs == 2);
3451	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType == DBGCVAR_TYPE_STRING);
3452	if (cArgs == 2)
3453	{
3454	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[1].enmType == DBGCVAR_TYPE_STRING);
3455	if (strcmp(paArgs[1].u.pszString, "nozero"))
3456	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
3457	}
3458	bool fIncZeroPgs = cArgs < 2;
3459
3460	/*
3461	* Open the output file and get the ram parameters.
3462	*/
3463	RTFILE hFile;
3464	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
3465	if (RT_FAILURE(rc))
3466	return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
3467
3468	uint32_t cbRamHole = 0;
3469	CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
3470	uint64_t cbRam = 0;
3471	CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
3472	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
3473
3474	/*
3475	* Dump the physical memory, page by page.
3476	*/
3477	RTGCPHYS GCPhys = 0;
3478	char abZeroPg[PAGE_SIZE];
3479	RT_ZERO(abZeroPg);
3480
3481	pgmLock(pVM);
3482	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3483	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
3484	pRam = pRam->pNextR3)
3485	{
3486	/* fill the gap */
3487	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
3488	{
3489	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
3490	{
3491	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3492	GCPhys += PAGE_SIZE;
3493	}
3494	}
3495
3496	PCPGMPAGE pPage = &pRam->aPages[0];
3497	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
3498	{
3499	if ( PGM_PAGE_IS_ZERO(pPage)
3500	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3501	{
3502	if (fIncZeroPgs)
3503	{
3504	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3505	if (RT_FAILURE(rc))
3506	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3507	}
3508	}
3509	else
3510	{
3511	switch (PGM_PAGE_GET_TYPE(pPage))
3512	{
3513	case PGMPAGETYPE_RAM:
3514	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
3515	case PGMPAGETYPE_ROM:
3516	case PGMPAGETYPE_MMIO2:
3517	{
3518	void const *pvPage;
3519	PGMPAGEMAPLOCK Lock;
3520	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
3521	if (RT_SUCCESS(rc))
3522	{
3523	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
3524	PGMPhysReleasePageMappingLock(pVM, &Lock);
3525	if (RT_FAILURE(rc))
3526	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3527	}
3528	else
3529	DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3530	break;
3531	}
3532
3533	default:
3534	AssertFailed();
3535	RT_FALL_THRU();
3536	case PGMPAGETYPE_MMIO:
3537	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3538	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
3539	if (fIncZeroPgs)
3540	{
3541	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3542	if (RT_FAILURE(rc))
3543	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3544	}
3545	break;
3546	}
3547	}
3548
3549
3550	/* advance */
3551	GCPhys += PAGE_SIZE;
3552	pPage++;
3553	}
3554	}
3555	pgmUnlock(pVM);
3556
3557	RTFileClose(hFile);
3558	if (RT_SUCCESS(rc))
3559	return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
3560	return VINF_SUCCESS;
3561	}
3562
3563	#endif /* VBOX_WITH_DEBUGGER */
3564
3565	/**
3566	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3567	*/
3568	typedef struct PGMCHECKINTARGS
3569	{
3570	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3571	PPGMPHYSHANDLER pPrevPhys;
3572	#ifdef VBOX_WITH_RAW_MODE
3573	PPGMVIRTHANDLER pPrevVirt;
3574	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3575	#else
3576	void pvFiller1, pvFiller2;
3577	#endif
3578	PVM pVM;
3579	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3580
3581	/**
3582	* Validate a node in the physical handler tree.
3583	*
3584	* @returns 0 on if ok, other wise 1.
3585	* @param pNode The handler node.
3586	* @param pvUser pVM.
3587	*/
3588	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3589	{
3590	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3591	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3592	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3593	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,
3594	("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3595	AssertReleaseMsg( !pArgs->pPrevPhys
3596	\|\| ( pArgs->fLeftToRight
3597	? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key
3598	: pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3599	("pPrevPhys=%p %RGp-%RGp %s\n"
3600	" pCur=%p %RGp-%RGp %s\n",
3601	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3602	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3603	pArgs->pPrevPhys = pCur;
3604	return 0;
3605	}
3606
3607	#ifdef VBOX_WITH_RAW_MODE
3608
3609	/**
3610	* Validate a node in the virtual handler tree.
3611	*
3612	* @returns 0 on if ok, other wise 1.
3613	* @param pNode The handler node.
3614	* @param pvUser pVM.
3615	*/
3616	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3617	{
3618	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3619	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3620	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3621	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3622	AssertReleaseMsg( !pArgs->pPrevVirt
3623	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3624	("pPrevVirt=%p %RGv-%RGv %s\n"
3625	" pCur=%p %RGv-%RGv %s\n",
3626	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3627	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3628	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3629	{
3630	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -(intptr_t)RT_UOFFSETOF_DYN(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3631	("pCur=%p %RGv-%RGv %s\n"
3632	"iPage=%d offVirtHandle=%#x expected %#x\n",
3633	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3634	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -(intptr_t)RT_UOFFSETOF_DYN(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3635	}
3636	pArgs->pPrevVirt = pCur;
3637	return 0;
3638	}
3639
3640
3641	/**
3642	* Validate a node in the virtual handler tree.
3643	*
3644	* @returns 0 on if ok, other wise 1.
3645	* @param pNode The handler node.
3646	* @param pvUser pVM.
3647	*/
3648	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3649	{
3650	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3651	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3652	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3653	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3654	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3655	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3656	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3657	("pPrevPhys2Virt=%p %RGp-%RGp\n"
3658	" pCur=%p %RGp-%RGp\n",
3659	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3660	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3661	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3662	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3663	("pPrevPhys2Virt=%p %RGp-%RGp\n"
3664	" pCur=%p %RGp-%RGp\n",
3665	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3666	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3667	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3668	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3669	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3670	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3671	{
3672	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3673	for (;;)
3674	{
3675	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3676	AssertReleaseMsg(pCur2 != pCur,
3677	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3678	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3679	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3680	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3681	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3682	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3683	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3684	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3685	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3686	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3687	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3688	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3689	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3690	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3691	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3692	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3693	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3694	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3695	break;
3696	}
3697	}
3698
3699	pArgs->pPrevPhys2Virt = pCur;
3700	return 0;
3701	}
3702
3703	#endif /* VBOX_WITH_RAW_MODE */
3704
3705	/**
3706	* Perform an integrity check on the PGM component.
3707	*
3708	* @returns VINF_SUCCESS if everything is fine.
3709	* @returns VBox error status after asserting on integrity breach.
3710	* @param pVM The cross context VM structure.
3711	*/
3712	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3713	{
3714	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3715
3716	/*
3717	* Check the trees.
3718	*/
3719	int cErrors = 0;
3720	const PGMCHECKINTARGS LeftToRight = { true, NULL, NULL, NULL, pVM };
3721	const PGMCHECKINTARGS RightToLeft = { false, NULL, NULL, NULL, pVM };
3722	PGMCHECKINTARGS Args = LeftToRight;
3723	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3724	Args = RightToLeft;
3725	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3726	#ifdef VBOX_WITH_RAW_MODE
3727	Args = LeftToRight;
3728	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3729	Args = RightToLeft;
3730	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3731	Args = LeftToRight;
3732	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3733	Args = RightToLeft;
3734	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3735	Args = LeftToRight;
3736	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3737	Args = RightToLeft;
3738	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3739	#endif /* VBOX_WITH_RAW_MODE */
3740
3741	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3742	}
3743

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 73268

Download in other formats: