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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 80386

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1/* $Id: PGM.cpp 80333 2019-08-16 20:28:38Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/** @page pg_pgm PGM - The Page Manager and Monitor
20 *
21 * @sa @ref grp_pgm
22 * @subpage pg_pgm_pool
23 * @subpage pg_pgm_phys
24 *
25 *
26 * @section sec_pgm_modes Paging Modes
27 *
28 * There are three memory contexts: Host Context (HC), Guest Context (GC)
29 * and intermediate context. When talking about paging HC can also be referred
30 * to as "host paging", and GC referred to as "shadow paging".
31 *
32 * We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33 * is defined by the host operating system. The mode used in the shadow paging mode
34 * depends on the host paging mode and what the mode the guest is currently in. The
35 * following relation between the two is defined:
36 *
37 * @verbatim
38 Host > 32-bit | PAE | AMD64 |
39 Guest | | | |
40 ==v================================
41 32-bit 32-bit PAE PAE
42 -------|--------|--------|--------|
43 PAE PAE PAE PAE
44 -------|--------|--------|--------|
45 AMD64 AMD64 AMD64 AMD64
46 -------|--------|--------|--------| @endverbatim
47 *
48 * All configuration except those in the diagonal (upper left) are expected to
49 * require special effort from the switcher (i.e. a bit slower).
50 *
51 *
52 *
53 *
54 * @section sec_pgm_shw The Shadow Memory Context
55 *
56 *
57 * [..]
58 *
59 * Because of guest context mappings requires PDPT and PML4 entries to allow
60 * writing on AMD64, the two upper levels will have fixed flags whatever the
61 * guest is thinking of using there. So, when shadowing the PD level we will
62 * calculate the effective flags of PD and all the higher levels. In legacy
63 * PAE mode this only applies to the PWT and PCD bits (the rest are
64 * ignored/reserved/MBZ). We will ignore those bits for the present.
65 *
66 *
67 *
68 * @section sec_pgm_int The Intermediate Memory Context
69 *
70 * The world switch goes thru an intermediate memory context which purpose it is
71 * to provide different mappings of the switcher code. All guest mappings are also
72 * present in this context.
73 *
74 * The switcher code is mapped at the same location as on the host, at an
75 * identity mapped location (physical equals virtual address), and at the
76 * hypervisor location. The identity mapped location is for when the world
77 * switches that involves disabling paging.
78 *
79 * PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80 * simplifies switching guest CPU mode and consistency at the cost of more
81 * code to do the work. All memory use for those page tables is located below
82 * 4GB (this includes page tables for guest context mappings).
83 *
84 * Note! The intermediate memory context is also used for 64-bit guest
85 * execution on 32-bit hosts. Because we need to load 64-bit registers
86 * prior to switching to guest context, we need to be in 64-bit mode
87 * first. So, HM has some 64-bit worker routines in VMMRC.rc that get
88 * invoked via the special world switcher code in LegacyToAMD64.asm.
89 *
90 *
91 * @subsection subsec_pgm_int_gc Guest Context Mappings
92 *
93 * During assignment and relocation of a guest context mapping the intermediate
94 * memory context is used to verify the new location.
95 *
96 * Guest context mappings are currently restricted to below 4GB, for reasons
97 * of simplicity. This may change when we implement AMD64 support.
98 *
99 *
100 *
101 *
102 * @section sec_pgm_misc Misc
103 *
104 *
105 * @subsection sec_pgm_misc_A20 The A20 Gate
106 *
107 * PGM implements the A20 gate masking when translating a virtual guest address
108 * into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
109 * the code reading the guest page table entries during shadowing. The masking
110 * is done consistenly for all CPU modes, paged ones included. Large pages are
111 * also masked correctly. (On current CPUs, experiments indicates that AMD does
112 * not apply A20M in paged modes and intel only does it for the 2nd MB of
113 * memory.)
114 *
115 * The A20 gate implementation is per CPU core. It can be configured on a per
116 * core basis via the keyboard device and PC architecture device. This is
117 * probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
118 * guest OSes try pushing things anyway, so who cares. (On current real systems
119 * the A20M signal is probably only sent to the boot CPU and it affects all
120 * thread and probably all cores in that package.)
121 *
122 * The keyboard device and the PC architecture device doesn't OR their A20
123 * config bits together, rather they are currently implemented such that they
124 * mirror the CPU state. So, flipping the bit in either of them will change the
125 * A20 state. (On real hardware the bits of the two devices should probably be
126 * ORed together to indicate enabled, i.e. both needs to be cleared to disable
127 * A20 masking.)
128 *
129 * The A20 state will change immediately, transmeta fashion. There is no delays
130 * due to buses, wiring or other physical stuff. (On real hardware there are
131 * normally delays, the delays differs between the two devices and probably also
132 * between chipsets and CPU generations. Note that it's said that transmeta CPUs
133 * does the change immediately like us, they apparently intercept/handles the
134 * port accesses in microcode. Neat.)
135 *
136 * @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
137 *
138 *
139 * @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
140 *
141 * The differences between legacy PAE and long mode PAE are:
142 * -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
143 * all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
144 * usual meanings while 6 is ignored (AMD). This means that upon switching to
145 * legacy PAE mode we'll have to clear these bits and when going to long mode
146 * they must be set. This applies to both intermediate and shadow contexts,
147 * however we don't need to do it for the intermediate one since we're
148 * executing with CR0.WP at that time.
149 * -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
150 * a page aligned one is required.
151 *
152 *
153 * @section sec_pgm_handlers Access Handlers
154 *
155 * Placeholder.
156 *
157 *
158 * @subsection sec_pgm_handlers_phys Physical Access Handlers
159 *
160 * Placeholder.
161 *
162 *
163 * @subsection sec_pgm_handlers_virt Virtual Access Handlers (obsolete)
164 *
165 * We currently implement three types of virtual access handlers: ALL, WRITE
166 * and HYPERVISOR (WRITE). See PGMVIRTHANDLERKIND for some more details.
167 *
168 * The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
169 * to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
170 * a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
171 * rest of this section is going to be about these handlers.
172 *
173 * We'll go thru the life cycle of a handler and try make sense of it all, don't know
174 * how successful this is gonna be...
175 *
176 * 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
177 * PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
178 * and create a new node that is inserted into the AVL tree (range key). Then
179 * a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
180 *
181 * 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
182 *
183 * 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
184 * via the current guest CR3 and update the physical page -> virtual handler
185 * translation. Needless to say, this doesn't exactly scale very well. If any changes
186 * are detected, it will flag a virtual bit update just like we did on registration.
187 * PGMPHYS pages with changes will have their virtual handler state reset to NONE.
188 *
189 * 2b. The virtual bit update process will iterate all the pages covered by all the
190 * virtual handlers and update the PGMPAGE virtual handler state to the max of all
191 * virtual handlers on that page.
192 *
193 * 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
194 * we don't miss any alias mappings of the monitored pages.
195 *
196 * 2d. SyncCR3 will then proceed with syncing the CR3 table.
197 *
198 * 3. \#PF(np,read) on a page in the range. This will cause it to be synced
199 * read-only and resumed if it's a WRITE handler. If it's an ALL handler we
200 * will call the handlers like in the next step. If the physical mapping has
201 * changed we will - some time in the future - perform a handler callback
202 * (optional) and update the physical -> virtual handler cache.
203 *
204 * 4. \#PF(,write) on a page in the range. This will cause the handler to
205 * be invoked.
206 *
207 * 5. The guest invalidates the page and changes the physical backing or
208 * unmaps it. This should cause the invalidation callback to be invoked
209 * (it might not yet be 100% perfect). Exactly what happens next... is
210 * this where we mess up and end up out of sync for a while?
211 *
212 * 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
213 * We will then set all PGMPAGEs in the physical -> virtual handler cache for
214 * this handler to NONE and trigger a full PGM resync (basically the same
215 * as int step 1). Which means 2 is executed again.
216 *
217 *
218 * @subsubsection sub_sec_pgm_handler_virt_todo TODOs
219 *
220 * There is a bunch of things that needs to be done to make the virtual handlers
221 * work 100% correctly and work more efficiently.
222 *
223 * The first bit hasn't been implemented yet because it's going to slow the
224 * whole mess down even more, and besides it seems to be working reliably for
225 * our current uses. OTOH, some of the optimizations might end up more or less
226 * implementing the missing bits, so we'll see.
227 *
228 * On the optimization side, the first thing to do is to try avoid unnecessary
229 * cache flushing. Then try team up with the shadowing code to track changes
230 * in mappings by means of access to them (shadow in), updates to shadows pages,
231 * invlpg, and shadow PT discarding (perhaps).
232 *
233 * Some idea that have popped up for optimization for current and new features:
234 * - bitmap indicating where there are virtual handlers installed.
235 * (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
236 * - Further optimize this by min/max (needs min/max avl getters).
237 * - Shadow page table entry bit (if any left)?
238 *
239 */
240
241
242/** @page pg_pgm_phys PGM Physical Guest Memory Management
243 *
244 *
245 * Objectives:
246 * - Guest RAM over-commitment using memory ballooning,
247 * zero pages and general page sharing.
248 * - Moving or mirroring a VM onto a different physical machine.
249 *
250 *
251 * @section sec_pgmPhys_Definitions Definitions
252 *
253 * Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
254 * machinery associated with it.
255 *
256 *
257 *
258 *
259 * @section sec_pgmPhys_AllocPage Allocating a page.
260 *
261 * Initially we map *all* guest memory to the (per VM) zero page, which
262 * means that none of the read functions will cause pages to be allocated.
263 *
264 * Exception, access bit in page tables that have been shared. This must
265 * be handled, but we must also make sure PGMGst*Modify doesn't make
266 * unnecessary modifications.
267 *
268 * Allocation points:
269 * - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
270 * - Replacing a zero page mapping at \#PF.
271 * - Replacing a shared page mapping at \#PF.
272 * - ROM registration (currently MMR3RomRegister).
273 * - VM restore (pgmR3Load).
274 *
275 * For the first three it would make sense to keep a few pages handy
276 * until we've reached the max memory commitment for the VM.
277 *
278 * For the ROM registration, we know exactly how many pages we need
279 * and will request these from ring-0. For restore, we will save
280 * the number of non-zero pages in the saved state and allocate
281 * them up front. This would allow the ring-0 component to refuse
282 * the request if the isn't sufficient memory available for VM use.
283 *
284 * Btw. for both ROM and restore allocations we won't be requiring
285 * zeroed pages as they are going to be filled instantly.
286 *
287 *
288 * @section sec_pgmPhys_FreePage Freeing a page
289 *
290 * There are a few points where a page can be freed:
291 * - After being replaced by the zero page.
292 * - After being replaced by a shared page.
293 * - After being ballooned by the guest additions.
294 * - At reset.
295 * - At restore.
296 *
297 * When freeing one or more pages they will be returned to the ring-0
298 * component and replaced by the zero page.
299 *
300 * The reasoning for clearing out all the pages on reset is that it will
301 * return us to the exact same state as on power on, and may thereby help
302 * us reduce the memory load on the system. Further it might have a
303 * (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
304 *
305 * On restore, as mention under the allocation topic, pages should be
306 * freed / allocated depending on how many is actually required by the
307 * new VM state. The simplest approach is to do like on reset, and free
308 * all non-ROM pages and then allocate what we need.
309 *
310 * A measure to prevent some fragmentation, would be to let each allocation
311 * chunk have some affinity towards the VM having allocated the most pages
312 * from it. Also, try make sure to allocate from allocation chunks that
313 * are almost full. Admittedly, both these measures might work counter to
314 * our intentions and its probably not worth putting a lot of effort,
315 * cpu time or memory into this.
316 *
317 *
318 * @section sec_pgmPhys_SharePage Sharing a page
319 *
320 * The basic idea is that there there will be a idle priority kernel
321 * thread walking the non-shared VM pages hashing them and looking for
322 * pages with the same checksum. If such pages are found, it will compare
323 * them byte-by-byte to see if they actually are identical. If found to be
324 * identical it will allocate a shared page, copy the content, check that
325 * the page didn't change while doing this, and finally request both the
326 * VMs to use the shared page instead. If the page is all zeros (special
327 * checksum and byte-by-byte check) it will request the VM that owns it
328 * to replace it with the zero page.
329 *
330 * To make this efficient, we will have to make sure not to try share a page
331 * that will change its contents soon. This part requires the most work.
332 * A simple idea would be to request the VM to write monitor the page for
333 * a while to make sure it isn't modified any time soon. Also, it may
334 * make sense to skip pages that are being write monitored since this
335 * information is readily available to the thread if it works on the
336 * per-VM guest memory structures (presently called PGMRAMRANGE).
337 *
338 *
339 * @section sec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
340 *
341 * The pages are organized in allocation chunks in ring-0, this is a necessity
342 * if we wish to have an OS agnostic approach to this whole thing. (On Linux we
343 * could easily work on a page-by-page basis if we liked. Whether this is possible
344 * or efficient on NT I don't quite know.) Fragmentation within these chunks may
345 * become a problem as part of the idea here is that we wish to return memory to
346 * the host system.
347 *
348 * For instance, starting two VMs at the same time, they will both allocate the
349 * guest memory on-demand and if permitted their page allocations will be
350 * intermixed. Shut down one of the two VMs and it will be difficult to return
351 * any memory to the host system because the page allocation for the two VMs are
352 * mixed up in the same allocation chunks.
353 *
354 * To further complicate matters, when pages are freed because they have been
355 * ballooned or become shared/zero the whole idea is that the page is supposed
356 * to be reused by another VM or returned to the host system. This will cause
357 * allocation chunks to contain pages belonging to different VMs and prevent
358 * returning memory to the host when one of those VM shuts down.
359 *
360 * The only way to really deal with this problem is to move pages. This can
361 * either be done at VM shutdown and or by the idle priority worker thread
362 * that will be responsible for finding sharable/zero pages. The mechanisms
363 * involved for coercing a VM to move a page (or to do it for it) will be
364 * the same as when telling it to share/zero a page.
365 *
366 *
367 * @section sec_pgmPhys_Tracking Tracking Structures And Their Cost
368 *
369 * There's a difficult balance between keeping the per-page tracking structures
370 * (global and guest page) easy to use and keeping them from eating too much
371 * memory. We have limited virtual memory resources available when operating in
372 * 32-bit kernel space (on 64-bit there'll it's quite a different story). The
373 * tracking structures will be attempted designed such that we can deal with up
374 * to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
375 *
376 *
377 * @subsection subsec_pgmPhys_Tracking_Kernel Kernel Space
378 *
379 * @see pg_GMM
380 *
381 * @subsection subsec_pgmPhys_Tracking_PerVM Per-VM
382 *
383 * Fixed info is the physical address of the page (HCPhys) and the page id
384 * (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
385 * Today we've restricting ourselves to 40(-12) bits because this is the current
386 * restrictions of all AMD64 implementations (I think Barcelona will up this
387 * to 48(-12) bits, not that it really matters) and I needed the bits for
388 * tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
389 * decent range for the page id: 2^(28+12) = 1024TB.
390 *
391 * In additions to these, we'll have to keep maintaining the page flags as we
392 * currently do. Although it wouldn't harm to optimize these quite a bit, like
393 * for instance the ROM shouldn't depend on having a write handler installed
394 * in order for it to become read-only. A RO/RW bit should be considered so
395 * that the page syncing code doesn't have to mess about checking multiple
396 * flag combinations (ROM || RW handler || write monitored) in order to
397 * figure out how to setup a shadow PTE. But this of course, is second
398 * priority at present. Current this requires 12 bits, but could probably
399 * be optimized to ~8.
400 *
401 * Then there's the 24 bits used to track which shadow page tables are
402 * currently mapping a page for the purpose of speeding up physical
403 * access handlers, and thereby the page pool cache. More bit for this
404 * purpose wouldn't hurt IIRC.
405 *
406 * Then there is a new bit in which we need to record what kind of page
407 * this is, shared, zero, normal or write-monitored-normal. This'll
408 * require 2 bits. One bit might be needed for indicating whether a
409 * write monitored page has been written to. And yet another one or
410 * two for tracking migration status. 3-4 bits total then.
411 *
412 * Whatever is left will can be used to record the sharabilitiy of a
413 * page. The page checksum will not be stored in the per-VM table as
414 * the idle thread will not be permitted to do modifications to it.
415 * It will instead have to keep its own working set of potentially
416 * shareable pages and their check sums and stuff.
417 *
418 * For the present we'll keep the current packing of the
419 * PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
420 * we'll have to change it to a struct with a total of 128-bits at
421 * our disposal.
422 *
423 * The initial layout will be like this:
424 * @verbatim
425 RTHCPHYS HCPhys; The current stuff.
426 63:40 Current shadow PT tracking stuff.
427 39:12 The physical page frame number.
428 11:0 The current flags.
429 uint32_t u28PageId : 28; The page id.
430 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
431 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
432 uint32_t u1Reserved : 1; Reserved for later.
433 uint32_t u32Reserved; Reserved for later, mostly sharing stats.
434 @endverbatim
435 *
436 * The final layout will be something like this:
437 * @verbatim
438 RTHCPHYS HCPhys; The current stuff.
439 63:48 High page id (12+).
440 47:12 The physical page frame number.
441 11:0 Low page id.
442 uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
443 uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
444 uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
445 uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
446 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
447 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
448 uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
449 uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
450 @endverbatim
451 *
452 * Cost wise, this means we'll double the cost for guest memory. There isn't anyway
453 * around that I'm afraid. It means that the cost of dealing out 32GB of memory
454 * to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
455 * example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
456 *
457 * A couple of cost examples for the total cost per-VM + kernel.
458 * 32-bit Windows and 32-bit linux:
459 * 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
460 * 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
461 * 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
462 * 64-bit Windows and 64-bit linux:
463 * 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
464 * 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
465 * 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
466 *
467 * UPDATE - 2007-09-27:
468 * Will need a ballooned flag/state too because we cannot
469 * trust the guest 100% and reporting the same page as ballooned more
470 * than once will put the GMM off balance.
471 *
472 *
473 * @section sec_pgmPhys_Serializing Serializing Access
474 *
475 * Initially, we'll try a simple scheme:
476 *
477 * - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
478 * by the EMT thread of that VM while in the pgm critsect.
479 * - Other threads in the VM process that needs to make reliable use of
480 * the per-VM RAM tracking structures will enter the critsect.
481 * - No process external thread or kernel thread will ever try enter
482 * the pgm critical section, as that just won't work.
483 * - The idle thread (and similar threads) doesn't not need 100% reliable
484 * data when performing it tasks as the EMT thread will be the one to
485 * do the actual changes later anyway. So, as long as it only accesses
486 * the main ram range, it can do so by somehow preventing the VM from
487 * being destroyed while it works on it...
488 *
489 * - The over-commitment management, including the allocating/freeing
490 * chunks, is serialized by a ring-0 mutex lock (a fast one since the
491 * more mundane mutex implementation is broken on Linux).
492 * - A separate mutex is protecting the set of allocation chunks so
493 * that pages can be shared or/and freed up while some other VM is
494 * allocating more chunks. This mutex can be take from under the other
495 * one, but not the other way around.
496 *
497 *
498 * @section sec_pgmPhys_Request VM Request interface
499 *
500 * When in ring-0 it will become necessary to send requests to a VM so it can
501 * for instance move a page while defragmenting during VM destroy. The idle
502 * thread will make use of this interface to request VMs to setup shared
503 * pages and to perform write monitoring of pages.
504 *
505 * I would propose an interface similar to the current VMReq interface, similar
506 * in that it doesn't require locking and that the one sending the request may
507 * wait for completion if it wishes to. This shouldn't be very difficult to
508 * realize.
509 *
510 * The requests themselves are also pretty simple. They are basically:
511 * -# Check that some precondition is still true.
512 * -# Do the update.
513 * -# Update all shadow page tables involved with the page.
514 *
515 * The 3rd step is identical to what we're already doing when updating a
516 * physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
517 *
518 *
519 *
520 * @section sec_pgmPhys_MappingCaches Mapping Caches
521 *
522 * In order to be able to map in and out memory and to be able to support
523 * guest with more RAM than we've got virtual address space, we'll employing
524 * a mapping cache. Normally ring-0 and ring-3 can share the same cache,
525 * however on 32-bit darwin the ring-0 code is running in a different memory
526 * context and therefore needs a separate cache. In raw-mode context we also
527 * need a separate cache. The 32-bit darwin mapping cache and the one for
528 * raw-mode context share a lot of code, see PGMRZDYNMAP.
529 *
530 *
531 * @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
532 *
533 * We've considered implementing the ring-3 mapping cache page based but found
534 * that this was bother some when one had to take into account TLBs+SMP and
535 * portability (missing the necessary APIs on several platforms). There were
536 * also some performance concerns with this approach which hadn't quite been
537 * worked out.
538 *
539 * Instead, we'll be mapping allocation chunks into the VM process. This simplifies
540 * matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
541 * only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
542 * compared to the previous idea is that mapping or unmapping a 1MB chunk is more
543 * costly than a single page, although how much more costly is uncertain. We'll
544 * try address this by using a very big cache, preferably bigger than the actual
545 * VM RAM size if possible. The current VM RAM sizes should give some idea for
546 * 32-bit boxes, while on 64-bit we can probably get away with employing an
547 * unlimited cache.
548 *
549 * The cache have to parts, as already indicated, the ring-3 side and the
550 * ring-0 side.
551 *
552 * The ring-0 will be tied to the page allocator since it will operate on the
553 * memory objects it contains. It will therefore require the first ring-0 mutex
554 * discussed in @ref sec_pgmPhys_Serializing. We some double house keeping wrt
555 * to who has mapped what I think, since both VMMR0.r0 and RTR0MemObj will keep
556 * track of mapping relations
557 *
558 * The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
559 * require anyone that desires to do changes to the mapping cache to do that
560 * from within this critsect. Alternatively, we could employ a separate critsect
561 * for serializing changes to the mapping cache as this would reduce potential
562 * contention with other threads accessing mappings unrelated to the changes
563 * that are in process. We can see about this later, contention will show
564 * up in the statistics anyway, so it'll be simple to tell.
565 *
566 * The organization of the ring-3 part will be very much like how the allocation
567 * chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
568 * having to walk the tree all the time, we'll have a couple of lookaside entries
569 * like in we do for I/O ports and MMIO in IOM.
570 *
571 * The simplified flow of a PGMPhysRead/Write function:
572 * -# Enter the PGM critsect.
573 * -# Lookup GCPhys in the ram ranges and get the Page ID.
574 * -# Calc the Allocation Chunk ID from the Page ID.
575 * -# Check the lookaside entries and then the AVL tree for the Chunk ID.
576 * If not found in cache:
577 * -# Call ring-0 and request it to be mapped and supply
578 * a chunk to be unmapped if the cache is maxed out already.
579 * -# Insert the new mapping into the AVL tree (id + R3 address).
580 * -# Update the relevant lookaside entry and return the mapping address.
581 * -# Do the read/write according to monitoring flags and everything.
582 * -# Leave the critsect.
583 *
584 *
585 * @section sec_pgmPhys_Fallback Fallback
586 *
587 * Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
588 * API and thus require a fallback.
589 *
590 * So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
591 * will return to the ring-3 caller (and later ring-0) and asking it to seed
592 * the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
593 * then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
594 * "SeededAllocPages" call to ring-0.
595 *
596 * The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
597 * all page sharing (zero page detection will continue). It will also force
598 * all allocations to come from the VM which seeded the page. Both these
599 * measures are taken to make sure that there will never be any need for
600 * mapping anything into ring-3 - everything will be mapped already.
601 *
602 * Whether we'll continue to use the current MM locked memory management
603 * for this I don't quite know (I'd prefer not to and just ditch that all
604 * together), we'll see what's simplest to do.
605 *
606 *
607 *
608 * @section sec_pgmPhys_Changes Changes
609 *
610 * Breakdown of the changes involved?
611 */
612
613
614/*********************************************************************************************************************************
615* Header Files *
616*********************************************************************************************************************************/
617#define LOG_GROUP LOG_GROUP_PGM
618#include <VBox/vmm/dbgf.h>
619#include <VBox/vmm/pgm.h>
620#include <VBox/vmm/cpum.h>
621#include <VBox/vmm/iom.h>
622#include <VBox/sup.h>
623#include <VBox/vmm/mm.h>
624#include <VBox/vmm/em.h>
625#include <VBox/vmm/stam.h>
626#ifdef VBOX_WITH_REM
627# include <VBox/vmm/rem.h>
628#endif
629#include <VBox/vmm/selm.h>
630#include <VBox/vmm/ssm.h>
631#include <VBox/vmm/hm.h>
632#include "PGMInternal.h"
633#include <VBox/vmm/vm.h>
634#include <VBox/vmm/uvm.h>
635#include "PGMInline.h"
636
637#include <VBox/dbg.h>
638#include <VBox/param.h>
639#include <VBox/err.h>
640
641#include <iprt/asm.h>
642#include <iprt/asm-amd64-x86.h>
643#include <iprt/assert.h>
644#include <iprt/env.h>
645#include <iprt/mem.h>
646#include <iprt/file.h>
647#include <iprt/string.h>
648#include <iprt/thread.h>
649
650
651/*********************************************************************************************************************************
652* Structures and Typedefs *
653*********************************************************************************************************************************/
654/**
655 * Argument package for pgmR3RElocatePhysHnadler, pgmR3RelocateVirtHandler and
656 * pgmR3RelocateHyperVirtHandler.
657 */
658typedef struct PGMRELOCHANDLERARGS
659{
660 RTGCINTPTR offDelta;
661 PVM pVM;
662} PGMRELOCHANDLERARGS;
663/** Pointer to a page access handlere relocation argument package. */
664typedef PGMRELOCHANDLERARGS const *PCPGMRELOCHANDLERARGS;
665
666
667/*********************************************************************************************************************************
668* Internal Functions *
669*********************************************************************************************************************************/
670static int pgmR3InitPaging(PVM pVM);
671static int pgmR3InitStats(PVM pVM);
672static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
673static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
674static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
675#ifdef VBOX_STRICT
676static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
677#endif
678
679#ifdef VBOX_WITH_DEBUGGER
680static FNDBGCCMD pgmR3CmdError;
681static FNDBGCCMD pgmR3CmdSync;
682static FNDBGCCMD pgmR3CmdSyncAlways;
683# ifdef VBOX_STRICT
684static FNDBGCCMD pgmR3CmdAssertCR3;
685# endif
686static FNDBGCCMD pgmR3CmdPhysToFile;
687#endif
688
689
690/*********************************************************************************************************************************
691* Global Variables *
692*********************************************************************************************************************************/
693#ifdef VBOX_WITH_DEBUGGER
694/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
695static const DBGCVARDESC g_aPgmErrorArgs[] =
696{
697 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
698 { 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
699};
700
701static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
702{
703 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
704 { 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
705 { 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
706};
707
708# ifdef DEBUG_sandervl
709static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
710{
711 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
712 { 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
713 { 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
714};
715# endif
716
717/** Command descriptors. */
718static const DBGCCMD g_aCmds[] =
719{
720 /* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
721 { "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
722 { "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
723 { "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
724# ifdef VBOX_STRICT
725 { "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
726# ifdef VBOX_WITH_PAGE_SHARING
727 { "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
728 { "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
729# endif
730# endif
731 { "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
732 { "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
733};
734#endif
735
736
737
738
739/**
740 * Initiates the paging of VM.
741 *
742 * @returns VBox status code.
743 * @param pVM The cross context VM structure.
744 */
745VMMR3DECL(int) PGMR3Init(PVM pVM)
746{
747 LogFlow(("PGMR3Init:\n"));
748 PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
749 int rc;
750
751 /*
752 * Assert alignment and sizes.
753 */
754 AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
755 AssertCompile(sizeof(pVM->apCpusR3[0]->pgm.s) <= sizeof(pVM->apCpusR3[0]->pgm.padding));
756 AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
757
758 /*
759 * Init the structure.
760 */
761 pVM->pgm.s.offVM = RT_UOFFSETOF(VM, pgm.s);
762 pVM->pgm.s.offVCpuPGM = RT_UOFFSETOF(VMCPU, pgm.s);
763 /*pVM->pgm.s.fRestoreRomPagesAtReset = false;*/
764
765 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
766 {
767 pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
768 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
769 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
770 }
771
772 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
773 {
774 pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
775 pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
776 pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
777 }
778
779 /* Init the per-CPU part. */
780 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
781 {
782 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
783 PPGMCPU pPGM = &pVCpu->pgm.s;
784
785 pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
786 pPGM->offVCpu = RT_UOFFSETOF(VMCPU, pgm.s);
787 pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
788
789 pPGM->enmShadowMode = PGMMODE_INVALID;
790 pPGM->enmGuestMode = PGMMODE_INVALID;
791 pPGM->idxGuestModeData = UINT8_MAX;
792 pPGM->idxShadowModeData = UINT8_MAX;
793 pPGM->idxBothModeData = UINT8_MAX;
794
795 pPGM->GCPhysCR3 = NIL_RTGCPHYS;
796
797 pPGM->pGst32BitPdR3 = NULL;
798 pPGM->pGstPaePdptR3 = NULL;
799 pPGM->pGstAmd64Pml4R3 = NULL;
800#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
801 pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
802 pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
803 pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
804#endif
805 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
806 {
807 pPGM->apGstPaePDsR3[i] = NULL;
808#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
809 pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
810#endif
811 pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
812 pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
813 pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
814 }
815
816 pPGM->fA20Enabled = true;
817 pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
818 }
819
820 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
821 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
822 pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
823
824 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
825#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
826 true
827#else
828 false
829#endif
830 );
831 AssertLogRelRCReturn(rc, rc);
832
833#if HC_ARCH_BITS == 32
834# ifdef RT_OS_DARWIN
835 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
836# else
837 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
838# endif
839#else
840 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
841#endif
842 AssertLogRelRCReturn(rc, rc);
843 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
844 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
845
846 /*
847 * Get the configured RAM size - to estimate saved state size.
848 */
849 uint64_t cbRam;
850 rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
851 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
852 cbRam = 0;
853 else if (RT_SUCCESS(rc))
854 {
855 if (cbRam < PAGE_SIZE)
856 cbRam = 0;
857 cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
858 }
859 else
860 {
861 AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
862 return rc;
863 }
864
865 /*
866 * Check for PCI pass-through and other configurables.
867 */
868 rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
869 AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
870 AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough || pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
871
872 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "PageFusionAllowed", &pVM->pgm.s.fPageFusionAllowed, false);
873 AssertLogRelRCReturn(rc, rc);
874
875 /** @cfgm{/PGM/ZeroRamPagesOnReset, boolean, true}
876 * Whether to clear RAM pages on (hard) reset. */
877 rc = CFGMR3QueryBoolDef(pCfgPGM, "ZeroRamPagesOnReset", &pVM->pgm.s.fZeroRamPagesOnReset, true);
878 AssertLogRelRCReturn(rc, rc);
879
880#ifdef VBOX_WITH_STATISTICS
881 /*
882 * Allocate memory for the statistics before someone tries to use them.
883 */
884 size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
885 void *pv;
886 rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
887 AssertRCReturn(rc, rc);
888
889 pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
890 pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
891 pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
892
893 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
894 {
895 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
896 pVCpu->pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
897 pVCpu->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
898
899 pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
900 }
901#endif /* VBOX_WITH_STATISTICS */
902
903 /*
904 * Register callbacks, string formatters and the saved state data unit.
905 */
906#ifdef VBOX_STRICT
907 VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
908#endif
909 PGMRegisterStringFormatTypes();
910
911 rc = pgmR3InitSavedState(pVM, cbRam);
912 if (RT_FAILURE(rc))
913 return rc;
914
915 /*
916 * Initialize the PGM critical section and flush the phys TLBs
917 */
918 rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
919 AssertRCReturn(rc, rc);
920
921 PGMR3PhysChunkInvalidateTLB(pVM);
922 pgmPhysInvalidatePageMapTLB(pVM);
923
924 /*
925 * For the time being we sport a full set of handy pages in addition to the base
926 * memory to simplify things.
927 */
928 rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
929 AssertRCReturn(rc, rc);
930
931 /*
932 * Trees
933 */
934 rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
935 if (RT_SUCCESS(rc))
936 pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
937
938 /*
939 * Allocate the zero page.
940 */
941 if (RT_SUCCESS(rc))
942 {
943 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
944 if (RT_SUCCESS(rc))
945 {
946 pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
947 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
948 pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
949 AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
950 }
951 }
952
953 /*
954 * Allocate the invalid MMIO page.
955 * (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
956 */
957 if (RT_SUCCESS(rc))
958 {
959 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
960 if (RT_SUCCESS(rc))
961 {
962 ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
963 pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
964 AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
965 pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
966 }
967 }
968
969 /*
970 * Register the physical access handler protecting ROMs.
971 */
972 if (RT_SUCCESS(rc))
973 rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE,
974 pgmPhysRomWriteHandler,
975 NULL, NULL, "pgmPhysRomWritePfHandler",
976 NULL, NULL, "pgmPhysRomWritePfHandler",
977 "ROM write protection",
978 &pVM->pgm.s.hRomPhysHandlerType);
979
980 /*
981 * Init the paging.
982 */
983 if (RT_SUCCESS(rc))
984 rc = pgmR3InitPaging(pVM);
985
986 /*
987 * Init the page pool.
988 */
989 if (RT_SUCCESS(rc))
990 rc = pgmR3PoolInit(pVM);
991
992 if (RT_SUCCESS(rc))
993 {
994 for (VMCPUID i = 0; i < pVM->cCpus; i++)
995 {
996 PVMCPU pVCpu = pVM->apCpusR3[i];
997 rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
998 if (RT_FAILURE(rc))
999 break;
1000 }
1001 }
1002
1003 if (RT_SUCCESS(rc))
1004 {
1005 /*
1006 * Info & statistics
1007 */
1008 DBGFR3InfoRegisterInternalEx(pVM, "mode",
1009 "Shows the current paging mode. "
1010 "Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1011 pgmR3InfoMode,
1012 DBGFINFO_FLAGS_ALL_EMTS);
1013 DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1014 "Dumps all the entries in the top level paging table. No arguments.",
1015 pgmR3InfoCr3);
1016 DBGFR3InfoRegisterInternal(pVM, "phys",
1017 "Dumps all the physical address ranges. Pass 'verbose' to get more details.",
1018 pgmR3PhysInfo);
1019 DBGFR3InfoRegisterInternal(pVM, "handlers",
1020 "Dumps physical, virtual and hyper virtual handlers. "
1021 "Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1022 "Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1023 pgmR3InfoHandlers);
1024#ifndef PGM_WITHOUT_MAPPINGS
1025 DBGFR3InfoRegisterInternal(pVM, "mappings",
1026 "Dumps guest mappings.",
1027 pgmR3MapInfo);
1028#endif
1029
1030 pgmR3InitStats(pVM);
1031
1032#ifdef VBOX_WITH_DEBUGGER
1033 /*
1034 * Debugger commands.
1035 */
1036 static bool s_fRegisteredCmds = false;
1037 if (!s_fRegisteredCmds)
1038 {
1039 int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1040 if (RT_SUCCESS(rc2))
1041 s_fRegisteredCmds = true;
1042 }
1043#endif
1044 return VINF_SUCCESS;
1045 }
1046
1047 /* Almost no cleanup necessary, MM frees all memory. */
1048 PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1049
1050 return rc;
1051}
1052
1053
1054/**
1055 * Init paging.
1056 *
1057 * Since we need to check what mode the host is operating in before we can choose
1058 * the right paging functions for the host we have to delay this until R0 has
1059 * been initialized.
1060 *
1061 * @returns VBox status code.
1062 * @param pVM The cross context VM structure.
1063 */
1064static int pgmR3InitPaging(PVM pVM)
1065{
1066 /*
1067 * Force a recalculation of modes and switcher so everyone gets notified.
1068 */
1069 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1070 {
1071 PVMCPU pVCpu = pVM->apCpusR3[i];
1072
1073 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1074 pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1075 pVCpu->pgm.s.idxGuestModeData = UINT8_MAX;
1076 pVCpu->pgm.s.idxShadowModeData = UINT8_MAX;
1077 pVCpu->pgm.s.idxBothModeData = UINT8_MAX;
1078 }
1079
1080 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1081
1082#ifndef PGM_WITHOUT_MAPPINGS
1083 /*
1084 * Allocate static mapping space for whatever the cr3 register
1085 * points to and in the case of PAE mode to the 4 PDs.
1086 */
1087 int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1088 if (RT_FAILURE(rc))
1089 {
1090 AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1091 return rc;
1092 }
1093 MMR3HyperReserveFence(pVM);
1094#endif
1095
1096#if 0
1097 /*
1098 * Allocate pages for the three possible intermediate contexts
1099 * (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1100 * for the sake of simplicity. The AMD64 uses the PAE for the
1101 * lower levels, making the total number of pages 11 (3 + 7 + 1).
1102 *
1103 * We assume that two page tables will be enought for the core code
1104 * mappings (HC virtual and identity).
1105 */
1106 pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1107 pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1108 pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1109 pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1110 pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1111 pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1112 pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1113 pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1114 pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1115 pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1116 pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1117 pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1118
1119 pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1120 AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1121 pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1122 AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1123 pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1124 AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1125
1126 /*
1127 * Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1128 */
1129 ASMMemZeroPage(pVM->pgm.s.pInterPD);
1130 ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1131 ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1132
1133 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1134 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1135
1136 ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1137 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1138 {
1139 ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1140 pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P | PGM_PLXFLAGS_PERMANENT
1141 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1142 }
1143
1144 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1145 {
1146 const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1147 pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A | PGM_PLXFLAGS_PERMANENT
1148 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1149 }
1150
1151 RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1152 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1153 pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A | PGM_PLXFLAGS_PERMANENT
1154 | HCPhysInterPaePDPT64;
1155#endif
1156
1157 /*
1158 * Initialize paging workers and mode from current host mode
1159 * and the guest running in real mode.
1160 */
1161 pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1162 switch (pVM->pgm.s.enmHostMode)
1163 {
1164 case SUPPAGINGMODE_32_BIT:
1165 case SUPPAGINGMODE_32_BIT_GLOBAL:
1166 case SUPPAGINGMODE_PAE:
1167 case SUPPAGINGMODE_PAE_GLOBAL:
1168 case SUPPAGINGMODE_PAE_NX:
1169 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1170 break;
1171
1172 case SUPPAGINGMODE_AMD64:
1173 case SUPPAGINGMODE_AMD64_GLOBAL:
1174 case SUPPAGINGMODE_AMD64_NX:
1175 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1176 if (ARCH_BITS != 64)
1177 {
1178 AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1179 LogRel(("PGM: Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1180 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1181 }
1182 break;
1183 default:
1184 AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1185 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1186 }
1187
1188 LogFlow(("pgmR3InitPaging: returns successfully\n"));
1189#if HC_ARCH_BITS == 64 && 0
1190 LogRel(("PGM: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1191 pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1192 LogRel(("PGM: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1193 MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1194 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1195 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1196 MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1197#endif
1198
1199 /*
1200 * Log the host paging mode. It may come in handy.
1201 */
1202 const char *pszHostMode;
1203 switch (pVM->pgm.s.enmHostMode)
1204 {
1205 case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1206 case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1207 case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1208 case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1209 case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1210 case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1211 case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1212 case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1213 case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1214 case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1215 default: pszHostMode = "???"; break;
1216 }
1217 LogRel(("PGM: Host paging mode: %s\n", pszHostMode));
1218
1219 return VINF_SUCCESS;
1220}
1221
1222
1223/**
1224 * Init statistics
1225 * @returns VBox status code.
1226 */
1227static int pgmR3InitStats(PVM pVM)
1228{
1229 PPGM pPGM = &pVM->pgm.s;
1230 int rc;
1231
1232 /*
1233 * Release statistics.
1234 */
1235 /* Common - misc variables */
1236 STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1237 STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1238 STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1239 STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1240 STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1241 STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1242 STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1243 STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1244 STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1245 STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1246 STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1247 STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1248 STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1249 STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1250 STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1251 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1252 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1253 STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1254 STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1255
1256 STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1257 STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1258 STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1259
1260 STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1261
1262 /* Live save */
1263 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1264 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1265 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1266 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1267 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1268 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1269 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1270 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1271 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1272 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1273 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1274 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1275 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1276 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1277 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1278 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1279 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1280 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1281
1282#ifdef VBOX_WITH_STATISTICS
1283
1284# define PGM_REG_COUNTER(a, b, c) \
1285 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1286 AssertRC(rc);
1287
1288# define PGM_REG_COUNTER_BYTES(a, b, c) \
1289 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1290 AssertRC(rc);
1291
1292# define PGM_REG_PROFILE(a, b, c) \
1293 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1294 AssertRC(rc);
1295
1296 PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1297
1298 PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1299 PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1300 PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1301 PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1302 PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1303
1304 PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1305 PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1306 PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1307 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1308 PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1309 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1310 PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1311 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1312 PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1313 PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1314
1315 PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1316 PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1317 PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1318 PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1319 PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1320 PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1321
1322 PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1323 PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1324 PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1325 PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1326 PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1327 PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1328 PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1329 PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1330
1331 PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1332 PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1333 PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1334 PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1335
1336 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1337 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1338 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1339 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1340 PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1341 PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1342
1343 PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1344 PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1345/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1346 PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1347 PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1348/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1349
1350 PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1351 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1352 PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1353 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1354 PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1355 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1356 PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1357 PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1358
1359 /* GC only: */
1360 PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1361 PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1362
1363 PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1364 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1365 PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1366 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1367 PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1368 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1369 PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1370 PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1371
1372 PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1373 PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1374 PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1375 PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1376 PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1377 PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1378 PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1379
1380# undef PGM_REG_COUNTER
1381# undef PGM_REG_PROFILE
1382#endif
1383
1384 /*
1385 * Note! The layout below matches the member layout exactly!
1386 */
1387
1388 /*
1389 * Common - stats
1390 */
1391 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1392 {
1393 PPGMCPU pPgmCpu = &pVM->apCpusR3[idCpu]->pgm.s;
1394
1395#define PGM_REG_COUNTER(a, b, c) \
1396 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1397 AssertRC(rc);
1398#define PGM_REG_PROFILE(a, b, c) \
1399 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1400 AssertRC(rc);
1401
1402 PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1403 PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1404
1405#ifdef VBOX_WITH_STATISTICS
1406 PGMCPUSTATS *pCpuStats = pVM->apCpusR3[idCpu]->pgm.s.pStatsR3;
1407
1408# if 0 /* rarely useful; leave for debugging. */
1409 for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1410 STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1411 "The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1412 for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1413 STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1414 "The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1415# endif
1416 /* R0 only: */
1417 PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1418 PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1419
1420 /* RZ only: */
1421 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1422 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1423 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1424 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1425 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1426 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1427 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1428 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1429 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1430 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1431 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1432 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1433 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1434 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1435 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1436 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1437 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsHack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USHack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled.");
1438 PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsUnhack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USUnhack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled.");
1439 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1440 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1441 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1442 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1443 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1444 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1445 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1446 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1447 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1448 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1449 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1450 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1451 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1452 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1453 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1454 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1455 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1456 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1457 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1458 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1459 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1460 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1461 PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1462#if 0 /* rarely useful; leave for debugging. */
1463 for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1464 STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1465 "The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1466#endif
1467 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1468 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1469 PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1470 PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1471 PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1472
1473 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1474 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1475 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1476 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1477 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1478 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1479 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1480 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1481 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1482 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1483 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1484 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1485 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1486 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1487 PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1488 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1489 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1490 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1491 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1492 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1493 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1494 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1495 //PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1496 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1497 PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1498 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1499 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1500 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1501 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1502 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1503 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1504 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1505 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1506 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1507 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1508 PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1509
1510 /* HC only: */
1511
1512 /* RZ & R3: */
1513 PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1514 PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1515 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1516 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1517 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1518 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1519 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1520 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1521 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1522 PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1523 PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1524 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1525 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1526 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1527 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1528 PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1529 PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1530 PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1531 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1532 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1533 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1534 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1535 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1536 PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1537 PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1538 PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1539 PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1540 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1541 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1542 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1543 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1544 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1545 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1546 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1547 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSizeChanges, "/PGM/CPU%u/RZ/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
1548 PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1549 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1550 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1551 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1552 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1553 PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1554 PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1555 PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1556 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1557 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1558 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1559 PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1560 PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1561
1562 PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1563 PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1564 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1565 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1566 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1567 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1568 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1569 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1570 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1571 PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1572 PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1573 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1574 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1575 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1576 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1577 PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1578 PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1579 PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1580 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1581 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1582 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1583 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1584 PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1585 PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1586 PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1587 PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1588 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1589 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1590 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1591 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1592 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1593 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1594 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1595 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSizeChanges, "/PGM/CPU%u/R3/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
1596 PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1597 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1598 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1599 PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1600 PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1601 PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1602 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1603 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1604 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1605 PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1606 PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1607#endif /* VBOX_WITH_STATISTICS */
1608
1609#undef PGM_REG_PROFILE
1610#undef PGM_REG_COUNTER
1611
1612 }
1613
1614 return VINF_SUCCESS;
1615}
1616
1617
1618/**
1619 * Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1620 *
1621 * The dynamic mapping area will also be allocated and initialized at this
1622 * time. We could allocate it during PGMR3Init of course, but the mapping
1623 * wouldn't be allocated at that time preventing us from setting up the
1624 * page table entries with the dummy page.
1625 *
1626 * @returns VBox status code.
1627 * @param pVM The cross context VM structure.
1628 */
1629VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1630{
1631#ifndef PGM_WITHOUT_MAPPINGS
1632 RTGCPTR GCPtr;
1633 int rc;
1634
1635 /*
1636 * Reserve space for the dynamic mappings.
1637 */
1638 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1639 if (RT_SUCCESS(rc))
1640 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1641
1642 if ( RT_SUCCESS(rc)
1643 && (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1644 {
1645 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1646 if (RT_SUCCESS(rc))
1647 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1648 }
1649 if (RT_SUCCESS(rc))
1650 {
1651 AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1652 MMR3HyperReserveFence(pVM);
1653 }
1654 return rc;
1655#else
1656 RT_NOREF(pVM);
1657 return VINF_SUCCESS;
1658#endif
1659}
1660
1661
1662/**
1663 * Ring-3 init finalizing.
1664 *
1665 * @returns VBox status code.
1666 * @param pVM The cross context VM structure.
1667 */
1668VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1669{
1670#ifndef PGM_WITHOUT_MAPPINGS
1671 int rc = VERR_IPE_UNINITIALIZED_STATUS; /* (MSC incorrectly thinks it can be used uninitialized) */
1672
1673 /*
1674 * Reserve space for the dynamic mappings.
1675 * Initialize the dynamic mapping pages with dummy pages to simply the cache.
1676 */
1677 /* get the pointer to the page table entries. */
1678 PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1679 AssertRelease(pMapping);
1680 const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1681 const unsigned iPT = off >> X86_PD_SHIFT;
1682 const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1683 pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1684 pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1685
1686 /* init cache area */
1687 RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1688 for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
1689 {
1690 rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
1691 AssertRCReturn(rc, rc);
1692 }
1693#endif
1694
1695 /*
1696 * Determine the max physical address width (MAXPHYADDR) and apply it to
1697 * all the mask members and stuff.
1698 */
1699 uint32_t cMaxPhysAddrWidth;
1700 uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
1701 if ( uMaxExtLeaf >= 0x80000008
1702 && uMaxExtLeaf <= 0x80000fff)
1703 {
1704 cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
1705 LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
1706 cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
1707 pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
1708 for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
1709 pVM->pgm.s.HCPhysInvMmioPg |= RT_BIT_64(iBit);
1710 }
1711 else
1712 {
1713 LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
1714 cMaxPhysAddrWidth = 48;
1715 pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
1716 pVM->pgm.s.HCPhysInvMmioPg |= UINT64_C(0x000f0000000000);
1717 }
1718
1719 /** @todo query from CPUM. */
1720 pVM->pgm.s.GCPhysInvAddrMask = 0;
1721 for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
1722 pVM->pgm.s.GCPhysInvAddrMask |= RT_BIT_64(iBit);
1723
1724 /*
1725 * Initialize the invalid paging entry masks, assuming NX is disabled.
1726 */
1727 uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
1728 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1729 {
1730 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1731
1732 /** @todo The manuals are not entirely clear whether the physical
1733 * address width is relevant. See table 5-9 in the intel
1734 * manual vs the PDE4M descriptions. Write testcase (NP). */
1735 pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
1736 | X86_PDE4M_MBZ_MASK;
1737
1738 pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask | X86_PTE_PAE_MBZ_MASK_NO_NX;
1739 pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask | X86_PDE_PAE_MBZ_MASK_NO_NX;
1740 pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask | X86_PDE2M_PAE_MBZ_MASK_NO_NX;
1741 pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask | X86_PDPE_PAE_MBZ_MASK;
1742
1743 pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask | X86_PTE_LM_MBZ_MASK_NO_NX;
1744 pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask | X86_PDE_LM_MBZ_MASK_NX;
1745 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask | X86_PDE2M_LM_MBZ_MASK_NX;
1746 pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask | X86_PDPE_LM_MBZ_MASK_NO_NX;
1747 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask | X86_PDPE1G_LM_MBZ_MASK_NO_NX;
1748 pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask | X86_PML4E_MBZ_MASK_NO_NX;
1749
1750 pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_G | X86_PTE_A | X86_PTE_D;
1751 pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_A;
1752 pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A;
1753 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
1754 X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_G | X86_PDE4M_A | X86_PDE4M_D;
1755 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A;
1756 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
1757 }
1758
1759 /*
1760 * Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1761 * Intel only goes up to 36 bits, so we stick to 36 as well.
1762 * Update: More recent intel manuals specifies 40 bits just like AMD.
1763 */
1764 uint32_t u32Dummy, u32Features;
1765 CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1766 if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1767 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
1768 else
1769 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1770
1771 /*
1772 * Allocate memory if we're supposed to do that.
1773 */
1774#ifdef PGM_WITHOUT_MAPPINGS
1775 int rc = VINF_SUCCESS;
1776#endif
1777 if (pVM->pgm.s.fRamPreAlloc)
1778 rc = pgmR3PhysRamPreAllocate(pVM);
1779
1780 //pgmLogState(pVM);
1781 LogRel(("PGM: PGMR3InitFinalize: 4 MB PSE mask %RGp -> %Rrc\n", pVM->pgm.s.GCPhys4MBPSEMask, rc));
1782 return rc;
1783}
1784
1785
1786/**
1787 * Init phase completed callback.
1788 *
1789 * @returns VBox status code.
1790 * @param pVM The cross context VM structure.
1791 * @param enmWhat What has been completed.
1792 * @thread EMT(0)
1793 */
1794VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1795{
1796 switch (enmWhat)
1797 {
1798 case VMINITCOMPLETED_HM:
1799#ifdef VBOX_WITH_PCI_PASSTHROUGH
1800 if (pVM->pgm.s.fPciPassthrough)
1801 {
1802 AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
1803 AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
1804 AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
1805
1806 /*
1807 * Report assignments to the IOMMU (hope that's good enough for now).
1808 */
1809 if (pVM->pgm.s.fPciPassthrough)
1810 {
1811 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
1812 AssertRCReturn(rc, rc);
1813 }
1814 }
1815#else
1816 AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
1817#endif
1818 break;
1819
1820 default:
1821 /* shut up gcc */
1822 break;
1823 }
1824
1825 return VINF_SUCCESS;
1826}
1827
1828
1829/**
1830 * Applies relocations to data and code managed by this component.
1831 *
1832 * This function will be called at init and whenever the VMM need to relocate it
1833 * self inside the GC.
1834 *
1835 * @param pVM The cross context VM structure.
1836 * @param offDelta Relocation delta relative to old location.
1837 */
1838VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1839{
1840 LogFlow(("PGMR3Relocate: offDelta=%RGv\n", offDelta));
1841
1842 /*
1843 * Paging stuff.
1844 */
1845
1846 /* Shadow, guest and both mode switch & relocation for each VCPU. */
1847 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1848 {
1849 PVMCPU pVCpu = pVM->apCpusR3[i];
1850
1851 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1852 if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
1853 && g_aPgmShadowModeData[idxShw].pfnRelocate)
1854 g_aPgmShadowModeData[idxShw].pfnRelocate(pVCpu, offDelta);
1855 else
1856 AssertFailed();
1857
1858 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1859 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1860 && g_aPgmGuestModeData[idxGst].pfnRelocate)
1861 g_aPgmGuestModeData[idxGst].pfnRelocate(pVCpu, offDelta);
1862 else
1863 AssertFailed();
1864 }
1865
1866 /*
1867 * Ram ranges.
1868 */
1869 if (pVM->pgm.s.pRamRangesXR3)
1870 pgmR3PhysRelinkRamRanges(pVM);
1871
1872#ifndef PGM_WITHOUT_MAPPINGS
1873
1874 /*
1875 * Update the two page directories with all page table mappings.
1876 * (One or more of them have changed, that's why we're here.)
1877 */
1878 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1879 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1880 pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1881
1882 /* Relocate GC addresses of Page Tables. */
1883 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1884 {
1885 for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1886 {
1887 pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1888 pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1889 }
1890 }
1891
1892 /*
1893 * Dynamic page mapping area.
1894 */
1895 pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1896 pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1897 pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1898
1899 if (pVM->pgm.s.pRCDynMap)
1900 {
1901 pVM->pgm.s.pRCDynMap += offDelta;
1902 PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
1903
1904 pDynMap->paPages += offDelta;
1905 PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
1906
1907 for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
1908 {
1909 paPages[iPage].pvPage += offDelta;
1910 paPages[iPage].uPte.pLegacy += offDelta;
1911 paPages[iPage].uPte.pPae += offDelta;
1912 }
1913 }
1914
1915#endif /* PGM_WITHOUT_MAPPINGS */
1916
1917 /*
1918 * The Zero page.
1919 */
1920 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1921 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
1922
1923 /*
1924 * The page pool.
1925 */
1926 pgmR3PoolRelocate(pVM);
1927}
1928
1929
1930/**
1931 * Resets a virtual CPU when unplugged.
1932 *
1933 * @param pVM The cross context VM structure.
1934 * @param pVCpu The cross context virtual CPU structure.
1935 */
1936VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1937{
1938 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1939 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1940 && g_aPgmGuestModeData[idxGst].pfnExit)
1941 {
1942 int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
1943 AssertReleaseRC(rc);
1944 }
1945 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1946
1947 int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1948 AssertReleaseRC(rc);
1949
1950 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
1951
1952 pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
1953
1954 /*
1955 * Re-init other members.
1956 */
1957 pVCpu->pgm.s.fA20Enabled = true;
1958 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
1959
1960 /*
1961 * Clear the FFs PGM owns.
1962 */
1963 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1964 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1965}
1966
1967
1968/**
1969 * The VM is being reset.
1970 *
1971 * For the PGM component this means that any PD write monitors
1972 * needs to be removed.
1973 *
1974 * @param pVM The cross context VM structure.
1975 */
1976VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
1977{
1978 LogFlow(("PGMR3Reset:\n"));
1979 VM_ASSERT_EMT(pVM);
1980
1981 pgmLock(pVM);
1982
1983 /*
1984 * Unfix any fixed mappings and disable CR3 monitoring.
1985 */
1986 pVM->pgm.s.fMappingsFixed = false;
1987 pVM->pgm.s.fMappingsFixedRestored = false;
1988 pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
1989 pVM->pgm.s.cbMappingFixed = 0;
1990
1991 /*
1992 * Exit the guest paging mode before the pgm pool gets reset.
1993 * Important to clean up the amd64 case.
1994 */
1995 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1996 {
1997 PVMCPU pVCpu = pVM->apCpusR3[i];
1998 uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1999 if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
2000 && g_aPgmGuestModeData[idxGst].pfnExit)
2001 {
2002 int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
2003 AssertReleaseRC(rc);
2004 }
2005 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2006 }
2007
2008#ifdef DEBUG
2009 DBGFR3_INFO_LOG_SAFE(pVM, "mappings", NULL);
2010 DBGFR3_INFO_LOG_SAFE(pVM, "handlers", "all nostat");
2011#endif
2012
2013 /*
2014 * Switch mode back to real mode. (Before resetting the pgm pool!)
2015 */
2016 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2017 {
2018 PVMCPU pVCpu = pVM->apCpusR3[i];
2019
2020 int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
2021 AssertReleaseRC(rc);
2022
2023 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2024 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2025 }
2026
2027 /*
2028 * Reset the shadow page pool.
2029 */
2030 pgmR3PoolReset(pVM);
2031
2032 /*
2033 * Re-init various other members and clear the FFs that PGM owns.
2034 */
2035 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2036 {
2037 PVMCPU pVCpu = pVM->apCpusR3[i];
2038
2039 pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2040 PGMNotifyNxeChanged(pVCpu, false);
2041
2042 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2043 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2044
2045 if (!pVCpu->pgm.s.fA20Enabled)
2046 {
2047 pVCpu->pgm.s.fA20Enabled = true;
2048 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2049#ifdef PGM_WITH_A20
2050 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2051 pgmR3RefreshShadowModeAfterA20Change(pVCpu);
2052 HMFlushTlb(pVCpu);
2053#endif
2054 }
2055 }
2056
2057 //pgmLogState(pVM);
2058 pgmUnlock(pVM);
2059}
2060
2061
2062/**
2063 * Memory setup after VM construction or reset.
2064 *
2065 * @param pVM The cross context VM structure.
2066 * @param fAtReset Indicates the context, after reset if @c true or after
2067 * construction if @c false.
2068 */
2069VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
2070{
2071 if (fAtReset)
2072 {
2073 pgmLock(pVM);
2074
2075 int rc = pgmR3PhysRamZeroAll(pVM);
2076 AssertReleaseRC(rc);
2077
2078 rc = pgmR3PhysRomReset(pVM);
2079 AssertReleaseRC(rc);
2080
2081 pgmUnlock(pVM);
2082 }
2083}
2084
2085
2086#ifdef VBOX_STRICT
2087/**
2088 * VM state change callback for clearing fNoMorePhysWrites after
2089 * a snapshot has been created.
2090 */
2091static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2092{
2093 if ( enmState == VMSTATE_RUNNING
2094 || enmState == VMSTATE_RESUMING)
2095 pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2096 NOREF(enmOldState); NOREF(pvUser);
2097}
2098#endif
2099
2100/**
2101 * Private API to reset fNoMorePhysWrites.
2102 */
2103VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2104{
2105 pVM->pgm.s.fNoMorePhysWrites = false;
2106}
2107
2108/**
2109 * Terminates the PGM.
2110 *
2111 * @returns VBox status code.
2112 * @param pVM The cross context VM structure.
2113 */
2114VMMR3DECL(int) PGMR3Term(PVM pVM)
2115{
2116 /* Must free shared pages here. */
2117 pgmLock(pVM);
2118 pgmR3PhysRamTerm(pVM);
2119 pgmR3PhysRomTerm(pVM);
2120 pgmUnlock(pVM);
2121
2122 PGMDeregisterStringFormatTypes();
2123 return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2124}
2125
2126
2127/**
2128 * Show paging mode.
2129 *
2130 * @param pVM The cross context VM structure.
2131 * @param pHlp The info helpers.
2132 * @param pszArgs "all" (default), "guest", "shadow" or "host".
2133 */
2134static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2135{
2136 /* digest argument. */
2137 bool fGuest, fShadow, fHost;
2138 if (pszArgs)
2139 pszArgs = RTStrStripL(pszArgs);
2140 if (!pszArgs || !*pszArgs || strstr(pszArgs, "all"))
2141 fShadow = fHost = fGuest = true;
2142 else
2143 {
2144 fShadow = fHost = fGuest = false;
2145 if (strstr(pszArgs, "guest"))
2146 fGuest = true;
2147 if (strstr(pszArgs, "shadow"))
2148 fShadow = true;
2149 if (strstr(pszArgs, "host"))
2150 fHost = true;
2151 }
2152
2153 PVMCPU pVCpu = VMMGetCpu(pVM);
2154 if (!pVCpu)
2155 pVCpu = pVM->apCpusR3[0];
2156
2157
2158 /* print info. */
2159 if (fGuest)
2160 pHlp->pfnPrintf(pHlp, "Guest paging mode (VCPU #%u): %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2161 pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmGuestMode), pVCpu->pgm.s.cGuestModeChanges.c,
2162 pVCpu->pgm.s.fA20Enabled ? "enabled" : "disabled", pVCpu->pgm.s.cA20Changes.c);
2163 if (fShadow)
2164 pHlp->pfnPrintf(pHlp, "Shadow paging mode (VCPU #%u): %s\n", pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmShadowMode));
2165 if (fHost)
2166 {
2167 const char *psz;
2168 switch (pVM->pgm.s.enmHostMode)
2169 {
2170 case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2171 case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2172 case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2173 case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2174 case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2175 case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2176 case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2177 case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2178 case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2179 case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2180 case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2181 default: psz = "unknown"; break;
2182 }
2183 pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2184 }
2185}
2186
2187
2188/**
2189 * Dump registered MMIO ranges to the log.
2190 *
2191 * @param pVM The cross context VM structure.
2192 * @param pHlp The info helpers.
2193 * @param pszArgs Arguments, ignored.
2194 */
2195static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2196{
2197 bool const fVerbose = pszArgs && strstr(pszArgs, "verbose") != NULL;
2198
2199 pHlp->pfnPrintf(pHlp,
2200 "RAM ranges (pVM=%p)\n"
2201 "%.*s %.*s\n",
2202 pVM,
2203 sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2204 sizeof(RTHCPTR) * 2, "pvHC ");
2205
2206 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2207 {
2208 pHlp->pfnPrintf(pHlp,
2209 "%RGp-%RGp %RHv %s\n",
2210 pCur->GCPhys,
2211 pCur->GCPhysLast,
2212 pCur->pvR3,
2213 pCur->pszDesc);
2214 if (fVerbose)
2215 {
2216 RTGCPHYS const cPages = pCur->cb >> X86_PAGE_SHIFT;
2217 RTGCPHYS iPage = 0;
2218 while (iPage < cPages)
2219 {
2220 RTGCPHYS const iFirstPage = iPage;
2221 PGMPAGETYPE const enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]);
2222 do
2223 iPage++;
2224 while (iPage < cPages && (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == enmType);
2225 const char *pszType;
2226 const char *pszMore = NULL;
2227 switch (enmType)
2228 {
2229 case PGMPAGETYPE_RAM:
2230 pszType = "RAM";
2231 break;
2232
2233 case PGMPAGETYPE_MMIO2:
2234 pszType = "MMIO2";
2235 break;
2236
2237 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2238 pszType = "MMIO2-alias-MMIO";
2239 break;
2240
2241 case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2242 pszType = "special-alias-MMIO";
2243 break;
2244
2245 case PGMPAGETYPE_ROM_SHADOW:
2246 case PGMPAGETYPE_ROM:
2247 {
2248 pszType = enmType == PGMPAGETYPE_ROM_SHADOW ? "ROM-shadowed" : "ROM";
2249
2250 RTGCPHYS const GCPhysFirstPg = iFirstPage * X86_PAGE_SIZE;
2251 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2252 while (pRom && GCPhysFirstPg > pRom->GCPhysLast)
2253 pRom = pRom->pNextR3;
2254 if (pRom && GCPhysFirstPg - pRom->GCPhys < pRom->cb)
2255 pszMore = pRom->pszDesc;
2256 break;
2257 }
2258
2259 case PGMPAGETYPE_MMIO:
2260 {
2261 pszType = "MMIO";
2262 pgmLock(pVM);
2263 PPGMPHYSHANDLER pHandler = pgmHandlerPhysicalLookup(pVM, iFirstPage * X86_PAGE_SIZE);
2264 if (pHandler)
2265 pszMore = pHandler->pszDesc;
2266 pgmUnlock(pVM);
2267 break;
2268 }
2269
2270 case PGMPAGETYPE_INVALID:
2271 pszType = "invalid";
2272 break;
2273
2274 default:
2275 pszType = "bad";
2276 break;
2277 }
2278 if (pszMore)
2279 pHlp->pfnPrintf(pHlp, " %RGp-%RGp %-20s %s\n",
2280 pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
2281 pCur->GCPhys + iPage * X86_PAGE_SIZE,
2282 pszType, pszMore);
2283 else
2284 pHlp->pfnPrintf(pHlp, " %RGp-%RGp %s\n",
2285 pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
2286 pCur->GCPhys + iPage * X86_PAGE_SIZE,
2287 pszType);
2288
2289 }
2290 }
2291 }
2292}
2293
2294
2295/**
2296 * Dump the page directory to the log.
2297 *
2298 * @param pVM The cross context VM structure.
2299 * @param pHlp The info helpers.
2300 * @param pszArgs Arguments, ignored.
2301 */
2302static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2303{
2304 /** @todo SMP support!! */
2305 PVMCPU pVCpu = pVM->apCpusR3[0];
2306
2307/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2308 /* Big pages supported? */
2309 const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2310
2311 /* Global pages supported? */
2312 const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2313
2314 NOREF(pszArgs);
2315
2316 /*
2317 * Get page directory addresses.
2318 */
2319 pgmLock(pVM);
2320 PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2321 Assert(pPDSrc);
2322
2323 /*
2324 * Iterate the page directory.
2325 */
2326 for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2327 {
2328 X86PDE PdeSrc = pPDSrc->a[iPD];
2329 if (PdeSrc.n.u1Present)
2330 {
2331 if (PdeSrc.b.u1Size && fPSE)
2332 pHlp->pfnPrintf(pHlp,
2333 "%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2334 iPD,
2335 pgmGstGet4MBPhysPage(pVM, PdeSrc),
2336 PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2337 else
2338 pHlp->pfnPrintf(pHlp,
2339 "%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2340 iPD,
2341 (RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2342 PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2343 }
2344 }
2345 pgmUnlock(pVM);
2346}
2347
2348
2349/**
2350 * Service a VMMCALLRING3_PGM_LOCK call.
2351 *
2352 * @returns VBox status code.
2353 * @param pVM The cross context VM structure.
2354 */
2355VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2356{
2357 int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2358 AssertRC(rc);
2359 return rc;
2360}
2361
2362
2363/**
2364 * Called by pgmPoolFlushAllInt prior to flushing the pool.
2365 *
2366 * @returns VBox status code, fully asserted.
2367 * @param pVCpu The cross context virtual CPU structure.
2368 */
2369int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
2370{
2371 /* Unmap the old CR3 value before flushing everything. */
2372 int rc = VINF_SUCCESS;
2373 uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
2374 if ( idxBth < RT_ELEMENTS(g_aPgmBothModeData)
2375 && g_aPgmBothModeData[idxBth].pfnMapCR3)
2376 {
2377 rc = g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
2378 AssertRC(rc);
2379 }
2380
2381 /* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
2382 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
2383 if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
2384 && g_aPgmShadowModeData[idxShw].pfnExit)
2385 {
2386 rc = g_aPgmShadowModeData[idxShw].pfnExit(pVCpu);
2387 AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
2388 }
2389
2390 Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
2391 return rc;
2392}
2393
2394
2395/**
2396 * Called by pgmPoolFlushAllInt after flushing the pool.
2397 *
2398 * @returns VBox status code, fully asserted.
2399 * @param pVM The cross context VM structure.
2400 * @param pVCpu The cross context virtual CPU structure.
2401 */
2402int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
2403{
2404 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
2405 int rc = PGMHCChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
2406 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2407 AssertRCReturn(rc, rc);
2408 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2409
2410 Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL || pVCpu->pgm.s.enmShadowMode == PGMMODE_NONE);
2411 AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED_32BIT
2412 || CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
2413 ("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
2414 return rc;
2415}
2416
2417
2418/**
2419 * Called by PGMR3PhysSetA20 after changing the A20 state.
2420 *
2421 * @param pVCpu The cross context virtual CPU structure.
2422 */
2423void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
2424{
2425 /** @todo Probably doing a bit too much here. */
2426 int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
2427 AssertReleaseRC(rc);
2428 rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
2429 AssertReleaseRC(rc);
2430}
2431
2432
2433#ifdef VBOX_WITH_DEBUGGER
2434
2435/**
2436 * @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
2437 */
2438static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2439{
2440 /*
2441 * Validate input.
2442 */
2443 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2444 PVM pVM = pUVM->pVM;
2445 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 || (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
2446
2447 if (!cArgs)
2448 {
2449 /*
2450 * Print the list of error injection locations with status.
2451 */
2452 DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
2453 DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
2454 }
2455 else
2456 {
2457 /*
2458 * String switch on where to inject the error.
2459 */
2460 bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
2461 const char *pszWhere = paArgs[0].u.pszString;
2462 if (!strcmp(pszWhere, "handy"))
2463 ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
2464 else
2465 return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
2466 DBGCCmdHlpPrintf(pCmdHlp, "done\n");
2467 }
2468 return VINF_SUCCESS;
2469}
2470
2471
2472/**
2473 * @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
2474 */
2475static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2476{
2477 /*
2478 * Validate input.
2479 */
2480 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2481 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2482 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
2483 if (!pVCpu)
2484 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
2485
2486 /*
2487 * Force page directory sync.
2488 */
2489 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2490
2491 int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
2492 if (RT_FAILURE(rc))
2493 return rc;
2494
2495 return VINF_SUCCESS;
2496}
2497
2498#ifdef VBOX_STRICT
2499
2500/**
2501 * EMT callback for pgmR3CmdAssertCR3.
2502 *
2503 * @returns VBox status code.
2504 * @param pUVM The user mode VM handle.
2505 * @param pcErrors Where to return the error count.
2506 */
2507static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
2508{
2509 PVM pVM = pUVM->pVM;
2510 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
2511 PVMCPU pVCpu = VMMGetCpu(pVM);
2512
2513 *pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
2514
2515 return VINF_SUCCESS;
2516}
2517
2518
2519/**
2520 * @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
2521 */
2522static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2523{
2524 /*
2525 * Validate input.
2526 */
2527 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2528 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2529
2530 int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
2531 if (RT_FAILURE(rc))
2532 return rc;
2533
2534 unsigned cErrors = 0;
2535 rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
2536 if (RT_FAILURE(rc))
2537 return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
2538 if (cErrors > 0)
2539 return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
2540 return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
2541}
2542
2543#endif /* VBOX_STRICT */
2544
2545/**
2546 * @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
2547 */
2548static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2549{
2550 /*
2551 * Validate input.
2552 */
2553 NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2554 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2555 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
2556 if (!pVCpu)
2557 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
2558
2559 /*
2560 * Force page directory sync.
2561 */
2562 int rc;
2563 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
2564 {
2565 ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
2566 rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
2567 }
2568 else
2569 {
2570 ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
2571 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2572 rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
2573 }
2574 return rc;
2575}
2576
2577
2578/**
2579 * @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
2580 */
2581static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2582{
2583 /*
2584 * Validate input.
2585 */
2586 NOREF(pCmd);
2587 DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2588 PVM pVM = pUVM->pVM;
2589 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 || cArgs == 2);
2590 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType == DBGCVAR_TYPE_STRING);
2591 if (cArgs == 2)
2592 {
2593 DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[1].enmType == DBGCVAR_TYPE_STRING);
2594 if (strcmp(paArgs[1].u.pszString, "nozero"))
2595 return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
2596 }
2597 bool fIncZeroPgs = cArgs < 2;
2598
2599 /*
2600 * Open the output file and get the ram parameters.
2601 */
2602 RTFILE hFile;
2603 int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE | RTFILE_O_CREATE_REPLACE | RTFILE_O_DENY_WRITE);
2604 if (RT_FAILURE(rc))
2605 return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
2606
2607 uint32_t cbRamHole = 0;
2608 CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
2609 uint64_t cbRam = 0;
2610 CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
2611 RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
2612
2613 /*
2614 * Dump the physical memory, page by page.
2615 */
2616 RTGCPHYS GCPhys = 0;
2617 char abZeroPg[PAGE_SIZE];
2618 RT_ZERO(abZeroPg);
2619
2620 pgmLock(pVM);
2621 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2622 pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
2623 pRam = pRam->pNextR3)
2624 {
2625 /* fill the gap */
2626 if (pRam->GCPhys > GCPhys && fIncZeroPgs)
2627 {
2628 while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
2629 {
2630 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
2631 GCPhys += PAGE_SIZE;
2632 }
2633 }
2634
2635 PCPGMPAGE pPage = &pRam->aPages[0];
2636 while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
2637 {
2638 if ( PGM_PAGE_IS_ZERO(pPage)
2639 || PGM_PAGE_IS_BALLOONED(pPage))
2640 {
2641 if (fIncZeroPgs)
2642 {
2643 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
2644 if (RT_FAILURE(rc))
2645 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2646 }
2647 }
2648 else
2649 {
2650 switch (PGM_PAGE_GET_TYPE(pPage))
2651 {
2652 case PGMPAGETYPE_RAM:
2653 case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
2654 case PGMPAGETYPE_ROM:
2655 case PGMPAGETYPE_MMIO2:
2656 {
2657 void const *pvPage;
2658 PGMPAGEMAPLOCK Lock;
2659 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
2660 if (RT_SUCCESS(rc))
2661 {
2662 rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
2663 PGMPhysReleasePageMappingLock(pVM, &Lock);
2664 if (RT_FAILURE(rc))
2665 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2666 }
2667 else
2668 DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2669 break;
2670 }
2671
2672 default:
2673 AssertFailed();
2674 RT_FALL_THRU();
2675 case PGMPAGETYPE_MMIO:
2676 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2677 case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2678 if (fIncZeroPgs)
2679 {
2680 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
2681 if (RT_FAILURE(rc))
2682 DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2683 }
2684 break;
2685 }
2686 }
2687
2688
2689 /* advance */
2690 GCPhys += PAGE_SIZE;
2691 pPage++;
2692 }
2693 }
2694 pgmUnlock(pVM);
2695
2696 RTFileClose(hFile);
2697 if (RT_SUCCESS(rc))
2698 return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
2699 return VINF_SUCCESS;
2700}
2701
2702#endif /* VBOX_WITH_DEBUGGER */
2703
2704/**
2705 * pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
2706 */
2707typedef struct PGMCHECKINTARGS
2708{
2709 bool fLeftToRight; /**< true: left-to-right; false: right-to-left. */
2710 PPGMPHYSHANDLER pPrevPhys;
2711 PVM pVM;
2712} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
2713
2714/**
2715 * Validate a node in the physical handler tree.
2716 *
2717 * @returns 0 on if ok, other wise 1.
2718 * @param pNode The handler node.
2719 * @param pvUser pVM.
2720 */
2721static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2722{
2723 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
2724 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
2725 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
2726 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,
2727 ("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
2728 AssertReleaseMsg( !pArgs->pPrevPhys
2729 || ( pArgs->fLeftToRight
2730 ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key
2731 : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
2732 ("pPrevPhys=%p %RGp-%RGp %s\n"
2733 " pCur=%p %RGp-%RGp %s\n",
2734 pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
2735 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
2736 pArgs->pPrevPhys = pCur;
2737 return 0;
2738}
2739
2740
2741/**
2742 * Perform an integrity check on the PGM component.
2743 *
2744 * @returns VINF_SUCCESS if everything is fine.
2745 * @returns VBox error status after asserting on integrity breach.
2746 * @param pVM The cross context VM structure.
2747 */
2748VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
2749{
2750 AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
2751
2752 /*
2753 * Check the trees.
2754 */
2755 int cErrors = 0;
2756 const PGMCHECKINTARGS LeftToRight = { true, NULL, pVM };
2757 const PGMCHECKINTARGS RightToLeft = { false, NULL, pVM };
2758 PGMCHECKINTARGS Args = LeftToRight;
2759 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
2760 Args = RightToLeft;
2761 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
2762
2763 return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
2764}
2765
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