PGM.cpp@ 93732

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1	/* $Id: PGM.cpp 93725 2022-02-14 13:46:16Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @sa @ref grp_pgm
22	* @subpage pg_pgm_pool
23	* @subpage pg_pgm_phys
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred
30	* to as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	* Note! The intermediate memory context is also used for 64-bit guest
85	* execution on 32-bit hosts. Because we need to load 64-bit registers
86	* prior to switching to guest context, we need to be in 64-bit mode
87	* first. So, HM has some 64-bit worker routines in VMMRC.rc that get
88	* invoked via the special world switcher code in LegacyToAMD64.asm.
89	*
90	*
91	* @subsection subsec_pgm_int_gc Guest Context Mappings
92	*
93	* During assignment and relocation of a guest context mapping the intermediate
94	* memory context is used to verify the new location.
95	*
96	* Guest context mappings are currently restricted to below 4GB, for reasons
97	* of simplicity. This may change when we implement AMD64 support.
98	*
99	*
100	*
101	*
102	* @section sec_pgm_misc Misc
103	*
104	*
105	* @subsection sec_pgm_misc_A20 The A20 Gate
106	*
107	* PGM implements the A20 gate masking when translating a virtual guest address
108	* into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
109	* the code reading the guest page table entries during shadowing. The masking
110	* is done consistenly for all CPU modes, paged ones included. Large pages are
111	* also masked correctly. (On current CPUs, experiments indicates that AMD does
112	* not apply A20M in paged modes and intel only does it for the 2nd MB of
113	* memory.)
114	*
115	* The A20 gate implementation is per CPU core. It can be configured on a per
116	* core basis via the keyboard device and PC architecture device. This is
117	* probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
118	* guest OSes try pushing things anyway, so who cares. (On current real systems
119	* the A20M signal is probably only sent to the boot CPU and it affects all
120	* thread and probably all cores in that package.)
121	*
122	* The keyboard device and the PC architecture device doesn't OR their A20
123	* config bits together, rather they are currently implemented such that they
124	* mirror the CPU state. So, flipping the bit in either of them will change the
125	* A20 state. (On real hardware the bits of the two devices should probably be
126	* ORed together to indicate enabled, i.e. both needs to be cleared to disable
127	* A20 masking.)
128	*
129	* The A20 state will change immediately, transmeta fashion. There is no delays
130	* due to buses, wiring or other physical stuff. (On real hardware there are
131	* normally delays, the delays differs between the two devices and probably also
132	* between chipsets and CPU generations. Note that it's said that transmeta CPUs
133	* does the change immediately like us, they apparently intercept/handles the
134	* port accesses in microcode. Neat.)
135	*
136	* @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
137	*
138	*
139	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
140	*
141	* The differences between legacy PAE and long mode PAE are:
142	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
143	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
144	* usual meanings while 6 is ignored (AMD). This means that upon switching to
145	* legacy PAE mode we'll have to clear these bits and when going to long mode
146	* they must be set. This applies to both intermediate and shadow contexts,
147	* however we don't need to do it for the intermediate one since we're
148	* executing with CR0.WP at that time.
149	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
150	* a page aligned one is required.
151	*
152	*
153	* @section sec_pgm_handlers Access Handlers
154	*
155	* Placeholder.
156	*
157	*
158	* @subsection sec_pgm_handlers_phys Physical Access Handlers
159	*
160	* Placeholder.
161	*
162	*
163	* @subsection sec_pgm_handlers_virt Virtual Access Handlers (obsolete)
164	*
165	* We currently implement three types of virtual access handlers: ALL, WRITE
166	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERKIND for some more details.
167	*
168	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
169	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
170	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
171	* rest of this section is going to be about these handlers.
172	*
173	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
174	* how successful this is gonna be...
175	*
176	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
177	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
178	* and create a new node that is inserted into the AVL tree (range key). Then
179	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
180	*
181	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
182	*
183	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
184	* via the current guest CR3 and update the physical page -> virtual handler
185	* translation. Needless to say, this doesn't exactly scale very well. If any changes
186	* are detected, it will flag a virtual bit update just like we did on registration.
187	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
188	*
189	* 2b. The virtual bit update process will iterate all the pages covered by all the
190	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
191	* virtual handlers on that page.
192	*
193	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
194	* we don't miss any alias mappings of the monitored pages.
195	*
196	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
197	*
198	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
199	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
200	* will call the handlers like in the next step. If the physical mapping has
201	* changed we will - some time in the future - perform a handler callback
202	* (optional) and update the physical -> virtual handler cache.
203	*
204	* 4. \#PF(,write) on a page in the range. This will cause the handler to
205	* be invoked.
206	*
207	* 5. The guest invalidates the page and changes the physical backing or
208	* unmaps it. This should cause the invalidation callback to be invoked
209	* (it might not yet be 100% perfect). Exactly what happens next... is
210	* this where we mess up and end up out of sync for a while?
211	*
212	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
213	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
214	* this handler to NONE and trigger a full PGM resync (basically the same
215	* as int step 1). Which means 2 is executed again.
216	*
217	*
218	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
219	*
220	* There is a bunch of things that needs to be done to make the virtual handlers
221	* work 100% correctly and work more efficiently.
222	*
223	* The first bit hasn't been implemented yet because it's going to slow the
224	* whole mess down even more, and besides it seems to be working reliably for
225	* our current uses. OTOH, some of the optimizations might end up more or less
226	* implementing the missing bits, so we'll see.
227	*
228	* On the optimization side, the first thing to do is to try avoid unnecessary
229	* cache flushing. Then try team up with the shadowing code to track changes
230	* in mappings by means of access to them (shadow in), updates to shadows pages,
231	* invlpg, and shadow PT discarding (perhaps).
232	*
233	* Some idea that have popped up for optimization for current and new features:
234	* - bitmap indicating where there are virtual handlers installed.
235	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
236	* - Further optimize this by min/max (needs min/max avl getters).
237	* - Shadow page table entry bit (if any left)?
238	*
239	*/
240
241
242	/** @page pg_pgm_phys PGM Physical Guest Memory Management
243	*
244	*
245	* Objectives:
246	* - Guest RAM over-commitment using memory ballooning,
247	* zero pages and general page sharing.
248	* - Moving or mirroring a VM onto a different physical machine.
249	*
250	*
251	* @section sec_pgmPhys_Definitions Definitions
252	*
253	* Allocation chunk - A RTR0MemObjAllocPhysNC or RTR0MemObjAllocPhys allocate
254	* memory object and the tracking machinery associated with it.
255	*
256	*
257	*
258	*
259	* @section sec_pgmPhys_AllocPage Allocating a page.
260	*
261	* Initially we map all guest memory to the (per VM) zero page, which
262	* means that none of the read functions will cause pages to be allocated.
263	*
264	* Exception, access bit in page tables that have been shared. This must
265	* be handled, but we must also make sure PGMGst*Modify doesn't make
266	* unnecessary modifications.
267	*
268	* Allocation points:
269	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
270	* - Replacing a zero page mapping at \#PF.
271	* - Replacing a shared page mapping at \#PF.
272	* - ROM registration (currently MMR3RomRegister).
273	* - VM restore (pgmR3Load).
274	*
275	* For the first three it would make sense to keep a few pages handy
276	* until we've reached the max memory commitment for the VM.
277	*
278	* For the ROM registration, we know exactly how many pages we need
279	* and will request these from ring-0. For restore, we will save
280	* the number of non-zero pages in the saved state and allocate
281	* them up front. This would allow the ring-0 component to refuse
282	* the request if the isn't sufficient memory available for VM use.
283	*
284	* Btw. for both ROM and restore allocations we won't be requiring
285	* zeroed pages as they are going to be filled instantly.
286	*
287	*
288	* @section sec_pgmPhys_FreePage Freeing a page
289	*
290	* There are a few points where a page can be freed:
291	* - After being replaced by the zero page.
292	* - After being replaced by a shared page.
293	* - After being ballooned by the guest additions.
294	* - At reset.
295	* - At restore.
296	*
297	* When freeing one or more pages they will be returned to the ring-0
298	* component and replaced by the zero page.
299	*
300	* The reasoning for clearing out all the pages on reset is that it will
301	* return us to the exact same state as on power on, and may thereby help
302	* us reduce the memory load on the system. Further it might have a
303	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
304	*
305	* On restore, as mention under the allocation topic, pages should be
306	* freed / allocated depending on how many is actually required by the
307	* new VM state. The simplest approach is to do like on reset, and free
308	* all non-ROM pages and then allocate what we need.
309	*
310	* A measure to prevent some fragmentation, would be to let each allocation
311	* chunk have some affinity towards the VM having allocated the most pages
312	* from it. Also, try make sure to allocate from allocation chunks that
313	* are almost full. Admittedly, both these measures might work counter to
314	* our intentions and its probably not worth putting a lot of effort,
315	* cpu time or memory into this.
316	*
317	*
318	* @section sec_pgmPhys_SharePage Sharing a page
319	*
320	* The basic idea is that there there will be a idle priority kernel
321	* thread walking the non-shared VM pages hashing them and looking for
322	* pages with the same checksum. If such pages are found, it will compare
323	* them byte-by-byte to see if they actually are identical. If found to be
324	* identical it will allocate a shared page, copy the content, check that
325	* the page didn't change while doing this, and finally request both the
326	* VMs to use the shared page instead. If the page is all zeros (special
327	* checksum and byte-by-byte check) it will request the VM that owns it
328	* to replace it with the zero page.
329	*
330	* To make this efficient, we will have to make sure not to try share a page
331	* that will change its contents soon. This part requires the most work.
332	* A simple idea would be to request the VM to write monitor the page for
333	* a while to make sure it isn't modified any time soon. Also, it may
334	* make sense to skip pages that are being write monitored since this
335	* information is readily available to the thread if it works on the
336	* per-VM guest memory structures (presently called PGMRAMRANGE).
337	*
338	*
339	* @section sec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
340	*
341	* The pages are organized in allocation chunks in ring-0, this is a necessity
342	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
343	* could easily work on a page-by-page basis if we liked. Whether this is possible
344	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
345	* become a problem as part of the idea here is that we wish to return memory to
346	* the host system.
347	*
348	* For instance, starting two VMs at the same time, they will both allocate the
349	* guest memory on-demand and if permitted their page allocations will be
350	* intermixed. Shut down one of the two VMs and it will be difficult to return
351	* any memory to the host system because the page allocation for the two VMs are
352	* mixed up in the same allocation chunks.
353	*
354	* To further complicate matters, when pages are freed because they have been
355	* ballooned or become shared/zero the whole idea is that the page is supposed
356	* to be reused by another VM or returned to the host system. This will cause
357	* allocation chunks to contain pages belonging to different VMs and prevent
358	* returning memory to the host when one of those VM shuts down.
359	*
360	* The only way to really deal with this problem is to move pages. This can
361	* either be done at VM shutdown and or by the idle priority worker thread
362	* that will be responsible for finding sharable/zero pages. The mechanisms
363	* involved for coercing a VM to move a page (or to do it for it) will be
364	* the same as when telling it to share/zero a page.
365	*
366	*
367	* @section sec_pgmPhys_Tracking Tracking Structures And Their Cost
368	*
369	* There's a difficult balance between keeping the per-page tracking structures
370	* (global and guest page) easy to use and keeping them from eating too much
371	* memory. We have limited virtual memory resources available when operating in
372	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
373	* tracking structures will be attempted designed such that we can deal with up
374	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
375	*
376	*
377	* @subsection subsec_pgmPhys_Tracking_Kernel Kernel Space
378	*
379	* @see pg_GMM
380	*
381	* @subsection subsec_pgmPhys_Tracking_PerVM Per-VM
382	*
383	* Fixed info is the physical address of the page (HCPhys) and the page id
384	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
385	* Today we've restricting ourselves to 40(-12) bits because this is the current
386	* restrictions of all AMD64 implementations (I think Barcelona will up this
387	* to 48(-12) bits, not that it really matters) and I needed the bits for
388	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
389	* decent range for the page id: 2^(28+12) = 1024TB.
390	*
391	* In additions to these, we'll have to keep maintaining the page flags as we
392	* currently do. Although it wouldn't harm to optimize these quite a bit, like
393	* for instance the ROM shouldn't depend on having a write handler installed
394	* in order for it to become read-only. A RO/RW bit should be considered so
395	* that the page syncing code doesn't have to mess about checking multiple
396	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
397	* figure out how to setup a shadow PTE. But this of course, is second
398	* priority at present. Current this requires 12 bits, but could probably
399	* be optimized to ~8.
400	*
401	* Then there's the 24 bits used to track which shadow page tables are
402	* currently mapping a page for the purpose of speeding up physical
403	* access handlers, and thereby the page pool cache. More bit for this
404	* purpose wouldn't hurt IIRC.
405	*
406	* Then there is a new bit in which we need to record what kind of page
407	* this is, shared, zero, normal or write-monitored-normal. This'll
408	* require 2 bits. One bit might be needed for indicating whether a
409	* write monitored page has been written to. And yet another one or
410	* two for tracking migration status. 3-4 bits total then.
411	*
412	* Whatever is left will can be used to record the sharabilitiy of a
413	* page. The page checksum will not be stored in the per-VM table as
414	* the idle thread will not be permitted to do modifications to it.
415	* It will instead have to keep its own working set of potentially
416	* shareable pages and their check sums and stuff.
417	*
418	* For the present we'll keep the current packing of the
419	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
420	* we'll have to change it to a struct with a total of 128-bits at
421	* our disposal.
422	*
423	* The initial layout will be like this:
424	* @verbatim
425	RTHCPHYS HCPhys; The current stuff.
426	63:40 Current shadow PT tracking stuff.
427	39:12 The physical page frame number.
428	11:0 The current flags.
429	uint32_t u28PageId : 28; The page id.
430	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
431	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
432	uint32_t u1Reserved : 1; Reserved for later.
433	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
434	@endverbatim
435	*
436	* The final layout will be something like this:
437	* @verbatim
438	RTHCPHYS HCPhys; The current stuff.
439	63:48 High page id (12+).
440	47:12 The physical page frame number.
441	11:0 Low page id.
442	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
443	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
444	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
445	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
446	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
447	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
448	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
449	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
450	@endverbatim
451	*
452	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
453	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
454	* to one or more VMs is: (32GB >> GUEST_PAGE_SHIFT) * 16 bytes, or 128MBs. Or
455	* another example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
456	*
457	* A couple of cost examples for the total cost per-VM + kernel.
458	* 32-bit Windows and 32-bit linux:
459	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
460	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
461	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
462	* 64-bit Windows and 64-bit linux:
463	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
464	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
465	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
466	*
467	* UPDATE - 2007-09-27:
468	* Will need a ballooned flag/state too because we cannot
469	* trust the guest 100% and reporting the same page as ballooned more
470	* than once will put the GMM off balance.
471	*
472	*
473	* @section sec_pgmPhys_Serializing Serializing Access
474	*
475	* Initially, we'll try a simple scheme:
476	*
477	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
478	* by the EMT thread of that VM while in the pgm critsect.
479	* - Other threads in the VM process that needs to make reliable use of
480	* the per-VM RAM tracking structures will enter the critsect.
481	* - No process external thread or kernel thread will ever try enter
482	* the pgm critical section, as that just won't work.
483	* - The idle thread (and similar threads) doesn't not need 100% reliable
484	* data when performing it tasks as the EMT thread will be the one to
485	* do the actual changes later anyway. So, as long as it only accesses
486	* the main ram range, it can do so by somehow preventing the VM from
487	* being destroyed while it works on it...
488	*
489	* - The over-commitment management, including the allocating/freeing
490	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
491	* more mundane mutex implementation is broken on Linux).
492	* - A separate mutex is protecting the set of allocation chunks so
493	* that pages can be shared or/and freed up while some other VM is
494	* allocating more chunks. This mutex can be take from under the other
495	* one, but not the other way around.
496	*
497	*
498	* @section sec_pgmPhys_Request VM Request interface
499	*
500	* When in ring-0 it will become necessary to send requests to a VM so it can
501	* for instance move a page while defragmenting during VM destroy. The idle
502	* thread will make use of this interface to request VMs to setup shared
503	* pages and to perform write monitoring of pages.
504	*
505	* I would propose an interface similar to the current VMReq interface, similar
506	* in that it doesn't require locking and that the one sending the request may
507	* wait for completion if it wishes to. This shouldn't be very difficult to
508	* realize.
509	*
510	* The requests themselves are also pretty simple. They are basically:
511	* -# Check that some precondition is still true.
512	* -# Do the update.
513	* -# Update all shadow page tables involved with the page.
514	*
515	* The 3rd step is identical to what we're already doing when updating a
516	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
517	*
518	*
519	*
520	* @section sec_pgmPhys_MappingCaches Mapping Caches
521	*
522	* In order to be able to map in and out memory and to be able to support
523	* guest with more RAM than we've got virtual address space, we'll employing
524	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
525	* however on 32-bit darwin the ring-0 code is running in a different memory
526	* context and therefore needs a separate cache. In raw-mode context we also
527	* need a separate cache. The 32-bit darwin mapping cache and the one for
528	* raw-mode context share a lot of code, see PGMRZDYNMAP.
529	*
530	*
531	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
532	*
533	* We've considered implementing the ring-3 mapping cache page based but found
534	* that this was bother some when one had to take into account TLBs+SMP and
535	* portability (missing the necessary APIs on several platforms). There were
536	* also some performance concerns with this approach which hadn't quite been
537	* worked out.
538	*
539	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
540	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
541	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
542	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
543	* costly than a single page, although how much more costly is uncertain. We'll
544	* try address this by using a very big cache, preferably bigger than the actual
545	* VM RAM size if possible. The current VM RAM sizes should give some idea for
546	* 32-bit boxes, while on 64-bit we can probably get away with employing an
547	* unlimited cache.
548	*
549	* The cache have to parts, as already indicated, the ring-3 side and the
550	* ring-0 side.
551	*
552	* The ring-0 will be tied to the page allocator since it will operate on the
553	* memory objects it contains. It will therefore require the first ring-0 mutex
554	* discussed in @ref sec_pgmPhys_Serializing. We some double house keeping wrt
555	* to who has mapped what I think, since both VMMR0.r0 and RTR0MemObj will keep
556	* track of mapping relations
557	*
558	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
559	* require anyone that desires to do changes to the mapping cache to do that
560	* from within this critsect. Alternatively, we could employ a separate critsect
561	* for serializing changes to the mapping cache as this would reduce potential
562	* contention with other threads accessing mappings unrelated to the changes
563	* that are in process. We can see about this later, contention will show
564	* up in the statistics anyway, so it'll be simple to tell.
565	*
566	* The organization of the ring-3 part will be very much like how the allocation
567	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
568	* having to walk the tree all the time, we'll have a couple of lookaside entries
569	* like in we do for I/O ports and MMIO in IOM.
570	*
571	* The simplified flow of a PGMPhysRead/Write function:
572	* -# Enter the PGM critsect.
573	* -# Lookup GCPhys in the ram ranges and get the Page ID.
574	* -# Calc the Allocation Chunk ID from the Page ID.
575	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
576	* If not found in cache:
577	* -# Call ring-0 and request it to be mapped and supply
578	* a chunk to be unmapped if the cache is maxed out already.
579	* -# Insert the new mapping into the AVL tree (id + R3 address).
580	* -# Update the relevant lookaside entry and return the mapping address.
581	* -# Do the read/write according to monitoring flags and everything.
582	* -# Leave the critsect.
583	*
584	*
585	* @section sec_pgmPhys_Changes Changes
586	*
587	* Breakdown of the changes involved?
588	*/
589
590
591	/*********************************************************************************************************************************
592	* Header Files *
593	*********************************************************************************************************************************/
594	#define LOG_GROUP LOG_GROUP_PGM
595	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
596	#include <VBox/vmm/dbgf.h>
597	#include <VBox/vmm/pgm.h>
598	#include <VBox/vmm/cpum.h>
599	#include <VBox/vmm/iom.h>
600	#include <VBox/sup.h>
601	#include <VBox/vmm/mm.h>
602	#include <VBox/vmm/em.h>
603	#include <VBox/vmm/stam.h>
604	#include <VBox/vmm/selm.h>
605	#include <VBox/vmm/ssm.h>
606	#include <VBox/vmm/hm.h>
607	#include "PGMInternal.h"
608	#include <VBox/vmm/vmcc.h>
609	#include <VBox/vmm/uvm.h>
610	#include "PGMInline.h"
611
612	#include <VBox/dbg.h>
613	#include <VBox/param.h>
614	#include <VBox/err.h>
615
616	#include <iprt/asm.h>
617	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
618	# include <iprt/asm-amd64-x86.h>
619	#endif
620	#include <iprt/assert.h>
621	#include <iprt/env.h>
622	#include <iprt/file.h>
623	#include <iprt/mem.h>
624	#include <iprt/rand.h>
625	#include <iprt/string.h>
626	#include <iprt/thread.h>
627	#ifdef RT_OS_LINUX
628	# include <iprt/linux/sysfs.h>
629	#endif
630
631
632	/*********************************************************************************************************************************
633	* Structures and Typedefs *
634	*********************************************************************************************************************************/
635	/**
636	* Argument package for pgmR3RElocatePhysHnadler, pgmR3RelocateVirtHandler and
637	* pgmR3RelocateHyperVirtHandler.
638	*/
639	typedef struct PGMRELOCHANDLERARGS
640	{
641	RTGCINTPTR offDelta;
642	PVM pVM;
643	} PGMRELOCHANDLERARGS;
644	/** Pointer to a page access handlere relocation argument package. */
645	typedef PGMRELOCHANDLERARGS const *PCPGMRELOCHANDLERARGS;
646
647
648	/*********************************************************************************************************************************
649	* Internal Functions *
650	*********************************************************************************************************************************/
651	static int pgmR3InitPaging(PVM pVM);
652	static int pgmR3InitStats(PVM pVM);
653	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
654	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
655	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
656	#ifdef VBOX_STRICT
657	static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
658	#endif
659
660	#ifdef VBOX_WITH_DEBUGGER
661	static FNDBGCCMD pgmR3CmdError;
662	static FNDBGCCMD pgmR3CmdSync;
663	static FNDBGCCMD pgmR3CmdSyncAlways;
664	# ifdef VBOX_STRICT
665	static FNDBGCCMD pgmR3CmdAssertCR3;
666	# endif
667	static FNDBGCCMD pgmR3CmdPhysToFile;
668	#endif
669
670
671	/*********************************************************************************************************************************
672	* Global Variables *
673	*********************************************************************************************************************************/
674	#ifdef VBOX_WITH_DEBUGGER
675	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
676	static const DBGCVARDESC g_aPgmErrorArgs[] =
677	{
678	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
679	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
680	};
681
682	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
683	{
684	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
685	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
686	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
687	};
688
689	# ifdef DEBUG_sandervl
690	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
691	{
692	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
693	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
694	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
695	};
696	# endif
697
698	/** Command descriptors. */
699	static const DBGCCMD g_aCmds[] =
700	{
701	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
702	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
703	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
704	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
705	# ifdef VBOX_STRICT
706	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
707	# ifdef VBOX_WITH_PAGE_SHARING
708	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
709	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
710	# endif
711	# endif
712	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
713	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
714	};
715	#endif
716
717	#ifdef VBOX_WITH_PGM_NEM_MODE
718
719	/**
720	* Interface that NEM uses to switch PGM into simplified memory managment mode.
721	*
722	* This call occurs before PGMR3Init.
723	*
724	* @param pVM The cross context VM structure.
725	*/
726	VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM)
727	{
728	AssertFatal(!PDMCritSectIsInitialized(&pVM->pgm.s.CritSectX));
729	pVM->pgm.s.fNemMode = true;
730	}
731
732
733	/**
734	* Checks whether the simplificed memory management mode for NEM is enabled.
735	*
736	* @returns true if enabled, false if not.
737	* @param pVM The cross context VM structure.
738	*/
739	VMMR3_INT_DECL(bool) PGMR3IsNemModeEnabled(PVM pVM)
740	{
741	return pVM->pgm.s.fNemMode;
742	}
743
744	#endif /* VBOX_WITH_PGM_NEM_MODE */
745
746	/**
747	* Initiates the paging of VM.
748	*
749	* @returns VBox status code.
750	* @param pVM The cross context VM structure.
751	*/
752	VMMR3DECL(int) PGMR3Init(PVM pVM)
753	{
754	LogFlow(("PGMR3Init:\n"));
755	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
756	int rc;
757
758	/*
759	* Assert alignment and sizes.
760	*/
761	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
762	AssertCompile(sizeof(pVM->apCpusR3[0]->pgm.s) <= sizeof(pVM->apCpusR3[0]->pgm.padding));
763	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
764
765	/*
766	* If we're in driveless mode we have to use the simplified memory mode.
767	*/
768	bool const fDriverless = SUPR3IsDriverless();
769	if (fDriverless)
770	{
771	#ifdef VBOX_WITH_PGM_NEM_MODE
772	if (!pVM->pgm.s.fNemMode)
773	pVM->pgm.s.fNemMode = true;
774	#else
775	return VMR3SetError(pVM->pUVM, VERR_SUP_DRIVERLESS, RT_SRC_POS,
776	"Driverless requires that VBox is built with VBOX_WITH_PGM_NEM_MODE defined");
777	#endif
778	}
779
780	/*
781	* Init the structure.
782	*/
783	/pVM->pgm.s.fRestoreRomPagesAtReset = false;/
784
785	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
786	{
787	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_GMMPAGEDESC_PHYS;
788	pVM->pgm.s.aHandyPages[i].fZeroed = false;
789	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
790	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
791	}
792
793	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
794	{
795	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_GMMPAGEDESC_PHYS;
796	pVM->pgm.s.aLargeHandyPage[i].fZeroed = false;
797	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
798	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
799	}
800
801	AssertReleaseReturn(pVM->pgm.s.cPhysHandlerTypes == 0, VERR_WRONG_ORDER);
802	for (size_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aPhysHandlerTypes); i++)
803	{
804	if (fDriverless)
805	pVM->pgm.s.aPhysHandlerTypes[i].hType = i \| (RTRandU64() & ~(uint64_t)PGMPHYSHANDLERTYPE_IDX_MASK);
806	pVM->pgm.s.aPhysHandlerTypes[i].enmKind = PGMPHYSHANDLERKIND_INVALID;
807	pVM->pgm.s.aPhysHandlerTypes[i].pfnHandler = pgmR3HandlerPhysicalHandlerInvalid;
808	}
809
810	/* Init the per-CPU part. */
811	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
812	{
813	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
814	PPGMCPU pPGM = &pVCpu->pgm.s;
815
816	pPGM->enmShadowMode = PGMMODE_INVALID;
817	pPGM->enmGuestMode = PGMMODE_INVALID;
818	pPGM->enmGuestSlatMode = PGMSLAT_INVALID;
819	pPGM->idxGuestModeData = UINT8_MAX;
820	pPGM->idxShadowModeData = UINT8_MAX;
821	pPGM->idxBothModeData = UINT8_MAX;
822
823	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
824	pPGM->GCPhysNstGstCR3 = NIL_RTGCPHYS;
825
826	pPGM->pGst32BitPdR3 = NULL;
827	pPGM->pGstPaePdptR3 = NULL;
828	pPGM->pGstAmd64Pml4R3 = NULL;
829	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
830	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
831	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
832	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
833	pPGM->pGstEptPml4R3 = NULL;
834	pPGM->pGstEptPml4R0 = NIL_RTR0PTR;
835	pPGM->uEptPtr = 0;
836	#endif
837	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
838	{
839	pPGM->apGstPaePDsR3[i] = NULL;
840	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
841	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
842	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
843	}
844
845	pPGM->fA20Enabled = true;
846	pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
847	}
848
849	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
850	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
851
852	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
853	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
854	true
855	#else
856	false
857	#endif
858	);
859	AssertLogRelRCReturn(rc, rc);
860
861	#if HC_ARCH_BITS == 32
862	# ifdef RT_OS_DARWIN
863	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
864	# else
865	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
866	# endif
867	#else
868	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
869	#endif
870	AssertLogRelRCReturn(rc, rc);
871	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
872	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
873
874	/*
875	* Get the configured RAM size - to estimate saved state size.
876	*/
877	uint64_t cbRam;
878	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
879	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
880	cbRam = 0;
881	else if (RT_SUCCESS(rc))
882	{
883	if (cbRam < GUEST_PAGE_SIZE)
884	cbRam = 0;
885	cbRam = RT_ALIGN_64(cbRam, GUEST_PAGE_SIZE);
886	}
887	else
888	{
889	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
890	return rc;
891	}
892
893	/*
894	* Check for PCI pass-through and other configurables.
895	*/
896	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
897	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
898	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
899
900	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "PageFusionAllowed", &pVM->pgm.s.fPageFusionAllowed, false);
901	AssertLogRelRCReturn(rc, rc);
902
903	/** @cfgm{/PGM/ZeroRamPagesOnReset, boolean, true}
904	* Whether to clear RAM pages on (hard) reset. */
905	rc = CFGMR3QueryBoolDef(pCfgPGM, "ZeroRamPagesOnReset", &pVM->pgm.s.fZeroRamPagesOnReset, true);
906	AssertLogRelRCReturn(rc, rc);
907
908	/*
909	* Register callbacks, string formatters and the saved state data unit.
910	*/
911	#ifdef VBOX_STRICT
912	VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
913	#endif
914	PGMRegisterStringFormatTypes();
915
916	rc = pgmR3InitSavedState(pVM, cbRam);
917	if (RT_FAILURE(rc))
918	return rc;
919
920	/*
921	* Initialize the PGM critical section and flush the phys TLBs
922	*/
923	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
924	AssertRCReturn(rc, rc);
925
926	PGMR3PhysChunkInvalidateTLB(pVM);
927	pgmPhysInvalidatePageMapTLB(pVM);
928
929	/*
930	* For the time being we sport a full set of handy pages in addition to the base
931	* memory to simplify things.
932	*/
933	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
934	AssertRCReturn(rc, rc);
935
936	/*
937	* Setup the zero page (HCPHysZeroPg is set by ring-0).
938	*/
939	RT_ZERO(pVM->pgm.s.abZeroPg); /* paranoia */
940	if (fDriverless)
941	pVM->pgm.s.HCPhysZeroPg = _4G - GUEST_PAGE_SIZE * 2 /* fake to avoid PGM_PAGE_INIT_ZERO assertion */;
942	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
943	AssertRelease(pVM->pgm.s.HCPhysZeroPg != 0);
944
945	/*
946	* Setup the invalid MMIO page (HCPhysMmioPg is set by ring-0).
947	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
948	*/
949	ASMMemFill32(pVM->pgm.s.abMmioPg, sizeof(pVM->pgm.s.abMmioPg), 0xfeedface);
950	if (fDriverless)
951	pVM->pgm.s.HCPhysMmioPg = _4G - GUEST_PAGE_SIZE * 3 /* fake to avoid PGM_PAGE_INIT_ZERO assertion */;
952	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
953	AssertRelease(pVM->pgm.s.HCPhysMmioPg != 0);
954	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
955
956	/*
957	* Initialize physical access handlers.
958	*/
959	/** @cfgm{/PGM/MaxPhysicalAccessHandlers, uint32_t, 32, 65536, 6144}
960	* Number of physical access handlers allowed (subject to rounding). This is
961	* managed as one time allocation during initializations. The default is
962	* lower for a driverless setup. */
963	/** @todo can lower it for nested paging too, at least when there is no
964	* nested guest involved. */
965	uint32_t cAccessHandlers = 0;
966	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxPhysicalAccessHandlers", &cAccessHandlers, !fDriverless ? 6144 : 640);
967	AssertLogRelRCReturn(rc, rc);
968	AssertLogRelMsgStmt(cAccessHandlers >= 32, ("cAccessHandlers=%#x, min 32\n", cAccessHandlers), cAccessHandlers = 32);
969	AssertLogRelMsgStmt(cAccessHandlers <= _64K, ("cAccessHandlers=%#x, max 65536\n", cAccessHandlers), cAccessHandlers = _64K);
970	if (!fDriverless)
971	{
972	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_HANDLER_INIT, cAccessHandlers, NULL);
973	AssertRCReturn(rc, rc);
974	AssertPtr(pVM->pgm.s.pPhysHandlerTree);
975	AssertPtr(pVM->pgm.s.PhysHandlerAllocator.m_paNodes);
976	AssertPtr(pVM->pgm.s.PhysHandlerAllocator.m_pbmAlloc);
977	}
978	else
979	{
980	uint32_t cbTreeAndBitmap = 0;
981	uint32_t const cbTotalAligned = pgmHandlerPhysicalCalcTableSizes(&cAccessHandlers, &cbTreeAndBitmap);
982	uint8_t *pb = NULL;
983	rc = SUPR3PageAlloc(cbTotalAligned >> HOST_PAGE_SHIFT, 0, (void **)&pb);
984	AssertLogRelRCReturn(rc, rc);
985
986	pVM->pgm.s.PhysHandlerAllocator.initSlabAllocator(cAccessHandlers, (PPGMPHYSHANDLER)&pb[cbTreeAndBitmap],
987	(uint64_t *)&pb[sizeof(PGMPHYSHANDLERTREE)]);
988	pVM->pgm.s.pPhysHandlerTree = (PPGMPHYSHANDLERTREE)pb;
989	pVM->pgm.s.pPhysHandlerTree->initWithAllocator(&pVM->pgm.s.PhysHandlerAllocator);
990	}
991
992	/*
993	* Register the physical access handler protecting ROMs.
994	*/
995	if (RT_SUCCESS(rc))
996	/** @todo why isn't pgmPhysRomWriteHandler registered for ring-0? */
997	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE, 0 /fFlags/, pgmPhysRomWriteHandler,
998	"ROM write protection", &pVM->pgm.s.hRomPhysHandlerType);
999
1000	/*
1001	* Register the physical access handler doing dirty MMIO2 tracing.
1002	*/
1003	if (RT_SUCCESS(rc))
1004	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE, PGMPHYSHANDLER_F_KEEP_PGM_LOCK,
1005	pgmPhysMmio2WriteHandler, "MMIO2 dirty page tracing",
1006	&pVM->pgm.s.hMmio2DirtyPhysHandlerType);
1007
1008	/*
1009	* Init the paging.
1010	*/
1011	if (RT_SUCCESS(rc))
1012	rc = pgmR3InitPaging(pVM);
1013
1014	/*
1015	* Init the page pool.
1016	*/
1017	if (RT_SUCCESS(rc))
1018	rc = pgmR3PoolInit(pVM);
1019
1020	if (RT_SUCCESS(rc))
1021	{
1022	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1023	{
1024	PVMCPU pVCpu = pVM->apCpusR3[i];
1025	rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1026	if (RT_FAILURE(rc))
1027	break;
1028	}
1029	}
1030
1031	if (RT_SUCCESS(rc))
1032	{
1033	/*
1034	* Info & statistics
1035	*/
1036	DBGFR3InfoRegisterInternalEx(pVM, "mode",
1037	"Shows the current paging mode. "
1038	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1039	pgmR3InfoMode,
1040	DBGFINFO_FLAGS_ALL_EMTS);
1041	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1042	"Dumps all the entries in the top level paging table. No arguments.",
1043	pgmR3InfoCr3);
1044	DBGFR3InfoRegisterInternal(pVM, "phys",
1045	"Dumps all the physical address ranges. Pass 'verbose' to get more details.",
1046	pgmR3PhysInfo);
1047	DBGFR3InfoRegisterInternal(pVM, "handlers",
1048	"Dumps physical, virtual and hyper virtual handlers. "
1049	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1050	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1051	pgmR3InfoHandlers);
1052
1053	pgmR3InitStats(pVM);
1054
1055	#ifdef VBOX_WITH_DEBUGGER
1056	/*
1057	* Debugger commands.
1058	*/
1059	static bool s_fRegisteredCmds = false;
1060	if (!s_fRegisteredCmds)
1061	{
1062	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1063	if (RT_SUCCESS(rc2))
1064	s_fRegisteredCmds = true;
1065	}
1066	#endif
1067
1068	#ifdef RT_OS_LINUX
1069	/*
1070	* Log the /proc/sys/vm/max_map_count value on linux as that is
1071	* frequently giving us grief when too low.
1072	*/
1073	int64_t const cGuessNeeded = MMR3PhysGetRamSize(pVM) / _2M + 16384 /guesstimate/;
1074	int64_t cMaxMapCount = 0;
1075	int rc2 = RTLinuxSysFsReadIntFile(10, &cMaxMapCount, "/proc/sys/vm/max_map_count");
1076	LogRel(("PGM: /proc/sys/vm/max_map_count = %RI64 (rc2=%Rrc); cGuessNeeded=%RI64\n", cMaxMapCount, rc2, cGuessNeeded));
1077	if (RT_SUCCESS(rc2) && cMaxMapCount < cGuessNeeded)
1078	LogRel(("PGM: WARNING!!\n"
1079	"PGM: WARNING!! Please increase /proc/sys/vm/max_map_count to at least %RI64 (or reduce the amount of RAM assigned to the VM)!\n"
1080	"PGM: WARNING!!\n", cMaxMapCount));
1081
1082	#endif
1083
1084	return VINF_SUCCESS;
1085	}
1086
1087	/* Almost no cleanup necessary, MM frees all memory. */
1088	PDMR3CritSectDelete(pVM, &pVM->pgm.s.CritSectX);
1089
1090	return rc;
1091	}
1092
1093
1094	/**
1095	* Init paging.
1096	*
1097	* Since we need to check what mode the host is operating in before we can choose
1098	* the right paging functions for the host we have to delay this until R0 has
1099	* been initialized.
1100	*
1101	* @returns VBox status code.
1102	* @param pVM The cross context VM structure.
1103	*/
1104	static int pgmR3InitPaging(PVM pVM)
1105	{
1106	/*
1107	* Force a recalculation of modes and switcher so everyone gets notified.
1108	*/
1109	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1110	{
1111	PVMCPU pVCpu = pVM->apCpusR3[i];
1112
1113	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1114	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1115	pVCpu->pgm.s.enmGuestSlatMode = PGMSLAT_INVALID;
1116	pVCpu->pgm.s.idxGuestModeData = UINT8_MAX;
1117	pVCpu->pgm.s.idxShadowModeData = UINT8_MAX;
1118	pVCpu->pgm.s.idxBothModeData = UINT8_MAX;
1119	}
1120
1121	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1122
1123	/*
1124	* Initialize paging workers and mode from current host mode
1125	* and the guest running in real mode.
1126	*/
1127	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1128	switch (pVM->pgm.s.enmHostMode)
1129	{
1130	case SUPPAGINGMODE_32_BIT:
1131	case SUPPAGINGMODE_32_BIT_GLOBAL:
1132	case SUPPAGINGMODE_PAE:
1133	case SUPPAGINGMODE_PAE_GLOBAL:
1134	case SUPPAGINGMODE_PAE_NX:
1135	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1136	break;
1137
1138	case SUPPAGINGMODE_AMD64:
1139	case SUPPAGINGMODE_AMD64_GLOBAL:
1140	case SUPPAGINGMODE_AMD64_NX:
1141	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1142	if (ARCH_BITS != 64)
1143	{
1144	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1145	LogRel(("PGM: Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1146	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1147	}
1148	break;
1149	default:
1150	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1151	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1152	}
1153
1154	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1155	#if HC_ARCH_BITS == 64 && 0
1156	LogRel(("PGM: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1157	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1158	LogRel(("PGM: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1159	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1160	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1161	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1162	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1163	#endif
1164
1165	/*
1166	* Log the host paging mode. It may come in handy.
1167	*/
1168	const char *pszHostMode;
1169	switch (pVM->pgm.s.enmHostMode)
1170	{
1171	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1172	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1173	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1174	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1175	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1176	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1177	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1178	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1179	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1180	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1181	default: pszHostMode = "???"; break;
1182	}
1183	LogRel(("PGM: Host paging mode: %s\n", pszHostMode));
1184
1185	return VINF_SUCCESS;
1186	}
1187
1188
1189	/**
1190	* Init statistics
1191	* @returns VBox status code.
1192	*/
1193	static int pgmR3InitStats(PVM pVM)
1194	{
1195	PPGM pPGM = &pVM->pgm.s;
1196	int rc;
1197
1198	/*
1199	* Release statistics.
1200	*/
1201	/* Common - misc variables */
1202	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1203	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1204	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1205	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1206	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1207	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1208	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1209	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1210	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1211	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1212	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1213	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1214	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1215	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1216	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1217	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1218	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1219	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1220
1221	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1222	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1223	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1224
1225	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1226	STAM_REL_REG(pVM, &pPGM->StatMmio2QueryAndResetDirtyBitmap, STAMTYPE_PROFILE, "/PGM/Mmio2QueryAndResetDirtyBitmap", STAMUNIT_TICKS_PER_CALL, "Profiles calls to PGMR3PhysMmio2QueryAndResetDirtyBitmap (sans locking).");
1227
1228	/* Live save */
1229	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1230	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1231	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1232	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1233	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1234	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1235	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1236	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1237	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1238	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1239	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1240	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1241	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1242	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1243	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1244	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1245	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1246	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1247
1248	#define PGM_REG_COUNTER(a, b, c) \
1249	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1250	AssertRC(rc);
1251
1252	#define PGM_REG_U64(a, b, c) \
1253	rc = STAMR3RegisterF(pVM, a, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1254	AssertRC(rc);
1255
1256	#define PGM_REG_U64_RESET(a, b, c) \
1257	rc = STAMR3RegisterF(pVM, a, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1258	AssertRC(rc);
1259
1260	#define PGM_REG_U32(a, b, c) \
1261	rc = STAMR3RegisterF(pVM, a, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1262	AssertRC(rc);
1263
1264	#define PGM_REG_COUNTER_BYTES(a, b, c) \
1265	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1266	AssertRC(rc);
1267
1268	#define PGM_REG_PROFILE(a, b, c) \
1269	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1270	AssertRC(rc);
1271	#define PGM_REG_PROFILE_NS(a, b, c) \
1272	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NS_PER_CALL, c, b); \
1273	AssertRC(rc);
1274
1275	#ifdef VBOX_WITH_STATISTICS
1276	PGMSTATS *pStats = &pPGM->Stats;
1277	#endif
1278
1279	PGM_REG_PROFILE_NS(&pPGM->StatLargePageAlloc, "/PGM/LargePage/Alloc", "Time spent by the host OS for large page allocation.");
1280	PGM_REG_COUNTER(&pPGM->StatLargePageAllocFailed, "/PGM/LargePage/AllocFailed", "Number of allocation failures.");
1281	PGM_REG_COUNTER(&pPGM->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1282	PGM_REG_COUNTER(&pPGM->StatLargePageTlbFlush, "/PGM/LargePage/TlbFlush", "The number of times a full VCPU TLB flush was required after a large allocation.");
1283	PGM_REG_COUNTER(&pPGM->StatLargePageZeroEvict, "/PGM/LargePage/ZeroEvict", "The number of zero page mappings we had to evict when allocating a large page.");
1284	#ifdef VBOX_WITH_STATISTICS
1285	PGM_REG_PROFILE(&pStats->StatLargePageAlloc2, "/PGM/LargePage/Alloc2", "Time spent allocating large pages.");
1286	PGM_REG_PROFILE(&pStats->StatLargePageSetup, "/PGM/LargePage/Setup", "Time spent setting up the newly allocated large pages.");
1287	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/IsValidR3", "pgmPhysIsValidLargePage profiling - R3.");
1288	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/IsValidRZ", "pgmPhysIsValidLargePage profiling - RZ.");
1289
1290	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1291	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1292	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1293	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1294	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1295	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1296	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1297	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1298	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1299	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1300
1301	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1302	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1303	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1304	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1305	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1306	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1307
1308	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1309	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1310	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1311	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1312	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1313	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1314	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1315	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1316
1317	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1318	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1319	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1320	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1321
1322	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1323	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1324	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1325	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1326	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1327	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1328	#endif /* VBOX_WITH_STATISTICS */
1329	PPGMPHYSHANDLERTREE pPhysHndlTree = pVM->pgm.s.pPhysHandlerTree;
1330	PGM_REG_U32(&pPhysHndlTree->m_cErrors, "/PGM/PhysHandlerTree/ErrorsTree", "Physical access handler tree errors.");
1331	PGM_REG_U32(&pVM->pgm.s.PhysHandlerAllocator.m_cErrors, "/PGM/PhysHandlerTree/ErrorsAllocatorR3", "Physical access handler tree allocator errors (ring-3 only).");
1332	PGM_REG_U64_RESET(&pPhysHndlTree->m_cInserts, "/PGM/PhysHandlerTree/Inserts", "Physical access handler tree inserts.");
1333	PGM_REG_U32(&pVM->pgm.s.PhysHandlerAllocator.m_cNodes, "/PGM/PhysHandlerTree/MaxHandlers", "Max physical access handlers.");
1334	PGM_REG_U64_RESET(&pPhysHndlTree->m_cRemovals, "/PGM/PhysHandlerTree/Removals", "Physical access handler tree removals.");
1335	PGM_REG_U64_RESET(&pPhysHndlTree->m_cRebalancingOperations, "/PGM/PhysHandlerTree/RebalancingOperations", "Physical access handler tree rebalancing transformations.");
1336
1337	#ifdef VBOX_WITH_STATISTICS
1338	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1339	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1340	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1341	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1342	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1343	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1344
1345	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1346	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1347	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1348	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1349	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1350	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1351	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1352	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1353
1354	/* GC only: */
1355	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1356	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1357
1358	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1359	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1360	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1361	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1362	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1363	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1364	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1365	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1366
1367	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1368	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1369	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1370	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1371	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1372	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1373	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1374	#endif
1375
1376	#undef PGM_REG_COUNTER
1377	#undef PGM_REG_U64
1378	#undef PGM_REG_U64_RESET
1379	#undef PGM_REG_U32
1380	#undef PGM_REG_PROFILE
1381	#undef PGM_REG_PROFILE_NS
1382
1383	/*
1384	* Note! The layout below matches the member layout exactly!
1385	*/
1386
1387	/*
1388	* Common - stats
1389	*/
1390	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1391	{
1392	PPGMCPU pPgmCpu = &pVM->apCpusR3[idCpu]->pgm.s;
1393
1394	#define PGM_REG_COUNTER(a, b, c) \
1395	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1396	AssertRC(rc);
1397	#define PGM_REG_PROFILE(a, b, c) \
1398	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1399	AssertRC(rc);
1400
1401	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1402	PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1403
1404	#ifdef VBOX_WITH_STATISTICS
1405	PGMCPUSTATS *pCpuStats = &pVM->apCpusR3[idCpu]->pgm.s.Stats;
1406
1407	# if 0 /* rarely useful; leave for debugging. */
1408	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1409	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1410	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1411	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1412	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1413	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1414	# endif
1415	/* R0 only: */
1416	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1417	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1418
1419	/* RZ only: */
1420	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1421	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1422	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1423	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1424	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1425	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1426	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1427	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1428	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1429	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1430	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1431	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1432	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1433	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1434	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1435	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsHack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USHack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled.");
1436	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Wp0RoUsUnhack, "/PGM/CPU%u/RZ/Trap0e/Time2/WP0R0USUnhack", "Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled.");
1437	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1438	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1439	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1440	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1441	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1442	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1443	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1444	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1445	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1446	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1447	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1448	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1449	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1450	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1451	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1452	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1453	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1454	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1455	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1456	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1457	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1458	#if 0 /* rarely useful; leave for debugging. */
1459	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1460	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1461	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1462	#endif
1463	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1464	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1465	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1466	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1467	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1468
1469	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1470	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1471	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1472	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1473	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1474	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1475	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1476	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1477	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1478	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1479	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1480	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1481	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1482	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1483	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1484	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1485	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1486	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1487	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1488	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1489	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1490	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1491	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1492	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1493	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1494	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1495	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1496	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1497	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1498	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1499	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1500	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1501	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1502	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1503	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1504	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1505
1506	/* HC only: */
1507
1508	/* RZ & R3: */
1509	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1510	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1511	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1512	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1513	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1514	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1515	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1516	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1517	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1518	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1519	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1520	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1521	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1522	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1523	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1524	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1525	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1526	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1527	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1528	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1529	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1530	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1531	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1532	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1533	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1534	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1535	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1536	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1537	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1538	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1539	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1540	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1541	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1542	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSizeChanges, "/PGM/CPU%u/RZ/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
1543	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1544	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1545	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1546	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1547	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1548	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1549	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1550	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1551	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1552	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1553	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1554	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1555	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1556
1557	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1558	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1559	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1560	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1561	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1562	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1563	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1564	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1565	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1566	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1567	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1568	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1569	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1570	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1571	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1572	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1573	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1574	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1575	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1576	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1577	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1578	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1579	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1580	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1581	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1582	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1583	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1584	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1585	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1586	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1587	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1588	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1589	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSizeChanges, "/PGM/CPU%u/R3/InvalidatePage/SizeChanges", "The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB).");
1590	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1591	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1592	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1593	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1594	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1595	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1596	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1597	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1598	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1599	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1600	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1601	#endif /* VBOX_WITH_STATISTICS */
1602
1603	#undef PGM_REG_PROFILE
1604	#undef PGM_REG_COUNTER
1605
1606	}
1607
1608	return VINF_SUCCESS;
1609	}
1610
1611
1612	/**
1613	* Ring-3 init finalizing.
1614	*
1615	* @returns VBox status code.
1616	* @param pVM The cross context VM structure.
1617	*/
1618	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1619	{
1620	/*
1621	* Determine the max physical address width (MAXPHYADDR) and apply it to
1622	* all the mask members and stuff.
1623	*/
1624	uint32_t cMaxPhysAddrWidth;
1625	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
1626	if ( uMaxExtLeaf >= 0x80000008
1627	&& uMaxExtLeaf <= 0x80000fff)
1628	{
1629	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
1630	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
1631	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
1632	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
1633	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
1634	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
1635	}
1636	else
1637	{
1638	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
1639	cMaxPhysAddrWidth = 48;
1640	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
1641	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
1642	}
1643	Assert(pVM->cpum.ro.GuestFeatures.cMaxPhysAddrWidth == cMaxPhysAddrWidth);
1644
1645	/** @todo query from CPUM. */
1646	pVM->pgm.s.GCPhysInvAddrMask = 0;
1647	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
1648	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
1649
1650	/*
1651	* Initialize the invalid paging entry masks, assuming NX is disabled.
1652	*/
1653	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
1654	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1655	uint64_t const fEptVpidCap = CPUMGetGuestIa32VmxEptVpidCap(pVM->apCpusR3[0]); /* should be identical for all VCPUs. */
1656	uint64_t const fGstEptMbzBigPdeMask = EPT_PDE2M_MBZ_MASK
1657	\| (RT_BF_GET(fEptVpidCap, VMX_BF_EPT_VPID_CAP_PDE_2M) ^ 1) << EPT_E_BIT_LEAF;
1658	uint64_t const fGstEptMbzBigPdpteMask = EPT_PDPTE1G_MBZ_MASK
1659	\| (RT_BF_GET(fEptVpidCap, VMX_BF_EPT_VPID_CAP_PDPTE_1G) ^ 1) << EPT_E_BIT_LEAF;
1660	#endif
1661	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1662	{
1663	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1664
1665	/** @todo The manuals are not entirely clear whether the physical
1666	* address width is relevant. See table 5-9 in the intel
1667	* manual vs the PDE4M descriptions. Write testcase (NP). */
1668	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
1669	\| X86_PDE4M_MBZ_MASK;
1670
1671	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
1672	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
1673	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
1674	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
1675
1676	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
1677	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
1678	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
1679	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
1680	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
1681	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
1682
1683	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
1684	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
1685	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
1686	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
1687	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
1688	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
1689	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
1690
1691	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1692	pVCpu->pgm.s.uEptVpidCapMsr = fEptVpidCap;
1693	pVCpu->pgm.s.fGstEptMbzPteMask = fMbzPageFrameMask \| EPT_PTE_MBZ_MASK;
1694	pVCpu->pgm.s.fGstEptMbzPdeMask = fMbzPageFrameMask \| EPT_PDE_MBZ_MASK;
1695	pVCpu->pgm.s.fGstEptMbzBigPdeMask = fMbzPageFrameMask \| fGstEptMbzBigPdeMask;
1696	pVCpu->pgm.s.fGstEptMbzPdpteMask = fMbzPageFrameMask \| EPT_PDPTE_MBZ_MASK;
1697	pVCpu->pgm.s.fGstEptMbzBigPdpteMask = fMbzPageFrameMask \| fGstEptMbzBigPdpteMask;
1698	pVCpu->pgm.s.fGstEptMbzPml4eMask = fMbzPageFrameMask \| EPT_PML4E_MBZ_MASK;
1699
1700	/* If any of the features (in the assert below) are enabled, we might have to shadow the relevant bits. */
1701	Assert( !pVM->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt
1702	&& !pVM->cpum.ro.GuestFeatures.fVmxSppEpt
1703	&& !pVM->cpum.ro.GuestFeatures.fVmxEptXcptVe);
1704	pVCpu->pgm.s.fGstEptPresentMask = EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE;
1705	#endif
1706	}
1707
1708	/*
1709	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1710	* Intel only goes up to 36 bits, so we stick to 36 as well.
1711	* Update: More recent intel manuals specifies 40 bits just like AMD.
1712	*/
1713	uint32_t u32Dummy, u32Features;
1714	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1715	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1716	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
1717	else
1718	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1719
1720	/*
1721	* Allocate memory if we're supposed to do that.
1722	*/
1723	int rc = VINF_SUCCESS;
1724	if (pVM->pgm.s.fRamPreAlloc)
1725	rc = pgmR3PhysRamPreAllocate(pVM);
1726
1727	//pgmLogState(pVM);
1728	LogRel(("PGM: PGMR3InitFinalize: 4 MB PSE mask %RGp -> %Rrc\n", pVM->pgm.s.GCPhys4MBPSEMask, rc));
1729	return rc;
1730	}
1731
1732
1733	/**
1734	* Init phase completed callback.
1735	*
1736	* @returns VBox status code.
1737	* @param pVM The cross context VM structure.
1738	* @param enmWhat What has been completed.
1739	* @thread EMT(0)
1740	*/
1741	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1742	{
1743	switch (enmWhat)
1744	{
1745	case VMINITCOMPLETED_HM:
1746	#ifdef VBOX_WITH_PCI_PASSTHROUGH
1747	if (pVM->pgm.s.fPciPassthrough)
1748	{
1749	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
1750	AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
1751	AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
1752
1753	/*
1754	* Report assignments to the IOMMU (hope that's good enough for now).
1755	*/
1756	if (pVM->pgm.s.fPciPassthrough)
1757	{
1758	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
1759	AssertRCReturn(rc, rc);
1760	}
1761	}
1762	#else
1763	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
1764	#endif
1765	break;
1766
1767	default:
1768	/* shut up gcc */
1769	break;
1770	}
1771
1772	return VINF_SUCCESS;
1773	}
1774
1775
1776	/**
1777	* Applies relocations to data and code managed by this component.
1778	*
1779	* This function will be called at init and whenever the VMM need to relocate it
1780	* self inside the GC.
1781	*
1782	* @param pVM The cross context VM structure.
1783	* @param offDelta Relocation delta relative to old location.
1784	*/
1785	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1786	{
1787	LogFlow(("PGMR3Relocate: offDelta=%RGv\n", offDelta));
1788
1789	/*
1790	* Paging stuff.
1791	*/
1792
1793	/* Shadow, guest and both mode switch & relocation for each VCPU. */
1794	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1795	{
1796	PVMCPU pVCpu = pVM->apCpusR3[i];
1797
1798	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1799	if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
1800	&& g_aPgmShadowModeData[idxShw].pfnRelocate)
1801	g_aPgmShadowModeData[idxShw].pfnRelocate(pVCpu, offDelta);
1802	else
1803	AssertFailed();
1804
1805	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1806	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1807	&& g_aPgmGuestModeData[idxGst].pfnRelocate)
1808	g_aPgmGuestModeData[idxGst].pfnRelocate(pVCpu, offDelta);
1809	else
1810	AssertFailed();
1811	}
1812
1813	/*
1814	* Ram ranges.
1815	*/
1816	if (pVM->pgm.s.pRamRangesXR3)
1817	pgmR3PhysRelinkRamRanges(pVM);
1818
1819	/*
1820	* The page pool.
1821	*/
1822	pgmR3PoolRelocate(pVM);
1823	}
1824
1825
1826	/**
1827	* Resets a virtual CPU when unplugged.
1828	*
1829	* @param pVM The cross context VM structure.
1830	* @param pVCpu The cross context virtual CPU structure.
1831	*/
1832	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1833	{
1834	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1835	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1836	&& g_aPgmGuestModeData[idxGst].pfnExit)
1837	{
1838	int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
1839	AssertReleaseRC(rc);
1840	}
1841	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1842	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
1843
1844	int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1845	AssertReleaseRC(rc);
1846
1847	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
1848
1849	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
1850
1851	/*
1852	* Re-init other members.
1853	*/
1854	pVCpu->pgm.s.fA20Enabled = true;
1855	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
1856
1857	/*
1858	* Clear the FFs PGM owns.
1859	*/
1860	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1861	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1862	}
1863
1864
1865	/**
1866	* The VM is being reset.
1867	*
1868	* For the PGM component this means that any PD write monitors
1869	* needs to be removed.
1870	*
1871	* @param pVM The cross context VM structure.
1872	*/
1873	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
1874	{
1875	LogFlow(("PGMR3Reset:\n"));
1876	VM_ASSERT_EMT(pVM);
1877
1878	PGM_LOCK_VOID(pVM);
1879
1880	/*
1881	* Exit the guest paging mode before the pgm pool gets reset.
1882	* Important to clean up the amd64 case.
1883	*/
1884	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1885	{
1886	PVMCPU pVCpu = pVM->apCpusR3[i];
1887	uintptr_t const idxGst = pVCpu->pgm.s.idxGuestModeData;
1888	if ( idxGst < RT_ELEMENTS(g_aPgmGuestModeData)
1889	&& g_aPgmGuestModeData[idxGst].pfnExit)
1890	{
1891	int rc = g_aPgmGuestModeData[idxGst].pfnExit(pVCpu);
1892	AssertReleaseRC(rc);
1893	}
1894	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1895	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
1896	}
1897
1898	#ifdef DEBUG
1899	DBGFR3_INFO_LOG_SAFE(pVM, "mappings", NULL);
1900	DBGFR3_INFO_LOG_SAFE(pVM, "handlers", "all nostat");
1901	#endif
1902
1903	/*
1904	* Switch mode back to real mode. (Before resetting the pgm pool!)
1905	*/
1906	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1907	{
1908	PVMCPU pVCpu = pVM->apCpusR3[i];
1909
1910	int rc = PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1911	AssertReleaseRC(rc);
1912
1913	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
1914	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
1915	}
1916
1917	/*
1918	* Reset the shadow page pool.
1919	*/
1920	pgmR3PoolReset(pVM);
1921
1922	/*
1923	* Re-init various other members and clear the FFs that PGM owns.
1924	*/
1925	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1926	{
1927	PVMCPU pVCpu = pVM->apCpusR3[i];
1928
1929	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
1930	PGMNotifyNxeChanged(pVCpu, false);
1931
1932	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1933	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1934
1935	if (!pVCpu->pgm.s.fA20Enabled)
1936	{
1937	pVCpu->pgm.s.fA20Enabled = true;
1938	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
1939	#ifdef PGM_WITH_A20
1940	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1941	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
1942	HMFlushTlb(pVCpu);
1943	#endif
1944	}
1945	}
1946
1947	//pgmLogState(pVM);
1948	PGM_UNLOCK(pVM);
1949	}
1950
1951
1952	/**
1953	* Memory setup after VM construction or reset.
1954	*
1955	* @param pVM The cross context VM structure.
1956	* @param fAtReset Indicates the context, after reset if @c true or after
1957	* construction if @c false.
1958	*/
1959	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
1960	{
1961	if (fAtReset)
1962	{
1963	PGM_LOCK_VOID(pVM);
1964
1965	int rc = pgmR3PhysRamZeroAll(pVM);
1966	AssertReleaseRC(rc);
1967
1968	rc = pgmR3PhysRomReset(pVM);
1969	AssertReleaseRC(rc);
1970
1971	PGM_UNLOCK(pVM);
1972	}
1973	}
1974
1975
1976	#ifdef VBOX_STRICT
1977	/**
1978	* VM state change callback for clearing fNoMorePhysWrites after
1979	* a snapshot has been created.
1980	*/
1981	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, PCVMMR3VTABLE pVMM, VMSTATE enmState,
1982	VMSTATE enmOldState, void *pvUser)
1983	{
1984	if ( enmState == VMSTATE_RUNNING
1985	\|\| enmState == VMSTATE_RESUMING)
1986	pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
1987	RT_NOREF(pVMM, enmOldState, pvUser);
1988	}
1989	#endif
1990
1991	/**
1992	* Private API to reset fNoMorePhysWrites.
1993	*/
1994	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
1995	{
1996	pVM->pgm.s.fNoMorePhysWrites = false;
1997	}
1998
1999	/**
2000	* Terminates the PGM.
2001	*
2002	* @returns VBox status code.
2003	* @param pVM The cross context VM structure.
2004	*/
2005	VMMR3DECL(int) PGMR3Term(PVM pVM)
2006	{
2007	/* Must free shared pages here. */
2008	PGM_LOCK_VOID(pVM);
2009	pgmR3PhysRamTerm(pVM);
2010	pgmR3PhysRomTerm(pVM);
2011	PGM_UNLOCK(pVM);
2012
2013	PGMDeregisterStringFormatTypes();
2014	return PDMR3CritSectDelete(pVM, &pVM->pgm.s.CritSectX);
2015	}
2016
2017
2018	/**
2019	* Show paging mode.
2020	*
2021	* @param pVM The cross context VM structure.
2022	* @param pHlp The info helpers.
2023	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2024	*/
2025	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2026	{
2027	/* digest argument. */
2028	bool fGuest, fShadow, fHost;
2029	if (pszArgs)
2030	pszArgs = RTStrStripL(pszArgs);
2031	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2032	fShadow = fHost = fGuest = true;
2033	else
2034	{
2035	fShadow = fHost = fGuest = false;
2036	if (strstr(pszArgs, "guest"))
2037	fGuest = true;
2038	if (strstr(pszArgs, "shadow"))
2039	fShadow = true;
2040	if (strstr(pszArgs, "host"))
2041	fHost = true;
2042	}
2043
2044	PVMCPU pVCpu = VMMGetCpu(pVM);
2045	if (!pVCpu)
2046	pVCpu = pVM->apCpusR3[0];
2047
2048
2049	/* print info. */
2050	if (fGuest)
2051	{
2052	pHlp->pfnPrintf(pHlp, "Guest paging mode (VCPU #%u): %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2053	pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmGuestMode), pVCpu->pgm.s.cGuestModeChanges.c,
2054	pVCpu->pgm.s.fA20Enabled ? "enabled" : "disabled", pVCpu->pgm.s.cA20Changes.c);
2055	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2056	if (pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_INVALID)
2057	pHlp->pfnPrintf(pHlp, "Guest SLAT mode (VCPU #%u): %s\n", pVCpu->idCpu,
2058	PGMGetSlatModeName(pVCpu->pgm.s.enmGuestSlatMode));
2059	#endif
2060	}
2061	if (fShadow)
2062	pHlp->pfnPrintf(pHlp, "Shadow paging mode (VCPU #%u): %s\n", pVCpu->idCpu, PGMGetModeName(pVCpu->pgm.s.enmShadowMode));
2063	if (fHost)
2064	{
2065	const char *psz;
2066	switch (pVM->pgm.s.enmHostMode)
2067	{
2068	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2069	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2070	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2071	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2072	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2073	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2074	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2075	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2076	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2077	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2078	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2079	default: psz = "unknown"; break;
2080	}
2081	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2082	}
2083	}
2084
2085
2086	/**
2087	* Dump registered MMIO ranges to the log.
2088	*
2089	* @param pVM The cross context VM structure.
2090	* @param pHlp The info helpers.
2091	* @param pszArgs Arguments, ignored.
2092	*/
2093	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2094	{
2095	bool const fVerbose = pszArgs && strstr(pszArgs, "verbose") != NULL;
2096
2097	pHlp->pfnPrintf(pHlp,
2098	"RAM ranges (pVM=%p)\n"
2099	"%.s %.s\n",
2100	pVM,
2101	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2102	sizeof(RTHCPTR) * 2, "pvHC ");
2103
2104	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2105	{
2106	pHlp->pfnPrintf(pHlp,
2107	"%RGp-%RGp %RHv %s\n",
2108	pCur->GCPhys,
2109	pCur->GCPhysLast,
2110	pCur->pvR3,
2111	pCur->pszDesc);
2112	if (fVerbose)
2113	{
2114	RTGCPHYS const cPages = pCur->cb >> X86_PAGE_SHIFT;
2115	RTGCPHYS iPage = 0;
2116	while (iPage < cPages)
2117	{
2118	RTGCPHYS const iFirstPage = iPage;
2119	PGMPAGETYPE const enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]);
2120	do
2121	iPage++;
2122	while (iPage < cPages && (PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == enmType);
2123	const char *pszType;
2124	const char *pszMore = NULL;
2125	switch (enmType)
2126	{
2127	case PGMPAGETYPE_RAM:
2128	pszType = "RAM";
2129	break;
2130
2131	case PGMPAGETYPE_MMIO2:
2132	pszType = "MMIO2";
2133	break;
2134
2135	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2136	pszType = "MMIO2-alias-MMIO";
2137	break;
2138
2139	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2140	pszType = "special-alias-MMIO";
2141	break;
2142
2143	case PGMPAGETYPE_ROM_SHADOW:
2144	case PGMPAGETYPE_ROM:
2145	{
2146	pszType = enmType == PGMPAGETYPE_ROM_SHADOW ? "ROM-shadowed" : "ROM";
2147
2148	RTGCPHYS const GCPhysFirstPg = iFirstPage * X86_PAGE_SIZE;
2149	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2150	while (pRom && GCPhysFirstPg > pRom->GCPhysLast)
2151	pRom = pRom->pNextR3;
2152	if (pRom && GCPhysFirstPg - pRom->GCPhys < pRom->cb)
2153	pszMore = pRom->pszDesc;
2154	break;
2155	}
2156
2157	case PGMPAGETYPE_MMIO:
2158	{
2159	pszType = "MMIO";
2160	PGM_LOCK_VOID(pVM);
2161	PPGMPHYSHANDLER pHandler;
2162	int rc = pgmHandlerPhysicalLookup(pVM, iFirstPage * X86_PAGE_SIZE, &pHandler);
2163	if (RT_SUCCESS(rc))
2164	pszMore = pHandler->pszDesc;
2165	PGM_UNLOCK(pVM);
2166	break;
2167	}
2168
2169	case PGMPAGETYPE_INVALID:
2170	pszType = "invalid";
2171	break;
2172
2173	default:
2174	pszType = "bad";
2175	break;
2176	}
2177	if (pszMore)
2178	pHlp->pfnPrintf(pHlp, " %RGp-%RGp %-20s %s\n",
2179	pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
2180	pCur->GCPhys + iPage * X86_PAGE_SIZE - 1,
2181	pszType, pszMore);
2182	else
2183	pHlp->pfnPrintf(pHlp, " %RGp-%RGp %s\n",
2184	pCur->GCPhys + iFirstPage * X86_PAGE_SIZE,
2185	pCur->GCPhys + iPage * X86_PAGE_SIZE - 1,
2186	pszType);
2187
2188	}
2189	}
2190	}
2191	}
2192
2193
2194	/**
2195	* Dump the page directory to the log.
2196	*
2197	* @param pVM The cross context VM structure.
2198	* @param pHlp The info helpers.
2199	* @param pszArgs Arguments, ignored.
2200	*/
2201	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2202	{
2203	/** @todo SMP support!! */
2204	PVMCPU pVCpu = pVM->apCpusR3[0];
2205
2206	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2207	/* Big pages supported? */
2208	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2209
2210	/* Global pages supported? */
2211	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2212
2213	NOREF(pszArgs);
2214
2215	/*
2216	* Get page directory addresses.
2217	*/
2218	PGM_LOCK_VOID(pVM);
2219	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2220	Assert(pPDSrc);
2221
2222	/*
2223	* Iterate the page directory.
2224	*/
2225	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2226	{
2227	X86PDE PdeSrc = pPDSrc->a[iPD];
2228	if (PdeSrc.u & X86_PDE_P)
2229	{
2230	if ((PdeSrc.u & X86_PDE_PS) && fPSE)
2231	pHlp->pfnPrintf(pHlp,
2232	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2233	iPD,
2234	pgmGstGet4MBPhysPage(pVM, PdeSrc), PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_US),
2235	!!(PdeSrc.u & X86_PDE_RW), (PdeSrc.u & X86_PDE4M_G) && fPGE);
2236	else
2237	pHlp->pfnPrintf(pHlp,
2238	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2239	iPD,
2240	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK), PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_US),
2241	!!(PdeSrc.u & X86_PDE_RW), (PdeSrc.u & X86_PDE4M_G) && fPGE);
2242	}
2243	}
2244	PGM_UNLOCK(pVM);
2245	}
2246
2247
2248	/**
2249	* Called by pgmPoolFlushAllInt prior to flushing the pool.
2250	*
2251	* @returns VBox status code, fully asserted.
2252	* @param pVCpu The cross context virtual CPU structure.
2253	*/
2254	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
2255	{
2256	/* Unmap the old CR3 value before flushing everything. */
2257	int rc = VINF_SUCCESS;
2258	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
2259	if ( idxBth < RT_ELEMENTS(g_aPgmBothModeData)
2260	&& g_aPgmBothModeData[idxBth].pfnUnmapCR3)
2261	{
2262	rc = g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
2263	AssertRC(rc);
2264	}
2265
2266	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
2267	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
2268	if ( idxShw < RT_ELEMENTS(g_aPgmShadowModeData)
2269	&& g_aPgmShadowModeData[idxShw].pfnExit)
2270	{
2271	rc = g_aPgmShadowModeData[idxShw].pfnExit(pVCpu);
2272	AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
2273	}
2274
2275	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
2276	return rc;
2277	}
2278
2279
2280	/**
2281	* Called by pgmPoolFlushAllInt after flushing the pool.
2282	*
2283	* @returns VBox status code, fully asserted.
2284	* @param pVM The cross context VM structure.
2285	* @param pVCpu The cross context virtual CPU structure.
2286	*/
2287	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
2288	{
2289	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
2290	int rc = PGMHCChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
2291	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2292	AssertRCReturn(rc, rc);
2293	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2294
2295	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL \|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_NONE);
2296	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED_32BIT
2297	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
2298	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
2299	return rc;
2300	}
2301
2302
2303	/**
2304	* Called by PGMR3PhysSetA20 after changing the A20 state.
2305	*
2306	* @param pVCpu The cross context virtual CPU structure.
2307	*/
2308	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
2309	{
2310	/** @todo Probably doing a bit too much here. */
2311	int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
2312	AssertReleaseRC(rc);
2313	rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
2314	AssertReleaseRC(rc);
2315	}
2316
2317
2318	#ifdef VBOX_WITH_DEBUGGER
2319
2320	/**
2321	* @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
2322	*/
2323	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2324	{
2325	/*
2326	* Validate input.
2327	*/
2328	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2329	PVM pVM = pUVM->pVM;
2330	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
2331
2332	if (!cArgs)
2333	{
2334	/*
2335	* Print the list of error injection locations with status.
2336	*/
2337	DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
2338	DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
2339	}
2340	else
2341	{
2342	/*
2343	* String switch on where to inject the error.
2344	*/
2345	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
2346	const char *pszWhere = paArgs[0].u.pszString;
2347	if (!strcmp(pszWhere, "handy"))
2348	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
2349	else
2350	return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
2351	DBGCCmdHlpPrintf(pCmdHlp, "done\n");
2352	}
2353	return VINF_SUCCESS;
2354	}
2355
2356
2357	/**
2358	* @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
2359	*/
2360	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2361	{
2362	/*
2363	* Validate input.
2364	*/
2365	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2366	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2367	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
2368	if (!pVCpu)
2369	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
2370
2371	/*
2372	* Force page directory sync.
2373	*/
2374	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2375
2376	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
2377	if (RT_FAILURE(rc))
2378	return rc;
2379
2380	return VINF_SUCCESS;
2381	}
2382
2383	#ifdef VBOX_STRICT
2384
2385	/**
2386	* EMT callback for pgmR3CmdAssertCR3.
2387	*
2388	* @returns VBox status code.
2389	* @param pUVM The user mode VM handle.
2390	* @param pcErrors Where to return the error count.
2391	*/
2392	static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
2393	{
2394	PVM pVM = pUVM->pVM;
2395	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
2396	PVMCPU pVCpu = VMMGetCpu(pVM);
2397
2398	*pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
2399
2400	return VINF_SUCCESS;
2401	}
2402
2403
2404	/**
2405	* @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
2406	*/
2407	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2408	{
2409	/*
2410	* Validate input.
2411	*/
2412	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2413	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2414
2415	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
2416	if (RT_FAILURE(rc))
2417	return rc;
2418
2419	unsigned cErrors = 0;
2420	rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
2421	if (RT_FAILURE(rc))
2422	return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
2423	if (cErrors > 0)
2424	return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
2425	return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
2426	}
2427
2428	#endif /* VBOX_STRICT */
2429
2430	/**
2431	* @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
2432	*/
2433	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2434	{
2435	/*
2436	* Validate input.
2437	*/
2438	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
2439	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2440	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
2441	if (!pVCpu)
2442	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
2443
2444	/*
2445	* Force page directory sync.
2446	*/
2447	int rc;
2448	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
2449	{
2450	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
2451	rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
2452	}
2453	else
2454	{
2455	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
2456	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2457	rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
2458	}
2459	return rc;
2460	}
2461
2462
2463	/**
2464	* @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
2465	*/
2466	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2467	{
2468	/*
2469	* Validate input.
2470	*/
2471	NOREF(pCmd);
2472	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
2473	PVM pVM = pUVM->pVM;
2474	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 \|\| cArgs == 2);
2475	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType == DBGCVAR_TYPE_STRING);
2476	if (cArgs == 2)
2477	{
2478	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[1].enmType == DBGCVAR_TYPE_STRING);
2479	if (strcmp(paArgs[1].u.pszString, "nozero"))
2480	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
2481	}
2482	bool fIncZeroPgs = cArgs < 2;
2483
2484	/*
2485	* Open the output file and get the ram parameters.
2486	*/
2487	RTFILE hFile;
2488	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
2489	if (RT_FAILURE(rc))
2490	return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
2491
2492	uint32_t cbRamHole = 0;
2493	CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
2494	uint64_t cbRam = 0;
2495	CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
2496	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
2497
2498	/*
2499	* Dump the physical memory, page by page.
2500	*/
2501	RTGCPHYS GCPhys = 0;
2502	char abZeroPg[GUEST_PAGE_SIZE];
2503	RT_ZERO(abZeroPg);
2504
2505	PGM_LOCK_VOID(pVM);
2506	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2507	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
2508	pRam = pRam->pNextR3)
2509	{
2510	/* fill the gap */
2511	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
2512	{
2513	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
2514	{
2515	rc = RTFileWrite(hFile, abZeroPg, GUEST_PAGE_SIZE, NULL);
2516	GCPhys += GUEST_PAGE_SIZE;
2517	}
2518	}
2519
2520	PCPGMPAGE pPage = &pRam->aPages[0];
2521	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
2522	{
2523	if ( PGM_PAGE_IS_ZERO(pPage)
2524	\|\| PGM_PAGE_IS_BALLOONED(pPage))
2525	{
2526	if (fIncZeroPgs)
2527	{
2528	rc = RTFileWrite(hFile, abZeroPg, GUEST_PAGE_SIZE, NULL);
2529	if (RT_FAILURE(rc))
2530	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2531	}
2532	}
2533	else
2534	{
2535	switch (PGM_PAGE_GET_TYPE(pPage))
2536	{
2537	case PGMPAGETYPE_RAM:
2538	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
2539	case PGMPAGETYPE_ROM:
2540	case PGMPAGETYPE_MMIO2:
2541	{
2542	void const *pvPage;
2543	PGMPAGEMAPLOCK Lock;
2544	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
2545	if (RT_SUCCESS(rc))
2546	{
2547	rc = RTFileWrite(hFile, pvPage, GUEST_PAGE_SIZE, NULL);
2548	PGMPhysReleasePageMappingLock(pVM, &Lock);
2549	if (RT_FAILURE(rc))
2550	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2551	}
2552	else
2553	DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2554	break;
2555	}
2556
2557	default:
2558	AssertFailed();
2559	RT_FALL_THRU();
2560	case PGMPAGETYPE_MMIO:
2561	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2562	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2563	if (fIncZeroPgs)
2564	{
2565	rc = RTFileWrite(hFile, abZeroPg, GUEST_PAGE_SIZE, NULL);
2566	if (RT_FAILURE(rc))
2567	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
2568	}
2569	break;
2570	}
2571	}
2572
2573
2574	/* advance */
2575	GCPhys += GUEST_PAGE_SIZE;
2576	pPage++;
2577	}
2578	}
2579	PGM_UNLOCK(pVM);
2580
2581	RTFileClose(hFile);
2582	if (RT_SUCCESS(rc))
2583	return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
2584	return VINF_SUCCESS;
2585	}
2586
2587	#endif /* VBOX_WITH_DEBUGGER */
2588
2589	/**
2590	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
2591	*/
2592	typedef struct PGMCHECKINTARGS
2593	{
2594	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
2595	uint32_t cErrors;
2596	PPGMPHYSHANDLER pPrevPhys;
2597	PVM pVM;
2598	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
2599
2600	/**
2601	* Validate a node in the physical handler tree.
2602	*
2603	* @returns 0 on if ok, other wise 1.
2604	* @param pNode The handler node.
2605	* @param pvUser pVM.
2606	*/
2607	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PPGMPHYSHANDLER pNode, void *pvUser)
2608	{
2609	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
2610
2611	AssertLogRelMsgReturnStmt(!((uintptr_t)pNode & 7), ("pNode=%p\n", pNode), pArgs->cErrors++, VERR_INVALID_POINTER);
2612
2613	AssertLogRelMsgStmt(pNode->Key <= pNode->KeyLast,
2614	("pNode=%p %RGp-%RGp %s\n", pNode, pNode->Key, pNode->KeyLast, pNode->pszDesc),
2615	pArgs->cErrors++);
2616
2617	AssertLogRelMsgStmt( !pArgs->pPrevPhys
2618	\|\| ( pArgs->fLeftToRight
2619	? pArgs->pPrevPhys->KeyLast < pNode->Key
2620	: pArgs->pPrevPhys->KeyLast > pNode->Key),
2621	("pPrevPhys=%p %RGp-%RGp %s\n"
2622	" pNode=%p %RGp-%RGp %s\n",
2623	pArgs->pPrevPhys, pArgs->pPrevPhys->Key, pArgs->pPrevPhys->KeyLast, pArgs->pPrevPhys->pszDesc,
2624	pNode, pNode->Key, pNode->KeyLast, pNode->pszDesc),
2625	pArgs->cErrors++);
2626
2627	pArgs->pPrevPhys = pNode;
2628	return 0;
2629	}
2630
2631
2632	/**
2633	* Perform an integrity check on the PGM component.
2634	*
2635	* @returns VINF_SUCCESS if everything is fine.
2636	* @returns VBox error status after asserting on integrity breach.
2637	* @param pVM The cross context VM structure.
2638	*/
2639	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
2640	{
2641	/*
2642	* Check the trees.
2643	*/
2644	PGMCHECKINTARGS Args = { true, 0, NULL, pVM };
2645	int rc = pVM->pgm.s.pPhysHandlerTree->doWithAllFromLeft(&pVM->pgm.s.PhysHandlerAllocator,
2646	pgmR3CheckIntegrityPhysHandlerNode, &Args);
2647	AssertLogRelRCReturn(rc, rc);
2648
2649	Args.fLeftToRight = false;
2650	Args.pPrevPhys = NULL;
2651	rc = pVM->pgm.s.pPhysHandlerTree->doWithAllFromRight(&pVM->pgm.s.PhysHandlerAllocator,
2652	pgmR3CheckIntegrityPhysHandlerNode, &Args);
2653	AssertLogRelMsgReturn(pVM->pgm.s.pPhysHandlerTree->m_cErrors == 0,
2654	("m_cErrors=%#x\n", pVM->pgm.s.pPhysHandlerTree->m_cErrors == 0),
2655	VERR_INTERNAL_ERROR);
2656
2657	return Args.cErrors == 0 ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
2658	}
2659

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 93732

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