VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PGMBth.h@ 61574

Last change on this file since 61574 was 58126, checked in by vboxsync, 9 years ago

VMM: Fixed almost all the Doxygen warnings.
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File size: 10.3 KB
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1/* $Id: PGMBth.h 58126 2015-10-08 20:59:48Z vboxsync $ */
2/** @file
3 * VBox - Page Manager / Monitor, Shadow+Guest Paging Template.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Internal Functions *
21*******************************************************************************/
22RT_C_DECLS_BEGIN
23PGM_BTH_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0);
24PGM_BTH_DECL(int, Enter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
25PGM_BTH_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
26
27PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
28PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
29PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uError);
30PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
31PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
32PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
33PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
34PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
35RT_C_DECLS_END
36
37
38/**
39 * Initializes the both bit of the paging mode data.
40 *
41 * @returns VBox status code.
42 * @param pVM The cross context VM structure.
43 * @param pModeData The pointer table to initialize.
44 * @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
45 * This is used early in the init process to avoid trouble with PDM
46 * not being initialized yet.
47 */
48PGM_BTH_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0)
49{
50 Assert(pModeData->uShwType == PGM_SHW_TYPE); Assert(pModeData->uGstType == PGM_GST_TYPE);
51
52 /* Ring 3 */
53 pModeData->pfnR3BthRelocate = PGM_BTH_NAME(Relocate);
54 pModeData->pfnR3BthSyncCR3 = PGM_BTH_NAME(SyncCR3);
55 pModeData->pfnR3BthInvalidatePage = PGM_BTH_NAME(InvalidatePage);
56 pModeData->pfnR3BthPrefetchPage = PGM_BTH_NAME(PrefetchPage);
57 pModeData->pfnR3BthVerifyAccessSyncPage = PGM_BTH_NAME(VerifyAccessSyncPage);
58#ifdef VBOX_STRICT
59 pModeData->pfnR3BthAssertCR3 = PGM_BTH_NAME(AssertCR3);
60#endif
61 pModeData->pfnR3BthMapCR3 = PGM_BTH_NAME(MapCR3);
62 pModeData->pfnR3BthUnmapCR3 = PGM_BTH_NAME(UnmapCR3);
63
64 if (fResolveGCAndR0)
65 {
66 int rc;
67
68 if (!HMIsEnabled(pVM))
69 {
70#if PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT /* No AMD64 for traditional virtualization, only VT-x and AMD-V. */
71 /* RC */
72 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(Trap0eHandler), &pModeData->pfnRCBthTrap0eHandler);
73 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_RC_STR(Trap0eHandler), rc), rc);
74 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(InvalidatePage), &pModeData->pfnRCBthInvalidatePage);
75 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_RC_STR(InvalidatePage), rc), rc);
76 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(SyncCR3), &pModeData->pfnRCBthSyncCR3);
77 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_RC_STR(SyncCR3), rc), rc);
78 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(PrefetchPage), &pModeData->pfnRCBthPrefetchPage);
79 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_RC_STR(PrefetchPage), rc), rc);
80 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(VerifyAccessSyncPage),&pModeData->pfnRCBthVerifyAccessSyncPage);
81 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_RC_STR(VerifyAccessSyncPage), rc), rc);
82# ifdef VBOX_STRICT
83 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(AssertCR3), &pModeData->pfnRCBthAssertCR3);
84 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_RC_STR(AssertCR3), rc), rc);
85# endif
86 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(MapCR3), &pModeData->pfnRCBthMapCR3);
87 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_RC_STR(MapCR3), rc), rc);
88 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(UnmapCR3), &pModeData->pfnRCBthUnmapCR3);
89 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_RC_STR(UnmapCR3), rc), rc);
90#endif /* Not AMD64 shadow paging. */
91 }
92
93 /* Ring 0 */
94 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(Trap0eHandler), &pModeData->pfnR0BthTrap0eHandler);
95 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_R0_STR(Trap0eHandler), rc), rc);
96 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(InvalidatePage), &pModeData->pfnR0BthInvalidatePage);
97 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_R0_STR(InvalidatePage), rc), rc);
98 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(SyncCR3), &pModeData->pfnR0BthSyncCR3);
99 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_R0_STR(SyncCR3), rc), rc);
100 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(PrefetchPage), &pModeData->pfnR0BthPrefetchPage);
101 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_R0_STR(PrefetchPage), rc), rc);
102 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(VerifyAccessSyncPage),&pModeData->pfnR0BthVerifyAccessSyncPage);
103 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_R0_STR(VerifyAccessSyncPage), rc), rc);
104#ifdef VBOX_STRICT
105 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(AssertCR3), &pModeData->pfnR0BthAssertCR3);
106 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_R0_STR(AssertCR3), rc), rc);
107#endif
108 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(MapCR3), &pModeData->pfnR0BthMapCR3);
109 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_R0_STR(MapCR3), rc), rc);
110 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(UnmapCR3), &pModeData->pfnR0BthUnmapCR3);
111 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_BTH_NAME_R0_STR(UnmapCR3), rc), rc);
112 }
113 return VINF_SUCCESS;
114}
115
116
117/**
118 * Enters the shadow+guest mode.
119 *
120 * @returns VBox status code.
121 * @param pVCpu The cross context virtual CPU structure.
122 * @param GCPhysCR3 The physical address from the CR3 register.
123 */
124PGM_BTH_DECL(int, Enter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
125{
126 /* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
127 * Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
128 */
129#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
130 || PGM_SHW_TYPE == PGM_TYPE_PAE \
131 || PGM_SHW_TYPE == PGM_TYPE_AMD64) \
132 && ( PGM_GST_TYPE == PGM_TYPE_REAL \
133 || PGM_GST_TYPE == PGM_TYPE_PROT))
134
135 PVM pVM = pVCpu->pVMR3;
136
137 Assert(HMIsNestedPagingActive(pVM) == pVM->pgm.s.fNestedPaging);
138 Assert(!pVM->pgm.s.fNestedPaging);
139
140 pgmLock(pVM);
141 /* Note: we only really need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes),
142 * but any calls to GC need a proper shadow page setup as well.
143 */
144 /* Free the previous root mapping if still active. */
145 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
146 if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
147 {
148 Assert(pVCpu->pgm.s.pShwPageCR3R3->enmKind != PGMPOOLKIND_FREE);
149
150 /* Mark the page as unlocked; allow flushing again. */
151 pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
152
153# ifndef PGM_WITHOUT_MAPPINGS
154 /* Remove the hypervisor mappings from the shadow page table. */
155 pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
156# endif
157
158 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.pShwPageCR3R3, NIL_PGMPOOL_IDX, UINT32_MAX);
159 pVCpu->pgm.s.pShwPageCR3R3 = 0;
160 pVCpu->pgm.s.pShwPageCR3RC = 0;
161 pVCpu->pgm.s.pShwPageCR3R0 = 0;
162 }
163
164 /* construct a fake address. */
165 GCPhysCR3 = RT_BIT_64(63);
166 int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
167 NIL_PGMPOOL_IDX, UINT32_MAX, false /*fLockPage*/,
168 &pVCpu->pgm.s.pShwPageCR3R3);
169 if (rc == VERR_PGM_POOL_FLUSHED)
170 {
171 Log(("Bth-Enter: PGM pool flushed -> signal sync cr3\n"));
172 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
173 pgmUnlock(pVM);
174 return VINF_PGM_SYNC_CR3;
175 }
176 AssertRCReturn(rc, rc);
177
178 /* Mark the page as locked; disallow flushing. */
179 pgmPoolLockPage(pPool, pVCpu->pgm.s.pShwPageCR3R3);
180
181 pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.pShwPageCR3R3);
182 pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.pShwPageCR3R3);
183
184 /* Set the current hypervisor CR3. */
185 CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
186
187# ifndef PGM_WITHOUT_MAPPINGS
188 /* Apply all hypervisor mappings to the new CR3. */
189 rc = pgmMapActivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
190# endif
191
192 pgmUnlock(pVM);
193 return rc;
194#else
195 NOREF(pVCpu); NOREF(GCPhysCR3);
196 return VINF_SUCCESS;
197#endif
198}
199
200
201/**
202 * Relocate any GC pointers related to shadow mode paging.
203 *
204 * @returns VBox status code.
205 * @param pVCpu The cross context virtual CPU structure.
206 * @param offDelta The relocation offset.
207 */
208PGM_BTH_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
209{
210 /* nothing special to do here - InitData does the job. */
211 NOREF(pVCpu); NOREF(offDelta);
212 return VINF_SUCCESS;
213}
214
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