PGMPhys.cpp@ 80090

Last change on this file since 80090 was 80074, checked in by vboxsync, 6 years ago
VMM,Main,++: Retired the unfinished FTM component.
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1	/* $Id: PGMPhys.cpp 80074 2019-07-31 14:18:34Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/iem.h>
25	#include <VBox/vmm/iom.h>
26	#include <VBox/vmm/mm.h>
27	#include <VBox/vmm/nem.h>
28	#include <VBox/vmm/stam.h>
29	#ifdef VBOX_WITH_REM
30	# include <VBox/vmm/rem.h>
31	#endif
32	#include <VBox/vmm/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/uvm.h>
36	#include "PGMInline.h"
37	#include <VBox/sup.h>
38	#include <VBox/param.h>
39	#include <VBox/err.h>
40	#include <VBox/log.h>
41	#include <iprt/assert.h>
42	#include <iprt/alloc.h>
43	#include <iprt/asm.h>
44	#ifdef VBOX_STRICT
45	# include <iprt/crc.h>
46	#endif
47	#include <iprt/thread.h>
48	#include <iprt/string.h>
49	#include <iprt/system.h>
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** The number of pages to free in one batch. */
56	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
57
58
59	/*
60	* PGMR3PhysReadU8-64
61	* PGMR3PhysWriteU8-64
62	*/
63	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
64	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
65	#define PGMPHYS_DATASIZE 1
66	#define PGMPHYS_DATATYPE uint8_t
67	#include "PGMPhysRWTmpl.h"
68
69	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
70	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
71	#define PGMPHYS_DATASIZE 2
72	#define PGMPHYS_DATATYPE uint16_t
73	#include "PGMPhysRWTmpl.h"
74
75	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
76	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
77	#define PGMPHYS_DATASIZE 4
78	#define PGMPHYS_DATATYPE uint32_t
79	#include "PGMPhysRWTmpl.h"
80
81	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
82	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
83	#define PGMPHYS_DATASIZE 8
84	#define PGMPHYS_DATATYPE uint64_t
85	#include "PGMPhysRWTmpl.h"
86
87
88	/**
89	* EMT worker for PGMR3PhysReadExternal.
90	*/
91	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
92	PGMACCESSORIGIN enmOrigin)
93	{
94	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
95	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
96	return VINF_SUCCESS;
97	}
98
99
100	/**
101	* Read from physical memory, external users.
102	*
103	* @returns VBox status code.
104	* @retval VINF_SUCCESS.
105	*
106	* @param pVM The cross context VM structure.
107	* @param GCPhys Physical address to read from.
108	* @param pvBuf Where to read into.
109	* @param cbRead How many bytes to read.
110	* @param enmOrigin Who is calling.
111	*
112	* @thread Any but EMTs.
113	*/
114	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
115	{
116	VM_ASSERT_OTHER_THREAD(pVM);
117
118	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
119	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
120
121	pgmLock(pVM);
122
123	/*
124	* Copy loop on ram ranges.
125	*/
126	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
127	for (;;)
128	{
129	/* Inside range or not? */
130	if (pRam && GCPhys >= pRam->GCPhys)
131	{
132	/*
133	* Must work our way thru this page by page.
134	*/
135	RTGCPHYS off = GCPhys - pRam->GCPhys;
136	while (off < pRam->cb)
137	{
138	unsigned iPage = off >> PAGE_SHIFT;
139	PPGMPAGE pPage = &pRam->aPages[iPage];
140
141	/*
142	* If the page has an ALL access handler, we'll have to
143	* delegate the job to EMT.
144	*/
145	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
146	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
147	{
148	pgmUnlock(pVM);
149
150	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
151	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
152	}
153	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
154
155	/*
156	* Simple stuff, go ahead.
157	*/
158	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
159	if (cb > cbRead)
160	cb = cbRead;
161	PGMPAGEMAPLOCK PgMpLck;
162	const void *pvSrc;
163	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
164	if (RT_SUCCESS(rc))
165	{
166	memcpy(pvBuf, pvSrc, cb);
167	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
168	}
169	else
170	{
171	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
172	pRam->GCPhys + off, pPage, rc));
173	memset(pvBuf, 0xff, cb);
174	}
175
176	/* next page */
177	if (cb >= cbRead)
178	{
179	pgmUnlock(pVM);
180	return VINF_SUCCESS;
181	}
182	cbRead -= cb;
183	off += cb;
184	GCPhys += cb;
185	pvBuf = (char *)pvBuf + cb;
186	} /* walk pages in ram range. */
187	}
188	else
189	{
190	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
191
192	/*
193	* Unassigned address space.
194	*/
195	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
196	if (cb >= cbRead)
197	{
198	memset(pvBuf, 0xff, cbRead);
199	break;
200	}
201	memset(pvBuf, 0xff, cb);
202
203	cbRead -= cb;
204	pvBuf = (char *)pvBuf + cb;
205	GCPhys += cb;
206	}
207
208	/* Advance range if necessary. */
209	while (pRam && GCPhys > pRam->GCPhysLast)
210	pRam = pRam->CTX_SUFF(pNext);
211	} /* Ram range walk */
212
213	pgmUnlock(pVM);
214
215	return VINF_SUCCESS;
216	}
217
218
219	/**
220	* EMT worker for PGMR3PhysWriteExternal.
221	*/
222	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
223	PGMACCESSORIGIN enmOrigin)
224	{
225	/** @todo VERR_EM_NO_MEMORY */
226	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
227	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
228	return VINF_SUCCESS;
229	}
230
231
232	/**
233	* Write to physical memory, external users.
234	*
235	* @returns VBox status code.
236	* @retval VINF_SUCCESS.
237	* @retval VERR_EM_NO_MEMORY.
238	*
239	* @param pVM The cross context VM structure.
240	* @param GCPhys Physical address to write to.
241	* @param pvBuf What to write.
242	* @param cbWrite How many bytes to write.
243	* @param enmOrigin Who is calling.
244	*
245	* @thread Any but EMTs.
246	*/
247	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
248	{
249	VM_ASSERT_OTHER_THREAD(pVM);
250
251	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
252	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
253	GCPhys, cbWrite, enmOrigin));
254	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
255	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
256
257	pgmLock(pVM);
258
259	/*
260	* Copy loop on ram ranges, stop when we hit something difficult.
261	*/
262	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
263	for (;;)
264	{
265	/* Inside range or not? */
266	if (pRam && GCPhys >= pRam->GCPhys)
267	{
268	/*
269	* Must work our way thru this page by page.
270	*/
271	RTGCPTR off = GCPhys - pRam->GCPhys;
272	while (off < pRam->cb)
273	{
274	RTGCPTR iPage = off >> PAGE_SHIFT;
275	PPGMPAGE pPage = &pRam->aPages[iPage];
276
277	/*
278	* Is the page problematic, we have to do the work on the EMT.
279	*
280	* Allocating writable pages and access handlers are
281	* problematic, write monitored pages are simple and can be
282	* dealt with here.
283	*/
284	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
285	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
286	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
287	{
288	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
289	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
290	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
291	else
292	{
293	pgmUnlock(pVM);
294
295	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
296	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
297	}
298	}
299	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
300
301	/*
302	* Simple stuff, go ahead.
303	*/
304	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
305	if (cb > cbWrite)
306	cb = cbWrite;
307	PGMPAGEMAPLOCK PgMpLck;
308	void *pvDst;
309	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
310	if (RT_SUCCESS(rc))
311	{
312	memcpy(pvDst, pvBuf, cb);
313	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
314	}
315	else
316	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
317	pRam->GCPhys + off, pPage, rc));
318
319	/* next page */
320	if (cb >= cbWrite)
321	{
322	pgmUnlock(pVM);
323	return VINF_SUCCESS;
324	}
325
326	cbWrite -= cb;
327	off += cb;
328	GCPhys += cb;
329	pvBuf = (const char *)pvBuf + cb;
330	} /* walk pages in ram range */
331	}
332	else
333	{
334	/*
335	* Unassigned address space, skip it.
336	*/
337	if (!pRam)
338	break;
339	size_t cb = pRam->GCPhys - GCPhys;
340	if (cb >= cbWrite)
341	break;
342	cbWrite -= cb;
343	pvBuf = (const char *)pvBuf + cb;
344	GCPhys += cb;
345	}
346
347	/* Advance range if necessary. */
348	while (pRam && GCPhys > pRam->GCPhysLast)
349	pRam = pRam->CTX_SUFF(pNext);
350	} /* Ram range walk */
351
352	pgmUnlock(pVM);
353	return VINF_SUCCESS;
354	}
355
356
357	/**
358	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
359	*
360	* @returns see PGMR3PhysGCPhys2CCPtrExternal
361	* @param pVM The cross context VM structure.
362	* @param pGCPhys Pointer to the guest physical address.
363	* @param ppv Where to store the mapping address.
364	* @param pLock Where to store the lock.
365	*/
366	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
367	{
368	/*
369	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
370	* an access handler after it succeeds.
371	*/
372	int rc = pgmLock(pVM);
373	AssertRCReturn(rc, rc);
374
375	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
376	if (RT_SUCCESS(rc))
377	{
378	PPGMPAGEMAPTLBE pTlbe;
379	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
380	AssertFatalRC(rc2);
381	PPGMPAGE pPage = pTlbe->pPage;
382	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
383	{
384	PGMPhysReleasePageMappingLock(pVM, pLock);
385	rc = VERR_PGM_PHYS_PAGE_RESERVED;
386	}
387	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
388	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
389	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
390	#endif
391	)
392	{
393	/* We must flush any corresponding pgm pool page here, otherwise we'll
394	* not be informed about writes and keep bogus gst->shw mappings around.
395	*/
396	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
397	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
398	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
399	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
400	}
401	}
402
403	pgmUnlock(pVM);
404	return rc;
405	}
406
407
408	/**
409	* Requests the mapping of a guest page into ring-3, external threads.
410	*
411	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
412	* release it.
413	*
414	* This API will assume your intention is to write to the page, and will
415	* therefore replace shared and zero pages. If you do not intend to modify the
416	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
417	*
418	* @returns VBox status code.
419	* @retval VINF_SUCCESS on success.
420	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
421	* backing or if the page has any active access handlers. The caller
422	* must fall back on using PGMR3PhysWriteExternal.
423	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
424	*
425	* @param pVM The cross context VM structure.
426	* @param GCPhys The guest physical address of the page that should be mapped.
427	* @param ppv Where to store the address corresponding to GCPhys.
428	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
429	*
430	* @remark Avoid calling this API from within critical sections (other than the
431	* PGM one) because of the deadlock risk when we have to delegating the
432	* task to an EMT.
433	* @thread Any.
434	*/
435	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
436	{
437	AssertPtr(ppv);
438	AssertPtr(pLock);
439
440	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
441
442	int rc = pgmLock(pVM);
443	AssertRCReturn(rc, rc);
444
445	/*
446	* Query the Physical TLB entry for the page (may fail).
447	*/
448	PPGMPAGEMAPTLBE pTlbe;
449	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
450	if (RT_SUCCESS(rc))
451	{
452	PPGMPAGE pPage = pTlbe->pPage;
453	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
454	rc = VERR_PGM_PHYS_PAGE_RESERVED;
455	else
456	{
457	/*
458	* If the page is shared, the zero page, or being write monitored
459	* it must be converted to an page that's writable if possible.
460	* We can only deal with write monitored pages here, the rest have
461	* to be on an EMT.
462	*/
463	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
464	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
465	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
466	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
467	#endif
468	)
469	{
470	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
471	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
472	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
473	&& !pgmPoolIsDirtyPage(pVM, GCPhys) /** @todo we're very likely doing this twice. */
474	#endif
475	)
476	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
477	else
478	{
479	pgmUnlock(pVM);
480
481	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
482	pVM, &GCPhys, ppv, pLock);
483	}
484	}
485
486	/*
487	* Now, just perform the locking and calculate the return address.
488	*/
489	PPGMPAGEMAP pMap = pTlbe->pMap;
490	if (pMap)
491	pMap->cRefs++;
492
493	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
494	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
495	{
496	if (cLocks == 0)
497	pVM->pgm.s.cWriteLockedPages++;
498	PGM_PAGE_INC_WRITE_LOCKS(pPage);
499	}
500	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
501	{
502	PGM_PAGE_INC_WRITE_LOCKS(pPage);
503	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
504	if (pMap)
505	pMap->cRefs++; /* Extra ref to prevent it from going away. */
506	}
507
508	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
509	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
510	pLock->pvMap = pMap;
511	}
512	}
513
514	pgmUnlock(pVM);
515	return rc;
516	}
517
518
519	/**
520	* Requests the mapping of a guest page into ring-3, external threads.
521	*
522	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
523	* release it.
524	*
525	* @returns VBox status code.
526	* @retval VINF_SUCCESS on success.
527	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
528	* backing or if the page as an active ALL access handler. The caller
529	* must fall back on using PGMPhysRead.
530	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
531	*
532	* @param pVM The cross context VM structure.
533	* @param GCPhys The guest physical address of the page that should be mapped.
534	* @param ppv Where to store the address corresponding to GCPhys.
535	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
536	*
537	* @remark Avoid calling this API from within critical sections (other than
538	* the PGM one) because of the deadlock risk.
539	* @thread Any.
540	*/
541	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
542	{
543	int rc = pgmLock(pVM);
544	AssertRCReturn(rc, rc);
545
546	/*
547	* Query the Physical TLB entry for the page (may fail).
548	*/
549	PPGMPAGEMAPTLBE pTlbe;
550	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
551	if (RT_SUCCESS(rc))
552	{
553	PPGMPAGE pPage = pTlbe->pPage;
554	#if 1
555	/* MMIO pages doesn't have any readable backing. */
556	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
557	rc = VERR_PGM_PHYS_PAGE_RESERVED;
558	#else
559	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
560	rc = VERR_PGM_PHYS_PAGE_RESERVED;
561	#endif
562	else
563	{
564	/*
565	* Now, just perform the locking and calculate the return address.
566	*/
567	PPGMPAGEMAP pMap = pTlbe->pMap;
568	if (pMap)
569	pMap->cRefs++;
570
571	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
572	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
573	{
574	if (cLocks == 0)
575	pVM->pgm.s.cReadLockedPages++;
576	PGM_PAGE_INC_READ_LOCKS(pPage);
577	}
578	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
579	{
580	PGM_PAGE_INC_READ_LOCKS(pPage);
581	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
582	if (pMap)
583	pMap->cRefs++; /* Extra ref to prevent it from going away. */
584	}
585
586	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
587	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
588	pLock->pvMap = pMap;
589	}
590	}
591
592	pgmUnlock(pVM);
593	return rc;
594	}
595
596
597	/**
598	* Requests the mapping of multiple guest page into ring-3, external threads.
599	*
600	* When you're done with the pages, call PGMPhysBulkReleasePageMappingLock()
601	* ASAP to release them.
602	*
603	* This API will assume your intention is to write to the pages, and will
604	* therefore replace shared and zero pages. If you do not intend to modify the
605	* pages, use the PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal() API.
606	*
607	* @returns VBox status code.
608	* @retval VINF_SUCCESS on success.
609	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
610	* backing or if any of the pages the page has any active access
611	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
612	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
613	* an invalid physical address.
614	*
615	* @param pVM The cross context VM structure.
616	* @param cPages Number of pages to lock.
617	* @param paGCPhysPages The guest physical address of the pages that
618	* should be mapped (@a cPages entries).
619	* @param papvPages Where to store the ring-3 mapping addresses
620	* corresponding to @a paGCPhysPages.
621	* @param paLocks Where to store the locking information that
622	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
623	* in length).
624	*
625	* @remark Avoid calling this API from within critical sections (other than the
626	* PGM one) because of the deadlock risk when we have to delegating the
627	* task to an EMT.
628	* @thread Any.
629	*/
630	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
631	void **papvPages, PPGMPAGEMAPLOCK paLocks)
632	{
633	Assert(cPages > 0);
634	AssertPtr(papvPages);
635	AssertPtr(paLocks);
636
637	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
638
639	int rc = pgmLock(pVM);
640	AssertRCReturn(rc, rc);
641
642	/*
643	* Lock the pages one by one.
644	* The loop body is similar to PGMR3PhysGCPhys2CCPtrExternal.
645	*/
646	int32_t cNextYield = 128;
647	uint32_t iPage;
648	for (iPage = 0; iPage < cPages; iPage++)
649	{
650	if (--cNextYield > 0)
651	{ /* likely */ }
652	else
653	{
654	pgmUnlock(pVM);
655	ASMNopPause();
656	pgmLock(pVM);
657	cNextYield = 128;
658	}
659
660	/*
661	* Query the Physical TLB entry for the page (may fail).
662	*/
663	PPGMPAGEMAPTLBE pTlbe;
664	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
665	if (RT_SUCCESS(rc))
666	{ }
667	else
668	break;
669	PPGMPAGE pPage = pTlbe->pPage;
670
671	/*
672	* No MMIO or active access handlers.
673	*/
674	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
675	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
676	{ }
677	else
678	{
679	rc = VERR_PGM_PHYS_PAGE_RESERVED;
680	break;
681	}
682
683	/*
684	* The page must be in the allocated state and not be a dirty pool page.
685	* We can handle converting a write monitored page to an allocated one, but
686	* anything more complicated must be delegated to an EMT.
687	*/
688	bool fDelegateToEmt = false;
689	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
690	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
691	fDelegateToEmt = pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]);
692	#else
693	fDelegateToEmt = false;
694	#endif
695	else if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
696	{
697	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
698	if (!pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]))
699	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, paGCPhysPages[iPage]);
700	else
701	fDelegateToEmt = true;
702	#endif
703	}
704	else
705	fDelegateToEmt = true;
706	if (!fDelegateToEmt)
707	{ }
708	else
709	{
710	/* We could do this delegation in bulk, but considered too much work vs gain. */
711	pgmUnlock(pVM);
712	rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
713	pVM, &paGCPhysPages[iPage], &papvPages[iPage], &paLocks[iPage]);
714	pgmLock(pVM);
715	if (RT_FAILURE(rc))
716	break;
717	cNextYield = 128;
718	}
719
720	/*
721	* Now, just perform the locking and address calculation.
722	*/
723	PPGMPAGEMAP pMap = pTlbe->pMap;
724	if (pMap)
725	pMap->cRefs++;
726
727	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
728	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
729	{
730	if (cLocks == 0)
731	pVM->pgm.s.cWriteLockedPages++;
732	PGM_PAGE_INC_WRITE_LOCKS(pPage);
733	}
734	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
735	{
736	PGM_PAGE_INC_WRITE_LOCKS(pPage);
737	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", paGCPhysPages[iPage], pPage));
738	if (pMap)
739	pMap->cRefs++; /* Extra ref to prevent it from going away. */
740	}
741
742	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
743	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
744	paLocks[iPage].pvMap = pMap;
745	}
746
747	pgmUnlock(pVM);
748
749	/*
750	* On failure we must unlock any pages we managed to get already.
751	*/
752	if (RT_FAILURE(rc) && iPage > 0)
753	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
754
755	return rc;
756	}
757
758
759	/**
760	* Requests the mapping of multiple guest page into ring-3, for reading only,
761	* external threads.
762	*
763	* When you're done with the pages, call PGMPhysReleasePageMappingLock() ASAP
764	* to release them.
765	*
766	* @returns VBox status code.
767	* @retval VINF_SUCCESS on success.
768	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
769	* backing or if any of the pages the page has an active ALL access
770	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
771	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
772	* an invalid physical address.
773	*
774	* @param pVM The cross context VM structure.
775	* @param cPages Number of pages to lock.
776	* @param paGCPhysPages The guest physical address of the pages that
777	* should be mapped (@a cPages entries).
778	* @param papvPages Where to store the ring-3 mapping addresses
779	* corresponding to @a paGCPhysPages.
780	* @param paLocks Where to store the lock information that
781	* pfnPhysReleasePageMappingLock needs (@a cPages
782	* in length).
783	*
784	* @remark Avoid calling this API from within critical sections (other than
785	* the PGM one) because of the deadlock risk.
786	* @thread Any.
787	*/
788	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
789	void const **papvPages, PPGMPAGEMAPLOCK paLocks)
790	{
791	Assert(cPages > 0);
792	AssertPtr(papvPages);
793	AssertPtr(paLocks);
794
795	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
796
797	int rc = pgmLock(pVM);
798	AssertRCReturn(rc, rc);
799
800	/*
801	* Lock the pages one by one.
802	* The loop body is similar to PGMR3PhysGCPhys2CCPtrReadOnlyExternal.
803	*/
804	int32_t cNextYield = 256;
805	uint32_t iPage;
806	for (iPage = 0; iPage < cPages; iPage++)
807	{
808	if (--cNextYield > 0)
809	{ /* likely */ }
810	else
811	{
812	pgmUnlock(pVM);
813	ASMNopPause();
814	pgmLock(pVM);
815	cNextYield = 256;
816	}
817
818	/*
819	* Query the Physical TLB entry for the page (may fail).
820	*/
821	PPGMPAGEMAPTLBE pTlbe;
822	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
823	if (RT_SUCCESS(rc))
824	{ }
825	else
826	break;
827	PPGMPAGE pPage = pTlbe->pPage;
828
829	/*
830	* No MMIO or active all access handlers, everything else can be accessed.
831	*/
832	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
833	&& !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
834	{ }
835	else
836	{
837	rc = VERR_PGM_PHYS_PAGE_RESERVED;
838	break;
839	}
840
841	/*
842	* Now, just perform the locking and address calculation.
843	*/
844	PPGMPAGEMAP pMap = pTlbe->pMap;
845	if (pMap)
846	pMap->cRefs++;
847
848	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
849	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
850	{
851	if (cLocks == 0)
852	pVM->pgm.s.cReadLockedPages++;
853	PGM_PAGE_INC_READ_LOCKS(pPage);
854	}
855	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
856	{
857	PGM_PAGE_INC_READ_LOCKS(pPage);
858	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", paGCPhysPages[iPage], pPage));
859	if (pMap)
860	pMap->cRefs++; /* Extra ref to prevent it from going away. */
861	}
862
863	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
864	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
865	paLocks[iPage].pvMap = pMap;
866	}
867
868	pgmUnlock(pVM);
869
870	/*
871	* On failure we must unlock any pages we managed to get already.
872	*/
873	if (RT_FAILURE(rc) && iPage > 0)
874	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
875
876	return rc;
877	}
878
879
880	#define MAKE_LEAF(a_pNode) \
881	do { \
882	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
883	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
884	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
885	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
886	(a_pNode)->pLeftRC = NIL_RTRCPTR; \
887	(a_pNode)->pRightRC = NIL_RTRCPTR; \
888	} while (0)
889
890	#define INSERT_LEFT(a_pParent, a_pNode) \
891	do { \
892	(a_pParent)->pLeftR3 = (a_pNode); \
893	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
894	(a_pParent)->pLeftRC = (a_pNode)->pSelfRC; \
895	} while (0)
896	#define INSERT_RIGHT(a_pParent, a_pNode) \
897	do { \
898	(a_pParent)->pRightR3 = (a_pNode); \
899	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
900	(a_pParent)->pRightRC = (a_pNode)->pSelfRC; \
901	} while (0)
902
903
904	/**
905	* Recursive tree builder.
906	*
907	* @param ppRam Pointer to the iterator variable.
908	* @param iDepth The current depth. Inserts a leaf node if 0.
909	*/
910	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
911	{
912	PPGMRAMRANGE pRam;
913	if (iDepth <= 0)
914	{
915	/*
916	* Leaf node.
917	*/
918	pRam = *ppRam;
919	if (pRam)
920	{
921	*ppRam = pRam->pNextR3;
922	MAKE_LEAF(pRam);
923	}
924	}
925	else
926	{
927
928	/*
929	* Intermediate node.
930	*/
931	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
932
933	pRam = *ppRam;
934	if (!pRam)
935	return pLeft;
936	*ppRam = pRam->pNextR3;
937	MAKE_LEAF(pRam);
938	INSERT_LEFT(pRam, pLeft);
939
940	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
941	if (pRight)
942	INSERT_RIGHT(pRam, pRight);
943	}
944	return pRam;
945	}
946
947
948	/**
949	* Rebuilds the RAM range search trees.
950	*
951	* @param pVM The cross context VM structure.
952	*/
953	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
954	{
955
956	/*
957	* Create the reasonably balanced tree in a sequential fashion.
958	* For simplicity (laziness) we use standard recursion here.
959	*/
960	int iDepth = 0;
961	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
962	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
963	while (pRam)
964	{
965	PPGMRAMRANGE pLeft = pRoot;
966
967	pRoot = pRam;
968	pRam = pRam->pNextR3;
969	MAKE_LEAF(pRoot);
970	INSERT_LEFT(pRoot, pLeft);
971
972	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
973	if (pRight)
974	INSERT_RIGHT(pRoot, pRight);
975	/** @todo else: rotate the tree. */
976
977	iDepth++;
978	}
979
980	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
981	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
982	pVM->pgm.s.pRamRangeTreeRC = pRoot ? pRoot->pSelfRC : NIL_RTRCPTR;
983
984	#ifdef VBOX_STRICT
985	/*
986	* Verify that the above code works.
987	*/
988	unsigned cRanges = 0;
989	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
990	cRanges++;
991	Assert(cRanges > 0);
992
993	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
994	if ((1U << cMaxDepth) < cRanges)
995	cMaxDepth++;
996
997	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
998	{
999	unsigned cDepth = 0;
1000	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
1001	for (;;)
1002	{
1003	if (pRam == pRam2)
1004	break;
1005	Assert(pRam2);
1006	if (pRam->GCPhys < pRam2->GCPhys)
1007	pRam2 = pRam2->pLeftR3;
1008	else
1009	pRam2 = pRam2->pRightR3;
1010	}
1011	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
1012	}
1013	#endif /* VBOX_STRICT */
1014	}
1015
1016	#undef MAKE_LEAF
1017	#undef INSERT_LEFT
1018	#undef INSERT_RIGHT
1019
1020	/**
1021	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
1022	*
1023	* Called when anything was relocated.
1024	*
1025	* @param pVM The cross context VM structure.
1026	*/
1027	void pgmR3PhysRelinkRamRanges(PVM pVM)
1028	{
1029	PPGMRAMRANGE pCur;
1030
1031	#ifdef VBOX_STRICT
1032	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1033	{
1034	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
1035	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
1036	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
1037	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1038	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
1039	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
1040	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
1041	Assert( pCur2 == pCur
1042	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
1043	}
1044	#endif
1045
1046	pCur = pVM->pgm.s.pRamRangesXR3;
1047	if (pCur)
1048	{
1049	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
1050	pVM->pgm.s.pRamRangesXRC = pCur->pSelfRC;
1051
1052	for (; pCur->pNextR3; pCur = pCur->pNextR3)
1053	{
1054	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
1055	pCur->pNextRC = pCur->pNextR3->pSelfRC;
1056	}
1057
1058	Assert(pCur->pNextR0 == NIL_RTR0PTR);
1059	Assert(pCur->pNextRC == NIL_RTRCPTR);
1060	}
1061	else
1062	{
1063	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
1064	Assert(pVM->pgm.s.pRamRangesXRC == NIL_RTRCPTR);
1065	}
1066	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1067
1068	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1069	}
1070
1071
1072	/**
1073	* Links a new RAM range into the list.
1074	*
1075	* @param pVM The cross context VM structure.
1076	* @param pNew Pointer to the new list entry.
1077	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1078	*/
1079	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
1080	{
1081	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
1082	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
1083	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
1084
1085	pgmLock(pVM);
1086
1087	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
1088	pNew->pNextR3 = pRam;
1089	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
1090	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
1091
1092	if (pPrev)
1093	{
1094	pPrev->pNextR3 = pNew;
1095	pPrev->pNextR0 = pNew->pSelfR0;
1096	pPrev->pNextRC = pNew->pSelfRC;
1097	}
1098	else
1099	{
1100	pVM->pgm.s.pRamRangesXR3 = pNew;
1101	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
1102	pVM->pgm.s.pRamRangesXRC = pNew->pSelfRC;
1103	}
1104	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1105
1106	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1107	pgmUnlock(pVM);
1108	}
1109
1110
1111	/**
1112	* Unlink an existing RAM range from the list.
1113	*
1114	* @param pVM The cross context VM structure.
1115	* @param pRam Pointer to the new list entry.
1116	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1117	*/
1118	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
1119	{
1120	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
1121	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
1122	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
1123
1124	pgmLock(pVM);
1125
1126	PPGMRAMRANGE pNext = pRam->pNextR3;
1127	if (pPrev)
1128	{
1129	pPrev->pNextR3 = pNext;
1130	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1131	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
1132	}
1133	else
1134	{
1135	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
1136	pVM->pgm.s.pRamRangesXR3 = pNext;
1137	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1138	pVM->pgm.s.pRamRangesXRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
1139	}
1140	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1141
1142	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1143	pgmUnlock(pVM);
1144	}
1145
1146
1147	/**
1148	* Unlink an existing RAM range from the list.
1149	*
1150	* @param pVM The cross context VM structure.
1151	* @param pRam Pointer to the new list entry.
1152	*/
1153	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
1154	{
1155	pgmLock(pVM);
1156
1157	/* find prev. */
1158	PPGMRAMRANGE pPrev = NULL;
1159	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
1160	while (pCur != pRam)
1161	{
1162	pPrev = pCur;
1163	pCur = pCur->pNextR3;
1164	}
1165	AssertFatal(pCur);
1166
1167	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
1168	pgmUnlock(pVM);
1169	}
1170
1171
1172	/**
1173	* Frees a range of pages, replacing them with ZERO pages of the specified type.
1174	*
1175	* @returns VBox status code.
1176	* @param pVM The cross context VM structure.
1177	* @param pRam The RAM range in which the pages resides.
1178	* @param GCPhys The address of the first page.
1179	* @param GCPhysLast The address of the last page.
1180	* @param enmType The page type to replace then with.
1181	*/
1182	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPAGETYPE enmType)
1183	{
1184	PGM_LOCK_ASSERT_OWNER(pVM);
1185	uint32_t cPendingPages = 0;
1186	PGMMFREEPAGESREQ pReq;
1187	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1188	AssertLogRelRCReturn(rc, rc);
1189
1190	/* Iterate the pages. */
1191	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1192	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1193	while (cPagesLeft-- > 0)
1194	{
1195	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys, enmType);
1196	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1197
1198	PGM_PAGE_SET_TYPE(pVM, pPageDst, enmType);
1199
1200	GCPhys += PAGE_SIZE;
1201	pPageDst++;
1202	}
1203
1204	if (cPendingPages)
1205	{
1206	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1207	AssertLogRelRCReturn(rc, rc);
1208	}
1209	GMMR3FreePagesCleanup(pReq);
1210
1211	return rc;
1212	}
1213
1214	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1215
1216	/**
1217	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
1218	*
1219	* This is only called on one of the EMTs while the other ones are waiting for
1220	* it to complete this function.
1221	*
1222	* @returns VINF_SUCCESS (VBox strict status code).
1223	* @param pVM The cross context VM structure.
1224	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1225	* @param pvUser User parameter
1226	*/
1227	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1228	{
1229	uintptr_t paUser = (uintptr_t )pvUser;
1230	bool fInflate = !!paUser[0];
1231	unsigned cPages = paUser[1];
1232	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
1233	uint32_t cPendingPages = 0;
1234	PGMMFREEPAGESREQ pReq;
1235	int rc;
1236
1237	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
1238	pgmLock(pVM);
1239
1240	if (fInflate)
1241	{
1242	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
1243	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
1244
1245	/* Replace pages with ZERO pages. */
1246	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1247	if (RT_FAILURE(rc))
1248	{
1249	pgmUnlock(pVM);
1250	AssertLogRelRC(rc);
1251	return rc;
1252	}
1253
1254	/* Iterate the pages. */
1255	for (unsigned i = 0; i < cPages; i++)
1256	{
1257	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1258	if ( pPage == NULL
1259	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
1260	{
1261	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
1262	break;
1263	}
1264
1265	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
1266
1267	/* Flush the shadow PT if this page was previously used as a guest page table. */
1268	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
1269
1270	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i], (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
1271	if (RT_FAILURE(rc))
1272	{
1273	pgmUnlock(pVM);
1274	AssertLogRelRC(rc);
1275	return rc;
1276	}
1277	Assert(PGM_PAGE_IS_ZERO(pPage));
1278	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
1279	}
1280
1281	if (cPendingPages)
1282	{
1283	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1284	if (RT_FAILURE(rc))
1285	{
1286	pgmUnlock(pVM);
1287	AssertLogRelRC(rc);
1288	return rc;
1289	}
1290	}
1291	GMMR3FreePagesCleanup(pReq);
1292	}
1293	else
1294	{
1295	/* Iterate the pages. */
1296	for (unsigned i = 0; i < cPages; i++)
1297	{
1298	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1299	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
1300
1301	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
1302
1303	Assert(PGM_PAGE_IS_BALLOONED(pPage));
1304
1305	/* Change back to zero page. (NEM does not need to be informed.) */
1306	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1307	}
1308
1309	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
1310	}
1311
1312	/* Notify GMM about the balloon change. */
1313	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
1314	if (RT_SUCCESS(rc))
1315	{
1316	if (!fInflate)
1317	{
1318	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
1319	pVM->pgm.s.cBalloonedPages -= cPages;
1320	}
1321	else
1322	pVM->pgm.s.cBalloonedPages += cPages;
1323	}
1324
1325	pgmUnlock(pVM);
1326
1327	/* Flush the recompiler's TLB as well. */
1328	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1329	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1330
1331	AssertLogRelRC(rc);
1332	return rc;
1333	}
1334
1335
1336	/**
1337	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
1338	*
1339	* @returns VBox status code.
1340	* @param pVM The cross context VM structure.
1341	* @param fInflate Inflate or deflate memory balloon
1342	* @param cPages Number of pages to free
1343	* @param paPhysPage Array of guest physical addresses
1344	*/
1345	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1346	{
1347	uintptr_t paUser[3];
1348
1349	paUser[0] = fInflate;
1350	paUser[1] = cPages;
1351	paUser[2] = (uintptr_t)paPhysPage;
1352	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1353	AssertRC(rc);
1354
1355	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
1356	RTMemFree(paPhysPage);
1357	}
1358
1359	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
1360
1361	/**
1362	* Inflate or deflate a memory balloon
1363	*
1364	* @returns VBox status code.
1365	* @param pVM The cross context VM structure.
1366	* @param fInflate Inflate or deflate memory balloon
1367	* @param cPages Number of pages to free
1368	* @param paPhysPage Array of guest physical addresses
1369	*/
1370	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1371	{
1372	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
1373	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1374	int rc;
1375
1376	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
1377	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
1378
1379	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
1380	* In the SMP case we post a request packet to postpone the job.
1381	*/
1382	if (pVM->cCpus > 1)
1383	{
1384	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
1385	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
1386	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
1387
1388	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
1389
1390	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
1391	AssertRC(rc);
1392	}
1393	else
1394	{
1395	uintptr_t paUser[3];
1396
1397	paUser[0] = fInflate;
1398	paUser[1] = cPages;
1399	paUser[2] = (uintptr_t)paPhysPage;
1400	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1401	AssertRC(rc);
1402	}
1403	return rc;
1404
1405	#else
1406	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
1407	return VERR_NOT_IMPLEMENTED;
1408	#endif
1409	}
1410
1411
1412	/**
1413	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
1414	* physical RAM.
1415	*
1416	* This is only called on one of the EMTs while the other ones are waiting for
1417	* it to complete this function.
1418	*
1419	* @returns VINF_SUCCESS (VBox strict status code).
1420	* @param pVM The cross context VM structure.
1421	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1422	* @param pvUser User parameter, unused.
1423	*/
1424	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1425	{
1426	int rc = VINF_SUCCESS;
1427	NOREF(pvUser); NOREF(pVCpu);
1428
1429	pgmLock(pVM);
1430	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1431	pgmPoolResetDirtyPages(pVM);
1432	#endif
1433
1434	/** @todo pointless to write protect the physical page pointed to by RSP. */
1435
1436	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1437	pRam;
1438	pRam = pRam->CTX_SUFF(pNext))
1439	{
1440	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1441	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1442	{
1443	PPGMPAGE pPage = &pRam->aPages[iPage];
1444	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1445
1446	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1447	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1448	{
1449	/*
1450	* A RAM page.
1451	*/
1452	switch (PGM_PAGE_GET_STATE(pPage))
1453	{
1454	case PGM_PAGE_STATE_ALLOCATED:
1455	/** @todo Optimize this: Don't always re-enable write
1456	* monitoring if the page is known to be very busy. */
1457	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
1458	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1459
1460	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1461	break;
1462
1463	case PGM_PAGE_STATE_SHARED:
1464	AssertFailed();
1465	break;
1466
1467	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
1468	default:
1469	break;
1470	}
1471	}
1472	}
1473	}
1474	pgmR3PoolWriteProtectPages(pVM);
1475	PGM_INVL_ALL_VCPU_TLBS(pVM);
1476	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1477	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1478
1479	pgmUnlock(pVM);
1480	return rc;
1481	}
1482
1483	/**
1484	* Protect all physical RAM to monitor writes
1485	*
1486	* @returns VBox status code.
1487	* @param pVM The cross context VM structure.
1488	*/
1489	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
1490	{
1491	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1492
1493	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
1494	AssertRC(rc);
1495	return rc;
1496	}
1497
1498
1499	/**
1500	* Gets the number of ram ranges.
1501	*
1502	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1503	* @param pVM The cross context VM structure.
1504	*/
1505	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1506	{
1507	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1508
1509	pgmLock(pVM);
1510	uint32_t cRamRanges = 0;
1511	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1512	cRamRanges++;
1513	pgmUnlock(pVM);
1514	return cRamRanges;
1515	}
1516
1517
1518	/**
1519	* Get information about a range.
1520	*
1521	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1522	* @param pVM The cross context VM structure.
1523	* @param iRange The ordinal of the range.
1524	* @param pGCPhysStart Where to return the start of the range. Optional.
1525	* @param pGCPhysLast Where to return the address of the last byte in the
1526	* range. Optional.
1527	* @param ppszDesc Where to return the range description. Optional.
1528	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1529	* Optional.
1530	*/
1531	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1532	const char *ppszDesc, bool pfIsMmio)
1533	{
1534	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1535
1536	pgmLock(pVM);
1537	uint32_t iCurRange = 0;
1538	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1539	if (iCurRange == iRange)
1540	{
1541	if (pGCPhysStart)
1542	*pGCPhysStart = pCur->GCPhys;
1543	if (pGCPhysLast)
1544	*pGCPhysLast = pCur->GCPhysLast;
1545	if (ppszDesc)
1546	*ppszDesc = pCur->pszDesc;
1547	if (pfIsMmio)
1548	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1549
1550	pgmUnlock(pVM);
1551	return VINF_SUCCESS;
1552	}
1553	pgmUnlock(pVM);
1554	return VERR_OUT_OF_RANGE;
1555	}
1556
1557
1558	/**
1559	* Query the amount of free memory inside VMMR0
1560	*
1561	* @returns VBox status code.
1562	* @param pUVM The user mode VM handle.
1563	* @param pcbAllocMem Where to return the amount of memory allocated
1564	* by VMs.
1565	* @param pcbFreeMem Where to return the amount of memory that is
1566	* allocated from the host but not currently used
1567	* by any VMs.
1568	* @param pcbBallonedMem Where to return the sum of memory that is
1569	* currently ballooned by the VMs.
1570	* @param pcbSharedMem Where to return the amount of memory that is
1571	* currently shared.
1572	*/
1573	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
1574	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
1575	{
1576	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1577	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
1578
1579	uint64_t cAllocPages = 0;
1580	uint64_t cFreePages = 0;
1581	uint64_t cBalloonPages = 0;
1582	uint64_t cSharedPages = 0;
1583	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
1584	AssertRCReturn(rc, rc);
1585
1586	if (pcbAllocMem)
1587	pcbAllocMem = cAllocPages _4K;
1588
1589	if (pcbFreeMem)
1590	pcbFreeMem = cFreePages _4K;
1591
1592	if (pcbBallonedMem)
1593	pcbBallonedMem = cBalloonPages _4K;
1594
1595	if (pcbSharedMem)
1596	pcbSharedMem = cSharedPages _4K;
1597
1598	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
1599	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
1600	return VINF_SUCCESS;
1601	}
1602
1603
1604	/**
1605	* Query memory stats for the VM.
1606	*
1607	* @returns VBox status code.
1608	* @param pUVM The user mode VM handle.
1609	* @param pcbTotalMem Where to return total amount memory the VM may
1610	* possibly use.
1611	* @param pcbPrivateMem Where to return the amount of private memory
1612	* currently allocated.
1613	* @param pcbSharedMem Where to return the amount of actually shared
1614	* memory currently used by the VM.
1615	* @param pcbZeroMem Where to return the amount of memory backed by
1616	* zero pages.
1617	*
1618	* @remarks The total mem is normally larger than the sum of the three
1619	* components. There are two reasons for this, first the amount of
1620	* shared memory is what we're sure is shared instead of what could
1621	* possibly be shared with someone. Secondly, because the total may
1622	* include some pure MMIO pages that doesn't go into any of the three
1623	* sub-counts.
1624	*
1625	* @todo Why do we return reused shared pages instead of anything that could
1626	* potentially be shared? Doesn't this mean the first VM gets a much
1627	* lower number of shared pages?
1628	*/
1629	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
1630	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
1631	{
1632	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1633	PVM pVM = pUVM->pVM;
1634	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1635
1636	if (pcbTotalMem)
1637	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
1638
1639	if (pcbPrivateMem)
1640	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
1641
1642	if (pcbSharedMem)
1643	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
1644
1645	if (pcbZeroMem)
1646	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
1647
1648	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
1649	return VINF_SUCCESS;
1650	}
1651
1652
1653	/**
1654	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1655	*
1656	* @param pVM The cross context VM structure.
1657	* @param pNew The new RAM range.
1658	* @param GCPhys The address of the RAM range.
1659	* @param GCPhysLast The last address of the RAM range.
1660	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
1661	* if in HMA.
1662	* @param R0PtrNew Ditto for R0.
1663	* @param pszDesc The description.
1664	* @param pPrev The previous RAM range (for linking).
1665	*/
1666	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1667	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
1668	{
1669	/*
1670	* Initialize the range.
1671	*/
1672	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
1673	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
1674	pNew->GCPhys = GCPhys;
1675	pNew->GCPhysLast = GCPhysLast;
1676	pNew->cb = GCPhysLast - GCPhys + 1;
1677	pNew->pszDesc = pszDesc;
1678	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
1679	pNew->pvR3 = NULL;
1680	pNew->paLSPages = NULL;
1681
1682	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1683	RTGCPHYS iPage = cPages;
1684	while (iPage-- > 0)
1685	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1686
1687	/* Update the page count stats. */
1688	pVM->pgm.s.cZeroPages += cPages;
1689	pVM->pgm.s.cAllPages += cPages;
1690
1691	/*
1692	* Link it.
1693	*/
1694	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1695	}
1696
1697
1698	/**
1699	* @callback_method_impl{FNPGMRELOCATE, Relocate a floating RAM range.}
1700	* @sa pgmR3PhysMMIO2ExRangeRelocate
1701	*/
1702	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
1703	PGMRELOCATECALL enmMode, void *pvUser)
1704	{
1705	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1706	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1707	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE); RT_NOREF_PV(GCPtrOld);
1708
1709	switch (enmMode)
1710	{
1711	case PGMRELOCATECALL_SUGGEST:
1712	return true;
1713
1714	case PGMRELOCATECALL_RELOCATE:
1715	{
1716	/*
1717	* Update myself, then relink all the ranges and flush the RC TLB.
1718	*/
1719	pgmLock(pVM);
1720
1721	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1722
1723	pgmR3PhysRelinkRamRanges(pVM);
1724	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
1725	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
1726
1727	pgmUnlock(pVM);
1728	return true;
1729	}
1730
1731	default:
1732	AssertFailedReturn(false);
1733	}
1734	}
1735
1736
1737	/**
1738	* PGMR3PhysRegisterRam worker that registers a high chunk.
1739	*
1740	* @returns VBox status code.
1741	* @param pVM The cross context VM structure.
1742	* @param GCPhys The address of the RAM.
1743	* @param cRamPages The number of RAM pages to register.
1744	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1745	* @param iChunk The chunk number.
1746	* @param pszDesc The RAM range description.
1747	* @param ppPrev Previous RAM range pointer. In/Out.
1748	*/
1749	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1750	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1751	PPGMRAMRANGE *ppPrev)
1752	{
1753	const char *pszDescChunk = iChunk == 0
1754	? pszDesc
1755	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1756	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1757
1758	/*
1759	* Allocate memory for the new chunk.
1760	*/
1761	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1762	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1763	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1764	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1765	void *pvChunk = NULL;
1766	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1767	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
1768	&R0PtrChunk,
1769	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
1770	VM_IS_HM_OR_NEM_ENABLED(pVM) ? &R0PtrChunk : NULL,
1771	#else
1772	NULL,
1773	#endif
1774	paChunkPages);
1775	if (RT_SUCCESS(rc))
1776	{
1777	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
1778	Assert(R0PtrChunk != NIL_RTR0PTR);
1779	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
1780	if (!VM_IS_HM_OR_NEM_ENABLED(pVM))
1781	R0PtrChunk = NIL_RTR0PTR;
1782	#else
1783	R0PtrChunk = (uintptr_t)pvChunk;
1784	#endif
1785	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1786
1787	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1788
1789	/*
1790	* Create a mapping and map the pages into it.
1791	* We push these in below the HMA.
1792	*/
1793	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1794	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1795	if (RT_SUCCESS(rc))
1796	{
1797	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1798
1799	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1800	RTGCPTR GCPtrPage = GCPtrChunk;
1801	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1802	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1803	if (RT_SUCCESS(rc))
1804	{
1805	/*
1806	* Ok, init and link the range.
1807	*/
1808	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1809	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1810	*ppPrev = pNew;
1811	}
1812	}
1813
1814	if (RT_FAILURE(rc))
1815	SUPR3PageFreeEx(pvChunk, cChunkPages);
1816	}
1817
1818	RTMemTmpFree(paChunkPages);
1819	return rc;
1820	}
1821
1822
1823	/**
1824	* Sets up a range RAM.
1825	*
1826	* This will check for conflicting registrations, make a resource
1827	* reservation for the memory (with GMM), and setup the per-page
1828	* tracking structures (PGMPAGE).
1829	*
1830	* @returns VBox status code.
1831	* @param pVM The cross context VM structure.
1832	* @param GCPhys The physical address of the RAM.
1833	* @param cb The size of the RAM.
1834	* @param pszDesc The description - not copied, so, don't free or change it.
1835	*/
1836	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1837	{
1838	/*
1839	* Validate input.
1840	*/
1841	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1842	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1843	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1844	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1845	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1846	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1847	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1848	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1849
1850	pgmLock(pVM);
1851
1852	/*
1853	* Find range location and check for conflicts.
1854	* (We don't lock here because the locking by EMT is only required on update.)
1855	*/
1856	PPGMRAMRANGE pPrev = NULL;
1857	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1858	while (pRam && GCPhysLast >= pRam->GCPhys)
1859	{
1860	if ( GCPhysLast >= pRam->GCPhys
1861	&& GCPhys <= pRam->GCPhysLast)
1862	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1863	GCPhys, GCPhysLast, pszDesc,
1864	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1865	VERR_PGM_RAM_CONFLICT);
1866
1867	/* next */
1868	pPrev = pRam;
1869	pRam = pRam->pNextR3;
1870	}
1871
1872	/*
1873	* Register it with GMM (the API bitches).
1874	*/
1875	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1876	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1877	if (RT_FAILURE(rc))
1878	{
1879	pgmUnlock(pVM);
1880	return rc;
1881	}
1882
1883	if ( GCPhys >= _4G
1884	&& cPages > 256)
1885	{
1886	/*
1887	* The PGMRAMRANGE structures for the high memory can get very big.
1888	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1889	* allocation size limit there and also to avoid being unable to find
1890	* guest mapping space for them, we split this memory up into 4MB in
1891	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1892	* mode.
1893	*
1894	* The first and last page of each mapping are guard pages and marked
1895	* not-present. So, we've got 4186112 and 16769024 bytes available for
1896	* the PGMRAMRANGE structure.
1897	*
1898	* Note! The sizes used here will influence the saved state.
1899	*/
1900	uint32_t cbChunk;
1901	uint32_t cPagesPerChunk;
1902	if (!VM_IS_RAW_MODE_ENABLED(pVM))
1903	{
1904	cbChunk = 16U*_1M;
1905	cPagesPerChunk = 1048048; /* max ~1048059 */
1906	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1907	}
1908	else
1909	{
1910	cbChunk = 4U*_1M;
1911	cPagesPerChunk = 261616; /* max ~261627 */
1912	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1913	}
1914	AssertRelease(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1915
1916	RTGCPHYS cPagesLeft = cPages;
1917	RTGCPHYS GCPhysChunk = GCPhys;
1918	uint32_t iChunk = 0;
1919	while (cPagesLeft > 0)
1920	{
1921	uint32_t cPagesInChunk = cPagesLeft;
1922	if (cPagesInChunk > cPagesPerChunk)
1923	cPagesInChunk = cPagesPerChunk;
1924
1925	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1926	AssertRCReturn(rc, rc);
1927
1928	/* advance */
1929	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1930	cPagesLeft -= cPagesInChunk;
1931	iChunk++;
1932	}
1933	}
1934	else
1935	{
1936	/*
1937	* Allocate, initialize and link the new RAM range.
1938	*/
1939	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
1940	PPGMRAMRANGE pNew;
1941	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1942	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1943
1944	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1945	}
1946	pgmPhysInvalidatePageMapTLB(pVM);
1947
1948	/*
1949	* Notify NEM while holding the lock (experimental) and REM without (like always).
1950	*/
1951	rc = NEMR3NotifyPhysRamRegister(pVM, GCPhys, cb);
1952	pgmUnlock(pVM);
1953	#ifdef VBOX_WITH_REM
1954	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1955	#endif
1956	return rc;
1957	}
1958
1959
1960	/**
1961	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1962	*
1963	* We do this late in the init process so that all the ROM and MMIO ranges have
1964	* been registered already and we don't go wasting memory on them.
1965	*
1966	* @returns VBox status code.
1967	*
1968	* @param pVM The cross context VM structure.
1969	*/
1970	int pgmR3PhysRamPreAllocate(PVM pVM)
1971	{
1972	Assert(pVM->pgm.s.fRamPreAlloc);
1973	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1974
1975	/*
1976	* Walk the RAM ranges and allocate all RAM pages, halt at
1977	* the first allocation error.
1978	*/
1979	uint64_t cPages = 0;
1980	uint64_t NanoTS = RTTimeNanoTS();
1981	pgmLock(pVM);
1982	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1983	{
1984	PPGMPAGE pPage = &pRam->aPages[0];
1985	RTGCPHYS GCPhys = pRam->GCPhys;
1986	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1987	while (cLeft-- > 0)
1988	{
1989	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1990	{
1991	switch (PGM_PAGE_GET_STATE(pPage))
1992	{
1993	case PGM_PAGE_STATE_ZERO:
1994	{
1995	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1996	if (RT_FAILURE(rc))
1997	{
1998	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1999	pgmUnlock(pVM);
2000	return rc;
2001	}
2002	cPages++;
2003	break;
2004	}
2005
2006	case PGM_PAGE_STATE_BALLOONED:
2007	case PGM_PAGE_STATE_ALLOCATED:
2008	case PGM_PAGE_STATE_WRITE_MONITORED:
2009	case PGM_PAGE_STATE_SHARED:
2010	/* nothing to do here. */
2011	break;
2012	}
2013	}
2014
2015	/* next */
2016	pPage++;
2017	GCPhys += PAGE_SIZE;
2018	}
2019	}
2020	pgmUnlock(pVM);
2021	NanoTS = RTTimeNanoTS() - NanoTS;
2022
2023	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
2024	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
2025	return VINF_SUCCESS;
2026	}
2027
2028
2029	/**
2030	* Checks shared page checksums.
2031	*
2032	* @param pVM The cross context VM structure.
2033	*/
2034	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
2035	{
2036	#ifdef VBOX_STRICT
2037	pgmLock(pVM);
2038
2039	if (pVM->pgm.s.cSharedPages > 0)
2040	{
2041	/*
2042	* Walk the ram ranges.
2043	*/
2044	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2045	{
2046	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2047	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2048
2049	while (iPage-- > 0)
2050	{
2051	PPGMPAGE pPage = &pRam->aPages[iPage];
2052	if (PGM_PAGE_IS_SHARED(pPage))
2053	{
2054	uint32_t u32Checksum = pPage->s.u2Unused0/* \| ((uint32_t)pPage->s.u2Unused1 << 8)*/;
2055	if (!u32Checksum)
2056	{
2057	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2058	void const *pvPage;
2059	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
2060	if (RT_SUCCESS(rc))
2061	{
2062	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
2063	# if 0
2064	AssertMsg((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
2065	# else
2066	if ((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum)
2067	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
2068	else
2069	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
2070	# endif
2071	}
2072	else
2073	AssertRC(rc);
2074	}
2075	}
2076
2077	} /* for each page */
2078
2079	} /* for each ram range */
2080	}
2081
2082	pgmUnlock(pVM);
2083	#endif /* VBOX_STRICT */
2084	NOREF(pVM);
2085	}
2086
2087
2088	/**
2089	* Resets the physical memory state.
2090	*
2091	* ASSUMES that the caller owns the PGM lock.
2092	*
2093	* @returns VBox status code.
2094	* @param pVM The cross context VM structure.
2095	*/
2096	int pgmR3PhysRamReset(PVM pVM)
2097	{
2098	PGM_LOCK_ASSERT_OWNER(pVM);
2099
2100	/* Reset the memory balloon. */
2101	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2102	AssertRC(rc);
2103
2104	#ifdef VBOX_WITH_PAGE_SHARING
2105	/* Clear all registered shared modules. */
2106	pgmR3PhysAssertSharedPageChecksums(pVM);
2107	rc = GMMR3ResetSharedModules(pVM);
2108	AssertRC(rc);
2109	#endif
2110	/* Reset counters. */
2111	pVM->pgm.s.cReusedSharedPages = 0;
2112	pVM->pgm.s.cBalloonedPages = 0;
2113
2114	return VINF_SUCCESS;
2115	}
2116
2117
2118	/**
2119	* Resets (zeros) the RAM after all devices and components have been reset.
2120	*
2121	* ASSUMES that the caller owns the PGM lock.
2122	*
2123	* @returns VBox status code.
2124	* @param pVM The cross context VM structure.
2125	*/
2126	int pgmR3PhysRamZeroAll(PVM pVM)
2127	{
2128	PGM_LOCK_ASSERT_OWNER(pVM);
2129
2130	/*
2131	* We batch up pages that should be freed instead of calling GMM for
2132	* each and every one of them.
2133	*/
2134	uint32_t cPendingPages = 0;
2135	PGMMFREEPAGESREQ pReq;
2136	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2137	AssertLogRelRCReturn(rc, rc);
2138
2139	/*
2140	* Walk the ram ranges.
2141	*/
2142	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2143	{
2144	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2145	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2146
2147	if ( !pVM->pgm.s.fRamPreAlloc
2148	&& pVM->pgm.s.fZeroRamPagesOnReset)
2149	{
2150	/* Replace all RAM pages by ZERO pages. */
2151	while (iPage-- > 0)
2152	{
2153	PPGMPAGE pPage = &pRam->aPages[iPage];
2154	switch (PGM_PAGE_GET_TYPE(pPage))
2155	{
2156	case PGMPAGETYPE_RAM:
2157	/* Do not replace pages part of a 2 MB continuous range
2158	with zero pages, but zero them instead. */
2159	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
2160	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2161	{
2162	void *pvPage;
2163	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2164	AssertLogRelRCReturn(rc, rc);
2165	ASMMemZeroPage(pvPage);
2166	}
2167	else if (PGM_PAGE_IS_BALLOONED(pPage))
2168	{
2169	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2170	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2171	}
2172	else if (!PGM_PAGE_IS_ZERO(pPage))
2173	{
2174	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2175	PGMPAGETYPE_RAM);
2176	AssertLogRelRCReturn(rc, rc);
2177	}
2178	break;
2179
2180	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2181	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2182	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2183	true /fDoAccounting/);
2184	break;
2185
2186	case PGMPAGETYPE_MMIO2:
2187	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2188	case PGMPAGETYPE_ROM:
2189	case PGMPAGETYPE_MMIO:
2190	break;
2191	default:
2192	AssertFailed();
2193	}
2194	} /* for each page */
2195	}
2196	else
2197	{
2198	/* Zero the memory. */
2199	while (iPage-- > 0)
2200	{
2201	PPGMPAGE pPage = &pRam->aPages[iPage];
2202	switch (PGM_PAGE_GET_TYPE(pPage))
2203	{
2204	case PGMPAGETYPE_RAM:
2205	switch (PGM_PAGE_GET_STATE(pPage))
2206	{
2207	case PGM_PAGE_STATE_ZERO:
2208	break;
2209
2210	case PGM_PAGE_STATE_BALLOONED:
2211	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2212	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2213	break;
2214
2215	case PGM_PAGE_STATE_SHARED:
2216	case PGM_PAGE_STATE_WRITE_MONITORED:
2217	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2218	AssertLogRelRCReturn(rc, rc);
2219	RT_FALL_THRU();
2220
2221	case PGM_PAGE_STATE_ALLOCATED:
2222	if (pVM->pgm.s.fZeroRamPagesOnReset)
2223	{
2224	void *pvPage;
2225	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2226	AssertLogRelRCReturn(rc, rc);
2227	ASMMemZeroPage(pvPage);
2228	}
2229	break;
2230	}
2231	break;
2232
2233	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2234	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2235	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2236	true /fDoAccounting/);
2237	break;
2238
2239	case PGMPAGETYPE_MMIO2:
2240	case PGMPAGETYPE_ROM_SHADOW:
2241	case PGMPAGETYPE_ROM:
2242	case PGMPAGETYPE_MMIO:
2243	break;
2244	default:
2245	AssertFailed();
2246
2247	}
2248	} /* for each page */
2249	}
2250
2251	}
2252
2253	/*
2254	* Finish off any pages pending freeing.
2255	*/
2256	if (cPendingPages)
2257	{
2258	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2259	AssertLogRelRCReturn(rc, rc);
2260	}
2261	GMMR3FreePagesCleanup(pReq);
2262	return VINF_SUCCESS;
2263	}
2264
2265
2266	/**
2267	* Frees all RAM during VM termination
2268	*
2269	* ASSUMES that the caller owns the PGM lock.
2270	*
2271	* @returns VBox status code.
2272	* @param pVM The cross context VM structure.
2273	*/
2274	int pgmR3PhysRamTerm(PVM pVM)
2275	{
2276	PGM_LOCK_ASSERT_OWNER(pVM);
2277
2278	/* Reset the memory balloon. */
2279	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2280	AssertRC(rc);
2281
2282	#ifdef VBOX_WITH_PAGE_SHARING
2283	/*
2284	* Clear all registered shared modules.
2285	*/
2286	pgmR3PhysAssertSharedPageChecksums(pVM);
2287	rc = GMMR3ResetSharedModules(pVM);
2288	AssertRC(rc);
2289
2290	/*
2291	* Flush the handy pages updates to make sure no shared pages are hiding
2292	* in there. (No unlikely if the VM shuts down, apparently.)
2293	*/
2294	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2295	#endif
2296
2297	/*
2298	* We batch up pages that should be freed instead of calling GMM for
2299	* each and every one of them.
2300	*/
2301	uint32_t cPendingPages = 0;
2302	PGMMFREEPAGESREQ pReq;
2303	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2304	AssertLogRelRCReturn(rc, rc);
2305
2306	/*
2307	* Walk the ram ranges.
2308	*/
2309	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2310	{
2311	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2312	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2313
2314	while (iPage-- > 0)
2315	{
2316	PPGMPAGE pPage = &pRam->aPages[iPage];
2317	switch (PGM_PAGE_GET_TYPE(pPage))
2318	{
2319	case PGMPAGETYPE_RAM:
2320	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2321	/** @todo change this to explicitly free private pages here. */
2322	if (PGM_PAGE_IS_SHARED(pPage))
2323	{
2324	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2325	PGMPAGETYPE_RAM);
2326	AssertLogRelRCReturn(rc, rc);
2327	}
2328	break;
2329
2330	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2331	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2332	case PGMPAGETYPE_MMIO2:
2333	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2334	case PGMPAGETYPE_ROM:
2335	case PGMPAGETYPE_MMIO:
2336	break;
2337	default:
2338	AssertFailed();
2339	}
2340	} /* for each page */
2341	}
2342
2343	/*
2344	* Finish off any pages pending freeing.
2345	*/
2346	if (cPendingPages)
2347	{
2348	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2349	AssertLogRelRCReturn(rc, rc);
2350	}
2351	GMMR3FreePagesCleanup(pReq);
2352	return VINF_SUCCESS;
2353	}
2354
2355
2356	/**
2357	* This is the interface IOM is using to register an MMIO region.
2358	*
2359	* It will check for conflicts and ensure that a RAM range structure
2360	* is present before calling the PGMR3HandlerPhysicalRegister API to
2361	* register the callbacks.
2362	*
2363	* @returns VBox status code.
2364	*
2365	* @param pVM The cross context VM structure.
2366	* @param GCPhys The start of the MMIO region.
2367	* @param cb The size of the MMIO region.
2368	* @param hType The physical access handler type registration.
2369	* @param pvUserR3 The user argument for R3.
2370	* @param pvUserR0 The user argument for R0.
2371	* @param pvUserRC The user argument for RC.
2372	* @param pszDesc The description of the MMIO region.
2373	*/
2374	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2375	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2376	{
2377	/*
2378	* Assert on some assumption.
2379	*/
2380	VM_ASSERT_EMT(pVM);
2381	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2382	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2383	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2384	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2385	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2386
2387	int rc = pgmLock(pVM);
2388	AssertRCReturn(rc, rc);
2389
2390	/*
2391	* Make sure there's a RAM range structure for the region.
2392	*/
2393	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2394	bool fRamExists = false;
2395	PPGMRAMRANGE pRamPrev = NULL;
2396	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2397	while (pRam && GCPhysLast >= pRam->GCPhys)
2398	{
2399	if ( GCPhysLast >= pRam->GCPhys
2400	&& GCPhys <= pRam->GCPhysLast)
2401	{
2402	/* Simplification: all within the same range. */
2403	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2404	&& GCPhysLast <= pRam->GCPhysLast,
2405	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2406	GCPhys, GCPhysLast, pszDesc,
2407	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2408	pgmUnlock(pVM),
2409	VERR_PGM_RAM_CONFLICT);
2410
2411	/* Check that it's all RAM or MMIO pages. */
2412	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2413	uint32_t cLeft = cb >> PAGE_SHIFT;
2414	while (cLeft-- > 0)
2415	{
2416	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2417	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2418	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2419	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2420	pgmUnlock(pVM),
2421	VERR_PGM_RAM_CONFLICT);
2422	pPage++;
2423	}
2424
2425	/* Looks good. */
2426	fRamExists = true;
2427	break;
2428	}
2429
2430	/* next */
2431	pRamPrev = pRam;
2432	pRam = pRam->pNextR3;
2433	}
2434	PPGMRAMRANGE pNew;
2435	if (fRamExists)
2436	{
2437	pNew = NULL;
2438
2439	/*
2440	* Make all the pages in the range MMIO/ZERO pages, freeing any
2441	* RAM pages currently mapped here. This might not be 100% correct
2442	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2443	*/
2444	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
2445	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
2446
2447	/* Force a PGM pool flush as guest ram references have been changed. */
2448	/** @todo not entirely SMP safe; assuming for now the guest takes
2449	* care of this internally (not touch mapped mmio while changing the
2450	* mapping). */
2451	PVMCPU pVCpu = VMMGetCpu(pVM);
2452	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2453	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2454	}
2455	else
2456	{
2457
2458	/*
2459	* No RAM range, insert an ad hoc one.
2460	*
2461	* Note that we don't have to tell REM about this range because
2462	* PGMHandlerPhysicalRegisterEx will do that for us.
2463	*/
2464	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2465
2466	const uint32_t cPages = cb >> PAGE_SHIFT;
2467	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
2468	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2469	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), pgmUnlock(pVM), rc);
2470
2471	/* Initialize the range. */
2472	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2473	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
2474	pNew->GCPhys = GCPhys;
2475	pNew->GCPhysLast = GCPhysLast;
2476	pNew->cb = cb;
2477	pNew->pszDesc = pszDesc;
2478	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2479	pNew->pvR3 = NULL;
2480	pNew->paLSPages = NULL;
2481
2482	uint32_t iPage = cPages;
2483	while (iPage-- > 0)
2484	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2485	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2486
2487	/* update the page count stats. */
2488	pVM->pgm.s.cPureMmioPages += cPages;
2489	pVM->pgm.s.cAllPages += cPages;
2490
2491	/* link it */
2492	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2493	}
2494
2495	/*
2496	* Register the access handler.
2497	*/
2498	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2499	if ( RT_FAILURE(rc)
2500	&& !fRamExists)
2501	{
2502	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2503	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2504
2505	/* remove the ad hoc range. */
2506	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2507	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2508	MMHyperFree(pVM, pRam);
2509	}
2510	pgmPhysInvalidatePageMapTLB(pVM);
2511
2512	pgmUnlock(pVM);
2513	return rc;
2514	}
2515
2516
2517	/**
2518	* This is the interface IOM is using to register an MMIO region.
2519	*
2520	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2521	* any ad hoc PGMRAMRANGE left behind.
2522	*
2523	* @returns VBox status code.
2524	* @param pVM The cross context VM structure.
2525	* @param GCPhys The start of the MMIO region.
2526	* @param cb The size of the MMIO region.
2527	*/
2528	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2529	{
2530	VM_ASSERT_EMT(pVM);
2531
2532	int rc = pgmLock(pVM);
2533	AssertRCReturn(rc, rc);
2534
2535	/*
2536	* First deregister the handler, then check if we should remove the ram range.
2537	*/
2538	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2539	if (RT_SUCCESS(rc))
2540	{
2541	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2542	PPGMRAMRANGE pRamPrev = NULL;
2543	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2544	while (pRam && GCPhysLast >= pRam->GCPhys)
2545	{
2546	/** @todo We're being a bit too careful here. rewrite. */
2547	if ( GCPhysLast == pRam->GCPhysLast
2548	&& GCPhys == pRam->GCPhys)
2549	{
2550	Assert(pRam->cb == cb);
2551
2552	/*
2553	* See if all the pages are dead MMIO pages.
2554	*/
2555	uint32_t const cPages = cb >> PAGE_SHIFT;
2556	bool fAllMMIO = true;
2557	uint32_t iPage = 0;
2558	uint32_t cLeft = cPages;
2559	while (cLeft-- > 0)
2560	{
2561	PPGMPAGE pPage = &pRam->aPages[iPage];
2562	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2563	/\|\| not-out-of-action later /)
2564	{
2565	fAllMMIO = false;
2566	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2567	break;
2568	}
2569	Assert( PGM_PAGE_IS_ZERO(pPage)
2570	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2571	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2572	pPage++;
2573	}
2574	if (fAllMMIO)
2575	{
2576	/*
2577	* Ad-hoc range, unlink and free it.
2578	*/
2579	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2580	GCPhys, GCPhysLast, pRam->pszDesc));
2581
2582	pVM->pgm.s.cAllPages -= cPages;
2583	pVM->pgm.s.cPureMmioPages -= cPages;
2584
2585	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2586	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2587	MMHyperFree(pVM, pRam);
2588	break;
2589	}
2590	}
2591
2592	/*
2593	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2594	*/
2595	if ( GCPhysLast >= pRam->GCPhys
2596	&& GCPhys <= pRam->GCPhysLast)
2597	{
2598	Assert(GCPhys >= pRam->GCPhys);
2599	Assert(GCPhysLast <= pRam->GCPhysLast);
2600
2601	/*
2602	* Turn the pages back into RAM pages.
2603	*/
2604	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2605	uint32_t cLeft = cb >> PAGE_SHIFT;
2606	while (cLeft--)
2607	{
2608	PPGMPAGE pPage = &pRam->aPages[iPage];
2609	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2610	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2611	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2612	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2613	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2614	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2615	}
2616	break;
2617	}
2618
2619	/* next */
2620	pRamPrev = pRam;
2621	pRam = pRam->pNextR3;
2622	}
2623	}
2624
2625	/* Force a PGM pool flush as guest ram references have been changed. */
2626	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2627	* this internally (not touch mapped mmio while changing the mapping). */
2628	PVMCPU pVCpu = VMMGetCpu(pVM);
2629	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2630	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2631
2632	pgmPhysInvalidatePageMapTLB(pVM);
2633	pgmPhysInvalidRamRangeTlbs(pVM);
2634	pgmUnlock(pVM);
2635	return rc;
2636	}
2637
2638
2639	/**
2640	* Locate a MMIO2 range.
2641	*
2642	* @returns Pointer to the MMIO2 range.
2643	* @param pVM The cross context VM structure.
2644	* @param pDevIns The device instance owning the region.
2645	* @param iSubDev The sub-device number.
2646	* @param iRegion The region.
2647	*/
2648	DECLINLINE(PPGMREGMMIORANGE) pgmR3PhysMMIOExFind(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion)
2649	{
2650	/*
2651	* Search the list. There shouldn't be many entries.
2652	*/
2653	/** @todo Optimize this lookup! There may now be many entries and it'll
2654	* become really slow when doing MMR3HyperMapMMIO2 and similar. */
2655	for (PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2656	if ( pCur->pDevInsR3 == pDevIns
2657	&& pCur->iRegion == iRegion
2658	&& pCur->iSubDev == iSubDev)
2659	return pCur;
2660	return NULL;
2661	}
2662
2663
2664	/**
2665	* @callback_method_impl{FNPGMRELOCATE, Relocate a floating MMIO/MMIO2 range.}
2666	* @sa pgmR3PhysRamRangeRelocate
2667	*/
2668	static DECLCALLBACK(bool) pgmR3PhysMMIOExRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
2669	PGMRELOCATECALL enmMode, void *pvUser)
2670	{
2671	PPGMREGMMIORANGE pMmio = (PPGMREGMMIORANGE)pvUser;
2672	Assert(pMmio->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
2673	Assert(pMmio->RamRange.pSelfRC == GCPtrOld + PAGE_SIZE + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange)); RT_NOREF_PV(GCPtrOld);
2674
2675	switch (enmMode)
2676	{
2677	case PGMRELOCATECALL_SUGGEST:
2678	return true;
2679
2680	case PGMRELOCATECALL_RELOCATE:
2681	{
2682	/*
2683	* Update myself, then relink all the ranges and flush the RC TLB.
2684	*/
2685	pgmLock(pVM);
2686
2687	pMmio->RamRange.pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange));
2688
2689	pgmR3PhysRelinkRamRanges(pVM);
2690	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2691	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2692
2693	pgmUnlock(pVM);
2694	return true;
2695	}
2696
2697	default:
2698	AssertFailedReturn(false);
2699	}
2700	}
2701
2702
2703	/**
2704	* Calculates the number of chunks
2705	*
2706	* @returns Number of registration chunk needed.
2707	* @param pVM The cross context VM structure.
2708	* @param cb The size of the MMIO/MMIO2 range.
2709	* @param pcPagesPerChunk Where to return the number of pages tracked by each
2710	* chunk. Optional.
2711	* @param pcbChunk Where to return the guest mapping size for a chunk.
2712	*/
2713	static uint16_t pgmR3PhysMMIOExCalcChunkCount(PVM pVM, RTGCPHYS cb, uint32_t pcPagesPerChunk, uint32_t pcbChunk)
2714	{
2715	RT_NOREF_PV(pVM); /* without raw mode */
2716
2717	/*
2718	* This is the same calculation as PGMR3PhysRegisterRam does, except we'll be
2719	* needing a few bytes extra the PGMREGMMIORANGE structure.
2720	*
2721	* Note! In additions, we've got a 24 bit sub-page range for MMIO2 ranges, leaving
2722	* us with an absolute maximum of 16777215 pages per chunk (close to 64 GB).
2723	*/
2724	uint32_t cbChunk;
2725	uint32_t cPagesPerChunk;
2726	if (!VM_IS_RAW_MODE_ENABLED(pVM))
2727	{
2728	cbChunk = 16U*_1M;
2729	cPagesPerChunk = 1048048; /* max ~1048059 */
2730	AssertCompile(sizeof(PGMREGMMIORANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
2731	}
2732	else
2733	{
2734	cbChunk = 4U*_1M;
2735	cPagesPerChunk = 261616; /* max ~261627 */
2736	AssertCompile(sizeof(PGMREGMMIORANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
2737	}
2738	AssertRelease(cPagesPerChunk <= PGM_MMIO2_MAX_PAGE_COUNT); /* See above note. */
2739	AssertRelease(RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
2740	if (pcbChunk)
2741	*pcbChunk = cbChunk;
2742	if (pcPagesPerChunk)
2743	*pcPagesPerChunk = cPagesPerChunk;
2744
2745	/* Calc the number of chunks we need. */
2746	RTGCPHYS const cPages = cb >> X86_PAGE_SHIFT;
2747	uint16_t cChunks = (uint16_t)((cPages + cPagesPerChunk - 1) / cPagesPerChunk);
2748	AssertRelease((RTGCPHYS)cChunks * cPagesPerChunk >= cPages);
2749	return cChunks;
2750	}
2751
2752
2753	/**
2754	* Worker for PGMR3PhysMMIOExPreRegister & PGMR3PhysMMIO2Register that allocates
2755	* and the PGMREGMMIORANGE structures and does basic initialization.
2756	*
2757	* Caller must set type specfic members and initialize the PGMPAGE structures.
2758	*
2759	* @returns VBox status code.
2760	* @param pVM The cross context VM structure.
2761	* @param pDevIns The device instance owning the region.
2762	* @param iSubDev The sub-device number (internal PCI config number).
2763	* @param iRegion The region number. If the MMIO2 memory is a PCI
2764	* I/O region this number has to be the number of that
2765	* region. Otherwise it can be any number safe
2766	* UINT8_MAX.
2767	* @param cb The size of the region. Must be page aligned.
2768	* @param pszDesc The description.
2769	* @param ppHeadRet Where to return the pointer to the first
2770	* registration chunk.
2771	*
2772	* @thread EMT
2773	*/
2774	static int pgmR3PhysMMIOExCreate(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2775	const char pszDesc, PPGMREGMMIORANGE ppHeadRet)
2776	{
2777	/*
2778	* Figure out how many chunks we need and of which size.
2779	*/
2780	uint32_t cPagesPerChunk;
2781	uint16_t cChunks = pgmR3PhysMMIOExCalcChunkCount(pVM, cb, &cPagesPerChunk, NULL);
2782	AssertReturn(cChunks, VERR_PGM_PHYS_MMIO_EX_IPE);
2783
2784	/*
2785	* Allocate the chunks.
2786	*/
2787	PPGMREGMMIORANGE *ppNext = ppHeadRet;
2788	*ppNext = NULL;
2789
2790	int rc = VINF_SUCCESS;
2791	uint32_t cPagesLeft = cb >> X86_PAGE_SHIFT;
2792	for (uint16_t iChunk = 0; iChunk < cChunks && RT_SUCCESS(rc); iChunk++)
2793	{
2794	/*
2795	* We currently do a single RAM range for the whole thing. This will
2796	* probably have to change once someone needs really large MMIO regions,
2797	* as we will be running into SUPR3PageAllocEx limitations and such.
2798	*/
2799	const uint32_t cPagesTrackedByChunk = RT_MIN(cPagesLeft, cPagesPerChunk);
2800	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPagesTrackedByChunk]);
2801	PPGMREGMMIORANGE pNew = NULL;
2802	if ( iChunk + 1 < cChunks
2803	\|\| cbRange >= _1M)
2804	{
2805	/*
2806	* Allocate memory for the registration structure.
2807	*/
2808	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2809	size_t const cbChunk = (1 + cChunkPages + 1) << PAGE_SHIFT;
2810	AssertLogRelBreakStmt(cbChunk == (uint32_t)cbChunk, rc = VERR_OUT_OF_RANGE);
2811	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
2812	AssertBreakStmt(paChunkPages, rc = VERR_NO_TMP_MEMORY);
2813	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
2814	void *pvChunk = NULL;
2815	rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
2816	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
2817	&R0PtrChunk,
2818	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
2819	VM_IS_HM_OR_NEM_ENABLED(pVM) ? &R0PtrChunk : NULL,
2820	#else
2821	NULL,
2822	#endif
2823	paChunkPages);
2824	AssertLogRelMsgRCBreakStmt(rc, ("rc=%Rrc, cChunkPages=%#zx\n", rc, cChunkPages), RTMemTmpFree(paChunkPages));
2825
2826	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
2827	Assert(R0PtrChunk != NIL_RTR0PTR);
2828	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
2829	if (!VM_IS_HM_OR_NEM_ENABLED(pVM))
2830	R0PtrChunk = NIL_RTR0PTR;
2831	#else
2832	R0PtrChunk = (uintptr_t)pvChunk;
2833	#endif
2834	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
2835
2836	pNew = (PPGMREGMMIORANGE)pvChunk;
2837	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_FLOATING;
2838	pNew->RamRange.pSelfR0 = R0PtrChunk + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange);
2839
2840	/*
2841	* If we might end up in raw-mode, make a HMA mapping of the range,
2842	* just like we do for memory above 4GB.
2843	*/
2844	if (!VM_IS_RAW_MODE_ENABLED(pVM))
2845	pNew->RamRange.pSelfRC = NIL_RTRCPTR;
2846	else
2847	{
2848	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - RT_ALIGN_Z(cbChunk, _4M);
2849	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
2850	rc = PGMR3MapPT(pVM, GCPtrChunkMap, (uint32_t)cbChunk, 0 /fFlags/, pgmR3PhysMMIOExRangeRelocate, pNew, pszDesc);
2851	if (RT_SUCCESS(rc))
2852	{
2853	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
2854
2855	RTGCPTR GCPtrPage = GCPtrChunk;
2856	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
2857	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
2858	}
2859	if (RT_FAILURE(rc))
2860	{
2861	SUPR3PageFreeEx(pvChunk, cChunkPages);
2862	RTMemTmpFree(paChunkPages);
2863	break;
2864	}
2865	pNew->RamRange.pSelfRC = GCPtrChunk + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange);
2866	}
2867	RTMemTmpFree(paChunkPages);
2868	}
2869	/*
2870	* Not so big, do a one time hyper allocation.
2871	*/
2872	else
2873	{
2874	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2875	AssertLogRelMsgRCBreak(rc, ("cbRange=%zu\n", cbRange));
2876
2877	/*
2878	* Initialize allocation specific items.
2879	*/
2880	//pNew->RamRange.fFlags = 0;
2881	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2882	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
2883	}
2884
2885	/*
2886	* Initialize the registration structure (caller does specific bits).
2887	*/
2888	pNew->pDevInsR3 = pDevIns;
2889	//pNew->pvR3 = NULL;
2890	//pNew->pNext = NULL;
2891	//pNew->fFlags = 0;
2892	if (iChunk == 0)
2893	pNew->fFlags \|= PGMREGMMIORANGE_F_FIRST_CHUNK;
2894	if (iChunk + 1 == cChunks)
2895	pNew->fFlags \|= PGMREGMMIORANGE_F_LAST_CHUNK;
2896	pNew->iSubDev = iSubDev;
2897	pNew->iRegion = iRegion;
2898	pNew->idSavedState = UINT8_MAX;
2899	pNew->idMmio2 = UINT8_MAX;
2900	//pNew->pPhysHandlerR3 = NULL;
2901	//pNew->paLSPages = NULL;
2902	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2903	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2904	pNew->RamRange.pszDesc = pszDesc;
2905	pNew->RamRange.cb = pNew->cbReal = (RTGCPHYS)cPagesTrackedByChunk << X86_PAGE_SHIFT;
2906	pNew->RamRange.fFlags \|= PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX;
2907	//pNew->RamRange.pvR3 = NULL;
2908	//pNew->RamRange.paLSPages = NULL;
2909
2910	*ppNext = pNew;
2911	ASMCompilerBarrier();
2912	cPagesLeft -= cPagesTrackedByChunk;
2913	ppNext = &pNew->pNextR3;
2914	}
2915	Assert(cPagesLeft == 0);
2916
2917	if (RT_SUCCESS(rc))
2918	{
2919	Assert((*ppHeadRet)->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
2920	return VINF_SUCCESS;
2921	}
2922
2923	/*
2924	* Free floating ranges.
2925	*/
2926	while (*ppHeadRet)
2927	{
2928	PPGMREGMMIORANGE pFree = *ppHeadRet;
2929	*ppHeadRet = pFree->pNextR3;
2930
2931	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
2932	{
2933	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
2934	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2935	SUPR3PageFreeEx(pFree, cChunkPages);
2936	}
2937	}
2938
2939	return rc;
2940	}
2941
2942
2943	/**
2944	* Common worker PGMR3PhysMMIOExPreRegister & PGMR3PhysMMIO2Register that links
2945	* a complete registration entry into the lists and lookup tables.
2946	*
2947	* @param pVM The cross context VM structure.
2948	* @param pNew The new MMIO / MMIO2 registration to link.
2949	*/
2950	static void pgmR3PhysMMIOExLink(PVM pVM, PPGMREGMMIORANGE pNew)
2951	{
2952	/*
2953	* Link it into the list (order doesn't matter, so insert it at the head).
2954	*
2955	* Note! The range we're link may consist of multiple chunks, so we have to
2956	* find the last one.
2957	*/
2958	PPGMREGMMIORANGE pLast = pNew;
2959	for (pLast = pNew; ; pLast = pLast->pNextR3)
2960	{
2961	if (pLast->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
2962	break;
2963	Assert(pLast->pNextR3);
2964	Assert(pLast->pNextR3->pDevInsR3 == pNew->pDevInsR3);
2965	Assert(pLast->pNextR3->iSubDev == pNew->iSubDev);
2966	Assert(pLast->pNextR3->iRegion == pNew->iRegion);
2967	Assert((pLast->pNextR3->fFlags & PGMREGMMIORANGE_F_MMIO2) == (pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
2968	Assert(pLast->pNextR3->idMmio2 == (pLast->fFlags & PGMREGMMIORANGE_F_MMIO2 ? pNew->idMmio2 + 1 : UINT8_MAX));
2969	}
2970
2971	pgmLock(pVM);
2972
2973	/* Link in the chain of ranges at the head of the list. */
2974	pLast->pNextR3 = pVM->pgm.s.pRegMmioRangesR3;
2975	pVM->pgm.s.pRegMmioRangesR3 = pNew;
2976
2977	/* If MMIO, insert the MMIO2 range/page IDs. */
2978	uint8_t idMmio2 = pNew->idMmio2;
2979	if (idMmio2 != UINT8_MAX)
2980	{
2981	for (;;)
2982	{
2983	Assert(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2);
2984	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
2985	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
2986	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
2987	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = pNew->RamRange.pSelfR0 - RT_UOFFSETOF(PGMREGMMIORANGE, RamRange);
2988	if (pNew->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
2989	break;
2990	pNew = pNew->pNextR3;
2991	}
2992	}
2993	else
2994	Assert(!(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
2995
2996	pgmPhysInvalidatePageMapTLB(pVM);
2997	pgmUnlock(pVM);
2998	}
2999
3000
3001	/**
3002	* Allocate and pre-register an MMIO region.
3003	*
3004	* This is currently the way to deal with large MMIO regions. It may in the
3005	* future be extended to be the way we deal with all MMIO regions, but that
3006	* means we'll have to do something about the simple list based approach we take
3007	* to tracking the registrations.
3008	*
3009	* @returns VBox status code.
3010	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
3011	* memory.
3012	* @retval VERR_ALREADY_EXISTS if the region already exists.
3013	*
3014	* @param pVM The cross context VM structure.
3015	* @param pDevIns The device instance owning the region.
3016	* @param iSubDev The sub-device number.
3017	* @param iRegion The region number. If the MMIO2 memory is a PCI
3018	* I/O region this number has to be the number of that
3019	* region. Otherwise it can be any number safe
3020	* UINT8_MAX.
3021	* @param cbRegion The size of the region. Must be page aligned.
3022	* @param hType The physical handler callback type.
3023	* @param pvUserR3 User parameter for ring-3 context callbacks.
3024	* @param pvUserR0 User parameter for ring-0 context callbacks.
3025	* @param pvUserRC User parameter for raw-mode context callbacks.
3026	* @param pszDesc The description.
3027	*
3028	* @thread EMT
3029	*
3030	* @sa PGMR3PhysMMIORegister, PGMR3PhysMMIO2Register,
3031	* PGMR3PhysMMIOExMap, PGMR3PhysMMIOExUnmap, PGMR3PhysMMIOExDeregister.
3032	*/
3033	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion,
3034	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
3035	const char *pszDesc)
3036	{
3037	/*
3038	* Validate input.
3039	*/
3040	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3041	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3042	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3043	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3044	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3045	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3046	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion) == NULL, VERR_ALREADY_EXISTS);
3047	AssertReturn(!(cbRegion & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3048	AssertReturn(cbRegion, VERR_INVALID_PARAMETER);
3049
3050	const uint32_t cPages = cbRegion >> PAGE_SHIFT;
3051	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cbRegion, VERR_INVALID_PARAMETER);
3052	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3053
3054	/*
3055	* For the 2nd+ instance, mangle the description string so it's unique.
3056	*/
3057	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3058	{
3059	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3060	if (!pszDesc)
3061	return VERR_NO_MEMORY;
3062	}
3063
3064	/*
3065	* Register the MMIO callbacks.
3066	*/
3067	PPGMPHYSHANDLER pPhysHandler;
3068	int rc = pgmHandlerPhysicalExCreate(pVM, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc, &pPhysHandler);
3069	if (RT_SUCCESS(rc))
3070	{
3071	/*
3072	* Create the registered MMIO range record for it.
3073	*/
3074	PPGMREGMMIORANGE pNew;
3075	rc = pgmR3PhysMMIOExCreate(pVM, pDevIns, iSubDev, iRegion, cbRegion, pszDesc, &pNew);
3076	if (RT_SUCCESS(rc))
3077	{
3078	Assert(!(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
3079
3080	/*
3081	* Intialize the page structures and set up physical handlers (one for each chunk).
3082	*/
3083	for (PPGMREGMMIORANGE pCur = pNew; pCur != NULL && RT_SUCCESS(rc); pCur = pCur->pNextR3)
3084	{
3085	if (pCur == pNew)
3086	pCur->pPhysHandlerR3 = pPhysHandler;
3087	else
3088	rc = pgmHandlerPhysicalExDup(pVM, pPhysHandler, &pCur->pPhysHandlerR3);
3089
3090	uint32_t iPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3091	while (iPage-- > 0)
3092	PGM_PAGE_INIT_ZERO(&pCur->RamRange.aPages[iPage], pVM, PGMPAGETYPE_MMIO);
3093	}
3094	if (RT_SUCCESS(rc))
3095	{
3096	/*
3097	* Update the page count stats, link the registration and we're done.
3098	*/
3099	pVM->pgm.s.cAllPages += cPages;
3100	pVM->pgm.s.cPureMmioPages += cPages;
3101
3102	pgmR3PhysMMIOExLink(pVM, pNew);
3103	return VINF_SUCCESS;
3104	}
3105
3106	/*
3107	* Clean up in case we're out of memory for extra access handlers.
3108	*/
3109	while (pNew != NULL)
3110	{
3111	PPGMREGMMIORANGE pFree = pNew;
3112	pNew = pFree->pNextR3;
3113
3114	if (pFree->pPhysHandlerR3)
3115	{
3116	pgmHandlerPhysicalExDestroy(pVM, pFree->pPhysHandlerR3);
3117	pFree->pPhysHandlerR3 = NULL;
3118	}
3119
3120	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3121	{
3122	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
3123	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3124	SUPR3PageFreeEx(pFree, cChunkPages);
3125	}
3126	}
3127	}
3128	else
3129	pgmHandlerPhysicalExDestroy(pVM, pPhysHandler);
3130	}
3131	return rc;
3132	}
3133
3134
3135	/**
3136	* Allocate and register an MMIO2 region.
3137	*
3138	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
3139	* associated with a device. It is also non-shared memory with a permanent
3140	* ring-3 mapping and page backing (presently).
3141	*
3142	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
3143	* the VM, in which case we'll drop the base memory pages. Presently we will
3144	* make no attempt to preserve anything that happens to be present in the base
3145	* memory that is replaced, this is of course incorrect but it's too much
3146	* effort.
3147	*
3148	* @returns VBox status code.
3149	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
3150	* memory.
3151	* @retval VERR_ALREADY_EXISTS if the region already exists.
3152	*
3153	* @param pVM The cross context VM structure.
3154	* @param pDevIns The device instance owning the region.
3155	* @param iSubDev The sub-device number.
3156	* @param iRegion The region number. If the MMIO2 memory is a PCI
3157	* I/O region this number has to be the number of that
3158	* region. Otherwise it can be any number safe
3159	* UINT8_MAX.
3160	* @param cb The size of the region. Must be page aligned.
3161	* @param fFlags Reserved for future use, must be zero.
3162	* @param ppv Where to store the pointer to the ring-3 mapping of
3163	* the memory.
3164	* @param pszDesc The description.
3165	* @thread EMT
3166	*/
3167	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
3168	uint32_t fFlags, void *ppv, const char pszDesc)
3169	{
3170	/*
3171	* Validate input.
3172	*/
3173	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3174	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3175	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3176	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3177	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
3178	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3179	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3180	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion) == NULL, VERR_ALREADY_EXISTS);
3181	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3182	AssertReturn(cb, VERR_INVALID_PARAMETER);
3183	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
3184
3185	const uint32_t cPages = cb >> PAGE_SHIFT;
3186	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
3187	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3188
3189	/*
3190	* For the 2nd+ instance, mangle the description string so it's unique.
3191	*/
3192	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3193	{
3194	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3195	if (!pszDesc)
3196	return VERR_NO_MEMORY;
3197	}
3198
3199	/*
3200	* Allocate an MMIO2 range ID (not freed on failure).
3201	*
3202	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID, so
3203	* the IDs goes from 1 thru PGM_MMIO2_MAX_RANGES.
3204	*/
3205	unsigned cChunks = pgmR3PhysMMIOExCalcChunkCount(pVM, cb, NULL, NULL);
3206	pgmLock(pVM);
3207	uint8_t idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
3208	unsigned cNewMmio2Regions = pVM->pgm.s.cMmio2Regions + cChunks;
3209	if (cNewMmio2Regions > PGM_MMIO2_MAX_RANGES)
3210	{
3211	pgmUnlock(pVM);
3212	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
3213	}
3214	pVM->pgm.s.cMmio2Regions = cNewMmio2Regions;
3215	pgmUnlock(pVM);
3216
3217	/*
3218	* Try reserve and allocate the backing memory first as this is what is
3219	* most likely to fail.
3220	*/
3221	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
3222	if (RT_SUCCESS(rc))
3223	{
3224	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
3225	if (RT_SUCCESS(rc))
3226	{
3227	void *pvPages;
3228	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
3229	if (RT_SUCCESS(rc))
3230	{
3231	memset(pvPages, 0, cPages * PAGE_SIZE);
3232
3233	/*
3234	* Create the registered MMIO range record for it.
3235	*/
3236	PPGMREGMMIORANGE pNew;
3237	rc = pgmR3PhysMMIOExCreate(pVM, pDevIns, iSubDev, iRegion, cb, pszDesc, &pNew);
3238	if (RT_SUCCESS(rc))
3239	{
3240	uint32_t iSrcPage = 0;
3241	uint8_t pbCurPages = (uint8_t )pvPages;
3242	for (PPGMREGMMIORANGE pCur = pNew; pCur; pCur = pCur->pNextR3)
3243	{
3244	pCur->pvR3 = pbCurPages;
3245	pCur->RamRange.pvR3 = pbCurPages;
3246	pCur->idMmio2 = idMmio2;
3247	pCur->fFlags \|= PGMREGMMIORANGE_F_MMIO2;
3248
3249	uint32_t iDstPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3250	while (iDstPage-- > 0)
3251	{
3252	PGM_PAGE_INIT(&pNew->RamRange.aPages[iDstPage],
3253	paPages[iDstPage + iSrcPage].Phys,
3254	PGM_MMIO2_PAGEID_MAKE(idMmio2, iDstPage),
3255	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
3256	}
3257
3258	/* advance. */
3259	iSrcPage += pCur->RamRange.cb >> X86_PAGE_SHIFT;
3260	pbCurPages += pCur->RamRange.cb;
3261	idMmio2++;
3262	}
3263
3264	RTMemTmpFree(paPages);
3265
3266	/*
3267	* Update the page count stats, link the registration and we're done.
3268	*/
3269	pVM->pgm.s.cAllPages += cPages;
3270	pVM->pgm.s.cPrivatePages += cPages;
3271
3272	pgmR3PhysMMIOExLink(pVM, pNew);
3273
3274	*ppv = pvPages;
3275	return VINF_SUCCESS;
3276	}
3277
3278	SUPR3PageFreeEx(pvPages, cPages);
3279	}
3280	}
3281	RTMemTmpFree(paPages);
3282	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
3283	}
3284	if (pDevIns->iInstance > 0)
3285	MMR3HeapFree((void *)pszDesc);
3286	return rc;
3287	}
3288
3289
3290	/**
3291	* Deregisters and frees an MMIO2 region or a pre-registered MMIO region
3292	*
3293	* Any physical (and virtual) access handlers registered for the region must
3294	* be deregistered before calling this function.
3295	*
3296	* @returns VBox status code.
3297	* @param pVM The cross context VM structure.
3298	* @param pDevIns The device instance owning the region.
3299	* @param iSubDev The sub-device number. Pass UINT32_MAX for wildcard
3300	* matching.
3301	* @param iRegion The region. Pass UINT32_MAX for wildcard matching.
3302	*/
3303	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion)
3304	{
3305	/*
3306	* Validate input.
3307	*/
3308	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3309	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3310	AssertReturn(iSubDev <= UINT8_MAX \|\| iSubDev == UINT32_MAX, VERR_INVALID_PARAMETER);
3311	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
3312
3313	/*
3314	* The loop here scanning all registrations will make sure that multi-chunk ranges
3315	* get properly deregistered, though it's original purpose was the wildcard iRegion.
3316	*/
3317	pgmLock(pVM);
3318	int rc = VINF_SUCCESS;
3319	unsigned cFound = 0;
3320	PPGMREGMMIORANGE pPrev = NULL;
3321	PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3;
3322	while (pCur)
3323	{
3324	if ( pCur->pDevInsR3 == pDevIns
3325	&& ( iRegion == UINT32_MAX
3326	\|\| pCur->iRegion == iRegion)
3327	&& ( iSubDev == UINT32_MAX
3328	\|\| pCur->iSubDev == iSubDev) )
3329	{
3330	cFound++;
3331
3332	/*
3333	* Unmap it if it's mapped.
3334	*/
3335	if (pCur->fFlags & PGMREGMMIORANGE_F_MAPPED)
3336	{
3337	int rc2 = PGMR3PhysMMIOExUnmap(pVM, pCur->pDevInsR3, pCur->iSubDev, pCur->iRegion, pCur->RamRange.GCPhys);
3338	AssertRC(rc2);
3339	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3340	rc = rc2;
3341	}
3342
3343	/*
3344	* Must tell IOM about MMIO (first one only).
3345	*/
3346	if ((pCur->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK)) == PGMREGMMIORANGE_F_MMIO2)
3347	IOMR3MmioExNotifyDeregistered(pVM, pCur->pPhysHandlerR3->pvUserR3);
3348
3349	/*
3350	* Unlink it
3351	*/
3352	PPGMREGMMIORANGE pNext = pCur->pNextR3;
3353	if (pPrev)
3354	pPrev->pNextR3 = pNext;
3355	else
3356	pVM->pgm.s.pRegMmioRangesR3 = pNext;
3357	pCur->pNextR3 = NULL;
3358
3359	uint8_t idMmio2 = pCur->idMmio2;
3360	if (idMmio2 != UINT8_MAX)
3361	{
3362	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
3363	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
3364	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
3365	}
3366
3367	/*
3368	* Free the memory.
3369	*/
3370	uint32_t const cPages = pCur->cbReal >> PAGE_SHIFT;
3371	if (pCur->fFlags & PGMREGMMIORANGE_F_MMIO2)
3372	{
3373	int rc2 = SUPR3PageFreeEx(pCur->pvR3, cPages);
3374	AssertRC(rc2);
3375	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3376	rc = rc2;
3377
3378	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
3379	AssertRC(rc2);
3380	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3381	rc = rc2;
3382	}
3383
3384	/* we're leaking hyper memory here if done at runtime. */
3385	#ifdef VBOX_STRICT
3386	VMSTATE const enmState = VMR3GetState(pVM);
3387	AssertMsg( enmState == VMSTATE_POWERING_OFF
3388	\|\| enmState == VMSTATE_POWERING_OFF_LS
3389	\|\| enmState == VMSTATE_OFF
3390	\|\| enmState == VMSTATE_OFF_LS
3391	\|\| enmState == VMSTATE_DESTROYING
3392	\|\| enmState == VMSTATE_TERMINATED
3393	\|\| enmState == VMSTATE_CREATING
3394	, ("%s\n", VMR3GetStateName(enmState)));
3395	#endif
3396
3397	const bool fIsMmio2 = RT_BOOL(pCur->fFlags & PGMREGMMIORANGE_F_MMIO2);
3398	if (pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3399	{
3400	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPages]);
3401	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3402	SUPR3PageFreeEx(pCur, cChunkPages);
3403	}
3404	/*else
3405	{
3406	rc = MMHyperFree(pVM, pCur); - does not work, see the alloc call.
3407	AssertRCReturn(rc, rc);
3408	} */
3409
3410
3411	/* update page count stats */
3412	pVM->pgm.s.cAllPages -= cPages;
3413	if (fIsMmio2)
3414	pVM->pgm.s.cPrivatePages -= cPages;
3415	else
3416	pVM->pgm.s.cPureMmioPages -= cPages;
3417
3418	/* next */
3419	pCur = pNext;
3420	}
3421	else
3422	{
3423	pPrev = pCur;
3424	pCur = pCur->pNextR3;
3425	}
3426	}
3427	pgmPhysInvalidatePageMapTLB(pVM);
3428	pgmUnlock(pVM);
3429	return !cFound && iRegion != UINT32_MAX && iSubDev != UINT32_MAX ? VERR_NOT_FOUND : rc;
3430	}
3431
3432
3433	/**
3434	* Maps a MMIO2 region or a pre-registered MMIO region.
3435	*
3436	* This is done when a guest / the bios / state loading changes the
3437	* PCI config. The replacing of base memory has the same restrictions
3438	* as during registration, of course.
3439	*
3440	* @returns VBox status code.
3441	*
3442	* @param pVM The cross context VM structure.
3443	* @param pDevIns The device instance owning the region.
3444	* @param iSubDev The sub-device number of the registered region.
3445	* @param iRegion The index of the registered region.
3446	* @param GCPhys The guest-physical address to be remapped.
3447	*/
3448	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys)
3449	{
3450	/*
3451	* Validate input.
3452	*
3453	* Note! It's safe to walk the MMIO/MMIO2 list since registrations only
3454	* happens during VM construction.
3455	*/
3456	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3457	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3458	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3459	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3460	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3461	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3462	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3463
3464	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3465	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3466	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3467
3468	PPGMREGMMIORANGE pLastMmio = pFirstMmio;
3469	RTGCPHYS cbRange = 0;
3470	for (;;)
3471	{
3472	AssertReturn(!(pLastMmio->fFlags & PGMREGMMIORANGE_F_MAPPED), VERR_WRONG_ORDER);
3473	Assert(pLastMmio->RamRange.GCPhys == NIL_RTGCPHYS);
3474	Assert(pLastMmio->RamRange.GCPhysLast == NIL_RTGCPHYS);
3475	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3476	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3477	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3478	cbRange += pLastMmio->RamRange.cb;
3479	if (pLastMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3480	break;
3481	pLastMmio = pLastMmio->pNextR3;
3482	}
3483
3484	RTGCPHYS GCPhysLast = GCPhys + cbRange - 1;
3485	AssertLogRelReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3486
3487	/*
3488	* Find our location in the ram range list, checking for restriction
3489	* we don't bother implementing yet (partially overlapping, multiple
3490	* ram ranges).
3491	*/
3492	pgmLock(pVM);
3493
3494	AssertReturnStmt(!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED), pgmUnlock(pVM), VERR_WRONG_ORDER);
3495
3496	bool fRamExists = false;
3497	PPGMRAMRANGE pRamPrev = NULL;
3498	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3499	while (pRam && GCPhysLast >= pRam->GCPhys)
3500	{
3501	if ( GCPhys <= pRam->GCPhysLast
3502	&& GCPhysLast >= pRam->GCPhys)
3503	{
3504	/* Completely within? */
3505	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
3506	&& GCPhysLast <= pRam->GCPhysLast,
3507	("%RGp-%RGp (MMIOEx/%s) falls partly outside %RGp-%RGp (%s)\n",
3508	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc,
3509	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3510	pgmUnlock(pVM),
3511	VERR_PGM_RAM_CONFLICT);
3512
3513	/* Check that all the pages are RAM pages. */
3514	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3515	uint32_t cPagesLeft = cbRange >> PAGE_SHIFT;
3516	while (cPagesLeft-- > 0)
3517	{
3518	AssertLogRelMsgReturnStmt(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3519	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
3520	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc),
3521	pgmUnlock(pVM),
3522	VERR_PGM_RAM_CONFLICT);
3523	pPage++;
3524	}
3525
3526	/* There can only be one MMIO/MMIO2 chunk matching here! */
3527	AssertLogRelMsgReturnStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK,
3528	("%RGp-%RGp (MMIOEx/%s, flags %#X) consists of multiple chunks whereas the RAM somehow doesn't!\n",
3529	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3530	pgmUnlock(pVM),
3531	VERR_PGM_PHYS_MMIO_EX_IPE);
3532
3533	fRamExists = true;
3534	break;
3535	}
3536
3537	/* next */
3538	pRamPrev = pRam;
3539	pRam = pRam->pNextR3;
3540	}
3541	Log(("PGMR3PhysMMIOExMap: %RGp-%RGp fRamExists=%RTbool %s\n", GCPhys, GCPhysLast, fRamExists, pFirstMmio->RamRange.pszDesc));
3542
3543
3544	/*
3545	* Make the changes.
3546	*/
3547	RTGCPHYS GCPhysCur = GCPhys;
3548	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3549	{
3550	pCurMmio->RamRange.GCPhys = GCPhysCur;
3551	pCurMmio->RamRange.GCPhysLast = GCPhysCur + pCurMmio->RamRange.cb - 1;
3552	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3553	{
3554	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3555	break;
3556	}
3557	GCPhysCur += pCurMmio->RamRange.cb;
3558	}
3559
3560	if (fRamExists)
3561	{
3562	/*
3563	* Make all the pages in the range MMIO/ZERO pages, freeing any
3564	* RAM pages currently mapped here. This might not be 100% correct
3565	* for PCI memory, but we're doing the same thing for MMIO2 pages.
3566	*
3567	* We replace this MMIO/ZERO pages with real pages in the MMIO2 case.
3568	*/
3569	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK); /* Only one chunk */
3570
3571	int rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
3572	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
3573
3574	if (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2)
3575	{
3576	/* replace the pages, freeing all present RAM pages. */
3577	PPGMPAGE pPageSrc = &pFirstMmio->RamRange.aPages[0];
3578	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3579	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3580	while (cPagesLeft-- > 0)
3581	{
3582	Assert(PGM_PAGE_IS_MMIO(pPageDst));
3583
3584	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
3585	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
3586	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
3587	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
3588	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
3589	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
3590	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
3591	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
3592	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
3593	/* (We tell NEM at the end of the function.) */
3594
3595	pVM->pgm.s.cZeroPages--;
3596	GCPhys += PAGE_SIZE;
3597	pPageSrc++;
3598	pPageDst++;
3599	}
3600	}
3601
3602	/* Flush physical page map TLB. */
3603	pgmPhysInvalidatePageMapTLB(pVM);
3604
3605	/* Force a PGM pool flush as guest ram references have been changed. */
3606	/** @todo not entirely SMP safe; assuming for now the guest takes care of
3607	* this internally (not touch mapped mmio while changing the mapping). */
3608	PVMCPU pVCpu = VMMGetCpu(pVM);
3609	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3610	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3611	}
3612	else
3613	{
3614	/*
3615	* No RAM range, insert the ones prepared during registration.
3616	*/
3617	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3618	{
3619	/* Clear the tracking data of pages we're going to reactivate. */
3620	PPGMPAGE pPageSrc = &pCurMmio->RamRange.aPages[0];
3621	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3622	while (cPagesLeft-- > 0)
3623	{
3624	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
3625	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
3626	pPageSrc++;
3627	}
3628
3629	/* link in the ram range */
3630	pgmR3PhysLinkRamRange(pVM, &pCurMmio->RamRange, pRamPrev);
3631
3632	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3633	{
3634	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3635	break;
3636	}
3637	pRamPrev = &pCurMmio->RamRange;
3638	}
3639	}
3640
3641	/*
3642	* Register the access handler if plain MMIO.
3643	*
3644	* We must register access handlers for each range since the access handler
3645	* code refuses to deal with multiple ranges (and we can).
3646	*/
3647	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2))
3648	{
3649	int rc = VINF_SUCCESS;
3650	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3651	{
3652	Assert(!(pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED));
3653	rc = pgmHandlerPhysicalExRegister(pVM, pCurMmio->pPhysHandlerR3, pCurMmio->RamRange.GCPhys,
3654	pCurMmio->RamRange.GCPhysLast);
3655	if (RT_FAILURE(rc))
3656	break;
3657	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_MAPPED; /* Use this to mark that the handler is registered. */
3658	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3659	{
3660	rc = IOMR3MmioExNotifyMapped(pVM, pFirstMmio->pPhysHandlerR3->pvUserR3, GCPhys);
3661	break;
3662	}
3663	}
3664	if (RT_FAILURE(rc))
3665	{
3666	/* Almost impossible, but try clean up properly and get out of here. */
3667	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3668	{
3669	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED)
3670	{
3671	pCurMmio->fFlags &= ~PGMREGMMIORANGE_F_MAPPED;
3672	pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3, fRamExists);
3673	}
3674
3675	if (!fRamExists)
3676	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3677	else
3678	{
3679	Assert(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK); /* Only one chunk */
3680
3681	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3682	PPGMPAGE pPageDst = &pRam->aPages[(pCurMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3683	while (cPagesLeft-- > 0)
3684	{
3685	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3686	pPageDst++;
3687	}
3688	}
3689
3690	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3691	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3692	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3693	break;
3694	}
3695
3696	pgmUnlock(pVM);
3697	return rc;
3698	}
3699	}
3700
3701	/*
3702	* We're good, set the flags and invalid the mapping TLB.
3703	*/
3704	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3705	{
3706	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_MAPPED;
3707	if (fRamExists)
3708	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_OVERLAPPING;
3709	else
3710	pCurMmio->fFlags &= ~PGMREGMMIORANGE_F_OVERLAPPING;
3711	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3712	break;
3713	}
3714	pgmPhysInvalidatePageMapTLB(pVM);
3715
3716	/*
3717	* Notify NEM while holding the lock (experimental) and REM without (like always).
3718	*/
3719	uint32_t const fNemNotify = (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0)
3720	\| (pFirstMmio->fFlags & PGMREGMMIORANGE_F_OVERLAPPING ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
3721	int rc = NEMR3NotifyPhysMmioExMap(pVM, GCPhys, cbRange, fNemNotify, pFirstMmio->pvR3);
3722
3723	pgmUnlock(pVM);
3724
3725	#ifdef VBOX_WITH_REM
3726	if (!fRamExists && (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2)) /** @todo this doesn't look right. */
3727	REMR3NotifyPhysRamRegister(pVM, GCPhys, cbRange, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
3728	#endif
3729	return rc;
3730	}
3731
3732
3733	/**
3734	* Unmaps a MMIO2 or a pre-registered MMIO region.
3735	*
3736	* This is done when a guest / the bios / state loading changes the
3737	* PCI config. The replacing of base memory has the same restrictions
3738	* as during registration, of course.
3739	*/
3740	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys)
3741	{
3742	/*
3743	* Validate input
3744	*/
3745	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3746	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3747	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3748	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3749	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3750	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3751	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3752
3753	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3754	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3755	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3756
3757	PPGMREGMMIORANGE pLastMmio = pFirstMmio;
3758	RTGCPHYS cbRange = 0;
3759	for (;;)
3760	{
3761	AssertReturn(pLastMmio->fFlags & PGMREGMMIORANGE_F_MAPPED, VERR_WRONG_ORDER);
3762	AssertReturn(pLastMmio->RamRange.GCPhys == GCPhys + cbRange, VERR_INVALID_PARAMETER);
3763	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3764	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3765	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3766	cbRange += pLastMmio->RamRange.cb;
3767	if (pLastMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3768	break;
3769	pLastMmio = pLastMmio->pNextR3;
3770	}
3771
3772	Log(("PGMR3PhysMMIOExUnmap: %RGp-%RGp %s\n",
3773	pFirstMmio->RamRange.GCPhys, pLastMmio->RamRange.GCPhysLast, pFirstMmio->RamRange.pszDesc));
3774
3775	int rc = pgmLock(pVM);
3776	AssertRCReturn(rc, rc);
3777	uint16_t const fOldFlags = pFirstMmio->fFlags;
3778	AssertReturnStmt(fOldFlags & PGMREGMMIORANGE_F_MAPPED, pgmUnlock(pVM), VERR_WRONG_ORDER);
3779
3780	/*
3781	* If plain MMIO, we must deregister the handlers first.
3782	*/
3783	if (!(fOldFlags & PGMREGMMIORANGE_F_MMIO2))
3784	{
3785	PPGMREGMMIORANGE pCurMmio = pFirstMmio;
3786	rc = pgmHandlerPhysicalExDeregister(pVM, pFirstMmio->pPhysHandlerR3, RT_BOOL(fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING));
3787	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
3788	while (!(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK))
3789	{
3790	pCurMmio = pCurMmio->pNextR3;
3791	rc = pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3, RT_BOOL(fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING));
3792	AssertRCReturnStmt(rc, pgmUnlock(pVM), VERR_PGM_PHYS_MMIO_EX_IPE);
3793	}
3794
3795	IOMR3MmioExNotifyUnmapped(pVM, pFirstMmio->pPhysHandlerR3->pvUserR3, GCPhys);
3796	}
3797
3798	/*
3799	* Unmap it.
3800	*/
3801	RTGCPHYS const GCPhysRangeNotify = pFirstMmio->RamRange.GCPhys;
3802	if (fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING)
3803	{
3804	/*
3805	* We've replaced RAM, replace with zero pages.
3806	*
3807	* Note! This is where we might differ a little from a real system, because
3808	* it's likely to just show the RAM pages as they were before the
3809	* MMIO/MMIO2 region was mapped here.
3810	*/
3811	/* Only one chunk allowed when overlapping! */
3812	Assert(fOldFlags & PGMREGMMIORANGE_F_LAST_CHUNK);
3813
3814	/* Restore the RAM pages we've replaced. */
3815	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3816	while (pRam->GCPhys > pFirstMmio->RamRange.GCPhysLast)
3817	pRam = pRam->pNextR3;
3818
3819	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3820	if (fOldFlags & PGMREGMMIORANGE_F_MMIO2)
3821	pVM->pgm.s.cZeroPages += cPagesLeft;
3822
3823	PPGMPAGE pPageDst = &pRam->aPages[(pFirstMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3824	while (cPagesLeft-- > 0)
3825	{
3826	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3827	pPageDst++;
3828	}
3829
3830	/* Flush physical page map TLB. */
3831	pgmPhysInvalidatePageMapTLB(pVM);
3832
3833	/* Update range state. */
3834	pFirstMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3835	pFirstMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3836	pFirstMmio->fFlags &= ~(PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MAPPED);
3837	}
3838	else
3839	{
3840	/*
3841	* Unlink the chunks related to the MMIO/MMIO2 region.
3842	*/
3843	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3844	{
3845	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3846	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3847	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3848	pCurMmio->fFlags &= ~(PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MAPPED);
3849	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3850	break;
3851	}
3852	}
3853
3854	/* Force a PGM pool flush as guest ram references have been changed. */
3855	/** @todo not entirely SMP safe; assuming for now the guest takes care
3856	* of this internally (not touch mapped mmio while changing the
3857	* mapping). */
3858	PVMCPU pVCpu = VMMGetCpu(pVM);
3859	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3860	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3861
3862	pgmPhysInvalidatePageMapTLB(pVM);
3863	pgmPhysInvalidRamRangeTlbs(pVM);
3864
3865	/*
3866	* Notify NEM while holding the lock (experimental) and REM without (like always).
3867	*/
3868	uint32_t const fNemFlags = (fOldFlags & PGMREGMMIORANGE_F_MMIO2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0)
3869	\| (fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
3870	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhysRangeNotify, cbRange, fNemFlags);
3871	pgmUnlock(pVM);
3872	#ifdef VBOX_WITH_REM
3873	if ((fOldFlags & (PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MMIO2)) == PGMREGMMIORANGE_F_MMIO2)
3874	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeNotify, cbRange);
3875	#endif
3876	return rc;
3877	}
3878
3879
3880	/**
3881	* Reduces the mapping size of a MMIO2 or pre-registered MMIO region.
3882	*
3883	* This is mainly for dealing with old saved states after changing the default
3884	* size of a mapping region. See PGMDevHlpMMIOExReduce and
3885	* PDMPCIDEV::pfnRegionLoadChangeHookR3.
3886	*
3887	* The region must not currently be mapped when making this call. The VM state
3888	* must be state restore or VM construction.
3889	*
3890	* @returns VBox status code.
3891	* @param pVM The cross context VM structure.
3892	* @param pDevIns The device instance owning the region.
3893	* @param iSubDev The sub-device number of the registered region.
3894	* @param iRegion The index of the registered region.
3895	* @param cbRegion The new mapping size.
3896	*/
3897	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion)
3898	{
3899	/*
3900	* Validate input
3901	*/
3902	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3903	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3904	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3905	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3906	AssertReturn(cbRegion >= X86_PAGE_SIZE, VERR_INVALID_PARAMETER);
3907	AssertReturn(!(cbRegion & X86_PAGE_OFFSET_MASK), VERR_UNSUPPORTED_ALIGNMENT);
3908	VMSTATE enmVmState = VMR3GetState(pVM);
3909	AssertLogRelMsgReturn( enmVmState == VMSTATE_CREATING
3910	\|\| enmVmState == VMSTATE_LOADING,
3911	("enmVmState=%d (%s)\n", enmVmState, VMR3GetStateName(enmVmState)),
3912	VERR_VM_INVALID_VM_STATE);
3913
3914	int rc = pgmLock(pVM);
3915	AssertRCReturn(rc, rc);
3916
3917	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3918	if (pFirstMmio)
3919	{
3920	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3921	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED))
3922	{
3923	/*
3924	* NOTE! Current implementation does not support multiple ranges.
3925	* Implement when there is a real world need and thus a testcase.
3926	*/
3927	AssertLogRelMsgStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK,
3928	("%s: %#x\n", pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3929	rc = VERR_NOT_SUPPORTED);
3930	if (RT_SUCCESS(rc))
3931	{
3932	/*
3933	* Make the change.
3934	*/
3935	Log(("PGMR3PhysMMIOExReduce: %s changes from %RGp bytes (%RGp) to %RGp bytes.\n",
3936	pFirstMmio->RamRange.pszDesc, pFirstMmio->RamRange.cb, pFirstMmio->cbReal, cbRegion));
3937
3938	AssertLogRelMsgStmt(cbRegion <= pFirstMmio->cbReal,
3939	("%s: cbRegion=%#RGp cbReal=%#RGp\n", pFirstMmio->RamRange.pszDesc, cbRegion, pFirstMmio->cbReal),
3940	rc = VERR_OUT_OF_RANGE);
3941	if (RT_SUCCESS(rc))
3942	{
3943	pFirstMmio->RamRange.cb = cbRegion;
3944	}
3945	}
3946	}
3947	else
3948	rc = VERR_WRONG_ORDER;
3949	}
3950	else
3951	rc = VERR_NOT_FOUND;
3952
3953	pgmUnlock(pVM);
3954	return rc;
3955	}
3956
3957
3958	/**
3959	* Checks if the given address is an MMIO2 or pre-registered MMIO base address
3960	* or not.
3961	*
3962	* @returns true/false accordingly.
3963	* @param pVM The cross context VM structure.
3964	* @param pDevIns The owner of the memory, optional.
3965	* @param GCPhys The address to check.
3966	*/
3967	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
3968	{
3969	/*
3970	* Validate input
3971	*/
3972	VM_ASSERT_EMT_RETURN(pVM, false);
3973	AssertPtrReturn(pDevIns, false);
3974	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
3975	AssertReturn(GCPhys != 0, false);
3976	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
3977
3978	/*
3979	* Search the list.
3980	*/
3981	pgmLock(pVM);
3982	for (PPGMREGMMIORANGE pCurMmio = pVM->pgm.s.pRegMmioRangesR3; pCurMmio; pCurMmio = pCurMmio->pNextR3)
3983	if (pCurMmio->RamRange.GCPhys == GCPhys)
3984	{
3985	Assert(pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED);
3986	bool fRet = RT_BOOL(pCurMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3987	pgmUnlock(pVM);
3988	return fRet;
3989	}
3990	pgmUnlock(pVM);
3991	return false;
3992	}
3993
3994
3995	/**
3996	* Gets the HC physical address of a page in the MMIO2 region.
3997	*
3998	* This is API is intended for MMHyper and shouldn't be called
3999	* by anyone else...
4000	*
4001	* @returns VBox status code.
4002	* @param pVM The cross context VM structure.
4003	* @param pDevIns The owner of the memory, optional.
4004	* @param iSubDev Sub-device number.
4005	* @param iRegion The region.
4006	* @param off The page expressed an offset into the MMIO2 region.
4007	* @param pHCPhys Where to store the result.
4008	*/
4009	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
4010	RTGCPHYS off, PRTHCPHYS pHCPhys)
4011	{
4012	/*
4013	* Validate input
4014	*/
4015	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4016	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4017	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
4018	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4019
4020	pgmLock(pVM);
4021	PPGMREGMMIORANGE pCurMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
4022	AssertReturn(pCurMmio, VERR_NOT_FOUND);
4023	AssertReturn(pCurMmio->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK), VERR_WRONG_TYPE);
4024
4025	while ( off >= pCurMmio->RamRange.cb
4026	&& !(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK))
4027	{
4028	off -= pCurMmio->RamRange.cb;
4029	pCurMmio = pCurMmio->pNextR3;
4030	}
4031	AssertReturn(off < pCurMmio->RamRange.cb, VERR_INVALID_PARAMETER);
4032
4033	PCPGMPAGE pPage = &pCurMmio->RamRange.aPages[off >> PAGE_SHIFT];
4034	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4035	pgmUnlock(pVM);
4036	return VINF_SUCCESS;
4037	}
4038
4039
4040	/**
4041	* Maps a portion of an MMIO2 region into kernel space (host).
4042	*
4043	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
4044	* or the VM is terminated.
4045	*
4046	* @return VBox status code.
4047	*
4048	* @param pVM The cross context VM structure.
4049	* @param pDevIns The device owning the MMIO2 memory.
4050	* @param iSubDev The sub-device number.
4051	* @param iRegion The region.
4052	* @param off The offset into the region. Must be page aligned.
4053	* @param cb The number of bytes to map. Must be page aligned.
4054	* @param pszDesc Mapping description.
4055	* @param pR0Ptr Where to store the R0 address.
4056	*/
4057	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
4058	RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr)
4059	{
4060	/*
4061	* Validate input.
4062	*/
4063	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4064	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4065	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
4066	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4067
4068	PPGMREGMMIORANGE pFirstRegMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
4069	AssertReturn(pFirstRegMmio, VERR_NOT_FOUND);
4070	AssertReturn(pFirstRegMmio->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK), VERR_WRONG_TYPE);
4071	AssertReturn(off < pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
4072	AssertReturn(cb <= pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
4073	AssertReturn(off + cb <= pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
4074	NOREF(pszDesc);
4075
4076	/*
4077	* Pass the request on to the support library/driver.
4078	*/
4079	#if defined(RT_OS_WINDOWS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_OS2) /** @todo Fully implement RTR0MemObjMapKernelEx everywhere. */
4080	AssertLogRelReturn(off == 0, VERR_NOT_SUPPORTED);
4081	AssertLogRelReturn(pFirstRegMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK, VERR_NOT_SUPPORTED);
4082	int rc = SUPR3PageMapKernel(pFirstRegMmio->pvR3, 0 /off/, pFirstRegMmio->RamRange.cb, 0 /fFlags/, pR0Ptr);
4083	#else
4084	int rc = SUPR3PageMapKernel(pFirstRegMmio->pvR3, off, cb, 0 /fFlags/, pR0Ptr);
4085	#endif
4086
4087	return rc;
4088	}
4089
4090
4091	/**
4092	* Changes the region number of an MMIO2 or pre-registered MMIO region.
4093	*
4094	* This is only for dealing with save state issues, nothing else.
4095	*
4096	* @return VBox status code.
4097	*
4098	* @param pVM The cross context VM structure.
4099	* @param pDevIns The device owning the MMIO2 memory.
4100	* @param iSubDev The sub-device number.
4101	* @param iRegion The region.
4102	* @param iNewRegion The new region index.
4103	*
4104	* @sa @bugref{9359}
4105	*/
4106	VMMR3_INT_DECL(int) PGMR3PhysMMIOExChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
4107	uint32_t iNewRegion)
4108	{
4109	/*
4110	* Validate input.
4111	*/
4112	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4113	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4114	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
4115	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4116	AssertReturn(iNewRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4117
4118	AssertReturn(pVM->enmVMState == VMSTATE_LOADING, VERR_INVALID_STATE);
4119
4120	PPGMREGMMIORANGE pFirstRegMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
4121	AssertReturn(pFirstRegMmio, VERR_NOT_FOUND);
4122	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iNewRegion) == NULL, VERR_RESOURCE_IN_USE);
4123
4124	/*
4125	* Make the change.
4126	*/
4127	pFirstRegMmio->iRegion = (uint8_t)iNewRegion;
4128
4129	return VINF_SUCCESS;
4130	}
4131
4132
4133	/**
4134	* Worker for PGMR3PhysRomRegister.
4135	*
4136	* This is here to simplify lock management, i.e. the caller does all the
4137	* locking and we can simply return without needing to remember to unlock
4138	* anything first.
4139	*
4140	* @returns VBox status code.
4141	* @param pVM The cross context VM structure.
4142	* @param pDevIns The device instance owning the ROM.
4143	* @param GCPhys First physical address in the range.
4144	* Must be page aligned!
4145	* @param cb The size of the range (in bytes).
4146	* Must be page aligned!
4147	* @param pvBinary Pointer to the binary data backing the ROM image.
4148	* @param cbBinary The size of the binary data pvBinary points to.
4149	* This must be less or equal to @a cb.
4150	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4151	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4152	* @param pszDesc Pointer to description string. This must not be freed.
4153	*/
4154	static int pgmR3PhysRomRegisterLocked(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4155	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
4156	{
4157	/*
4158	* Validate input.
4159	*/
4160	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4161	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
4162	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
4163	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4164	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4165	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
4166	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
4167	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
4168	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
4169
4170	const uint32_t cPages = cb >> PAGE_SHIFT;
4171
4172	/*
4173	* Find the ROM location in the ROM list first.
4174	*/
4175	PPGMROMRANGE pRomPrev = NULL;
4176	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
4177	while (pRom && GCPhysLast >= pRom->GCPhys)
4178	{
4179	if ( GCPhys <= pRom->GCPhysLast
4180	&& GCPhysLast >= pRom->GCPhys)
4181	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
4182	GCPhys, GCPhysLast, pszDesc,
4183	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
4184	VERR_PGM_RAM_CONFLICT);
4185	/* next */
4186	pRomPrev = pRom;
4187	pRom = pRom->pNextR3;
4188	}
4189
4190	/*
4191	* Find the RAM location and check for conflicts.
4192	*
4193	* Conflict detection is a bit different than for RAM
4194	* registration since a ROM can be located within a RAM
4195	* range. So, what we have to check for is other memory
4196	* types (other than RAM that is) and that we don't span
4197	* more than one RAM range (layz).
4198	*/
4199	bool fRamExists = false;
4200	PPGMRAMRANGE pRamPrev = NULL;
4201	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4202	while (pRam && GCPhysLast >= pRam->GCPhys)
4203	{
4204	if ( GCPhys <= pRam->GCPhysLast
4205	&& GCPhysLast >= pRam->GCPhys)
4206	{
4207	/* completely within? */
4208	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
4209	&& GCPhysLast <= pRam->GCPhysLast,
4210	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
4211	GCPhys, GCPhysLast, pszDesc,
4212	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
4213	VERR_PGM_RAM_CONFLICT);
4214	fRamExists = true;
4215	break;
4216	}
4217
4218	/* next */
4219	pRamPrev = pRam;
4220	pRam = pRam->pNextR3;
4221	}
4222	if (fRamExists)
4223	{
4224	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4225	uint32_t cPagesLeft = cPages;
4226	while (cPagesLeft-- > 0)
4227	{
4228	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
4229	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
4230	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
4231	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
4232	Assert(PGM_PAGE_IS_ZERO(pPage));
4233	pPage++;
4234	}
4235	}
4236
4237	/*
4238	* Update the base memory reservation if necessary.
4239	*/
4240	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
4241	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4242	cExtraBaseCost += cPages;
4243	if (cExtraBaseCost)
4244	{
4245	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
4246	if (RT_FAILURE(rc))
4247	return rc;
4248	}
4249
4250	/*
4251	* Allocate memory for the virgin copy of the RAM.
4252	*/
4253	PGMMALLOCATEPAGESREQ pReq;
4254	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
4255	AssertRCReturn(rc, rc);
4256
4257	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4258	{
4259	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
4260	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
4261	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
4262	}
4263
4264	rc = GMMR3AllocatePagesPerform(pVM, pReq);
4265	if (RT_FAILURE(rc))
4266	{
4267	GMMR3AllocatePagesCleanup(pReq);
4268	return rc;
4269	}
4270
4271	/*
4272	* Allocate the new ROM range and RAM range (if necessary).
4273	*/
4274	PPGMROMRANGE pRomNew;
4275	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
4276	if (RT_SUCCESS(rc))
4277	{
4278	PPGMRAMRANGE pRamNew = NULL;
4279	if (!fRamExists)
4280	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
4281	if (RT_SUCCESS(rc))
4282	{
4283	/*
4284	* Initialize and insert the RAM range (if required).
4285	*/
4286	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
4287	if (!fRamExists)
4288	{
4289	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
4290	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
4291	pRamNew->GCPhys = GCPhys;
4292	pRamNew->GCPhysLast = GCPhysLast;
4293	pRamNew->cb = cb;
4294	pRamNew->pszDesc = pszDesc;
4295	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
4296	pRamNew->pvR3 = NULL;
4297	pRamNew->paLSPages = NULL;
4298
4299	PPGMPAGE pPage = &pRamNew->aPages[0];
4300	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
4301	{
4302	PGM_PAGE_INIT(pPage,
4303	pReq->aPages[iPage].HCPhysGCPhys,
4304	pReq->aPages[iPage].idPage,
4305	PGMPAGETYPE_ROM,
4306	PGM_PAGE_STATE_ALLOCATED);
4307
4308	pRomPage->Virgin = *pPage;
4309	}
4310
4311	pVM->pgm.s.cAllPages += cPages;
4312	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
4313	}
4314	else
4315	{
4316	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4317	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
4318	{
4319	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_ROM);
4320	PGM_PAGE_SET_HCPHYS(pVM, pPage, pReq->aPages[iPage].HCPhysGCPhys);
4321	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
4322	PGM_PAGE_SET_PAGEID(pVM, pPage, pReq->aPages[iPage].idPage);
4323	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4324	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
4325	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
4326
4327	pRomPage->Virgin = *pPage;
4328	}
4329
4330	pRamNew = pRam;
4331
4332	pVM->pgm.s.cZeroPages -= cPages;
4333	}
4334	pVM->pgm.s.cPrivatePages += cPages;
4335
4336	/* Flush physical page map TLB. */
4337	pgmPhysInvalidatePageMapTLB(pVM);
4338
4339
4340	/* Notify NEM before we register handlers. */
4341	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_ROM_F_REPLACE : 0)
4342	\| (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED ? NEM_NOTIFY_PHYS_ROM_F_SHADOW : 0);
4343	rc = NEMR3NotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fNemNotify);
4344
4345	/*
4346	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
4347	*
4348	* If it's shadowed we'll register the handler after the ROM notification
4349	* so we get the access handler callbacks that we should. If it isn't
4350	* shadowed we'll do it the other way around to make REM use the built-in
4351	* ROM behavior and not the handler behavior (which is to route all access
4352	* to PGM atm).
4353	*/
4354	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4355	{
4356	#ifdef VBOX_WITH_REM
4357	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
4358	#endif
4359	if (RT_SUCCESS(rc))
4360	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4361	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
4362	pszDesc);
4363	}
4364	else
4365	{
4366	if (RT_SUCCESS(rc))
4367	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4368	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
4369	pszDesc);
4370	#ifdef VBOX_WITH_REM
4371	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
4372	#endif
4373	}
4374	if (RT_SUCCESS(rc))
4375	{
4376	/*
4377	* Copy the image over to the virgin pages.
4378	* This must be done after linking in the RAM range.
4379	*/
4380	size_t cbBinaryLeft = cbBinary;
4381	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
4382	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4383	{
4384	void *pvDstPage;
4385	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
4386	if (RT_FAILURE(rc))
4387	{
4388	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
4389	break;
4390	}
4391	if (cbBinaryLeft >= PAGE_SIZE)
4392	{
4393	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
4394	cbBinaryLeft -= PAGE_SIZE;
4395	}
4396	else
4397	{
4398	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
4399	if (cbBinaryLeft > 0)
4400	{
4401	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
4402	cbBinaryLeft = 0;
4403	}
4404	}
4405	}
4406	if (RT_SUCCESS(rc))
4407	{
4408	/*
4409	* Initialize the ROM range.
4410	* Note that the Virgin member of the pages has already been initialized above.
4411	*/
4412	pRomNew->GCPhys = GCPhys;
4413	pRomNew->GCPhysLast = GCPhysLast;
4414	pRomNew->cb = cb;
4415	pRomNew->fFlags = fFlags;
4416	pRomNew->idSavedState = UINT8_MAX;
4417	pRomNew->cbOriginal = cbBinary;
4418	pRomNew->pszDesc = pszDesc;
4419	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
4420	? pvBinary : RTMemDup(pvBinary, cbBinary);
4421	if (pRomNew->pvOriginal)
4422	{
4423	for (unsigned iPage = 0; iPage < cPages; iPage++)
4424	{
4425	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
4426	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
4427	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
4428	}
4429
4430	/* update the page count stats for the shadow pages. */
4431	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4432	{
4433	pVM->pgm.s.cZeroPages += cPages;
4434	pVM->pgm.s.cAllPages += cPages;
4435	}
4436
4437	/*
4438	* Insert the ROM range, tell REM and return successfully.
4439	*/
4440	pRomNew->pNextR3 = pRom;
4441	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4442	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
4443
4444	if (pRomPrev)
4445	{
4446	pRomPrev->pNextR3 = pRomNew;
4447	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
4448	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
4449	}
4450	else
4451	{
4452	pVM->pgm.s.pRomRangesR3 = pRomNew;
4453	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
4454	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
4455	}
4456
4457	pgmPhysInvalidatePageMapTLB(pVM);
4458	GMMR3AllocatePagesCleanup(pReq);
4459
4460	/* Notify NEM again. */
4461	return NEMR3NotifyPhysRomRegisterLate(pVM, GCPhys, cb, fNemNotify);
4462	}
4463
4464	/* bail out */
4465	rc = VERR_NO_MEMORY;
4466	}
4467
4468	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
4469	AssertRC(rc2);
4470	}
4471
4472	if (!fRamExists)
4473	{
4474	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
4475	MMHyperFree(pVM, pRamNew);
4476	}
4477	}
4478	MMHyperFree(pVM, pRomNew);
4479	}
4480
4481	/** @todo Purge the mapping cache or something... */
4482	GMMR3FreeAllocatedPages(pVM, pReq);
4483	GMMR3AllocatePagesCleanup(pReq);
4484	return rc;
4485	}
4486
4487
4488	/**
4489	* Registers a ROM image.
4490	*
4491	* Shadowed ROM images requires double the amount of backing memory, so,
4492	* don't use that unless you have to. Shadowing of ROM images is process
4493	* where we can select where the reads go and where the writes go. On real
4494	* hardware the chipset provides means to configure this. We provide
4495	* PGMR3PhysProtectROM() for this purpose.
4496	*
4497	* A read-only copy of the ROM image will always be kept around while we
4498	* will allocate RAM pages for the changes on demand (unless all memory
4499	* is configured to be preallocated).
4500	*
4501	* @returns VBox status code.
4502	* @param pVM The cross context VM structure.
4503	* @param pDevIns The device instance owning the ROM.
4504	* @param GCPhys First physical address in the range.
4505	* Must be page aligned!
4506	* @param cb The size of the range (in bytes).
4507	* Must be page aligned!
4508	* @param pvBinary Pointer to the binary data backing the ROM image.
4509	* @param cbBinary The size of the binary data pvBinary points to.
4510	* This must be less or equal to @a cb.
4511	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4512	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4513	* @param pszDesc Pointer to description string. This must not be freed.
4514	*
4515	* @remark There is no way to remove the rom, automatically on device cleanup or
4516	* manually from the device yet. This isn't difficult in any way, it's
4517	* just not something we expect to be necessary for a while.
4518	*/
4519	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4520	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
4521	{
4522	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
4523	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
4524	pgmLock(pVM);
4525	int rc = pgmR3PhysRomRegisterLocked(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
4526	pgmUnlock(pVM);
4527	return rc;
4528	}
4529
4530
4531	/**
4532	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
4533	* that the virgin part is untouched.
4534	*
4535	* This is done after the normal memory has been cleared.
4536	*
4537	* ASSUMES that the caller owns the PGM lock.
4538	*
4539	* @param pVM The cross context VM structure.
4540	*/
4541	int pgmR3PhysRomReset(PVM pVM)
4542	{
4543	PGM_LOCK_ASSERT_OWNER(pVM);
4544	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4545	{
4546	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
4547
4548	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4549	{
4550	/*
4551	* Reset the physical handler.
4552	*/
4553	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
4554	AssertRCReturn(rc, rc);
4555
4556	/*
4557	* What we do with the shadow pages depends on the memory
4558	* preallocation option. If not enabled, we'll just throw
4559	* out all the dirty pages and replace them by the zero page.
4560	*/
4561	if (!pVM->pgm.s.fRamPreAlloc)
4562	{
4563	/* Free the dirty pages. */
4564	uint32_t cPendingPages = 0;
4565	PGMMFREEPAGESREQ pReq;
4566	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4567	AssertRCReturn(rc, rc);
4568
4569	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4570	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
4571	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
4572	{
4573	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
4574	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
4575	pRom->GCPhys + (iPage << PAGE_SHIFT),
4576	(PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pRom->aPages[iPage].Shadow));
4577	AssertLogRelRCReturn(rc, rc);
4578	}
4579
4580	if (cPendingPages)
4581	{
4582	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
4583	AssertLogRelRCReturn(rc, rc);
4584	}
4585	GMMR3FreePagesCleanup(pReq);
4586	}
4587	else
4588	{
4589	/* clear all the shadow pages. */
4590	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4591	{
4592	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
4593	continue;
4594	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
4595	void *pvDstPage;
4596	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4597	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
4598	if (RT_FAILURE(rc))
4599	break;
4600	ASMMemZeroPage(pvDstPage);
4601	}
4602	AssertRCReturn(rc, rc);
4603	}
4604	}
4605
4606	/*
4607	* Restore the original ROM pages after a saved state load.
4608	* Also, in strict builds check that ROM pages remain unmodified.
4609	*/
4610	#ifndef VBOX_STRICT
4611	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4612	#endif
4613	{
4614	size_t cbSrcLeft = pRom->cbOriginal;
4615	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
4616	uint32_t cRestored = 0;
4617	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
4618	{
4619	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4620	void const *pvDstPage;
4621	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
4622	if (RT_FAILURE(rc))
4623	break;
4624
4625	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
4626	{
4627	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4628	{
4629	void *pvDstPageW;
4630	rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPageW);
4631	AssertLogRelRCReturn(rc, rc);
4632	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
4633	cRestored++;
4634	}
4635	else
4636	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
4637	}
4638	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
4639	}
4640	if (cRestored > 0)
4641	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
4642	}
4643	}
4644
4645	/* Clear the ROM restore flag now as we only need to do this once after
4646	loading saved state. */
4647	pVM->pgm.s.fRestoreRomPagesOnReset = false;
4648
4649	return VINF_SUCCESS;
4650	}
4651
4652
4653	/**
4654	* Called by PGMR3Term to free resources.
4655	*
4656	* ASSUMES that the caller owns the PGM lock.
4657	*
4658	* @param pVM The cross context VM structure.
4659	*/
4660	void pgmR3PhysRomTerm(PVM pVM)
4661	{
4662	/*
4663	* Free the heap copy of the original bits.
4664	*/
4665	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4666	{
4667	if ( pRom->pvOriginal
4668	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
4669	{
4670	RTMemFree((void *)pRom->pvOriginal);
4671	pRom->pvOriginal = NULL;
4672	}
4673	}
4674	}
4675
4676
4677	/**
4678	* Change the shadowing of a range of ROM pages.
4679	*
4680	* This is intended for implementing chipset specific memory registers
4681	* and will not be very strict about the input. It will silently ignore
4682	* any pages that are not the part of a shadowed ROM.
4683	*
4684	* @returns VBox status code.
4685	* @retval VINF_PGM_SYNC_CR3
4686	*
4687	* @param pVM The cross context VM structure.
4688	* @param GCPhys Where to start. Page aligned.
4689	* @param cb How much to change. Page aligned.
4690	* @param enmProt The new ROM protection.
4691	*/
4692	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
4693	{
4694	/*
4695	* Check input
4696	*/
4697	if (!cb)
4698	return VINF_SUCCESS;
4699	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4700	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4701	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4702	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4703	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
4704
4705	/*
4706	* Process the request.
4707	*/
4708	pgmLock(pVM);
4709	int rc = VINF_SUCCESS;
4710	bool fFlushTLB = false;
4711	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4712	{
4713	if ( GCPhys <= pRom->GCPhysLast
4714	&& GCPhysLast >= pRom->GCPhys
4715	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
4716	{
4717	/*
4718	* Iterate the relevant pages and make necessary the changes.
4719	*/
4720	bool fChanges = false;
4721	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
4722	? pRom->cb >> PAGE_SHIFT
4723	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
4724	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
4725	iPage < cPages;
4726	iPage++)
4727	{
4728	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
4729	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
4730	{
4731	fChanges = true;
4732
4733	/* flush references to the page. */
4734	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT));
4735	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage,
4736	true /fFlushPTEs/, &fFlushTLB);
4737	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
4738	rc = rc2;
4739	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pRamPage);
4740
4741	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
4742	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
4743
4744	pOld = pRamPage;
4745	pRamPage = pNew;
4746	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
4747
4748	/* Tell NEM about the backing and protection change. */
4749	if (VM_IS_NEM_ENABLED(pVM))
4750	{
4751	PGMPAGETYPE enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pNew);
4752	NEMHCNotifyPhysPageChanged(pVM, GCPhys, PGM_PAGE_GET_HCPHYS(pOld), PGM_PAGE_GET_HCPHYS(pNew),
4753	pgmPhysPageCalcNemProtection(pRamPage, enmType), enmType, &u2State);
4754	PGM_PAGE_SET_NEM_STATE(pRamPage, u2State);
4755	}
4756	}
4757	pRomPage->enmProt = enmProt;
4758	}
4759
4760	/*
4761	* Reset the access handler if we made changes, no need
4762	* to optimize this.
4763	*/
4764	if (fChanges)
4765	{
4766	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
4767	if (RT_FAILURE(rc2))
4768	{
4769	pgmUnlock(pVM);
4770	AssertRC(rc);
4771	return rc2;
4772	}
4773	}
4774
4775	/* Advance - cb isn't updated. */
4776	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
4777	}
4778	}
4779	pgmUnlock(pVM);
4780	if (fFlushTLB)
4781	PGM_INVL_ALL_VCPU_TLBS(pVM);
4782
4783	return rc;
4784	}
4785
4786
4787	/**
4788	* Sets the Address Gate 20 state.
4789	*
4790	* @param pVCpu The cross context virtual CPU structure.
4791	* @param fEnable True if the gate should be enabled.
4792	* False if the gate should be disabled.
4793	*/
4794	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
4795	{
4796	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
4797	if (pVCpu->pgm.s.fA20Enabled != fEnable)
4798	{
4799	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4800	PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
4801	if ( CPUMIsGuestInVmxRootMode(pCtx)
4802	&& !fEnable)
4803	{
4804	Log(("Cannot enter A20M mode while in VMX root mode\n"));
4805	return;
4806	}
4807	#endif
4808	pVCpu->pgm.s.fA20Enabled = fEnable;
4809	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
4810	#ifdef VBOX_WITH_REM
4811	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
4812	#endif
4813	NEMR3NotifySetA20(pVCpu, fEnable);
4814	#ifdef PGM_WITH_A20
4815	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
4816	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4817	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
4818	HMFlushTlb(pVCpu);
4819	#endif
4820	IEMTlbInvalidateAllPhysical(pVCpu);
4821	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
4822	}
4823	}
4824
4825
4826	/**
4827	* Tree enumeration callback for dealing with age rollover.
4828	* It will perform a simple compression of the current age.
4829	*/
4830	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
4831	{
4832	/* Age compression - ASSUMES iNow == 4. */
4833	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4834	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
4835	pChunk->iLastUsed = 3;
4836	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
4837	pChunk->iLastUsed = 2;
4838	else if (pChunk->iLastUsed)
4839	pChunk->iLastUsed = 1;
4840	else /* iLastUsed = 0 */
4841	pChunk->iLastUsed = 4;
4842
4843	NOREF(pvUser);
4844	return 0;
4845	}
4846
4847
4848	/**
4849	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
4850	*/
4851	typedef struct PGMR3PHYSCHUNKUNMAPCB
4852	{
4853	PVM pVM; /*< Pointer to the VM. /
4854	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
4855	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
4856
4857
4858	/**
4859	* Callback used to find the mapping that's been unused for
4860	* the longest time.
4861	*/
4862	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
4863	{
4864	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4865	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
4866
4867	/*
4868	* Check for locks and compare when last used.
4869	*/
4870	if (pChunk->cRefs)
4871	return 0;
4872	if (pChunk->cPermRefs)
4873	return 0;
4874	if ( pArg->pChunk
4875	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
4876	return 0;
4877
4878	/*
4879	* Check that it's not in any of the TLBs.
4880	*/
4881	PVM pVM = pArg->pVM;
4882	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
4883	== pChunk->Core.Key)
4884	{
4885	pChunk = NULL;
4886	return 0;
4887	}
4888	#ifdef VBOX_STRICT
4889	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
4890	{
4891	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
4892	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
4893	}
4894	#endif
4895
4896	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
4897	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
4898	return 0;
4899
4900	pArg->pChunk = pChunk;
4901	return 0;
4902	}
4903
4904
4905	/**
4906	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
4907	*
4908	* The candidate will not be part of any TLBs, so no need to flush
4909	* anything afterwards.
4910	*
4911	* @returns Chunk id.
4912	* @param pVM The cross context VM structure.
4913	*/
4914	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
4915	{
4916	PGM_LOCK_ASSERT_OWNER(pVM);
4917
4918	/*
4919	* Enumerate the age tree starting with the left most node.
4920	*/
4921	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4922	PGMR3PHYSCHUNKUNMAPCB Args;
4923	Args.pVM = pVM;
4924	Args.pChunk = NULL;
4925	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
4926	Assert(Args.pChunk);
4927	if (Args.pChunk)
4928	{
4929	Assert(Args.pChunk->cRefs == 0);
4930	Assert(Args.pChunk->cPermRefs == 0);
4931	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4932	return Args.pChunk->Core.Key;
4933	}
4934
4935	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4936	return INT32_MAX;
4937	}
4938
4939
4940	/**
4941	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
4942	*
4943	* This is only called on one of the EMTs while the other ones are waiting for
4944	* it to complete this function.
4945	*
4946	* @returns VINF_SUCCESS (VBox strict status code).
4947	* @param pVM The cross context VM structure.
4948	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
4949	* @param pvUser User pointer. Unused
4950	*
4951	*/
4952	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
4953	{
4954	int rc = VINF_SUCCESS;
4955	pgmLock(pVM);
4956	NOREF(pVCpu); NOREF(pvUser);
4957
4958	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
4959	{
4960	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
4961	/** @todo also not really efficient to unmap a chunk that contains PD
4962	* or PT pages. */
4963	pgmR3PoolClearAllRendezvous(pVM, &pVM->aCpus[0], NULL /* no need to flush the REM TLB as we already did that above */);
4964
4965	/*
4966	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
4967	*/
4968	GMMMAPUNMAPCHUNKREQ Req;
4969	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
4970	Req.Hdr.cbReq = sizeof(Req);
4971	Req.pvR3 = NULL;
4972	Req.idChunkMap = NIL_GMM_CHUNKID;
4973	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
4974	if (Req.idChunkUnmap != INT32_MAX)
4975	{
4976	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
4977	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
4978	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
4979	if (RT_SUCCESS(rc))
4980	{
4981	/*
4982	* Remove the unmapped one.
4983	*/
4984	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
4985	AssertRelease(pUnmappedChunk);
4986	AssertRelease(!pUnmappedChunk->cRefs);
4987	AssertRelease(!pUnmappedChunk->cPermRefs);
4988	pUnmappedChunk->pv = NULL;
4989	pUnmappedChunk->Core.Key = UINT32_MAX;
4990	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
4991	MMR3HeapFree(pUnmappedChunk);
4992	#else
4993	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
4994	#endif
4995	pVM->pgm.s.ChunkR3Map.c--;
4996	pVM->pgm.s.cUnmappedChunks++;
4997
4998	/*
4999	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
5000	*/
5001	/** @todo We should not flush chunks which include cr3 mappings. */
5002	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5003	{
5004	PPGMCPU pPGM = &pVM->aCpus[idCpu].pgm.s;
5005
5006	pPGM->pGst32BitPdR3 = NULL;
5007	pPGM->pGstPaePdptR3 = NULL;
5008	pPGM->pGstAmd64Pml4R3 = NULL;
5009	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
5010	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
5011	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
5012	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
5013	#endif
5014	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
5015	{
5016	pPGM->apGstPaePDsR3[i] = NULL;
5017	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
5018	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
5019	#endif
5020	}
5021
5022	/* Flush REM TLBs. */
5023	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5024	}
5025	#ifdef VBOX_WITH_REM
5026	/* Flush REM translation blocks. */
5027	REMFlushTBs(pVM);
5028	#endif
5029	}
5030	}
5031	}
5032	pgmUnlock(pVM);
5033	return rc;
5034	}
5035
5036	/**
5037	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
5038	*
5039	* @returns VBox status code.
5040	* @param pVM The cross context VM structure.
5041	*/
5042	void pgmR3PhysUnmapChunk(PVM pVM)
5043	{
5044	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
5045	AssertRC(rc);
5046	}
5047
5048
5049	/**
5050	* Maps the given chunk into the ring-3 mapping cache.
5051	*
5052	* This will call ring-0.
5053	*
5054	* @returns VBox status code.
5055	* @param pVM The cross context VM structure.
5056	* @param idChunk The chunk in question.
5057	* @param ppChunk Where to store the chunk tracking structure.
5058	*
5059	* @remarks Called from within the PGM critical section.
5060	* @remarks Can be called from any thread!
5061	*/
5062	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
5063	{
5064	int rc;
5065
5066	PGM_LOCK_ASSERT_OWNER(pVM);
5067
5068	/*
5069	* Move the chunk time forward.
5070	*/
5071	pVM->pgm.s.ChunkR3Map.iNow++;
5072	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
5073	{
5074	pVM->pgm.s.ChunkR3Map.iNow = 4;
5075	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
5076	}
5077
5078	/*
5079	* Allocate a new tracking structure first.
5080	*/
5081	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
5082	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
5083	#else
5084	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
5085	#endif
5086	AssertReturn(pChunk, VERR_NO_MEMORY);
5087	pChunk->Core.Key = idChunk;
5088	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
5089
5090	/*
5091	* Request the ring-0 part to map the chunk in question.
5092	*/
5093	GMMMAPUNMAPCHUNKREQ Req;
5094	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5095	Req.Hdr.cbReq = sizeof(Req);
5096	Req.pvR3 = NULL;
5097	Req.idChunkMap = idChunk;
5098	Req.idChunkUnmap = NIL_GMM_CHUNKID;
5099
5100	/* Must be callable from any thread, so can't use VMMR3CallR0. */
5101	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
5102	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5103	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
5104	if (RT_SUCCESS(rc))
5105	{
5106	pChunk->pv = Req.pvR3;
5107
5108	/*
5109	* If we're running out of virtual address space, then we should
5110	* unmap another chunk.
5111	*
5112	* Currently, an unmap operation requires that all other virtual CPUs
5113	* are idling and not by chance making use of the memory we're
5114	* unmapping. So, we create an async unmap operation here.
5115	*
5116	* Now, when creating or restoring a saved state this wont work very
5117	* well since we may want to restore all guest RAM + a little something.
5118	* So, we have to do the unmap synchronously. Fortunately for us
5119	* though, during these operations the other virtual CPUs are inactive
5120	* and it should be safe to do this.
5121	*/
5122	/** @todo Eventually we should lock all memory when used and do
5123	* map+unmap as one kernel call without any rendezvous or
5124	* other precautions. */
5125	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
5126	{
5127	switch (VMR3GetState(pVM))
5128	{
5129	case VMSTATE_LOADING:
5130	case VMSTATE_SAVING:
5131	{
5132	PVMCPU pVCpu = VMMGetCpu(pVM);
5133	if ( pVCpu
5134	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
5135	{
5136	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
5137	break;
5138	}
5139	}
5140	RT_FALL_THRU();
5141	default:
5142	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
5143	AssertRC(rc);
5144	break;
5145	}
5146	}
5147
5148	/*
5149	* Update the tree. We must do this after any unmapping to make sure
5150	* the chunk we're going to return isn't unmapped by accident.
5151	*/
5152	AssertPtr(Req.pvR3);
5153	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
5154	AssertRelease(fRc);
5155	pVM->pgm.s.ChunkR3Map.c++;
5156	pVM->pgm.s.cMappedChunks++;
5157	}
5158	else
5159	{
5160	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
5161	* should probably restrict ourselves on linux. */
5162	AssertRC(rc);
5163	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
5164	MMR3HeapFree(pChunk);
5165	#else
5166	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
5167	#endif
5168	pChunk = NULL;
5169	}
5170
5171	*ppChunk = pChunk;
5172	return rc;
5173	}
5174
5175
5176	/**
5177	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
5178	*
5179	* @returns see pgmR3PhysChunkMap.
5180	* @param pVM The cross context VM structure.
5181	* @param idChunk The chunk to map.
5182	*/
5183	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
5184	{
5185	PPGMCHUNKR3MAP pChunk;
5186	int rc;
5187
5188	pgmLock(pVM);
5189	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
5190	pgmUnlock(pVM);
5191	return rc;
5192	}
5193
5194
5195	/**
5196	* Invalidates the TLB for the ring-3 mapping cache.
5197	*
5198	* @param pVM The cross context VM structure.
5199	*/
5200	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
5201	{
5202	pgmLock(pVM);
5203	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5204	{
5205	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
5206	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
5207	}
5208	/* The page map TLB references chunks, so invalidate that one too. */
5209	pgmPhysInvalidatePageMapTLB(pVM);
5210	pgmUnlock(pVM);
5211	}
5212
5213
5214	/**
5215	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE to allocate a large
5216	* (2MB) page for use with a nested paging PDE.
5217	*
5218	* @returns The following VBox status codes.
5219	* @retval VINF_SUCCESS on success.
5220	* @retval VINF_EM_NO_MEMORY if we're out of memory.
5221	*
5222	* @param pVM The cross context VM structure.
5223	* @param GCPhys GC physical start address of the 2 MB range
5224	*/
5225	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
5226	{
5227	#ifdef PGM_WITH_LARGE_PAGES
5228	uint64_t u64TimeStamp1, u64TimeStamp2;
5229
5230	pgmLock(pVM);
5231
5232	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
5233	u64TimeStamp1 = RTTimeMilliTS();
5234	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
5235	u64TimeStamp2 = RTTimeMilliTS();
5236	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
5237	if (RT_SUCCESS(rc))
5238	{
5239	Assert(pVM->pgm.s.cLargeHandyPages == 1);
5240
5241	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
5242	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
5243
5244	void *pv;
5245
5246	/* Map the large page into our address space.
5247	*
5248	* Note: assuming that within the 2 MB range:
5249	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
5250	* - user space mapping is continuous as well
5251	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
5252	*/
5253	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
5254	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", idPage, HCPhys, rc));
5255
5256	if (RT_SUCCESS(rc))
5257	{
5258	/*
5259	* Clear the pages.
5260	*/
5261	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
5262	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
5263	{
5264	ASMMemZeroPage(pv);
5265
5266	PPGMPAGE pPage;
5267	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
5268	AssertRC(rc);
5269
5270	Assert(PGM_PAGE_IS_ZERO(pPage));
5271	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRZPageReplaceZero);
5272	pVM->pgm.s.cZeroPages--;
5273
5274	/*
5275	* Do the PGMPAGE modifications.
5276	*/
5277	pVM->pgm.s.cPrivatePages++;
5278	PGM_PAGE_SET_HCPHYS(pVM, pPage, HCPhys);
5279	PGM_PAGE_SET_PAGEID(pVM, pPage, idPage);
5280	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
5281	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE);
5282	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5283	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5284
5285	/* Somewhat dirty assumption that page ids are increasing. */
5286	idPage++;
5287
5288	HCPhys += PAGE_SIZE;
5289	GCPhys += PAGE_SIZE;
5290
5291	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
5292
5293	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
5294	}
5295	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
5296
5297	/* Flush all TLBs. */
5298	PGM_INVL_ALL_VCPU_TLBS(pVM);
5299	pgmPhysInvalidatePageMapTLB(pVM);
5300	}
5301	pVM->pgm.s.cLargeHandyPages = 0;
5302	}
5303
5304	if (RT_SUCCESS(rc))
5305	{
5306	static uint32_t cTimeOut = 0;
5307	uint64_t u64TimeStampDelta = u64TimeStamp2 - u64TimeStamp1;
5308
5309	if (u64TimeStampDelta > 100)
5310	{
5311	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatLargePageOverflow);
5312	if ( ++cTimeOut > 10
5313	\|\| u64TimeStampDelta > 1000 /* more than one second forces an early retirement from allocating large pages. */)
5314	{
5315	/* If repeated attempts to allocate a large page takes more than 100 ms, then we fall back to normal 4k pages.
5316	* E.g. Vista 64 tries to move memory around, which takes a huge amount of time.
5317	*/
5318	LogRel(("PGMR3PhysAllocateLargePage: allocating large pages takes too long (last attempt %d ms; nr of timeouts %d); DISABLE\n", u64TimeStampDelta, cTimeOut));
5319	PGMSetLargePageUsage(pVM, false);
5320	}
5321	}
5322	else
5323	if (cTimeOut > 0)
5324	cTimeOut--;
5325	}
5326
5327	pgmUnlock(pVM);
5328	return rc;
5329	#else
5330	RT_NOREF(pVM, GCPhys);
5331	return VERR_NOT_IMPLEMENTED;
5332	#endif /* PGM_WITH_LARGE_PAGES */
5333	}
5334
5335
5336	/**
5337	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
5338	*
5339	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
5340	* signal and clear the out of memory condition. When contracted, this API is
5341	* used to try clear the condition when the user wants to resume.
5342	*
5343	* @returns The following VBox status codes.
5344	* @retval VINF_SUCCESS on success. FFs cleared.
5345	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
5346	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
5347	*
5348	* @param pVM The cross context VM structure.
5349	*
5350	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
5351	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
5352	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
5353	* handler.
5354	*/
5355	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
5356	{
5357	pgmLock(pVM);
5358
5359	/*
5360	* Allocate more pages, noting down the index of the first new page.
5361	*/
5362	uint32_t iClear = pVM->pgm.s.cHandyPages;
5363	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
5364	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
5365	int rcAlloc = VINF_SUCCESS;
5366	int rcSeed = VINF_SUCCESS;
5367	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5368	while (rc == VERR_GMM_SEED_ME)
5369	{
5370	void *pvChunk;
5371	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
5372	if (RT_SUCCESS(rc))
5373	{
5374	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
5375	if (RT_FAILURE(rc))
5376	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
5377	}
5378	if (RT_SUCCESS(rc))
5379	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5380	}
5381
5382	/** @todo we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
5383	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
5384	&& pVM->pgm.s.cHandyPages > 0)
5385	{
5386	/* Still handy pages left, so don't panic. */
5387	rc = VINF_SUCCESS;
5388	}
5389
5390	if (RT_SUCCESS(rc))
5391	{
5392	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
5393	Assert(pVM->pgm.s.cHandyPages > 0);
5394	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5395	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
5396
5397	#ifdef VBOX_STRICT
5398	uint32_t i;
5399	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
5400	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
5401	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
5402	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
5403	break;
5404	if (i != pVM->pgm.s.cHandyPages)
5405	{
5406	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
5407	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
5408	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
5409	RTAssertMsg2Add("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%\n", j,
5410	pVM->pgm.s.aHandyPages[j].idPage,
5411	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
5412	pVM->pgm.s.aHandyPages[j].idSharedPage,
5413	j == i ? " <---" : "");
5414	RTAssertPanic();
5415	}
5416	#endif
5417	/*
5418	* Clear the pages.
5419	*/
5420	while (iClear < pVM->pgm.s.cHandyPages)
5421	{
5422	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
5423	void *pv;
5424	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
5425	AssertLogRelMsgBreak(RT_SUCCESS(rc),
5426	("%u/%u: idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n",
5427	iClear, pVM->pgm.s.cHandyPages, pPage->idPage, pPage->HCPhysGCPhys, rc));
5428	ASMMemZeroPage(pv);
5429	iClear++;
5430	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
5431	}
5432	}
5433	else
5434	{
5435	uint64_t cAllocPages, cMaxPages, cBalloonPages;
5436
5437	/*
5438	* We should never get here unless there is a genuine shortage of
5439	* memory (or some internal error). Flag the error so the VM can be
5440	* suspended ASAP and the user informed. If we're totally out of
5441	* handy pages we will return failure.
5442	*/
5443	/* Report the failure. */
5444	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
5445	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
5446	rc, rcAlloc, rcSeed,
5447	pVM->pgm.s.cHandyPages,
5448	pVM->pgm.s.cAllPages,
5449	pVM->pgm.s.cPrivatePages,
5450	pVM->pgm.s.cSharedPages,
5451	pVM->pgm.s.cZeroPages));
5452
5453	if (GMMR3QueryMemoryStats(pVM, &cAllocPages, &cMaxPages, &cBalloonPages) == VINF_SUCCESS)
5454	{
5455	LogRel(("GMM: Statistics:\n"
5456	" Allocated pages: %RX64\n"
5457	" Maximum pages: %RX64\n"
5458	" Ballooned pages: %RX64\n", cAllocPages, cMaxPages, cBalloonPages));
5459	}
5460
5461	if ( rc != VERR_NO_MEMORY
5462	&& rc != VERR_NO_PHYS_MEMORY
5463	&& rc != VERR_LOCK_FAILED)
5464	{
5465	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5466	{
5467	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
5468	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
5469	pVM->pgm.s.aHandyPages[i].idSharedPage));
5470	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
5471	if (idPage != NIL_GMM_PAGEID)
5472	{
5473	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
5474	pRam;
5475	pRam = pRam->pNextR3)
5476	{
5477	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
5478	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5479	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
5480	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
5481	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
5482	}
5483	}
5484	}
5485	}
5486
5487	if (rc == VERR_NO_MEMORY)
5488	{
5489	uint64_t cbHostRamAvail = 0;
5490	int rc2 = RTSystemQueryAvailableRam(&cbHostRamAvail);
5491	if (RT_SUCCESS(rc2))
5492	LogRel(("Host RAM: %RU64MB available\n", cbHostRamAvail / _1M));
5493	else
5494	LogRel(("Cannot determine the amount of available host memory\n"));
5495	}
5496
5497	/* Set the FFs and adjust rc. */
5498	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5499	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
5500	if ( rc == VERR_NO_MEMORY
5501	\|\| rc == VERR_NO_PHYS_MEMORY
5502	\|\| rc == VERR_LOCK_FAILED)
5503	rc = VINF_EM_NO_MEMORY;
5504	}
5505
5506	pgmUnlock(pVM);
5507	return rc;
5508	}
5509
5510
5511	/**
5512	* Frees the specified RAM page and replaces it with the ZERO page.
5513	*
5514	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
5515	*
5516	* @param pVM The cross context VM structure.
5517	* @param pReq Pointer to the request.
5518	* @param pcPendingPages Where the number of pages waiting to be freed are
5519	* kept. This will normally be incremented.
5520	* @param pPage Pointer to the page structure.
5521	* @param GCPhys The guest physical address of the page, if applicable.
5522	* @param enmNewType New page type for NEM notification, since several
5523	* callers will change the type upon successful return.
5524	*
5525	* @remarks The caller must own the PGM lock.
5526	*/
5527	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
5528	PGMPAGETYPE enmNewType)
5529	{
5530	/*
5531	* Assert sanity.
5532	*/
5533	PGM_LOCK_ASSERT_OWNER(pVM);
5534	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
5535	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
5536	{
5537	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5538	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
5539	}
5540
5541	/** @todo What about ballooning of large pages??! */
5542	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
5543	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
5544
5545	if ( PGM_PAGE_IS_ZERO(pPage)
5546	\|\| PGM_PAGE_IS_BALLOONED(pPage))
5547	return VINF_SUCCESS;
5548
5549	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
5550	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
5551	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
5552	\|\| idPage > GMM_PAGEID_LAST
5553	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
5554	{
5555	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5556	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
5557	}
5558	const RTHCPHYS HCPhysPrev = PGM_PAGE_GET_HCPHYS(pPage);
5559
5560	/* update page count stats. */
5561	if (PGM_PAGE_IS_SHARED(pPage))
5562	pVM->pgm.s.cSharedPages--;
5563	else
5564	pVM->pgm.s.cPrivatePages--;
5565	pVM->pgm.s.cZeroPages++;
5566
5567	/* Deal with write monitored pages. */
5568	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
5569	{
5570	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
5571	pVM->pgm.s.cWrittenToPages++;
5572	}
5573
5574	/*
5575	* pPage = ZERO page.
5576	*/
5577	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
5578	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
5579	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
5580	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
5581	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5582	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5583
5584	/* Flush physical page map TLB entry. */
5585	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
5586
5587	/* Notify NEM. */
5588	/** @todo consider doing batch NEM notifications. */
5589	if (VM_IS_NEM_ENABLED(pVM))
5590	{
5591	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pPage);
5592	NEMHCNotifyPhysPageChanged(pVM, GCPhys, HCPhysPrev, pVM->pgm.s.HCPhysZeroPg,
5593	pgmPhysPageCalcNemProtection(pPage, enmNewType), enmNewType, &u2State);
5594	PGM_PAGE_SET_NEM_STATE(pPage, u2State);
5595	}
5596
5597	/*
5598	* Make sure it's not in the handy page array.
5599	*/
5600	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5601	{
5602	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
5603	{
5604	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
5605	break;
5606	}
5607	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
5608	{
5609	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
5610	break;
5611	}
5612	}
5613
5614	/*
5615	* Push it onto the page array.
5616	*/
5617	uint32_t iPage = *pcPendingPages;
5618	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
5619	*pcPendingPages += 1;
5620
5621	pReq->aPages[iPage].idPage = idPage;
5622
5623	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
5624	return VINF_SUCCESS;
5625
5626	/*
5627	* Flush the pages.
5628	*/
5629	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
5630	if (RT_SUCCESS(rc))
5631	{
5632	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
5633	*pcPendingPages = 0;
5634	}
5635	return rc;
5636	}
5637
5638
5639	/**
5640	* Converts a GC physical address to a HC ring-3 pointer, with some
5641	* additional checks.
5642	*
5643	* @returns VBox status code.
5644	* @retval VINF_SUCCESS on success.
5645	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
5646	* access handler of some kind.
5647	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
5648	* accesses or is odd in any way.
5649	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
5650	*
5651	* @param pVM The cross context VM structure.
5652	* @param GCPhys The GC physical address to convert. Since this is only
5653	* used for filling the REM TLB, the A20 mask must be
5654	* applied before calling this API.
5655	* @param fWritable Whether write access is required.
5656	* @param ppv Where to store the pointer corresponding to GCPhys on
5657	* success.
5658	*/
5659	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
5660	{
5661	pgmLock(pVM);
5662	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
5663
5664	PPGMRAMRANGE pRam;
5665	PPGMPAGE pPage;
5666	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
5667	if (RT_SUCCESS(rc))
5668	{
5669	if (PGM_PAGE_IS_BALLOONED(pPage))
5670	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5671	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
5672	rc = VINF_SUCCESS;
5673	else
5674	{
5675	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
5676	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5677	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
5678	{
5679	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
5680	* in -norawr0 mode. */
5681	if (fWritable)
5682	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5683	}
5684	else
5685	{
5686	/* Temporarily disabled physical handler(s), since the recompiler
5687	doesn't get notified when it's reset we'll have to pretend it's
5688	operating normally. */
5689	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
5690	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5691	else
5692	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5693	}
5694	}
5695	if (RT_SUCCESS(rc))
5696	{
5697	int rc2;
5698
5699	/* Make sure what we return is writable. */
5700	if (fWritable)
5701	switch (PGM_PAGE_GET_STATE(pPage))
5702	{
5703	case PGM_PAGE_STATE_ALLOCATED:
5704	break;
5705	case PGM_PAGE_STATE_BALLOONED:
5706	AssertFailed();
5707	break;
5708	case PGM_PAGE_STATE_ZERO:
5709	case PGM_PAGE_STATE_SHARED:
5710	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
5711	break;
5712	RT_FALL_THRU();
5713	case PGM_PAGE_STATE_WRITE_MONITORED:
5714	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
5715	AssertLogRelRCReturn(rc2, rc2);
5716	break;
5717	}
5718
5719	/* Get a ring-3 mapping of the address. */
5720	PPGMPAGER3MAPTLBE pTlbe;
5721	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
5722	AssertLogRelRCReturn(rc2, rc2);
5723	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
5724	/** @todo mapping/locking hell; this isn't horribly efficient since
5725	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
5726
5727	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
5728	}
5729	else
5730	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
5731
5732	/* else: handler catching all access, no pointer returned. */
5733	}
5734	else
5735	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
5736
5737	pgmUnlock(pVM);
5738	return rc;
5739	}
5740

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 80090

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