PGMPhys.cpp@ 60380

Last change on this file since 60380 was 58782, checked in by vboxsync, 9 years ago
PGM: we've always got pvOriginal now, no need to check here.
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1	/* $Id: PGMPhys.cpp 58782 2015-11-19 22:34:17Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/iom.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/stam.h>
27	#ifdef VBOX_WITH_REM
28	# include <VBox/vmm/rem.h>
29	#endif
30	#include <VBox/vmm/pdmdev.h>
31	#include "PGMInternal.h"
32	#include <VBox/vmm/vm.h>
33	#include <VBox/vmm/uvm.h>
34	#include "PGMInline.h"
35	#include <VBox/sup.h>
36	#include <VBox/param.h>
37	#include <VBox/err.h>
38	#include <VBox/log.h>
39	#include <iprt/assert.h>
40	#include <iprt/alloc.h>
41	#include <iprt/asm.h>
42	#ifdef VBOX_STRICT
43	# include <iprt/crc.h>
44	#endif
45	#include <iprt/thread.h>
46	#include <iprt/string.h>
47	#include <iprt/system.h>
48
49
50	/*********************************************************************************************************************************
51	* Defined Constants And Macros *
52	*********************************************************************************************************************************/
53	/** The number of pages to free in one batch. */
54	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
55
56
57	/*
58	* PGMR3PhysReadU8-64
59	* PGMR3PhysWriteU8-64
60	*/
61	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
62	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
63	#define PGMPHYS_DATASIZE 1
64	#define PGMPHYS_DATATYPE uint8_t
65	#include "PGMPhysRWTmpl.h"
66
67	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
68	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
69	#define PGMPHYS_DATASIZE 2
70	#define PGMPHYS_DATATYPE uint16_t
71	#include "PGMPhysRWTmpl.h"
72
73	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
74	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
75	#define PGMPHYS_DATASIZE 4
76	#define PGMPHYS_DATATYPE uint32_t
77	#include "PGMPhysRWTmpl.h"
78
79	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
80	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
81	#define PGMPHYS_DATASIZE 8
82	#define PGMPHYS_DATATYPE uint64_t
83	#include "PGMPhysRWTmpl.h"
84
85
86	/**
87	* EMT worker for PGMR3PhysReadExternal.
88	*/
89	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
90	PGMACCESSORIGIN enmOrigin)
91	{
92	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
93	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
94	return VINF_SUCCESS;
95	}
96
97
98	/**
99	* Read from physical memory, external users.
100	*
101	* @returns VBox status code.
102	* @retval VINF_SUCCESS.
103	*
104	* @param pVM The cross context VM structure.
105	* @param GCPhys Physical address to read from.
106	* @param pvBuf Where to read into.
107	* @param cbRead How many bytes to read.
108	* @param enmOrigin Who is calling.
109	*
110	* @thread Any but EMTs.
111	*/
112	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
113	{
114	VM_ASSERT_OTHER_THREAD(pVM);
115
116	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
117	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
118
119	pgmLock(pVM);
120
121	/*
122	* Copy loop on ram ranges.
123	*/
124	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
125	for (;;)
126	{
127	/* Inside range or not? */
128	if (pRam && GCPhys >= pRam->GCPhys)
129	{
130	/*
131	* Must work our way thru this page by page.
132	*/
133	RTGCPHYS off = GCPhys - pRam->GCPhys;
134	while (off < pRam->cb)
135	{
136	unsigned iPage = off >> PAGE_SHIFT;
137	PPGMPAGE pPage = &pRam->aPages[iPage];
138
139	/*
140	* If the page has an ALL access handler, we'll have to
141	* delegate the job to EMT.
142	*/
143	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
144	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
145	{
146	pgmUnlock(pVM);
147
148	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
149	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
150	}
151	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
152
153	/*
154	* Simple stuff, go ahead.
155	*/
156	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
157	if (cb > cbRead)
158	cb = cbRead;
159	PGMPAGEMAPLOCK PgMpLck;
160	const void *pvSrc;
161	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
162	if (RT_SUCCESS(rc))
163	{
164	memcpy(pvBuf, pvSrc, cb);
165	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
166	}
167	else
168	{
169	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
170	pRam->GCPhys + off, pPage, rc));
171	memset(pvBuf, 0xff, cb);
172	}
173
174	/* next page */
175	if (cb >= cbRead)
176	{
177	pgmUnlock(pVM);
178	return VINF_SUCCESS;
179	}
180	cbRead -= cb;
181	off += cb;
182	GCPhys += cb;
183	pvBuf = (char *)pvBuf + cb;
184	} /* walk pages in ram range. */
185	}
186	else
187	{
188	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
189
190	/*
191	* Unassigned address space.
192	*/
193	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
194	if (cb >= cbRead)
195	{
196	memset(pvBuf, 0xff, cbRead);
197	break;
198	}
199	memset(pvBuf, 0xff, cb);
200
201	cbRead -= cb;
202	pvBuf = (char *)pvBuf + cb;
203	GCPhys += cb;
204	}
205
206	/* Advance range if necessary. */
207	while (pRam && GCPhys > pRam->GCPhysLast)
208	pRam = pRam->CTX_SUFF(pNext);
209	} /* Ram range walk */
210
211	pgmUnlock(pVM);
212
213	return VINF_SUCCESS;
214	}
215
216
217	/**
218	* EMT worker for PGMR3PhysWriteExternal.
219	*/
220	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
221	PGMACCESSORIGIN enmOrigin)
222	{
223	/** @todo VERR_EM_NO_MEMORY */
224	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
225	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
226	return VINF_SUCCESS;
227	}
228
229
230	/**
231	* Write to physical memory, external users.
232	*
233	* @returns VBox status code.
234	* @retval VINF_SUCCESS.
235	* @retval VERR_EM_NO_MEMORY.
236	*
237	* @param pVM The cross context VM structure.
238	* @param GCPhys Physical address to write to.
239	* @param pvBuf What to write.
240	* @param cbWrite How many bytes to write.
241	* @param enmOrigin Who is calling.
242	*
243	* @thread Any but EMTs.
244	*/
245	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
246	{
247	VM_ASSERT_OTHER_THREAD(pVM);
248
249	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
250	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
251	GCPhys, cbWrite, enmOrigin));
252	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
253	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
254
255	pgmLock(pVM);
256
257	/*
258	* Copy loop on ram ranges, stop when we hit something difficult.
259	*/
260	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
261	for (;;)
262	{
263	/* Inside range or not? */
264	if (pRam && GCPhys >= pRam->GCPhys)
265	{
266	/*
267	* Must work our way thru this page by page.
268	*/
269	RTGCPTR off = GCPhys - pRam->GCPhys;
270	while (off < pRam->cb)
271	{
272	RTGCPTR iPage = off >> PAGE_SHIFT;
273	PPGMPAGE pPage = &pRam->aPages[iPage];
274
275	/*
276	* Is the page problematic, we have to do the work on the EMT.
277	*
278	* Allocating writable pages and access handlers are
279	* problematic, write monitored pages are simple and can be
280	* dealt with here.
281	*/
282	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
283	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
284	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
285	{
286	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
287	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
288	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
289	else
290	{
291	pgmUnlock(pVM);
292
293	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
294	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
295	}
296	}
297	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
298
299	/*
300	* Simple stuff, go ahead.
301	*/
302	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
303	if (cb > cbWrite)
304	cb = cbWrite;
305	PGMPAGEMAPLOCK PgMpLck;
306	void *pvDst;
307	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
308	if (RT_SUCCESS(rc))
309	{
310	memcpy(pvDst, pvBuf, cb);
311	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
312	}
313	else
314	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
315	pRam->GCPhys + off, pPage, rc));
316
317	/* next page */
318	if (cb >= cbWrite)
319	{
320	pgmUnlock(pVM);
321	return VINF_SUCCESS;
322	}
323
324	cbWrite -= cb;
325	off += cb;
326	GCPhys += cb;
327	pvBuf = (const char *)pvBuf + cb;
328	} /* walk pages in ram range */
329	}
330	else
331	{
332	/*
333	* Unassigned address space, skip it.
334	*/
335	if (!pRam)
336	break;
337	size_t cb = pRam->GCPhys - GCPhys;
338	if (cb >= cbWrite)
339	break;
340	cbWrite -= cb;
341	pvBuf = (const char *)pvBuf + cb;
342	GCPhys += cb;
343	}
344
345	/* Advance range if necessary. */
346	while (pRam && GCPhys > pRam->GCPhysLast)
347	pRam = pRam->CTX_SUFF(pNext);
348	} /* Ram range walk */
349
350	pgmUnlock(pVM);
351	return VINF_SUCCESS;
352	}
353
354
355	/**
356	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
357	*
358	* @returns see PGMR3PhysGCPhys2CCPtrExternal
359	* @param pVM The cross context VM structure.
360	* @param pGCPhys Pointer to the guest physical address.
361	* @param ppv Where to store the mapping address.
362	* @param pLock Where to store the lock.
363	*/
364	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
365	{
366	/*
367	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
368	* an access handler after it succeeds.
369	*/
370	int rc = pgmLock(pVM);
371	AssertRCReturn(rc, rc);
372
373	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
374	if (RT_SUCCESS(rc))
375	{
376	PPGMPAGEMAPTLBE pTlbe;
377	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
378	AssertFatalRC(rc2);
379	PPGMPAGE pPage = pTlbe->pPage;
380	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
381	{
382	PGMPhysReleasePageMappingLock(pVM, pLock);
383	rc = VERR_PGM_PHYS_PAGE_RESERVED;
384	}
385	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
386	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
387	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
388	#endif
389	)
390	{
391	/* We must flush any corresponding pgm pool page here, otherwise we'll
392	* not be informed about writes and keep bogus gst->shw mappings around.
393	*/
394	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
395	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
396	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
397	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
398	}
399	}
400
401	pgmUnlock(pVM);
402	return rc;
403	}
404
405
406	/**
407	* Requests the mapping of a guest page into ring-3, external threads.
408	*
409	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
410	* release it.
411	*
412	* This API will assume your intention is to write to the page, and will
413	* therefore replace shared and zero pages. If you do not intend to modify the
414	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
415	*
416	* @returns VBox status code.
417	* @retval VINF_SUCCESS on success.
418	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
419	* backing or if the page has any active access handlers. The caller
420	* must fall back on using PGMR3PhysWriteExternal.
421	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
422	*
423	* @param pVM The cross context VM structure.
424	* @param GCPhys The guest physical address of the page that should be mapped.
425	* @param ppv Where to store the address corresponding to GCPhys.
426	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
427	*
428	* @remark Avoid calling this API from within critical sections (other than the
429	* PGM one) because of the deadlock risk when we have to delegating the
430	* task to an EMT.
431	* @thread Any.
432	*/
433	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
434	{
435	AssertPtr(ppv);
436	AssertPtr(pLock);
437
438	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
439
440	int rc = pgmLock(pVM);
441	AssertRCReturn(rc, rc);
442
443	/*
444	* Query the Physical TLB entry for the page (may fail).
445	*/
446	PPGMPAGEMAPTLBE pTlbe;
447	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
448	if (RT_SUCCESS(rc))
449	{
450	PPGMPAGE pPage = pTlbe->pPage;
451	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
452	rc = VERR_PGM_PHYS_PAGE_RESERVED;
453	else
454	{
455	/*
456	* If the page is shared, the zero page, or being write monitored
457	* it must be converted to an page that's writable if possible.
458	* We can only deal with write monitored pages here, the rest have
459	* to be on an EMT.
460	*/
461	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
462	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
463	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
464	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
465	#endif
466	)
467	{
468	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
469	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
470	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
471	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
472	#endif
473	)
474	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
475	else
476	{
477	pgmUnlock(pVM);
478
479	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
480	pVM, &GCPhys, ppv, pLock);
481	}
482	}
483
484	/*
485	* Now, just perform the locking and calculate the return address.
486	*/
487	PPGMPAGEMAP pMap = pTlbe->pMap;
488	if (pMap)
489	pMap->cRefs++;
490
491	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
492	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
493	{
494	if (cLocks == 0)
495	pVM->pgm.s.cWriteLockedPages++;
496	PGM_PAGE_INC_WRITE_LOCKS(pPage);
497	}
498	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
499	{
500	PGM_PAGE_INC_WRITE_LOCKS(pPage);
501	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
502	if (pMap)
503	pMap->cRefs++; /* Extra ref to prevent it from going away. */
504	}
505
506	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
507	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
508	pLock->pvMap = pMap;
509	}
510	}
511
512	pgmUnlock(pVM);
513	return rc;
514	}
515
516
517	/**
518	* Requests the mapping of a guest page into ring-3, external threads.
519	*
520	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
521	* release it.
522	*
523	* @returns VBox status code.
524	* @retval VINF_SUCCESS on success.
525	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
526	* backing or if the page as an active ALL access handler. The caller
527	* must fall back on using PGMPhysRead.
528	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
529	*
530	* @param pVM The cross context VM structure.
531	* @param GCPhys The guest physical address of the page that should be mapped.
532	* @param ppv Where to store the address corresponding to GCPhys.
533	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
534	*
535	* @remark Avoid calling this API from within critical sections (other than
536	* the PGM one) because of the deadlock risk.
537	* @thread Any.
538	*/
539	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
540	{
541	int rc = pgmLock(pVM);
542	AssertRCReturn(rc, rc);
543
544	/*
545	* Query the Physical TLB entry for the page (may fail).
546	*/
547	PPGMPAGEMAPTLBE pTlbe;
548	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
549	if (RT_SUCCESS(rc))
550	{
551	PPGMPAGE pPage = pTlbe->pPage;
552	#if 1
553	/* MMIO pages doesn't have any readable backing. */
554	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
555	rc = VERR_PGM_PHYS_PAGE_RESERVED;
556	#else
557	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
558	rc = VERR_PGM_PHYS_PAGE_RESERVED;
559	#endif
560	else
561	{
562	/*
563	* Now, just perform the locking and calculate the return address.
564	*/
565	PPGMPAGEMAP pMap = pTlbe->pMap;
566	if (pMap)
567	pMap->cRefs++;
568
569	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
570	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
571	{
572	if (cLocks == 0)
573	pVM->pgm.s.cReadLockedPages++;
574	PGM_PAGE_INC_READ_LOCKS(pPage);
575	}
576	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
577	{
578	PGM_PAGE_INC_READ_LOCKS(pPage);
579	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
580	if (pMap)
581	pMap->cRefs++; /* Extra ref to prevent it from going away. */
582	}
583
584	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
585	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
586	pLock->pvMap = pMap;
587	}
588	}
589
590	pgmUnlock(pVM);
591	return rc;
592	}
593
594
595	#define MAKE_LEAF(a_pNode) \
596	do { \
597	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
598	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
599	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
600	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
601	(a_pNode)->pLeftRC = NIL_RTRCPTR; \
602	(a_pNode)->pRightRC = NIL_RTRCPTR; \
603	} while (0)
604
605	#define INSERT_LEFT(a_pParent, a_pNode) \
606	do { \
607	(a_pParent)->pLeftR3 = (a_pNode); \
608	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
609	(a_pParent)->pLeftRC = (a_pNode)->pSelfRC; \
610	} while (0)
611	#define INSERT_RIGHT(a_pParent, a_pNode) \
612	do { \
613	(a_pParent)->pRightR3 = (a_pNode); \
614	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
615	(a_pParent)->pRightRC = (a_pNode)->pSelfRC; \
616	} while (0)
617
618
619	/**
620	* Recursive tree builder.
621	*
622	* @param ppRam Pointer to the iterator variable.
623	* @param iDepth The current depth. Inserts a leaf node if 0.
624	*/
625	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
626	{
627	PPGMRAMRANGE pRam;
628	if (iDepth <= 0)
629	{
630	/*
631	* Leaf node.
632	*/
633	pRam = *ppRam;
634	if (pRam)
635	{
636	*ppRam = pRam->pNextR3;
637	MAKE_LEAF(pRam);
638	}
639	}
640	else
641	{
642
643	/*
644	* Intermediate node.
645	*/
646	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
647
648	pRam = *ppRam;
649	if (!pRam)
650	return pLeft;
651	*ppRam = pRam->pNextR3;
652	MAKE_LEAF(pRam);
653	INSERT_LEFT(pRam, pLeft);
654
655	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
656	if (pRight)
657	INSERT_RIGHT(pRam, pRight);
658	}
659	return pRam;
660	}
661
662
663	/**
664	* Rebuilds the RAM range search trees.
665	*
666	* @param pVM The cross context VM structure.
667	*/
668	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
669	{
670
671	/*
672	* Create the reasonably balanced tree in a sequential fashion.
673	* For simplicity (laziness) we use standard recursion here.
674	*/
675	int iDepth = 0;
676	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
677	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
678	while (pRam)
679	{
680	PPGMRAMRANGE pLeft = pRoot;
681
682	pRoot = pRam;
683	pRam = pRam->pNextR3;
684	MAKE_LEAF(pRoot);
685	INSERT_LEFT(pRoot, pLeft);
686
687	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
688	if (pRight)
689	INSERT_RIGHT(pRoot, pRight);
690	/** @todo else: rotate the tree. */
691
692	iDepth++;
693	}
694
695	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
696	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
697	pVM->pgm.s.pRamRangeTreeRC = pRoot ? pRoot->pSelfRC : NIL_RTRCPTR;
698
699	#ifdef VBOX_STRICT
700	/*
701	* Verify that the above code works.
702	*/
703	unsigned cRanges = 0;
704	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
705	cRanges++;
706	Assert(cRanges > 0);
707
708	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
709	if ((1U << cMaxDepth) < cRanges)
710	cMaxDepth++;
711
712	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
713	{
714	unsigned cDepth = 0;
715	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
716	for (;;)
717	{
718	if (pRam == pRam2)
719	break;
720	Assert(pRam2);
721	if (pRam->GCPhys < pRam2->GCPhys)
722	pRam2 = pRam2->pLeftR3;
723	else
724	pRam2 = pRam2->pRightR3;
725	}
726	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
727	}
728	#endif /* VBOX_STRICT */
729	}
730
731	#undef MAKE_LEAF
732	#undef INSERT_LEFT
733	#undef INSERT_RIGHT
734
735	/**
736	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
737	*
738	* Called when anything was relocated.
739	*
740	* @param pVM The cross context VM structure.
741	*/
742	void pgmR3PhysRelinkRamRanges(PVM pVM)
743	{
744	PPGMRAMRANGE pCur;
745
746	#ifdef VBOX_STRICT
747	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
748	{
749	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
750	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
751	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
752	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
753	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
754	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
755	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
756	Assert( pCur2 == pCur
757	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
758	}
759	#endif
760
761	pCur = pVM->pgm.s.pRamRangesXR3;
762	if (pCur)
763	{
764	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
765	pVM->pgm.s.pRamRangesXRC = pCur->pSelfRC;
766
767	for (; pCur->pNextR3; pCur = pCur->pNextR3)
768	{
769	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
770	pCur->pNextRC = pCur->pNextR3->pSelfRC;
771	}
772
773	Assert(pCur->pNextR0 == NIL_RTR0PTR);
774	Assert(pCur->pNextRC == NIL_RTRCPTR);
775	}
776	else
777	{
778	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
779	Assert(pVM->pgm.s.pRamRangesXRC == NIL_RTRCPTR);
780	}
781	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
782
783	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
784	}
785
786
787	/**
788	* Links a new RAM range into the list.
789	*
790	* @param pVM The cross context VM structure.
791	* @param pNew Pointer to the new list entry.
792	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
793	*/
794	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
795	{
796	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
797	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
798	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
799
800	pgmLock(pVM);
801
802	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
803	pNew->pNextR3 = pRam;
804	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
805	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
806
807	if (pPrev)
808	{
809	pPrev->pNextR3 = pNew;
810	pPrev->pNextR0 = pNew->pSelfR0;
811	pPrev->pNextRC = pNew->pSelfRC;
812	}
813	else
814	{
815	pVM->pgm.s.pRamRangesXR3 = pNew;
816	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
817	pVM->pgm.s.pRamRangesXRC = pNew->pSelfRC;
818	}
819	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
820
821	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
822	pgmUnlock(pVM);
823	}
824
825
826	/**
827	* Unlink an existing RAM range from the list.
828	*
829	* @param pVM The cross context VM structure.
830	* @param pRam Pointer to the new list entry.
831	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
832	*/
833	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
834	{
835	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
836	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
837	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
838
839	pgmLock(pVM);
840
841	PPGMRAMRANGE pNext = pRam->pNextR3;
842	if (pPrev)
843	{
844	pPrev->pNextR3 = pNext;
845	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
846	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
847	}
848	else
849	{
850	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
851	pVM->pgm.s.pRamRangesXR3 = pNext;
852	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
853	pVM->pgm.s.pRamRangesXRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
854	}
855	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
856
857	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
858	pgmUnlock(pVM);
859	}
860
861
862	/**
863	* Unlink an existing RAM range from the list.
864	*
865	* @param pVM The cross context VM structure.
866	* @param pRam Pointer to the new list entry.
867	*/
868	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
869	{
870	pgmLock(pVM);
871
872	/* find prev. */
873	PPGMRAMRANGE pPrev = NULL;
874	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
875	while (pCur != pRam)
876	{
877	pPrev = pCur;
878	pCur = pCur->pNextR3;
879	}
880	AssertFatal(pCur);
881
882	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
883	pgmUnlock(pVM);
884	}
885
886
887	/**
888	* Frees a range of pages, replacing them with ZERO pages of the specified type.
889	*
890	* @returns VBox status code.
891	* @param pVM The cross context VM structure.
892	* @param pRam The RAM range in which the pages resides.
893	* @param GCPhys The address of the first page.
894	* @param GCPhysLast The address of the last page.
895	* @param uType The page type to replace then with.
896	*/
897	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
898	{
899	PGM_LOCK_ASSERT_OWNER(pVM);
900	uint32_t cPendingPages = 0;
901	PGMMFREEPAGESREQ pReq;
902	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
903	AssertLogRelRCReturn(rc, rc);
904
905	/* Iterate the pages. */
906	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
907	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
908	while (cPagesLeft-- > 0)
909	{
910	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
911	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
912
913	PGM_PAGE_SET_TYPE(pVM, pPageDst, uType);
914
915	GCPhys += PAGE_SIZE;
916	pPageDst++;
917	}
918
919	if (cPendingPages)
920	{
921	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
922	AssertLogRelRCReturn(rc, rc);
923	}
924	GMMR3FreePagesCleanup(pReq);
925
926	return rc;
927	}
928
929	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
930
931	/**
932	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
933	*
934	* This is only called on one of the EMTs while the other ones are waiting for
935	* it to complete this function.
936	*
937	* @returns VINF_SUCCESS (VBox strict status code).
938	* @param pVM The cross context VM structure.
939	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
940	* @param pvUser User parameter
941	*/
942	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
943	{
944	uintptr_t paUser = (uintptr_t )pvUser;
945	bool fInflate = !!paUser[0];
946	unsigned cPages = paUser[1];
947	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
948	uint32_t cPendingPages = 0;
949	PGMMFREEPAGESREQ pReq;
950	int rc;
951
952	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
953	pgmLock(pVM);
954
955	if (fInflate)
956	{
957	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
958	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
959
960	/* Replace pages with ZERO pages. */
961	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
962	if (RT_FAILURE(rc))
963	{
964	pgmUnlock(pVM);
965	AssertLogRelRC(rc);
966	return rc;
967	}
968
969	/* Iterate the pages. */
970	for (unsigned i = 0; i < cPages; i++)
971	{
972	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
973	if ( pPage == NULL
974	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
975	{
976	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
977	break;
978	}
979
980	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
981
982	/* Flush the shadow PT if this page was previously used as a guest page table. */
983	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
984
985	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
986	if (RT_FAILURE(rc))
987	{
988	pgmUnlock(pVM);
989	AssertLogRelRC(rc);
990	return rc;
991	}
992	Assert(PGM_PAGE_IS_ZERO(pPage));
993	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
994	}
995
996	if (cPendingPages)
997	{
998	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
999	if (RT_FAILURE(rc))
1000	{
1001	pgmUnlock(pVM);
1002	AssertLogRelRC(rc);
1003	return rc;
1004	}
1005	}
1006	GMMR3FreePagesCleanup(pReq);
1007	}
1008	else
1009	{
1010	/* Iterate the pages. */
1011	for (unsigned i = 0; i < cPages; i++)
1012	{
1013	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1014	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
1015
1016	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
1017
1018	Assert(PGM_PAGE_IS_BALLOONED(pPage));
1019
1020	/* Change back to zero page. */
1021	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1022	}
1023
1024	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
1025	}
1026
1027	/* Notify GMM about the balloon change. */
1028	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
1029	if (RT_SUCCESS(rc))
1030	{
1031	if (!fInflate)
1032	{
1033	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
1034	pVM->pgm.s.cBalloonedPages -= cPages;
1035	}
1036	else
1037	pVM->pgm.s.cBalloonedPages += cPages;
1038	}
1039
1040	pgmUnlock(pVM);
1041
1042	/* Flush the recompiler's TLB as well. */
1043	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1044	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1045
1046	AssertLogRelRC(rc);
1047	return rc;
1048	}
1049
1050
1051	/**
1052	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
1053	*
1054	* @returns VBox status code.
1055	* @param pVM The cross context VM structure.
1056	* @param fInflate Inflate or deflate memory balloon
1057	* @param cPages Number of pages to free
1058	* @param paPhysPage Array of guest physical addresses
1059	*/
1060	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1061	{
1062	uintptr_t paUser[3];
1063
1064	paUser[0] = fInflate;
1065	paUser[1] = cPages;
1066	paUser[2] = (uintptr_t)paPhysPage;
1067	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1068	AssertRC(rc);
1069
1070	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
1071	RTMemFree(paPhysPage);
1072	}
1073
1074	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
1075
1076	/**
1077	* Inflate or deflate a memory balloon
1078	*
1079	* @returns VBox status code.
1080	* @param pVM The cross context VM structure.
1081	* @param fInflate Inflate or deflate memory balloon
1082	* @param cPages Number of pages to free
1083	* @param paPhysPage Array of guest physical addresses
1084	*/
1085	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1086	{
1087	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
1088	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1089	int rc;
1090
1091	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
1092	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
1093
1094	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
1095	* In the SMP case we post a request packet to postpone the job.
1096	*/
1097	if (pVM->cCpus > 1)
1098	{
1099	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
1100	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
1101	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
1102
1103	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
1104
1105	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
1106	AssertRC(rc);
1107	}
1108	else
1109	{
1110	uintptr_t paUser[3];
1111
1112	paUser[0] = fInflate;
1113	paUser[1] = cPages;
1114	paUser[2] = (uintptr_t)paPhysPage;
1115	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1116	AssertRC(rc);
1117	}
1118	return rc;
1119
1120	#else
1121	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
1122	return VERR_NOT_IMPLEMENTED;
1123	#endif
1124	}
1125
1126
1127	/**
1128	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
1129	* physical RAM.
1130	*
1131	* This is only called on one of the EMTs while the other ones are waiting for
1132	* it to complete this function.
1133	*
1134	* @returns VINF_SUCCESS (VBox strict status code).
1135	* @param pVM The cross context VM structure.
1136	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1137	* @param pvUser User parameter, unused.
1138	*/
1139	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1140	{
1141	int rc = VINF_SUCCESS;
1142	NOREF(pvUser); NOREF(pVCpu);
1143
1144	pgmLock(pVM);
1145	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1146	pgmPoolResetDirtyPages(pVM);
1147	#endif
1148
1149	/** @todo pointless to write protect the physical page pointed to by RSP. */
1150
1151	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1152	pRam;
1153	pRam = pRam->CTX_SUFF(pNext))
1154	{
1155	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1156	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1157	{
1158	PPGMPAGE pPage = &pRam->aPages[iPage];
1159	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1160
1161	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1162	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1163	{
1164	/*
1165	* A RAM page.
1166	*/
1167	switch (PGM_PAGE_GET_STATE(pPage))
1168	{
1169	case PGM_PAGE_STATE_ALLOCATED:
1170	/** @todo Optimize this: Don't always re-enable write
1171	* monitoring if the page is known to be very busy. */
1172	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
1173	{
1174	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1175	/* Remember this dirty page for the next (memory) sync. */
1176	PGM_PAGE_SET_FT_DIRTY(pPage);
1177	}
1178
1179	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1180	break;
1181
1182	case PGM_PAGE_STATE_SHARED:
1183	AssertFailed();
1184	break;
1185
1186	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
1187	default:
1188	break;
1189	}
1190	}
1191	}
1192	}
1193	pgmR3PoolWriteProtectPages(pVM);
1194	PGM_INVL_ALL_VCPU_TLBS(pVM);
1195	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1196	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1197
1198	pgmUnlock(pVM);
1199	return rc;
1200	}
1201
1202	/**
1203	* Protect all physical RAM to monitor writes
1204	*
1205	* @returns VBox status code.
1206	* @param pVM The cross context VM structure.
1207	*/
1208	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
1209	{
1210	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1211
1212	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
1213	AssertRC(rc);
1214	return rc;
1215	}
1216
1217	/**
1218	* Enumerate all dirty FT pages.
1219	*
1220	* @returns VBox status code.
1221	* @param pVM The cross context VM structure.
1222	* @param pfnEnum Enumerate callback handler.
1223	* @param pvUser Enumerate callback handler parameter.
1224	*/
1225	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser)
1226	{
1227	int rc = VINF_SUCCESS;
1228
1229	pgmLock(pVM);
1230	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1231	pRam;
1232	pRam = pRam->CTX_SUFF(pNext))
1233	{
1234	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1235	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1236	{
1237	PPGMPAGE pPage = &pRam->aPages[iPage];
1238	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1239
1240	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1241	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1242	{
1243	/*
1244	* A RAM page.
1245	*/
1246	switch (PGM_PAGE_GET_STATE(pPage))
1247	{
1248	case PGM_PAGE_STATE_ALLOCATED:
1249	case PGM_PAGE_STATE_WRITE_MONITORED:
1250	if ( !PGM_PAGE_IS_WRITTEN_TO(pPage) /* not very recently updated? */
1251	&& PGM_PAGE_IS_FT_DIRTY(pPage))
1252	{
1253	unsigned cbPageRange = PAGE_SIZE;
1254	unsigned iPageClean = iPage + 1;
1255	RTGCPHYS GCPhysPage = pRam->GCPhys + iPage * PAGE_SIZE;
1256	uint8_t *pu8Page = NULL;
1257	PGMPAGEMAPLOCK Lock;
1258
1259	/* Find the next clean page, so we can merge adjacent dirty pages. */
1260	for (; iPageClean < cPages; iPageClean++)
1261	{
1262	PPGMPAGE pPageNext = &pRam->aPages[iPageClean];
1263	if ( RT_UNLIKELY(PGM_PAGE_GET_TYPE(pPageNext) != PGMPAGETYPE_RAM)
1264	\|\| PGM_PAGE_GET_STATE(pPageNext) != PGM_PAGE_STATE_ALLOCATED
1265	\|\| PGM_PAGE_IS_WRITTEN_TO(pPageNext)
1266	\|\| !PGM_PAGE_IS_FT_DIRTY(pPageNext)
1267	/* Crossing a chunk boundary? */
1268	\|\| (GCPhysPage & GMM_PAGEID_IDX_MASK) != ((GCPhysPage + cbPageRange) & GMM_PAGEID_IDX_MASK)
1269	)
1270	break;
1271
1272	cbPageRange += PAGE_SIZE;
1273	}
1274
1275	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhysPage, (const void **)&pu8Page, &Lock);
1276	if (RT_SUCCESS(rc))
1277	{
1278	/** @todo this is risky; the range might be changed, but little choice as the sync
1279	* costs a lot of time. */
1280	pgmUnlock(pVM);
1281	pfnEnum(pVM, GCPhysPage, pu8Page, cbPageRange, pvUser);
1282	pgmLock(pVM);
1283	PGMPhysReleasePageMappingLock(pVM, &Lock);
1284	}
1285
1286	for (iPage; iPage < iPageClean; iPage++)
1287	PGM_PAGE_CLEAR_FT_DIRTY(&pRam->aPages[iPage]);
1288
1289	iPage = iPageClean - 1;
1290	}
1291	break;
1292	}
1293	}
1294	}
1295	}
1296	pgmUnlock(pVM);
1297	return rc;
1298	}
1299
1300
1301	/**
1302	* Gets the number of ram ranges.
1303	*
1304	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1305	* @param pVM The cross context VM structure.
1306	*/
1307	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1308	{
1309	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1310
1311	pgmLock(pVM);
1312	uint32_t cRamRanges = 0;
1313	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1314	cRamRanges++;
1315	pgmUnlock(pVM);
1316	return cRamRanges;
1317	}
1318
1319
1320	/**
1321	* Get information about a range.
1322	*
1323	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1324	* @param pVM The cross context VM structure.
1325	* @param iRange The ordinal of the range.
1326	* @param pGCPhysStart Where to return the start of the range. Optional.
1327	* @param pGCPhysLast Where to return the address of the last byte in the
1328	* range. Optional.
1329	* @param ppszDesc Where to return the range description. Optional.
1330	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1331	* Optional.
1332	*/
1333	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1334	const char *ppszDesc, bool pfIsMmio)
1335	{
1336	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1337
1338	pgmLock(pVM);
1339	uint32_t iCurRange = 0;
1340	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1341	if (iCurRange == iRange)
1342	{
1343	if (pGCPhysStart)
1344	*pGCPhysStart = pCur->GCPhys;
1345	if (pGCPhysLast)
1346	*pGCPhysLast = pCur->GCPhysLast;
1347	if (ppszDesc)
1348	*ppszDesc = pCur->pszDesc;
1349	if (pfIsMmio)
1350	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1351
1352	pgmUnlock(pVM);
1353	return VINF_SUCCESS;
1354	}
1355	pgmUnlock(pVM);
1356	return VERR_OUT_OF_RANGE;
1357	}
1358
1359
1360	/**
1361	* Query the amount of free memory inside VMMR0
1362	*
1363	* @returns VBox status code.
1364	* @param pUVM The user mode VM handle.
1365	* @param pcbAllocMem Where to return the amount of memory allocated
1366	* by VMs.
1367	* @param pcbFreeMem Where to return the amount of memory that is
1368	* allocated from the host but not currently used
1369	* by any VMs.
1370	* @param pcbBallonedMem Where to return the sum of memory that is
1371	* currently ballooned by the VMs.
1372	* @param pcbSharedMem Where to return the amount of memory that is
1373	* currently shared.
1374	*/
1375	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
1376	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
1377	{
1378	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1379	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
1380
1381	uint64_t cAllocPages = 0;
1382	uint64_t cFreePages = 0;
1383	uint64_t cBalloonPages = 0;
1384	uint64_t cSharedPages = 0;
1385	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
1386	AssertRCReturn(rc, rc);
1387
1388	if (pcbAllocMem)
1389	pcbAllocMem = cAllocPages _4K;
1390
1391	if (pcbFreeMem)
1392	pcbFreeMem = cFreePages _4K;
1393
1394	if (pcbBallonedMem)
1395	pcbBallonedMem = cBalloonPages _4K;
1396
1397	if (pcbSharedMem)
1398	pcbSharedMem = cSharedPages _4K;
1399
1400	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
1401	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
1402	return VINF_SUCCESS;
1403	}
1404
1405
1406	/**
1407	* Query memory stats for the VM.
1408	*
1409	* @returns VBox status code.
1410	* @param pUVM The user mode VM handle.
1411	* @param pcbTotalMem Where to return total amount memory the VM may
1412	* possibly use.
1413	* @param pcbPrivateMem Where to return the amount of private memory
1414	* currently allocated.
1415	* @param pcbSharedMem Where to return the amount of actually shared
1416	* memory currently used by the VM.
1417	* @param pcbZeroMem Where to return the amount of memory backed by
1418	* zero pages.
1419	*
1420	* @remarks The total mem is normally larger than the sum of the three
1421	* components. There are two reasons for this, first the amount of
1422	* shared memory is what we're sure is shared instead of what could
1423	* possibly be shared with someone. Secondly, because the total may
1424	* include some pure MMIO pages that doesn't go into any of the three
1425	* sub-counts.
1426	*
1427	* @todo Why do we return reused shared pages instead of anything that could
1428	* potentially be shared? Doesn't this mean the first VM gets a much
1429	* lower number of shared pages?
1430	*/
1431	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
1432	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
1433	{
1434	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1435	PVM pVM = pUVM->pVM;
1436	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1437
1438	if (pcbTotalMem)
1439	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
1440
1441	if (pcbPrivateMem)
1442	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
1443
1444	if (pcbSharedMem)
1445	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
1446
1447	if (pcbZeroMem)
1448	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
1449
1450	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
1451	return VINF_SUCCESS;
1452	}
1453
1454
1455	/**
1456	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1457	*
1458	* @param pVM The cross context VM structure.
1459	* @param pNew The new RAM range.
1460	* @param GCPhys The address of the RAM range.
1461	* @param GCPhysLast The last address of the RAM range.
1462	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
1463	* if in HMA.
1464	* @param R0PtrNew Ditto for R0.
1465	* @param pszDesc The description.
1466	* @param pPrev The previous RAM range (for linking).
1467	*/
1468	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1469	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
1470	{
1471	/*
1472	* Initialize the range.
1473	*/
1474	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
1475	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
1476	pNew->GCPhys = GCPhys;
1477	pNew->GCPhysLast = GCPhysLast;
1478	pNew->cb = GCPhysLast - GCPhys + 1;
1479	pNew->pszDesc = pszDesc;
1480	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
1481	pNew->pvR3 = NULL;
1482	pNew->paLSPages = NULL;
1483
1484	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1485	RTGCPHYS iPage = cPages;
1486	while (iPage-- > 0)
1487	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1488
1489	/* Update the page count stats. */
1490	pVM->pgm.s.cZeroPages += cPages;
1491	pVM->pgm.s.cAllPages += cPages;
1492
1493	/*
1494	* Link it.
1495	*/
1496	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1497	}
1498
1499
1500	/**
1501	* Relocate a floating RAM range.
1502	*
1503	* @copydoc FNPGMRELOCATE
1504	*/
1505	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
1506	PGMRELOCATECALL enmMode, void *pvUser)
1507	{
1508	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1509	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1510	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
1511
1512	switch (enmMode)
1513	{
1514	case PGMRELOCATECALL_SUGGEST:
1515	return true;
1516
1517	case PGMRELOCATECALL_RELOCATE:
1518	{
1519	/*
1520	* Update myself, then relink all the ranges and flush the RC TLB.
1521	*/
1522	pgmLock(pVM);
1523
1524	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1525
1526	pgmR3PhysRelinkRamRanges(pVM);
1527	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
1528	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
1529
1530	pgmUnlock(pVM);
1531	return true;
1532	}
1533
1534	default:
1535	AssertFailedReturn(false);
1536	}
1537	}
1538
1539
1540	/**
1541	* PGMR3PhysRegisterRam worker that registers a high chunk.
1542	*
1543	* @returns VBox status code.
1544	* @param pVM The cross context VM structure.
1545	* @param GCPhys The address of the RAM.
1546	* @param cRamPages The number of RAM pages to register.
1547	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1548	* @param iChunk The chunk number.
1549	* @param pszDesc The RAM range description.
1550	* @param ppPrev Previous RAM range pointer. In/Out.
1551	*/
1552	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1553	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1554	PPGMRAMRANGE *ppPrev)
1555	{
1556	const char *pszDescChunk = iChunk == 0
1557	? pszDesc
1558	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1559	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1560
1561	/*
1562	* Allocate memory for the new chunk.
1563	*/
1564	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1565	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1566	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1567	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1568	void *pvChunk = NULL;
1569	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1570	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
1571	&R0PtrChunk,
1572	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
1573	HMIsEnabled(pVM) ? &R0PtrChunk : NULL,
1574	#else
1575	NULL,
1576	#endif
1577	paChunkPages);
1578	if (RT_SUCCESS(rc))
1579	{
1580	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
1581	Assert(R0PtrChunk != NIL_RTR0PTR);
1582	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
1583	if (!HMIsEnabled(pVM))
1584	R0PtrChunk = NIL_RTR0PTR;
1585	#else
1586	R0PtrChunk = (uintptr_t)pvChunk;
1587	#endif
1588	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1589
1590	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1591
1592	/*
1593	* Create a mapping and map the pages into it.
1594	* We push these in below the HMA.
1595	*/
1596	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1597	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1598	if (RT_SUCCESS(rc))
1599	{
1600	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1601
1602	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1603	RTGCPTR GCPtrPage = GCPtrChunk;
1604	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1605	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1606	if (RT_SUCCESS(rc))
1607	{
1608	/*
1609	* Ok, init and link the range.
1610	*/
1611	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1612	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1613	*ppPrev = pNew;
1614	}
1615	}
1616
1617	if (RT_FAILURE(rc))
1618	SUPR3PageFreeEx(pvChunk, cChunkPages);
1619	}
1620
1621	RTMemTmpFree(paChunkPages);
1622	return rc;
1623	}
1624
1625
1626	/**
1627	* Sets up a range RAM.
1628	*
1629	* This will check for conflicting registrations, make a resource
1630	* reservation for the memory (with GMM), and setup the per-page
1631	* tracking structures (PGMPAGE).
1632	*
1633	* @returns VBox status code.
1634	* @param pVM The cross context VM structure.
1635	* @param GCPhys The physical address of the RAM.
1636	* @param cb The size of the RAM.
1637	* @param pszDesc The description - not copied, so, don't free or change it.
1638	*/
1639	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1640	{
1641	/*
1642	* Validate input.
1643	*/
1644	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1645	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1646	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1647	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1648	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1649	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1650	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1651	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1652
1653	pgmLock(pVM);
1654
1655	/*
1656	* Find range location and check for conflicts.
1657	* (We don't lock here because the locking by EMT is only required on update.)
1658	*/
1659	PPGMRAMRANGE pPrev = NULL;
1660	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1661	while (pRam && GCPhysLast >= pRam->GCPhys)
1662	{
1663	if ( GCPhysLast >= pRam->GCPhys
1664	&& GCPhys <= pRam->GCPhysLast)
1665	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1666	GCPhys, GCPhysLast, pszDesc,
1667	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1668	VERR_PGM_RAM_CONFLICT);
1669
1670	/* next */
1671	pPrev = pRam;
1672	pRam = pRam->pNextR3;
1673	}
1674
1675	/*
1676	* Register it with GMM (the API bitches).
1677	*/
1678	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1679	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1680	if (RT_FAILURE(rc))
1681	{
1682	pgmUnlock(pVM);
1683	return rc;
1684	}
1685
1686	if ( GCPhys >= _4G
1687	&& cPages > 256)
1688	{
1689	/*
1690	* The PGMRAMRANGE structures for the high memory can get very big.
1691	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1692	* allocation size limit there and also to avoid being unable to find
1693	* guest mapping space for them, we split this memory up into 4MB in
1694	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1695	* mode.
1696	*
1697	* The first and last page of each mapping are guard pages and marked
1698	* not-present. So, we've got 4186112 and 16769024 bytes available for
1699	* the PGMRAMRANGE structure.
1700	*
1701	* Note! The sizes used here will influence the saved state.
1702	*/
1703	uint32_t cbChunk;
1704	uint32_t cPagesPerChunk;
1705	if (HMIsEnabled(pVM))
1706	{
1707	cbChunk = 16U*_1M;
1708	cPagesPerChunk = 1048048; /* max ~1048059 */
1709	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1710	}
1711	else
1712	{
1713	cbChunk = 4U*_1M;
1714	cPagesPerChunk = 261616; /* max ~261627 */
1715	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1716	}
1717	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1718
1719	RTGCPHYS cPagesLeft = cPages;
1720	RTGCPHYS GCPhysChunk = GCPhys;
1721	uint32_t iChunk = 0;
1722	while (cPagesLeft > 0)
1723	{
1724	uint32_t cPagesInChunk = cPagesLeft;
1725	if (cPagesInChunk > cPagesPerChunk)
1726	cPagesInChunk = cPagesPerChunk;
1727
1728	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1729	AssertRCReturn(rc, rc);
1730
1731	/* advance */
1732	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1733	cPagesLeft -= cPagesInChunk;
1734	iChunk++;
1735	}
1736	}
1737	else
1738	{
1739	/*
1740	* Allocate, initialize and link the new RAM range.
1741	*/
1742	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1743	PPGMRAMRANGE pNew;
1744	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1745	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1746
1747	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1748	}
1749	pgmPhysInvalidatePageMapTLB(pVM);
1750	pgmUnlock(pVM);
1751
1752	#ifdef VBOX_WITH_REM
1753	/*
1754	* Notify REM.
1755	*/
1756	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1757	#endif
1758
1759	return VINF_SUCCESS;
1760	}
1761
1762
1763	/**
1764	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1765	*
1766	* We do this late in the init process so that all the ROM and MMIO ranges have
1767	* been registered already and we don't go wasting memory on them.
1768	*
1769	* @returns VBox status code.
1770	*
1771	* @param pVM The cross context VM structure.
1772	*/
1773	int pgmR3PhysRamPreAllocate(PVM pVM)
1774	{
1775	Assert(pVM->pgm.s.fRamPreAlloc);
1776	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1777
1778	/*
1779	* Walk the RAM ranges and allocate all RAM pages, halt at
1780	* the first allocation error.
1781	*/
1782	uint64_t cPages = 0;
1783	uint64_t NanoTS = RTTimeNanoTS();
1784	pgmLock(pVM);
1785	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1786	{
1787	PPGMPAGE pPage = &pRam->aPages[0];
1788	RTGCPHYS GCPhys = pRam->GCPhys;
1789	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1790	while (cLeft-- > 0)
1791	{
1792	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1793	{
1794	switch (PGM_PAGE_GET_STATE(pPage))
1795	{
1796	case PGM_PAGE_STATE_ZERO:
1797	{
1798	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1799	if (RT_FAILURE(rc))
1800	{
1801	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1802	pgmUnlock(pVM);
1803	return rc;
1804	}
1805	cPages++;
1806	break;
1807	}
1808
1809	case PGM_PAGE_STATE_BALLOONED:
1810	case PGM_PAGE_STATE_ALLOCATED:
1811	case PGM_PAGE_STATE_WRITE_MONITORED:
1812	case PGM_PAGE_STATE_SHARED:
1813	/* nothing to do here. */
1814	break;
1815	}
1816	}
1817
1818	/* next */
1819	pPage++;
1820	GCPhys += PAGE_SIZE;
1821	}
1822	}
1823	pgmUnlock(pVM);
1824	NanoTS = RTTimeNanoTS() - NanoTS;
1825
1826	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1827	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1828	return VINF_SUCCESS;
1829	}
1830
1831
1832	/**
1833	* Checks shared page checksums.
1834	*
1835	* @param pVM The cross context VM structure.
1836	*/
1837	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
1838	{
1839	#ifdef VBOX_STRICT
1840	pgmLock(pVM);
1841
1842	if (pVM->pgm.s.cSharedPages > 0)
1843	{
1844	/*
1845	* Walk the ram ranges.
1846	*/
1847	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1848	{
1849	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1850	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1851
1852	while (iPage-- > 0)
1853	{
1854	PPGMPAGE pPage = &pRam->aPages[iPage];
1855	if (PGM_PAGE_IS_SHARED(pPage))
1856	{
1857	uint32_t u32Checksum = pPage->s.u2Unused0 \| ((uint32_t)pPage->s.u2Unused1 << 8);
1858	if (!u32Checksum)
1859	{
1860	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1861	void const *pvPage;
1862	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
1863	if (RT_SUCCESS(rc))
1864	{
1865	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
1866	# if 0
1867	AssertMsg((u32Checksum2 & UINT32_C(0x00000303)) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
1868	# else
1869	if ((u32Checksum2 & UINT32_C(0x00000303)) == u32Checksum)
1870	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1871	else
1872	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1873	# endif
1874	}
1875	else
1876	AssertRC(rc);
1877	}
1878	}
1879
1880	} /* for each page */
1881
1882	} /* for each ram range */
1883	}
1884
1885	pgmUnlock(pVM);
1886	#endif /* VBOX_STRICT */
1887	NOREF(pVM);
1888	}
1889
1890
1891	/**
1892	* Resets the physical memory state.
1893	*
1894	* ASSUMES that the caller owns the PGM lock.
1895	*
1896	* @returns VBox status code.
1897	* @param pVM The cross context VM structure.
1898	*/
1899	int pgmR3PhysRamReset(PVM pVM)
1900	{
1901	PGM_LOCK_ASSERT_OWNER(pVM);
1902
1903	/* Reset the memory balloon. */
1904	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1905	AssertRC(rc);
1906
1907	#ifdef VBOX_WITH_PAGE_SHARING
1908	/* Clear all registered shared modules. */
1909	pgmR3PhysAssertSharedPageChecksums(pVM);
1910	rc = GMMR3ResetSharedModules(pVM);
1911	AssertRC(rc);
1912	#endif
1913	/* Reset counters. */
1914	pVM->pgm.s.cReusedSharedPages = 0;
1915	pVM->pgm.s.cBalloonedPages = 0;
1916
1917	return VINF_SUCCESS;
1918	}
1919
1920
1921	/**
1922	* Resets (zeros) the RAM after all devices and components have been reset.
1923	*
1924	* ASSUMES that the caller owns the PGM lock.
1925	*
1926	* @returns VBox status code.
1927	* @param pVM The cross context VM structure.
1928	*/
1929	int pgmR3PhysRamZeroAll(PVM pVM)
1930	{
1931	PGM_LOCK_ASSERT_OWNER(pVM);
1932
1933	/*
1934	* We batch up pages that should be freed instead of calling GMM for
1935	* each and every one of them.
1936	*/
1937	uint32_t cPendingPages = 0;
1938	PGMMFREEPAGESREQ pReq;
1939	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1940	AssertLogRelRCReturn(rc, rc);
1941
1942	/*
1943	* Walk the ram ranges.
1944	*/
1945	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1946	{
1947	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1948	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1949
1950	#ifndef NO_RAM_RESET
1951	if (!pVM->pgm.s.fRamPreAlloc)
1952	#else
1953	if (0)
1954	#endif
1955	{
1956	/* Replace all RAM pages by ZERO pages. */
1957	while (iPage-- > 0)
1958	{
1959	PPGMPAGE pPage = &pRam->aPages[iPage];
1960	switch (PGM_PAGE_GET_TYPE(pPage))
1961	{
1962	case PGMPAGETYPE_RAM:
1963	/* Do not replace pages part of a 2 MB continuous range
1964	with zero pages, but zero them instead. */
1965	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
1966	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
1967	{
1968	void *pvPage;
1969	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1970	AssertLogRelRCReturn(rc, rc);
1971	ASMMemZeroPage(pvPage);
1972	}
1973	else if (PGM_PAGE_IS_BALLOONED(pPage))
1974	{
1975	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1976	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1977	}
1978	else if (!PGM_PAGE_IS_ZERO(pPage))
1979	{
1980	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1981	AssertLogRelRCReturn(rc, rc);
1982	}
1983	break;
1984
1985	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1986	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
1987	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
1988	true /fDoAccounting/);
1989	break;
1990
1991	case PGMPAGETYPE_MMIO2:
1992	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1993	case PGMPAGETYPE_ROM:
1994	case PGMPAGETYPE_MMIO:
1995	break;
1996	default:
1997	AssertFailed();
1998	}
1999	} /* for each page */
2000	}
2001	else
2002	{
2003	/* Zero the memory. */
2004	while (iPage-- > 0)
2005	{
2006	PPGMPAGE pPage = &pRam->aPages[iPage];
2007	switch (PGM_PAGE_GET_TYPE(pPage))
2008	{
2009	case PGMPAGETYPE_RAM:
2010	switch (PGM_PAGE_GET_STATE(pPage))
2011	{
2012	case PGM_PAGE_STATE_ZERO:
2013	break;
2014
2015	case PGM_PAGE_STATE_BALLOONED:
2016	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2017	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2018	break;
2019
2020	case PGM_PAGE_STATE_SHARED:
2021	case PGM_PAGE_STATE_WRITE_MONITORED:
2022	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2023	AssertLogRelRCReturn(rc, rc);
2024	/* no break */
2025
2026	case PGM_PAGE_STATE_ALLOCATED:
2027	{
2028	void *pvPage;
2029	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2030	AssertLogRelRCReturn(rc, rc);
2031	#ifndef NO_RAM_RESET
2032	ASMMemZeroPage(pvPage);
2033	#endif
2034	break;
2035	}
2036	}
2037	break;
2038
2039	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2040	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2041	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2042	true /fDoAccounting/);
2043	break;
2044
2045	case PGMPAGETYPE_MMIO2:
2046	case PGMPAGETYPE_ROM_SHADOW:
2047	case PGMPAGETYPE_ROM:
2048	case PGMPAGETYPE_MMIO:
2049	break;
2050	default:
2051	AssertFailed();
2052
2053	}
2054	} /* for each page */
2055	}
2056
2057	}
2058
2059	/*
2060	* Finish off any pages pending freeing.
2061	*/
2062	if (cPendingPages)
2063	{
2064	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2065	AssertLogRelRCReturn(rc, rc);
2066	}
2067	GMMR3FreePagesCleanup(pReq);
2068	return VINF_SUCCESS;
2069	}
2070
2071
2072	/**
2073	* Frees all RAM during VM termination
2074	*
2075	* ASSUMES that the caller owns the PGM lock.
2076	*
2077	* @returns VBox status code.
2078	* @param pVM The cross context VM structure.
2079	*/
2080	int pgmR3PhysRamTerm(PVM pVM)
2081	{
2082	PGM_LOCK_ASSERT_OWNER(pVM);
2083
2084	/* Reset the memory balloon. */
2085	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2086	AssertRC(rc);
2087
2088	#ifdef VBOX_WITH_PAGE_SHARING
2089	/*
2090	* Clear all registered shared modules.
2091	*/
2092	pgmR3PhysAssertSharedPageChecksums(pVM);
2093	rc = GMMR3ResetSharedModules(pVM);
2094	AssertRC(rc);
2095
2096	/*
2097	* Flush the handy pages updates to make sure no shared pages are hiding
2098	* in there. (No unlikely if the VM shuts down, apparently.)
2099	*/
2100	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2101	#endif
2102
2103	/*
2104	* We batch up pages that should be freed instead of calling GMM for
2105	* each and every one of them.
2106	*/
2107	uint32_t cPendingPages = 0;
2108	PGMMFREEPAGESREQ pReq;
2109	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2110	AssertLogRelRCReturn(rc, rc);
2111
2112	/*
2113	* Walk the ram ranges.
2114	*/
2115	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2116	{
2117	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2118	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2119
2120	while (iPage-- > 0)
2121	{
2122	PPGMPAGE pPage = &pRam->aPages[iPage];
2123	switch (PGM_PAGE_GET_TYPE(pPage))
2124	{
2125	case PGMPAGETYPE_RAM:
2126	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2127	/** @todo change this to explicitly free private pages here. */
2128	if (PGM_PAGE_IS_SHARED(pPage))
2129	{
2130	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2131	AssertLogRelRCReturn(rc, rc);
2132	}
2133	break;
2134
2135	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2136	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2137	case PGMPAGETYPE_MMIO2:
2138	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2139	case PGMPAGETYPE_ROM:
2140	case PGMPAGETYPE_MMIO:
2141	break;
2142	default:
2143	AssertFailed();
2144	}
2145	} /* for each page */
2146	}
2147
2148	/*
2149	* Finish off any pages pending freeing.
2150	*/
2151	if (cPendingPages)
2152	{
2153	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2154	AssertLogRelRCReturn(rc, rc);
2155	}
2156	GMMR3FreePagesCleanup(pReq);
2157	return VINF_SUCCESS;
2158	}
2159
2160
2161	/**
2162	* This is the interface IOM is using to register an MMIO region.
2163	*
2164	* It will check for conflicts and ensure that a RAM range structure
2165	* is present before calling the PGMR3HandlerPhysicalRegister API to
2166	* register the callbacks.
2167	*
2168	* @returns VBox status code.
2169	*
2170	* @param pVM The cross context VM structure.
2171	* @param GCPhys The start of the MMIO region.
2172	* @param cb The size of the MMIO region.
2173	* @param hType The physical access handler type registration.
2174	* @param pvUserR3 The user argument for R3.
2175	* @param pvUserR0 The user argument for R0.
2176	* @param pvUserRC The user argument for RC.
2177	* @param pszDesc The description of the MMIO region.
2178	*/
2179	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2180	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2181	{
2182	/*
2183	* Assert on some assumption.
2184	*/
2185	VM_ASSERT_EMT(pVM);
2186	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2187	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2188	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2189	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2190	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2191
2192	int rc = pgmLock(pVM);
2193	AssertRCReturn(rc, rc);
2194
2195	/*
2196	* Make sure there's a RAM range structure for the region.
2197	*/
2198	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2199	bool fRamExists = false;
2200	PPGMRAMRANGE pRamPrev = NULL;
2201	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2202	while (pRam && GCPhysLast >= pRam->GCPhys)
2203	{
2204	if ( GCPhysLast >= pRam->GCPhys
2205	&& GCPhys <= pRam->GCPhysLast)
2206	{
2207	/* Simplification: all within the same range. */
2208	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2209	&& GCPhysLast <= pRam->GCPhysLast,
2210	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2211	GCPhys, GCPhysLast, pszDesc,
2212	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2213	pgmUnlock(pVM),
2214	VERR_PGM_RAM_CONFLICT);
2215
2216	/* Check that it's all RAM or MMIO pages. */
2217	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2218	uint32_t cLeft = cb >> PAGE_SHIFT;
2219	while (cLeft-- > 0)
2220	{
2221	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2222	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2223	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2224	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2225	pgmUnlock(pVM),
2226	VERR_PGM_RAM_CONFLICT);
2227	pPage++;
2228	}
2229
2230	/* Looks good. */
2231	fRamExists = true;
2232	break;
2233	}
2234
2235	/* next */
2236	pRamPrev = pRam;
2237	pRam = pRam->pNextR3;
2238	}
2239	PPGMRAMRANGE pNew;
2240	if (fRamExists)
2241	{
2242	pNew = NULL;
2243
2244	/*
2245	* Make all the pages in the range MMIO/ZERO pages, freeing any
2246	* RAM pages currently mapped here. This might not be 100% correct
2247	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2248	*/
2249	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
2250	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
2251
2252	/* Force a PGM pool flush as guest ram references have been changed. */
2253	/** @todo not entirely SMP safe; assuming for now the guest takes
2254	* care of this internally (not touch mapped mmio while changing the
2255	* mapping). */
2256	PVMCPU pVCpu = VMMGetCpu(pVM);
2257	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2258	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2259	}
2260	else
2261	{
2262
2263	/*
2264	* No RAM range, insert an ad hoc one.
2265	*
2266	* Note that we don't have to tell REM about this range because
2267	* PGMHandlerPhysicalRegisterEx will do that for us.
2268	*/
2269	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2270
2271	const uint32_t cPages = cb >> PAGE_SHIFT;
2272	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
2273	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2274	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), pgmUnlock(pVM), rc);
2275
2276	/* Initialize the range. */
2277	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2278	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
2279	pNew->GCPhys = GCPhys;
2280	pNew->GCPhysLast = GCPhysLast;
2281	pNew->cb = cb;
2282	pNew->pszDesc = pszDesc;
2283	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2284	pNew->pvR3 = NULL;
2285	pNew->paLSPages = NULL;
2286
2287	uint32_t iPage = cPages;
2288	while (iPage-- > 0)
2289	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2290	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2291
2292	/* update the page count stats. */
2293	pVM->pgm.s.cPureMmioPages += cPages;
2294	pVM->pgm.s.cAllPages += cPages;
2295
2296	/* link it */
2297	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2298	}
2299
2300	/*
2301	* Register the access handler.
2302	*/
2303	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2304	if ( RT_FAILURE(rc)
2305	&& !fRamExists)
2306	{
2307	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2308	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2309
2310	/* remove the ad hoc range. */
2311	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2312	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2313	MMHyperFree(pVM, pRam);
2314	}
2315	pgmPhysInvalidatePageMapTLB(pVM);
2316
2317	pgmUnlock(pVM);
2318	return rc;
2319	}
2320
2321
2322	/**
2323	* This is the interface IOM is using to register an MMIO region.
2324	*
2325	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2326	* any ad hoc PGMRAMRANGE left behind.
2327	*
2328	* @returns VBox status code.
2329	* @param pVM The cross context VM structure.
2330	* @param GCPhys The start of the MMIO region.
2331	* @param cb The size of the MMIO region.
2332	*/
2333	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2334	{
2335	VM_ASSERT_EMT(pVM);
2336
2337	int rc = pgmLock(pVM);
2338	AssertRCReturn(rc, rc);
2339
2340	/*
2341	* First deregister the handler, then check if we should remove the ram range.
2342	*/
2343	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2344	if (RT_SUCCESS(rc))
2345	{
2346	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2347	PPGMRAMRANGE pRamPrev = NULL;
2348	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2349	while (pRam && GCPhysLast >= pRam->GCPhys)
2350	{
2351	/** @todo We're being a bit too careful here. rewrite. */
2352	if ( GCPhysLast == pRam->GCPhysLast
2353	&& GCPhys == pRam->GCPhys)
2354	{
2355	Assert(pRam->cb == cb);
2356
2357	/*
2358	* See if all the pages are dead MMIO pages.
2359	*/
2360	uint32_t const cPages = cb >> PAGE_SHIFT;
2361	bool fAllMMIO = true;
2362	uint32_t iPage = 0;
2363	uint32_t cLeft = cPages;
2364	while (cLeft-- > 0)
2365	{
2366	PPGMPAGE pPage = &pRam->aPages[iPage];
2367	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2368	/\|\| not-out-of-action later /)
2369	{
2370	fAllMMIO = false;
2371	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2372	break;
2373	}
2374	Assert( PGM_PAGE_IS_ZERO(pPage)
2375	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2376	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2377	pPage++;
2378	}
2379	if (fAllMMIO)
2380	{
2381	/*
2382	* Ad-hoc range, unlink and free it.
2383	*/
2384	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2385	GCPhys, GCPhysLast, pRam->pszDesc));
2386
2387	pVM->pgm.s.cAllPages -= cPages;
2388	pVM->pgm.s.cPureMmioPages -= cPages;
2389
2390	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2391	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2392	MMHyperFree(pVM, pRam);
2393	break;
2394	}
2395	}
2396
2397	/*
2398	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2399	*/
2400	if ( GCPhysLast >= pRam->GCPhys
2401	&& GCPhys <= pRam->GCPhysLast)
2402	{
2403	Assert(GCPhys >= pRam->GCPhys);
2404	Assert(GCPhysLast <= pRam->GCPhysLast);
2405
2406	/*
2407	* Turn the pages back into RAM pages.
2408	*/
2409	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2410	uint32_t cLeft = cb >> PAGE_SHIFT;
2411	while (cLeft--)
2412	{
2413	PPGMPAGE pPage = &pRam->aPages[iPage];
2414	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2415	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2416	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2417	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2418	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2419	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2420	}
2421	break;
2422	}
2423
2424	/* next */
2425	pRamPrev = pRam;
2426	pRam = pRam->pNextR3;
2427	}
2428	}
2429
2430	/* Force a PGM pool flush as guest ram references have been changed. */
2431	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2432	* this internally (not touch mapped mmio while changing the mapping). */
2433	PVMCPU pVCpu = VMMGetCpu(pVM);
2434	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2435	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2436
2437	pgmPhysInvalidatePageMapTLB(pVM);
2438	pgmPhysInvalidRamRangeTlbs(pVM);
2439	pgmUnlock(pVM);
2440	return rc;
2441	}
2442
2443
2444	/**
2445	* Locate a MMIO2 range.
2446	*
2447	* @returns Pointer to the MMIO2 range.
2448	* @param pVM The cross context VM structure.
2449	* @param pDevIns The device instance owning the region.
2450	* @param iRegion The region.
2451	*/
2452	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
2453	{
2454	/*
2455	* Search the list.
2456	*/
2457	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2458	if ( pCur->pDevInsR3 == pDevIns
2459	&& pCur->iRegion == iRegion)
2460	return pCur;
2461	return NULL;
2462	}
2463
2464
2465	/**
2466	* Allocate and register an MMIO2 region.
2467	*
2468	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2469	* associated with a device. It is also non-shared memory with a permanent
2470	* ring-3 mapping and page backing (presently).
2471	*
2472	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
2473	* the VM, in which case we'll drop the base memory pages. Presently we will
2474	* make no attempt to preserve anything that happens to be present in the base
2475	* memory that is replaced, this is of course incorrect but it's too much
2476	* effort.
2477	*
2478	* @returns VBox status code.
2479	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2480	* memory.
2481	* @retval VERR_ALREADY_EXISTS if the region already exists.
2482	*
2483	* @param pVM The cross context VM structure.
2484	* @param pDevIns The device instance owning the region.
2485	* @param iRegion The region number. If the MMIO2 memory is a PCI
2486	* I/O region this number has to be the number of that
2487	* region. Otherwise it can be any number safe
2488	* UINT8_MAX.
2489	* @param cb The size of the region. Must be page aligned.
2490	* @param fFlags Reserved for future use, must be zero.
2491	* @param ppv Where to store the pointer to the ring-3 mapping of
2492	* the memory.
2493	* @param pszDesc The description.
2494	*/
2495	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags,
2496	void *ppv, const char pszDesc)
2497	{
2498	/*
2499	* Validate input.
2500	*/
2501	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2502	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2503	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2504	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
2505	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2506	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2507	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
2508	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2509	AssertReturn(cb, VERR_INVALID_PARAMETER);
2510	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
2511
2512	const uint32_t cPages = cb >> PAGE_SHIFT;
2513	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
2514	AssertLogRelReturn(cPages <= PGM_MMIO2_MAX_PAGE_COUNT, VERR_NO_MEMORY);
2515
2516	/*
2517	* For the 2nd+ instance, mangle the description string so it's unique.
2518	*/
2519	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
2520	{
2521	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
2522	if (!pszDesc)
2523	return VERR_NO_MEMORY;
2524	}
2525
2526	/*
2527	* Allocate an MMIO2 range ID (not freed on failure).
2528	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID.
2529	*/
2530	pgmLock(pVM);
2531	uint8_t idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
2532	if (idMmio2 > PGM_MMIO2_MAX_RANGES)
2533	{
2534	pgmUnlock(pVM);
2535	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
2536	}
2537	pVM->pgm.s.cMmio2Regions = idMmio2;
2538	pgmUnlock(pVM);
2539
2540	/*
2541	* Try reserve and allocate the backing memory first as this is what is
2542	* most likely to fail.
2543	*/
2544	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
2545	if (RT_SUCCESS(rc))
2546	{
2547	void *pvPages;
2548	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
2549	if (RT_SUCCESS(rc))
2550	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
2551	if (RT_SUCCESS(rc))
2552	{
2553	memset(pvPages, 0, cPages * PAGE_SIZE);
2554
2555	/*
2556	* Create the MMIO2 range record for it.
2557	*/
2558	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
2559	PPGMMMIO2RANGE pNew;
2560	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2561	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
2562	if (RT_SUCCESS(rc))
2563	{
2564	pNew->pDevInsR3 = pDevIns;
2565	pNew->pvR3 = pvPages;
2566	//pNew->pNext = NULL;
2567	//pNew->fMapped = false;
2568	//pNew->fOverlapping = false;
2569	pNew->iRegion = iRegion;
2570	pNew->idSavedState = UINT8_MAX;
2571	pNew->idMmio2 = idMmio2;
2572	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2573	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
2574	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2575	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2576	pNew->RamRange.pszDesc = pszDesc;
2577	pNew->RamRange.cb = cb;
2578	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
2579	pNew->RamRange.pvR3 = pvPages;
2580	//pNew->RamRange.paLSPages = NULL;
2581
2582	uint32_t iPage = cPages;
2583	while (iPage-- > 0)
2584	{
2585	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
2586	paPages[iPage].Phys,
2587	PGM_MMIO2_PAGEID_MAKE(idMmio2, iPage),
2588	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
2589	}
2590
2591	/* update page count stats */
2592	pVM->pgm.s.cAllPages += cPages;
2593	pVM->pgm.s.cPrivatePages += cPages;
2594
2595	/*
2596	* Link it into the list.
2597	* Since there is no particular order, just push it.
2598	*/
2599	/** @todo we can save us the linked list now, just search the lookup table... */
2600	pgmLock(pVM);
2601	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
2602	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
2603	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
2604	pVM->pgm.s.pMmio2RangesR3 = pNew;
2605	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
2606	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = MMHyperCCToR0(pVM, pNew);
2607	pgmUnlock(pVM);
2608
2609	*ppv = pvPages;
2610	RTMemTmpFree(paPages);
2611	pgmPhysInvalidatePageMapTLB(pVM);
2612	return VINF_SUCCESS;
2613	}
2614
2615	SUPR3PageFreeEx(pvPages, cPages);
2616	}
2617	RTMemTmpFree(paPages);
2618	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
2619	}
2620	if (pDevIns->iInstance > 0)
2621	MMR3HeapFree((void *)pszDesc);
2622	return rc;
2623	}
2624
2625
2626	/**
2627	* Deregisters and frees an MMIO2 region.
2628	*
2629	* Any physical (and virtual) access handlers registered for the region must
2630	* be deregistered before calling this function.
2631	*
2632	* @returns VBox status code.
2633	* @param pVM The cross context VM structure.
2634	* @param pDevIns The device instance owning the region.
2635	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
2636	*/
2637	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
2638	{
2639	/*
2640	* Validate input.
2641	*/
2642	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2643	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2644	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
2645
2646	pgmLock(pVM);
2647	int rc = VINF_SUCCESS;
2648	unsigned cFound = 0;
2649	PPGMMMIO2RANGE pPrev = NULL;
2650	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
2651	while (pCur)
2652	{
2653	if ( pCur->pDevInsR3 == pDevIns
2654	&& ( iRegion == UINT32_MAX
2655	\|\| pCur->iRegion == iRegion))
2656	{
2657	cFound++;
2658
2659	/*
2660	* Unmap it if it's mapped.
2661	*/
2662	if (pCur->fMapped)
2663	{
2664	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
2665	AssertRC(rc2);
2666	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2667	rc = rc2;
2668	}
2669
2670	/*
2671	* Unlink it
2672	*/
2673	PPGMMMIO2RANGE pNext = pCur->pNextR3;
2674	if (pPrev)
2675	pPrev->pNextR3 = pNext;
2676	else
2677	pVM->pgm.s.pMmio2RangesR3 = pNext;
2678	pCur->pNextR3 = NULL;
2679
2680	uint8_t idMmio2 = pCur->idMmio2;
2681	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
2682	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
2683	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
2684
2685	/*
2686	* Free the memory.
2687	*/
2688	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
2689	AssertRC(rc2);
2690	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2691	rc = rc2;
2692
2693	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
2694	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
2695	AssertRC(rc2);
2696	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2697	rc = rc2;
2698
2699	/* we're leaking hyper memory here if done at runtime. */
2700	#ifdef VBOX_STRICT
2701	VMSTATE const enmState = VMR3GetState(pVM);
2702	AssertMsg( enmState == VMSTATE_POWERING_OFF
2703	\|\| enmState == VMSTATE_POWERING_OFF_LS
2704	\|\| enmState == VMSTATE_OFF
2705	\|\| enmState == VMSTATE_OFF_LS
2706	\|\| enmState == VMSTATE_DESTROYING
2707	\|\| enmState == VMSTATE_TERMINATED
2708	\|\| enmState == VMSTATE_CREATING
2709	, ("%s\n", VMR3GetStateName(enmState)));
2710	#endif
2711	/*rc = MMHyperFree(pVM, pCur);
2712	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
2713
2714
2715	/* update page count stats */
2716	pVM->pgm.s.cAllPages -= cPages;
2717	pVM->pgm.s.cPrivatePages -= cPages;
2718
2719	/* next */
2720	pCur = pNext;
2721	}
2722	else
2723	{
2724	pPrev = pCur;
2725	pCur = pCur->pNextR3;
2726	}
2727	}
2728	pgmPhysInvalidatePageMapTLB(pVM);
2729	pgmUnlock(pVM);
2730	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
2731	}
2732
2733
2734	/**
2735	* Maps a MMIO2 region.
2736	*
2737	* This is done when a guest / the bios / state loading changes the
2738	* PCI config. The replacing of base memory has the same restrictions
2739	* as during registration, of course.
2740	*
2741	* @returns VBox status code.
2742	*
2743	* @param pVM The cross context VM structure.
2744	* @param pDevIns The device instance owning the region.
2745	* @param iRegion The index of the registered region.
2746	* @param GCPhys The guest-physical address to be remapped.
2747	*/
2748	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2749	{
2750	/*
2751	* Validate input
2752	*/
2753	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2754	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2755	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2756	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2757	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2758	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2759
2760	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2761	AssertReturn(pCur, VERR_NOT_FOUND);
2762	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
2763	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
2764	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
2765
2766	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
2767	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2768
2769	/*
2770	* Find our location in the ram range list, checking for
2771	* restriction we don't bother implementing yet (partially overlapping).
2772	*/
2773	bool fRamExists = false;
2774	PPGMRAMRANGE pRamPrev = NULL;
2775	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2776	while (pRam && GCPhysLast >= pRam->GCPhys)
2777	{
2778	if ( GCPhys <= pRam->GCPhysLast
2779	&& GCPhysLast >= pRam->GCPhys)
2780	{
2781	/* completely within? */
2782	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2783	&& GCPhysLast <= pRam->GCPhysLast,
2784	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
2785	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
2786	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2787	VERR_PGM_RAM_CONFLICT);
2788	fRamExists = true;
2789	break;
2790	}
2791
2792	/* next */
2793	pRamPrev = pRam;
2794	pRam = pRam->pNextR3;
2795	}
2796	if (fRamExists)
2797	{
2798	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2799	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2800	while (cPagesLeft-- > 0)
2801	{
2802	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2803	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
2804	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
2805	VERR_PGM_RAM_CONFLICT);
2806	pPage++;
2807	}
2808	}
2809	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
2810	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
2811
2812	/*
2813	* Make the changes.
2814	*/
2815	pgmLock(pVM);
2816
2817	pCur->RamRange.GCPhys = GCPhys;
2818	pCur->RamRange.GCPhysLast = GCPhysLast;
2819	pCur->fMapped = true;
2820	pCur->fOverlapping = fRamExists;
2821
2822	if (fRamExists)
2823	{
2824	/** @todo use pgmR3PhysFreePageRange here. */
2825	uint32_t cPendingPages = 0;
2826	PGMMFREEPAGESREQ pReq;
2827	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2828	AssertLogRelRCReturn(rc, rc);
2829
2830	/* replace the pages, freeing all present RAM pages. */
2831	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2832	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2833	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2834	while (cPagesLeft-- > 0)
2835	{
2836	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
2837	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
2838
2839	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
2840	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
2841	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
2842	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
2843	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
2844	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
2845	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
2846	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
2847	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
2848
2849	pVM->pgm.s.cZeroPages--;
2850	GCPhys += PAGE_SIZE;
2851	pPageSrc++;
2852	pPageDst++;
2853	}
2854
2855	/* Flush physical page map TLB. */
2856	pgmPhysInvalidatePageMapTLB(pVM);
2857
2858	if (cPendingPages)
2859	{
2860	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2861	AssertLogRelRCReturn(rc, rc);
2862	}
2863	GMMR3FreePagesCleanup(pReq);
2864
2865	/* Force a PGM pool flush as guest ram references have been changed. */
2866	/** @todo not entirely SMP safe; assuming for now the guest takes care of
2867	* this internally (not touch mapped mmio while changing the mapping). */
2868	PVMCPU pVCpu = VMMGetCpu(pVM);
2869	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2870	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2871
2872	pgmUnlock(pVM);
2873	}
2874	else
2875	{
2876	RTGCPHYS cb = pCur->RamRange.cb;
2877
2878	/* Clear the tracking data of pages we're going to reactivate. */
2879	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
2880	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2881	while (cPagesLeft-- > 0)
2882	{
2883	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
2884	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
2885	pPageSrc++;
2886	}
2887
2888	/* link in the ram range */
2889	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
2890	pgmUnlock(pVM);
2891
2892	#ifdef VBOX_WITH_REM
2893	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
2894	#endif
2895	}
2896
2897	pgmPhysInvalidatePageMapTLB(pVM);
2898	return VINF_SUCCESS;
2899	}
2900
2901
2902	/**
2903	* Unmaps a MMIO2 region.
2904	*
2905	* This is done when a guest / the bios / state loading changes the
2906	* PCI config. The replacing of base memory has the same restrictions
2907	* as during registration, of course.
2908	*/
2909	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2910	{
2911	/*
2912	* Validate input
2913	*/
2914	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2915	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2916	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2917	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
2918	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
2919	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2920
2921	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2922	AssertReturn(pCur, VERR_NOT_FOUND);
2923	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
2924	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
2925	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
2926
2927	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
2928	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
2929
2930	/*
2931	* Unmap it.
2932	*/
2933	pgmLock(pVM);
2934
2935	#ifdef VBOX_WITH_REM
2936	RTGCPHYS GCPhysRangeREM;
2937	RTGCPHYS cbRangeREM;
2938	bool fInformREM;
2939	#endif
2940	if (pCur->fOverlapping)
2941	{
2942	/* Restore the RAM pages we've replaced. */
2943	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2944	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
2945	pRam = pRam->pNextR3;
2946
2947	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2948	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
2949	while (cPagesLeft-- > 0)
2950	{
2951	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
2952	pVM->pgm.s.cZeroPages++;
2953	pPageDst++;
2954	}
2955
2956	/* Flush physical page map TLB. */
2957	pgmPhysInvalidatePageMapTLB(pVM);
2958	#ifdef VBOX_WITH_REM
2959	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
2960	cbRangeREM = RTGCPHYS_MAX; /* ditto */
2961	fInformREM = false;
2962	#endif
2963	}
2964	else
2965	{
2966	#ifdef VBOX_WITH_REM
2967	GCPhysRangeREM = pCur->RamRange.GCPhys;
2968	cbRangeREM = pCur->RamRange.cb;
2969	fInformREM = true;
2970	#endif
2971	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
2972	}
2973
2974	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
2975	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
2976	pCur->fOverlapping = false;
2977	pCur->fMapped = false;
2978
2979	/* Force a PGM pool flush as guest ram references have been changed. */
2980	/** @todo not entirely SMP safe; assuming for now the guest takes care
2981	* of this internally (not touch mapped mmio while changing the
2982	* mapping). */
2983	PVMCPU pVCpu = VMMGetCpu(pVM);
2984	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2985	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2986
2987	pgmPhysInvalidatePageMapTLB(pVM);
2988	pgmPhysInvalidRamRangeTlbs(pVM);
2989	pgmUnlock(pVM);
2990
2991	#ifdef VBOX_WITH_REM
2992	if (fInformREM)
2993	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2994	#endif
2995
2996	return VINF_SUCCESS;
2997	}
2998
2999
3000	/**
3001	* Checks if the given address is an MMIO2 base address or not.
3002	*
3003	* @returns true/false accordingly.
3004	* @param pVM The cross context VM structure.
3005	* @param pDevIns The owner of the memory, optional.
3006	* @param GCPhys The address to check.
3007	*/
3008	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
3009	{
3010	/*
3011	* Validate input
3012	*/
3013	VM_ASSERT_EMT_RETURN(pVM, false);
3014	AssertPtrReturn(pDevIns, false);
3015	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
3016	AssertReturn(GCPhys != 0, false);
3017	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
3018
3019	/*
3020	* Search the list.
3021	*/
3022	pgmLock(pVM);
3023	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
3024	if (pCur->RamRange.GCPhys == GCPhys)
3025	{
3026	Assert(pCur->fMapped);
3027	pgmUnlock(pVM);
3028	return true;
3029	}
3030	pgmUnlock(pVM);
3031	return false;
3032	}
3033
3034
3035	/**
3036	* Gets the HC physical address of a page in the MMIO2 region.
3037	*
3038	* This is API is intended for MMHyper and shouldn't be called
3039	* by anyone else...
3040	*
3041	* @returns VBox status code.
3042	* @param pVM The cross context VM structure.
3043	* @param pDevIns The owner of the memory, optional.
3044	* @param iRegion The region.
3045	* @param off The page expressed an offset into the MMIO2 region.
3046	* @param pHCPhys Where to store the result.
3047	*/
3048	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
3049	{
3050	/*
3051	* Validate input
3052	*/
3053	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3054	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3055	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3056
3057	pgmLock(pVM);
3058	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
3059	AssertReturn(pCur, VERR_NOT_FOUND);
3060	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
3061
3062	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
3063	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3064	pgmUnlock(pVM);
3065	return VINF_SUCCESS;
3066	}
3067
3068
3069	/**
3070	* Maps a portion of an MMIO2 region into kernel space (host).
3071	*
3072	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
3073	* or the VM is terminated.
3074	*
3075	* @return VBox status code.
3076	*
3077	* @param pVM The cross context VM structure.
3078	* @param pDevIns The device owning the MMIO2 memory.
3079	* @param iRegion The region.
3080	* @param off The offset into the region. Must be page aligned.
3081	* @param cb The number of bytes to map. Must be page aligned.
3082	* @param pszDesc Mapping description.
3083	* @param pR0Ptr Where to store the R0 address.
3084	*/
3085	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
3086	const char *pszDesc, PRTR0PTR pR0Ptr)
3087	{
3088	/*
3089	* Validate input.
3090	*/
3091	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3092	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3093	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3094
3095	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
3096	AssertReturn(pCur, VERR_NOT_FOUND);
3097	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
3098	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
3099	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
3100	NOREF(pszDesc);
3101
3102	/*
3103	* Pass the request on to the support library/driver.
3104	*/
3105	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
3106
3107	return rc;
3108	}
3109
3110
3111	/**
3112	* Worker for PGMR3PhysRomRegister.
3113	*
3114	* This is here to simplify lock management, i.e. the caller does all the
3115	* locking and we can simply return without needing to remember to unlock
3116	* anything first.
3117	*
3118	* @returns VBox status code.
3119	* @param pVM The cross context VM structure.
3120	* @param pDevIns The device instance owning the ROM.
3121	* @param GCPhys First physical address in the range.
3122	* Must be page aligned!
3123	* @param cb The size of the range (in bytes).
3124	* Must be page aligned!
3125	* @param pvBinary Pointer to the binary data backing the ROM image.
3126	* @param cbBinary The size of the binary data pvBinary points to.
3127	* This must be less or equal to @a cb.
3128	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
3129	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
3130	* @param pszDesc Pointer to description string. This must not be freed.
3131	*/
3132	static int pgmR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
3133	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
3134	{
3135	/*
3136	* Validate input.
3137	*/
3138	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3139	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
3140	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
3141	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
3142	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3143	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
3144	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3145	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
3146	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
3147
3148	const uint32_t cPages = cb >> PAGE_SHIFT;
3149
3150	/*
3151	* Find the ROM location in the ROM list first.
3152	*/
3153	PPGMROMRANGE pRomPrev = NULL;
3154	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
3155	while (pRom && GCPhysLast >= pRom->GCPhys)
3156	{
3157	if ( GCPhys <= pRom->GCPhysLast
3158	&& GCPhysLast >= pRom->GCPhys)
3159	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
3160	GCPhys, GCPhysLast, pszDesc,
3161	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
3162	VERR_PGM_RAM_CONFLICT);
3163	/* next */
3164	pRomPrev = pRom;
3165	pRom = pRom->pNextR3;
3166	}
3167
3168	/*
3169	* Find the RAM location and check for conflicts.
3170	*
3171	* Conflict detection is a bit different than for RAM
3172	* registration since a ROM can be located within a RAM
3173	* range. So, what we have to check for is other memory
3174	* types (other than RAM that is) and that we don't span
3175	* more than one RAM range (layz).
3176	*/
3177	bool fRamExists = false;
3178	PPGMRAMRANGE pRamPrev = NULL;
3179	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3180	while (pRam && GCPhysLast >= pRam->GCPhys)
3181	{
3182	if ( GCPhys <= pRam->GCPhysLast
3183	&& GCPhysLast >= pRam->GCPhys)
3184	{
3185	/* completely within? */
3186	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
3187	&& GCPhysLast <= pRam->GCPhysLast,
3188	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
3189	GCPhys, GCPhysLast, pszDesc,
3190	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3191	VERR_PGM_RAM_CONFLICT);
3192	fRamExists = true;
3193	break;
3194	}
3195
3196	/* next */
3197	pRamPrev = pRam;
3198	pRam = pRam->pNextR3;
3199	}
3200	if (fRamExists)
3201	{
3202	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3203	uint32_t cPagesLeft = cPages;
3204	while (cPagesLeft-- > 0)
3205	{
3206	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3207	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
3208	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
3209	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
3210	Assert(PGM_PAGE_IS_ZERO(pPage));
3211	pPage++;
3212	}
3213	}
3214
3215	/*
3216	* Update the base memory reservation if necessary.
3217	*/
3218	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
3219	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
3220	cExtraBaseCost += cPages;
3221	if (cExtraBaseCost)
3222	{
3223	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
3224	if (RT_FAILURE(rc))
3225	return rc;
3226	}
3227
3228	/*
3229	* Allocate memory for the virgin copy of the RAM.
3230	*/
3231	PGMMALLOCATEPAGESREQ pReq;
3232	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
3233	AssertRCReturn(rc, rc);
3234
3235	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3236	{
3237	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
3238	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
3239	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
3240	}
3241
3242	rc = GMMR3AllocatePagesPerform(pVM, pReq);
3243	if (RT_FAILURE(rc))
3244	{
3245	GMMR3AllocatePagesCleanup(pReq);
3246	return rc;
3247	}
3248
3249	/*
3250	* Allocate the new ROM range and RAM range (if necessary).
3251	*/
3252	PPGMROMRANGE pRomNew;
3253	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
3254	if (RT_SUCCESS(rc))
3255	{
3256	PPGMRAMRANGE pRamNew = NULL;
3257	if (!fRamExists)
3258	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
3259	if (RT_SUCCESS(rc))
3260	{
3261	/*
3262	* Initialize and insert the RAM range (if required).
3263	*/
3264	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
3265	if (!fRamExists)
3266	{
3267	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
3268	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
3269	pRamNew->GCPhys = GCPhys;
3270	pRamNew->GCPhysLast = GCPhysLast;
3271	pRamNew->cb = cb;
3272	pRamNew->pszDesc = pszDesc;
3273	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
3274	pRamNew->pvR3 = NULL;
3275	pRamNew->paLSPages = NULL;
3276
3277	PPGMPAGE pPage = &pRamNew->aPages[0];
3278	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
3279	{
3280	PGM_PAGE_INIT(pPage,
3281	pReq->aPages[iPage].HCPhysGCPhys,
3282	pReq->aPages[iPage].idPage,
3283	PGMPAGETYPE_ROM,
3284	PGM_PAGE_STATE_ALLOCATED);
3285
3286	pRomPage->Virgin = *pPage;
3287	}
3288
3289	pVM->pgm.s.cAllPages += cPages;
3290	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
3291	}
3292	else
3293	{
3294	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3295	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
3296	{
3297	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_ROM);
3298	PGM_PAGE_SET_HCPHYS(pVM, pPage, pReq->aPages[iPage].HCPhysGCPhys);
3299	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
3300	PGM_PAGE_SET_PAGEID(pVM, pPage, pReq->aPages[iPage].idPage);
3301	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
3302	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
3303	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
3304
3305	pRomPage->Virgin = *pPage;
3306	}
3307
3308	pRamNew = pRam;
3309
3310	pVM->pgm.s.cZeroPages -= cPages;
3311	}
3312	pVM->pgm.s.cPrivatePages += cPages;
3313
3314	/* Flush physical page map TLB. */
3315	pgmPhysInvalidatePageMapTLB(pVM);
3316
3317
3318	/*
3319	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
3320	*
3321	* If it's shadowed we'll register the handler after the ROM notification
3322	* so we get the access handler callbacks that we should. If it isn't
3323	* shadowed we'll do it the other way around to make REM use the built-in
3324	* ROM behavior and not the handler behavior (which is to route all access
3325	* to PGM atm).
3326	*/
3327	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
3328	{
3329	#ifdef VBOX_WITH_REM
3330	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
3331	#endif
3332	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
3333	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
3334	pszDesc);
3335	}
3336	else
3337	{
3338	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
3339	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
3340	pszDesc);
3341	#ifdef VBOX_WITH_REM
3342	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
3343	#endif
3344	}
3345	if (RT_SUCCESS(rc))
3346	{
3347	/*
3348	* Copy the image over to the virgin pages.
3349	* This must be done after linking in the RAM range.
3350	*/
3351	size_t cbBinaryLeft = cbBinary;
3352	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
3353	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
3354	{
3355	void *pvDstPage;
3356	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
3357	if (RT_FAILURE(rc))
3358	{
3359	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
3360	break;
3361	}
3362	if (cbBinaryLeft >= PAGE_SIZE)
3363	{
3364	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
3365	cbBinaryLeft -= PAGE_SIZE;
3366	}
3367	else
3368	{
3369	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
3370	if (cbBinaryLeft > 0)
3371	{
3372	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
3373	cbBinaryLeft = 0;
3374	}
3375	}
3376	}
3377	if (RT_SUCCESS(rc))
3378	{
3379	/*
3380	* Initialize the ROM range.
3381	* Note that the Virgin member of the pages has already been initialized above.
3382	*/
3383	pRomNew->GCPhys = GCPhys;
3384	pRomNew->GCPhysLast = GCPhysLast;
3385	pRomNew->cb = cb;
3386	pRomNew->fFlags = fFlags;
3387	pRomNew->idSavedState = UINT8_MAX;
3388	pRomNew->cbOriginal = cbBinary;
3389	pRomNew->pszDesc = pszDesc;
3390	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
3391	? pvBinary : RTMemDup(pvBinary, cbBinary);
3392	if (pRomNew->pvOriginal)
3393	{
3394	for (unsigned iPage = 0; iPage < cPages; iPage++)
3395	{
3396	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
3397	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
3398	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
3399	}
3400
3401	/* update the page count stats for the shadow pages. */
3402	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
3403	{
3404	pVM->pgm.s.cZeroPages += cPages;
3405	pVM->pgm.s.cAllPages += cPages;
3406	}
3407
3408	/*
3409	* Insert the ROM range, tell REM and return successfully.
3410	*/
3411	pRomNew->pNextR3 = pRom;
3412	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
3413	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
3414
3415	if (pRomPrev)
3416	{
3417	pRomPrev->pNextR3 = pRomNew;
3418	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
3419	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
3420	}
3421	else
3422	{
3423	pVM->pgm.s.pRomRangesR3 = pRomNew;
3424	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
3425	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
3426	}
3427
3428	pgmPhysInvalidatePageMapTLB(pVM);
3429	GMMR3AllocatePagesCleanup(pReq);
3430	return VINF_SUCCESS;
3431	}
3432
3433	/* bail out */
3434	rc = VERR_NO_MEMORY;
3435	}
3436
3437	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
3438	AssertRC(rc2);
3439	}
3440
3441	if (!fRamExists)
3442	{
3443	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
3444	MMHyperFree(pVM, pRamNew);
3445	}
3446	}
3447	MMHyperFree(pVM, pRomNew);
3448	}
3449
3450	/** @todo Purge the mapping cache or something... */
3451	GMMR3FreeAllocatedPages(pVM, pReq);
3452	GMMR3AllocatePagesCleanup(pReq);
3453	return rc;
3454	}
3455
3456
3457	/**
3458	* Registers a ROM image.
3459	*
3460	* Shadowed ROM images requires double the amount of backing memory, so,
3461	* don't use that unless you have to. Shadowing of ROM images is process
3462	* where we can select where the reads go and where the writes go. On real
3463	* hardware the chipset provides means to configure this. We provide
3464	* PGMR3PhysProtectROM() for this purpose.
3465	*
3466	* A read-only copy of the ROM image will always be kept around while we
3467	* will allocate RAM pages for the changes on demand (unless all memory
3468	* is configured to be preallocated).
3469	*
3470	* @returns VBox status code.
3471	* @param pVM The cross context VM structure.
3472	* @param pDevIns The device instance owning the ROM.
3473	* @param GCPhys First physical address in the range.
3474	* Must be page aligned!
3475	* @param cb The size of the range (in bytes).
3476	* Must be page aligned!
3477	* @param pvBinary Pointer to the binary data backing the ROM image.
3478	* @param cbBinary The size of the binary data pvBinary points to.
3479	* This must be less or equal to @a cb.
3480	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
3481	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
3482	* @param pszDesc Pointer to description string. This must not be freed.
3483	*
3484	* @remark There is no way to remove the rom, automatically on device cleanup or
3485	* manually from the device yet. This isn't difficult in any way, it's
3486	* just not something we expect to be necessary for a while.
3487	*/
3488	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
3489	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
3490	{
3491	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
3492	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
3493	pgmLock(pVM);
3494	int rc = pgmR3PhysRomRegister(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
3495	pgmUnlock(pVM);
3496	return rc;
3497	}
3498
3499
3500	/**
3501	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
3502	* that the virgin part is untouched.
3503	*
3504	* This is done after the normal memory has been cleared.
3505	*
3506	* ASSUMES that the caller owns the PGM lock.
3507	*
3508	* @param pVM The cross context VM structure.
3509	*/
3510	int pgmR3PhysRomReset(PVM pVM)
3511	{
3512	PGM_LOCK_ASSERT_OWNER(pVM);
3513	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3514	{
3515	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
3516
3517	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
3518	{
3519	/*
3520	* Reset the physical handler.
3521	*/
3522	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
3523	AssertRCReturn(rc, rc);
3524
3525	/*
3526	* What we do with the shadow pages depends on the memory
3527	* preallocation option. If not enabled, we'll just throw
3528	* out all the dirty pages and replace them by the zero page.
3529	*/
3530	if (!pVM->pgm.s.fRamPreAlloc)
3531	{
3532	/* Free the dirty pages. */
3533	uint32_t cPendingPages = 0;
3534	PGMMFREEPAGESREQ pReq;
3535	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3536	AssertRCReturn(rc, rc);
3537
3538	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3539	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
3540	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
3541	{
3542	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
3543	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
3544	pRom->GCPhys + (iPage << PAGE_SHIFT));
3545	AssertLogRelRCReturn(rc, rc);
3546	}
3547
3548	if (cPendingPages)
3549	{
3550	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
3551	AssertLogRelRCReturn(rc, rc);
3552	}
3553	GMMR3FreePagesCleanup(pReq);
3554	}
3555	else
3556	{
3557	/* clear all the shadow pages. */
3558	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3559	{
3560	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
3561	continue;
3562	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
3563	void *pvDstPage;
3564	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
3565	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
3566	if (RT_FAILURE(rc))
3567	break;
3568	ASMMemZeroPage(pvDstPage);
3569	}
3570	AssertRCReturn(rc, rc);
3571	}
3572	}
3573
3574	/*
3575	* Restore the original ROM pages after a saved state load.
3576	* Also, in strict builds check that ROM pages remain unmodified.
3577	*/
3578	#ifndef VBOX_STRICT
3579	if (pVM->pgm.s.fRestoreRomPagesAtReset)
3580	#endif
3581	{
3582	size_t cbSrcLeft = pRom->cbOriginal;
3583	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
3584	uint32_t cRestored = 0;
3585	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
3586	{
3587	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
3588	void const *pvDstPage;
3589	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
3590	if (RT_FAILURE(rc))
3591	break;
3592
3593	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
3594	{
3595	if (pVM->pgm.s.fRestoreRomPagesAtReset)
3596	{
3597	void *pvDstPageW;
3598	rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPageW);
3599	AssertLogRelRCReturn(rc, rc);
3600	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
3601	cRestored++;
3602	}
3603	else
3604	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
3605	}
3606	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
3607	}
3608	if (cRestored > 0)
3609	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
3610	}
3611	}
3612
3613	/* Clear the ROM restore flag now as we only need to do this once after
3614	loading saved state. */
3615	pVM->pgm.s.fRestoreRomPagesAtReset = false;
3616
3617	return VINF_SUCCESS;
3618	}
3619
3620
3621	/**
3622	* Called by PGMR3Term to free resources.
3623	*
3624	* ASSUMES that the caller owns the PGM lock.
3625	*
3626	* @param pVM The cross context VM structure.
3627	*/
3628	void pgmR3PhysRomTerm(PVM pVM)
3629	{
3630	/*
3631	* Free the heap copy of the original bits.
3632	*/
3633	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3634	{
3635	if ( pRom->pvOriginal
3636	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
3637	{
3638	RTMemFree((void *)pRom->pvOriginal);
3639	pRom->pvOriginal = NULL;
3640	}
3641	}
3642	}
3643
3644
3645	/**
3646	* Change the shadowing of a range of ROM pages.
3647	*
3648	* This is intended for implementing chipset specific memory registers
3649	* and will not be very strict about the input. It will silently ignore
3650	* any pages that are not the part of a shadowed ROM.
3651	*
3652	* @returns VBox status code.
3653	* @retval VINF_PGM_SYNC_CR3
3654	*
3655	* @param pVM The cross context VM structure.
3656	* @param GCPhys Where to start. Page aligned.
3657	* @param cb How much to change. Page aligned.
3658	* @param enmProt The new ROM protection.
3659	*/
3660	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
3661	{
3662	/*
3663	* Check input
3664	*/
3665	if (!cb)
3666	return VINF_SUCCESS;
3667	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3668	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3669	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
3670	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3671	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
3672
3673	/*
3674	* Process the request.
3675	*/
3676	pgmLock(pVM);
3677	int rc = VINF_SUCCESS;
3678	bool fFlushTLB = false;
3679	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
3680	{
3681	if ( GCPhys <= pRom->GCPhysLast
3682	&& GCPhysLast >= pRom->GCPhys
3683	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
3684	{
3685	/*
3686	* Iterate the relevant pages and make necessary the changes.
3687	*/
3688	bool fChanges = false;
3689	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
3690	? pRom->cb >> PAGE_SHIFT
3691	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
3692	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
3693	iPage < cPages;
3694	iPage++)
3695	{
3696	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
3697	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
3698	{
3699	fChanges = true;
3700
3701	/* flush references to the page. */
3702	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT));
3703	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage,
3704	true /fFlushPTEs/, &fFlushTLB);
3705	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
3706	rc = rc2;
3707
3708	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
3709	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
3710
3711	pOld = pRamPage;
3712	pRamPage = pNew;
3713	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
3714	}
3715	pRomPage->enmProt = enmProt;
3716	}
3717
3718	/*
3719	* Reset the access handler if we made changes, no need
3720	* to optimize this.
3721	*/
3722	if (fChanges)
3723	{
3724	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
3725	if (RT_FAILURE(rc2))
3726	{
3727	pgmUnlock(pVM);
3728	AssertRC(rc);
3729	return rc2;
3730	}
3731	}
3732
3733	/* Advance - cb isn't updated. */
3734	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
3735	}
3736	}
3737	pgmUnlock(pVM);
3738	if (fFlushTLB)
3739	PGM_INVL_ALL_VCPU_TLBS(pVM);
3740
3741	return rc;
3742	}
3743
3744
3745	/**
3746	* Sets the Address Gate 20 state.
3747	*
3748	* @param pVCpu The cross context virtual CPU structure.
3749	* @param fEnable True if the gate should be enabled.
3750	* False if the gate should be disabled.
3751	*/
3752	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
3753	{
3754	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
3755	if (pVCpu->pgm.s.fA20Enabled != fEnable)
3756	{
3757	pVCpu->pgm.s.fA20Enabled = fEnable;
3758	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
3759	#ifdef VBOX_WITH_REM
3760	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
3761	#endif
3762	#ifdef PGM_WITH_A20
3763	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3764	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3765	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
3766	HMFlushTLB(pVCpu);
3767	#endif
3768	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
3769	}
3770	}
3771
3772
3773	/**
3774	* Tree enumeration callback for dealing with age rollover.
3775	* It will perform a simple compression of the current age.
3776	*/
3777	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
3778	{
3779	/* Age compression - ASSUMES iNow == 4. */
3780	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3781	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
3782	pChunk->iLastUsed = 3;
3783	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
3784	pChunk->iLastUsed = 2;
3785	else if (pChunk->iLastUsed)
3786	pChunk->iLastUsed = 1;
3787	else /* iLastUsed = 0 */
3788	pChunk->iLastUsed = 4;
3789
3790	NOREF(pvUser);
3791	return 0;
3792	}
3793
3794
3795	/**
3796	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3797	*/
3798	typedef struct PGMR3PHYSCHUNKUNMAPCB
3799	{
3800	PVM pVM; /*< Pointer to the VM. /
3801	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3802	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3803
3804
3805	/**
3806	* Callback used to find the mapping that's been unused for
3807	* the longest time.
3808	*/
3809	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
3810	{
3811	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3812	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
3813
3814	/*
3815	* Check for locks and compare when last used.
3816	*/
3817	if (pChunk->cRefs)
3818	return 0;
3819	if (pChunk->cPermRefs)
3820	return 0;
3821	if ( pArg->pChunk
3822	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
3823	return 0;
3824
3825	/*
3826	* Check that it's not in any of the TLBs.
3827	*/
3828	PVM pVM = pArg->pVM;
3829	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
3830	== pChunk->Core.Key)
3831	{
3832	pChunk = NULL;
3833	return 0;
3834	}
3835	#ifdef VBOX_STRICT
3836	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3837	{
3838	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
3839	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
3840	}
3841	#endif
3842
3843	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3844	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3845	return 0;
3846
3847	pArg->pChunk = pChunk;
3848	return 0;
3849	}
3850
3851
3852	/**
3853	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3854	*
3855	* The candidate will not be part of any TLBs, so no need to flush
3856	* anything afterwards.
3857	*
3858	* @returns Chunk id.
3859	* @param pVM The cross context VM structure.
3860	*/
3861	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3862	{
3863	PGM_LOCK_ASSERT_OWNER(pVM);
3864
3865	/*
3866	* Enumerate the age tree starting with the left most node.
3867	*/
3868	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3869	PGMR3PHYSCHUNKUNMAPCB Args;
3870	Args.pVM = pVM;
3871	Args.pChunk = NULL;
3872	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
3873	Assert(Args.pChunk);
3874	if (Args.pChunk)
3875	{
3876	Assert(Args.pChunk->cRefs == 0);
3877	Assert(Args.pChunk->cPermRefs == 0);
3878	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3879	return Args.pChunk->Core.Key;
3880	}
3881
3882	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
3883	return INT32_MAX;
3884	}
3885
3886
3887	/**
3888	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
3889	*
3890	* This is only called on one of the EMTs while the other ones are waiting for
3891	* it to complete this function.
3892	*
3893	* @returns VINF_SUCCESS (VBox strict status code).
3894	* @param pVM The cross context VM structure.
3895	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
3896	* @param pvUser User pointer. Unused
3897	*
3898	*/
3899	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
3900	{
3901	int rc = VINF_SUCCESS;
3902	pgmLock(pVM);
3903	NOREF(pVCpu); NOREF(pvUser);
3904
3905	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3906	{
3907	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
3908	/** @todo also not really efficient to unmap a chunk that contains PD
3909	* or PT pages. */
3910	pgmR3PoolClearAllRendezvous(pVM, &pVM->aCpus[0], NULL /* no need to flush the REM TLB as we already did that above */);
3911
3912	/*
3913	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
3914	*/
3915	GMMMAPUNMAPCHUNKREQ Req;
3916	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3917	Req.Hdr.cbReq = sizeof(Req);
3918	Req.pvR3 = NULL;
3919	Req.idChunkMap = NIL_GMM_CHUNKID;
3920	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3921	if (Req.idChunkUnmap != INT32_MAX)
3922	{
3923	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
3924	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3925	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
3926	if (RT_SUCCESS(rc))
3927	{
3928	/*
3929	* Remove the unmapped one.
3930	*/
3931	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3932	AssertRelease(pUnmappedChunk);
3933	AssertRelease(!pUnmappedChunk->cRefs);
3934	AssertRelease(!pUnmappedChunk->cPermRefs);
3935	pUnmappedChunk->pv = NULL;
3936	pUnmappedChunk->Core.Key = UINT32_MAX;
3937	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3938	MMR3HeapFree(pUnmappedChunk);
3939	#else
3940	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3941	#endif
3942	pVM->pgm.s.ChunkR3Map.c--;
3943	pVM->pgm.s.cUnmappedChunks++;
3944
3945	/*
3946	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
3947	*/
3948	/** @todo We should not flush chunks which include cr3 mappings. */
3949	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3950	{
3951	PPGMCPU pPGM = &pVM->aCpus[idCpu].pgm.s;
3952
3953	pPGM->pGst32BitPdR3 = NULL;
3954	pPGM->pGstPaePdptR3 = NULL;
3955	pPGM->pGstAmd64Pml4R3 = NULL;
3956	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3957	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
3958	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
3959	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
3960	#endif
3961	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
3962	{
3963	pPGM->apGstPaePDsR3[i] = NULL;
3964	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3965	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
3966	#endif
3967	}
3968
3969	/* Flush REM TLBs. */
3970	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3971	}
3972	#ifdef VBOX_WITH_REM
3973	/* Flush REM translation blocks. */
3974	REMFlushTBs(pVM);
3975	#endif
3976	}
3977	}
3978	}
3979	pgmUnlock(pVM);
3980	return rc;
3981	}
3982
3983	/**
3984	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
3985	*
3986	* @returns VBox status code.
3987	* @param pVM The cross context VM structure.
3988	*/
3989	void pgmR3PhysUnmapChunk(PVM pVM)
3990	{
3991	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
3992	AssertRC(rc);
3993	}
3994
3995
3996	/**
3997	* Maps the given chunk into the ring-3 mapping cache.
3998	*
3999	* This will call ring-0.
4000	*
4001	* @returns VBox status code.
4002	* @param pVM The cross context VM structure.
4003	* @param idChunk The chunk in question.
4004	* @param ppChunk Where to store the chunk tracking structure.
4005	*
4006	* @remarks Called from within the PGM critical section.
4007	* @remarks Can be called from any thread!
4008	*/
4009	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
4010	{
4011	int rc;
4012
4013	PGM_LOCK_ASSERT_OWNER(pVM);
4014
4015	/*
4016	* Move the chunk time forward.
4017	*/
4018	pVM->pgm.s.ChunkR3Map.iNow++;
4019	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
4020	{
4021	pVM->pgm.s.ChunkR3Map.iNow = 4;
4022	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
4023	}
4024
4025	/*
4026	* Allocate a new tracking structure first.
4027	*/
4028	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
4029	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
4030	#else
4031	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
4032	#endif
4033	AssertReturn(pChunk, VERR_NO_MEMORY);
4034	pChunk->Core.Key = idChunk;
4035	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
4036
4037	/*
4038	* Request the ring-0 part to map the chunk in question.
4039	*/
4040	GMMMAPUNMAPCHUNKREQ Req;
4041	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
4042	Req.Hdr.cbReq = sizeof(Req);
4043	Req.pvR3 = NULL;
4044	Req.idChunkMap = idChunk;
4045	Req.idChunkUnmap = NIL_GMM_CHUNKID;
4046
4047	/* Must be callable from any thread, so can't use VMMR3CallR0. */
4048	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
4049	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
4050	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
4051	if (RT_SUCCESS(rc))
4052	{
4053	pChunk->pv = Req.pvR3;
4054
4055	/*
4056	* If we're running out of virtual address space, then we should
4057	* unmap another chunk.
4058	*
4059	* Currently, an unmap operation requires that all other virtual CPUs
4060	* are idling and not by chance making use of the memory we're
4061	* unmapping. So, we create an async unmap operation here.
4062	*
4063	* Now, when creating or restoring a saved state this wont work very
4064	* well since we may want to restore all guest RAM + a little something.
4065	* So, we have to do the unmap synchronously. Fortunately for us
4066	* though, during these operations the other virtual CPUs are inactive
4067	* and it should be safe to do this.
4068	*/
4069	/** @todo Eventually we should lock all memory when used and do
4070	* map+unmap as one kernel call without any rendezvous or
4071	* other precautions. */
4072	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
4073	{
4074	switch (VMR3GetState(pVM))
4075	{
4076	case VMSTATE_LOADING:
4077	case VMSTATE_SAVING:
4078	{
4079	PVMCPU pVCpu = VMMGetCpu(pVM);
4080	if ( pVCpu
4081	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
4082	{
4083	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
4084	break;
4085	}
4086	/* fall thru */
4087	}
4088	default:
4089	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
4090	AssertRC(rc);
4091	break;
4092	}
4093	}
4094
4095	/*
4096	* Update the tree. We must do this after any unmapping to make sure
4097	* the chunk we're going to return isn't unmapped by accident.
4098	*/
4099	AssertPtr(Req.pvR3);
4100	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
4101	AssertRelease(fRc);
4102	pVM->pgm.s.ChunkR3Map.c++;
4103	pVM->pgm.s.cMappedChunks++;
4104	}
4105	else
4106	{
4107	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
4108	* should probably restrict ourselves on linux. */
4109	AssertRC(rc);
4110	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
4111	MMR3HeapFree(pChunk);
4112	#else
4113	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
4114	#endif
4115	pChunk = NULL;
4116	}
4117
4118	*ppChunk = pChunk;
4119	return rc;
4120	}
4121
4122
4123	/**
4124	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
4125	*
4126	* @returns see pgmR3PhysChunkMap.
4127	* @param pVM The cross context VM structure.
4128	* @param idChunk The chunk to map.
4129	*/
4130	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
4131	{
4132	PPGMCHUNKR3MAP pChunk;
4133	int rc;
4134
4135	pgmLock(pVM);
4136	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
4137	pgmUnlock(pVM);
4138	return rc;
4139	}
4140
4141
4142	/**
4143	* Invalidates the TLB for the ring-3 mapping cache.
4144	*
4145	* @param pVM The cross context VM structure.
4146	*/
4147	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
4148	{
4149	pgmLock(pVM);
4150	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
4151	{
4152	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
4153	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
4154	}
4155	/* The page map TLB references chunks, so invalidate that one too. */
4156	pgmPhysInvalidatePageMapTLB(pVM);
4157	pgmUnlock(pVM);
4158	}
4159
4160
4161	/**
4162	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE to allocate a large
4163	* (2MB) page for use with a nested paging PDE.
4164	*
4165	* @returns The following VBox status codes.
4166	* @retval VINF_SUCCESS on success.
4167	* @retval VINF_EM_NO_MEMORY if we're out of memory.
4168	*
4169	* @param pVM The cross context VM structure.
4170	* @param GCPhys GC physical start address of the 2 MB range
4171	*/
4172	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
4173	{
4174	#ifdef PGM_WITH_LARGE_PAGES
4175	uint64_t u64TimeStamp1, u64TimeStamp2;
4176
4177	pgmLock(pVM);
4178
4179	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
4180	u64TimeStamp1 = RTTimeMilliTS();
4181	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
4182	u64TimeStamp2 = RTTimeMilliTS();
4183	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
4184	if (RT_SUCCESS(rc))
4185	{
4186	Assert(pVM->pgm.s.cLargeHandyPages == 1);
4187
4188	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
4189	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
4190
4191	void *pv;
4192
4193	/* Map the large page into our address space.
4194	*
4195	* Note: assuming that within the 2 MB range:
4196	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
4197	* - user space mapping is continuous as well
4198	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
4199	*/
4200	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
4201	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", idPage, HCPhys, rc));
4202
4203	if (RT_SUCCESS(rc))
4204	{
4205	/*
4206	* Clear the pages.
4207	*/
4208	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
4209	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
4210	{
4211	ASMMemZeroPage(pv);
4212
4213	PPGMPAGE pPage;
4214	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
4215	AssertRC(rc);
4216
4217	Assert(PGM_PAGE_IS_ZERO(pPage));
4218	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRZPageReplaceZero);
4219	pVM->pgm.s.cZeroPages--;
4220
4221	/*
4222	* Do the PGMPAGE modifications.
4223	*/
4224	pVM->pgm.s.cPrivatePages++;
4225	PGM_PAGE_SET_HCPHYS(pVM, pPage, HCPhys);
4226	PGM_PAGE_SET_PAGEID(pVM, pPage, idPage);
4227	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
4228	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE);
4229	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
4230	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
4231
4232	/* Somewhat dirty assumption that page ids are increasing. */
4233	idPage++;
4234
4235	HCPhys += PAGE_SIZE;
4236	GCPhys += PAGE_SIZE;
4237
4238	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
4239
4240	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
4241	}
4242	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
4243
4244	/* Flush all TLBs. */
4245	PGM_INVL_ALL_VCPU_TLBS(pVM);
4246	pgmPhysInvalidatePageMapTLB(pVM);
4247	}
4248	pVM->pgm.s.cLargeHandyPages = 0;
4249	}
4250
4251	if (RT_SUCCESS(rc))
4252	{
4253	static uint32_t cTimeOut = 0;
4254	uint64_t u64TimeStampDelta = u64TimeStamp2 - u64TimeStamp1;
4255
4256	if (u64TimeStampDelta > 100)
4257	{
4258	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatLargePageOverflow);
4259	if ( ++cTimeOut > 10
4260	\|\| u64TimeStampDelta > 1000 /* more than one second forces an early retirement from allocating large pages. */)
4261	{
4262	/* If repeated attempts to allocate a large page takes more than 100 ms, then we fall back to normal 4k pages.
4263	* E.g. Vista 64 tries to move memory around, which takes a huge amount of time.
4264	*/
4265	LogRel(("PGMR3PhysAllocateLargePage: allocating large pages takes too long (last attempt %d ms; nr of timeouts %d); DISABLE\n", u64TimeStampDelta, cTimeOut));
4266	PGMSetLargePageUsage(pVM, false);
4267	}
4268	}
4269	else
4270	if (cTimeOut > 0)
4271	cTimeOut--;
4272	}
4273
4274	pgmUnlock(pVM);
4275	return rc;
4276	#else
4277	return VERR_NOT_IMPLEMENTED;
4278	#endif /* PGM_WITH_LARGE_PAGES */
4279	}
4280
4281
4282	/**
4283	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
4284	*
4285	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
4286	* signal and clear the out of memory condition. When contracted, this API is
4287	* used to try clear the condition when the user wants to resume.
4288	*
4289	* @returns The following VBox status codes.
4290	* @retval VINF_SUCCESS on success. FFs cleared.
4291	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
4292	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
4293	*
4294	* @param pVM The cross context VM structure.
4295	*
4296	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
4297	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
4298	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
4299	* handler.
4300	*/
4301	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
4302	{
4303	pgmLock(pVM);
4304
4305	/*
4306	* Allocate more pages, noting down the index of the first new page.
4307	*/
4308	uint32_t iClear = pVM->pgm.s.cHandyPages;
4309	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
4310	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
4311	int rcAlloc = VINF_SUCCESS;
4312	int rcSeed = VINF_SUCCESS;
4313	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
4314	while (rc == VERR_GMM_SEED_ME)
4315	{
4316	void *pvChunk;
4317	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
4318	if (RT_SUCCESS(rc))
4319	{
4320	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
4321	if (RT_FAILURE(rc))
4322	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
4323	}
4324	if (RT_SUCCESS(rc))
4325	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
4326	}
4327
4328	/* todo: we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
4329	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
4330	&& pVM->pgm.s.cHandyPages > 0)
4331	{
4332	/* Still handy pages left, so don't panic. */
4333	rc = VINF_SUCCESS;
4334	}
4335
4336	if (RT_SUCCESS(rc))
4337	{
4338	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
4339	Assert(pVM->pgm.s.cHandyPages > 0);
4340	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
4341	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
4342
4343	#ifdef VBOX_STRICT
4344	uint32_t i;
4345	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
4346	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
4347	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
4348	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
4349	break;
4350	if (i != pVM->pgm.s.cHandyPages)
4351	{
4352	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
4353	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
4354	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
4355	RTAssertMsg2Add(("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%\n", j,
4356	pVM->pgm.s.aHandyPages[j].idPage,
4357	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
4358	pVM->pgm.s.aHandyPages[j].idSharedPage,
4359	j == i ? " <---" : ""));
4360	RTAssertPanic();
4361	}
4362	#endif
4363	/*
4364	* Clear the pages.
4365	*/
4366	while (iClear < pVM->pgm.s.cHandyPages)
4367	{
4368	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
4369	void *pv;
4370	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
4371	AssertLogRelMsgBreak(RT_SUCCESS(rc),
4372	("%u/%u: idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n",
4373	iClear, pVM->pgm.s.cHandyPages, pPage->idPage, pPage->HCPhysGCPhys, rc));
4374	ASMMemZeroPage(pv);
4375	iClear++;
4376	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
4377	}
4378	}
4379	else
4380	{
4381	uint64_t cAllocPages, cMaxPages, cBalloonPages;
4382
4383	/*
4384	* We should never get here unless there is a genuine shortage of
4385	* memory (or some internal error). Flag the error so the VM can be
4386	* suspended ASAP and the user informed. If we're totally out of
4387	* handy pages we will return failure.
4388	*/
4389	/* Report the failure. */
4390	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
4391	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
4392	rc, rcAlloc, rcSeed,
4393	pVM->pgm.s.cHandyPages,
4394	pVM->pgm.s.cAllPages,
4395	pVM->pgm.s.cPrivatePages,
4396	pVM->pgm.s.cSharedPages,
4397	pVM->pgm.s.cZeroPages));
4398
4399	if (GMMR3QueryMemoryStats(pVM, &cAllocPages, &cMaxPages, &cBalloonPages) == VINF_SUCCESS)
4400	{
4401	LogRel(("GMM: Statistics:\n"
4402	" Allocated pages: %RX64\n"
4403	" Maximum pages: %RX64\n"
4404	" Ballooned pages: %RX64\n", cAllocPages, cMaxPages, cBalloonPages));
4405	}
4406
4407	if ( rc != VERR_NO_MEMORY
4408	&& rc != VERR_NO_PHYS_MEMORY
4409	&& rc != VERR_LOCK_FAILED)
4410	{
4411	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
4412	{
4413	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
4414	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
4415	pVM->pgm.s.aHandyPages[i].idSharedPage));
4416	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
4417	if (idPage != NIL_GMM_PAGEID)
4418	{
4419	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4420	pRam;
4421	pRam = pRam->pNextR3)
4422	{
4423	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
4424	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4425	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
4426	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
4427	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
4428	}
4429	}
4430	}
4431	}
4432
4433	/* Set the FFs and adjust rc. */
4434	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
4435	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
4436	if ( rc == VERR_NO_MEMORY
4437	\|\| rc == VERR_NO_PHYS_MEMORY
4438	\|\| rc == VERR_LOCK_FAILED)
4439	rc = VINF_EM_NO_MEMORY;
4440	}
4441
4442	pgmUnlock(pVM);
4443	return rc;
4444	}
4445
4446
4447	/**
4448	* Frees the specified RAM page and replaces it with the ZERO page.
4449	*
4450	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
4451	*
4452	* @param pVM The cross context VM structure.
4453	* @param pReq Pointer to the request.
4454	* @param pcPendingPages Where the number of pages waiting to be freed are
4455	* kept. This will normally be incremented.
4456	* @param pPage Pointer to the page structure.
4457	* @param GCPhys The guest physical address of the page, if applicable.
4458	*
4459	* @remarks The caller must own the PGM lock.
4460	*/
4461	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
4462	{
4463	/*
4464	* Assert sanity.
4465	*/
4466	PGM_LOCK_ASSERT_OWNER(pVM);
4467	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
4468	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
4469	{
4470	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
4471	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
4472	}
4473
4474	/** @todo What about ballooning of large pages??! */
4475	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
4476	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
4477
4478	if ( PGM_PAGE_IS_ZERO(pPage)
4479	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4480	return VINF_SUCCESS;
4481
4482	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
4483	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
4484	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
4485	\|\| idPage > GMM_PAGEID_LAST
4486	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
4487	{
4488	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
4489	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
4490	}
4491
4492	/* update page count stats. */
4493	if (PGM_PAGE_IS_SHARED(pPage))
4494	pVM->pgm.s.cSharedPages--;
4495	else
4496	pVM->pgm.s.cPrivatePages--;
4497	pVM->pgm.s.cZeroPages++;
4498
4499	/* Deal with write monitored pages. */
4500	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
4501	{
4502	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
4503	pVM->pgm.s.cWrittenToPages++;
4504	}
4505
4506	/*
4507	* pPage = ZERO page.
4508	*/
4509	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
4510	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
4511	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
4512	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4513	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
4514	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
4515
4516	/* Flush physical page map TLB entry. */
4517	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
4518
4519	/*
4520	* Make sure it's not in the handy page array.
4521	*/
4522	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
4523	{
4524	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
4525	{
4526	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
4527	break;
4528	}
4529	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
4530	{
4531	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
4532	break;
4533	}
4534	}
4535
4536	/*
4537	* Push it onto the page array.
4538	*/
4539	uint32_t iPage = *pcPendingPages;
4540	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
4541	*pcPendingPages += 1;
4542
4543	pReq->aPages[iPage].idPage = idPage;
4544
4545	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
4546	return VINF_SUCCESS;
4547
4548	/*
4549	* Flush the pages.
4550	*/
4551	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
4552	if (RT_SUCCESS(rc))
4553	{
4554	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4555	*pcPendingPages = 0;
4556	}
4557	return rc;
4558	}
4559
4560
4561	/**
4562	* Converts a GC physical address to a HC ring-3 pointer, with some
4563	* additional checks.
4564	*
4565	* @returns VBox status code.
4566	* @retval VINF_SUCCESS on success.
4567	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
4568	* access handler of some kind.
4569	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
4570	* accesses or is odd in any way.
4571	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
4572	*
4573	* @param pVM The cross context VM structure.
4574	* @param GCPhys The GC physical address to convert. Since this is only
4575	* used for filling the REM TLB, the A20 mask must be
4576	* applied before calling this API.
4577	* @param fWritable Whether write access is required.
4578	* @param ppv Where to store the pointer corresponding to GCPhys on
4579	* success.
4580	*/
4581	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
4582	{
4583	pgmLock(pVM);
4584	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
4585
4586	PPGMRAMRANGE pRam;
4587	PPGMPAGE pPage;
4588	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
4589	if (RT_SUCCESS(rc))
4590	{
4591	if (PGM_PAGE_IS_BALLOONED(pPage))
4592	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4593	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
4594	rc = VINF_SUCCESS;
4595	else
4596	{
4597	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
4598	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4599	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
4600	{
4601	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
4602	* in -norawr0 mode. */
4603	if (fWritable)
4604	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4605	}
4606	else
4607	{
4608	/* Temporarily disabled physical handler(s), since the recompiler
4609	doesn't get notified when it's reset we'll have to pretend it's
4610	operating normally. */
4611	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
4612	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4613	else
4614	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
4615	}
4616	}
4617	if (RT_SUCCESS(rc))
4618	{
4619	int rc2;
4620
4621	/* Make sure what we return is writable. */
4622	if (fWritable)
4623	switch (PGM_PAGE_GET_STATE(pPage))
4624	{
4625	case PGM_PAGE_STATE_ALLOCATED:
4626	break;
4627	case PGM_PAGE_STATE_BALLOONED:
4628	AssertFailed();
4629	break;
4630	case PGM_PAGE_STATE_ZERO:
4631	case PGM_PAGE_STATE_SHARED:
4632	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
4633	break;
4634	case PGM_PAGE_STATE_WRITE_MONITORED:
4635	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
4636	AssertLogRelRCReturn(rc2, rc2);
4637	break;
4638	}
4639
4640	/* Get a ring-3 mapping of the address. */
4641	PPGMPAGER3MAPTLBE pTlbe;
4642	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
4643	AssertLogRelRCReturn(rc2, rc2);
4644	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
4645	/** @todo mapping/locking hell; this isn't horribly efficient since
4646	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
4647
4648	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
4649	}
4650	else
4651	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
4652
4653	/* else: handler catching all access, no pointer returned. */
4654	}
4655	else
4656	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
4657
4658	pgmUnlock(pVM);
4659	return rc;
4660	}
4661

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 60380

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