PGMPhys.cpp@ 70951

Last change on this file since 70951 was 70951, checked in by vboxsync, 7 years ago
VMM: Added a bMainExecutionEngine member to the VM structure for use instead of fHMEnabled and fNEMEnabled. Changed a lot of HMIsEnabled invocations to use the new macros VM_IS_RAW_MODE_ENABLED and VM_IS_HM_OR_NEM_ENABLED. Eliminated fHMEnabledFixed. Fixed inverted test for raw-mode debug register sanity checking. Some other minor cleanups. [build fix]
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 199.6 KB

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1	/* $Id: PGMPhys.cpp 70951 2018-02-10 15:45:36Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/iem.h>
25	#include <VBox/vmm/iom.h>
26	#include <VBox/vmm/mm.h>
27	#include <VBox/vmm/stam.h>
28	#ifdef VBOX_WITH_REM
29	# include <VBox/vmm/rem.h>
30	#endif
31	#include <VBox/vmm/pdmdev.h>
32	#include "PGMInternal.h"
33	#include <VBox/vmm/vm.h>
34	#include <VBox/vmm/uvm.h>
35	#include "PGMInline.h"
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#ifdef VBOX_STRICT
44	# include <iprt/crc.h>
45	#endif
46	#include <iprt/thread.h>
47	#include <iprt/string.h>
48	#include <iprt/system.h>
49
50
51	/*********************************************************************************************************************************
52	* Defined Constants And Macros *
53	*********************************************************************************************************************************/
54	/** The number of pages to free in one batch. */
55	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
56
57
58	/*
59	* PGMR3PhysReadU8-64
60	* PGMR3PhysWriteU8-64
61	*/
62	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
63	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
64	#define PGMPHYS_DATASIZE 1
65	#define PGMPHYS_DATATYPE uint8_t
66	#include "PGMPhysRWTmpl.h"
67
68	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
69	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
70	#define PGMPHYS_DATASIZE 2
71	#define PGMPHYS_DATATYPE uint16_t
72	#include "PGMPhysRWTmpl.h"
73
74	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
75	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
76	#define PGMPHYS_DATASIZE 4
77	#define PGMPHYS_DATATYPE uint32_t
78	#include "PGMPhysRWTmpl.h"
79
80	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
81	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
82	#define PGMPHYS_DATASIZE 8
83	#define PGMPHYS_DATATYPE uint64_t
84	#include "PGMPhysRWTmpl.h"
85
86
87	/**
88	* EMT worker for PGMR3PhysReadExternal.
89	*/
90	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
91	PGMACCESSORIGIN enmOrigin)
92	{
93	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
94	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
95	return VINF_SUCCESS;
96	}
97
98
99	/**
100	* Read from physical memory, external users.
101	*
102	* @returns VBox status code.
103	* @retval VINF_SUCCESS.
104	*
105	* @param pVM The cross context VM structure.
106	* @param GCPhys Physical address to read from.
107	* @param pvBuf Where to read into.
108	* @param cbRead How many bytes to read.
109	* @param enmOrigin Who is calling.
110	*
111	* @thread Any but EMTs.
112	*/
113	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
114	{
115	VM_ASSERT_OTHER_THREAD(pVM);
116
117	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120	pgmLock(pVM);
121
122	/*
123	* Copy loop on ram ranges.
124	*/
125	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
126	for (;;)
127	{
128	/* Inside range or not? */
129	if (pRam && GCPhys >= pRam->GCPhys)
130	{
131	/*
132	* Must work our way thru this page by page.
133	*/
134	RTGCPHYS off = GCPhys - pRam->GCPhys;
135	while (off < pRam->cb)
136	{
137	unsigned iPage = off >> PAGE_SHIFT;
138	PPGMPAGE pPage = &pRam->aPages[iPage];
139
140	/*
141	* If the page has an ALL access handler, we'll have to
142	* delegate the job to EMT.
143	*/
144	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
145	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
146	{
147	pgmUnlock(pVM);
148
149	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
150	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
151	}
152	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
153
154	/*
155	* Simple stuff, go ahead.
156	*/
157	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
158	if (cb > cbRead)
159	cb = cbRead;
160	PGMPAGEMAPLOCK PgMpLck;
161	const void *pvSrc;
162	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
163	if (RT_SUCCESS(rc))
164	{
165	memcpy(pvBuf, pvSrc, cb);
166	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
167	}
168	else
169	{
170	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
171	pRam->GCPhys + off, pPage, rc));
172	memset(pvBuf, 0xff, cb);
173	}
174
175	/* next page */
176	if (cb >= cbRead)
177	{
178	pgmUnlock(pVM);
179	return VINF_SUCCESS;
180	}
181	cbRead -= cb;
182	off += cb;
183	GCPhys += cb;
184	pvBuf = (char *)pvBuf + cb;
185	} /* walk pages in ram range. */
186	}
187	else
188	{
189	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
190
191	/*
192	* Unassigned address space.
193	*/
194	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
195	if (cb >= cbRead)
196	{
197	memset(pvBuf, 0xff, cbRead);
198	break;
199	}
200	memset(pvBuf, 0xff, cb);
201
202	cbRead -= cb;
203	pvBuf = (char *)pvBuf + cb;
204	GCPhys += cb;
205	}
206
207	/* Advance range if necessary. */
208	while (pRam && GCPhys > pRam->GCPhysLast)
209	pRam = pRam->CTX_SUFF(pNext);
210	} /* Ram range walk */
211
212	pgmUnlock(pVM);
213
214	return VINF_SUCCESS;
215	}
216
217
218	/**
219	* EMT worker for PGMR3PhysWriteExternal.
220	*/
221	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
222	PGMACCESSORIGIN enmOrigin)
223	{
224	/** @todo VERR_EM_NO_MEMORY */
225	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
226	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
227	return VINF_SUCCESS;
228	}
229
230
231	/**
232	* Write to physical memory, external users.
233	*
234	* @returns VBox status code.
235	* @retval VINF_SUCCESS.
236	* @retval VERR_EM_NO_MEMORY.
237	*
238	* @param pVM The cross context VM structure.
239	* @param GCPhys Physical address to write to.
240	* @param pvBuf What to write.
241	* @param cbWrite How many bytes to write.
242	* @param enmOrigin Who is calling.
243	*
244	* @thread Any but EMTs.
245	*/
246	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
247	{
248	VM_ASSERT_OTHER_THREAD(pVM);
249
250	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
251	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
252	GCPhys, cbWrite, enmOrigin));
253	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
254	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
255
256	pgmLock(pVM);
257
258	/*
259	* Copy loop on ram ranges, stop when we hit something difficult.
260	*/
261	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
262	for (;;)
263	{
264	/* Inside range or not? */
265	if (pRam && GCPhys >= pRam->GCPhys)
266	{
267	/*
268	* Must work our way thru this page by page.
269	*/
270	RTGCPTR off = GCPhys - pRam->GCPhys;
271	while (off < pRam->cb)
272	{
273	RTGCPTR iPage = off >> PAGE_SHIFT;
274	PPGMPAGE pPage = &pRam->aPages[iPage];
275
276	/*
277	* Is the page problematic, we have to do the work on the EMT.
278	*
279	* Allocating writable pages and access handlers are
280	* problematic, write monitored pages are simple and can be
281	* dealt with here.
282	*/
283	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
284	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
285	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
286	{
287	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
288	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
289	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
290	else
291	{
292	pgmUnlock(pVM);
293
294	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
295	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
296	}
297	}
298	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
299
300	/*
301	* Simple stuff, go ahead.
302	*/
303	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
304	if (cb > cbWrite)
305	cb = cbWrite;
306	PGMPAGEMAPLOCK PgMpLck;
307	void *pvDst;
308	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
309	if (RT_SUCCESS(rc))
310	{
311	memcpy(pvDst, pvBuf, cb);
312	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
313	}
314	else
315	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
316	pRam->GCPhys + off, pPage, rc));
317
318	/* next page */
319	if (cb >= cbWrite)
320	{
321	pgmUnlock(pVM);
322	return VINF_SUCCESS;
323	}
324
325	cbWrite -= cb;
326	off += cb;
327	GCPhys += cb;
328	pvBuf = (const char *)pvBuf + cb;
329	} /* walk pages in ram range */
330	}
331	else
332	{
333	/*
334	* Unassigned address space, skip it.
335	*/
336	if (!pRam)
337	break;
338	size_t cb = pRam->GCPhys - GCPhys;
339	if (cb >= cbWrite)
340	break;
341	cbWrite -= cb;
342	pvBuf = (const char *)pvBuf + cb;
343	GCPhys += cb;
344	}
345
346	/* Advance range if necessary. */
347	while (pRam && GCPhys > pRam->GCPhysLast)
348	pRam = pRam->CTX_SUFF(pNext);
349	} /* Ram range walk */
350
351	pgmUnlock(pVM);
352	return VINF_SUCCESS;
353	}
354
355
356	/**
357	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
358	*
359	* @returns see PGMR3PhysGCPhys2CCPtrExternal
360	* @param pVM The cross context VM structure.
361	* @param pGCPhys Pointer to the guest physical address.
362	* @param ppv Where to store the mapping address.
363	* @param pLock Where to store the lock.
364	*/
365	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
366	{
367	/*
368	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
369	* an access handler after it succeeds.
370	*/
371	int rc = pgmLock(pVM);
372	AssertRCReturn(rc, rc);
373
374	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
375	if (RT_SUCCESS(rc))
376	{
377	PPGMPAGEMAPTLBE pTlbe;
378	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
379	AssertFatalRC(rc2);
380	PPGMPAGE pPage = pTlbe->pPage;
381	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
382	{
383	PGMPhysReleasePageMappingLock(pVM, pLock);
384	rc = VERR_PGM_PHYS_PAGE_RESERVED;
385	}
386	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
387	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
388	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
389	#endif
390	)
391	{
392	/* We must flush any corresponding pgm pool page here, otherwise we'll
393	* not be informed about writes and keep bogus gst->shw mappings around.
394	*/
395	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
396	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
397	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
398	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
399	}
400	}
401
402	pgmUnlock(pVM);
403	return rc;
404	}
405
406
407	/**
408	* Requests the mapping of a guest page into ring-3, external threads.
409	*
410	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
411	* release it.
412	*
413	* This API will assume your intention is to write to the page, and will
414	* therefore replace shared and zero pages. If you do not intend to modify the
415	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
416	*
417	* @returns VBox status code.
418	* @retval VINF_SUCCESS on success.
419	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
420	* backing or if the page has any active access handlers. The caller
421	* must fall back on using PGMR3PhysWriteExternal.
422	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
423	*
424	* @param pVM The cross context VM structure.
425	* @param GCPhys The guest physical address of the page that should be mapped.
426	* @param ppv Where to store the address corresponding to GCPhys.
427	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
428	*
429	* @remark Avoid calling this API from within critical sections (other than the
430	* PGM one) because of the deadlock risk when we have to delegating the
431	* task to an EMT.
432	* @thread Any.
433	*/
434	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
435	{
436	AssertPtr(ppv);
437	AssertPtr(pLock);
438
439	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
440
441	int rc = pgmLock(pVM);
442	AssertRCReturn(rc, rc);
443
444	/*
445	* Query the Physical TLB entry for the page (may fail).
446	*/
447	PPGMPAGEMAPTLBE pTlbe;
448	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
449	if (RT_SUCCESS(rc))
450	{
451	PPGMPAGE pPage = pTlbe->pPage;
452	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
453	rc = VERR_PGM_PHYS_PAGE_RESERVED;
454	else
455	{
456	/*
457	* If the page is shared, the zero page, or being write monitored
458	* it must be converted to an page that's writable if possible.
459	* We can only deal with write monitored pages here, the rest have
460	* to be on an EMT.
461	*/
462	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
463	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
464	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
465	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
466	#endif
467	)
468	{
469	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
470	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
471	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
472	&& !pgmPoolIsDirtyPage(pVM, GCPhys)
473	#endif
474	)
475	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
476	else
477	{
478	pgmUnlock(pVM);
479
480	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
481	pVM, &GCPhys, ppv, pLock);
482	}
483	}
484
485	/*
486	* Now, just perform the locking and calculate the return address.
487	*/
488	PPGMPAGEMAP pMap = pTlbe->pMap;
489	if (pMap)
490	pMap->cRefs++;
491
492	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
493	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
494	{
495	if (cLocks == 0)
496	pVM->pgm.s.cWriteLockedPages++;
497	PGM_PAGE_INC_WRITE_LOCKS(pPage);
498	}
499	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
500	{
501	PGM_PAGE_INC_WRITE_LOCKS(pPage);
502	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
503	if (pMap)
504	pMap->cRefs++; /* Extra ref to prevent it from going away. */
505	}
506
507	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
508	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
509	pLock->pvMap = pMap;
510	}
511	}
512
513	pgmUnlock(pVM);
514	return rc;
515	}
516
517
518	/**
519	* Requests the mapping of a guest page into ring-3, external threads.
520	*
521	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
522	* release it.
523	*
524	* @returns VBox status code.
525	* @retval VINF_SUCCESS on success.
526	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
527	* backing or if the page as an active ALL access handler. The caller
528	* must fall back on using PGMPhysRead.
529	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
530	*
531	* @param pVM The cross context VM structure.
532	* @param GCPhys The guest physical address of the page that should be mapped.
533	* @param ppv Where to store the address corresponding to GCPhys.
534	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
535	*
536	* @remark Avoid calling this API from within critical sections (other than
537	* the PGM one) because of the deadlock risk.
538	* @thread Any.
539	*/
540	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
541	{
542	int rc = pgmLock(pVM);
543	AssertRCReturn(rc, rc);
544
545	/*
546	* Query the Physical TLB entry for the page (may fail).
547	*/
548	PPGMPAGEMAPTLBE pTlbe;
549	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
550	if (RT_SUCCESS(rc))
551	{
552	PPGMPAGE pPage = pTlbe->pPage;
553	#if 1
554	/* MMIO pages doesn't have any readable backing. */
555	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
556	rc = VERR_PGM_PHYS_PAGE_RESERVED;
557	#else
558	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
559	rc = VERR_PGM_PHYS_PAGE_RESERVED;
560	#endif
561	else
562	{
563	/*
564	* Now, just perform the locking and calculate the return address.
565	*/
566	PPGMPAGEMAP pMap = pTlbe->pMap;
567	if (pMap)
568	pMap->cRefs++;
569
570	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
571	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
572	{
573	if (cLocks == 0)
574	pVM->pgm.s.cReadLockedPages++;
575	PGM_PAGE_INC_READ_LOCKS(pPage);
576	}
577	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
578	{
579	PGM_PAGE_INC_READ_LOCKS(pPage);
580	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
581	if (pMap)
582	pMap->cRefs++; /* Extra ref to prevent it from going away. */
583	}
584
585	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
586	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
587	pLock->pvMap = pMap;
588	}
589	}
590
591	pgmUnlock(pVM);
592	return rc;
593	}
594
595
596	#define MAKE_LEAF(a_pNode) \
597	do { \
598	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
599	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
600	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
601	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
602	(a_pNode)->pLeftRC = NIL_RTRCPTR; \
603	(a_pNode)->pRightRC = NIL_RTRCPTR; \
604	} while (0)
605
606	#define INSERT_LEFT(a_pParent, a_pNode) \
607	do { \
608	(a_pParent)->pLeftR3 = (a_pNode); \
609	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
610	(a_pParent)->pLeftRC = (a_pNode)->pSelfRC; \
611	} while (0)
612	#define INSERT_RIGHT(a_pParent, a_pNode) \
613	do { \
614	(a_pParent)->pRightR3 = (a_pNode); \
615	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
616	(a_pParent)->pRightRC = (a_pNode)->pSelfRC; \
617	} while (0)
618
619
620	/**
621	* Recursive tree builder.
622	*
623	* @param ppRam Pointer to the iterator variable.
624	* @param iDepth The current depth. Inserts a leaf node if 0.
625	*/
626	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
627	{
628	PPGMRAMRANGE pRam;
629	if (iDepth <= 0)
630	{
631	/*
632	* Leaf node.
633	*/
634	pRam = *ppRam;
635	if (pRam)
636	{
637	*ppRam = pRam->pNextR3;
638	MAKE_LEAF(pRam);
639	}
640	}
641	else
642	{
643
644	/*
645	* Intermediate node.
646	*/
647	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
648
649	pRam = *ppRam;
650	if (!pRam)
651	return pLeft;
652	*ppRam = pRam->pNextR3;
653	MAKE_LEAF(pRam);
654	INSERT_LEFT(pRam, pLeft);
655
656	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
657	if (pRight)
658	INSERT_RIGHT(pRam, pRight);
659	}
660	return pRam;
661	}
662
663
664	/**
665	* Rebuilds the RAM range search trees.
666	*
667	* @param pVM The cross context VM structure.
668	*/
669	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
670	{
671
672	/*
673	* Create the reasonably balanced tree in a sequential fashion.
674	* For simplicity (laziness) we use standard recursion here.
675	*/
676	int iDepth = 0;
677	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
678	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
679	while (pRam)
680	{
681	PPGMRAMRANGE pLeft = pRoot;
682
683	pRoot = pRam;
684	pRam = pRam->pNextR3;
685	MAKE_LEAF(pRoot);
686	INSERT_LEFT(pRoot, pLeft);
687
688	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
689	if (pRight)
690	INSERT_RIGHT(pRoot, pRight);
691	/** @todo else: rotate the tree. */
692
693	iDepth++;
694	}
695
696	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
697	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
698	pVM->pgm.s.pRamRangeTreeRC = pRoot ? pRoot->pSelfRC : NIL_RTRCPTR;
699
700	#ifdef VBOX_STRICT
701	/*
702	* Verify that the above code works.
703	*/
704	unsigned cRanges = 0;
705	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
706	cRanges++;
707	Assert(cRanges > 0);
708
709	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
710	if ((1U << cMaxDepth) < cRanges)
711	cMaxDepth++;
712
713	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
714	{
715	unsigned cDepth = 0;
716	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
717	for (;;)
718	{
719	if (pRam == pRam2)
720	break;
721	Assert(pRam2);
722	if (pRam->GCPhys < pRam2->GCPhys)
723	pRam2 = pRam2->pLeftR3;
724	else
725	pRam2 = pRam2->pRightR3;
726	}
727	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
728	}
729	#endif /* VBOX_STRICT */
730	}
731
732	#undef MAKE_LEAF
733	#undef INSERT_LEFT
734	#undef INSERT_RIGHT
735
736	/**
737	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
738	*
739	* Called when anything was relocated.
740	*
741	* @param pVM The cross context VM structure.
742	*/
743	void pgmR3PhysRelinkRamRanges(PVM pVM)
744	{
745	PPGMRAMRANGE pCur;
746
747	#ifdef VBOX_STRICT
748	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
749	{
750	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
751	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
752	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
753	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
754	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
755	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
756	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
757	Assert( pCur2 == pCur
758	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
759	}
760	#endif
761
762	pCur = pVM->pgm.s.pRamRangesXR3;
763	if (pCur)
764	{
765	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
766	pVM->pgm.s.pRamRangesXRC = pCur->pSelfRC;
767
768	for (; pCur->pNextR3; pCur = pCur->pNextR3)
769	{
770	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
771	pCur->pNextRC = pCur->pNextR3->pSelfRC;
772	}
773
774	Assert(pCur->pNextR0 == NIL_RTR0PTR);
775	Assert(pCur->pNextRC == NIL_RTRCPTR);
776	}
777	else
778	{
779	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
780	Assert(pVM->pgm.s.pRamRangesXRC == NIL_RTRCPTR);
781	}
782	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
783
784	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
785	}
786
787
788	/**
789	* Links a new RAM range into the list.
790	*
791	* @param pVM The cross context VM structure.
792	* @param pNew Pointer to the new list entry.
793	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
794	*/
795	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
796	{
797	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
798	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
799	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
800
801	pgmLock(pVM);
802
803	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
804	pNew->pNextR3 = pRam;
805	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
806	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
807
808	if (pPrev)
809	{
810	pPrev->pNextR3 = pNew;
811	pPrev->pNextR0 = pNew->pSelfR0;
812	pPrev->pNextRC = pNew->pSelfRC;
813	}
814	else
815	{
816	pVM->pgm.s.pRamRangesXR3 = pNew;
817	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
818	pVM->pgm.s.pRamRangesXRC = pNew->pSelfRC;
819	}
820	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
821
822	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
823	pgmUnlock(pVM);
824	}
825
826
827	/**
828	* Unlink an existing RAM range from the list.
829	*
830	* @param pVM The cross context VM structure.
831	* @param pRam Pointer to the new list entry.
832	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
833	*/
834	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
835	{
836	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
837	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
838	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
839
840	pgmLock(pVM);
841
842	PPGMRAMRANGE pNext = pRam->pNextR3;
843	if (pPrev)
844	{
845	pPrev->pNextR3 = pNext;
846	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
847	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
848	}
849	else
850	{
851	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
852	pVM->pgm.s.pRamRangesXR3 = pNext;
853	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
854	pVM->pgm.s.pRamRangesXRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
855	}
856	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
857
858	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
859	pgmUnlock(pVM);
860	}
861
862
863	/**
864	* Unlink an existing RAM range from the list.
865	*
866	* @param pVM The cross context VM structure.
867	* @param pRam Pointer to the new list entry.
868	*/
869	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
870	{
871	pgmLock(pVM);
872
873	/* find prev. */
874	PPGMRAMRANGE pPrev = NULL;
875	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
876	while (pCur != pRam)
877	{
878	pPrev = pCur;
879	pCur = pCur->pNextR3;
880	}
881	AssertFatal(pCur);
882
883	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
884	pgmUnlock(pVM);
885	}
886
887
888	/**
889	* Frees a range of pages, replacing them with ZERO pages of the specified type.
890	*
891	* @returns VBox status code.
892	* @param pVM The cross context VM structure.
893	* @param pRam The RAM range in which the pages resides.
894	* @param GCPhys The address of the first page.
895	* @param GCPhysLast The address of the last page.
896	* @param uType The page type to replace then with.
897	*/
898	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
899	{
900	PGM_LOCK_ASSERT_OWNER(pVM);
901	uint32_t cPendingPages = 0;
902	PGMMFREEPAGESREQ pReq;
903	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
904	AssertLogRelRCReturn(rc, rc);
905
906	/* Iterate the pages. */
907	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
908	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
909	while (cPagesLeft-- > 0)
910	{
911	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
912	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
913
914	PGM_PAGE_SET_TYPE(pVM, pPageDst, uType);
915
916	GCPhys += PAGE_SIZE;
917	pPageDst++;
918	}
919
920	if (cPendingPages)
921	{
922	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
923	AssertLogRelRCReturn(rc, rc);
924	}
925	GMMR3FreePagesCleanup(pReq);
926
927	return rc;
928	}
929
930	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
931
932	/**
933	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
934	*
935	* This is only called on one of the EMTs while the other ones are waiting for
936	* it to complete this function.
937	*
938	* @returns VINF_SUCCESS (VBox strict status code).
939	* @param pVM The cross context VM structure.
940	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
941	* @param pvUser User parameter
942	*/
943	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
944	{
945	uintptr_t paUser = (uintptr_t )pvUser;
946	bool fInflate = !!paUser[0];
947	unsigned cPages = paUser[1];
948	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
949	uint32_t cPendingPages = 0;
950	PGMMFREEPAGESREQ pReq;
951	int rc;
952
953	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
954	pgmLock(pVM);
955
956	if (fInflate)
957	{
958	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
959	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
960
961	/* Replace pages with ZERO pages. */
962	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
963	if (RT_FAILURE(rc))
964	{
965	pgmUnlock(pVM);
966	AssertLogRelRC(rc);
967	return rc;
968	}
969
970	/* Iterate the pages. */
971	for (unsigned i = 0; i < cPages; i++)
972	{
973	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
974	if ( pPage == NULL
975	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
976	{
977	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
978	break;
979	}
980
981	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
982
983	/* Flush the shadow PT if this page was previously used as a guest page table. */
984	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
985
986	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i]);
987	if (RT_FAILURE(rc))
988	{
989	pgmUnlock(pVM);
990	AssertLogRelRC(rc);
991	return rc;
992	}
993	Assert(PGM_PAGE_IS_ZERO(pPage));
994	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
995	}
996
997	if (cPendingPages)
998	{
999	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1000	if (RT_FAILURE(rc))
1001	{
1002	pgmUnlock(pVM);
1003	AssertLogRelRC(rc);
1004	return rc;
1005	}
1006	}
1007	GMMR3FreePagesCleanup(pReq);
1008	}
1009	else
1010	{
1011	/* Iterate the pages. */
1012	for (unsigned i = 0; i < cPages; i++)
1013	{
1014	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1015	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
1016
1017	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
1018
1019	Assert(PGM_PAGE_IS_BALLOONED(pPage));
1020
1021	/* Change back to zero page. */
1022	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1023	}
1024
1025	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
1026	}
1027
1028	/* Notify GMM about the balloon change. */
1029	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
1030	if (RT_SUCCESS(rc))
1031	{
1032	if (!fInflate)
1033	{
1034	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
1035	pVM->pgm.s.cBalloonedPages -= cPages;
1036	}
1037	else
1038	pVM->pgm.s.cBalloonedPages += cPages;
1039	}
1040
1041	pgmUnlock(pVM);
1042
1043	/* Flush the recompiler's TLB as well. */
1044	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1045	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1046
1047	AssertLogRelRC(rc);
1048	return rc;
1049	}
1050
1051
1052	/**
1053	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
1054	*
1055	* @returns VBox status code.
1056	* @param pVM The cross context VM structure.
1057	* @param fInflate Inflate or deflate memory balloon
1058	* @param cPages Number of pages to free
1059	* @param paPhysPage Array of guest physical addresses
1060	*/
1061	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1062	{
1063	uintptr_t paUser[3];
1064
1065	paUser[0] = fInflate;
1066	paUser[1] = cPages;
1067	paUser[2] = (uintptr_t)paPhysPage;
1068	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1069	AssertRC(rc);
1070
1071	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
1072	RTMemFree(paPhysPage);
1073	}
1074
1075	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
1076
1077	/**
1078	* Inflate or deflate a memory balloon
1079	*
1080	* @returns VBox status code.
1081	* @param pVM The cross context VM structure.
1082	* @param fInflate Inflate or deflate memory balloon
1083	* @param cPages Number of pages to free
1084	* @param paPhysPage Array of guest physical addresses
1085	*/
1086	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1087	{
1088	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
1089	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1090	int rc;
1091
1092	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
1093	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
1094
1095	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
1096	* In the SMP case we post a request packet to postpone the job.
1097	*/
1098	if (pVM->cCpus > 1)
1099	{
1100	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
1101	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
1102	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
1103
1104	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
1105
1106	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
1107	AssertRC(rc);
1108	}
1109	else
1110	{
1111	uintptr_t paUser[3];
1112
1113	paUser[0] = fInflate;
1114	paUser[1] = cPages;
1115	paUser[2] = (uintptr_t)paPhysPage;
1116	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1117	AssertRC(rc);
1118	}
1119	return rc;
1120
1121	#else
1122	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
1123	return VERR_NOT_IMPLEMENTED;
1124	#endif
1125	}
1126
1127
1128	/**
1129	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
1130	* physical RAM.
1131	*
1132	* This is only called on one of the EMTs while the other ones are waiting for
1133	* it to complete this function.
1134	*
1135	* @returns VINF_SUCCESS (VBox strict status code).
1136	* @param pVM The cross context VM structure.
1137	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1138	* @param pvUser User parameter, unused.
1139	*/
1140	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1141	{
1142	int rc = VINF_SUCCESS;
1143	NOREF(pvUser); NOREF(pVCpu);
1144
1145	pgmLock(pVM);
1146	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1147	pgmPoolResetDirtyPages(pVM);
1148	#endif
1149
1150	/** @todo pointless to write protect the physical page pointed to by RSP. */
1151
1152	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1153	pRam;
1154	pRam = pRam->CTX_SUFF(pNext))
1155	{
1156	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1157	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1158	{
1159	PPGMPAGE pPage = &pRam->aPages[iPage];
1160	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1161
1162	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1163	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1164	{
1165	/*
1166	* A RAM page.
1167	*/
1168	switch (PGM_PAGE_GET_STATE(pPage))
1169	{
1170	case PGM_PAGE_STATE_ALLOCATED:
1171	/** @todo Optimize this: Don't always re-enable write
1172	* monitoring if the page is known to be very busy. */
1173	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
1174	{
1175	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1176	/* Remember this dirty page for the next (memory) sync. */
1177	PGM_PAGE_SET_FT_DIRTY(pPage);
1178	}
1179
1180	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1181	break;
1182
1183	case PGM_PAGE_STATE_SHARED:
1184	AssertFailed();
1185	break;
1186
1187	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
1188	default:
1189	break;
1190	}
1191	}
1192	}
1193	}
1194	pgmR3PoolWriteProtectPages(pVM);
1195	PGM_INVL_ALL_VCPU_TLBS(pVM);
1196	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1197	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1198
1199	pgmUnlock(pVM);
1200	return rc;
1201	}
1202
1203	/**
1204	* Protect all physical RAM to monitor writes
1205	*
1206	* @returns VBox status code.
1207	* @param pVM The cross context VM structure.
1208	*/
1209	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
1210	{
1211	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1212
1213	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
1214	AssertRC(rc);
1215	return rc;
1216	}
1217
1218	/**
1219	* Enumerate all dirty FT pages.
1220	*
1221	* @returns VBox status code.
1222	* @param pVM The cross context VM structure.
1223	* @param pfnEnum Enumerate callback handler.
1224	* @param pvUser Enumerate callback handler parameter.
1225	*/
1226	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser)
1227	{
1228	int rc = VINF_SUCCESS;
1229
1230	pgmLock(pVM);
1231	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1232	pRam;
1233	pRam = pRam->CTX_SUFF(pNext))
1234	{
1235	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1236	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1237	{
1238	PPGMPAGE pPage = &pRam->aPages[iPage];
1239	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1240
1241	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1242	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1243	{
1244	/*
1245	* A RAM page.
1246	*/
1247	switch (PGM_PAGE_GET_STATE(pPage))
1248	{
1249	case PGM_PAGE_STATE_ALLOCATED:
1250	case PGM_PAGE_STATE_WRITE_MONITORED:
1251	if ( !PGM_PAGE_IS_WRITTEN_TO(pPage) /* not very recently updated? */
1252	&& PGM_PAGE_IS_FT_DIRTY(pPage))
1253	{
1254	uint32_t cbPageRange = PAGE_SIZE;
1255	uint32_t iPageClean = iPage + 1;
1256	RTGCPHYS GCPhysPage = pRam->GCPhys + iPage * PAGE_SIZE;
1257	uint8_t *pu8Page = NULL;
1258	PGMPAGEMAPLOCK Lock;
1259
1260	/* Find the next clean page, so we can merge adjacent dirty pages. */
1261	for (; iPageClean < cPages; iPageClean++)
1262	{
1263	PPGMPAGE pPageNext = &pRam->aPages[iPageClean];
1264	if ( RT_UNLIKELY(PGM_PAGE_GET_TYPE(pPageNext) != PGMPAGETYPE_RAM)
1265	\|\| PGM_PAGE_GET_STATE(pPageNext) != PGM_PAGE_STATE_ALLOCATED
1266	\|\| PGM_PAGE_IS_WRITTEN_TO(pPageNext)
1267	\|\| !PGM_PAGE_IS_FT_DIRTY(pPageNext)
1268	/* Crossing a chunk boundary? */
1269	\|\| (GCPhysPage & GMM_PAGEID_IDX_MASK) != ((GCPhysPage + cbPageRange) & GMM_PAGEID_IDX_MASK)
1270	)
1271	break;
1272
1273	cbPageRange += PAGE_SIZE;
1274	}
1275
1276	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhysPage, (const void **)&pu8Page, &Lock);
1277	if (RT_SUCCESS(rc))
1278	{
1279	/** @todo this is risky; the range might be changed, but little choice as the sync
1280	* costs a lot of time. */
1281	pgmUnlock(pVM);
1282	pfnEnum(pVM, GCPhysPage, pu8Page, cbPageRange, pvUser);
1283	pgmLock(pVM);
1284	PGMPhysReleasePageMappingLock(pVM, &Lock);
1285	}
1286
1287	for (uint32_t iTmp = iPage; iTmp < iPageClean; iTmp++)
1288	PGM_PAGE_CLEAR_FT_DIRTY(&pRam->aPages[iTmp]);
1289	}
1290	break;
1291	}
1292	}
1293	}
1294	}
1295	pgmUnlock(pVM);
1296	return rc;
1297	}
1298
1299
1300	/**
1301	* Gets the number of ram ranges.
1302	*
1303	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1304	* @param pVM The cross context VM structure.
1305	*/
1306	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1307	{
1308	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1309
1310	pgmLock(pVM);
1311	uint32_t cRamRanges = 0;
1312	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1313	cRamRanges++;
1314	pgmUnlock(pVM);
1315	return cRamRanges;
1316	}
1317
1318
1319	/**
1320	* Get information about a range.
1321	*
1322	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1323	* @param pVM The cross context VM structure.
1324	* @param iRange The ordinal of the range.
1325	* @param pGCPhysStart Where to return the start of the range. Optional.
1326	* @param pGCPhysLast Where to return the address of the last byte in the
1327	* range. Optional.
1328	* @param ppszDesc Where to return the range description. Optional.
1329	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1330	* Optional.
1331	*/
1332	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1333	const char *ppszDesc, bool pfIsMmio)
1334	{
1335	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1336
1337	pgmLock(pVM);
1338	uint32_t iCurRange = 0;
1339	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1340	if (iCurRange == iRange)
1341	{
1342	if (pGCPhysStart)
1343	*pGCPhysStart = pCur->GCPhys;
1344	if (pGCPhysLast)
1345	*pGCPhysLast = pCur->GCPhysLast;
1346	if (ppszDesc)
1347	*ppszDesc = pCur->pszDesc;
1348	if (pfIsMmio)
1349	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1350
1351	pgmUnlock(pVM);
1352	return VINF_SUCCESS;
1353	}
1354	pgmUnlock(pVM);
1355	return VERR_OUT_OF_RANGE;
1356	}
1357
1358
1359	/**
1360	* Query the amount of free memory inside VMMR0
1361	*
1362	* @returns VBox status code.
1363	* @param pUVM The user mode VM handle.
1364	* @param pcbAllocMem Where to return the amount of memory allocated
1365	* by VMs.
1366	* @param pcbFreeMem Where to return the amount of memory that is
1367	* allocated from the host but not currently used
1368	* by any VMs.
1369	* @param pcbBallonedMem Where to return the sum of memory that is
1370	* currently ballooned by the VMs.
1371	* @param pcbSharedMem Where to return the amount of memory that is
1372	* currently shared.
1373	*/
1374	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
1375	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
1376	{
1377	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1378	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
1379
1380	uint64_t cAllocPages = 0;
1381	uint64_t cFreePages = 0;
1382	uint64_t cBalloonPages = 0;
1383	uint64_t cSharedPages = 0;
1384	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
1385	AssertRCReturn(rc, rc);
1386
1387	if (pcbAllocMem)
1388	pcbAllocMem = cAllocPages _4K;
1389
1390	if (pcbFreeMem)
1391	pcbFreeMem = cFreePages _4K;
1392
1393	if (pcbBallonedMem)
1394	pcbBallonedMem = cBalloonPages _4K;
1395
1396	if (pcbSharedMem)
1397	pcbSharedMem = cSharedPages _4K;
1398
1399	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
1400	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
1401	return VINF_SUCCESS;
1402	}
1403
1404
1405	/**
1406	* Query memory stats for the VM.
1407	*
1408	* @returns VBox status code.
1409	* @param pUVM The user mode VM handle.
1410	* @param pcbTotalMem Where to return total amount memory the VM may
1411	* possibly use.
1412	* @param pcbPrivateMem Where to return the amount of private memory
1413	* currently allocated.
1414	* @param pcbSharedMem Where to return the amount of actually shared
1415	* memory currently used by the VM.
1416	* @param pcbZeroMem Where to return the amount of memory backed by
1417	* zero pages.
1418	*
1419	* @remarks The total mem is normally larger than the sum of the three
1420	* components. There are two reasons for this, first the amount of
1421	* shared memory is what we're sure is shared instead of what could
1422	* possibly be shared with someone. Secondly, because the total may
1423	* include some pure MMIO pages that doesn't go into any of the three
1424	* sub-counts.
1425	*
1426	* @todo Why do we return reused shared pages instead of anything that could
1427	* potentially be shared? Doesn't this mean the first VM gets a much
1428	* lower number of shared pages?
1429	*/
1430	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
1431	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
1432	{
1433	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1434	PVM pVM = pUVM->pVM;
1435	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1436
1437	if (pcbTotalMem)
1438	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
1439
1440	if (pcbPrivateMem)
1441	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
1442
1443	if (pcbSharedMem)
1444	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
1445
1446	if (pcbZeroMem)
1447	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
1448
1449	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
1450	return VINF_SUCCESS;
1451	}
1452
1453
1454	/**
1455	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1456	*
1457	* @param pVM The cross context VM structure.
1458	* @param pNew The new RAM range.
1459	* @param GCPhys The address of the RAM range.
1460	* @param GCPhysLast The last address of the RAM range.
1461	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
1462	* if in HMA.
1463	* @param R0PtrNew Ditto for R0.
1464	* @param pszDesc The description.
1465	* @param pPrev The previous RAM range (for linking).
1466	*/
1467	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1468	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
1469	{
1470	/*
1471	* Initialize the range.
1472	*/
1473	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
1474	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
1475	pNew->GCPhys = GCPhys;
1476	pNew->GCPhysLast = GCPhysLast;
1477	pNew->cb = GCPhysLast - GCPhys + 1;
1478	pNew->pszDesc = pszDesc;
1479	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
1480	pNew->pvR3 = NULL;
1481	pNew->paLSPages = NULL;
1482
1483	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1484	RTGCPHYS iPage = cPages;
1485	while (iPage-- > 0)
1486	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1487
1488	/* Update the page count stats. */
1489	pVM->pgm.s.cZeroPages += cPages;
1490	pVM->pgm.s.cAllPages += cPages;
1491
1492	/*
1493	* Link it.
1494	*/
1495	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1496	}
1497
1498
1499	/**
1500	* @callback_method_impl{FNPGMRELOCATE, Relocate a floating RAM range.}
1501	* @sa pgmR3PhysMMIO2ExRangeRelocate
1502	*/
1503	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
1504	PGMRELOCATECALL enmMode, void *pvUser)
1505	{
1506	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1507	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1508	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE); RT_NOREF_PV(GCPtrOld);
1509
1510	switch (enmMode)
1511	{
1512	case PGMRELOCATECALL_SUGGEST:
1513	return true;
1514
1515	case PGMRELOCATECALL_RELOCATE:
1516	{
1517	/*
1518	* Update myself, then relink all the ranges and flush the RC TLB.
1519	*/
1520	pgmLock(pVM);
1521
1522	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1523
1524	pgmR3PhysRelinkRamRanges(pVM);
1525	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
1526	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
1527
1528	pgmUnlock(pVM);
1529	return true;
1530	}
1531
1532	default:
1533	AssertFailedReturn(false);
1534	}
1535	}
1536
1537
1538	/**
1539	* PGMR3PhysRegisterRam worker that registers a high chunk.
1540	*
1541	* @returns VBox status code.
1542	* @param pVM The cross context VM structure.
1543	* @param GCPhys The address of the RAM.
1544	* @param cRamPages The number of RAM pages to register.
1545	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1546	* @param iChunk The chunk number.
1547	* @param pszDesc The RAM range description.
1548	* @param ppPrev Previous RAM range pointer. In/Out.
1549	*/
1550	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1551	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1552	PPGMRAMRANGE *ppPrev)
1553	{
1554	const char *pszDescChunk = iChunk == 0
1555	? pszDesc
1556	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1557	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1558
1559	/*
1560	* Allocate memory for the new chunk.
1561	*/
1562	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1563	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1564	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1565	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1566	void *pvChunk = NULL;
1567	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1568	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
1569	&R0PtrChunk,
1570	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
1571	VM_IS_HM_OR_NEM_ENABLED(pVM) ? &R0PtrChunk : NULL,
1572	#else
1573	NULL,
1574	#endif
1575	paChunkPages);
1576	if (RT_SUCCESS(rc))
1577	{
1578	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
1579	Assert(R0PtrChunk != NIL_RTR0PTR);
1580	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
1581	if (!VM_IS_HM_OR_NEM_ENABLED(pVM))
1582	R0PtrChunk = NIL_RTR0PTR;
1583	#else
1584	R0PtrChunk = (uintptr_t)pvChunk;
1585	#endif
1586	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1587
1588	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1589
1590	/*
1591	* Create a mapping and map the pages into it.
1592	* We push these in below the HMA.
1593	*/
1594	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1595	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1596	if (RT_SUCCESS(rc))
1597	{
1598	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1599
1600	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1601	RTGCPTR GCPtrPage = GCPtrChunk;
1602	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1603	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1604	if (RT_SUCCESS(rc))
1605	{
1606	/*
1607	* Ok, init and link the range.
1608	*/
1609	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1610	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1611	*ppPrev = pNew;
1612	}
1613	}
1614
1615	if (RT_FAILURE(rc))
1616	SUPR3PageFreeEx(pvChunk, cChunkPages);
1617	}
1618
1619	RTMemTmpFree(paChunkPages);
1620	return rc;
1621	}
1622
1623
1624	/**
1625	* Sets up a range RAM.
1626	*
1627	* This will check for conflicting registrations, make a resource
1628	* reservation for the memory (with GMM), and setup the per-page
1629	* tracking structures (PGMPAGE).
1630	*
1631	* @returns VBox status code.
1632	* @param pVM The cross context VM structure.
1633	* @param GCPhys The physical address of the RAM.
1634	* @param cb The size of the RAM.
1635	* @param pszDesc The description - not copied, so, don't free or change it.
1636	*/
1637	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1638	{
1639	/*
1640	* Validate input.
1641	*/
1642	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1643	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1644	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1645	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1646	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1647	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1648	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1649	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1650
1651	pgmLock(pVM);
1652
1653	/*
1654	* Find range location and check for conflicts.
1655	* (We don't lock here because the locking by EMT is only required on update.)
1656	*/
1657	PPGMRAMRANGE pPrev = NULL;
1658	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1659	while (pRam && GCPhysLast >= pRam->GCPhys)
1660	{
1661	if ( GCPhysLast >= pRam->GCPhys
1662	&& GCPhys <= pRam->GCPhysLast)
1663	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1664	GCPhys, GCPhysLast, pszDesc,
1665	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1666	VERR_PGM_RAM_CONFLICT);
1667
1668	/* next */
1669	pPrev = pRam;
1670	pRam = pRam->pNextR3;
1671	}
1672
1673	/*
1674	* Register it with GMM (the API bitches).
1675	*/
1676	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1677	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1678	if (RT_FAILURE(rc))
1679	{
1680	pgmUnlock(pVM);
1681	return rc;
1682	}
1683
1684	if ( GCPhys >= _4G
1685	&& cPages > 256)
1686	{
1687	/*
1688	* The PGMRAMRANGE structures for the high memory can get very big.
1689	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1690	* allocation size limit there and also to avoid being unable to find
1691	* guest mapping space for them, we split this memory up into 4MB in
1692	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1693	* mode.
1694	*
1695	* The first and last page of each mapping are guard pages and marked
1696	* not-present. So, we've got 4186112 and 16769024 bytes available for
1697	* the PGMRAMRANGE structure.
1698	*
1699	* Note! The sizes used here will influence the saved state.
1700	*/
1701	uint32_t cbChunk;
1702	uint32_t cPagesPerChunk;
1703	if (!VM_IS_RAW_MODE_ENABLED(pVM))
1704	{
1705	cbChunk = 16U*_1M;
1706	cPagesPerChunk = 1048048; /* max ~1048059 */
1707	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1708	}
1709	else
1710	{
1711	cbChunk = 4U*_1M;
1712	cPagesPerChunk = 261616; /* max ~261627 */
1713	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1714	}
1715	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1716
1717	RTGCPHYS cPagesLeft = cPages;
1718	RTGCPHYS GCPhysChunk = GCPhys;
1719	uint32_t iChunk = 0;
1720	while (cPagesLeft > 0)
1721	{
1722	uint32_t cPagesInChunk = cPagesLeft;
1723	if (cPagesInChunk > cPagesPerChunk)
1724	cPagesInChunk = cPagesPerChunk;
1725
1726	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1727	AssertRCReturn(rc, rc);
1728
1729	/* advance */
1730	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1731	cPagesLeft -= cPagesInChunk;
1732	iChunk++;
1733	}
1734	}
1735	else
1736	{
1737	/*
1738	* Allocate, initialize and link the new RAM range.
1739	*/
1740	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1741	PPGMRAMRANGE pNew;
1742	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1743	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1744
1745	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1746	}
1747	pgmPhysInvalidatePageMapTLB(pVM);
1748	pgmUnlock(pVM);
1749
1750	#ifdef VBOX_WITH_REM
1751	/*
1752	* Notify REM.
1753	*/
1754	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1755	#endif
1756
1757	return VINF_SUCCESS;
1758	}
1759
1760
1761	/**
1762	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1763	*
1764	* We do this late in the init process so that all the ROM and MMIO ranges have
1765	* been registered already and we don't go wasting memory on them.
1766	*
1767	* @returns VBox status code.
1768	*
1769	* @param pVM The cross context VM structure.
1770	*/
1771	int pgmR3PhysRamPreAllocate(PVM pVM)
1772	{
1773	Assert(pVM->pgm.s.fRamPreAlloc);
1774	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1775
1776	/*
1777	* Walk the RAM ranges and allocate all RAM pages, halt at
1778	* the first allocation error.
1779	*/
1780	uint64_t cPages = 0;
1781	uint64_t NanoTS = RTTimeNanoTS();
1782	pgmLock(pVM);
1783	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1784	{
1785	PPGMPAGE pPage = &pRam->aPages[0];
1786	RTGCPHYS GCPhys = pRam->GCPhys;
1787	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1788	while (cLeft-- > 0)
1789	{
1790	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1791	{
1792	switch (PGM_PAGE_GET_STATE(pPage))
1793	{
1794	case PGM_PAGE_STATE_ZERO:
1795	{
1796	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1797	if (RT_FAILURE(rc))
1798	{
1799	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1800	pgmUnlock(pVM);
1801	return rc;
1802	}
1803	cPages++;
1804	break;
1805	}
1806
1807	case PGM_PAGE_STATE_BALLOONED:
1808	case PGM_PAGE_STATE_ALLOCATED:
1809	case PGM_PAGE_STATE_WRITE_MONITORED:
1810	case PGM_PAGE_STATE_SHARED:
1811	/* nothing to do here. */
1812	break;
1813	}
1814	}
1815
1816	/* next */
1817	pPage++;
1818	GCPhys += PAGE_SIZE;
1819	}
1820	}
1821	pgmUnlock(pVM);
1822	NanoTS = RTTimeNanoTS() - NanoTS;
1823
1824	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1825	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1826	return VINF_SUCCESS;
1827	}
1828
1829
1830	/**
1831	* Checks shared page checksums.
1832	*
1833	* @param pVM The cross context VM structure.
1834	*/
1835	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
1836	{
1837	#ifdef VBOX_STRICT
1838	pgmLock(pVM);
1839
1840	if (pVM->pgm.s.cSharedPages > 0)
1841	{
1842	/*
1843	* Walk the ram ranges.
1844	*/
1845	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1846	{
1847	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1848	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1849
1850	while (iPage-- > 0)
1851	{
1852	PPGMPAGE pPage = &pRam->aPages[iPage];
1853	if (PGM_PAGE_IS_SHARED(pPage))
1854	{
1855	uint32_t u32Checksum = pPage->s.u2Unused0 \| ((uint32_t)pPage->s.u2Unused1 << 8);
1856	if (!u32Checksum)
1857	{
1858	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1859	void const *pvPage;
1860	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
1861	if (RT_SUCCESS(rc))
1862	{
1863	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
1864	# if 0
1865	AssertMsg((u32Checksum2 & UINT32_C(0x00000303)) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
1866	# else
1867	if ((u32Checksum2 & UINT32_C(0x00000303)) == u32Checksum)
1868	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1869	else
1870	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1871	# endif
1872	}
1873	else
1874	AssertRC(rc);
1875	}
1876	}
1877
1878	} /* for each page */
1879
1880	} /* for each ram range */
1881	}
1882
1883	pgmUnlock(pVM);
1884	#endif /* VBOX_STRICT */
1885	NOREF(pVM);
1886	}
1887
1888
1889	/**
1890	* Resets the physical memory state.
1891	*
1892	* ASSUMES that the caller owns the PGM lock.
1893	*
1894	* @returns VBox status code.
1895	* @param pVM The cross context VM structure.
1896	*/
1897	int pgmR3PhysRamReset(PVM pVM)
1898	{
1899	PGM_LOCK_ASSERT_OWNER(pVM);
1900
1901	/* Reset the memory balloon. */
1902	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1903	AssertRC(rc);
1904
1905	#ifdef VBOX_WITH_PAGE_SHARING
1906	/* Clear all registered shared modules. */
1907	pgmR3PhysAssertSharedPageChecksums(pVM);
1908	rc = GMMR3ResetSharedModules(pVM);
1909	AssertRC(rc);
1910	#endif
1911	/* Reset counters. */
1912	pVM->pgm.s.cReusedSharedPages = 0;
1913	pVM->pgm.s.cBalloonedPages = 0;
1914
1915	return VINF_SUCCESS;
1916	}
1917
1918
1919	/**
1920	* Resets (zeros) the RAM after all devices and components have been reset.
1921	*
1922	* ASSUMES that the caller owns the PGM lock.
1923	*
1924	* @returns VBox status code.
1925	* @param pVM The cross context VM structure.
1926	*/
1927	int pgmR3PhysRamZeroAll(PVM pVM)
1928	{
1929	PGM_LOCK_ASSERT_OWNER(pVM);
1930
1931	/*
1932	* We batch up pages that should be freed instead of calling GMM for
1933	* each and every one of them.
1934	*/
1935	uint32_t cPendingPages = 0;
1936	PGMMFREEPAGESREQ pReq;
1937	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1938	AssertLogRelRCReturn(rc, rc);
1939
1940	/*
1941	* Walk the ram ranges.
1942	*/
1943	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1944	{
1945	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1946	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1947
1948	if ( !pVM->pgm.s.fRamPreAlloc
1949	&& pVM->pgm.s.fZeroRamPagesOnReset)
1950	{
1951	/* Replace all RAM pages by ZERO pages. */
1952	while (iPage-- > 0)
1953	{
1954	PPGMPAGE pPage = &pRam->aPages[iPage];
1955	switch (PGM_PAGE_GET_TYPE(pPage))
1956	{
1957	case PGMPAGETYPE_RAM:
1958	/* Do not replace pages part of a 2 MB continuous range
1959	with zero pages, but zero them instead. */
1960	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
1961	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
1962	{
1963	void *pvPage;
1964	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1965	AssertLogRelRCReturn(rc, rc);
1966	ASMMemZeroPage(pvPage);
1967	}
1968	else if (PGM_PAGE_IS_BALLOONED(pPage))
1969	{
1970	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
1971	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1972	}
1973	else if (!PGM_PAGE_IS_ZERO(pPage))
1974	{
1975	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1976	AssertLogRelRCReturn(rc, rc);
1977	}
1978	break;
1979
1980	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1981	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
1982	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
1983	true /fDoAccounting/);
1984	break;
1985
1986	case PGMPAGETYPE_MMIO2:
1987	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1988	case PGMPAGETYPE_ROM:
1989	case PGMPAGETYPE_MMIO:
1990	break;
1991	default:
1992	AssertFailed();
1993	}
1994	} /* for each page */
1995	}
1996	else
1997	{
1998	/* Zero the memory. */
1999	while (iPage-- > 0)
2000	{
2001	PPGMPAGE pPage = &pRam->aPages[iPage];
2002	switch (PGM_PAGE_GET_TYPE(pPage))
2003	{
2004	case PGMPAGETYPE_RAM:
2005	switch (PGM_PAGE_GET_STATE(pPage))
2006	{
2007	case PGM_PAGE_STATE_ZERO:
2008	break;
2009
2010	case PGM_PAGE_STATE_BALLOONED:
2011	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2012	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2013	break;
2014
2015	case PGM_PAGE_STATE_SHARED:
2016	case PGM_PAGE_STATE_WRITE_MONITORED:
2017	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2018	AssertLogRelRCReturn(rc, rc);
2019	RT_FALL_THRU();
2020
2021	case PGM_PAGE_STATE_ALLOCATED:
2022	if (pVM->pgm.s.fZeroRamPagesOnReset)
2023	{
2024	void *pvPage;
2025	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2026	AssertLogRelRCReturn(rc, rc);
2027	ASMMemZeroPage(pvPage);
2028	}
2029	break;
2030	}
2031	break;
2032
2033	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2034	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2035	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2036	true /fDoAccounting/);
2037	break;
2038
2039	case PGMPAGETYPE_MMIO2:
2040	case PGMPAGETYPE_ROM_SHADOW:
2041	case PGMPAGETYPE_ROM:
2042	case PGMPAGETYPE_MMIO:
2043	break;
2044	default:
2045	AssertFailed();
2046
2047	}
2048	} /* for each page */
2049	}
2050
2051	}
2052
2053	/*
2054	* Finish off any pages pending freeing.
2055	*/
2056	if (cPendingPages)
2057	{
2058	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2059	AssertLogRelRCReturn(rc, rc);
2060	}
2061	GMMR3FreePagesCleanup(pReq);
2062	return VINF_SUCCESS;
2063	}
2064
2065
2066	/**
2067	* Frees all RAM during VM termination
2068	*
2069	* ASSUMES that the caller owns the PGM lock.
2070	*
2071	* @returns VBox status code.
2072	* @param pVM The cross context VM structure.
2073	*/
2074	int pgmR3PhysRamTerm(PVM pVM)
2075	{
2076	PGM_LOCK_ASSERT_OWNER(pVM);
2077
2078	/* Reset the memory balloon. */
2079	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2080	AssertRC(rc);
2081
2082	#ifdef VBOX_WITH_PAGE_SHARING
2083	/*
2084	* Clear all registered shared modules.
2085	*/
2086	pgmR3PhysAssertSharedPageChecksums(pVM);
2087	rc = GMMR3ResetSharedModules(pVM);
2088	AssertRC(rc);
2089
2090	/*
2091	* Flush the handy pages updates to make sure no shared pages are hiding
2092	* in there. (No unlikely if the VM shuts down, apparently.)
2093	*/
2094	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2095	#endif
2096
2097	/*
2098	* We batch up pages that should be freed instead of calling GMM for
2099	* each and every one of them.
2100	*/
2101	uint32_t cPendingPages = 0;
2102	PGMMFREEPAGESREQ pReq;
2103	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2104	AssertLogRelRCReturn(rc, rc);
2105
2106	/*
2107	* Walk the ram ranges.
2108	*/
2109	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2110	{
2111	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2112	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2113
2114	while (iPage-- > 0)
2115	{
2116	PPGMPAGE pPage = &pRam->aPages[iPage];
2117	switch (PGM_PAGE_GET_TYPE(pPage))
2118	{
2119	case PGMPAGETYPE_RAM:
2120	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2121	/** @todo change this to explicitly free private pages here. */
2122	if (PGM_PAGE_IS_SHARED(pPage))
2123	{
2124	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2125	AssertLogRelRCReturn(rc, rc);
2126	}
2127	break;
2128
2129	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2130	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2131	case PGMPAGETYPE_MMIO2:
2132	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2133	case PGMPAGETYPE_ROM:
2134	case PGMPAGETYPE_MMIO:
2135	break;
2136	default:
2137	AssertFailed();
2138	}
2139	} /* for each page */
2140	}
2141
2142	/*
2143	* Finish off any pages pending freeing.
2144	*/
2145	if (cPendingPages)
2146	{
2147	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2148	AssertLogRelRCReturn(rc, rc);
2149	}
2150	GMMR3FreePagesCleanup(pReq);
2151	return VINF_SUCCESS;
2152	}
2153
2154
2155	/**
2156	* This is the interface IOM is using to register an MMIO region.
2157	*
2158	* It will check for conflicts and ensure that a RAM range structure
2159	* is present before calling the PGMR3HandlerPhysicalRegister API to
2160	* register the callbacks.
2161	*
2162	* @returns VBox status code.
2163	*
2164	* @param pVM The cross context VM structure.
2165	* @param GCPhys The start of the MMIO region.
2166	* @param cb The size of the MMIO region.
2167	* @param hType The physical access handler type registration.
2168	* @param pvUserR3 The user argument for R3.
2169	* @param pvUserR0 The user argument for R0.
2170	* @param pvUserRC The user argument for RC.
2171	* @param pszDesc The description of the MMIO region.
2172	*/
2173	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2174	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2175	{
2176	/*
2177	* Assert on some assumption.
2178	*/
2179	VM_ASSERT_EMT(pVM);
2180	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2181	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2182	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2183	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2184	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2185
2186	int rc = pgmLock(pVM);
2187	AssertRCReturn(rc, rc);
2188
2189	/*
2190	* Make sure there's a RAM range structure for the region.
2191	*/
2192	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2193	bool fRamExists = false;
2194	PPGMRAMRANGE pRamPrev = NULL;
2195	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2196	while (pRam && GCPhysLast >= pRam->GCPhys)
2197	{
2198	if ( GCPhysLast >= pRam->GCPhys
2199	&& GCPhys <= pRam->GCPhysLast)
2200	{
2201	/* Simplification: all within the same range. */
2202	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2203	&& GCPhysLast <= pRam->GCPhysLast,
2204	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2205	GCPhys, GCPhysLast, pszDesc,
2206	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2207	pgmUnlock(pVM),
2208	VERR_PGM_RAM_CONFLICT);
2209
2210	/* Check that it's all RAM or MMIO pages. */
2211	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2212	uint32_t cLeft = cb >> PAGE_SHIFT;
2213	while (cLeft-- > 0)
2214	{
2215	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2216	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2217	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2218	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2219	pgmUnlock(pVM),
2220	VERR_PGM_RAM_CONFLICT);
2221	pPage++;
2222	}
2223
2224	/* Looks good. */
2225	fRamExists = true;
2226	break;
2227	}
2228
2229	/* next */
2230	pRamPrev = pRam;
2231	pRam = pRam->pNextR3;
2232	}
2233	PPGMRAMRANGE pNew;
2234	if (fRamExists)
2235	{
2236	pNew = NULL;
2237
2238	/*
2239	* Make all the pages in the range MMIO/ZERO pages, freeing any
2240	* RAM pages currently mapped here. This might not be 100% correct
2241	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2242	*/
2243	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
2244	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
2245
2246	/* Force a PGM pool flush as guest ram references have been changed. */
2247	/** @todo not entirely SMP safe; assuming for now the guest takes
2248	* care of this internally (not touch mapped mmio while changing the
2249	* mapping). */
2250	PVMCPU pVCpu = VMMGetCpu(pVM);
2251	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2252	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2253	}
2254	else
2255	{
2256
2257	/*
2258	* No RAM range, insert an ad hoc one.
2259	*
2260	* Note that we don't have to tell REM about this range because
2261	* PGMHandlerPhysicalRegisterEx will do that for us.
2262	*/
2263	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2264
2265	const uint32_t cPages = cb >> PAGE_SHIFT;
2266	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
2267	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2268	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), pgmUnlock(pVM), rc);
2269
2270	/* Initialize the range. */
2271	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2272	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
2273	pNew->GCPhys = GCPhys;
2274	pNew->GCPhysLast = GCPhysLast;
2275	pNew->cb = cb;
2276	pNew->pszDesc = pszDesc;
2277	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2278	pNew->pvR3 = NULL;
2279	pNew->paLSPages = NULL;
2280
2281	uint32_t iPage = cPages;
2282	while (iPage-- > 0)
2283	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2284	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2285
2286	/* update the page count stats. */
2287	pVM->pgm.s.cPureMmioPages += cPages;
2288	pVM->pgm.s.cAllPages += cPages;
2289
2290	/* link it */
2291	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2292	}
2293
2294	/*
2295	* Register the access handler.
2296	*/
2297	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2298	if ( RT_FAILURE(rc)
2299	&& !fRamExists)
2300	{
2301	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2302	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2303
2304	/* remove the ad hoc range. */
2305	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2306	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2307	MMHyperFree(pVM, pRam);
2308	}
2309	pgmPhysInvalidatePageMapTLB(pVM);
2310
2311	pgmUnlock(pVM);
2312	return rc;
2313	}
2314
2315
2316	/**
2317	* This is the interface IOM is using to register an MMIO region.
2318	*
2319	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2320	* any ad hoc PGMRAMRANGE left behind.
2321	*
2322	* @returns VBox status code.
2323	* @param pVM The cross context VM structure.
2324	* @param GCPhys The start of the MMIO region.
2325	* @param cb The size of the MMIO region.
2326	*/
2327	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2328	{
2329	VM_ASSERT_EMT(pVM);
2330
2331	int rc = pgmLock(pVM);
2332	AssertRCReturn(rc, rc);
2333
2334	/*
2335	* First deregister the handler, then check if we should remove the ram range.
2336	*/
2337	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2338	if (RT_SUCCESS(rc))
2339	{
2340	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2341	PPGMRAMRANGE pRamPrev = NULL;
2342	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2343	while (pRam && GCPhysLast >= pRam->GCPhys)
2344	{
2345	/** @todo We're being a bit too careful here. rewrite. */
2346	if ( GCPhysLast == pRam->GCPhysLast
2347	&& GCPhys == pRam->GCPhys)
2348	{
2349	Assert(pRam->cb == cb);
2350
2351	/*
2352	* See if all the pages are dead MMIO pages.
2353	*/
2354	uint32_t const cPages = cb >> PAGE_SHIFT;
2355	bool fAllMMIO = true;
2356	uint32_t iPage = 0;
2357	uint32_t cLeft = cPages;
2358	while (cLeft-- > 0)
2359	{
2360	PPGMPAGE pPage = &pRam->aPages[iPage];
2361	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2362	/\|\| not-out-of-action later /)
2363	{
2364	fAllMMIO = false;
2365	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2366	break;
2367	}
2368	Assert( PGM_PAGE_IS_ZERO(pPage)
2369	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2370	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2371	pPage++;
2372	}
2373	if (fAllMMIO)
2374	{
2375	/*
2376	* Ad-hoc range, unlink and free it.
2377	*/
2378	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2379	GCPhys, GCPhysLast, pRam->pszDesc));
2380
2381	pVM->pgm.s.cAllPages -= cPages;
2382	pVM->pgm.s.cPureMmioPages -= cPages;
2383
2384	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2385	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2386	MMHyperFree(pVM, pRam);
2387	break;
2388	}
2389	}
2390
2391	/*
2392	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2393	*/
2394	if ( GCPhysLast >= pRam->GCPhys
2395	&& GCPhys <= pRam->GCPhysLast)
2396	{
2397	Assert(GCPhys >= pRam->GCPhys);
2398	Assert(GCPhysLast <= pRam->GCPhysLast);
2399
2400	/*
2401	* Turn the pages back into RAM pages.
2402	*/
2403	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2404	uint32_t cLeft = cb >> PAGE_SHIFT;
2405	while (cLeft--)
2406	{
2407	PPGMPAGE pPage = &pRam->aPages[iPage];
2408	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2409	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2410	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2411	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2412	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2413	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2414	}
2415	break;
2416	}
2417
2418	/* next */
2419	pRamPrev = pRam;
2420	pRam = pRam->pNextR3;
2421	}
2422	}
2423
2424	/* Force a PGM pool flush as guest ram references have been changed. */
2425	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2426	* this internally (not touch mapped mmio while changing the mapping). */
2427	PVMCPU pVCpu = VMMGetCpu(pVM);
2428	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2429	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2430
2431	pgmPhysInvalidatePageMapTLB(pVM);
2432	pgmPhysInvalidRamRangeTlbs(pVM);
2433	pgmUnlock(pVM);
2434	return rc;
2435	}
2436
2437
2438	/**
2439	* Locate a MMIO2 range.
2440	*
2441	* @returns Pointer to the MMIO2 range.
2442	* @param pVM The cross context VM structure.
2443	* @param pDevIns The device instance owning the region.
2444	* @param iSubDev The sub-device number.
2445	* @param iRegion The region.
2446	*/
2447	DECLINLINE(PPGMREGMMIORANGE) pgmR3PhysMMIOExFind(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion)
2448	{
2449	/*
2450	* Search the list. There shouldn't be many entries.
2451	*/
2452	/** @todo Optimize this lookup! There may now be many entries and it'll
2453	* become really slow when doing MMR3HyperMapMMIO2 and similar. */
2454	for (PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2455	if ( pCur->pDevInsR3 == pDevIns
2456	&& pCur->iRegion == iRegion
2457	&& pCur->iSubDev == iSubDev)
2458	return pCur;
2459	return NULL;
2460	}
2461
2462
2463	/**
2464	* @callback_method_impl{FNPGMRELOCATE, Relocate a floating MMIO/MMIO2 range.}
2465	* @sa pgmR3PhysRamRangeRelocate
2466	*/
2467	static DECLCALLBACK(bool) pgmR3PhysMMIOExRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
2468	PGMRELOCATECALL enmMode, void *pvUser)
2469	{
2470	PPGMREGMMIORANGE pMmio = (PPGMREGMMIORANGE)pvUser;
2471	Assert(pMmio->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
2472	Assert(pMmio->RamRange.pSelfRC == GCPtrOld + PAGE_SIZE + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange)); RT_NOREF_PV(GCPtrOld);
2473
2474	switch (enmMode)
2475	{
2476	case PGMRELOCATECALL_SUGGEST:
2477	return true;
2478
2479	case PGMRELOCATECALL_RELOCATE:
2480	{
2481	/*
2482	* Update myself, then relink all the ranges and flush the RC TLB.
2483	*/
2484	pgmLock(pVM);
2485
2486	pMmio->RamRange.pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange));
2487
2488	pgmR3PhysRelinkRamRanges(pVM);
2489	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2490	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2491
2492	pgmUnlock(pVM);
2493	return true;
2494	}
2495
2496	default:
2497	AssertFailedReturn(false);
2498	}
2499	}
2500
2501
2502	/**
2503	* Calculates the number of chunks
2504	*
2505	* @returns Number of registration chunk needed.
2506	* @param pVM The cross context VM structure.
2507	* @param cb The size of the MMIO/MMIO2 range.
2508	* @param pcPagesPerChunk Where to return the number of pages tracked by each
2509	* chunk. Optional.
2510	* @param pcbChunk Where to return the guest mapping size for a chunk.
2511	*/
2512	static uint16_t pgmR3PhysMMIOExCalcChunkCount(PVM pVM, RTGCPHYS cb, uint32_t pcPagesPerChunk, uint32_t pcbChunk)
2513	{
2514	RT_NOREF_PV(pVM); /* without raw mode */
2515
2516	/*
2517	* This is the same calculation as PGMR3PhysRegisterRam does, except we'll be
2518	* needing a few bytes extra the PGMREGMMIORANGE structure.
2519	*
2520	* Note! In additions, we've got a 24 bit sub-page range for MMIO2 ranges, leaving
2521	* us with an absolute maximum of 16777215 pages per chunk (close to 64 GB).
2522	*/
2523	uint32_t cbChunk;
2524	uint32_t cPagesPerChunk;
2525	if (!VM_IS_RAW_MODE_ENABLED(pVM))
2526	{
2527	cbChunk = 16U*_1M;
2528	cPagesPerChunk = 1048048; /* max ~1048059 */
2529	AssertCompile(sizeof(PGMREGMMIORANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
2530	}
2531	else
2532	{
2533	cbChunk = 4U*_1M;
2534	cPagesPerChunk = 261616; /* max ~261627 */
2535	AssertCompile(sizeof(PGMREGMMIORANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
2536	}
2537	AssertRelease(cPagesPerChunk <= PGM_MMIO2_MAX_PAGE_COUNT); /* See above note. */
2538	AssertRelease(RT_UOFFSETOF(PGMREGMMIORANGE, RamRange.aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
2539	if (pcbChunk)
2540	*pcbChunk = cbChunk;
2541	if (pcPagesPerChunk)
2542	*pcPagesPerChunk = cPagesPerChunk;
2543
2544	/* Calc the number of chunks we need. */
2545	RTGCPHYS const cPages = cb >> X86_PAGE_SHIFT;
2546	uint16_t cChunks = (uint16_t)((cPages + cPagesPerChunk - 1) / cPagesPerChunk);
2547	AssertRelease((RTGCPHYS)cChunks * cPagesPerChunk >= cPages);
2548	return cChunks;
2549	}
2550
2551
2552	/**
2553	* Worker for PGMR3PhysMMIOExPreRegister & PGMR3PhysMMIO2Register that allocates
2554	* and the PGMREGMMIORANGE structures and does basic initialization.
2555	*
2556	* Caller must set type specfic members and initialize the PGMPAGE structures.
2557	*
2558	* @returns VBox status code.
2559	* @param pVM The cross context VM structure.
2560	* @param pDevIns The device instance owning the region.
2561	* @param iSubDev The sub-device number (internal PCI config number).
2562	* @param iRegion The region number. If the MMIO2 memory is a PCI
2563	* I/O region this number has to be the number of that
2564	* region. Otherwise it can be any number safe
2565	* UINT8_MAX.
2566	* @param cb The size of the region. Must be page aligned.
2567	* @param pszDesc The description.
2568	* @param ppHeadRet Where to return the pointer to the first
2569	* registration chunk.
2570	*
2571	* @thread EMT
2572	*/
2573	static int pgmR3PhysMMIOExCreate(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2574	const char pszDesc, PPGMREGMMIORANGE ppHeadRet)
2575	{
2576	/*
2577	* Figure out how many chunks we need and of which size.
2578	*/
2579	uint32_t cPagesPerChunk;
2580	uint16_t cChunks = pgmR3PhysMMIOExCalcChunkCount(pVM, cb, &cPagesPerChunk, NULL);
2581	AssertReturn(cChunks, VERR_PGM_PHYS_MMIO_EX_IPE);
2582
2583	/*
2584	* Allocate the chunks.
2585	*/
2586	PPGMREGMMIORANGE *ppNext = ppHeadRet;
2587	*ppNext = NULL;
2588
2589	int rc = VINF_SUCCESS;
2590	uint32_t cPagesLeft = cb >> X86_PAGE_SHIFT;
2591	for (uint16_t iChunk = 0; iChunk < cChunks && RT_SUCCESS(rc); iChunk++)
2592	{
2593	/*
2594	* We currently do a single RAM range for the whole thing. This will
2595	* probably have to change once someone needs really large MMIO regions,
2596	* as we will be running into SUPR3PageAllocEx limitations and such.
2597	*/
2598	const uint32_t cPagesTrackedByChunk = RT_MIN(cPagesLeft, cPagesPerChunk);
2599	const size_t cbRange = RT_OFFSETOF(PGMREGMMIORANGE, RamRange.aPages[cPagesTrackedByChunk]);
2600	PPGMREGMMIORANGE pNew = NULL;
2601	if ( iChunk + 1 < cChunks
2602	\|\| cbRange >= _1M)
2603	{
2604	/*
2605	* Allocate memory for the registration structure.
2606	*/
2607	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2608	size_t const cbChunk = (1 + cChunkPages + 1) << PAGE_SHIFT;
2609	AssertLogRelBreakStmt(cbChunk == (uint32_t)cbChunk, rc = VERR_OUT_OF_RANGE);
2610	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
2611	AssertBreakStmt(paChunkPages, rc = VERR_NO_TMP_MEMORY);
2612	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
2613	void *pvChunk = NULL;
2614	rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
2615	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
2616	&R0PtrChunk,
2617	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
2618	VM_IS_HM_OR_NEM_ENABLED(pVM) ? &R0PtrChunk : NULL,
2619	#else
2620	NULL,
2621	#endif
2622	paChunkPages);
2623	AssertLogRelMsgRCBreakStmt(rc, ("rc=%Rrc, cChunkPages=%#zx\n", rc, cChunkPages), RTMemTmpFree(paChunkPages));
2624
2625	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
2626	Assert(R0PtrChunk != NIL_RTR0PTR);
2627	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
2628	if (!VM_IS_HM_OR_NEM_ENABLED(pVM))
2629	R0PtrChunk = NIL_RTR0PTR;
2630	#else
2631	R0PtrChunk = (uintptr_t)pvChunk;
2632	#endif
2633	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
2634
2635	pNew = (PPGMREGMMIORANGE)pvChunk;
2636	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_FLOATING;
2637	pNew->RamRange.pSelfR0 = R0PtrChunk + RT_OFFSETOF(PGMREGMMIORANGE, RamRange);
2638
2639	/*
2640	* If we might end up in raw-mode, make a HMA mapping of the range,
2641	* just like we do for memory above 4GB.
2642	*/
2643	if (!VM_IS_RAW_MODE_ENABLED(pVM))
2644	pNew->RamRange.pSelfRC = NIL_RTRCPTR;
2645	else
2646	{
2647	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - RT_ALIGN_Z(cbChunk, _4M);
2648	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
2649	rc = PGMR3MapPT(pVM, GCPtrChunkMap, (uint32_t)cbChunk, 0 /fFlags/, pgmR3PhysMMIOExRangeRelocate, pNew, pszDesc);
2650	if (RT_SUCCESS(rc))
2651	{
2652	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
2653
2654	RTGCPTR GCPtrPage = GCPtrChunk;
2655	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
2656	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
2657	}
2658	if (RT_FAILURE(rc))
2659	{
2660	SUPR3PageFreeEx(pvChunk, cChunkPages);
2661	break;
2662	}
2663	pNew->RamRange.pSelfRC = GCPtrChunk + RT_OFFSETOF(PGMREGMMIORANGE, RamRange);
2664	}
2665	}
2666	/*
2667	* Not so big, do a one time hyper allocation.
2668	*/
2669	else
2670	{
2671	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2672	AssertLogRelMsgRCBreak(rc, ("cbRange=%zu\n", cbRange));
2673
2674	/*
2675	* Initialize allocation specific items.
2676	*/
2677	//pNew->RamRange.fFlags = 0;
2678	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2679	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
2680	}
2681
2682	/*
2683	* Initialize the registration structure (caller does specific bits).
2684	*/
2685	pNew->pDevInsR3 = pDevIns;
2686	//pNew->pvR3 = NULL;
2687	//pNew->pNext = NULL;
2688	//pNew->fFlags = 0;
2689	if (iChunk == 0)
2690	pNew->fFlags \|= PGMREGMMIORANGE_F_FIRST_CHUNK;
2691	if (iChunk + 1 == cChunks)
2692	pNew->fFlags \|= PGMREGMMIORANGE_F_LAST_CHUNK;
2693	pNew->iSubDev = iSubDev;
2694	pNew->iRegion = iRegion;
2695	pNew->idSavedState = UINT8_MAX;
2696	pNew->idMmio2 = UINT8_MAX;
2697	//pNew->pPhysHandlerR3 = NULL;
2698	//pNew->paLSPages = NULL;
2699	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2700	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2701	pNew->RamRange.pszDesc = pszDesc;
2702	pNew->RamRange.cb = pNew->cbReal = (RTGCPHYS)cPagesTrackedByChunk << X86_PAGE_SHIFT;
2703	pNew->RamRange.fFlags \|= PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX;
2704	//pNew->RamRange.pvR3 = NULL;
2705	//pNew->RamRange.paLSPages = NULL;
2706
2707	*ppNext = pNew;
2708	ASMCompilerBarrier();
2709	cPagesLeft -= cPagesTrackedByChunk;
2710	ppNext = &pNew->pNextR3;
2711	}
2712	Assert(cPagesLeft == 0);
2713
2714	if (RT_SUCCESS(rc))
2715	{
2716	Assert((*ppHeadRet)->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
2717	return VINF_SUCCESS;
2718	}
2719
2720	/*
2721	* Free floating ranges.
2722	*/
2723	while (*ppHeadRet)
2724	{
2725	PPGMREGMMIORANGE pFree = *ppHeadRet;
2726	*ppHeadRet = pFree->pNextR3;
2727
2728	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
2729	{
2730	const size_t cbRange = RT_OFFSETOF(PGMREGMMIORANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
2731	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2732	SUPR3PageFreeEx(pFree, cChunkPages);
2733	}
2734	}
2735
2736	return rc;
2737	}
2738
2739
2740	/**
2741	* Common worker PGMR3PhysMMIOExPreRegister & PGMR3PhysMMIO2Register that links
2742	* a complete registration entry into the lists and lookup tables.
2743	*
2744	* @param pVM The cross context VM structure.
2745	* @param pNew The new MMIO / MMIO2 registration to link.
2746	*/
2747	static void pgmR3PhysMMIOExLink(PVM pVM, PPGMREGMMIORANGE pNew)
2748	{
2749	/*
2750	* Link it into the list (order doesn't matter, so insert it at the head).
2751	*
2752	* Note! The range we're link may consist of multiple chunks, so we have to
2753	* find the last one.
2754	*/
2755	PPGMREGMMIORANGE pLast = pNew;
2756	for (pLast = pNew; ; pLast = pLast->pNextR3)
2757	{
2758	if (pLast->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
2759	break;
2760	Assert(pLast->pNextR3);
2761	Assert(pLast->pNextR3->pDevInsR3 == pNew->pDevInsR3);
2762	Assert(pLast->pNextR3->iSubDev == pNew->iSubDev);
2763	Assert(pLast->pNextR3->iRegion == pNew->iRegion);
2764	Assert((pLast->pNextR3->fFlags & PGMREGMMIORANGE_F_MMIO2) == (pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
2765	Assert(pLast->pNextR3->idMmio2 == (pLast->fFlags & PGMREGMMIORANGE_F_MMIO2 ? pNew->idMmio2 + 1 : UINT8_MAX));
2766	}
2767
2768	pgmLock(pVM);
2769
2770	/* Link in the chain of ranges at the head of the list. */
2771	pLast->pNextR3 = pVM->pgm.s.pRegMmioRangesR3;
2772	pVM->pgm.s.pRegMmioRangesR3 = pNew;
2773
2774	/* If MMIO, insert the MMIO2 range/page IDs. */
2775	uint8_t idMmio2 = pNew->idMmio2;
2776	if (idMmio2 != UINT8_MAX)
2777	{
2778	for (;;)
2779	{
2780	Assert(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2);
2781	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
2782	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
2783	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
2784	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = pNew->RamRange.pSelfR0 - RT_OFFSETOF(PGMREGMMIORANGE, RamRange);
2785	if (pNew->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
2786	break;
2787	pNew = pNew->pNextR3;
2788	}
2789	}
2790	else
2791	Assert(!(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
2792
2793	pgmPhysInvalidatePageMapTLB(pVM);
2794	pgmUnlock(pVM);
2795	}
2796
2797
2798	/**
2799	* Allocate and pre-register an MMIO region.
2800	*
2801	* This is currently the way to deal with large MMIO regions. It may in the
2802	* future be extended to be the way we deal with all MMIO regions, but that
2803	* means we'll have to do something about the simple list based approach we take
2804	* to tracking the registrations.
2805	*
2806	* @returns VBox status code.
2807	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2808	* memory.
2809	* @retval VERR_ALREADY_EXISTS if the region already exists.
2810	*
2811	* @param pVM The cross context VM structure.
2812	* @param pDevIns The device instance owning the region.
2813	* @param iSubDev The sub-device number.
2814	* @param iRegion The region number. If the MMIO2 memory is a PCI
2815	* I/O region this number has to be the number of that
2816	* region. Otherwise it can be any number safe
2817	* UINT8_MAX.
2818	* @param cbRegion The size of the region. Must be page aligned.
2819	* @param hType The physical handler callback type.
2820	* @param pvUserR3 User parameter for ring-3 context callbacks.
2821	* @param pvUserR0 User parameter for ring-0 context callbacks.
2822	* @param pvUserRC User parameter for raw-mode context callbacks.
2823	* @param pszDesc The description.
2824	*
2825	* @thread EMT
2826	*
2827	* @sa PGMR3PhysMMIORegister, PGMR3PhysMMIO2Register,
2828	* PGMR3PhysMMIOExMap, PGMR3PhysMMIOExUnmap, PGMR3PhysMMIOExDeregister.
2829	*/
2830	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion,
2831	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
2832	const char *pszDesc)
2833	{
2834	/*
2835	* Validate input.
2836	*/
2837	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2838	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2839	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
2840	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2841	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2842	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2843	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion) == NULL, VERR_ALREADY_EXISTS);
2844	AssertReturn(!(cbRegion & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2845	AssertReturn(cbRegion, VERR_INVALID_PARAMETER);
2846
2847	const uint32_t cPages = cbRegion >> PAGE_SHIFT;
2848	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cbRegion, VERR_INVALID_PARAMETER);
2849	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
2850
2851	/*
2852	* For the 2nd+ instance, mangle the description string so it's unique.
2853	*/
2854	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
2855	{
2856	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
2857	if (!pszDesc)
2858	return VERR_NO_MEMORY;
2859	}
2860
2861	/*
2862	* Register the MMIO callbacks.
2863	*/
2864	PPGMPHYSHANDLER pPhysHandler;
2865	int rc = pgmHandlerPhysicalExCreate(pVM, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc, &pPhysHandler);
2866	if (RT_SUCCESS(rc))
2867	{
2868	/*
2869	* Create the registered MMIO range record for it.
2870	*/
2871	PPGMREGMMIORANGE pNew;
2872	rc = pgmR3PhysMMIOExCreate(pVM, pDevIns, iSubDev, iRegion, cbRegion, pszDesc, &pNew);
2873	if (RT_SUCCESS(rc))
2874	{
2875	Assert(!(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
2876
2877	/*
2878	* Intialize the page structures and set up physical handlers (one for each chunk).
2879	*/
2880	for (PPGMREGMMIORANGE pCur = pNew; pCur != NULL && RT_SUCCESS(rc); pCur = pCur->pNextR3)
2881	{
2882	if (pCur == pNew)
2883	pCur->pPhysHandlerR3 = pPhysHandler;
2884	else
2885	rc = pgmHandlerPhysicalExDup(pVM, pPhysHandler, &pCur->pPhysHandlerR3);
2886
2887	uint32_t iPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
2888	while (iPage-- > 0)
2889	PGM_PAGE_INIT_ZERO(&pCur->RamRange.aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2890	}
2891	if (RT_SUCCESS(rc))
2892	{
2893	/*
2894	* Update the page count stats, link the registration and we're done.
2895	*/
2896	pVM->pgm.s.cAllPages += cPages;
2897	pVM->pgm.s.cPureMmioPages += cPages;
2898
2899	pgmR3PhysMMIOExLink(pVM, pNew);
2900	return VINF_SUCCESS;
2901	}
2902
2903	/*
2904	* Clean up in case we're out of memory for extra access handlers.
2905	*/
2906	while (pNew != NULL)
2907	{
2908	PPGMREGMMIORANGE pFree = pNew;
2909	pNew = pFree->pNextR3;
2910
2911	if (pFree->pPhysHandlerR3)
2912	{
2913	pgmHandlerPhysicalExDestroy(pVM, pFree->pPhysHandlerR3);
2914	pFree->pPhysHandlerR3 = NULL;
2915	}
2916
2917	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
2918	{
2919	const size_t cbRange = RT_OFFSETOF(PGMREGMMIORANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
2920	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2921	SUPR3PageFreeEx(pFree, cChunkPages);
2922	}
2923	}
2924	}
2925	else
2926	pgmHandlerPhysicalExDestroy(pVM, pPhysHandler);
2927	}
2928	return rc;
2929	}
2930
2931
2932	/**
2933	* Allocate and register an MMIO2 region.
2934	*
2935	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2936	* associated with a device. It is also non-shared memory with a permanent
2937	* ring-3 mapping and page backing (presently).
2938	*
2939	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
2940	* the VM, in which case we'll drop the base memory pages. Presently we will
2941	* make no attempt to preserve anything that happens to be present in the base
2942	* memory that is replaced, this is of course incorrect but it's too much
2943	* effort.
2944	*
2945	* @returns VBox status code.
2946	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2947	* memory.
2948	* @retval VERR_ALREADY_EXISTS if the region already exists.
2949	*
2950	* @param pVM The cross context VM structure.
2951	* @param pDevIns The device instance owning the region.
2952	* @param iSubDev The sub-device number.
2953	* @param iRegion The region number. If the MMIO2 memory is a PCI
2954	* I/O region this number has to be the number of that
2955	* region. Otherwise it can be any number safe
2956	* UINT8_MAX.
2957	* @param cb The size of the region. Must be page aligned.
2958	* @param fFlags Reserved for future use, must be zero.
2959	* @param ppv Where to store the pointer to the ring-3 mapping of
2960	* the memory.
2961	* @param pszDesc The description.
2962	* @thread EMT
2963	*/
2964	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2965	uint32_t fFlags, void *ppv, const char pszDesc)
2966	{
2967	/*
2968	* Validate input.
2969	*/
2970	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2971	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2972	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
2973	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2974	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
2975	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2976	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2977	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion) == NULL, VERR_ALREADY_EXISTS);
2978	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2979	AssertReturn(cb, VERR_INVALID_PARAMETER);
2980	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
2981
2982	const uint32_t cPages = cb >> PAGE_SHIFT;
2983	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
2984	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
2985
2986	/*
2987	* For the 2nd+ instance, mangle the description string so it's unique.
2988	*/
2989	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
2990	{
2991	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
2992	if (!pszDesc)
2993	return VERR_NO_MEMORY;
2994	}
2995
2996	/*
2997	* Allocate an MMIO2 range ID (not freed on failure).
2998	*
2999	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID, so
3000	* the IDs goes from 1 thru PGM_MMIO2_MAX_RANGES.
3001	*/
3002	unsigned cChunks = pgmR3PhysMMIOExCalcChunkCount(pVM, cb, NULL, NULL);
3003	pgmLock(pVM);
3004	uint8_t idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
3005	unsigned cNewMmio2Regions = pVM->pgm.s.cMmio2Regions + cChunks;
3006	if (cNewMmio2Regions > PGM_MMIO2_MAX_RANGES)
3007	{
3008	pgmUnlock(pVM);
3009	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
3010	}
3011	pVM->pgm.s.cMmio2Regions = cNewMmio2Regions;
3012	pgmUnlock(pVM);
3013
3014	/*
3015	* Try reserve and allocate the backing memory first as this is what is
3016	* most likely to fail.
3017	*/
3018	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
3019	if (RT_SUCCESS(rc))
3020	{
3021	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
3022	if (RT_SUCCESS(rc))
3023	{
3024	void *pvPages;
3025	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
3026	if (RT_SUCCESS(rc))
3027	{
3028	memset(pvPages, 0, cPages * PAGE_SIZE);
3029
3030	/*
3031	* Create the registered MMIO range record for it.
3032	*/
3033	PPGMREGMMIORANGE pNew;
3034	rc = pgmR3PhysMMIOExCreate(pVM, pDevIns, iSubDev, iRegion, cb, pszDesc, &pNew);
3035	if (RT_SUCCESS(rc))
3036	{
3037	uint32_t iSrcPage = 0;
3038	uint8_t pbCurPages = (uint8_t )pvPages;
3039	for (PPGMREGMMIORANGE pCur = pNew; pCur; pCur = pCur->pNextR3)
3040	{
3041	pCur->pvR3 = pbCurPages;
3042	pCur->RamRange.pvR3 = pbCurPages;
3043	pCur->idMmio2 = idMmio2;
3044	pCur->fFlags \|= PGMREGMMIORANGE_F_MMIO2;
3045
3046	uint32_t iDstPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3047	while (iDstPage-- > 0)
3048	{
3049	PGM_PAGE_INIT(&pNew->RamRange.aPages[iDstPage],
3050	paPages[iDstPage + iSrcPage].Phys,
3051	PGM_MMIO2_PAGEID_MAKE(idMmio2, iDstPage),
3052	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
3053	}
3054
3055	/* advance. */
3056	iSrcPage += pCur->RamRange.cb >> X86_PAGE_SHIFT;
3057	pbCurPages += pCur->RamRange.cb;
3058	idMmio2++;
3059	}
3060
3061	RTMemTmpFree(paPages);
3062
3063	/*
3064	* Update the page count stats, link the registration and we're done.
3065	*/
3066	pVM->pgm.s.cAllPages += cPages;
3067	pVM->pgm.s.cPrivatePages += cPages;
3068
3069	pgmR3PhysMMIOExLink(pVM, pNew);
3070
3071	*ppv = pvPages;
3072	return VINF_SUCCESS;
3073	}
3074
3075	SUPR3PageFreeEx(pvPages, cPages);
3076	}
3077	}
3078	RTMemTmpFree(paPages);
3079	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
3080	}
3081	if (pDevIns->iInstance > 0)
3082	MMR3HeapFree((void *)pszDesc);
3083	return rc;
3084	}
3085
3086
3087	/**
3088	* Deregisters and frees an MMIO2 region or a pre-registered MMIO region
3089	*
3090	* Any physical (and virtual) access handlers registered for the region must
3091	* be deregistered before calling this function.
3092	*
3093	* @returns VBox status code.
3094	* @param pVM The cross context VM structure.
3095	* @param pDevIns The device instance owning the region.
3096	* @param iSubDev The sub-device number. Pass UINT32_MAX for wildcard
3097	* matching.
3098	* @param iRegion The region. Pass UINT32_MAX for wildcard matching.
3099	*/
3100	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion)
3101	{
3102	/*
3103	* Validate input.
3104	*/
3105	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3106	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3107	AssertReturn(iSubDev <= UINT8_MAX \|\| iSubDev == UINT32_MAX, VERR_INVALID_PARAMETER);
3108	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
3109
3110	/*
3111	* The loop here scanning all registrations will make sure that multi-chunk ranges
3112	* get properly deregistered, though it's original purpose was the wildcard iRegion.
3113	*/
3114	pgmLock(pVM);
3115	int rc = VINF_SUCCESS;
3116	unsigned cFound = 0;
3117	PPGMREGMMIORANGE pPrev = NULL;
3118	PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3;
3119	while (pCur)
3120	{
3121	if ( pCur->pDevInsR3 == pDevIns
3122	&& ( iRegion == UINT32_MAX
3123	\|\| pCur->iRegion == iRegion)
3124	&& ( iSubDev == UINT32_MAX
3125	\|\| pCur->iSubDev == iSubDev) )
3126	{
3127	cFound++;
3128
3129	/*
3130	* Unmap it if it's mapped.
3131	*/
3132	if (pCur->fFlags & PGMREGMMIORANGE_F_MAPPED)
3133	{
3134	int rc2 = PGMR3PhysMMIOExUnmap(pVM, pCur->pDevInsR3, pCur->iSubDev, pCur->iRegion, pCur->RamRange.GCPhys);
3135	AssertRC(rc2);
3136	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3137	rc = rc2;
3138	}
3139
3140	/*
3141	* Must tell IOM about MMIO (first one only).
3142	*/
3143	if ((pCur->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK)) == PGMREGMMIORANGE_F_MMIO2)
3144	IOMR3MmioExNotifyDeregistered(pVM, pCur->pPhysHandlerR3->pvUserR3);
3145
3146	/*
3147	* Unlink it
3148	*/
3149	PPGMREGMMIORANGE pNext = pCur->pNextR3;
3150	if (pPrev)
3151	pPrev->pNextR3 = pNext;
3152	else
3153	pVM->pgm.s.pRegMmioRangesR3 = pNext;
3154	pCur->pNextR3 = NULL;
3155
3156	uint8_t idMmio2 = pCur->idMmio2;
3157	if (idMmio2 != UINT8_MAX)
3158	{
3159	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
3160	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
3161	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
3162	}
3163
3164	/*
3165	* Free the memory.
3166	*/
3167	uint32_t const cPages = pCur->cbReal >> PAGE_SHIFT;
3168	if (pCur->fFlags & PGMREGMMIORANGE_F_MMIO2)
3169	{
3170	int rc2 = SUPR3PageFreeEx(pCur->pvR3, cPages);
3171	AssertRC(rc2);
3172	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3173	rc = rc2;
3174
3175	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
3176	AssertRC(rc2);
3177	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3178	rc = rc2;
3179	}
3180
3181	/* we're leaking hyper memory here if done at runtime. */
3182	#ifdef VBOX_STRICT
3183	VMSTATE const enmState = VMR3GetState(pVM);
3184	AssertMsg( enmState == VMSTATE_POWERING_OFF
3185	\|\| enmState == VMSTATE_POWERING_OFF_LS
3186	\|\| enmState == VMSTATE_OFF
3187	\|\| enmState == VMSTATE_OFF_LS
3188	\|\| enmState == VMSTATE_DESTROYING
3189	\|\| enmState == VMSTATE_TERMINATED
3190	\|\| enmState == VMSTATE_CREATING
3191	, ("%s\n", VMR3GetStateName(enmState)));
3192	#endif
3193
3194	const bool fIsMmio2 = RT_BOOL(pCur->fFlags & PGMREGMMIORANGE_F_MMIO2);
3195	if (pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3196	{
3197	const size_t cbRange = RT_OFFSETOF(PGMREGMMIORANGE, RamRange.aPages[cPages]);
3198	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3199	SUPR3PageFreeEx(pCur, cChunkPages);
3200	}
3201	/*else
3202	{
3203	rc = MMHyperFree(pVM, pCur); - does not work, see the alloc call.
3204	AssertRCReturn(rc, rc);
3205	} */
3206
3207
3208	/* update page count stats */
3209	pVM->pgm.s.cAllPages -= cPages;
3210	if (fIsMmio2)
3211	pVM->pgm.s.cPrivatePages -= cPages;
3212	else
3213	pVM->pgm.s.cPureMmioPages -= cPages;
3214
3215	/* next */
3216	pCur = pNext;
3217	}
3218	else
3219	{
3220	pPrev = pCur;
3221	pCur = pCur->pNextR3;
3222	}
3223	}
3224	pgmPhysInvalidatePageMapTLB(pVM);
3225	pgmUnlock(pVM);
3226	return !cFound && iRegion != UINT32_MAX && iSubDev != UINT32_MAX ? VERR_NOT_FOUND : rc;
3227	}
3228
3229
3230	/**
3231	* Maps a MMIO2 region or a pre-registered MMIO region.
3232	*
3233	* This is done when a guest / the bios / state loading changes the
3234	* PCI config. The replacing of base memory has the same restrictions
3235	* as during registration, of course.
3236	*
3237	* @returns VBox status code.
3238	*
3239	* @param pVM The cross context VM structure.
3240	* @param pDevIns The device instance owning the region.
3241	* @param iSubDev The sub-device number of the registered region.
3242	* @param iRegion The index of the registered region.
3243	* @param GCPhys The guest-physical address to be remapped.
3244	*/
3245	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys)
3246	{
3247	/*
3248	* Validate input.
3249	*
3250	* Note! It's safe to walk the MMIO/MMIO2 list since registrations only
3251	* happens during VM construction.
3252	*/
3253	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3254	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3255	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3256	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3257	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3258	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3259	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3260
3261	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3262	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3263	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3264
3265	PPGMREGMMIORANGE pLastMmio = pFirstMmio;
3266	RTGCPHYS cbRange = 0;
3267	for (;;)
3268	{
3269	AssertReturn(!(pLastMmio->fFlags & PGMREGMMIORANGE_F_MAPPED), VERR_WRONG_ORDER);
3270	Assert(pLastMmio->RamRange.GCPhys == NIL_RTGCPHYS);
3271	Assert(pLastMmio->RamRange.GCPhysLast == NIL_RTGCPHYS);
3272	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3273	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3274	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3275	cbRange += pLastMmio->RamRange.cb;
3276	if (pLastMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3277	break;
3278	pLastMmio = pLastMmio->pNextR3;
3279	}
3280
3281	RTGCPHYS GCPhysLast = GCPhys + cbRange - 1;
3282	AssertLogRelReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3283
3284	/*
3285	* Find our location in the ram range list, checking for restriction
3286	* we don't bother implementing yet (partially overlapping, multiple
3287	* ram ranges).
3288	*/
3289	pgmLock(pVM);
3290
3291	AssertReturnStmt(!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED), pgmUnlock(pVM), VERR_WRONG_ORDER);
3292
3293	bool fRamExists = false;
3294	PPGMRAMRANGE pRamPrev = NULL;
3295	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3296	while (pRam && GCPhysLast >= pRam->GCPhys)
3297	{
3298	if ( GCPhys <= pRam->GCPhysLast
3299	&& GCPhysLast >= pRam->GCPhys)
3300	{
3301	/* Completely within? */
3302	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
3303	&& GCPhysLast <= pRam->GCPhysLast,
3304	("%RGp-%RGp (MMIOEx/%s) falls partly outside %RGp-%RGp (%s)\n",
3305	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc,
3306	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3307	pgmUnlock(pVM),
3308	VERR_PGM_RAM_CONFLICT);
3309
3310	/* Check that all the pages are RAM pages. */
3311	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3312	uint32_t cPagesLeft = cbRange >> PAGE_SHIFT;
3313	while (cPagesLeft-- > 0)
3314	{
3315	AssertLogRelMsgReturnStmt(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3316	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
3317	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc),
3318	pgmUnlock(pVM),
3319	VERR_PGM_RAM_CONFLICT);
3320	pPage++;
3321	}
3322
3323	/* There can only be one MMIO/MMIO2 chunk matching here! */
3324	AssertLogRelMsgReturnStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK,
3325	("%RGp-%RGp (MMIOEx/%s, flags %#X) consists of multiple chunks whereas the RAM somehow doesn't!\n",
3326	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3327	pgmUnlock(pVM),
3328	VERR_PGM_PHYS_MMIO_EX_IPE);
3329
3330	fRamExists = true;
3331	break;
3332	}
3333
3334	/* next */
3335	pRamPrev = pRam;
3336	pRam = pRam->pNextR3;
3337	}
3338	Log(("PGMR3PhysMMIOExMap: %RGp-%RGp fRamExists=%RTbool %s\n", GCPhys, GCPhysLast, fRamExists, pFirstMmio->RamRange.pszDesc));
3339
3340
3341	/*
3342	* Make the changes.
3343	*/
3344	RTGCPHYS GCPhysCur = GCPhys;
3345	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3346	{
3347	pCurMmio->RamRange.GCPhys = GCPhysCur;
3348	pCurMmio->RamRange.GCPhysLast = GCPhysCur + pCurMmio->RamRange.cb - 1;
3349	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3350	{
3351	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3352	break;
3353	}
3354	GCPhysCur += pCurMmio->RamRange.cb;
3355	}
3356
3357	if (fRamExists)
3358	{
3359	/*
3360	* Make all the pages in the range MMIO/ZERO pages, freeing any
3361	* RAM pages currently mapped here. This might not be 100% correct
3362	* for PCI memory, but we're doing the same thing for MMIO2 pages.
3363	*
3364	* We replace this MMIO/ZERO pages with real pages in the MMIO2 case.
3365	*/
3366	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK); /* Only one chunk */
3367
3368	int rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
3369	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
3370
3371	if (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2)
3372	{
3373	/* replace the pages, freeing all present RAM pages. */
3374	PPGMPAGE pPageSrc = &pFirstMmio->RamRange.aPages[0];
3375	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3376	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3377	while (cPagesLeft-- > 0)
3378	{
3379	Assert(PGM_PAGE_IS_MMIO(pPageDst));
3380
3381	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
3382	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
3383	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
3384	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
3385	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
3386	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
3387	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
3388	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
3389	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
3390
3391	pVM->pgm.s.cZeroPages--;
3392	GCPhys += PAGE_SIZE;
3393	pPageSrc++;
3394	pPageDst++;
3395	}
3396	}
3397
3398	/* Flush physical page map TLB. */
3399	pgmPhysInvalidatePageMapTLB(pVM);
3400
3401	/* Force a PGM pool flush as guest ram references have been changed. */
3402	/** @todo not entirely SMP safe; assuming for now the guest takes care of
3403	* this internally (not touch mapped mmio while changing the mapping). */
3404	PVMCPU pVCpu = VMMGetCpu(pVM);
3405	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3406	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3407	}
3408	else
3409	{
3410	/*
3411	* No RAM range, insert the ones prepared during registration.
3412	*/
3413	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3414	{
3415	/* Clear the tracking data of pages we're going to reactivate. */
3416	PPGMPAGE pPageSrc = &pCurMmio->RamRange.aPages[0];
3417	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3418	while (cPagesLeft-- > 0)
3419	{
3420	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
3421	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
3422	pPageSrc++;
3423	}
3424
3425	/* link in the ram range */
3426	pgmR3PhysLinkRamRange(pVM, &pCurMmio->RamRange, pRamPrev);
3427
3428	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3429	{
3430	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3431	break;
3432	}
3433	pRamPrev = &pCurMmio->RamRange;
3434	}
3435	}
3436
3437	/*
3438	* Register the access handler if plain MMIO.
3439	*
3440	* We must register access handlers for each range since the access handler
3441	* code refuses to deal with multiple ranges (and we can).
3442	*/
3443	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2))
3444	{
3445	int rc = VINF_SUCCESS;
3446	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3447	{
3448	Assert(!(pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED));
3449	rc = pgmHandlerPhysicalExRegister(pVM, pCurMmio->pPhysHandlerR3, pCurMmio->RamRange.GCPhys,
3450	pCurMmio->RamRange.GCPhysLast);
3451	if (RT_FAILURE(rc))
3452	break;
3453	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_MAPPED; /* Use this to mark that the handler is registered. */
3454	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3455	{
3456	rc = IOMR3MmioExNotifyMapped(pVM, pFirstMmio->pPhysHandlerR3->pvUserR3, GCPhys);
3457	break;
3458	}
3459	}
3460	if (RT_FAILURE(rc))
3461	{
3462	/* Almost impossible, but try clean up properly and get out of here. */
3463	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3464	{
3465	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED)
3466	{
3467	pCurMmio->fFlags &= ~PGMREGMMIORANGE_F_MAPPED;
3468	pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3);
3469	}
3470
3471	if (!fRamExists)
3472	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3473	else
3474	{
3475	Assert(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK); /* Only one chunk */
3476
3477	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3478	PPGMPAGE pPageDst = &pRam->aPages[(pCurMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3479	while (cPagesLeft-- > 0)
3480	{
3481	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3482	pPageDst++;
3483	}
3484	}
3485
3486	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3487	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3488	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3489	break;
3490	}
3491
3492	pgmUnlock(pVM);
3493	return rc;
3494	}
3495	}
3496
3497	/*
3498	* We're good, set the flags and invalid the mapping TLB.
3499	*/
3500	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3501	{
3502	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_MAPPED;
3503	if (fRamExists)
3504	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_OVERLAPPING;
3505	else
3506	pCurMmio->fFlags &= ~PGMREGMMIORANGE_F_OVERLAPPING;
3507	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3508	break;
3509	}
3510	pgmPhysInvalidatePageMapTLB(pVM);
3511
3512	pgmUnlock(pVM);
3513
3514	#ifdef VBOX_WITH_REM
3515	/*
3516	* Inform REM without holding the PGM lock.
3517	*/
3518	if (!fRamExists && (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2))
3519	REMR3NotifyPhysRamRegister(pVM, GCPhys, cbRange, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
3520	#endif
3521	return VINF_SUCCESS;
3522	}
3523
3524
3525	/**
3526	* Unmaps a MMIO2 or a pre-registered MMIO region.
3527	*
3528	* This is done when a guest / the bios / state loading changes the
3529	* PCI config. The replacing of base memory has the same restrictions
3530	* as during registration, of course.
3531	*/
3532	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys)
3533	{
3534	/*
3535	* Validate input
3536	*/
3537	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3538	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3539	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3540	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3541	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3542	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3543	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3544
3545	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3546	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3547	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3548
3549	PPGMREGMMIORANGE pLastMmio = pFirstMmio;
3550	RTGCPHYS cbRange = 0;
3551	for (;;)
3552	{
3553	AssertReturn(pLastMmio->fFlags & PGMREGMMIORANGE_F_MAPPED, VERR_WRONG_ORDER);
3554	AssertReturn(pLastMmio->RamRange.GCPhys == GCPhys + cbRange, VERR_INVALID_PARAMETER);
3555	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3556	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3557	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3558	cbRange += pLastMmio->RamRange.cb;
3559	if (pLastMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3560	break;
3561	pLastMmio = pLastMmio->pNextR3;
3562	}
3563
3564	Log(("PGMR3PhysMMIOExUnmap: %RGp-%RGp %s\n",
3565	pFirstMmio->RamRange.GCPhys, pLastMmio->RamRange.GCPhysLast, pFirstMmio->RamRange.pszDesc));
3566
3567	int rc = pgmLock(pVM);
3568	AssertRCReturn(rc, rc);
3569	AssertReturnStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED, pgmUnlock(pVM), VERR_WRONG_ORDER);
3570
3571	/*
3572	* If plain MMIO, we must deregister the handlers first.
3573	*/
3574	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2))
3575	{
3576	PPGMREGMMIORANGE pCurMmio = pFirstMmio;
3577	rc = pgmHandlerPhysicalExDeregister(pVM, pFirstMmio->pPhysHandlerR3);
3578	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
3579	while (!(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK))
3580	{
3581	pCurMmio = pCurMmio->pNextR3;
3582	rc = pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3);
3583	AssertRCReturnStmt(rc, pgmUnlock(pVM), VERR_PGM_PHYS_MMIO_EX_IPE);
3584	}
3585
3586	IOMR3MmioExNotifyUnmapped(pVM, pFirstMmio->pPhysHandlerR3->pvUserR3, GCPhys);
3587	}
3588
3589	/*
3590	* Unmap it.
3591	*/
3592	#ifdef VBOX_WITH_REM
3593	RTGCPHYS GCPhysRangeREM;
3594	bool fInformREM;
3595	#endif
3596	if (pFirstMmio->fFlags & PGMREGMMIORANGE_F_OVERLAPPING)
3597	{
3598	/*
3599	* We've replaced RAM, replace with zero pages.
3600	*
3601	* Note! This is where we might differ a little from a real system, because
3602	* it's likely to just show the RAM pages as they were before the
3603	* MMIO/MMIO2 region was mapped here.
3604	*/
3605	/* Only one chunk allowed when overlapping! */
3606	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK);
3607
3608	/* Restore the RAM pages we've replaced. */
3609	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3610	while (pRam->GCPhys > pFirstMmio->RamRange.GCPhysLast)
3611	pRam = pRam->pNextR3;
3612
3613	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3614	if (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2)
3615	pVM->pgm.s.cZeroPages += cPagesLeft;
3616
3617	PPGMPAGE pPageDst = &pRam->aPages[(pFirstMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3618	while (cPagesLeft-- > 0)
3619	{
3620	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3621	pPageDst++;
3622	}
3623
3624	/* Flush physical page map TLB. */
3625	pgmPhysInvalidatePageMapTLB(pVM);
3626	#ifdef VBOX_WITH_REM
3627	GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
3628	fInformREM = false;
3629	#endif
3630
3631	/* Update range state. */
3632	pFirstMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3633	pFirstMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3634	pFirstMmio->fFlags &= ~(PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MAPPED);
3635	}
3636	else
3637	{
3638	/*
3639	* Unlink the chunks related to the MMIO/MMIO2 region.
3640	*/
3641	#ifdef VBOX_WITH_REM
3642	GCPhysRangeREM = pFirstMmio->RamRange.GCPhys;
3643	fInformREM = RT_BOOL(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2);
3644	#endif
3645	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3646	{
3647	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3648	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3649	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3650	pCurMmio->fFlags &= ~(PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MAPPED);
3651	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3652	break;
3653	}
3654	}
3655
3656	/* Force a PGM pool flush as guest ram references have been changed. */
3657	/** @todo not entirely SMP safe; assuming for now the guest takes care
3658	* of this internally (not touch mapped mmio while changing the
3659	* mapping). */
3660	PVMCPU pVCpu = VMMGetCpu(pVM);
3661	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3662	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3663
3664	pgmPhysInvalidatePageMapTLB(pVM);
3665	pgmPhysInvalidRamRangeTlbs(pVM);
3666
3667	pgmUnlock(pVM);
3668
3669	#ifdef VBOX_WITH_REM
3670	/*
3671	* Inform REM without holding the PGM lock.
3672	*/
3673	if (fInformREM)
3674	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRange);
3675	#endif
3676
3677	return VINF_SUCCESS;
3678	}
3679
3680
3681	/**
3682	* Reduces the mapping size of a MMIO2 or pre-registered MMIO region.
3683	*
3684	* This is mainly for dealing with old saved states after changing the default
3685	* size of a mapping region. See PGMDevHlpMMIOExReduce and
3686	* PDMPCIDEV::pfnRegionLoadChangeHookR3.
3687	*
3688	* The region must not currently be mapped when making this call. The VM state
3689	* must be state restore or VM construction.
3690	*
3691	* @returns VBox status code.
3692	* @param pVM The cross context VM structure.
3693	* @param pDevIns The device instance owning the region.
3694	* @param iSubDev The sub-device number of the registered region.
3695	* @param iRegion The index of the registered region.
3696	* @param cbRegion The new mapping size.
3697	*/
3698	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion)
3699	{
3700	/*
3701	* Validate input
3702	*/
3703	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3704	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3705	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3706	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3707	AssertReturn(cbRegion >= X86_PAGE_SIZE, VERR_INVALID_PARAMETER);
3708	AssertReturn(!(cbRegion & X86_PAGE_OFFSET_MASK), VERR_UNSUPPORTED_ALIGNMENT);
3709	VMSTATE enmVmState = VMR3GetState(pVM);
3710	AssertLogRelMsgReturn( enmVmState == VMSTATE_CREATING
3711	\|\| enmVmState == VMSTATE_LOADING,
3712	("enmVmState=%d (%s)\n", enmVmState, VMR3GetStateName(enmVmState)),
3713	VERR_VM_INVALID_VM_STATE);
3714
3715	int rc = pgmLock(pVM);
3716	AssertRCReturn(rc, rc);
3717
3718	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3719	if (pFirstMmio)
3720	{
3721	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3722	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED))
3723	{
3724	/*
3725	* NOTE! Current implementation does not support multiple ranges.
3726	* Implement when there is a real world need and thus a testcase.
3727	*/
3728	AssertLogRelMsgStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK,
3729	("%s: %#x\n", pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3730	rc = VERR_NOT_SUPPORTED);
3731	if (RT_SUCCESS(rc))
3732	{
3733	/*
3734	* Make the change.
3735	*/
3736	Log(("PGMR3PhysMMIOExReduce: %s changes from %RGp bytes (%RGp) to %RGp bytes.\n",
3737	pFirstMmio->RamRange.pszDesc, pFirstMmio->RamRange.cb, pFirstMmio->cbReal, cbRegion));
3738
3739	AssertLogRelMsgStmt(cbRegion <= pFirstMmio->cbReal,
3740	("%s: cbRegion=%#RGp cbReal=%#RGp\n", pFirstMmio->RamRange.pszDesc, cbRegion, pFirstMmio->cbReal),
3741	rc = VERR_OUT_OF_RANGE);
3742	if (RT_SUCCESS(rc))
3743	{
3744	pFirstMmio->RamRange.cb = cbRegion;
3745	}
3746	}
3747	}
3748	else
3749	rc = VERR_WRONG_ORDER;
3750	}
3751	else
3752	rc = VERR_NOT_FOUND;
3753
3754	pgmUnlock(pVM);
3755	return rc;
3756	}
3757
3758
3759	/**
3760	* Checks if the given address is an MMIO2 or pre-registered MMIO base address
3761	* or not.
3762	*
3763	* @returns true/false accordingly.
3764	* @param pVM The cross context VM structure.
3765	* @param pDevIns The owner of the memory, optional.
3766	* @param GCPhys The address to check.
3767	*/
3768	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
3769	{
3770	/*
3771	* Validate input
3772	*/
3773	VM_ASSERT_EMT_RETURN(pVM, false);
3774	AssertPtrReturn(pDevIns, false);
3775	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
3776	AssertReturn(GCPhys != 0, false);
3777	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
3778
3779	/*
3780	* Search the list.
3781	*/
3782	pgmLock(pVM);
3783	for (PPGMREGMMIORANGE pCurMmio = pVM->pgm.s.pRegMmioRangesR3; pCurMmio; pCurMmio = pCurMmio->pNextR3)
3784	if (pCurMmio->RamRange.GCPhys == GCPhys)
3785	{
3786	Assert(pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED);
3787	bool fRet = RT_BOOL(pCurMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3788	pgmUnlock(pVM);
3789	return fRet;
3790	}
3791	pgmUnlock(pVM);
3792	return false;
3793	}
3794
3795
3796	/**
3797	* Gets the HC physical address of a page in the MMIO2 region.
3798	*
3799	* This is API is intended for MMHyper and shouldn't be called
3800	* by anyone else...
3801	*
3802	* @returns VBox status code.
3803	* @param pVM The cross context VM structure.
3804	* @param pDevIns The owner of the memory, optional.
3805	* @param iSubDev Sub-device number.
3806	* @param iRegion The region.
3807	* @param off The page expressed an offset into the MMIO2 region.
3808	* @param pHCPhys Where to store the result.
3809	*/
3810	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
3811	RTGCPHYS off, PRTHCPHYS pHCPhys)
3812	{
3813	/*
3814	* Validate input
3815	*/
3816	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3817	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3818	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3819	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3820
3821	pgmLock(pVM);
3822	PPGMREGMMIORANGE pCurMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3823	AssertReturn(pCurMmio, VERR_NOT_FOUND);
3824	AssertReturn(pCurMmio->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK), VERR_WRONG_TYPE);
3825
3826	while ( off >= pCurMmio->RamRange.cb
3827	&& !(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK))
3828	{
3829	off -= pCurMmio->RamRange.cb;
3830	pCurMmio = pCurMmio->pNextR3;
3831	}
3832	AssertReturn(off < pCurMmio->RamRange.cb, VERR_INVALID_PARAMETER);
3833
3834	PCPGMPAGE pPage = &pCurMmio->RamRange.aPages[off >> PAGE_SHIFT];
3835	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3836	pgmUnlock(pVM);
3837	return VINF_SUCCESS;
3838	}
3839
3840
3841	/**
3842	* Maps a portion of an MMIO2 region into kernel space (host).
3843	*
3844	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
3845	* or the VM is terminated.
3846	*
3847	* @return VBox status code.
3848	*
3849	* @param pVM The cross context VM structure.
3850	* @param pDevIns The device owning the MMIO2 memory.
3851	* @param iSubDev The sub-device number.
3852	* @param iRegion The region.
3853	* @param off The offset into the region. Must be page aligned.
3854	* @param cb The number of bytes to map. Must be page aligned.
3855	* @param pszDesc Mapping description.
3856	* @param pR0Ptr Where to store the R0 address.
3857	*/
3858	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
3859	RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr)
3860	{
3861	/*
3862	* Validate input.
3863	*/
3864	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3865	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3866	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3867	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3868
3869	PPGMREGMMIORANGE pFirstRegMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3870	AssertReturn(pFirstRegMmio, VERR_NOT_FOUND);
3871	AssertReturn(pFirstRegMmio->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK), VERR_WRONG_TYPE);
3872	AssertReturn(off < pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
3873	AssertReturn(cb <= pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
3874	AssertReturn(off + cb <= pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
3875	NOREF(pszDesc);
3876
3877	/*
3878	* Pass the request on to the support library/driver.
3879	*/
3880	int rc = SUPR3PageMapKernel(pFirstRegMmio->pvR3, off, cb, 0, pR0Ptr);
3881
3882	return rc;
3883	}
3884
3885
3886	/**
3887	* Worker for PGMR3PhysRomRegister.
3888	*
3889	* This is here to simplify lock management, i.e. the caller does all the
3890	* locking and we can simply return without needing to remember to unlock
3891	* anything first.
3892	*
3893	* @returns VBox status code.
3894	* @param pVM The cross context VM structure.
3895	* @param pDevIns The device instance owning the ROM.
3896	* @param GCPhys First physical address in the range.
3897	* Must be page aligned!
3898	* @param cb The size of the range (in bytes).
3899	* Must be page aligned!
3900	* @param pvBinary Pointer to the binary data backing the ROM image.
3901	* @param cbBinary The size of the binary data pvBinary points to.
3902	* This must be less or equal to @a cb.
3903	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
3904	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
3905	* @param pszDesc Pointer to description string. This must not be freed.
3906	*/
3907	static int pgmR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
3908	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
3909	{
3910	/*
3911	* Validate input.
3912	*/
3913	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3914	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
3915	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
3916	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
3917	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3918	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
3919	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3920	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
3921	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
3922
3923	const uint32_t cPages = cb >> PAGE_SHIFT;
3924
3925	/*
3926	* Find the ROM location in the ROM list first.
3927	*/
3928	PPGMROMRANGE pRomPrev = NULL;
3929	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
3930	while (pRom && GCPhysLast >= pRom->GCPhys)
3931	{
3932	if ( GCPhys <= pRom->GCPhysLast
3933	&& GCPhysLast >= pRom->GCPhys)
3934	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
3935	GCPhys, GCPhysLast, pszDesc,
3936	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
3937	VERR_PGM_RAM_CONFLICT);
3938	/* next */
3939	pRomPrev = pRom;
3940	pRom = pRom->pNextR3;
3941	}
3942
3943	/*
3944	* Find the RAM location and check for conflicts.
3945	*
3946	* Conflict detection is a bit different than for RAM
3947	* registration since a ROM can be located within a RAM
3948	* range. So, what we have to check for is other memory
3949	* types (other than RAM that is) and that we don't span
3950	* more than one RAM range (layz).
3951	*/
3952	bool fRamExists = false;
3953	PPGMRAMRANGE pRamPrev = NULL;
3954	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3955	while (pRam && GCPhysLast >= pRam->GCPhys)
3956	{
3957	if ( GCPhys <= pRam->GCPhysLast
3958	&& GCPhysLast >= pRam->GCPhys)
3959	{
3960	/* completely within? */
3961	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
3962	&& GCPhysLast <= pRam->GCPhysLast,
3963	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
3964	GCPhys, GCPhysLast, pszDesc,
3965	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3966	VERR_PGM_RAM_CONFLICT);
3967	fRamExists = true;
3968	break;
3969	}
3970
3971	/* next */
3972	pRamPrev = pRam;
3973	pRam = pRam->pNextR3;
3974	}
3975	if (fRamExists)
3976	{
3977	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3978	uint32_t cPagesLeft = cPages;
3979	while (cPagesLeft-- > 0)
3980	{
3981	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3982	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
3983	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
3984	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
3985	Assert(PGM_PAGE_IS_ZERO(pPage));
3986	pPage++;
3987	}
3988	}
3989
3990	/*
3991	* Update the base memory reservation if necessary.
3992	*/
3993	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
3994	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
3995	cExtraBaseCost += cPages;
3996	if (cExtraBaseCost)
3997	{
3998	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
3999	if (RT_FAILURE(rc))
4000	return rc;
4001	}
4002
4003	/*
4004	* Allocate memory for the virgin copy of the RAM.
4005	*/
4006	PGMMALLOCATEPAGESREQ pReq;
4007	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
4008	AssertRCReturn(rc, rc);
4009
4010	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4011	{
4012	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
4013	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
4014	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
4015	}
4016
4017	rc = GMMR3AllocatePagesPerform(pVM, pReq);
4018	if (RT_FAILURE(rc))
4019	{
4020	GMMR3AllocatePagesCleanup(pReq);
4021	return rc;
4022	}
4023
4024	/*
4025	* Allocate the new ROM range and RAM range (if necessary).
4026	*/
4027	PPGMROMRANGE pRomNew;
4028	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
4029	if (RT_SUCCESS(rc))
4030	{
4031	PPGMRAMRANGE pRamNew = NULL;
4032	if (!fRamExists)
4033	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
4034	if (RT_SUCCESS(rc))
4035	{
4036	/*
4037	* Initialize and insert the RAM range (if required).
4038	*/
4039	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
4040	if (!fRamExists)
4041	{
4042	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
4043	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
4044	pRamNew->GCPhys = GCPhys;
4045	pRamNew->GCPhysLast = GCPhysLast;
4046	pRamNew->cb = cb;
4047	pRamNew->pszDesc = pszDesc;
4048	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
4049	pRamNew->pvR3 = NULL;
4050	pRamNew->paLSPages = NULL;
4051
4052	PPGMPAGE pPage = &pRamNew->aPages[0];
4053	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
4054	{
4055	PGM_PAGE_INIT(pPage,
4056	pReq->aPages[iPage].HCPhysGCPhys,
4057	pReq->aPages[iPage].idPage,
4058	PGMPAGETYPE_ROM,
4059	PGM_PAGE_STATE_ALLOCATED);
4060
4061	pRomPage->Virgin = *pPage;
4062	}
4063
4064	pVM->pgm.s.cAllPages += cPages;
4065	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
4066	}
4067	else
4068	{
4069	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4070	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
4071	{
4072	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_ROM);
4073	PGM_PAGE_SET_HCPHYS(pVM, pPage, pReq->aPages[iPage].HCPhysGCPhys);
4074	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
4075	PGM_PAGE_SET_PAGEID(pVM, pPage, pReq->aPages[iPage].idPage);
4076	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4077	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
4078	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
4079
4080	pRomPage->Virgin = *pPage;
4081	}
4082
4083	pRamNew = pRam;
4084
4085	pVM->pgm.s.cZeroPages -= cPages;
4086	}
4087	pVM->pgm.s.cPrivatePages += cPages;
4088
4089	/* Flush physical page map TLB. */
4090	pgmPhysInvalidatePageMapTLB(pVM);
4091
4092
4093	/*
4094	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
4095	*
4096	* If it's shadowed we'll register the handler after the ROM notification
4097	* so we get the access handler callbacks that we should. If it isn't
4098	* shadowed we'll do it the other way around to make REM use the built-in
4099	* ROM behavior and not the handler behavior (which is to route all access
4100	* to PGM atm).
4101	*/
4102	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4103	{
4104	#ifdef VBOX_WITH_REM
4105	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
4106	#endif
4107	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4108	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
4109	pszDesc);
4110	}
4111	else
4112	{
4113	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4114	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
4115	pszDesc);
4116	#ifdef VBOX_WITH_REM
4117	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
4118	#endif
4119	}
4120	if (RT_SUCCESS(rc))
4121	{
4122	/*
4123	* Copy the image over to the virgin pages.
4124	* This must be done after linking in the RAM range.
4125	*/
4126	size_t cbBinaryLeft = cbBinary;
4127	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
4128	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4129	{
4130	void *pvDstPage;
4131	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
4132	if (RT_FAILURE(rc))
4133	{
4134	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
4135	break;
4136	}
4137	if (cbBinaryLeft >= PAGE_SIZE)
4138	{
4139	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
4140	cbBinaryLeft -= PAGE_SIZE;
4141	}
4142	else
4143	{
4144	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
4145	if (cbBinaryLeft > 0)
4146	{
4147	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
4148	cbBinaryLeft = 0;
4149	}
4150	}
4151	}
4152	if (RT_SUCCESS(rc))
4153	{
4154	/*
4155	* Initialize the ROM range.
4156	* Note that the Virgin member of the pages has already been initialized above.
4157	*/
4158	pRomNew->GCPhys = GCPhys;
4159	pRomNew->GCPhysLast = GCPhysLast;
4160	pRomNew->cb = cb;
4161	pRomNew->fFlags = fFlags;
4162	pRomNew->idSavedState = UINT8_MAX;
4163	pRomNew->cbOriginal = cbBinary;
4164	pRomNew->pszDesc = pszDesc;
4165	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
4166	? pvBinary : RTMemDup(pvBinary, cbBinary);
4167	if (pRomNew->pvOriginal)
4168	{
4169	for (unsigned iPage = 0; iPage < cPages; iPage++)
4170	{
4171	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
4172	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
4173	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
4174	}
4175
4176	/* update the page count stats for the shadow pages. */
4177	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4178	{
4179	pVM->pgm.s.cZeroPages += cPages;
4180	pVM->pgm.s.cAllPages += cPages;
4181	}
4182
4183	/*
4184	* Insert the ROM range, tell REM and return successfully.
4185	*/
4186	pRomNew->pNextR3 = pRom;
4187	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4188	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
4189
4190	if (pRomPrev)
4191	{
4192	pRomPrev->pNextR3 = pRomNew;
4193	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
4194	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
4195	}
4196	else
4197	{
4198	pVM->pgm.s.pRomRangesR3 = pRomNew;
4199	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
4200	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
4201	}
4202
4203	pgmPhysInvalidatePageMapTLB(pVM);
4204	GMMR3AllocatePagesCleanup(pReq);
4205	return VINF_SUCCESS;
4206	}
4207
4208	/* bail out */
4209	rc = VERR_NO_MEMORY;
4210	}
4211
4212	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
4213	AssertRC(rc2);
4214	}
4215
4216	if (!fRamExists)
4217	{
4218	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
4219	MMHyperFree(pVM, pRamNew);
4220	}
4221	}
4222	MMHyperFree(pVM, pRomNew);
4223	}
4224
4225	/** @todo Purge the mapping cache or something... */
4226	GMMR3FreeAllocatedPages(pVM, pReq);
4227	GMMR3AllocatePagesCleanup(pReq);
4228	return rc;
4229	}
4230
4231
4232	/**
4233	* Registers a ROM image.
4234	*
4235	* Shadowed ROM images requires double the amount of backing memory, so,
4236	* don't use that unless you have to. Shadowing of ROM images is process
4237	* where we can select where the reads go and where the writes go. On real
4238	* hardware the chipset provides means to configure this. We provide
4239	* PGMR3PhysProtectROM() for this purpose.
4240	*
4241	* A read-only copy of the ROM image will always be kept around while we
4242	* will allocate RAM pages for the changes on demand (unless all memory
4243	* is configured to be preallocated).
4244	*
4245	* @returns VBox status code.
4246	* @param pVM The cross context VM structure.
4247	* @param pDevIns The device instance owning the ROM.
4248	* @param GCPhys First physical address in the range.
4249	* Must be page aligned!
4250	* @param cb The size of the range (in bytes).
4251	* Must be page aligned!
4252	* @param pvBinary Pointer to the binary data backing the ROM image.
4253	* @param cbBinary The size of the binary data pvBinary points to.
4254	* This must be less or equal to @a cb.
4255	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4256	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4257	* @param pszDesc Pointer to description string. This must not be freed.
4258	*
4259	* @remark There is no way to remove the rom, automatically on device cleanup or
4260	* manually from the device yet. This isn't difficult in any way, it's
4261	* just not something we expect to be necessary for a while.
4262	*/
4263	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4264	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
4265	{
4266	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
4267	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
4268	pgmLock(pVM);
4269	int rc = pgmR3PhysRomRegister(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
4270	pgmUnlock(pVM);
4271	return rc;
4272	}
4273
4274
4275	/**
4276	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
4277	* that the virgin part is untouched.
4278	*
4279	* This is done after the normal memory has been cleared.
4280	*
4281	* ASSUMES that the caller owns the PGM lock.
4282	*
4283	* @param pVM The cross context VM structure.
4284	*/
4285	int pgmR3PhysRomReset(PVM pVM)
4286	{
4287	PGM_LOCK_ASSERT_OWNER(pVM);
4288	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4289	{
4290	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
4291
4292	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4293	{
4294	/*
4295	* Reset the physical handler.
4296	*/
4297	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
4298	AssertRCReturn(rc, rc);
4299
4300	/*
4301	* What we do with the shadow pages depends on the memory
4302	* preallocation option. If not enabled, we'll just throw
4303	* out all the dirty pages and replace them by the zero page.
4304	*/
4305	if (!pVM->pgm.s.fRamPreAlloc)
4306	{
4307	/* Free the dirty pages. */
4308	uint32_t cPendingPages = 0;
4309	PGMMFREEPAGESREQ pReq;
4310	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4311	AssertRCReturn(rc, rc);
4312
4313	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4314	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
4315	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
4316	{
4317	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
4318	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
4319	pRom->GCPhys + (iPage << PAGE_SHIFT));
4320	AssertLogRelRCReturn(rc, rc);
4321	}
4322
4323	if (cPendingPages)
4324	{
4325	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
4326	AssertLogRelRCReturn(rc, rc);
4327	}
4328	GMMR3FreePagesCleanup(pReq);
4329	}
4330	else
4331	{
4332	/* clear all the shadow pages. */
4333	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4334	{
4335	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
4336	continue;
4337	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
4338	void *pvDstPage;
4339	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4340	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
4341	if (RT_FAILURE(rc))
4342	break;
4343	ASMMemZeroPage(pvDstPage);
4344	}
4345	AssertRCReturn(rc, rc);
4346	}
4347	}
4348
4349	/*
4350	* Restore the original ROM pages after a saved state load.
4351	* Also, in strict builds check that ROM pages remain unmodified.
4352	*/
4353	#ifndef VBOX_STRICT
4354	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4355	#endif
4356	{
4357	size_t cbSrcLeft = pRom->cbOriginal;
4358	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
4359	uint32_t cRestored = 0;
4360	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
4361	{
4362	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4363	void const *pvDstPage;
4364	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
4365	if (RT_FAILURE(rc))
4366	break;
4367
4368	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
4369	{
4370	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4371	{
4372	void *pvDstPageW;
4373	rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPageW);
4374	AssertLogRelRCReturn(rc, rc);
4375	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
4376	cRestored++;
4377	}
4378	else
4379	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
4380	}
4381	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
4382	}
4383	if (cRestored > 0)
4384	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
4385	}
4386	}
4387
4388	/* Clear the ROM restore flag now as we only need to do this once after
4389	loading saved state. */
4390	pVM->pgm.s.fRestoreRomPagesOnReset = false;
4391
4392	return VINF_SUCCESS;
4393	}
4394
4395
4396	/**
4397	* Called by PGMR3Term to free resources.
4398	*
4399	* ASSUMES that the caller owns the PGM lock.
4400	*
4401	* @param pVM The cross context VM structure.
4402	*/
4403	void pgmR3PhysRomTerm(PVM pVM)
4404	{
4405	/*
4406	* Free the heap copy of the original bits.
4407	*/
4408	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4409	{
4410	if ( pRom->pvOriginal
4411	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
4412	{
4413	RTMemFree((void *)pRom->pvOriginal);
4414	pRom->pvOriginal = NULL;
4415	}
4416	}
4417	}
4418
4419
4420	/**
4421	* Change the shadowing of a range of ROM pages.
4422	*
4423	* This is intended for implementing chipset specific memory registers
4424	* and will not be very strict about the input. It will silently ignore
4425	* any pages that are not the part of a shadowed ROM.
4426	*
4427	* @returns VBox status code.
4428	* @retval VINF_PGM_SYNC_CR3
4429	*
4430	* @param pVM The cross context VM structure.
4431	* @param GCPhys Where to start. Page aligned.
4432	* @param cb How much to change. Page aligned.
4433	* @param enmProt The new ROM protection.
4434	*/
4435	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
4436	{
4437	/*
4438	* Check input
4439	*/
4440	if (!cb)
4441	return VINF_SUCCESS;
4442	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4443	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4444	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4445	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4446	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
4447
4448	/*
4449	* Process the request.
4450	*/
4451	pgmLock(pVM);
4452	int rc = VINF_SUCCESS;
4453	bool fFlushTLB = false;
4454	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4455	{
4456	if ( GCPhys <= pRom->GCPhysLast
4457	&& GCPhysLast >= pRom->GCPhys
4458	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
4459	{
4460	/*
4461	* Iterate the relevant pages and make necessary the changes.
4462	*/
4463	bool fChanges = false;
4464	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
4465	? pRom->cb >> PAGE_SHIFT
4466	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
4467	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
4468	iPage < cPages;
4469	iPage++)
4470	{
4471	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
4472	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
4473	{
4474	fChanges = true;
4475
4476	/* flush references to the page. */
4477	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT));
4478	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage,
4479	true /fFlushPTEs/, &fFlushTLB);
4480	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
4481	rc = rc2;
4482
4483	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
4484	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
4485
4486	pOld = pRamPage;
4487	pRamPage = pNew;
4488	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
4489	}
4490	pRomPage->enmProt = enmProt;
4491	}
4492
4493	/*
4494	* Reset the access handler if we made changes, no need
4495	* to optimize this.
4496	*/
4497	if (fChanges)
4498	{
4499	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
4500	if (RT_FAILURE(rc2))
4501	{
4502	pgmUnlock(pVM);
4503	AssertRC(rc);
4504	return rc2;
4505	}
4506	}
4507
4508	/* Advance - cb isn't updated. */
4509	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
4510	}
4511	}
4512	pgmUnlock(pVM);
4513	if (fFlushTLB)
4514	PGM_INVL_ALL_VCPU_TLBS(pVM);
4515
4516	return rc;
4517	}
4518
4519
4520	/**
4521	* Sets the Address Gate 20 state.
4522	*
4523	* @param pVCpu The cross context virtual CPU structure.
4524	* @param fEnable True if the gate should be enabled.
4525	* False if the gate should be disabled.
4526	*/
4527	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
4528	{
4529	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
4530	if (pVCpu->pgm.s.fA20Enabled != fEnable)
4531	{
4532	pVCpu->pgm.s.fA20Enabled = fEnable;
4533	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
4534	#ifdef VBOX_WITH_REM
4535	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
4536	#endif
4537	#ifdef PGM_WITH_A20
4538	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
4539	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4540	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
4541	HMFlushTLB(pVCpu);
4542	#endif
4543	IEMTlbInvalidateAllPhysical(pVCpu);
4544	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
4545	}
4546	}
4547
4548
4549	/**
4550	* Tree enumeration callback for dealing with age rollover.
4551	* It will perform a simple compression of the current age.
4552	*/
4553	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
4554	{
4555	/* Age compression - ASSUMES iNow == 4. */
4556	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4557	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
4558	pChunk->iLastUsed = 3;
4559	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
4560	pChunk->iLastUsed = 2;
4561	else if (pChunk->iLastUsed)
4562	pChunk->iLastUsed = 1;
4563	else /* iLastUsed = 0 */
4564	pChunk->iLastUsed = 4;
4565
4566	NOREF(pvUser);
4567	return 0;
4568	}
4569
4570
4571	/**
4572	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
4573	*/
4574	typedef struct PGMR3PHYSCHUNKUNMAPCB
4575	{
4576	PVM pVM; /*< Pointer to the VM. /
4577	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
4578	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
4579
4580
4581	/**
4582	* Callback used to find the mapping that's been unused for
4583	* the longest time.
4584	*/
4585	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
4586	{
4587	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4588	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
4589
4590	/*
4591	* Check for locks and compare when last used.
4592	*/
4593	if (pChunk->cRefs)
4594	return 0;
4595	if (pChunk->cPermRefs)
4596	return 0;
4597	if ( pArg->pChunk
4598	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
4599	return 0;
4600
4601	/*
4602	* Check that it's not in any of the TLBs.
4603	*/
4604	PVM pVM = pArg->pVM;
4605	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
4606	== pChunk->Core.Key)
4607	{
4608	pChunk = NULL;
4609	return 0;
4610	}
4611	#ifdef VBOX_STRICT
4612	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
4613	{
4614	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
4615	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
4616	}
4617	#endif
4618
4619	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
4620	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
4621	return 0;
4622
4623	pArg->pChunk = pChunk;
4624	return 0;
4625	}
4626
4627
4628	/**
4629	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
4630	*
4631	* The candidate will not be part of any TLBs, so no need to flush
4632	* anything afterwards.
4633	*
4634	* @returns Chunk id.
4635	* @param pVM The cross context VM structure.
4636	*/
4637	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
4638	{
4639	PGM_LOCK_ASSERT_OWNER(pVM);
4640
4641	/*
4642	* Enumerate the age tree starting with the left most node.
4643	*/
4644	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4645	PGMR3PHYSCHUNKUNMAPCB Args;
4646	Args.pVM = pVM;
4647	Args.pChunk = NULL;
4648	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
4649	Assert(Args.pChunk);
4650	if (Args.pChunk)
4651	{
4652	Assert(Args.pChunk->cRefs == 0);
4653	Assert(Args.pChunk->cPermRefs == 0);
4654	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4655	return Args.pChunk->Core.Key;
4656	}
4657
4658	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4659	return INT32_MAX;
4660	}
4661
4662
4663	/**
4664	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
4665	*
4666	* This is only called on one of the EMTs while the other ones are waiting for
4667	* it to complete this function.
4668	*
4669	* @returns VINF_SUCCESS (VBox strict status code).
4670	* @param pVM The cross context VM structure.
4671	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
4672	* @param pvUser User pointer. Unused
4673	*
4674	*/
4675	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
4676	{
4677	int rc = VINF_SUCCESS;
4678	pgmLock(pVM);
4679	NOREF(pVCpu); NOREF(pvUser);
4680
4681	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
4682	{
4683	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
4684	/** @todo also not really efficient to unmap a chunk that contains PD
4685	* or PT pages. */
4686	pgmR3PoolClearAllRendezvous(pVM, &pVM->aCpus[0], NULL /* no need to flush the REM TLB as we already did that above */);
4687
4688	/*
4689	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
4690	*/
4691	GMMMAPUNMAPCHUNKREQ Req;
4692	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
4693	Req.Hdr.cbReq = sizeof(Req);
4694	Req.pvR3 = NULL;
4695	Req.idChunkMap = NIL_GMM_CHUNKID;
4696	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
4697	if (Req.idChunkUnmap != INT32_MAX)
4698	{
4699	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
4700	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
4701	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
4702	if (RT_SUCCESS(rc))
4703	{
4704	/*
4705	* Remove the unmapped one.
4706	*/
4707	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
4708	AssertRelease(pUnmappedChunk);
4709	AssertRelease(!pUnmappedChunk->cRefs);
4710	AssertRelease(!pUnmappedChunk->cPermRefs);
4711	pUnmappedChunk->pv = NULL;
4712	pUnmappedChunk->Core.Key = UINT32_MAX;
4713	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
4714	MMR3HeapFree(pUnmappedChunk);
4715	#else
4716	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
4717	#endif
4718	pVM->pgm.s.ChunkR3Map.c--;
4719	pVM->pgm.s.cUnmappedChunks++;
4720
4721	/*
4722	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
4723	*/
4724	/** @todo We should not flush chunks which include cr3 mappings. */
4725	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4726	{
4727	PPGMCPU pPGM = &pVM->aCpus[idCpu].pgm.s;
4728
4729	pPGM->pGst32BitPdR3 = NULL;
4730	pPGM->pGstPaePdptR3 = NULL;
4731	pPGM->pGstAmd64Pml4R3 = NULL;
4732	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4733	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
4734	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
4735	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
4736	#endif
4737	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
4738	{
4739	pPGM->apGstPaePDsR3[i] = NULL;
4740	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4741	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
4742	#endif
4743	}
4744
4745	/* Flush REM TLBs. */
4746	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
4747	}
4748	#ifdef VBOX_WITH_REM
4749	/* Flush REM translation blocks. */
4750	REMFlushTBs(pVM);
4751	#endif
4752	}
4753	}
4754	}
4755	pgmUnlock(pVM);
4756	return rc;
4757	}
4758
4759	/**
4760	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
4761	*
4762	* @returns VBox status code.
4763	* @param pVM The cross context VM structure.
4764	*/
4765	void pgmR3PhysUnmapChunk(PVM pVM)
4766	{
4767	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
4768	AssertRC(rc);
4769	}
4770
4771
4772	/**
4773	* Maps the given chunk into the ring-3 mapping cache.
4774	*
4775	* This will call ring-0.
4776	*
4777	* @returns VBox status code.
4778	* @param pVM The cross context VM structure.
4779	* @param idChunk The chunk in question.
4780	* @param ppChunk Where to store the chunk tracking structure.
4781	*
4782	* @remarks Called from within the PGM critical section.
4783	* @remarks Can be called from any thread!
4784	*/
4785	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
4786	{
4787	int rc;
4788
4789	PGM_LOCK_ASSERT_OWNER(pVM);
4790
4791	/*
4792	* Move the chunk time forward.
4793	*/
4794	pVM->pgm.s.ChunkR3Map.iNow++;
4795	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
4796	{
4797	pVM->pgm.s.ChunkR3Map.iNow = 4;
4798	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
4799	}
4800
4801	/*
4802	* Allocate a new tracking structure first.
4803	*/
4804	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
4805	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
4806	#else
4807	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
4808	#endif
4809	AssertReturn(pChunk, VERR_NO_MEMORY);
4810	pChunk->Core.Key = idChunk;
4811	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
4812
4813	/*
4814	* Request the ring-0 part to map the chunk in question.
4815	*/
4816	GMMMAPUNMAPCHUNKREQ Req;
4817	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
4818	Req.Hdr.cbReq = sizeof(Req);
4819	Req.pvR3 = NULL;
4820	Req.idChunkMap = idChunk;
4821	Req.idChunkUnmap = NIL_GMM_CHUNKID;
4822
4823	/* Must be callable from any thread, so can't use VMMR3CallR0. */
4824	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
4825	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
4826	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
4827	if (RT_SUCCESS(rc))
4828	{
4829	pChunk->pv = Req.pvR3;
4830
4831	/*
4832	* If we're running out of virtual address space, then we should
4833	* unmap another chunk.
4834	*
4835	* Currently, an unmap operation requires that all other virtual CPUs
4836	* are idling and not by chance making use of the memory we're
4837	* unmapping. So, we create an async unmap operation here.
4838	*
4839	* Now, when creating or restoring a saved state this wont work very
4840	* well since we may want to restore all guest RAM + a little something.
4841	* So, we have to do the unmap synchronously. Fortunately for us
4842	* though, during these operations the other virtual CPUs are inactive
4843	* and it should be safe to do this.
4844	*/
4845	/** @todo Eventually we should lock all memory when used and do
4846	* map+unmap as one kernel call without any rendezvous or
4847	* other precautions. */
4848	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
4849	{
4850	switch (VMR3GetState(pVM))
4851	{
4852	case VMSTATE_LOADING:
4853	case VMSTATE_SAVING:
4854	{
4855	PVMCPU pVCpu = VMMGetCpu(pVM);
4856	if ( pVCpu
4857	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
4858	{
4859	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
4860	break;
4861	}
4862	}
4863	RT_FALL_THRU();
4864	default:
4865	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
4866	AssertRC(rc);
4867	break;
4868	}
4869	}
4870
4871	/*
4872	* Update the tree. We must do this after any unmapping to make sure
4873	* the chunk we're going to return isn't unmapped by accident.
4874	*/
4875	AssertPtr(Req.pvR3);
4876	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
4877	AssertRelease(fRc);
4878	pVM->pgm.s.ChunkR3Map.c++;
4879	pVM->pgm.s.cMappedChunks++;
4880	}
4881	else
4882	{
4883	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
4884	* should probably restrict ourselves on linux. */
4885	AssertRC(rc);
4886	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
4887	MMR3HeapFree(pChunk);
4888	#else
4889	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
4890	#endif
4891	pChunk = NULL;
4892	}
4893
4894	*ppChunk = pChunk;
4895	return rc;
4896	}
4897
4898
4899	/**
4900	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
4901	*
4902	* @returns see pgmR3PhysChunkMap.
4903	* @param pVM The cross context VM structure.
4904	* @param idChunk The chunk to map.
4905	*/
4906	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
4907	{
4908	PPGMCHUNKR3MAP pChunk;
4909	int rc;
4910
4911	pgmLock(pVM);
4912	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
4913	pgmUnlock(pVM);
4914	return rc;
4915	}
4916
4917
4918	/**
4919	* Invalidates the TLB for the ring-3 mapping cache.
4920	*
4921	* @param pVM The cross context VM structure.
4922	*/
4923	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
4924	{
4925	pgmLock(pVM);
4926	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
4927	{
4928	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
4929	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
4930	}
4931	/* The page map TLB references chunks, so invalidate that one too. */
4932	pgmPhysInvalidatePageMapTLB(pVM);
4933	pgmUnlock(pVM);
4934	}
4935
4936
4937	/**
4938	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE to allocate a large
4939	* (2MB) page for use with a nested paging PDE.
4940	*
4941	* @returns The following VBox status codes.
4942	* @retval VINF_SUCCESS on success.
4943	* @retval VINF_EM_NO_MEMORY if we're out of memory.
4944	*
4945	* @param pVM The cross context VM structure.
4946	* @param GCPhys GC physical start address of the 2 MB range
4947	*/
4948	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
4949	{
4950	#ifdef PGM_WITH_LARGE_PAGES
4951	uint64_t u64TimeStamp1, u64TimeStamp2;
4952
4953	pgmLock(pVM);
4954
4955	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
4956	u64TimeStamp1 = RTTimeMilliTS();
4957	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
4958	u64TimeStamp2 = RTTimeMilliTS();
4959	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
4960	if (RT_SUCCESS(rc))
4961	{
4962	Assert(pVM->pgm.s.cLargeHandyPages == 1);
4963
4964	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
4965	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
4966
4967	void *pv;
4968
4969	/* Map the large page into our address space.
4970	*
4971	* Note: assuming that within the 2 MB range:
4972	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
4973	* - user space mapping is continuous as well
4974	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
4975	*/
4976	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
4977	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", idPage, HCPhys, rc));
4978
4979	if (RT_SUCCESS(rc))
4980	{
4981	/*
4982	* Clear the pages.
4983	*/
4984	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
4985	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
4986	{
4987	ASMMemZeroPage(pv);
4988
4989	PPGMPAGE pPage;
4990	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
4991	AssertRC(rc);
4992
4993	Assert(PGM_PAGE_IS_ZERO(pPage));
4994	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRZPageReplaceZero);
4995	pVM->pgm.s.cZeroPages--;
4996
4997	/*
4998	* Do the PGMPAGE modifications.
4999	*/
5000	pVM->pgm.s.cPrivatePages++;
5001	PGM_PAGE_SET_HCPHYS(pVM, pPage, HCPhys);
5002	PGM_PAGE_SET_PAGEID(pVM, pPage, idPage);
5003	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
5004	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE);
5005	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5006	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5007
5008	/* Somewhat dirty assumption that page ids are increasing. */
5009	idPage++;
5010
5011	HCPhys += PAGE_SIZE;
5012	GCPhys += PAGE_SIZE;
5013
5014	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
5015
5016	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
5017	}
5018	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
5019
5020	/* Flush all TLBs. */
5021	PGM_INVL_ALL_VCPU_TLBS(pVM);
5022	pgmPhysInvalidatePageMapTLB(pVM);
5023	}
5024	pVM->pgm.s.cLargeHandyPages = 0;
5025	}
5026
5027	if (RT_SUCCESS(rc))
5028	{
5029	static uint32_t cTimeOut = 0;
5030	uint64_t u64TimeStampDelta = u64TimeStamp2 - u64TimeStamp1;
5031
5032	if (u64TimeStampDelta > 100)
5033	{
5034	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatLargePageOverflow);
5035	if ( ++cTimeOut > 10
5036	\|\| u64TimeStampDelta > 1000 /* more than one second forces an early retirement from allocating large pages. */)
5037	{
5038	/* If repeated attempts to allocate a large page takes more than 100 ms, then we fall back to normal 4k pages.
5039	* E.g. Vista 64 tries to move memory around, which takes a huge amount of time.
5040	*/
5041	LogRel(("PGMR3PhysAllocateLargePage: allocating large pages takes too long (last attempt %d ms; nr of timeouts %d); DISABLE\n", u64TimeStampDelta, cTimeOut));
5042	PGMSetLargePageUsage(pVM, false);
5043	}
5044	}
5045	else
5046	if (cTimeOut > 0)
5047	cTimeOut--;
5048	}
5049
5050	pgmUnlock(pVM);
5051	return rc;
5052	#else
5053	RT_NOREF(pVM, GCPhys);
5054	return VERR_NOT_IMPLEMENTED;
5055	#endif /* PGM_WITH_LARGE_PAGES */
5056	}
5057
5058
5059	/**
5060	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
5061	*
5062	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
5063	* signal and clear the out of memory condition. When contracted, this API is
5064	* used to try clear the condition when the user wants to resume.
5065	*
5066	* @returns The following VBox status codes.
5067	* @retval VINF_SUCCESS on success. FFs cleared.
5068	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
5069	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
5070	*
5071	* @param pVM The cross context VM structure.
5072	*
5073	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
5074	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
5075	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
5076	* handler.
5077	*/
5078	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
5079	{
5080	pgmLock(pVM);
5081
5082	/*
5083	* Allocate more pages, noting down the index of the first new page.
5084	*/
5085	uint32_t iClear = pVM->pgm.s.cHandyPages;
5086	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
5087	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
5088	int rcAlloc = VINF_SUCCESS;
5089	int rcSeed = VINF_SUCCESS;
5090	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5091	while (rc == VERR_GMM_SEED_ME)
5092	{
5093	void *pvChunk;
5094	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
5095	if (RT_SUCCESS(rc))
5096	{
5097	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
5098	if (RT_FAILURE(rc))
5099	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
5100	}
5101	if (RT_SUCCESS(rc))
5102	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5103	}
5104
5105	/** @todo we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
5106	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
5107	&& pVM->pgm.s.cHandyPages > 0)
5108	{
5109	/* Still handy pages left, so don't panic. */
5110	rc = VINF_SUCCESS;
5111	}
5112
5113	if (RT_SUCCESS(rc))
5114	{
5115	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
5116	Assert(pVM->pgm.s.cHandyPages > 0);
5117	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5118	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
5119
5120	#ifdef VBOX_STRICT
5121	uint32_t i;
5122	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
5123	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
5124	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
5125	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
5126	break;
5127	if (i != pVM->pgm.s.cHandyPages)
5128	{
5129	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
5130	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
5131	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
5132	RTAssertMsg2Add("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%\n", j,
5133	pVM->pgm.s.aHandyPages[j].idPage,
5134	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
5135	pVM->pgm.s.aHandyPages[j].idSharedPage,
5136	j == i ? " <---" : "");
5137	RTAssertPanic();
5138	}
5139	#endif
5140	/*
5141	* Clear the pages.
5142	*/
5143	while (iClear < pVM->pgm.s.cHandyPages)
5144	{
5145	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
5146	void *pv;
5147	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
5148	AssertLogRelMsgBreak(RT_SUCCESS(rc),
5149	("%u/%u: idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n",
5150	iClear, pVM->pgm.s.cHandyPages, pPage->idPage, pPage->HCPhysGCPhys, rc));
5151	ASMMemZeroPage(pv);
5152	iClear++;
5153	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
5154	}
5155	}
5156	else
5157	{
5158	uint64_t cAllocPages, cMaxPages, cBalloonPages;
5159
5160	/*
5161	* We should never get here unless there is a genuine shortage of
5162	* memory (or some internal error). Flag the error so the VM can be
5163	* suspended ASAP and the user informed. If we're totally out of
5164	* handy pages we will return failure.
5165	*/
5166	/* Report the failure. */
5167	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
5168	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
5169	rc, rcAlloc, rcSeed,
5170	pVM->pgm.s.cHandyPages,
5171	pVM->pgm.s.cAllPages,
5172	pVM->pgm.s.cPrivatePages,
5173	pVM->pgm.s.cSharedPages,
5174	pVM->pgm.s.cZeroPages));
5175
5176	if (GMMR3QueryMemoryStats(pVM, &cAllocPages, &cMaxPages, &cBalloonPages) == VINF_SUCCESS)
5177	{
5178	LogRel(("GMM: Statistics:\n"
5179	" Allocated pages: %RX64\n"
5180	" Maximum pages: %RX64\n"
5181	" Ballooned pages: %RX64\n", cAllocPages, cMaxPages, cBalloonPages));
5182	}
5183
5184	if ( rc != VERR_NO_MEMORY
5185	&& rc != VERR_NO_PHYS_MEMORY
5186	&& rc != VERR_LOCK_FAILED)
5187	{
5188	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5189	{
5190	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
5191	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
5192	pVM->pgm.s.aHandyPages[i].idSharedPage));
5193	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
5194	if (idPage != NIL_GMM_PAGEID)
5195	{
5196	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
5197	pRam;
5198	pRam = pRam->pNextR3)
5199	{
5200	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
5201	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5202	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
5203	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
5204	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
5205	}
5206	}
5207	}
5208	}
5209
5210	if (rc == VERR_NO_MEMORY)
5211	{
5212	uint64_t cbHostRamAvail = 0;
5213	int rc2 = RTSystemQueryAvailableRam(&cbHostRamAvail);
5214	if (RT_SUCCESS(rc2))
5215	LogRel(("Host RAM: %RU64MB available\n", cbHostRamAvail / _1M));
5216	else
5217	LogRel(("Cannot determine the amount of available host memory\n"));
5218	}
5219
5220	/* Set the FFs and adjust rc. */
5221	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5222	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
5223	if ( rc == VERR_NO_MEMORY
5224	\|\| rc == VERR_NO_PHYS_MEMORY
5225	\|\| rc == VERR_LOCK_FAILED)
5226	rc = VINF_EM_NO_MEMORY;
5227	}
5228
5229	pgmUnlock(pVM);
5230	return rc;
5231	}
5232
5233
5234	/**
5235	* Frees the specified RAM page and replaces it with the ZERO page.
5236	*
5237	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
5238	*
5239	* @param pVM The cross context VM structure.
5240	* @param pReq Pointer to the request.
5241	* @param pcPendingPages Where the number of pages waiting to be freed are
5242	* kept. This will normally be incremented.
5243	* @param pPage Pointer to the page structure.
5244	* @param GCPhys The guest physical address of the page, if applicable.
5245	*
5246	* @remarks The caller must own the PGM lock.
5247	*/
5248	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
5249	{
5250	/*
5251	* Assert sanity.
5252	*/
5253	PGM_LOCK_ASSERT_OWNER(pVM);
5254	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
5255	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
5256	{
5257	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5258	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
5259	}
5260
5261	/** @todo What about ballooning of large pages??! */
5262	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
5263	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
5264
5265	if ( PGM_PAGE_IS_ZERO(pPage)
5266	\|\| PGM_PAGE_IS_BALLOONED(pPage))
5267	return VINF_SUCCESS;
5268
5269	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
5270	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
5271	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
5272	\|\| idPage > GMM_PAGEID_LAST
5273	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
5274	{
5275	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5276	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
5277	}
5278
5279	/* update page count stats. */
5280	if (PGM_PAGE_IS_SHARED(pPage))
5281	pVM->pgm.s.cSharedPages--;
5282	else
5283	pVM->pgm.s.cPrivatePages--;
5284	pVM->pgm.s.cZeroPages++;
5285
5286	/* Deal with write monitored pages. */
5287	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
5288	{
5289	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
5290	pVM->pgm.s.cWrittenToPages++;
5291	}
5292
5293	/*
5294	* pPage = ZERO page.
5295	*/
5296	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
5297	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
5298	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
5299	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
5300	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5301	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5302
5303	/* Flush physical page map TLB entry. */
5304	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
5305
5306	/*
5307	* Make sure it's not in the handy page array.
5308	*/
5309	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5310	{
5311	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
5312	{
5313	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
5314	break;
5315	}
5316	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
5317	{
5318	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
5319	break;
5320	}
5321	}
5322
5323	/*
5324	* Push it onto the page array.
5325	*/
5326	uint32_t iPage = *pcPendingPages;
5327	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
5328	*pcPendingPages += 1;
5329
5330	pReq->aPages[iPage].idPage = idPage;
5331
5332	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
5333	return VINF_SUCCESS;
5334
5335	/*
5336	* Flush the pages.
5337	*/
5338	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
5339	if (RT_SUCCESS(rc))
5340	{
5341	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
5342	*pcPendingPages = 0;
5343	}
5344	return rc;
5345	}
5346
5347
5348	/**
5349	* Converts a GC physical address to a HC ring-3 pointer, with some
5350	* additional checks.
5351	*
5352	* @returns VBox status code.
5353	* @retval VINF_SUCCESS on success.
5354	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
5355	* access handler of some kind.
5356	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
5357	* accesses or is odd in any way.
5358	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
5359	*
5360	* @param pVM The cross context VM structure.
5361	* @param GCPhys The GC physical address to convert. Since this is only
5362	* used for filling the REM TLB, the A20 mask must be
5363	* applied before calling this API.
5364	* @param fWritable Whether write access is required.
5365	* @param ppv Where to store the pointer corresponding to GCPhys on
5366	* success.
5367	*/
5368	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
5369	{
5370	pgmLock(pVM);
5371	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
5372
5373	PPGMRAMRANGE pRam;
5374	PPGMPAGE pPage;
5375	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
5376	if (RT_SUCCESS(rc))
5377	{
5378	if (PGM_PAGE_IS_BALLOONED(pPage))
5379	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5380	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
5381	rc = VINF_SUCCESS;
5382	else
5383	{
5384	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
5385	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5386	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
5387	{
5388	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
5389	* in -norawr0 mode. */
5390	if (fWritable)
5391	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5392	}
5393	else
5394	{
5395	/* Temporarily disabled physical handler(s), since the recompiler
5396	doesn't get notified when it's reset we'll have to pretend it's
5397	operating normally. */
5398	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
5399	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5400	else
5401	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5402	}
5403	}
5404	if (RT_SUCCESS(rc))
5405	{
5406	int rc2;
5407
5408	/* Make sure what we return is writable. */
5409	if (fWritable)
5410	switch (PGM_PAGE_GET_STATE(pPage))
5411	{
5412	case PGM_PAGE_STATE_ALLOCATED:
5413	break;
5414	case PGM_PAGE_STATE_BALLOONED:
5415	AssertFailed();
5416	break;
5417	case PGM_PAGE_STATE_ZERO:
5418	case PGM_PAGE_STATE_SHARED:
5419	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
5420	break;
5421	RT_FALL_THRU();
5422	case PGM_PAGE_STATE_WRITE_MONITORED:
5423	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
5424	AssertLogRelRCReturn(rc2, rc2);
5425	break;
5426	}
5427
5428	/* Get a ring-3 mapping of the address. */
5429	PPGMPAGER3MAPTLBE pTlbe;
5430	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
5431	AssertLogRelRCReturn(rc2, rc2);
5432	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
5433	/** @todo mapping/locking hell; this isn't horribly efficient since
5434	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
5435
5436	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
5437	}
5438	else
5439	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
5440
5441	/* else: handler catching all access, no pointer returned. */
5442	}
5443	else
5444	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
5445
5446	pgmUnlock(pVM);
5447	return rc;
5448	}
5449

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 70951

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