PGMPhys.cpp@ 77241

Last change on this file since 77241 was 77241, checked in by vboxsync, 6 years ago
VMM: Added dev helps for bulk page mapping locking. VMMDev will be using this for a new variation on the HGCM page list parameter type. bugref:9172
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1	/* $Id: PGMPhys.cpp 77241 2019-02-10 22:30:33Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/iem.h>
25	#include <VBox/vmm/iom.h>
26	#include <VBox/vmm/mm.h>
27	#include <VBox/vmm/nem.h>
28	#include <VBox/vmm/stam.h>
29	#ifdef VBOX_WITH_REM
30	# include <VBox/vmm/rem.h>
31	#endif
32	#include <VBox/vmm/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/uvm.h>
36	#include "PGMInline.h"
37	#include <VBox/sup.h>
38	#include <VBox/param.h>
39	#include <VBox/err.h>
40	#include <VBox/log.h>
41	#include <iprt/assert.h>
42	#include <iprt/alloc.h>
43	#include <iprt/asm.h>
44	#ifdef VBOX_STRICT
45	# include <iprt/crc.h>
46	#endif
47	#include <iprt/thread.h>
48	#include <iprt/string.h>
49	#include <iprt/system.h>
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** The number of pages to free in one batch. */
56	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
57
58
59	/*
60	* PGMR3PhysReadU8-64
61	* PGMR3PhysWriteU8-64
62	*/
63	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
64	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
65	#define PGMPHYS_DATASIZE 1
66	#define PGMPHYS_DATATYPE uint8_t
67	#include "PGMPhysRWTmpl.h"
68
69	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
70	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
71	#define PGMPHYS_DATASIZE 2
72	#define PGMPHYS_DATATYPE uint16_t
73	#include "PGMPhysRWTmpl.h"
74
75	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
76	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
77	#define PGMPHYS_DATASIZE 4
78	#define PGMPHYS_DATATYPE uint32_t
79	#include "PGMPhysRWTmpl.h"
80
81	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
82	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
83	#define PGMPHYS_DATASIZE 8
84	#define PGMPHYS_DATATYPE uint64_t
85	#include "PGMPhysRWTmpl.h"
86
87
88	/**
89	* EMT worker for PGMR3PhysReadExternal.
90	*/
91	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
92	PGMACCESSORIGIN enmOrigin)
93	{
94	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
95	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
96	return VINF_SUCCESS;
97	}
98
99
100	/**
101	* Read from physical memory, external users.
102	*
103	* @returns VBox status code.
104	* @retval VINF_SUCCESS.
105	*
106	* @param pVM The cross context VM structure.
107	* @param GCPhys Physical address to read from.
108	* @param pvBuf Where to read into.
109	* @param cbRead How many bytes to read.
110	* @param enmOrigin Who is calling.
111	*
112	* @thread Any but EMTs.
113	*/
114	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
115	{
116	VM_ASSERT_OTHER_THREAD(pVM);
117
118	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
119	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
120
121	pgmLock(pVM);
122
123	/*
124	* Copy loop on ram ranges.
125	*/
126	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
127	for (;;)
128	{
129	/* Inside range or not? */
130	if (pRam && GCPhys >= pRam->GCPhys)
131	{
132	/*
133	* Must work our way thru this page by page.
134	*/
135	RTGCPHYS off = GCPhys - pRam->GCPhys;
136	while (off < pRam->cb)
137	{
138	unsigned iPage = off >> PAGE_SHIFT;
139	PPGMPAGE pPage = &pRam->aPages[iPage];
140
141	/*
142	* If the page has an ALL access handler, we'll have to
143	* delegate the job to EMT.
144	*/
145	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
146	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
147	{
148	pgmUnlock(pVM);
149
150	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
151	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
152	}
153	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
154
155	/*
156	* Simple stuff, go ahead.
157	*/
158	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
159	if (cb > cbRead)
160	cb = cbRead;
161	PGMPAGEMAPLOCK PgMpLck;
162	const void *pvSrc;
163	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
164	if (RT_SUCCESS(rc))
165	{
166	memcpy(pvBuf, pvSrc, cb);
167	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
168	}
169	else
170	{
171	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
172	pRam->GCPhys + off, pPage, rc));
173	memset(pvBuf, 0xff, cb);
174	}
175
176	/* next page */
177	if (cb >= cbRead)
178	{
179	pgmUnlock(pVM);
180	return VINF_SUCCESS;
181	}
182	cbRead -= cb;
183	off += cb;
184	GCPhys += cb;
185	pvBuf = (char *)pvBuf + cb;
186	} /* walk pages in ram range. */
187	}
188	else
189	{
190	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
191
192	/*
193	* Unassigned address space.
194	*/
195	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
196	if (cb >= cbRead)
197	{
198	memset(pvBuf, 0xff, cbRead);
199	break;
200	}
201	memset(pvBuf, 0xff, cb);
202
203	cbRead -= cb;
204	pvBuf = (char *)pvBuf + cb;
205	GCPhys += cb;
206	}
207
208	/* Advance range if necessary. */
209	while (pRam && GCPhys > pRam->GCPhysLast)
210	pRam = pRam->CTX_SUFF(pNext);
211	} /* Ram range walk */
212
213	pgmUnlock(pVM);
214
215	return VINF_SUCCESS;
216	}
217
218
219	/**
220	* EMT worker for PGMR3PhysWriteExternal.
221	*/
222	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
223	PGMACCESSORIGIN enmOrigin)
224	{
225	/** @todo VERR_EM_NO_MEMORY */
226	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
227	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
228	return VINF_SUCCESS;
229	}
230
231
232	/**
233	* Write to physical memory, external users.
234	*
235	* @returns VBox status code.
236	* @retval VINF_SUCCESS.
237	* @retval VERR_EM_NO_MEMORY.
238	*
239	* @param pVM The cross context VM structure.
240	* @param GCPhys Physical address to write to.
241	* @param pvBuf What to write.
242	* @param cbWrite How many bytes to write.
243	* @param enmOrigin Who is calling.
244	*
245	* @thread Any but EMTs.
246	*/
247	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
248	{
249	VM_ASSERT_OTHER_THREAD(pVM);
250
251	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
252	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
253	GCPhys, cbWrite, enmOrigin));
254	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
255	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
256
257	pgmLock(pVM);
258
259	/*
260	* Copy loop on ram ranges, stop when we hit something difficult.
261	*/
262	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
263	for (;;)
264	{
265	/* Inside range or not? */
266	if (pRam && GCPhys >= pRam->GCPhys)
267	{
268	/*
269	* Must work our way thru this page by page.
270	*/
271	RTGCPTR off = GCPhys - pRam->GCPhys;
272	while (off < pRam->cb)
273	{
274	RTGCPTR iPage = off >> PAGE_SHIFT;
275	PPGMPAGE pPage = &pRam->aPages[iPage];
276
277	/*
278	* Is the page problematic, we have to do the work on the EMT.
279	*
280	* Allocating writable pages and access handlers are
281	* problematic, write monitored pages are simple and can be
282	* dealt with here.
283	*/
284	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
285	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
286	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
287	{
288	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
289	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
290	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
291	else
292	{
293	pgmUnlock(pVM);
294
295	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
296	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
297	}
298	}
299	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
300
301	/*
302	* Simple stuff, go ahead.
303	*/
304	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
305	if (cb > cbWrite)
306	cb = cbWrite;
307	PGMPAGEMAPLOCK PgMpLck;
308	void *pvDst;
309	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
310	if (RT_SUCCESS(rc))
311	{
312	memcpy(pvDst, pvBuf, cb);
313	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
314	}
315	else
316	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
317	pRam->GCPhys + off, pPage, rc));
318
319	/* next page */
320	if (cb >= cbWrite)
321	{
322	pgmUnlock(pVM);
323	return VINF_SUCCESS;
324	}
325
326	cbWrite -= cb;
327	off += cb;
328	GCPhys += cb;
329	pvBuf = (const char *)pvBuf + cb;
330	} /* walk pages in ram range */
331	}
332	else
333	{
334	/*
335	* Unassigned address space, skip it.
336	*/
337	if (!pRam)
338	break;
339	size_t cb = pRam->GCPhys - GCPhys;
340	if (cb >= cbWrite)
341	break;
342	cbWrite -= cb;
343	pvBuf = (const char *)pvBuf + cb;
344	GCPhys += cb;
345	}
346
347	/* Advance range if necessary. */
348	while (pRam && GCPhys > pRam->GCPhysLast)
349	pRam = pRam->CTX_SUFF(pNext);
350	} /* Ram range walk */
351
352	pgmUnlock(pVM);
353	return VINF_SUCCESS;
354	}
355
356
357	/**
358	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
359	*
360	* @returns see PGMR3PhysGCPhys2CCPtrExternal
361	* @param pVM The cross context VM structure.
362	* @param pGCPhys Pointer to the guest physical address.
363	* @param ppv Where to store the mapping address.
364	* @param pLock Where to store the lock.
365	*/
366	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
367	{
368	/*
369	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
370	* an access handler after it succeeds.
371	*/
372	int rc = pgmLock(pVM);
373	AssertRCReturn(rc, rc);
374
375	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
376	if (RT_SUCCESS(rc))
377	{
378	PPGMPAGEMAPTLBE pTlbe;
379	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
380	AssertFatalRC(rc2);
381	PPGMPAGE pPage = pTlbe->pPage;
382	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
383	{
384	PGMPhysReleasePageMappingLock(pVM, pLock);
385	rc = VERR_PGM_PHYS_PAGE_RESERVED;
386	}
387	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
388	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
389	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
390	#endif
391	)
392	{
393	/* We must flush any corresponding pgm pool page here, otherwise we'll
394	* not be informed about writes and keep bogus gst->shw mappings around.
395	*/
396	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
397	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
398	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
399	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
400	}
401	}
402
403	pgmUnlock(pVM);
404	return rc;
405	}
406
407
408	/**
409	* Requests the mapping of a guest page into ring-3, external threads.
410	*
411	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
412	* release it.
413	*
414	* This API will assume your intention is to write to the page, and will
415	* therefore replace shared and zero pages. If you do not intend to modify the
416	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
417	*
418	* @returns VBox status code.
419	* @retval VINF_SUCCESS on success.
420	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
421	* backing or if the page has any active access handlers. The caller
422	* must fall back on using PGMR3PhysWriteExternal.
423	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
424	*
425	* @param pVM The cross context VM structure.
426	* @param GCPhys The guest physical address of the page that should be mapped.
427	* @param ppv Where to store the address corresponding to GCPhys.
428	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
429	*
430	* @remark Avoid calling this API from within critical sections (other than the
431	* PGM one) because of the deadlock risk when we have to delegating the
432	* task to an EMT.
433	* @thread Any.
434	*/
435	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
436	{
437	AssertPtr(ppv);
438	AssertPtr(pLock);
439
440	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
441
442	int rc = pgmLock(pVM);
443	AssertRCReturn(rc, rc);
444
445	/*
446	* Query the Physical TLB entry for the page (may fail).
447	*/
448	PPGMPAGEMAPTLBE pTlbe;
449	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
450	if (RT_SUCCESS(rc))
451	{
452	PPGMPAGE pPage = pTlbe->pPage;
453	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
454	rc = VERR_PGM_PHYS_PAGE_RESERVED;
455	else
456	{
457	/*
458	* If the page is shared, the zero page, or being write monitored
459	* it must be converted to an page that's writable if possible.
460	* We can only deal with write monitored pages here, the rest have
461	* to be on an EMT.
462	*/
463	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
464	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
465	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
466	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
467	#endif
468	)
469	{
470	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
471	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
472	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
473	&& !pgmPoolIsDirtyPage(pVM, GCPhys) /** @todo we're very likely doing this twice. */
474	#endif
475	)
476	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
477	else
478	{
479	pgmUnlock(pVM);
480
481	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
482	pVM, &GCPhys, ppv, pLock);
483	}
484	}
485
486	/*
487	* Now, just perform the locking and calculate the return address.
488	*/
489	PPGMPAGEMAP pMap = pTlbe->pMap;
490	if (pMap)
491	pMap->cRefs++;
492
493	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
494	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
495	{
496	if (cLocks == 0)
497	pVM->pgm.s.cWriteLockedPages++;
498	PGM_PAGE_INC_WRITE_LOCKS(pPage);
499	}
500	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
501	{
502	PGM_PAGE_INC_WRITE_LOCKS(pPage);
503	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
504	if (pMap)
505	pMap->cRefs++; /* Extra ref to prevent it from going away. */
506	}
507
508	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
509	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
510	pLock->pvMap = pMap;
511	}
512	}
513
514	pgmUnlock(pVM);
515	return rc;
516	}
517
518
519	/**
520	* Requests the mapping of a guest page into ring-3, external threads.
521	*
522	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
523	* release it.
524	*
525	* @returns VBox status code.
526	* @retval VINF_SUCCESS on success.
527	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
528	* backing or if the page as an active ALL access handler. The caller
529	* must fall back on using PGMPhysRead.
530	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
531	*
532	* @param pVM The cross context VM structure.
533	* @param GCPhys The guest physical address of the page that should be mapped.
534	* @param ppv Where to store the address corresponding to GCPhys.
535	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
536	*
537	* @remark Avoid calling this API from within critical sections (other than
538	* the PGM one) because of the deadlock risk.
539	* @thread Any.
540	*/
541	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
542	{
543	int rc = pgmLock(pVM);
544	AssertRCReturn(rc, rc);
545
546	/*
547	* Query the Physical TLB entry for the page (may fail).
548	*/
549	PPGMPAGEMAPTLBE pTlbe;
550	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
551	if (RT_SUCCESS(rc))
552	{
553	PPGMPAGE pPage = pTlbe->pPage;
554	#if 1
555	/* MMIO pages doesn't have any readable backing. */
556	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
557	rc = VERR_PGM_PHYS_PAGE_RESERVED;
558	#else
559	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
560	rc = VERR_PGM_PHYS_PAGE_RESERVED;
561	#endif
562	else
563	{
564	/*
565	* Now, just perform the locking and calculate the return address.
566	*/
567	PPGMPAGEMAP pMap = pTlbe->pMap;
568	if (pMap)
569	pMap->cRefs++;
570
571	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
572	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
573	{
574	if (cLocks == 0)
575	pVM->pgm.s.cReadLockedPages++;
576	PGM_PAGE_INC_READ_LOCKS(pPage);
577	}
578	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
579	{
580	PGM_PAGE_INC_READ_LOCKS(pPage);
581	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
582	if (pMap)
583	pMap->cRefs++; /* Extra ref to prevent it from going away. */
584	}
585
586	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
587	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
588	pLock->pvMap = pMap;
589	}
590	}
591
592	pgmUnlock(pVM);
593	return rc;
594	}
595
596
597	/**
598	* Requests the mapping of multiple guest page into ring-3, external threads.
599	*
600	* When you're done with the pages, call PGMPhysBulkReleasePageMappingLock()
601	* ASAP to release them.
602	*
603	* This API will assume your intention is to write to the pages, and will
604	* therefore replace shared and zero pages. If you do not intend to modify the
605	* pages, use the PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal() API.
606	*
607	* @returns VBox status code.
608	* @retval VINF_SUCCESS on success.
609	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
610	* backing or if any of the pages the page has any active access
611	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
612	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
613	* an invalid physical address.
614	*
615	* @param pVM The cross context VM structure.
616	* @param cPages Number of pages to lock.
617	* @param paGCPhysPages The guest physical address of the pages that
618	* should be mapped (@a cPages entries).
619	* @param fFlags Flags reserved for future use, MBZ.
620	* @param papvPages Where to store the ring-3 mapping addresses
621	* corresponding to @a paGCPhysPages.
622	* @param paLocks Where to store the locking information that
623	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
624	* in length).
625	*
626	* @remark Avoid calling this API from within critical sections (other than the
627	* PGM one) because of the deadlock risk when we have to delegating the
628	* task to an EMT.
629	* @thread Any.
630	*/
631	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
632	void **papvPages, PPGMPAGEMAPLOCK paLocks)
633	{
634	Assert(cPages > 0);
635	AssertPtr(papvPages);
636	AssertPtr(paLocks);
637
638	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
639
640	int rc = pgmLock(pVM);
641	AssertRCReturn(rc, rc);
642
643	/*
644	* Lock the pages one by one.
645	* The loop body is similar to PGMR3PhysGCPhys2CCPtrExternal.
646	*/
647	int32_t cNextYield = 128;
648	uint32_t iPage;
649	for (iPage = 0; iPage < cPages; iPage++)
650	{
651	if (--cNextYield > 0)
652	{ /* likely */ }
653	else
654	{
655	pgmUnlock(pVM);
656	ASMNopPause();
657	pgmLock(pVM);
658	cNextYield = 128;
659	}
660
661	/*
662	* Query the Physical TLB entry for the page (may fail).
663	*/
664	PPGMPAGEMAPTLBE pTlbe;
665	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
666	if (RT_SUCCESS(rc))
667	{ }
668	else
669	break;
670	PPGMPAGE pPage = pTlbe->pPage;
671
672	/*
673	* No MMIO or active access handlers.
674	*/
675	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
676	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
677	{ }
678	else
679	{
680	rc = VERR_PGM_PHYS_PAGE_RESERVED;
681	break;
682	}
683
684	/*
685	* The page must be in the allocated state and not be a dirty pool page.
686	* We can handle converting a write monitored page to an allocated one, but
687	* anything more complicated must be delegated to an EMT.
688	*/
689	bool fDelegateToEmt = false;
690	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
691	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
692	fDelegateToEmt = pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]);
693	#else
694	fDelegateToEmt = false;
695	#endif
696	else if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
697	{
698	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
699	if (!pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]))
700	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, paGCPhysPages[iPage]);
701	else
702	fDelegateToEmt = true;
703	#endif
704	}
705	else
706	fDelegateToEmt = true;
707	if (!fDelegateToEmt)
708	{ }
709	else
710	{
711	/* We could do this delegation in bulk, but considered too much work vs gain. */
712	pgmUnlock(pVM);
713	rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
714	pVM, paGCPhysPages[iPage], &papvPages[iPage], &paLocks[iPage]);
715	pgmLock(pVM);
716	if (RT_FAILURE(rc))
717	break;
718	cNextYield = 128;
719	}
720
721	/*
722	* Now, just perform the locking and address calculation.
723	*/
724	PPGMPAGEMAP pMap = pTlbe->pMap;
725	if (pMap)
726	pMap->cRefs++;
727
728	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
729	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
730	{
731	if (cLocks == 0)
732	pVM->pgm.s.cWriteLockedPages++;
733	PGM_PAGE_INC_WRITE_LOCKS(pPage);
734	}
735	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
736	{
737	PGM_PAGE_INC_WRITE_LOCKS(pPage);
738	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", paGCPhysPages[iPage], pPage));
739	if (pMap)
740	pMap->cRefs++; /* Extra ref to prevent it from going away. */
741	}
742
743	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
744	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
745	paLocks[iPage].pvMap = pMap;
746	}
747
748	pgmUnlock(pVM);
749
750	/*
751	* On failure we must unlock any pages we managed to get already.
752	*/
753	if (RT_FAILURE(rc) && iPage > 0)
754	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
755
756	return rc;
757	}
758
759
760	/**
761	* Requests the mapping of multiple guest page into ring-3, for reading only,
762	* external threads.
763	*
764	* When you're done with the pages, call PGMPhysReleasePageMappingLock() ASAP
765	* to release them.
766	*
767	* @returns VBox status code.
768	* @retval VINF_SUCCESS on success.
769	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
770	* backing or if any of the pages the page has an active ALL access
771	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
772	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
773	* an invalid physical address.
774	*
775	* @param pVM The cross context VM structure.
776	* @param cPages Number of pages to lock.
777	* @param paGCPhysPages The guest physical address of the pages that
778	* should be mapped (@a cPages entries).
779	* @param fFlags Flags reserved for future use, MBZ.
780	* @param papvPages Where to store the ring-3 mapping addresses
781	* corresponding to @a paGCPhysPages.
782	* @param paLocks Where to store the lock information that
783	* pfnPhysReleasePageMappingLock needs (@a cPages
784	* in length).
785	*
786	* @remark Avoid calling this API from within critical sections (other than
787	* the PGM one) because of the deadlock risk.
788	* @thread Any.
789	*/
790	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
791	void const **papvPages, PPGMPAGEMAPLOCK paLocks)
792	{
793	Assert(cPages > 0);
794	AssertPtr(papvPages);
795	AssertPtr(paLocks);
796
797	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
798
799	int rc = pgmLock(pVM);
800	AssertRCReturn(rc, rc);
801
802	/*
803	* Lock the pages one by one.
804	* The loop body is similar to PGMR3PhysGCPhys2CCPtrReadOnlyExternal.
805	*/
806	int32_t cNextYield = 256;
807	uint32_t iPage;
808	for (iPage = 0; iPage < cPages; iPage++)
809	{
810	if (--cNextYield > 0)
811	{ /* likely */ }
812	else
813	{
814	pgmUnlock(pVM);
815	ASMNopPause();
816	pgmLock(pVM);
817	cNextYield = 256;
818	}
819
820	/*
821	* Query the Physical TLB entry for the page (may fail).
822	*/
823	PPGMPAGEMAPTLBE pTlbe;
824	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
825	if (RT_SUCCESS(rc))
826	{ }
827	else
828	break;
829	PPGMPAGE pPage = pTlbe->pPage;
830
831	/*
832	* No MMIO or active all access handlers, everything else can be accessed.
833	*/
834	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
835	&& !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
836	{ }
837	else
838	{
839	rc = VERR_PGM_PHYS_PAGE_RESERVED;
840	break;
841	}
842
843	/*
844	* Now, just perform the locking and address calculation.
845	*/
846	PPGMPAGEMAP pMap = pTlbe->pMap;
847	if (pMap)
848	pMap->cRefs++;
849
850	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
851	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
852	{
853	if (cLocks == 0)
854	pVM->pgm.s.cReadLockedPages++;
855	PGM_PAGE_INC_READ_LOCKS(pPage);
856	}
857	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
858	{
859	PGM_PAGE_INC_READ_LOCKS(pPage);
860	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", paGCPhysPages[iPage], pPage));
861	if (pMap)
862	pMap->cRefs++; /* Extra ref to prevent it from going away. */
863	}
864
865	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
866	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
867	paLocks[iPage].pvMap = pMap;
868	}
869
870	pgmUnlock(pVM);
871
872	/*
873	* On failure we must unlock any pages we managed to get already.
874	*/
875	if (RT_FAILURE(rc) && iPage > 0)
876	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
877
878	return rc;
879	}
880
881
882	#define MAKE_LEAF(a_pNode) \
883	do { \
884	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
885	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
886	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
887	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
888	(a_pNode)->pLeftRC = NIL_RTRCPTR; \
889	(a_pNode)->pRightRC = NIL_RTRCPTR; \
890	} while (0)
891
892	#define INSERT_LEFT(a_pParent, a_pNode) \
893	do { \
894	(a_pParent)->pLeftR3 = (a_pNode); \
895	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
896	(a_pParent)->pLeftRC = (a_pNode)->pSelfRC; \
897	} while (0)
898	#define INSERT_RIGHT(a_pParent, a_pNode) \
899	do { \
900	(a_pParent)->pRightR3 = (a_pNode); \
901	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
902	(a_pParent)->pRightRC = (a_pNode)->pSelfRC; \
903	} while (0)
904
905
906	/**
907	* Recursive tree builder.
908	*
909	* @param ppRam Pointer to the iterator variable.
910	* @param iDepth The current depth. Inserts a leaf node if 0.
911	*/
912	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
913	{
914	PPGMRAMRANGE pRam;
915	if (iDepth <= 0)
916	{
917	/*
918	* Leaf node.
919	*/
920	pRam = *ppRam;
921	if (pRam)
922	{
923	*ppRam = pRam->pNextR3;
924	MAKE_LEAF(pRam);
925	}
926	}
927	else
928	{
929
930	/*
931	* Intermediate node.
932	*/
933	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
934
935	pRam = *ppRam;
936	if (!pRam)
937	return pLeft;
938	*ppRam = pRam->pNextR3;
939	MAKE_LEAF(pRam);
940	INSERT_LEFT(pRam, pLeft);
941
942	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
943	if (pRight)
944	INSERT_RIGHT(pRam, pRight);
945	}
946	return pRam;
947	}
948
949
950	/**
951	* Rebuilds the RAM range search trees.
952	*
953	* @param pVM The cross context VM structure.
954	*/
955	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
956	{
957
958	/*
959	* Create the reasonably balanced tree in a sequential fashion.
960	* For simplicity (laziness) we use standard recursion here.
961	*/
962	int iDepth = 0;
963	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
964	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
965	while (pRam)
966	{
967	PPGMRAMRANGE pLeft = pRoot;
968
969	pRoot = pRam;
970	pRam = pRam->pNextR3;
971	MAKE_LEAF(pRoot);
972	INSERT_LEFT(pRoot, pLeft);
973
974	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
975	if (pRight)
976	INSERT_RIGHT(pRoot, pRight);
977	/** @todo else: rotate the tree. */
978
979	iDepth++;
980	}
981
982	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
983	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
984	pVM->pgm.s.pRamRangeTreeRC = pRoot ? pRoot->pSelfRC : NIL_RTRCPTR;
985
986	#ifdef VBOX_STRICT
987	/*
988	* Verify that the above code works.
989	*/
990	unsigned cRanges = 0;
991	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
992	cRanges++;
993	Assert(cRanges > 0);
994
995	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
996	if ((1U << cMaxDepth) < cRanges)
997	cMaxDepth++;
998
999	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1000	{
1001	unsigned cDepth = 0;
1002	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
1003	for (;;)
1004	{
1005	if (pRam == pRam2)
1006	break;
1007	Assert(pRam2);
1008	if (pRam->GCPhys < pRam2->GCPhys)
1009	pRam2 = pRam2->pLeftR3;
1010	else
1011	pRam2 = pRam2->pRightR3;
1012	}
1013	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
1014	}
1015	#endif /* VBOX_STRICT */
1016	}
1017
1018	#undef MAKE_LEAF
1019	#undef INSERT_LEFT
1020	#undef INSERT_RIGHT
1021
1022	/**
1023	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
1024	*
1025	* Called when anything was relocated.
1026	*
1027	* @param pVM The cross context VM structure.
1028	*/
1029	void pgmR3PhysRelinkRamRanges(PVM pVM)
1030	{
1031	PPGMRAMRANGE pCur;
1032
1033	#ifdef VBOX_STRICT
1034	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1035	{
1036	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
1037	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
1038	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
1039	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1040	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
1041	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
1042	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
1043	Assert( pCur2 == pCur
1044	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
1045	}
1046	#endif
1047
1048	pCur = pVM->pgm.s.pRamRangesXR3;
1049	if (pCur)
1050	{
1051	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
1052	pVM->pgm.s.pRamRangesXRC = pCur->pSelfRC;
1053
1054	for (; pCur->pNextR3; pCur = pCur->pNextR3)
1055	{
1056	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
1057	pCur->pNextRC = pCur->pNextR3->pSelfRC;
1058	}
1059
1060	Assert(pCur->pNextR0 == NIL_RTR0PTR);
1061	Assert(pCur->pNextRC == NIL_RTRCPTR);
1062	}
1063	else
1064	{
1065	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
1066	Assert(pVM->pgm.s.pRamRangesXRC == NIL_RTRCPTR);
1067	}
1068	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1069
1070	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1071	}
1072
1073
1074	/**
1075	* Links a new RAM range into the list.
1076	*
1077	* @param pVM The cross context VM structure.
1078	* @param pNew Pointer to the new list entry.
1079	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1080	*/
1081	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
1082	{
1083	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
1084	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
1085	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
1086
1087	pgmLock(pVM);
1088
1089	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
1090	pNew->pNextR3 = pRam;
1091	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
1092	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
1093
1094	if (pPrev)
1095	{
1096	pPrev->pNextR3 = pNew;
1097	pPrev->pNextR0 = pNew->pSelfR0;
1098	pPrev->pNextRC = pNew->pSelfRC;
1099	}
1100	else
1101	{
1102	pVM->pgm.s.pRamRangesXR3 = pNew;
1103	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
1104	pVM->pgm.s.pRamRangesXRC = pNew->pSelfRC;
1105	}
1106	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1107
1108	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1109	pgmUnlock(pVM);
1110	}
1111
1112
1113	/**
1114	* Unlink an existing RAM range from the list.
1115	*
1116	* @param pVM The cross context VM structure.
1117	* @param pRam Pointer to the new list entry.
1118	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1119	*/
1120	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
1121	{
1122	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
1123	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
1124	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
1125
1126	pgmLock(pVM);
1127
1128	PPGMRAMRANGE pNext = pRam->pNextR3;
1129	if (pPrev)
1130	{
1131	pPrev->pNextR3 = pNext;
1132	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1133	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
1134	}
1135	else
1136	{
1137	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
1138	pVM->pgm.s.pRamRangesXR3 = pNext;
1139	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1140	pVM->pgm.s.pRamRangesXRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
1141	}
1142	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1143
1144	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1145	pgmUnlock(pVM);
1146	}
1147
1148
1149	/**
1150	* Unlink an existing RAM range from the list.
1151	*
1152	* @param pVM The cross context VM structure.
1153	* @param pRam Pointer to the new list entry.
1154	*/
1155	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
1156	{
1157	pgmLock(pVM);
1158
1159	/* find prev. */
1160	PPGMRAMRANGE pPrev = NULL;
1161	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
1162	while (pCur != pRam)
1163	{
1164	pPrev = pCur;
1165	pCur = pCur->pNextR3;
1166	}
1167	AssertFatal(pCur);
1168
1169	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
1170	pgmUnlock(pVM);
1171	}
1172
1173
1174	/**
1175	* Frees a range of pages, replacing them with ZERO pages of the specified type.
1176	*
1177	* @returns VBox status code.
1178	* @param pVM The cross context VM structure.
1179	* @param pRam The RAM range in which the pages resides.
1180	* @param GCPhys The address of the first page.
1181	* @param GCPhysLast The address of the last page.
1182	* @param enmType The page type to replace then with.
1183	*/
1184	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPAGETYPE enmType)
1185	{
1186	PGM_LOCK_ASSERT_OWNER(pVM);
1187	uint32_t cPendingPages = 0;
1188	PGMMFREEPAGESREQ pReq;
1189	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1190	AssertLogRelRCReturn(rc, rc);
1191
1192	/* Iterate the pages. */
1193	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1194	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1195	while (cPagesLeft-- > 0)
1196	{
1197	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys, enmType);
1198	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1199
1200	PGM_PAGE_SET_TYPE(pVM, pPageDst, enmType);
1201
1202	GCPhys += PAGE_SIZE;
1203	pPageDst++;
1204	}
1205
1206	if (cPendingPages)
1207	{
1208	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1209	AssertLogRelRCReturn(rc, rc);
1210	}
1211	GMMR3FreePagesCleanup(pReq);
1212
1213	return rc;
1214	}
1215
1216	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1217
1218	/**
1219	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
1220	*
1221	* This is only called on one of the EMTs while the other ones are waiting for
1222	* it to complete this function.
1223	*
1224	* @returns VINF_SUCCESS (VBox strict status code).
1225	* @param pVM The cross context VM structure.
1226	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1227	* @param pvUser User parameter
1228	*/
1229	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1230	{
1231	uintptr_t paUser = (uintptr_t )pvUser;
1232	bool fInflate = !!paUser[0];
1233	unsigned cPages = paUser[1];
1234	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
1235	uint32_t cPendingPages = 0;
1236	PGMMFREEPAGESREQ pReq;
1237	int rc;
1238
1239	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
1240	pgmLock(pVM);
1241
1242	if (fInflate)
1243	{
1244	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
1245	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
1246
1247	/* Replace pages with ZERO pages. */
1248	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1249	if (RT_FAILURE(rc))
1250	{
1251	pgmUnlock(pVM);
1252	AssertLogRelRC(rc);
1253	return rc;
1254	}
1255
1256	/* Iterate the pages. */
1257	for (unsigned i = 0; i < cPages; i++)
1258	{
1259	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1260	if ( pPage == NULL
1261	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
1262	{
1263	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
1264	break;
1265	}
1266
1267	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
1268
1269	/* Flush the shadow PT if this page was previously used as a guest page table. */
1270	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
1271
1272	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i], (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
1273	if (RT_FAILURE(rc))
1274	{
1275	pgmUnlock(pVM);
1276	AssertLogRelRC(rc);
1277	return rc;
1278	}
1279	Assert(PGM_PAGE_IS_ZERO(pPage));
1280	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
1281	}
1282
1283	if (cPendingPages)
1284	{
1285	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1286	if (RT_FAILURE(rc))
1287	{
1288	pgmUnlock(pVM);
1289	AssertLogRelRC(rc);
1290	return rc;
1291	}
1292	}
1293	GMMR3FreePagesCleanup(pReq);
1294	}
1295	else
1296	{
1297	/* Iterate the pages. */
1298	for (unsigned i = 0; i < cPages; i++)
1299	{
1300	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1301	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
1302
1303	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
1304
1305	Assert(PGM_PAGE_IS_BALLOONED(pPage));
1306
1307	/* Change back to zero page. (NEM does not need to be informed.) */
1308	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1309	}
1310
1311	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
1312	}
1313
1314	/* Notify GMM about the balloon change. */
1315	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
1316	if (RT_SUCCESS(rc))
1317	{
1318	if (!fInflate)
1319	{
1320	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
1321	pVM->pgm.s.cBalloonedPages -= cPages;
1322	}
1323	else
1324	pVM->pgm.s.cBalloonedPages += cPages;
1325	}
1326
1327	pgmUnlock(pVM);
1328
1329	/* Flush the recompiler's TLB as well. */
1330	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1331	CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1332
1333	AssertLogRelRC(rc);
1334	return rc;
1335	}
1336
1337
1338	/**
1339	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
1340	*
1341	* @returns VBox status code.
1342	* @param pVM The cross context VM structure.
1343	* @param fInflate Inflate or deflate memory balloon
1344	* @param cPages Number of pages to free
1345	* @param paPhysPage Array of guest physical addresses
1346	*/
1347	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1348	{
1349	uintptr_t paUser[3];
1350
1351	paUser[0] = fInflate;
1352	paUser[1] = cPages;
1353	paUser[2] = (uintptr_t)paPhysPage;
1354	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1355	AssertRC(rc);
1356
1357	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
1358	RTMemFree(paPhysPage);
1359	}
1360
1361	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
1362
1363	/**
1364	* Inflate or deflate a memory balloon
1365	*
1366	* @returns VBox status code.
1367	* @param pVM The cross context VM structure.
1368	* @param fInflate Inflate or deflate memory balloon
1369	* @param cPages Number of pages to free
1370	* @param paPhysPage Array of guest physical addresses
1371	*/
1372	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1373	{
1374	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
1375	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1376	int rc;
1377
1378	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
1379	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
1380
1381	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
1382	* In the SMP case we post a request packet to postpone the job.
1383	*/
1384	if (pVM->cCpus > 1)
1385	{
1386	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
1387	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
1388	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
1389
1390	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
1391
1392	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
1393	AssertRC(rc);
1394	}
1395	else
1396	{
1397	uintptr_t paUser[3];
1398
1399	paUser[0] = fInflate;
1400	paUser[1] = cPages;
1401	paUser[2] = (uintptr_t)paPhysPage;
1402	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1403	AssertRC(rc);
1404	}
1405	return rc;
1406
1407	#else
1408	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
1409	return VERR_NOT_IMPLEMENTED;
1410	#endif
1411	}
1412
1413
1414	/**
1415	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
1416	* physical RAM.
1417	*
1418	* This is only called on one of the EMTs while the other ones are waiting for
1419	* it to complete this function.
1420	*
1421	* @returns VINF_SUCCESS (VBox strict status code).
1422	* @param pVM The cross context VM structure.
1423	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1424	* @param pvUser User parameter, unused.
1425	*/
1426	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1427	{
1428	int rc = VINF_SUCCESS;
1429	NOREF(pvUser); NOREF(pVCpu);
1430
1431	pgmLock(pVM);
1432	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1433	pgmPoolResetDirtyPages(pVM);
1434	#endif
1435
1436	/** @todo pointless to write protect the physical page pointed to by RSP. */
1437
1438	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1439	pRam;
1440	pRam = pRam->CTX_SUFF(pNext))
1441	{
1442	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1443	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1444	{
1445	PPGMPAGE pPage = &pRam->aPages[iPage];
1446	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1447
1448	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1449	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1450	{
1451	/*
1452	* A RAM page.
1453	*/
1454	switch (PGM_PAGE_GET_STATE(pPage))
1455	{
1456	case PGM_PAGE_STATE_ALLOCATED:
1457	/** @todo Optimize this: Don't always re-enable write
1458	* monitoring if the page is known to be very busy. */
1459	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
1460	{
1461	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1462	/* Remember this dirty page for the next (memory) sync. */
1463	PGM_PAGE_SET_FT_DIRTY(pPage);
1464	}
1465
1466	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1467	break;
1468
1469	case PGM_PAGE_STATE_SHARED:
1470	AssertFailed();
1471	break;
1472
1473	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
1474	default:
1475	break;
1476	}
1477	}
1478	}
1479	}
1480	pgmR3PoolWriteProtectPages(pVM);
1481	PGM_INVL_ALL_VCPU_TLBS(pVM);
1482	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1483	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1484
1485	pgmUnlock(pVM);
1486	return rc;
1487	}
1488
1489	/**
1490	* Protect all physical RAM to monitor writes
1491	*
1492	* @returns VBox status code.
1493	* @param pVM The cross context VM structure.
1494	*/
1495	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
1496	{
1497	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1498
1499	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
1500	AssertRC(rc);
1501	return rc;
1502	}
1503
1504	/**
1505	* Enumerate all dirty FT pages.
1506	*
1507	* @returns VBox status code.
1508	* @param pVM The cross context VM structure.
1509	* @param pfnEnum Enumerate callback handler.
1510	* @param pvUser Enumerate callback handler parameter.
1511	*/
1512	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser)
1513	{
1514	int rc = VINF_SUCCESS;
1515
1516	pgmLock(pVM);
1517	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1518	pRam;
1519	pRam = pRam->CTX_SUFF(pNext))
1520	{
1521	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1522	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1523	{
1524	PPGMPAGE pPage = &pRam->aPages[iPage];
1525	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1526
1527	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1528	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1529	{
1530	/*
1531	* A RAM page.
1532	*/
1533	switch (PGM_PAGE_GET_STATE(pPage))
1534	{
1535	case PGM_PAGE_STATE_ALLOCATED:
1536	case PGM_PAGE_STATE_WRITE_MONITORED:
1537	if ( !PGM_PAGE_IS_WRITTEN_TO(pPage) /* not very recently updated? */
1538	&& PGM_PAGE_IS_FT_DIRTY(pPage))
1539	{
1540	uint32_t cbPageRange = PAGE_SIZE;
1541	uint32_t iPageClean = iPage + 1;
1542	RTGCPHYS GCPhysPage = pRam->GCPhys + iPage * PAGE_SIZE;
1543	uint8_t *pu8Page = NULL;
1544	PGMPAGEMAPLOCK Lock;
1545
1546	/* Find the next clean page, so we can merge adjacent dirty pages. */
1547	for (; iPageClean < cPages; iPageClean++)
1548	{
1549	PPGMPAGE pPageNext = &pRam->aPages[iPageClean];
1550	if ( RT_UNLIKELY(PGM_PAGE_GET_TYPE(pPageNext) != PGMPAGETYPE_RAM)
1551	\|\| PGM_PAGE_GET_STATE(pPageNext) != PGM_PAGE_STATE_ALLOCATED
1552	\|\| PGM_PAGE_IS_WRITTEN_TO(pPageNext)
1553	\|\| !PGM_PAGE_IS_FT_DIRTY(pPageNext)
1554	/* Crossing a chunk boundary? */
1555	\|\| (GCPhysPage & GMM_PAGEID_IDX_MASK) != ((GCPhysPage + cbPageRange) & GMM_PAGEID_IDX_MASK)
1556	)
1557	break;
1558
1559	cbPageRange += PAGE_SIZE;
1560	}
1561
1562	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhysPage, (const void **)&pu8Page, &Lock);
1563	if (RT_SUCCESS(rc))
1564	{
1565	/** @todo this is risky; the range might be changed, but little choice as the sync
1566	* costs a lot of time. */
1567	pgmUnlock(pVM);
1568	pfnEnum(pVM, GCPhysPage, pu8Page, cbPageRange, pvUser);
1569	pgmLock(pVM);
1570	PGMPhysReleasePageMappingLock(pVM, &Lock);
1571	}
1572
1573	for (uint32_t iTmp = iPage; iTmp < iPageClean; iTmp++)
1574	PGM_PAGE_CLEAR_FT_DIRTY(&pRam->aPages[iTmp]);
1575	}
1576	break;
1577	}
1578	}
1579	}
1580	}
1581	pgmUnlock(pVM);
1582	return rc;
1583	}
1584
1585
1586	/**
1587	* Gets the number of ram ranges.
1588	*
1589	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1590	* @param pVM The cross context VM structure.
1591	*/
1592	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1593	{
1594	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1595
1596	pgmLock(pVM);
1597	uint32_t cRamRanges = 0;
1598	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1599	cRamRanges++;
1600	pgmUnlock(pVM);
1601	return cRamRanges;
1602	}
1603
1604
1605	/**
1606	* Get information about a range.
1607	*
1608	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1609	* @param pVM The cross context VM structure.
1610	* @param iRange The ordinal of the range.
1611	* @param pGCPhysStart Where to return the start of the range. Optional.
1612	* @param pGCPhysLast Where to return the address of the last byte in the
1613	* range. Optional.
1614	* @param ppszDesc Where to return the range description. Optional.
1615	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1616	* Optional.
1617	*/
1618	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1619	const char *ppszDesc, bool pfIsMmio)
1620	{
1621	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1622
1623	pgmLock(pVM);
1624	uint32_t iCurRange = 0;
1625	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1626	if (iCurRange == iRange)
1627	{
1628	if (pGCPhysStart)
1629	*pGCPhysStart = pCur->GCPhys;
1630	if (pGCPhysLast)
1631	*pGCPhysLast = pCur->GCPhysLast;
1632	if (ppszDesc)
1633	*ppszDesc = pCur->pszDesc;
1634	if (pfIsMmio)
1635	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1636
1637	pgmUnlock(pVM);
1638	return VINF_SUCCESS;
1639	}
1640	pgmUnlock(pVM);
1641	return VERR_OUT_OF_RANGE;
1642	}
1643
1644
1645	/**
1646	* Query the amount of free memory inside VMMR0
1647	*
1648	* @returns VBox status code.
1649	* @param pUVM The user mode VM handle.
1650	* @param pcbAllocMem Where to return the amount of memory allocated
1651	* by VMs.
1652	* @param pcbFreeMem Where to return the amount of memory that is
1653	* allocated from the host but not currently used
1654	* by any VMs.
1655	* @param pcbBallonedMem Where to return the sum of memory that is
1656	* currently ballooned by the VMs.
1657	* @param pcbSharedMem Where to return the amount of memory that is
1658	* currently shared.
1659	*/
1660	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
1661	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
1662	{
1663	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1664	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
1665
1666	uint64_t cAllocPages = 0;
1667	uint64_t cFreePages = 0;
1668	uint64_t cBalloonPages = 0;
1669	uint64_t cSharedPages = 0;
1670	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
1671	AssertRCReturn(rc, rc);
1672
1673	if (pcbAllocMem)
1674	pcbAllocMem = cAllocPages _4K;
1675
1676	if (pcbFreeMem)
1677	pcbFreeMem = cFreePages _4K;
1678
1679	if (pcbBallonedMem)
1680	pcbBallonedMem = cBalloonPages _4K;
1681
1682	if (pcbSharedMem)
1683	pcbSharedMem = cSharedPages _4K;
1684
1685	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
1686	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
1687	return VINF_SUCCESS;
1688	}
1689
1690
1691	/**
1692	* Query memory stats for the VM.
1693	*
1694	* @returns VBox status code.
1695	* @param pUVM The user mode VM handle.
1696	* @param pcbTotalMem Where to return total amount memory the VM may
1697	* possibly use.
1698	* @param pcbPrivateMem Where to return the amount of private memory
1699	* currently allocated.
1700	* @param pcbSharedMem Where to return the amount of actually shared
1701	* memory currently used by the VM.
1702	* @param pcbZeroMem Where to return the amount of memory backed by
1703	* zero pages.
1704	*
1705	* @remarks The total mem is normally larger than the sum of the three
1706	* components. There are two reasons for this, first the amount of
1707	* shared memory is what we're sure is shared instead of what could
1708	* possibly be shared with someone. Secondly, because the total may
1709	* include some pure MMIO pages that doesn't go into any of the three
1710	* sub-counts.
1711	*
1712	* @todo Why do we return reused shared pages instead of anything that could
1713	* potentially be shared? Doesn't this mean the first VM gets a much
1714	* lower number of shared pages?
1715	*/
1716	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
1717	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
1718	{
1719	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1720	PVM pVM = pUVM->pVM;
1721	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1722
1723	if (pcbTotalMem)
1724	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
1725
1726	if (pcbPrivateMem)
1727	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
1728
1729	if (pcbSharedMem)
1730	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
1731
1732	if (pcbZeroMem)
1733	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
1734
1735	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
1736	return VINF_SUCCESS;
1737	}
1738
1739
1740	/**
1741	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1742	*
1743	* @param pVM The cross context VM structure.
1744	* @param pNew The new RAM range.
1745	* @param GCPhys The address of the RAM range.
1746	* @param GCPhysLast The last address of the RAM range.
1747	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
1748	* if in HMA.
1749	* @param R0PtrNew Ditto for R0.
1750	* @param pszDesc The description.
1751	* @param pPrev The previous RAM range (for linking).
1752	*/
1753	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1754	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
1755	{
1756	/*
1757	* Initialize the range.
1758	*/
1759	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
1760	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
1761	pNew->GCPhys = GCPhys;
1762	pNew->GCPhysLast = GCPhysLast;
1763	pNew->cb = GCPhysLast - GCPhys + 1;
1764	pNew->pszDesc = pszDesc;
1765	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
1766	pNew->pvR3 = NULL;
1767	pNew->paLSPages = NULL;
1768
1769	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1770	RTGCPHYS iPage = cPages;
1771	while (iPage-- > 0)
1772	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1773
1774	/* Update the page count stats. */
1775	pVM->pgm.s.cZeroPages += cPages;
1776	pVM->pgm.s.cAllPages += cPages;
1777
1778	/*
1779	* Link it.
1780	*/
1781	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1782	}
1783
1784
1785	/**
1786	* @callback_method_impl{FNPGMRELOCATE, Relocate a floating RAM range.}
1787	* @sa pgmR3PhysMMIO2ExRangeRelocate
1788	*/
1789	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
1790	PGMRELOCATECALL enmMode, void *pvUser)
1791	{
1792	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1793	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1794	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE); RT_NOREF_PV(GCPtrOld);
1795
1796	switch (enmMode)
1797	{
1798	case PGMRELOCATECALL_SUGGEST:
1799	return true;
1800
1801	case PGMRELOCATECALL_RELOCATE:
1802	{
1803	/*
1804	* Update myself, then relink all the ranges and flush the RC TLB.
1805	*/
1806	pgmLock(pVM);
1807
1808	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1809
1810	pgmR3PhysRelinkRamRanges(pVM);
1811	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
1812	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
1813
1814	pgmUnlock(pVM);
1815	return true;
1816	}
1817
1818	default:
1819	AssertFailedReturn(false);
1820	}
1821	}
1822
1823
1824	/**
1825	* PGMR3PhysRegisterRam worker that registers a high chunk.
1826	*
1827	* @returns VBox status code.
1828	* @param pVM The cross context VM structure.
1829	* @param GCPhys The address of the RAM.
1830	* @param cRamPages The number of RAM pages to register.
1831	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1832	* @param iChunk The chunk number.
1833	* @param pszDesc The RAM range description.
1834	* @param ppPrev Previous RAM range pointer. In/Out.
1835	*/
1836	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1837	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1838	PPGMRAMRANGE *ppPrev)
1839	{
1840	const char *pszDescChunk = iChunk == 0
1841	? pszDesc
1842	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1843	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1844
1845	/*
1846	* Allocate memory for the new chunk.
1847	*/
1848	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1849	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1850	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1851	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1852	void *pvChunk = NULL;
1853	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
1854	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
1855	&R0PtrChunk,
1856	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
1857	VM_IS_HM_OR_NEM_ENABLED(pVM) ? &R0PtrChunk : NULL,
1858	#else
1859	NULL,
1860	#endif
1861	paChunkPages);
1862	if (RT_SUCCESS(rc))
1863	{
1864	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
1865	Assert(R0PtrChunk != NIL_RTR0PTR);
1866	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
1867	if (!VM_IS_HM_OR_NEM_ENABLED(pVM))
1868	R0PtrChunk = NIL_RTR0PTR;
1869	#else
1870	R0PtrChunk = (uintptr_t)pvChunk;
1871	#endif
1872	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1873
1874	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1875
1876	/*
1877	* Create a mapping and map the pages into it.
1878	* We push these in below the HMA.
1879	*/
1880	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1881	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1882	if (RT_SUCCESS(rc))
1883	{
1884	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1885
1886	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1887	RTGCPTR GCPtrPage = GCPtrChunk;
1888	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1889	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1890	if (RT_SUCCESS(rc))
1891	{
1892	/*
1893	* Ok, init and link the range.
1894	*/
1895	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1896	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1897	*ppPrev = pNew;
1898	}
1899	}
1900
1901	if (RT_FAILURE(rc))
1902	SUPR3PageFreeEx(pvChunk, cChunkPages);
1903	}
1904
1905	RTMemTmpFree(paChunkPages);
1906	return rc;
1907	}
1908
1909
1910	/**
1911	* Sets up a range RAM.
1912	*
1913	* This will check for conflicting registrations, make a resource
1914	* reservation for the memory (with GMM), and setup the per-page
1915	* tracking structures (PGMPAGE).
1916	*
1917	* @returns VBox status code.
1918	* @param pVM The cross context VM structure.
1919	* @param GCPhys The physical address of the RAM.
1920	* @param cb The size of the RAM.
1921	* @param pszDesc The description - not copied, so, don't free or change it.
1922	*/
1923	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1924	{
1925	/*
1926	* Validate input.
1927	*/
1928	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1929	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1930	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1931	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1932	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1933	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1934	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1935	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1936
1937	pgmLock(pVM);
1938
1939	/*
1940	* Find range location and check for conflicts.
1941	* (We don't lock here because the locking by EMT is only required on update.)
1942	*/
1943	PPGMRAMRANGE pPrev = NULL;
1944	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1945	while (pRam && GCPhysLast >= pRam->GCPhys)
1946	{
1947	if ( GCPhysLast >= pRam->GCPhys
1948	&& GCPhys <= pRam->GCPhysLast)
1949	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1950	GCPhys, GCPhysLast, pszDesc,
1951	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1952	VERR_PGM_RAM_CONFLICT);
1953
1954	/* next */
1955	pPrev = pRam;
1956	pRam = pRam->pNextR3;
1957	}
1958
1959	/*
1960	* Register it with GMM (the API bitches).
1961	*/
1962	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1963	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1964	if (RT_FAILURE(rc))
1965	{
1966	pgmUnlock(pVM);
1967	return rc;
1968	}
1969
1970	if ( GCPhys >= _4G
1971	&& cPages > 256)
1972	{
1973	/*
1974	* The PGMRAMRANGE structures for the high memory can get very big.
1975	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1976	* allocation size limit there and also to avoid being unable to find
1977	* guest mapping space for them, we split this memory up into 4MB in
1978	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1979	* mode.
1980	*
1981	* The first and last page of each mapping are guard pages and marked
1982	* not-present. So, we've got 4186112 and 16769024 bytes available for
1983	* the PGMRAMRANGE structure.
1984	*
1985	* Note! The sizes used here will influence the saved state.
1986	*/
1987	uint32_t cbChunk;
1988	uint32_t cPagesPerChunk;
1989	if (!VM_IS_RAW_MODE_ENABLED(pVM))
1990	{
1991	cbChunk = 16U*_1M;
1992	cPagesPerChunk = 1048048; /* max ~1048059 */
1993	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1994	}
1995	else
1996	{
1997	cbChunk = 4U*_1M;
1998	cPagesPerChunk = 261616; /* max ~261627 */
1999	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
2000	}
2001	AssertRelease(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
2002
2003	RTGCPHYS cPagesLeft = cPages;
2004	RTGCPHYS GCPhysChunk = GCPhys;
2005	uint32_t iChunk = 0;
2006	while (cPagesLeft > 0)
2007	{
2008	uint32_t cPagesInChunk = cPagesLeft;
2009	if (cPagesInChunk > cPagesPerChunk)
2010	cPagesInChunk = cPagesPerChunk;
2011
2012	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
2013	AssertRCReturn(rc, rc);
2014
2015	/* advance */
2016	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
2017	cPagesLeft -= cPagesInChunk;
2018	iChunk++;
2019	}
2020	}
2021	else
2022	{
2023	/*
2024	* Allocate, initialize and link the new RAM range.
2025	*/
2026	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
2027	PPGMRAMRANGE pNew;
2028	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2029	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
2030
2031	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
2032	}
2033	pgmPhysInvalidatePageMapTLB(pVM);
2034
2035	/*
2036	* Notify NEM while holding the lock (experimental) and REM without (like always).
2037	*/
2038	rc = NEMR3NotifyPhysRamRegister(pVM, GCPhys, cb);
2039	pgmUnlock(pVM);
2040	#ifdef VBOX_WITH_REM
2041	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
2042	#endif
2043	return rc;
2044	}
2045
2046
2047	/**
2048	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
2049	*
2050	* We do this late in the init process so that all the ROM and MMIO ranges have
2051	* been registered already and we don't go wasting memory on them.
2052	*
2053	* @returns VBox status code.
2054	*
2055	* @param pVM The cross context VM structure.
2056	*/
2057	int pgmR3PhysRamPreAllocate(PVM pVM)
2058	{
2059	Assert(pVM->pgm.s.fRamPreAlloc);
2060	Log(("pgmR3PhysRamPreAllocate: enter\n"));
2061
2062	/*
2063	* Walk the RAM ranges and allocate all RAM pages, halt at
2064	* the first allocation error.
2065	*/
2066	uint64_t cPages = 0;
2067	uint64_t NanoTS = RTTimeNanoTS();
2068	pgmLock(pVM);
2069	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2070	{
2071	PPGMPAGE pPage = &pRam->aPages[0];
2072	RTGCPHYS GCPhys = pRam->GCPhys;
2073	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
2074	while (cLeft-- > 0)
2075	{
2076	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2077	{
2078	switch (PGM_PAGE_GET_STATE(pPage))
2079	{
2080	case PGM_PAGE_STATE_ZERO:
2081	{
2082	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
2083	if (RT_FAILURE(rc))
2084	{
2085	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
2086	pgmUnlock(pVM);
2087	return rc;
2088	}
2089	cPages++;
2090	break;
2091	}
2092
2093	case PGM_PAGE_STATE_BALLOONED:
2094	case PGM_PAGE_STATE_ALLOCATED:
2095	case PGM_PAGE_STATE_WRITE_MONITORED:
2096	case PGM_PAGE_STATE_SHARED:
2097	/* nothing to do here. */
2098	break;
2099	}
2100	}
2101
2102	/* next */
2103	pPage++;
2104	GCPhys += PAGE_SIZE;
2105	}
2106	}
2107	pgmUnlock(pVM);
2108	NanoTS = RTTimeNanoTS() - NanoTS;
2109
2110	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
2111	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
2112	return VINF_SUCCESS;
2113	}
2114
2115
2116	/**
2117	* Checks shared page checksums.
2118	*
2119	* @param pVM The cross context VM structure.
2120	*/
2121	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
2122	{
2123	#ifdef VBOX_STRICT
2124	pgmLock(pVM);
2125
2126	if (pVM->pgm.s.cSharedPages > 0)
2127	{
2128	/*
2129	* Walk the ram ranges.
2130	*/
2131	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2132	{
2133	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2134	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2135
2136	while (iPage-- > 0)
2137	{
2138	PPGMPAGE pPage = &pRam->aPages[iPage];
2139	if (PGM_PAGE_IS_SHARED(pPage))
2140	{
2141	uint32_t u32Checksum = pPage->s.u2Unused0/* \| ((uint32_t)pPage->s.u2Unused1 << 8)*/;
2142	if (!u32Checksum)
2143	{
2144	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2145	void const *pvPage;
2146	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
2147	if (RT_SUCCESS(rc))
2148	{
2149	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
2150	# if 0
2151	AssertMsg((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
2152	# else
2153	if ((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum)
2154	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
2155	else
2156	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
2157	# endif
2158	}
2159	else
2160	AssertRC(rc);
2161	}
2162	}
2163
2164	} /* for each page */
2165
2166	} /* for each ram range */
2167	}
2168
2169	pgmUnlock(pVM);
2170	#endif /* VBOX_STRICT */
2171	NOREF(pVM);
2172	}
2173
2174
2175	/**
2176	* Resets the physical memory state.
2177	*
2178	* ASSUMES that the caller owns the PGM lock.
2179	*
2180	* @returns VBox status code.
2181	* @param pVM The cross context VM structure.
2182	*/
2183	int pgmR3PhysRamReset(PVM pVM)
2184	{
2185	PGM_LOCK_ASSERT_OWNER(pVM);
2186
2187	/* Reset the memory balloon. */
2188	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2189	AssertRC(rc);
2190
2191	#ifdef VBOX_WITH_PAGE_SHARING
2192	/* Clear all registered shared modules. */
2193	pgmR3PhysAssertSharedPageChecksums(pVM);
2194	rc = GMMR3ResetSharedModules(pVM);
2195	AssertRC(rc);
2196	#endif
2197	/* Reset counters. */
2198	pVM->pgm.s.cReusedSharedPages = 0;
2199	pVM->pgm.s.cBalloonedPages = 0;
2200
2201	return VINF_SUCCESS;
2202	}
2203
2204
2205	/**
2206	* Resets (zeros) the RAM after all devices and components have been reset.
2207	*
2208	* ASSUMES that the caller owns the PGM lock.
2209	*
2210	* @returns VBox status code.
2211	* @param pVM The cross context VM structure.
2212	*/
2213	int pgmR3PhysRamZeroAll(PVM pVM)
2214	{
2215	PGM_LOCK_ASSERT_OWNER(pVM);
2216
2217	/*
2218	* We batch up pages that should be freed instead of calling GMM for
2219	* each and every one of them.
2220	*/
2221	uint32_t cPendingPages = 0;
2222	PGMMFREEPAGESREQ pReq;
2223	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2224	AssertLogRelRCReturn(rc, rc);
2225
2226	/*
2227	* Walk the ram ranges.
2228	*/
2229	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2230	{
2231	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2232	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2233
2234	if ( !pVM->pgm.s.fRamPreAlloc
2235	&& pVM->pgm.s.fZeroRamPagesOnReset)
2236	{
2237	/* Replace all RAM pages by ZERO pages. */
2238	while (iPage-- > 0)
2239	{
2240	PPGMPAGE pPage = &pRam->aPages[iPage];
2241	switch (PGM_PAGE_GET_TYPE(pPage))
2242	{
2243	case PGMPAGETYPE_RAM:
2244	/* Do not replace pages part of a 2 MB continuous range
2245	with zero pages, but zero them instead. */
2246	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
2247	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2248	{
2249	void *pvPage;
2250	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2251	AssertLogRelRCReturn(rc, rc);
2252	ASMMemZeroPage(pvPage);
2253	}
2254	else if (PGM_PAGE_IS_BALLOONED(pPage))
2255	{
2256	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2257	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2258	}
2259	else if (!PGM_PAGE_IS_ZERO(pPage))
2260	{
2261	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2262	PGMPAGETYPE_RAM);
2263	AssertLogRelRCReturn(rc, rc);
2264	}
2265	break;
2266
2267	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2268	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2269	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2270	true /fDoAccounting/);
2271	break;
2272
2273	case PGMPAGETYPE_MMIO2:
2274	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2275	case PGMPAGETYPE_ROM:
2276	case PGMPAGETYPE_MMIO:
2277	break;
2278	default:
2279	AssertFailed();
2280	}
2281	} /* for each page */
2282	}
2283	else
2284	{
2285	/* Zero the memory. */
2286	while (iPage-- > 0)
2287	{
2288	PPGMPAGE pPage = &pRam->aPages[iPage];
2289	switch (PGM_PAGE_GET_TYPE(pPage))
2290	{
2291	case PGMPAGETYPE_RAM:
2292	switch (PGM_PAGE_GET_STATE(pPage))
2293	{
2294	case PGM_PAGE_STATE_ZERO:
2295	break;
2296
2297	case PGM_PAGE_STATE_BALLOONED:
2298	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2299	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2300	break;
2301
2302	case PGM_PAGE_STATE_SHARED:
2303	case PGM_PAGE_STATE_WRITE_MONITORED:
2304	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2305	AssertLogRelRCReturn(rc, rc);
2306	RT_FALL_THRU();
2307
2308	case PGM_PAGE_STATE_ALLOCATED:
2309	if (pVM->pgm.s.fZeroRamPagesOnReset)
2310	{
2311	void *pvPage;
2312	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2313	AssertLogRelRCReturn(rc, rc);
2314	ASMMemZeroPage(pvPage);
2315	}
2316	break;
2317	}
2318	break;
2319
2320	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2321	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2322	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2323	true /fDoAccounting/);
2324	break;
2325
2326	case PGMPAGETYPE_MMIO2:
2327	case PGMPAGETYPE_ROM_SHADOW:
2328	case PGMPAGETYPE_ROM:
2329	case PGMPAGETYPE_MMIO:
2330	break;
2331	default:
2332	AssertFailed();
2333
2334	}
2335	} /* for each page */
2336	}
2337
2338	}
2339
2340	/*
2341	* Finish off any pages pending freeing.
2342	*/
2343	if (cPendingPages)
2344	{
2345	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2346	AssertLogRelRCReturn(rc, rc);
2347	}
2348	GMMR3FreePagesCleanup(pReq);
2349	return VINF_SUCCESS;
2350	}
2351
2352
2353	/**
2354	* Frees all RAM during VM termination
2355	*
2356	* ASSUMES that the caller owns the PGM lock.
2357	*
2358	* @returns VBox status code.
2359	* @param pVM The cross context VM structure.
2360	*/
2361	int pgmR3PhysRamTerm(PVM pVM)
2362	{
2363	PGM_LOCK_ASSERT_OWNER(pVM);
2364
2365	/* Reset the memory balloon. */
2366	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2367	AssertRC(rc);
2368
2369	#ifdef VBOX_WITH_PAGE_SHARING
2370	/*
2371	* Clear all registered shared modules.
2372	*/
2373	pgmR3PhysAssertSharedPageChecksums(pVM);
2374	rc = GMMR3ResetSharedModules(pVM);
2375	AssertRC(rc);
2376
2377	/*
2378	* Flush the handy pages updates to make sure no shared pages are hiding
2379	* in there. (No unlikely if the VM shuts down, apparently.)
2380	*/
2381	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2382	#endif
2383
2384	/*
2385	* We batch up pages that should be freed instead of calling GMM for
2386	* each and every one of them.
2387	*/
2388	uint32_t cPendingPages = 0;
2389	PGMMFREEPAGESREQ pReq;
2390	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2391	AssertLogRelRCReturn(rc, rc);
2392
2393	/*
2394	* Walk the ram ranges.
2395	*/
2396	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2397	{
2398	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2399	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2400
2401	while (iPage-- > 0)
2402	{
2403	PPGMPAGE pPage = &pRam->aPages[iPage];
2404	switch (PGM_PAGE_GET_TYPE(pPage))
2405	{
2406	case PGMPAGETYPE_RAM:
2407	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2408	/** @todo change this to explicitly free private pages here. */
2409	if (PGM_PAGE_IS_SHARED(pPage))
2410	{
2411	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2412	PGMPAGETYPE_RAM);
2413	AssertLogRelRCReturn(rc, rc);
2414	}
2415	break;
2416
2417	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2418	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2419	case PGMPAGETYPE_MMIO2:
2420	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2421	case PGMPAGETYPE_ROM:
2422	case PGMPAGETYPE_MMIO:
2423	break;
2424	default:
2425	AssertFailed();
2426	}
2427	} /* for each page */
2428	}
2429
2430	/*
2431	* Finish off any pages pending freeing.
2432	*/
2433	if (cPendingPages)
2434	{
2435	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2436	AssertLogRelRCReturn(rc, rc);
2437	}
2438	GMMR3FreePagesCleanup(pReq);
2439	return VINF_SUCCESS;
2440	}
2441
2442
2443	/**
2444	* This is the interface IOM is using to register an MMIO region.
2445	*
2446	* It will check for conflicts and ensure that a RAM range structure
2447	* is present before calling the PGMR3HandlerPhysicalRegister API to
2448	* register the callbacks.
2449	*
2450	* @returns VBox status code.
2451	*
2452	* @param pVM The cross context VM structure.
2453	* @param GCPhys The start of the MMIO region.
2454	* @param cb The size of the MMIO region.
2455	* @param hType The physical access handler type registration.
2456	* @param pvUserR3 The user argument for R3.
2457	* @param pvUserR0 The user argument for R0.
2458	* @param pvUserRC The user argument for RC.
2459	* @param pszDesc The description of the MMIO region.
2460	*/
2461	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2462	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2463	{
2464	/*
2465	* Assert on some assumption.
2466	*/
2467	VM_ASSERT_EMT(pVM);
2468	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2469	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2470	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2471	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2472	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2473
2474	int rc = pgmLock(pVM);
2475	AssertRCReturn(rc, rc);
2476
2477	/*
2478	* Make sure there's a RAM range structure for the region.
2479	*/
2480	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2481	bool fRamExists = false;
2482	PPGMRAMRANGE pRamPrev = NULL;
2483	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2484	while (pRam && GCPhysLast >= pRam->GCPhys)
2485	{
2486	if ( GCPhysLast >= pRam->GCPhys
2487	&& GCPhys <= pRam->GCPhysLast)
2488	{
2489	/* Simplification: all within the same range. */
2490	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2491	&& GCPhysLast <= pRam->GCPhysLast,
2492	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2493	GCPhys, GCPhysLast, pszDesc,
2494	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2495	pgmUnlock(pVM),
2496	VERR_PGM_RAM_CONFLICT);
2497
2498	/* Check that it's all RAM or MMIO pages. */
2499	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2500	uint32_t cLeft = cb >> PAGE_SHIFT;
2501	while (cLeft-- > 0)
2502	{
2503	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2504	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2505	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2506	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2507	pgmUnlock(pVM),
2508	VERR_PGM_RAM_CONFLICT);
2509	pPage++;
2510	}
2511
2512	/* Looks good. */
2513	fRamExists = true;
2514	break;
2515	}
2516
2517	/* next */
2518	pRamPrev = pRam;
2519	pRam = pRam->pNextR3;
2520	}
2521	PPGMRAMRANGE pNew;
2522	if (fRamExists)
2523	{
2524	pNew = NULL;
2525
2526	/*
2527	* Make all the pages in the range MMIO/ZERO pages, freeing any
2528	* RAM pages currently mapped here. This might not be 100% correct
2529	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2530	*/
2531	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
2532	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
2533
2534	/* Force a PGM pool flush as guest ram references have been changed. */
2535	/** @todo not entirely SMP safe; assuming for now the guest takes
2536	* care of this internally (not touch mapped mmio while changing the
2537	* mapping). */
2538	PVMCPU pVCpu = VMMGetCpu(pVM);
2539	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2540	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2541	}
2542	else
2543	{
2544
2545	/*
2546	* No RAM range, insert an ad hoc one.
2547	*
2548	* Note that we don't have to tell REM about this range because
2549	* PGMHandlerPhysicalRegisterEx will do that for us.
2550	*/
2551	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2552
2553	const uint32_t cPages = cb >> PAGE_SHIFT;
2554	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
2555	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2556	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), pgmUnlock(pVM), rc);
2557
2558	/* Initialize the range. */
2559	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2560	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
2561	pNew->GCPhys = GCPhys;
2562	pNew->GCPhysLast = GCPhysLast;
2563	pNew->cb = cb;
2564	pNew->pszDesc = pszDesc;
2565	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2566	pNew->pvR3 = NULL;
2567	pNew->paLSPages = NULL;
2568
2569	uint32_t iPage = cPages;
2570	while (iPage-- > 0)
2571	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2572	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2573
2574	/* update the page count stats. */
2575	pVM->pgm.s.cPureMmioPages += cPages;
2576	pVM->pgm.s.cAllPages += cPages;
2577
2578	/* link it */
2579	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2580	}
2581
2582	/*
2583	* Register the access handler.
2584	*/
2585	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2586	if ( RT_FAILURE(rc)
2587	&& !fRamExists)
2588	{
2589	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2590	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2591
2592	/* remove the ad hoc range. */
2593	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2594	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2595	MMHyperFree(pVM, pRam);
2596	}
2597	pgmPhysInvalidatePageMapTLB(pVM);
2598
2599	pgmUnlock(pVM);
2600	return rc;
2601	}
2602
2603
2604	/**
2605	* This is the interface IOM is using to register an MMIO region.
2606	*
2607	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2608	* any ad hoc PGMRAMRANGE left behind.
2609	*
2610	* @returns VBox status code.
2611	* @param pVM The cross context VM structure.
2612	* @param GCPhys The start of the MMIO region.
2613	* @param cb The size of the MMIO region.
2614	*/
2615	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2616	{
2617	VM_ASSERT_EMT(pVM);
2618
2619	int rc = pgmLock(pVM);
2620	AssertRCReturn(rc, rc);
2621
2622	/*
2623	* First deregister the handler, then check if we should remove the ram range.
2624	*/
2625	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2626	if (RT_SUCCESS(rc))
2627	{
2628	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2629	PPGMRAMRANGE pRamPrev = NULL;
2630	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2631	while (pRam && GCPhysLast >= pRam->GCPhys)
2632	{
2633	/** @todo We're being a bit too careful here. rewrite. */
2634	if ( GCPhysLast == pRam->GCPhysLast
2635	&& GCPhys == pRam->GCPhys)
2636	{
2637	Assert(pRam->cb == cb);
2638
2639	/*
2640	* See if all the pages are dead MMIO pages.
2641	*/
2642	uint32_t const cPages = cb >> PAGE_SHIFT;
2643	bool fAllMMIO = true;
2644	uint32_t iPage = 0;
2645	uint32_t cLeft = cPages;
2646	while (cLeft-- > 0)
2647	{
2648	PPGMPAGE pPage = &pRam->aPages[iPage];
2649	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2650	/\|\| not-out-of-action later /)
2651	{
2652	fAllMMIO = false;
2653	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2654	break;
2655	}
2656	Assert( PGM_PAGE_IS_ZERO(pPage)
2657	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2658	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2659	pPage++;
2660	}
2661	if (fAllMMIO)
2662	{
2663	/*
2664	* Ad-hoc range, unlink and free it.
2665	*/
2666	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2667	GCPhys, GCPhysLast, pRam->pszDesc));
2668
2669	pVM->pgm.s.cAllPages -= cPages;
2670	pVM->pgm.s.cPureMmioPages -= cPages;
2671
2672	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2673	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2674	MMHyperFree(pVM, pRam);
2675	break;
2676	}
2677	}
2678
2679	/*
2680	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2681	*/
2682	if ( GCPhysLast >= pRam->GCPhys
2683	&& GCPhys <= pRam->GCPhysLast)
2684	{
2685	Assert(GCPhys >= pRam->GCPhys);
2686	Assert(GCPhysLast <= pRam->GCPhysLast);
2687
2688	/*
2689	* Turn the pages back into RAM pages.
2690	*/
2691	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2692	uint32_t cLeft = cb >> PAGE_SHIFT;
2693	while (cLeft--)
2694	{
2695	PPGMPAGE pPage = &pRam->aPages[iPage];
2696	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2697	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2698	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2699	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2700	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2701	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2702	}
2703	break;
2704	}
2705
2706	/* next */
2707	pRamPrev = pRam;
2708	pRam = pRam->pNextR3;
2709	}
2710	}
2711
2712	/* Force a PGM pool flush as guest ram references have been changed. */
2713	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2714	* this internally (not touch mapped mmio while changing the mapping). */
2715	PVMCPU pVCpu = VMMGetCpu(pVM);
2716	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2717	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2718
2719	pgmPhysInvalidatePageMapTLB(pVM);
2720	pgmPhysInvalidRamRangeTlbs(pVM);
2721	pgmUnlock(pVM);
2722	return rc;
2723	}
2724
2725
2726	/**
2727	* Locate a MMIO2 range.
2728	*
2729	* @returns Pointer to the MMIO2 range.
2730	* @param pVM The cross context VM structure.
2731	* @param pDevIns The device instance owning the region.
2732	* @param iSubDev The sub-device number.
2733	* @param iRegion The region.
2734	*/
2735	DECLINLINE(PPGMREGMMIORANGE) pgmR3PhysMMIOExFind(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion)
2736	{
2737	/*
2738	* Search the list. There shouldn't be many entries.
2739	*/
2740	/** @todo Optimize this lookup! There may now be many entries and it'll
2741	* become really slow when doing MMR3HyperMapMMIO2 and similar. */
2742	for (PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2743	if ( pCur->pDevInsR3 == pDevIns
2744	&& pCur->iRegion == iRegion
2745	&& pCur->iSubDev == iSubDev)
2746	return pCur;
2747	return NULL;
2748	}
2749
2750
2751	/**
2752	* @callback_method_impl{FNPGMRELOCATE, Relocate a floating MMIO/MMIO2 range.}
2753	* @sa pgmR3PhysRamRangeRelocate
2754	*/
2755	static DECLCALLBACK(bool) pgmR3PhysMMIOExRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
2756	PGMRELOCATECALL enmMode, void *pvUser)
2757	{
2758	PPGMREGMMIORANGE pMmio = (PPGMREGMMIORANGE)pvUser;
2759	Assert(pMmio->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
2760	Assert(pMmio->RamRange.pSelfRC == GCPtrOld + PAGE_SIZE + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange)); RT_NOREF_PV(GCPtrOld);
2761
2762	switch (enmMode)
2763	{
2764	case PGMRELOCATECALL_SUGGEST:
2765	return true;
2766
2767	case PGMRELOCATECALL_RELOCATE:
2768	{
2769	/*
2770	* Update myself, then relink all the ranges and flush the RC TLB.
2771	*/
2772	pgmLock(pVM);
2773
2774	pMmio->RamRange.pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange));
2775
2776	pgmR3PhysRelinkRamRanges(pVM);
2777	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2778	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2779
2780	pgmUnlock(pVM);
2781	return true;
2782	}
2783
2784	default:
2785	AssertFailedReturn(false);
2786	}
2787	}
2788
2789
2790	/**
2791	* Calculates the number of chunks
2792	*
2793	* @returns Number of registration chunk needed.
2794	* @param pVM The cross context VM structure.
2795	* @param cb The size of the MMIO/MMIO2 range.
2796	* @param pcPagesPerChunk Where to return the number of pages tracked by each
2797	* chunk. Optional.
2798	* @param pcbChunk Where to return the guest mapping size for a chunk.
2799	*/
2800	static uint16_t pgmR3PhysMMIOExCalcChunkCount(PVM pVM, RTGCPHYS cb, uint32_t pcPagesPerChunk, uint32_t pcbChunk)
2801	{
2802	RT_NOREF_PV(pVM); /* without raw mode */
2803
2804	/*
2805	* This is the same calculation as PGMR3PhysRegisterRam does, except we'll be
2806	* needing a few bytes extra the PGMREGMMIORANGE structure.
2807	*
2808	* Note! In additions, we've got a 24 bit sub-page range for MMIO2 ranges, leaving
2809	* us with an absolute maximum of 16777215 pages per chunk (close to 64 GB).
2810	*/
2811	uint32_t cbChunk;
2812	uint32_t cPagesPerChunk;
2813	if (!VM_IS_RAW_MODE_ENABLED(pVM))
2814	{
2815	cbChunk = 16U*_1M;
2816	cPagesPerChunk = 1048048; /* max ~1048059 */
2817	AssertCompile(sizeof(PGMREGMMIORANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
2818	}
2819	else
2820	{
2821	cbChunk = 4U*_1M;
2822	cPagesPerChunk = 261616; /* max ~261627 */
2823	AssertCompile(sizeof(PGMREGMMIORANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
2824	}
2825	AssertRelease(cPagesPerChunk <= PGM_MMIO2_MAX_PAGE_COUNT); /* See above note. */
2826	AssertRelease(RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
2827	if (pcbChunk)
2828	*pcbChunk = cbChunk;
2829	if (pcPagesPerChunk)
2830	*pcPagesPerChunk = cPagesPerChunk;
2831
2832	/* Calc the number of chunks we need. */
2833	RTGCPHYS const cPages = cb >> X86_PAGE_SHIFT;
2834	uint16_t cChunks = (uint16_t)((cPages + cPagesPerChunk - 1) / cPagesPerChunk);
2835	AssertRelease((RTGCPHYS)cChunks * cPagesPerChunk >= cPages);
2836	return cChunks;
2837	}
2838
2839
2840	/**
2841	* Worker for PGMR3PhysMMIOExPreRegister & PGMR3PhysMMIO2Register that allocates
2842	* and the PGMREGMMIORANGE structures and does basic initialization.
2843	*
2844	* Caller must set type specfic members and initialize the PGMPAGE structures.
2845	*
2846	* @returns VBox status code.
2847	* @param pVM The cross context VM structure.
2848	* @param pDevIns The device instance owning the region.
2849	* @param iSubDev The sub-device number (internal PCI config number).
2850	* @param iRegion The region number. If the MMIO2 memory is a PCI
2851	* I/O region this number has to be the number of that
2852	* region. Otherwise it can be any number safe
2853	* UINT8_MAX.
2854	* @param cb The size of the region. Must be page aligned.
2855	* @param pszDesc The description.
2856	* @param ppHeadRet Where to return the pointer to the first
2857	* registration chunk.
2858	*
2859	* @thread EMT
2860	*/
2861	static int pgmR3PhysMMIOExCreate(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2862	const char pszDesc, PPGMREGMMIORANGE ppHeadRet)
2863	{
2864	/*
2865	* Figure out how many chunks we need and of which size.
2866	*/
2867	uint32_t cPagesPerChunk;
2868	uint16_t cChunks = pgmR3PhysMMIOExCalcChunkCount(pVM, cb, &cPagesPerChunk, NULL);
2869	AssertReturn(cChunks, VERR_PGM_PHYS_MMIO_EX_IPE);
2870
2871	/*
2872	* Allocate the chunks.
2873	*/
2874	PPGMREGMMIORANGE *ppNext = ppHeadRet;
2875	*ppNext = NULL;
2876
2877	int rc = VINF_SUCCESS;
2878	uint32_t cPagesLeft = cb >> X86_PAGE_SHIFT;
2879	for (uint16_t iChunk = 0; iChunk < cChunks && RT_SUCCESS(rc); iChunk++)
2880	{
2881	/*
2882	* We currently do a single RAM range for the whole thing. This will
2883	* probably have to change once someone needs really large MMIO regions,
2884	* as we will be running into SUPR3PageAllocEx limitations and such.
2885	*/
2886	const uint32_t cPagesTrackedByChunk = RT_MIN(cPagesLeft, cPagesPerChunk);
2887	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPagesTrackedByChunk]);
2888	PPGMREGMMIORANGE pNew = NULL;
2889	if ( iChunk + 1 < cChunks
2890	\|\| cbRange >= _1M)
2891	{
2892	/*
2893	* Allocate memory for the registration structure.
2894	*/
2895	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2896	size_t const cbChunk = (1 + cChunkPages + 1) << PAGE_SHIFT;
2897	AssertLogRelBreakStmt(cbChunk == (uint32_t)cbChunk, rc = VERR_OUT_OF_RANGE);
2898	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
2899	AssertBreakStmt(paChunkPages, rc = VERR_NO_TMP_MEMORY);
2900	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
2901	void *pvChunk = NULL;
2902	rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
2903	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
2904	&R0PtrChunk,
2905	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
2906	VM_IS_HM_OR_NEM_ENABLED(pVM) ? &R0PtrChunk : NULL,
2907	#else
2908	NULL,
2909	#endif
2910	paChunkPages);
2911	AssertLogRelMsgRCBreakStmt(rc, ("rc=%Rrc, cChunkPages=%#zx\n", rc, cChunkPages), RTMemTmpFree(paChunkPages));
2912
2913	#if defined(VBOX_WITH_MORE_RING0_MEM_MAPPINGS)
2914	Assert(R0PtrChunk != NIL_RTR0PTR);
2915	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
2916	if (!VM_IS_HM_OR_NEM_ENABLED(pVM))
2917	R0PtrChunk = NIL_RTR0PTR;
2918	#else
2919	R0PtrChunk = (uintptr_t)pvChunk;
2920	#endif
2921	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
2922
2923	pNew = (PPGMREGMMIORANGE)pvChunk;
2924	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_FLOATING;
2925	pNew->RamRange.pSelfR0 = R0PtrChunk + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange);
2926
2927	/*
2928	* If we might end up in raw-mode, make a HMA mapping of the range,
2929	* just like we do for memory above 4GB.
2930	*/
2931	if (!VM_IS_RAW_MODE_ENABLED(pVM))
2932	pNew->RamRange.pSelfRC = NIL_RTRCPTR;
2933	else
2934	{
2935	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - RT_ALIGN_Z(cbChunk, _4M);
2936	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
2937	rc = PGMR3MapPT(pVM, GCPtrChunkMap, (uint32_t)cbChunk, 0 /fFlags/, pgmR3PhysMMIOExRangeRelocate, pNew, pszDesc);
2938	if (RT_SUCCESS(rc))
2939	{
2940	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
2941
2942	RTGCPTR GCPtrPage = GCPtrChunk;
2943	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
2944	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
2945	}
2946	if (RT_FAILURE(rc))
2947	{
2948	SUPR3PageFreeEx(pvChunk, cChunkPages);
2949	break;
2950	}
2951	pNew->RamRange.pSelfRC = GCPtrChunk + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange);
2952	}
2953	}
2954	/*
2955	* Not so big, do a one time hyper allocation.
2956	*/
2957	else
2958	{
2959	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2960	AssertLogRelMsgRCBreak(rc, ("cbRange=%zu\n", cbRange));
2961
2962	/*
2963	* Initialize allocation specific items.
2964	*/
2965	//pNew->RamRange.fFlags = 0;
2966	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2967	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
2968	}
2969
2970	/*
2971	* Initialize the registration structure (caller does specific bits).
2972	*/
2973	pNew->pDevInsR3 = pDevIns;
2974	//pNew->pvR3 = NULL;
2975	//pNew->pNext = NULL;
2976	//pNew->fFlags = 0;
2977	if (iChunk == 0)
2978	pNew->fFlags \|= PGMREGMMIORANGE_F_FIRST_CHUNK;
2979	if (iChunk + 1 == cChunks)
2980	pNew->fFlags \|= PGMREGMMIORANGE_F_LAST_CHUNK;
2981	pNew->iSubDev = iSubDev;
2982	pNew->iRegion = iRegion;
2983	pNew->idSavedState = UINT8_MAX;
2984	pNew->idMmio2 = UINT8_MAX;
2985	//pNew->pPhysHandlerR3 = NULL;
2986	//pNew->paLSPages = NULL;
2987	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2988	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2989	pNew->RamRange.pszDesc = pszDesc;
2990	pNew->RamRange.cb = pNew->cbReal = (RTGCPHYS)cPagesTrackedByChunk << X86_PAGE_SHIFT;
2991	pNew->RamRange.fFlags \|= PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX;
2992	//pNew->RamRange.pvR3 = NULL;
2993	//pNew->RamRange.paLSPages = NULL;
2994
2995	*ppNext = pNew;
2996	ASMCompilerBarrier();
2997	cPagesLeft -= cPagesTrackedByChunk;
2998	ppNext = &pNew->pNextR3;
2999	}
3000	Assert(cPagesLeft == 0);
3001
3002	if (RT_SUCCESS(rc))
3003	{
3004	Assert((*ppHeadRet)->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3005	return VINF_SUCCESS;
3006	}
3007
3008	/*
3009	* Free floating ranges.
3010	*/
3011	while (*ppHeadRet)
3012	{
3013	PPGMREGMMIORANGE pFree = *ppHeadRet;
3014	*ppHeadRet = pFree->pNextR3;
3015
3016	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3017	{
3018	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
3019	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3020	SUPR3PageFreeEx(pFree, cChunkPages);
3021	}
3022	}
3023
3024	return rc;
3025	}
3026
3027
3028	/**
3029	* Common worker PGMR3PhysMMIOExPreRegister & PGMR3PhysMMIO2Register that links
3030	* a complete registration entry into the lists and lookup tables.
3031	*
3032	* @param pVM The cross context VM structure.
3033	* @param pNew The new MMIO / MMIO2 registration to link.
3034	*/
3035	static void pgmR3PhysMMIOExLink(PVM pVM, PPGMREGMMIORANGE pNew)
3036	{
3037	/*
3038	* Link it into the list (order doesn't matter, so insert it at the head).
3039	*
3040	* Note! The range we're link may consist of multiple chunks, so we have to
3041	* find the last one.
3042	*/
3043	PPGMREGMMIORANGE pLast = pNew;
3044	for (pLast = pNew; ; pLast = pLast->pNextR3)
3045	{
3046	if (pLast->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3047	break;
3048	Assert(pLast->pNextR3);
3049	Assert(pLast->pNextR3->pDevInsR3 == pNew->pDevInsR3);
3050	Assert(pLast->pNextR3->iSubDev == pNew->iSubDev);
3051	Assert(pLast->pNextR3->iRegion == pNew->iRegion);
3052	Assert((pLast->pNextR3->fFlags & PGMREGMMIORANGE_F_MMIO2) == (pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
3053	Assert(pLast->pNextR3->idMmio2 == (pLast->fFlags & PGMREGMMIORANGE_F_MMIO2 ? pNew->idMmio2 + 1 : UINT8_MAX));
3054	}
3055
3056	pgmLock(pVM);
3057
3058	/* Link in the chain of ranges at the head of the list. */
3059	pLast->pNextR3 = pVM->pgm.s.pRegMmioRangesR3;
3060	pVM->pgm.s.pRegMmioRangesR3 = pNew;
3061
3062	/* If MMIO, insert the MMIO2 range/page IDs. */
3063	uint8_t idMmio2 = pNew->idMmio2;
3064	if (idMmio2 != UINT8_MAX)
3065	{
3066	for (;;)
3067	{
3068	Assert(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2);
3069	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
3070	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
3071	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
3072	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = pNew->RamRange.pSelfR0 - RT_UOFFSETOF(PGMREGMMIORANGE, RamRange);
3073	if (pNew->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3074	break;
3075	pNew = pNew->pNextR3;
3076	}
3077	}
3078	else
3079	Assert(!(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
3080
3081	pgmPhysInvalidatePageMapTLB(pVM);
3082	pgmUnlock(pVM);
3083	}
3084
3085
3086	/**
3087	* Allocate and pre-register an MMIO region.
3088	*
3089	* This is currently the way to deal with large MMIO regions. It may in the
3090	* future be extended to be the way we deal with all MMIO regions, but that
3091	* means we'll have to do something about the simple list based approach we take
3092	* to tracking the registrations.
3093	*
3094	* @returns VBox status code.
3095	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
3096	* memory.
3097	* @retval VERR_ALREADY_EXISTS if the region already exists.
3098	*
3099	* @param pVM The cross context VM structure.
3100	* @param pDevIns The device instance owning the region.
3101	* @param iSubDev The sub-device number.
3102	* @param iRegion The region number. If the MMIO2 memory is a PCI
3103	* I/O region this number has to be the number of that
3104	* region. Otherwise it can be any number safe
3105	* UINT8_MAX.
3106	* @param cbRegion The size of the region. Must be page aligned.
3107	* @param hType The physical handler callback type.
3108	* @param pvUserR3 User parameter for ring-3 context callbacks.
3109	* @param pvUserR0 User parameter for ring-0 context callbacks.
3110	* @param pvUserRC User parameter for raw-mode context callbacks.
3111	* @param pszDesc The description.
3112	*
3113	* @thread EMT
3114	*
3115	* @sa PGMR3PhysMMIORegister, PGMR3PhysMMIO2Register,
3116	* PGMR3PhysMMIOExMap, PGMR3PhysMMIOExUnmap, PGMR3PhysMMIOExDeregister.
3117	*/
3118	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion,
3119	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
3120	const char *pszDesc)
3121	{
3122	/*
3123	* Validate input.
3124	*/
3125	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3126	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3127	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3128	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3129	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3130	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3131	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion) == NULL, VERR_ALREADY_EXISTS);
3132	AssertReturn(!(cbRegion & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3133	AssertReturn(cbRegion, VERR_INVALID_PARAMETER);
3134
3135	const uint32_t cPages = cbRegion >> PAGE_SHIFT;
3136	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cbRegion, VERR_INVALID_PARAMETER);
3137	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3138
3139	/*
3140	* For the 2nd+ instance, mangle the description string so it's unique.
3141	*/
3142	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3143	{
3144	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3145	if (!pszDesc)
3146	return VERR_NO_MEMORY;
3147	}
3148
3149	/*
3150	* Register the MMIO callbacks.
3151	*/
3152	PPGMPHYSHANDLER pPhysHandler;
3153	int rc = pgmHandlerPhysicalExCreate(pVM, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc, &pPhysHandler);
3154	if (RT_SUCCESS(rc))
3155	{
3156	/*
3157	* Create the registered MMIO range record for it.
3158	*/
3159	PPGMREGMMIORANGE pNew;
3160	rc = pgmR3PhysMMIOExCreate(pVM, pDevIns, iSubDev, iRegion, cbRegion, pszDesc, &pNew);
3161	if (RT_SUCCESS(rc))
3162	{
3163	Assert(!(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
3164
3165	/*
3166	* Intialize the page structures and set up physical handlers (one for each chunk).
3167	*/
3168	for (PPGMREGMMIORANGE pCur = pNew; pCur != NULL && RT_SUCCESS(rc); pCur = pCur->pNextR3)
3169	{
3170	if (pCur == pNew)
3171	pCur->pPhysHandlerR3 = pPhysHandler;
3172	else
3173	rc = pgmHandlerPhysicalExDup(pVM, pPhysHandler, &pCur->pPhysHandlerR3);
3174
3175	uint32_t iPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3176	while (iPage-- > 0)
3177	PGM_PAGE_INIT_ZERO(&pCur->RamRange.aPages[iPage], pVM, PGMPAGETYPE_MMIO);
3178	}
3179	if (RT_SUCCESS(rc))
3180	{
3181	/*
3182	* Update the page count stats, link the registration and we're done.
3183	*/
3184	pVM->pgm.s.cAllPages += cPages;
3185	pVM->pgm.s.cPureMmioPages += cPages;
3186
3187	pgmR3PhysMMIOExLink(pVM, pNew);
3188	return VINF_SUCCESS;
3189	}
3190
3191	/*
3192	* Clean up in case we're out of memory for extra access handlers.
3193	*/
3194	while (pNew != NULL)
3195	{
3196	PPGMREGMMIORANGE pFree = pNew;
3197	pNew = pFree->pNextR3;
3198
3199	if (pFree->pPhysHandlerR3)
3200	{
3201	pgmHandlerPhysicalExDestroy(pVM, pFree->pPhysHandlerR3);
3202	pFree->pPhysHandlerR3 = NULL;
3203	}
3204
3205	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3206	{
3207	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
3208	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3209	SUPR3PageFreeEx(pFree, cChunkPages);
3210	}
3211	}
3212	}
3213	else
3214	pgmHandlerPhysicalExDestroy(pVM, pPhysHandler);
3215	}
3216	return rc;
3217	}
3218
3219
3220	/**
3221	* Allocate and register an MMIO2 region.
3222	*
3223	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
3224	* associated with a device. It is also non-shared memory with a permanent
3225	* ring-3 mapping and page backing (presently).
3226	*
3227	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
3228	* the VM, in which case we'll drop the base memory pages. Presently we will
3229	* make no attempt to preserve anything that happens to be present in the base
3230	* memory that is replaced, this is of course incorrect but it's too much
3231	* effort.
3232	*
3233	* @returns VBox status code.
3234	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
3235	* memory.
3236	* @retval VERR_ALREADY_EXISTS if the region already exists.
3237	*
3238	* @param pVM The cross context VM structure.
3239	* @param pDevIns The device instance owning the region.
3240	* @param iSubDev The sub-device number.
3241	* @param iRegion The region number. If the MMIO2 memory is a PCI
3242	* I/O region this number has to be the number of that
3243	* region. Otherwise it can be any number safe
3244	* UINT8_MAX.
3245	* @param cb The size of the region. Must be page aligned.
3246	* @param fFlags Reserved for future use, must be zero.
3247	* @param ppv Where to store the pointer to the ring-3 mapping of
3248	* the memory.
3249	* @param pszDesc The description.
3250	* @thread EMT
3251	*/
3252	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
3253	uint32_t fFlags, void *ppv, const char pszDesc)
3254	{
3255	/*
3256	* Validate input.
3257	*/
3258	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3259	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3260	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3261	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3262	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
3263	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3264	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3265	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion) == NULL, VERR_ALREADY_EXISTS);
3266	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3267	AssertReturn(cb, VERR_INVALID_PARAMETER);
3268	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
3269
3270	const uint32_t cPages = cb >> PAGE_SHIFT;
3271	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
3272	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3273
3274	/*
3275	* For the 2nd+ instance, mangle the description string so it's unique.
3276	*/
3277	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3278	{
3279	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3280	if (!pszDesc)
3281	return VERR_NO_MEMORY;
3282	}
3283
3284	/*
3285	* Allocate an MMIO2 range ID (not freed on failure).
3286	*
3287	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID, so
3288	* the IDs goes from 1 thru PGM_MMIO2_MAX_RANGES.
3289	*/
3290	unsigned cChunks = pgmR3PhysMMIOExCalcChunkCount(pVM, cb, NULL, NULL);
3291	pgmLock(pVM);
3292	uint8_t idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
3293	unsigned cNewMmio2Regions = pVM->pgm.s.cMmio2Regions + cChunks;
3294	if (cNewMmio2Regions > PGM_MMIO2_MAX_RANGES)
3295	{
3296	pgmUnlock(pVM);
3297	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
3298	}
3299	pVM->pgm.s.cMmio2Regions = cNewMmio2Regions;
3300	pgmUnlock(pVM);
3301
3302	/*
3303	* Try reserve and allocate the backing memory first as this is what is
3304	* most likely to fail.
3305	*/
3306	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
3307	if (RT_SUCCESS(rc))
3308	{
3309	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
3310	if (RT_SUCCESS(rc))
3311	{
3312	void *pvPages;
3313	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
3314	if (RT_SUCCESS(rc))
3315	{
3316	memset(pvPages, 0, cPages * PAGE_SIZE);
3317
3318	/*
3319	* Create the registered MMIO range record for it.
3320	*/
3321	PPGMREGMMIORANGE pNew;
3322	rc = pgmR3PhysMMIOExCreate(pVM, pDevIns, iSubDev, iRegion, cb, pszDesc, &pNew);
3323	if (RT_SUCCESS(rc))
3324	{
3325	uint32_t iSrcPage = 0;
3326	uint8_t pbCurPages = (uint8_t )pvPages;
3327	for (PPGMREGMMIORANGE pCur = pNew; pCur; pCur = pCur->pNextR3)
3328	{
3329	pCur->pvR3 = pbCurPages;
3330	pCur->RamRange.pvR3 = pbCurPages;
3331	pCur->idMmio2 = idMmio2;
3332	pCur->fFlags \|= PGMREGMMIORANGE_F_MMIO2;
3333
3334	uint32_t iDstPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3335	while (iDstPage-- > 0)
3336	{
3337	PGM_PAGE_INIT(&pNew->RamRange.aPages[iDstPage],
3338	paPages[iDstPage + iSrcPage].Phys,
3339	PGM_MMIO2_PAGEID_MAKE(idMmio2, iDstPage),
3340	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
3341	}
3342
3343	/* advance. */
3344	iSrcPage += pCur->RamRange.cb >> X86_PAGE_SHIFT;
3345	pbCurPages += pCur->RamRange.cb;
3346	idMmio2++;
3347	}
3348
3349	RTMemTmpFree(paPages);
3350
3351	/*
3352	* Update the page count stats, link the registration and we're done.
3353	*/
3354	pVM->pgm.s.cAllPages += cPages;
3355	pVM->pgm.s.cPrivatePages += cPages;
3356
3357	pgmR3PhysMMIOExLink(pVM, pNew);
3358
3359	*ppv = pvPages;
3360	return VINF_SUCCESS;
3361	}
3362
3363	SUPR3PageFreeEx(pvPages, cPages);
3364	}
3365	}
3366	RTMemTmpFree(paPages);
3367	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
3368	}
3369	if (pDevIns->iInstance > 0)
3370	MMR3HeapFree((void *)pszDesc);
3371	return rc;
3372	}
3373
3374
3375	/**
3376	* Deregisters and frees an MMIO2 region or a pre-registered MMIO region
3377	*
3378	* Any physical (and virtual) access handlers registered for the region must
3379	* be deregistered before calling this function.
3380	*
3381	* @returns VBox status code.
3382	* @param pVM The cross context VM structure.
3383	* @param pDevIns The device instance owning the region.
3384	* @param iSubDev The sub-device number. Pass UINT32_MAX for wildcard
3385	* matching.
3386	* @param iRegion The region. Pass UINT32_MAX for wildcard matching.
3387	*/
3388	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion)
3389	{
3390	/*
3391	* Validate input.
3392	*/
3393	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3394	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3395	AssertReturn(iSubDev <= UINT8_MAX \|\| iSubDev == UINT32_MAX, VERR_INVALID_PARAMETER);
3396	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
3397
3398	/*
3399	* The loop here scanning all registrations will make sure that multi-chunk ranges
3400	* get properly deregistered, though it's original purpose was the wildcard iRegion.
3401	*/
3402	pgmLock(pVM);
3403	int rc = VINF_SUCCESS;
3404	unsigned cFound = 0;
3405	PPGMREGMMIORANGE pPrev = NULL;
3406	PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3;
3407	while (pCur)
3408	{
3409	if ( pCur->pDevInsR3 == pDevIns
3410	&& ( iRegion == UINT32_MAX
3411	\|\| pCur->iRegion == iRegion)
3412	&& ( iSubDev == UINT32_MAX
3413	\|\| pCur->iSubDev == iSubDev) )
3414	{
3415	cFound++;
3416
3417	/*
3418	* Unmap it if it's mapped.
3419	*/
3420	if (pCur->fFlags & PGMREGMMIORANGE_F_MAPPED)
3421	{
3422	int rc2 = PGMR3PhysMMIOExUnmap(pVM, pCur->pDevInsR3, pCur->iSubDev, pCur->iRegion, pCur->RamRange.GCPhys);
3423	AssertRC(rc2);
3424	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3425	rc = rc2;
3426	}
3427
3428	/*
3429	* Must tell IOM about MMIO (first one only).
3430	*/
3431	if ((pCur->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK)) == PGMREGMMIORANGE_F_MMIO2)
3432	IOMR3MmioExNotifyDeregistered(pVM, pCur->pPhysHandlerR3->pvUserR3);
3433
3434	/*
3435	* Unlink it
3436	*/
3437	PPGMREGMMIORANGE pNext = pCur->pNextR3;
3438	if (pPrev)
3439	pPrev->pNextR3 = pNext;
3440	else
3441	pVM->pgm.s.pRegMmioRangesR3 = pNext;
3442	pCur->pNextR3 = NULL;
3443
3444	uint8_t idMmio2 = pCur->idMmio2;
3445	if (idMmio2 != UINT8_MAX)
3446	{
3447	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
3448	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
3449	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
3450	}
3451
3452	/*
3453	* Free the memory.
3454	*/
3455	uint32_t const cPages = pCur->cbReal >> PAGE_SHIFT;
3456	if (pCur->fFlags & PGMREGMMIORANGE_F_MMIO2)
3457	{
3458	int rc2 = SUPR3PageFreeEx(pCur->pvR3, cPages);
3459	AssertRC(rc2);
3460	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3461	rc = rc2;
3462
3463	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
3464	AssertRC(rc2);
3465	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3466	rc = rc2;
3467	}
3468
3469	/* we're leaking hyper memory here if done at runtime. */
3470	#ifdef VBOX_STRICT
3471	VMSTATE const enmState = VMR3GetState(pVM);
3472	AssertMsg( enmState == VMSTATE_POWERING_OFF
3473	\|\| enmState == VMSTATE_POWERING_OFF_LS
3474	\|\| enmState == VMSTATE_OFF
3475	\|\| enmState == VMSTATE_OFF_LS
3476	\|\| enmState == VMSTATE_DESTROYING
3477	\|\| enmState == VMSTATE_TERMINATED
3478	\|\| enmState == VMSTATE_CREATING
3479	, ("%s\n", VMR3GetStateName(enmState)));
3480	#endif
3481
3482	const bool fIsMmio2 = RT_BOOL(pCur->fFlags & PGMREGMMIORANGE_F_MMIO2);
3483	if (pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3484	{
3485	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPages]);
3486	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3487	SUPR3PageFreeEx(pCur, cChunkPages);
3488	}
3489	/*else
3490	{
3491	rc = MMHyperFree(pVM, pCur); - does not work, see the alloc call.
3492	AssertRCReturn(rc, rc);
3493	} */
3494
3495
3496	/* update page count stats */
3497	pVM->pgm.s.cAllPages -= cPages;
3498	if (fIsMmio2)
3499	pVM->pgm.s.cPrivatePages -= cPages;
3500	else
3501	pVM->pgm.s.cPureMmioPages -= cPages;
3502
3503	/* next */
3504	pCur = pNext;
3505	}
3506	else
3507	{
3508	pPrev = pCur;
3509	pCur = pCur->pNextR3;
3510	}
3511	}
3512	pgmPhysInvalidatePageMapTLB(pVM);
3513	pgmUnlock(pVM);
3514	return !cFound && iRegion != UINT32_MAX && iSubDev != UINT32_MAX ? VERR_NOT_FOUND : rc;
3515	}
3516
3517
3518	/**
3519	* Maps a MMIO2 region or a pre-registered MMIO region.
3520	*
3521	* This is done when a guest / the bios / state loading changes the
3522	* PCI config. The replacing of base memory has the same restrictions
3523	* as during registration, of course.
3524	*
3525	* @returns VBox status code.
3526	*
3527	* @param pVM The cross context VM structure.
3528	* @param pDevIns The device instance owning the region.
3529	* @param iSubDev The sub-device number of the registered region.
3530	* @param iRegion The index of the registered region.
3531	* @param GCPhys The guest-physical address to be remapped.
3532	*/
3533	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys)
3534	{
3535	/*
3536	* Validate input.
3537	*
3538	* Note! It's safe to walk the MMIO/MMIO2 list since registrations only
3539	* happens during VM construction.
3540	*/
3541	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3542	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3543	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3544	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3545	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3546	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3547	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3548
3549	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3550	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3551	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3552
3553	PPGMREGMMIORANGE pLastMmio = pFirstMmio;
3554	RTGCPHYS cbRange = 0;
3555	for (;;)
3556	{
3557	AssertReturn(!(pLastMmio->fFlags & PGMREGMMIORANGE_F_MAPPED), VERR_WRONG_ORDER);
3558	Assert(pLastMmio->RamRange.GCPhys == NIL_RTGCPHYS);
3559	Assert(pLastMmio->RamRange.GCPhysLast == NIL_RTGCPHYS);
3560	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3561	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3562	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3563	cbRange += pLastMmio->RamRange.cb;
3564	if (pLastMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3565	break;
3566	pLastMmio = pLastMmio->pNextR3;
3567	}
3568
3569	RTGCPHYS GCPhysLast = GCPhys + cbRange - 1;
3570	AssertLogRelReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3571
3572	/*
3573	* Find our location in the ram range list, checking for restriction
3574	* we don't bother implementing yet (partially overlapping, multiple
3575	* ram ranges).
3576	*/
3577	pgmLock(pVM);
3578
3579	AssertReturnStmt(!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED), pgmUnlock(pVM), VERR_WRONG_ORDER);
3580
3581	bool fRamExists = false;
3582	PPGMRAMRANGE pRamPrev = NULL;
3583	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3584	while (pRam && GCPhysLast >= pRam->GCPhys)
3585	{
3586	if ( GCPhys <= pRam->GCPhysLast
3587	&& GCPhysLast >= pRam->GCPhys)
3588	{
3589	/* Completely within? */
3590	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
3591	&& GCPhysLast <= pRam->GCPhysLast,
3592	("%RGp-%RGp (MMIOEx/%s) falls partly outside %RGp-%RGp (%s)\n",
3593	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc,
3594	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3595	pgmUnlock(pVM),
3596	VERR_PGM_RAM_CONFLICT);
3597
3598	/* Check that all the pages are RAM pages. */
3599	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3600	uint32_t cPagesLeft = cbRange >> PAGE_SHIFT;
3601	while (cPagesLeft-- > 0)
3602	{
3603	AssertLogRelMsgReturnStmt(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3604	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
3605	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc),
3606	pgmUnlock(pVM),
3607	VERR_PGM_RAM_CONFLICT);
3608	pPage++;
3609	}
3610
3611	/* There can only be one MMIO/MMIO2 chunk matching here! */
3612	AssertLogRelMsgReturnStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK,
3613	("%RGp-%RGp (MMIOEx/%s, flags %#X) consists of multiple chunks whereas the RAM somehow doesn't!\n",
3614	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3615	pgmUnlock(pVM),
3616	VERR_PGM_PHYS_MMIO_EX_IPE);
3617
3618	fRamExists = true;
3619	break;
3620	}
3621
3622	/* next */
3623	pRamPrev = pRam;
3624	pRam = pRam->pNextR3;
3625	}
3626	Log(("PGMR3PhysMMIOExMap: %RGp-%RGp fRamExists=%RTbool %s\n", GCPhys, GCPhysLast, fRamExists, pFirstMmio->RamRange.pszDesc));
3627
3628
3629	/*
3630	* Make the changes.
3631	*/
3632	RTGCPHYS GCPhysCur = GCPhys;
3633	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3634	{
3635	pCurMmio->RamRange.GCPhys = GCPhysCur;
3636	pCurMmio->RamRange.GCPhysLast = GCPhysCur + pCurMmio->RamRange.cb - 1;
3637	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3638	{
3639	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3640	break;
3641	}
3642	GCPhysCur += pCurMmio->RamRange.cb;
3643	}
3644
3645	if (fRamExists)
3646	{
3647	/*
3648	* Make all the pages in the range MMIO/ZERO pages, freeing any
3649	* RAM pages currently mapped here. This might not be 100% correct
3650	* for PCI memory, but we're doing the same thing for MMIO2 pages.
3651	*
3652	* We replace this MMIO/ZERO pages with real pages in the MMIO2 case.
3653	*/
3654	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK); /* Only one chunk */
3655
3656	int rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
3657	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
3658
3659	if (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2)
3660	{
3661	/* replace the pages, freeing all present RAM pages. */
3662	PPGMPAGE pPageSrc = &pFirstMmio->RamRange.aPages[0];
3663	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3664	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3665	while (cPagesLeft-- > 0)
3666	{
3667	Assert(PGM_PAGE_IS_MMIO(pPageDst));
3668
3669	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
3670	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
3671	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
3672	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
3673	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
3674	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
3675	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
3676	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
3677	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
3678	/* (We tell NEM at the end of the function.) */
3679
3680	pVM->pgm.s.cZeroPages--;
3681	GCPhys += PAGE_SIZE;
3682	pPageSrc++;
3683	pPageDst++;
3684	}
3685	}
3686
3687	/* Flush physical page map TLB. */
3688	pgmPhysInvalidatePageMapTLB(pVM);
3689
3690	/* Force a PGM pool flush as guest ram references have been changed. */
3691	/** @todo not entirely SMP safe; assuming for now the guest takes care of
3692	* this internally (not touch mapped mmio while changing the mapping). */
3693	PVMCPU pVCpu = VMMGetCpu(pVM);
3694	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3695	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3696	}
3697	else
3698	{
3699	/*
3700	* No RAM range, insert the ones prepared during registration.
3701	*/
3702	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3703	{
3704	/* Clear the tracking data of pages we're going to reactivate. */
3705	PPGMPAGE pPageSrc = &pCurMmio->RamRange.aPages[0];
3706	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3707	while (cPagesLeft-- > 0)
3708	{
3709	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
3710	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
3711	pPageSrc++;
3712	}
3713
3714	/* link in the ram range */
3715	pgmR3PhysLinkRamRange(pVM, &pCurMmio->RamRange, pRamPrev);
3716
3717	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3718	{
3719	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3720	break;
3721	}
3722	pRamPrev = &pCurMmio->RamRange;
3723	}
3724	}
3725
3726	/*
3727	* Register the access handler if plain MMIO.
3728	*
3729	* We must register access handlers for each range since the access handler
3730	* code refuses to deal with multiple ranges (and we can).
3731	*/
3732	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2))
3733	{
3734	int rc = VINF_SUCCESS;
3735	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3736	{
3737	Assert(!(pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED));
3738	rc = pgmHandlerPhysicalExRegister(pVM, pCurMmio->pPhysHandlerR3, pCurMmio->RamRange.GCPhys,
3739	pCurMmio->RamRange.GCPhysLast);
3740	if (RT_FAILURE(rc))
3741	break;
3742	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_MAPPED; /* Use this to mark that the handler is registered. */
3743	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3744	{
3745	rc = IOMR3MmioExNotifyMapped(pVM, pFirstMmio->pPhysHandlerR3->pvUserR3, GCPhys);
3746	break;
3747	}
3748	}
3749	if (RT_FAILURE(rc))
3750	{
3751	/* Almost impossible, but try clean up properly and get out of here. */
3752	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3753	{
3754	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED)
3755	{
3756	pCurMmio->fFlags &= ~PGMREGMMIORANGE_F_MAPPED;
3757	pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3, fRamExists);
3758	}
3759
3760	if (!fRamExists)
3761	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3762	else
3763	{
3764	Assert(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK); /* Only one chunk */
3765
3766	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3767	PPGMPAGE pPageDst = &pRam->aPages[(pCurMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3768	while (cPagesLeft-- > 0)
3769	{
3770	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3771	pPageDst++;
3772	}
3773	}
3774
3775	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3776	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3777	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3778	break;
3779	}
3780
3781	pgmUnlock(pVM);
3782	return rc;
3783	}
3784	}
3785
3786	/*
3787	* We're good, set the flags and invalid the mapping TLB.
3788	*/
3789	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3790	{
3791	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_MAPPED;
3792	if (fRamExists)
3793	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_OVERLAPPING;
3794	else
3795	pCurMmio->fFlags &= ~PGMREGMMIORANGE_F_OVERLAPPING;
3796	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3797	break;
3798	}
3799	pgmPhysInvalidatePageMapTLB(pVM);
3800
3801	/*
3802	* Notify NEM while holding the lock (experimental) and REM without (like always).
3803	*/
3804	uint32_t const fNemNotify = (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0)
3805	\| (pFirstMmio->fFlags & PGMREGMMIORANGE_F_OVERLAPPING ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
3806	int rc = NEMR3NotifyPhysMmioExMap(pVM, GCPhys, cbRange, fNemNotify, pFirstMmio->pvR3);
3807
3808	pgmUnlock(pVM);
3809
3810	#ifdef VBOX_WITH_REM
3811	if (!fRamExists && (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2)) /** @todo this doesn't look right. */
3812	REMR3NotifyPhysRamRegister(pVM, GCPhys, cbRange, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
3813	#endif
3814	return rc;
3815	}
3816
3817
3818	/**
3819	* Unmaps a MMIO2 or a pre-registered MMIO region.
3820	*
3821	* This is done when a guest / the bios / state loading changes the
3822	* PCI config. The replacing of base memory has the same restrictions
3823	* as during registration, of course.
3824	*/
3825	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys)
3826	{
3827	/*
3828	* Validate input
3829	*/
3830	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3831	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3832	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3833	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3834	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3835	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3836	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3837
3838	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3839	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3840	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3841
3842	PPGMREGMMIORANGE pLastMmio = pFirstMmio;
3843	RTGCPHYS cbRange = 0;
3844	for (;;)
3845	{
3846	AssertReturn(pLastMmio->fFlags & PGMREGMMIORANGE_F_MAPPED, VERR_WRONG_ORDER);
3847	AssertReturn(pLastMmio->RamRange.GCPhys == GCPhys + cbRange, VERR_INVALID_PARAMETER);
3848	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3849	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3850	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3851	cbRange += pLastMmio->RamRange.cb;
3852	if (pLastMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3853	break;
3854	pLastMmio = pLastMmio->pNextR3;
3855	}
3856
3857	Log(("PGMR3PhysMMIOExUnmap: %RGp-%RGp %s\n",
3858	pFirstMmio->RamRange.GCPhys, pLastMmio->RamRange.GCPhysLast, pFirstMmio->RamRange.pszDesc));
3859
3860	int rc = pgmLock(pVM);
3861	AssertRCReturn(rc, rc);
3862	uint16_t const fOldFlags = pFirstMmio->fFlags;
3863	AssertReturnStmt(fOldFlags & PGMREGMMIORANGE_F_MAPPED, pgmUnlock(pVM), VERR_WRONG_ORDER);
3864
3865	/*
3866	* If plain MMIO, we must deregister the handlers first.
3867	*/
3868	if (!(fOldFlags & PGMREGMMIORANGE_F_MMIO2))
3869	{
3870	PPGMREGMMIORANGE pCurMmio = pFirstMmio;
3871	rc = pgmHandlerPhysicalExDeregister(pVM, pFirstMmio->pPhysHandlerR3, RT_BOOL(fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING));
3872	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
3873	while (!(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK))
3874	{
3875	pCurMmio = pCurMmio->pNextR3;
3876	rc = pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3, RT_BOOL(fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING));
3877	AssertRCReturnStmt(rc, pgmUnlock(pVM), VERR_PGM_PHYS_MMIO_EX_IPE);
3878	}
3879
3880	IOMR3MmioExNotifyUnmapped(pVM, pFirstMmio->pPhysHandlerR3->pvUserR3, GCPhys);
3881	}
3882
3883	/*
3884	* Unmap it.
3885	*/
3886	RTGCPHYS const GCPhysRangeNotify = pFirstMmio->RamRange.GCPhys;
3887	if (fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING)
3888	{
3889	/*
3890	* We've replaced RAM, replace with zero pages.
3891	*
3892	* Note! This is where we might differ a little from a real system, because
3893	* it's likely to just show the RAM pages as they were before the
3894	* MMIO/MMIO2 region was mapped here.
3895	*/
3896	/* Only one chunk allowed when overlapping! */
3897	Assert(fOldFlags & PGMREGMMIORANGE_F_LAST_CHUNK);
3898
3899	/* Restore the RAM pages we've replaced. */
3900	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3901	while (pRam->GCPhys > pFirstMmio->RamRange.GCPhysLast)
3902	pRam = pRam->pNextR3;
3903
3904	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3905	if (fOldFlags & PGMREGMMIORANGE_F_MMIO2)
3906	pVM->pgm.s.cZeroPages += cPagesLeft;
3907
3908	PPGMPAGE pPageDst = &pRam->aPages[(pFirstMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3909	while (cPagesLeft-- > 0)
3910	{
3911	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3912	pPageDst++;
3913	}
3914
3915	/* Flush physical page map TLB. */
3916	pgmPhysInvalidatePageMapTLB(pVM);
3917
3918	/* Update range state. */
3919	pFirstMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3920	pFirstMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3921	pFirstMmio->fFlags &= ~(PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MAPPED);
3922	}
3923	else
3924	{
3925	/*
3926	* Unlink the chunks related to the MMIO/MMIO2 region.
3927	*/
3928	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3929	{
3930	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3931	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3932	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3933	pCurMmio->fFlags &= ~(PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MAPPED);
3934	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3935	break;
3936	}
3937	}
3938
3939	/* Force a PGM pool flush as guest ram references have been changed. */
3940	/** @todo not entirely SMP safe; assuming for now the guest takes care
3941	* of this internally (not touch mapped mmio while changing the
3942	* mapping). */
3943	PVMCPU pVCpu = VMMGetCpu(pVM);
3944	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3945	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3946
3947	pgmPhysInvalidatePageMapTLB(pVM);
3948	pgmPhysInvalidRamRangeTlbs(pVM);
3949
3950	/*
3951	* Notify NEM while holding the lock (experimental) and REM without (like always).
3952	*/
3953	uint32_t const fNemFlags = (fOldFlags & PGMREGMMIORANGE_F_MMIO2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0)
3954	\| (fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
3955	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhysRangeNotify, cbRange, fNemFlags);
3956	pgmUnlock(pVM);
3957	#ifdef VBOX_WITH_REM
3958	if ((fOldFlags & (PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MMIO2)) == PGMREGMMIORANGE_F_MMIO2)
3959	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeNotify, cbRange);
3960	#endif
3961	return rc;
3962	}
3963
3964
3965	/**
3966	* Reduces the mapping size of a MMIO2 or pre-registered MMIO region.
3967	*
3968	* This is mainly for dealing with old saved states after changing the default
3969	* size of a mapping region. See PGMDevHlpMMIOExReduce and
3970	* PDMPCIDEV::pfnRegionLoadChangeHookR3.
3971	*
3972	* The region must not currently be mapped when making this call. The VM state
3973	* must be state restore or VM construction.
3974	*
3975	* @returns VBox status code.
3976	* @param pVM The cross context VM structure.
3977	* @param pDevIns The device instance owning the region.
3978	* @param iSubDev The sub-device number of the registered region.
3979	* @param iRegion The index of the registered region.
3980	* @param cbRegion The new mapping size.
3981	*/
3982	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion)
3983	{
3984	/*
3985	* Validate input
3986	*/
3987	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3988	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3989	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3990	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3991	AssertReturn(cbRegion >= X86_PAGE_SIZE, VERR_INVALID_PARAMETER);
3992	AssertReturn(!(cbRegion & X86_PAGE_OFFSET_MASK), VERR_UNSUPPORTED_ALIGNMENT);
3993	VMSTATE enmVmState = VMR3GetState(pVM);
3994	AssertLogRelMsgReturn( enmVmState == VMSTATE_CREATING
3995	\|\| enmVmState == VMSTATE_LOADING,
3996	("enmVmState=%d (%s)\n", enmVmState, VMR3GetStateName(enmVmState)),
3997	VERR_VM_INVALID_VM_STATE);
3998
3999	int rc = pgmLock(pVM);
4000	AssertRCReturn(rc, rc);
4001
4002	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
4003	if (pFirstMmio)
4004	{
4005	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
4006	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED))
4007	{
4008	/*
4009	* NOTE! Current implementation does not support multiple ranges.
4010	* Implement when there is a real world need and thus a testcase.
4011	*/
4012	AssertLogRelMsgStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK,
4013	("%s: %#x\n", pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
4014	rc = VERR_NOT_SUPPORTED);
4015	if (RT_SUCCESS(rc))
4016	{
4017	/*
4018	* Make the change.
4019	*/
4020	Log(("PGMR3PhysMMIOExReduce: %s changes from %RGp bytes (%RGp) to %RGp bytes.\n",
4021	pFirstMmio->RamRange.pszDesc, pFirstMmio->RamRange.cb, pFirstMmio->cbReal, cbRegion));
4022
4023	AssertLogRelMsgStmt(cbRegion <= pFirstMmio->cbReal,
4024	("%s: cbRegion=%#RGp cbReal=%#RGp\n", pFirstMmio->RamRange.pszDesc, cbRegion, pFirstMmio->cbReal),
4025	rc = VERR_OUT_OF_RANGE);
4026	if (RT_SUCCESS(rc))
4027	{
4028	pFirstMmio->RamRange.cb = cbRegion;
4029	}
4030	}
4031	}
4032	else
4033	rc = VERR_WRONG_ORDER;
4034	}
4035	else
4036	rc = VERR_NOT_FOUND;
4037
4038	pgmUnlock(pVM);
4039	return rc;
4040	}
4041
4042
4043	/**
4044	* Checks if the given address is an MMIO2 or pre-registered MMIO base address
4045	* or not.
4046	*
4047	* @returns true/false accordingly.
4048	* @param pVM The cross context VM structure.
4049	* @param pDevIns The owner of the memory, optional.
4050	* @param GCPhys The address to check.
4051	*/
4052	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
4053	{
4054	/*
4055	* Validate input
4056	*/
4057	VM_ASSERT_EMT_RETURN(pVM, false);
4058	AssertPtrReturn(pDevIns, false);
4059	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
4060	AssertReturn(GCPhys != 0, false);
4061	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
4062
4063	/*
4064	* Search the list.
4065	*/
4066	pgmLock(pVM);
4067	for (PPGMREGMMIORANGE pCurMmio = pVM->pgm.s.pRegMmioRangesR3; pCurMmio; pCurMmio = pCurMmio->pNextR3)
4068	if (pCurMmio->RamRange.GCPhys == GCPhys)
4069	{
4070	Assert(pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED);
4071	bool fRet = RT_BOOL(pCurMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
4072	pgmUnlock(pVM);
4073	return fRet;
4074	}
4075	pgmUnlock(pVM);
4076	return false;
4077	}
4078
4079
4080	/**
4081	* Gets the HC physical address of a page in the MMIO2 region.
4082	*
4083	* This is API is intended for MMHyper and shouldn't be called
4084	* by anyone else...
4085	*
4086	* @returns VBox status code.
4087	* @param pVM The cross context VM structure.
4088	* @param pDevIns The owner of the memory, optional.
4089	* @param iSubDev Sub-device number.
4090	* @param iRegion The region.
4091	* @param off The page expressed an offset into the MMIO2 region.
4092	* @param pHCPhys Where to store the result.
4093	*/
4094	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
4095	RTGCPHYS off, PRTHCPHYS pHCPhys)
4096	{
4097	/*
4098	* Validate input
4099	*/
4100	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4101	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4102	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
4103	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4104
4105	pgmLock(pVM);
4106	PPGMREGMMIORANGE pCurMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
4107	AssertReturn(pCurMmio, VERR_NOT_FOUND);
4108	AssertReturn(pCurMmio->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK), VERR_WRONG_TYPE);
4109
4110	while ( off >= pCurMmio->RamRange.cb
4111	&& !(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK))
4112	{
4113	off -= pCurMmio->RamRange.cb;
4114	pCurMmio = pCurMmio->pNextR3;
4115	}
4116	AssertReturn(off < pCurMmio->RamRange.cb, VERR_INVALID_PARAMETER);
4117
4118	PCPGMPAGE pPage = &pCurMmio->RamRange.aPages[off >> PAGE_SHIFT];
4119	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4120	pgmUnlock(pVM);
4121	return VINF_SUCCESS;
4122	}
4123
4124
4125	/**
4126	* Maps a portion of an MMIO2 region into kernel space (host).
4127	*
4128	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
4129	* or the VM is terminated.
4130	*
4131	* @return VBox status code.
4132	*
4133	* @param pVM The cross context VM structure.
4134	* @param pDevIns The device owning the MMIO2 memory.
4135	* @param iSubDev The sub-device number.
4136	* @param iRegion The region.
4137	* @param off The offset into the region. Must be page aligned.
4138	* @param cb The number of bytes to map. Must be page aligned.
4139	* @param pszDesc Mapping description.
4140	* @param pR0Ptr Where to store the R0 address.
4141	*/
4142	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
4143	RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr)
4144	{
4145	/*
4146	* Validate input.
4147	*/
4148	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4149	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4150	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
4151	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4152
4153	PPGMREGMMIORANGE pFirstRegMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
4154	AssertReturn(pFirstRegMmio, VERR_NOT_FOUND);
4155	AssertReturn(pFirstRegMmio->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK), VERR_WRONG_TYPE);
4156	AssertReturn(off < pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
4157	AssertReturn(cb <= pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
4158	AssertReturn(off + cb <= pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
4159	NOREF(pszDesc);
4160
4161	/*
4162	* Pass the request on to the support library/driver.
4163	*/
4164	#if defined(RT_OS_WINDOWS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_OS2) /** @todo Fully implement RTR0MemObjMapKernelEx everywhere. */
4165	AssertLogRelReturn(off == 0, VERR_NOT_SUPPORTED);
4166	AssertLogRelReturn(pFirstRegMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK, VERR_NOT_SUPPORTED);
4167	int rc = SUPR3PageMapKernel(pFirstRegMmio->pvR3, 0 /off/, pFirstRegMmio->RamRange.cb, 0 /fFlags/, pR0Ptr);
4168	#else
4169	int rc = SUPR3PageMapKernel(pFirstRegMmio->pvR3, off, cb, 0 /fFlags/, pR0Ptr);
4170	#endif
4171
4172	return rc;
4173	}
4174
4175
4176	/**
4177	* Worker for PGMR3PhysRomRegister.
4178	*
4179	* This is here to simplify lock management, i.e. the caller does all the
4180	* locking and we can simply return without needing to remember to unlock
4181	* anything first.
4182	*
4183	* @returns VBox status code.
4184	* @param pVM The cross context VM structure.
4185	* @param pDevIns The device instance owning the ROM.
4186	* @param GCPhys First physical address in the range.
4187	* Must be page aligned!
4188	* @param cb The size of the range (in bytes).
4189	* Must be page aligned!
4190	* @param pvBinary Pointer to the binary data backing the ROM image.
4191	* @param cbBinary The size of the binary data pvBinary points to.
4192	* This must be less or equal to @a cb.
4193	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4194	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4195	* @param pszDesc Pointer to description string. This must not be freed.
4196	*/
4197	static int pgmR3PhysRomRegisterLocked(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4198	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
4199	{
4200	/*
4201	* Validate input.
4202	*/
4203	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4204	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
4205	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
4206	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4207	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4208	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
4209	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
4210	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
4211	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
4212
4213	const uint32_t cPages = cb >> PAGE_SHIFT;
4214
4215	/*
4216	* Find the ROM location in the ROM list first.
4217	*/
4218	PPGMROMRANGE pRomPrev = NULL;
4219	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
4220	while (pRom && GCPhysLast >= pRom->GCPhys)
4221	{
4222	if ( GCPhys <= pRom->GCPhysLast
4223	&& GCPhysLast >= pRom->GCPhys)
4224	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
4225	GCPhys, GCPhysLast, pszDesc,
4226	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
4227	VERR_PGM_RAM_CONFLICT);
4228	/* next */
4229	pRomPrev = pRom;
4230	pRom = pRom->pNextR3;
4231	}
4232
4233	/*
4234	* Find the RAM location and check for conflicts.
4235	*
4236	* Conflict detection is a bit different than for RAM
4237	* registration since a ROM can be located within a RAM
4238	* range. So, what we have to check for is other memory
4239	* types (other than RAM that is) and that we don't span
4240	* more than one RAM range (layz).
4241	*/
4242	bool fRamExists = false;
4243	PPGMRAMRANGE pRamPrev = NULL;
4244	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4245	while (pRam && GCPhysLast >= pRam->GCPhys)
4246	{
4247	if ( GCPhys <= pRam->GCPhysLast
4248	&& GCPhysLast >= pRam->GCPhys)
4249	{
4250	/* completely within? */
4251	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
4252	&& GCPhysLast <= pRam->GCPhysLast,
4253	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
4254	GCPhys, GCPhysLast, pszDesc,
4255	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
4256	VERR_PGM_RAM_CONFLICT);
4257	fRamExists = true;
4258	break;
4259	}
4260
4261	/* next */
4262	pRamPrev = pRam;
4263	pRam = pRam->pNextR3;
4264	}
4265	if (fRamExists)
4266	{
4267	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4268	uint32_t cPagesLeft = cPages;
4269	while (cPagesLeft-- > 0)
4270	{
4271	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
4272	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
4273	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
4274	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
4275	Assert(PGM_PAGE_IS_ZERO(pPage));
4276	pPage++;
4277	}
4278	}
4279
4280	/*
4281	* Update the base memory reservation if necessary.
4282	*/
4283	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
4284	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4285	cExtraBaseCost += cPages;
4286	if (cExtraBaseCost)
4287	{
4288	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
4289	if (RT_FAILURE(rc))
4290	return rc;
4291	}
4292
4293	/*
4294	* Allocate memory for the virgin copy of the RAM.
4295	*/
4296	PGMMALLOCATEPAGESREQ pReq;
4297	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
4298	AssertRCReturn(rc, rc);
4299
4300	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4301	{
4302	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
4303	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
4304	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
4305	}
4306
4307	rc = GMMR3AllocatePagesPerform(pVM, pReq);
4308	if (RT_FAILURE(rc))
4309	{
4310	GMMR3AllocatePagesCleanup(pReq);
4311	return rc;
4312	}
4313
4314	/*
4315	* Allocate the new ROM range and RAM range (if necessary).
4316	*/
4317	PPGMROMRANGE pRomNew;
4318	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
4319	if (RT_SUCCESS(rc))
4320	{
4321	PPGMRAMRANGE pRamNew = NULL;
4322	if (!fRamExists)
4323	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
4324	if (RT_SUCCESS(rc))
4325	{
4326	/*
4327	* Initialize and insert the RAM range (if required).
4328	*/
4329	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
4330	if (!fRamExists)
4331	{
4332	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
4333	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
4334	pRamNew->GCPhys = GCPhys;
4335	pRamNew->GCPhysLast = GCPhysLast;
4336	pRamNew->cb = cb;
4337	pRamNew->pszDesc = pszDesc;
4338	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
4339	pRamNew->pvR3 = NULL;
4340	pRamNew->paLSPages = NULL;
4341
4342	PPGMPAGE pPage = &pRamNew->aPages[0];
4343	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
4344	{
4345	PGM_PAGE_INIT(pPage,
4346	pReq->aPages[iPage].HCPhysGCPhys,
4347	pReq->aPages[iPage].idPage,
4348	PGMPAGETYPE_ROM,
4349	PGM_PAGE_STATE_ALLOCATED);
4350
4351	pRomPage->Virgin = *pPage;
4352	}
4353
4354	pVM->pgm.s.cAllPages += cPages;
4355	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
4356	}
4357	else
4358	{
4359	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4360	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
4361	{
4362	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_ROM);
4363	PGM_PAGE_SET_HCPHYS(pVM, pPage, pReq->aPages[iPage].HCPhysGCPhys);
4364	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
4365	PGM_PAGE_SET_PAGEID(pVM, pPage, pReq->aPages[iPage].idPage);
4366	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4367	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
4368	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
4369
4370	pRomPage->Virgin = *pPage;
4371	}
4372
4373	pRamNew = pRam;
4374
4375	pVM->pgm.s.cZeroPages -= cPages;
4376	}
4377	pVM->pgm.s.cPrivatePages += cPages;
4378
4379	/* Flush physical page map TLB. */
4380	pgmPhysInvalidatePageMapTLB(pVM);
4381
4382
4383	/* Notify NEM before we register handlers. */
4384	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_ROM_F_REPLACE : 0)
4385	\| (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED ? NEM_NOTIFY_PHYS_ROM_F_SHADOW : 0);
4386	rc = NEMR3NotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fNemNotify);
4387
4388	/*
4389	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
4390	*
4391	* If it's shadowed we'll register the handler after the ROM notification
4392	* so we get the access handler callbacks that we should. If it isn't
4393	* shadowed we'll do it the other way around to make REM use the built-in
4394	* ROM behavior and not the handler behavior (which is to route all access
4395	* to PGM atm).
4396	*/
4397	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4398	{
4399	#ifdef VBOX_WITH_REM
4400	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
4401	#endif
4402	if (RT_SUCCESS(rc))
4403	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4404	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
4405	pszDesc);
4406	}
4407	else
4408	{
4409	if (RT_SUCCESS(rc))
4410	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4411	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
4412	pszDesc);
4413	#ifdef VBOX_WITH_REM
4414	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
4415	#endif
4416	}
4417	if (RT_SUCCESS(rc))
4418	{
4419	/*
4420	* Copy the image over to the virgin pages.
4421	* This must be done after linking in the RAM range.
4422	*/
4423	size_t cbBinaryLeft = cbBinary;
4424	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
4425	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4426	{
4427	void *pvDstPage;
4428	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
4429	if (RT_FAILURE(rc))
4430	{
4431	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
4432	break;
4433	}
4434	if (cbBinaryLeft >= PAGE_SIZE)
4435	{
4436	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
4437	cbBinaryLeft -= PAGE_SIZE;
4438	}
4439	else
4440	{
4441	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
4442	if (cbBinaryLeft > 0)
4443	{
4444	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
4445	cbBinaryLeft = 0;
4446	}
4447	}
4448	}
4449	if (RT_SUCCESS(rc))
4450	{
4451	/*
4452	* Initialize the ROM range.
4453	* Note that the Virgin member of the pages has already been initialized above.
4454	*/
4455	pRomNew->GCPhys = GCPhys;
4456	pRomNew->GCPhysLast = GCPhysLast;
4457	pRomNew->cb = cb;
4458	pRomNew->fFlags = fFlags;
4459	pRomNew->idSavedState = UINT8_MAX;
4460	pRomNew->cbOriginal = cbBinary;
4461	pRomNew->pszDesc = pszDesc;
4462	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
4463	? pvBinary : RTMemDup(pvBinary, cbBinary);
4464	if (pRomNew->pvOriginal)
4465	{
4466	for (unsigned iPage = 0; iPage < cPages; iPage++)
4467	{
4468	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
4469	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
4470	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
4471	}
4472
4473	/* update the page count stats for the shadow pages. */
4474	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4475	{
4476	pVM->pgm.s.cZeroPages += cPages;
4477	pVM->pgm.s.cAllPages += cPages;
4478	}
4479
4480	/*
4481	* Insert the ROM range, tell REM and return successfully.
4482	*/
4483	pRomNew->pNextR3 = pRom;
4484	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4485	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
4486
4487	if (pRomPrev)
4488	{
4489	pRomPrev->pNextR3 = pRomNew;
4490	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
4491	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
4492	}
4493	else
4494	{
4495	pVM->pgm.s.pRomRangesR3 = pRomNew;
4496	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
4497	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
4498	}
4499
4500	pgmPhysInvalidatePageMapTLB(pVM);
4501	GMMR3AllocatePagesCleanup(pReq);
4502
4503	/* Notify NEM again. */
4504	return NEMR3NotifyPhysRomRegisterLate(pVM, GCPhys, cb, fNemNotify);
4505	}
4506
4507	/* bail out */
4508	rc = VERR_NO_MEMORY;
4509	}
4510
4511	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
4512	AssertRC(rc2);
4513	}
4514
4515	if (!fRamExists)
4516	{
4517	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
4518	MMHyperFree(pVM, pRamNew);
4519	}
4520	}
4521	MMHyperFree(pVM, pRomNew);
4522	}
4523
4524	/** @todo Purge the mapping cache or something... */
4525	GMMR3FreeAllocatedPages(pVM, pReq);
4526	GMMR3AllocatePagesCleanup(pReq);
4527	return rc;
4528	}
4529
4530
4531	/**
4532	* Registers a ROM image.
4533	*
4534	* Shadowed ROM images requires double the amount of backing memory, so,
4535	* don't use that unless you have to. Shadowing of ROM images is process
4536	* where we can select where the reads go and where the writes go. On real
4537	* hardware the chipset provides means to configure this. We provide
4538	* PGMR3PhysProtectROM() for this purpose.
4539	*
4540	* A read-only copy of the ROM image will always be kept around while we
4541	* will allocate RAM pages for the changes on demand (unless all memory
4542	* is configured to be preallocated).
4543	*
4544	* @returns VBox status code.
4545	* @param pVM The cross context VM structure.
4546	* @param pDevIns The device instance owning the ROM.
4547	* @param GCPhys First physical address in the range.
4548	* Must be page aligned!
4549	* @param cb The size of the range (in bytes).
4550	* Must be page aligned!
4551	* @param pvBinary Pointer to the binary data backing the ROM image.
4552	* @param cbBinary The size of the binary data pvBinary points to.
4553	* This must be less or equal to @a cb.
4554	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4555	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4556	* @param pszDesc Pointer to description string. This must not be freed.
4557	*
4558	* @remark There is no way to remove the rom, automatically on device cleanup or
4559	* manually from the device yet. This isn't difficult in any way, it's
4560	* just not something we expect to be necessary for a while.
4561	*/
4562	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4563	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
4564	{
4565	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
4566	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
4567	pgmLock(pVM);
4568	int rc = pgmR3PhysRomRegisterLocked(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
4569	pgmUnlock(pVM);
4570	return rc;
4571	}
4572
4573
4574	/**
4575	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
4576	* that the virgin part is untouched.
4577	*
4578	* This is done after the normal memory has been cleared.
4579	*
4580	* ASSUMES that the caller owns the PGM lock.
4581	*
4582	* @param pVM The cross context VM structure.
4583	*/
4584	int pgmR3PhysRomReset(PVM pVM)
4585	{
4586	PGM_LOCK_ASSERT_OWNER(pVM);
4587	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4588	{
4589	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
4590
4591	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4592	{
4593	/*
4594	* Reset the physical handler.
4595	*/
4596	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
4597	AssertRCReturn(rc, rc);
4598
4599	/*
4600	* What we do with the shadow pages depends on the memory
4601	* preallocation option. If not enabled, we'll just throw
4602	* out all the dirty pages and replace them by the zero page.
4603	*/
4604	if (!pVM->pgm.s.fRamPreAlloc)
4605	{
4606	/* Free the dirty pages. */
4607	uint32_t cPendingPages = 0;
4608	PGMMFREEPAGESREQ pReq;
4609	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4610	AssertRCReturn(rc, rc);
4611
4612	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4613	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
4614	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
4615	{
4616	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
4617	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
4618	pRom->GCPhys + (iPage << PAGE_SHIFT),
4619	(PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pRom->aPages[iPage].Shadow));
4620	AssertLogRelRCReturn(rc, rc);
4621	}
4622
4623	if (cPendingPages)
4624	{
4625	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
4626	AssertLogRelRCReturn(rc, rc);
4627	}
4628	GMMR3FreePagesCleanup(pReq);
4629	}
4630	else
4631	{
4632	/* clear all the shadow pages. */
4633	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4634	{
4635	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
4636	continue;
4637	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
4638	void *pvDstPage;
4639	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4640	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
4641	if (RT_FAILURE(rc))
4642	break;
4643	ASMMemZeroPage(pvDstPage);
4644	}
4645	AssertRCReturn(rc, rc);
4646	}
4647	}
4648
4649	/*
4650	* Restore the original ROM pages after a saved state load.
4651	* Also, in strict builds check that ROM pages remain unmodified.
4652	*/
4653	#ifndef VBOX_STRICT
4654	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4655	#endif
4656	{
4657	size_t cbSrcLeft = pRom->cbOriginal;
4658	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
4659	uint32_t cRestored = 0;
4660	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
4661	{
4662	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4663	void const *pvDstPage;
4664	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
4665	if (RT_FAILURE(rc))
4666	break;
4667
4668	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
4669	{
4670	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4671	{
4672	void *pvDstPageW;
4673	rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPageW);
4674	AssertLogRelRCReturn(rc, rc);
4675	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
4676	cRestored++;
4677	}
4678	else
4679	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
4680	}
4681	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
4682	}
4683	if (cRestored > 0)
4684	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
4685	}
4686	}
4687
4688	/* Clear the ROM restore flag now as we only need to do this once after
4689	loading saved state. */
4690	pVM->pgm.s.fRestoreRomPagesOnReset = false;
4691
4692	return VINF_SUCCESS;
4693	}
4694
4695
4696	/**
4697	* Called by PGMR3Term to free resources.
4698	*
4699	* ASSUMES that the caller owns the PGM lock.
4700	*
4701	* @param pVM The cross context VM structure.
4702	*/
4703	void pgmR3PhysRomTerm(PVM pVM)
4704	{
4705	/*
4706	* Free the heap copy of the original bits.
4707	*/
4708	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4709	{
4710	if ( pRom->pvOriginal
4711	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
4712	{
4713	RTMemFree((void *)pRom->pvOriginal);
4714	pRom->pvOriginal = NULL;
4715	}
4716	}
4717	}
4718
4719
4720	/**
4721	* Change the shadowing of a range of ROM pages.
4722	*
4723	* This is intended for implementing chipset specific memory registers
4724	* and will not be very strict about the input. It will silently ignore
4725	* any pages that are not the part of a shadowed ROM.
4726	*
4727	* @returns VBox status code.
4728	* @retval VINF_PGM_SYNC_CR3
4729	*
4730	* @param pVM The cross context VM structure.
4731	* @param GCPhys Where to start. Page aligned.
4732	* @param cb How much to change. Page aligned.
4733	* @param enmProt The new ROM protection.
4734	*/
4735	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
4736	{
4737	/*
4738	* Check input
4739	*/
4740	if (!cb)
4741	return VINF_SUCCESS;
4742	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4743	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4744	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4745	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4746	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
4747
4748	/*
4749	* Process the request.
4750	*/
4751	pgmLock(pVM);
4752	int rc = VINF_SUCCESS;
4753	bool fFlushTLB = false;
4754	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4755	{
4756	if ( GCPhys <= pRom->GCPhysLast
4757	&& GCPhysLast >= pRom->GCPhys
4758	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
4759	{
4760	/*
4761	* Iterate the relevant pages and make necessary the changes.
4762	*/
4763	bool fChanges = false;
4764	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
4765	? pRom->cb >> PAGE_SHIFT
4766	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
4767	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
4768	iPage < cPages;
4769	iPage++)
4770	{
4771	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
4772	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
4773	{
4774	fChanges = true;
4775
4776	/* flush references to the page. */
4777	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT));
4778	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage,
4779	true /fFlushPTEs/, &fFlushTLB);
4780	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
4781	rc = rc2;
4782	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pRamPage);
4783
4784	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
4785	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
4786
4787	pOld = pRamPage;
4788	pRamPage = pNew;
4789	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
4790
4791	/* Tell NEM about the backing and protection change. */
4792	if (VM_IS_NEM_ENABLED(pVM))
4793	{
4794	PGMPAGETYPE enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pNew);
4795	NEMHCNotifyPhysPageChanged(pVM, GCPhys, PGM_PAGE_GET_HCPHYS(pOld), PGM_PAGE_GET_HCPHYS(pNew),
4796	pgmPhysPageCalcNemProtection(pRamPage, enmType), enmType, &u2State);
4797	PGM_PAGE_SET_NEM_STATE(pRamPage, u2State);
4798	}
4799	}
4800	pRomPage->enmProt = enmProt;
4801	}
4802
4803	/*
4804	* Reset the access handler if we made changes, no need
4805	* to optimize this.
4806	*/
4807	if (fChanges)
4808	{
4809	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
4810	if (RT_FAILURE(rc2))
4811	{
4812	pgmUnlock(pVM);
4813	AssertRC(rc);
4814	return rc2;
4815	}
4816	}
4817
4818	/* Advance - cb isn't updated. */
4819	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
4820	}
4821	}
4822	pgmUnlock(pVM);
4823	if (fFlushTLB)
4824	PGM_INVL_ALL_VCPU_TLBS(pVM);
4825
4826	return rc;
4827	}
4828
4829
4830	/**
4831	* Sets the Address Gate 20 state.
4832	*
4833	* @param pVCpu The cross context virtual CPU structure.
4834	* @param fEnable True if the gate should be enabled.
4835	* False if the gate should be disabled.
4836	*/
4837	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
4838	{
4839	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
4840	if (pVCpu->pgm.s.fA20Enabled != fEnable)
4841	{
4842	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4843	PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
4844	if ( CPUMIsGuestInVmxRootMode(pCtx)
4845	&& !fEnable)
4846	{
4847	Log(("Cannot enter A20M mode while in VMX root mode\n"));
4848	return;
4849	}
4850	#endif
4851	pVCpu->pgm.s.fA20Enabled = fEnable;
4852	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
4853	#ifdef VBOX_WITH_REM
4854	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
4855	#endif
4856	NEMR3NotifySetA20(pVCpu, fEnable);
4857	#ifdef PGM_WITH_A20
4858	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
4859	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4860	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
4861	HMFlushTlb(pVCpu);
4862	#endif
4863	IEMTlbInvalidateAllPhysical(pVCpu);
4864	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
4865	}
4866	}
4867
4868
4869	/**
4870	* Tree enumeration callback for dealing with age rollover.
4871	* It will perform a simple compression of the current age.
4872	*/
4873	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
4874	{
4875	/* Age compression - ASSUMES iNow == 4. */
4876	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4877	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
4878	pChunk->iLastUsed = 3;
4879	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
4880	pChunk->iLastUsed = 2;
4881	else if (pChunk->iLastUsed)
4882	pChunk->iLastUsed = 1;
4883	else /* iLastUsed = 0 */
4884	pChunk->iLastUsed = 4;
4885
4886	NOREF(pvUser);
4887	return 0;
4888	}
4889
4890
4891	/**
4892	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
4893	*/
4894	typedef struct PGMR3PHYSCHUNKUNMAPCB
4895	{
4896	PVM pVM; /*< Pointer to the VM. /
4897	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
4898	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
4899
4900
4901	/**
4902	* Callback used to find the mapping that's been unused for
4903	* the longest time.
4904	*/
4905	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
4906	{
4907	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4908	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
4909
4910	/*
4911	* Check for locks and compare when last used.
4912	*/
4913	if (pChunk->cRefs)
4914	return 0;
4915	if (pChunk->cPermRefs)
4916	return 0;
4917	if ( pArg->pChunk
4918	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
4919	return 0;
4920
4921	/*
4922	* Check that it's not in any of the TLBs.
4923	*/
4924	PVM pVM = pArg->pVM;
4925	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
4926	== pChunk->Core.Key)
4927	{
4928	pChunk = NULL;
4929	return 0;
4930	}
4931	#ifdef VBOX_STRICT
4932	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
4933	{
4934	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
4935	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
4936	}
4937	#endif
4938
4939	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
4940	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
4941	return 0;
4942
4943	pArg->pChunk = pChunk;
4944	return 0;
4945	}
4946
4947
4948	/**
4949	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
4950	*
4951	* The candidate will not be part of any TLBs, so no need to flush
4952	* anything afterwards.
4953	*
4954	* @returns Chunk id.
4955	* @param pVM The cross context VM structure.
4956	*/
4957	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
4958	{
4959	PGM_LOCK_ASSERT_OWNER(pVM);
4960
4961	/*
4962	* Enumerate the age tree starting with the left most node.
4963	*/
4964	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4965	PGMR3PHYSCHUNKUNMAPCB Args;
4966	Args.pVM = pVM;
4967	Args.pChunk = NULL;
4968	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
4969	Assert(Args.pChunk);
4970	if (Args.pChunk)
4971	{
4972	Assert(Args.pChunk->cRefs == 0);
4973	Assert(Args.pChunk->cPermRefs == 0);
4974	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4975	return Args.pChunk->Core.Key;
4976	}
4977
4978	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4979	return INT32_MAX;
4980	}
4981
4982
4983	/**
4984	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
4985	*
4986	* This is only called on one of the EMTs while the other ones are waiting for
4987	* it to complete this function.
4988	*
4989	* @returns VINF_SUCCESS (VBox strict status code).
4990	* @param pVM The cross context VM structure.
4991	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
4992	* @param pvUser User pointer. Unused
4993	*
4994	*/
4995	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
4996	{
4997	int rc = VINF_SUCCESS;
4998	pgmLock(pVM);
4999	NOREF(pVCpu); NOREF(pvUser);
5000
5001	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
5002	{
5003	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
5004	/** @todo also not really efficient to unmap a chunk that contains PD
5005	* or PT pages. */
5006	pgmR3PoolClearAllRendezvous(pVM, &pVM->aCpus[0], NULL /* no need to flush the REM TLB as we already did that above */);
5007
5008	/*
5009	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
5010	*/
5011	GMMMAPUNMAPCHUNKREQ Req;
5012	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5013	Req.Hdr.cbReq = sizeof(Req);
5014	Req.pvR3 = NULL;
5015	Req.idChunkMap = NIL_GMM_CHUNKID;
5016	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
5017	if (Req.idChunkUnmap != INT32_MAX)
5018	{
5019	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
5020	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5021	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
5022	if (RT_SUCCESS(rc))
5023	{
5024	/*
5025	* Remove the unmapped one.
5026	*/
5027	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
5028	AssertRelease(pUnmappedChunk);
5029	AssertRelease(!pUnmappedChunk->cRefs);
5030	AssertRelease(!pUnmappedChunk->cPermRefs);
5031	pUnmappedChunk->pv = NULL;
5032	pUnmappedChunk->Core.Key = UINT32_MAX;
5033	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
5034	MMR3HeapFree(pUnmappedChunk);
5035	#else
5036	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
5037	#endif
5038	pVM->pgm.s.ChunkR3Map.c--;
5039	pVM->pgm.s.cUnmappedChunks++;
5040
5041	/*
5042	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
5043	*/
5044	/** @todo We should not flush chunks which include cr3 mappings. */
5045	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5046	{
5047	PPGMCPU pPGM = &pVM->aCpus[idCpu].pgm.s;
5048
5049	pPGM->pGst32BitPdR3 = NULL;
5050	pPGM->pGstPaePdptR3 = NULL;
5051	pPGM->pGstAmd64Pml4R3 = NULL;
5052	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
5053	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
5054	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
5055	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
5056	#endif
5057	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
5058	{
5059	pPGM->apGstPaePDsR3[i] = NULL;
5060	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
5061	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
5062	#endif
5063	}
5064
5065	/* Flush REM TLBs. */
5066	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5067	}
5068	#ifdef VBOX_WITH_REM
5069	/* Flush REM translation blocks. */
5070	REMFlushTBs(pVM);
5071	#endif
5072	}
5073	}
5074	}
5075	pgmUnlock(pVM);
5076	return rc;
5077	}
5078
5079	/**
5080	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
5081	*
5082	* @returns VBox status code.
5083	* @param pVM The cross context VM structure.
5084	*/
5085	void pgmR3PhysUnmapChunk(PVM pVM)
5086	{
5087	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
5088	AssertRC(rc);
5089	}
5090
5091
5092	/**
5093	* Maps the given chunk into the ring-3 mapping cache.
5094	*
5095	* This will call ring-0.
5096	*
5097	* @returns VBox status code.
5098	* @param pVM The cross context VM structure.
5099	* @param idChunk The chunk in question.
5100	* @param ppChunk Where to store the chunk tracking structure.
5101	*
5102	* @remarks Called from within the PGM critical section.
5103	* @remarks Can be called from any thread!
5104	*/
5105	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
5106	{
5107	int rc;
5108
5109	PGM_LOCK_ASSERT_OWNER(pVM);
5110
5111	/*
5112	* Move the chunk time forward.
5113	*/
5114	pVM->pgm.s.ChunkR3Map.iNow++;
5115	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
5116	{
5117	pVM->pgm.s.ChunkR3Map.iNow = 4;
5118	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
5119	}
5120
5121	/*
5122	* Allocate a new tracking structure first.
5123	*/
5124	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
5125	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
5126	#else
5127	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
5128	#endif
5129	AssertReturn(pChunk, VERR_NO_MEMORY);
5130	pChunk->Core.Key = idChunk;
5131	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
5132
5133	/*
5134	* Request the ring-0 part to map the chunk in question.
5135	*/
5136	GMMMAPUNMAPCHUNKREQ Req;
5137	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5138	Req.Hdr.cbReq = sizeof(Req);
5139	Req.pvR3 = NULL;
5140	Req.idChunkMap = idChunk;
5141	Req.idChunkUnmap = NIL_GMM_CHUNKID;
5142
5143	/* Must be callable from any thread, so can't use VMMR3CallR0. */
5144	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
5145	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5146	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
5147	if (RT_SUCCESS(rc))
5148	{
5149	pChunk->pv = Req.pvR3;
5150
5151	/*
5152	* If we're running out of virtual address space, then we should
5153	* unmap another chunk.
5154	*
5155	* Currently, an unmap operation requires that all other virtual CPUs
5156	* are idling and not by chance making use of the memory we're
5157	* unmapping. So, we create an async unmap operation here.
5158	*
5159	* Now, when creating or restoring a saved state this wont work very
5160	* well since we may want to restore all guest RAM + a little something.
5161	* So, we have to do the unmap synchronously. Fortunately for us
5162	* though, during these operations the other virtual CPUs are inactive
5163	* and it should be safe to do this.
5164	*/
5165	/** @todo Eventually we should lock all memory when used and do
5166	* map+unmap as one kernel call without any rendezvous or
5167	* other precautions. */
5168	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
5169	{
5170	switch (VMR3GetState(pVM))
5171	{
5172	case VMSTATE_LOADING:
5173	case VMSTATE_SAVING:
5174	{
5175	PVMCPU pVCpu = VMMGetCpu(pVM);
5176	if ( pVCpu
5177	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
5178	{
5179	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
5180	break;
5181	}
5182	}
5183	RT_FALL_THRU();
5184	default:
5185	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
5186	AssertRC(rc);
5187	break;
5188	}
5189	}
5190
5191	/*
5192	* Update the tree. We must do this after any unmapping to make sure
5193	* the chunk we're going to return isn't unmapped by accident.
5194	*/
5195	AssertPtr(Req.pvR3);
5196	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
5197	AssertRelease(fRc);
5198	pVM->pgm.s.ChunkR3Map.c++;
5199	pVM->pgm.s.cMappedChunks++;
5200	}
5201	else
5202	{
5203	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
5204	* should probably restrict ourselves on linux. */
5205	AssertRC(rc);
5206	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
5207	MMR3HeapFree(pChunk);
5208	#else
5209	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
5210	#endif
5211	pChunk = NULL;
5212	}
5213
5214	*ppChunk = pChunk;
5215	return rc;
5216	}
5217
5218
5219	/**
5220	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
5221	*
5222	* @returns see pgmR3PhysChunkMap.
5223	* @param pVM The cross context VM structure.
5224	* @param idChunk The chunk to map.
5225	*/
5226	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
5227	{
5228	PPGMCHUNKR3MAP pChunk;
5229	int rc;
5230
5231	pgmLock(pVM);
5232	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
5233	pgmUnlock(pVM);
5234	return rc;
5235	}
5236
5237
5238	/**
5239	* Invalidates the TLB for the ring-3 mapping cache.
5240	*
5241	* @param pVM The cross context VM structure.
5242	*/
5243	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
5244	{
5245	pgmLock(pVM);
5246	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5247	{
5248	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
5249	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
5250	}
5251	/* The page map TLB references chunks, so invalidate that one too. */
5252	pgmPhysInvalidatePageMapTLB(pVM);
5253	pgmUnlock(pVM);
5254	}
5255
5256
5257	/**
5258	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE to allocate a large
5259	* (2MB) page for use with a nested paging PDE.
5260	*
5261	* @returns The following VBox status codes.
5262	* @retval VINF_SUCCESS on success.
5263	* @retval VINF_EM_NO_MEMORY if we're out of memory.
5264	*
5265	* @param pVM The cross context VM structure.
5266	* @param GCPhys GC physical start address of the 2 MB range
5267	*/
5268	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
5269	{
5270	#ifdef PGM_WITH_LARGE_PAGES
5271	uint64_t u64TimeStamp1, u64TimeStamp2;
5272
5273	pgmLock(pVM);
5274
5275	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
5276	u64TimeStamp1 = RTTimeMilliTS();
5277	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
5278	u64TimeStamp2 = RTTimeMilliTS();
5279	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
5280	if (RT_SUCCESS(rc))
5281	{
5282	Assert(pVM->pgm.s.cLargeHandyPages == 1);
5283
5284	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
5285	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
5286
5287	void *pv;
5288
5289	/* Map the large page into our address space.
5290	*
5291	* Note: assuming that within the 2 MB range:
5292	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
5293	* - user space mapping is continuous as well
5294	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
5295	*/
5296	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
5297	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", idPage, HCPhys, rc));
5298
5299	if (RT_SUCCESS(rc))
5300	{
5301	/*
5302	* Clear the pages.
5303	*/
5304	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
5305	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
5306	{
5307	ASMMemZeroPage(pv);
5308
5309	PPGMPAGE pPage;
5310	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
5311	AssertRC(rc);
5312
5313	Assert(PGM_PAGE_IS_ZERO(pPage));
5314	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRZPageReplaceZero);
5315	pVM->pgm.s.cZeroPages--;
5316
5317	/*
5318	* Do the PGMPAGE modifications.
5319	*/
5320	pVM->pgm.s.cPrivatePages++;
5321	PGM_PAGE_SET_HCPHYS(pVM, pPage, HCPhys);
5322	PGM_PAGE_SET_PAGEID(pVM, pPage, idPage);
5323	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
5324	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE);
5325	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5326	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5327
5328	/* Somewhat dirty assumption that page ids are increasing. */
5329	idPage++;
5330
5331	HCPhys += PAGE_SIZE;
5332	GCPhys += PAGE_SIZE;
5333
5334	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
5335
5336	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
5337	}
5338	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
5339
5340	/* Flush all TLBs. */
5341	PGM_INVL_ALL_VCPU_TLBS(pVM);
5342	pgmPhysInvalidatePageMapTLB(pVM);
5343	}
5344	pVM->pgm.s.cLargeHandyPages = 0;
5345	}
5346
5347	if (RT_SUCCESS(rc))
5348	{
5349	static uint32_t cTimeOut = 0;
5350	uint64_t u64TimeStampDelta = u64TimeStamp2 - u64TimeStamp1;
5351
5352	if (u64TimeStampDelta > 100)
5353	{
5354	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatLargePageOverflow);
5355	if ( ++cTimeOut > 10
5356	\|\| u64TimeStampDelta > 1000 /* more than one second forces an early retirement from allocating large pages. */)
5357	{
5358	/* If repeated attempts to allocate a large page takes more than 100 ms, then we fall back to normal 4k pages.
5359	* E.g. Vista 64 tries to move memory around, which takes a huge amount of time.
5360	*/
5361	LogRel(("PGMR3PhysAllocateLargePage: allocating large pages takes too long (last attempt %d ms; nr of timeouts %d); DISABLE\n", u64TimeStampDelta, cTimeOut));
5362	PGMSetLargePageUsage(pVM, false);
5363	}
5364	}
5365	else
5366	if (cTimeOut > 0)
5367	cTimeOut--;
5368	}
5369
5370	pgmUnlock(pVM);
5371	return rc;
5372	#else
5373	RT_NOREF(pVM, GCPhys);
5374	return VERR_NOT_IMPLEMENTED;
5375	#endif /* PGM_WITH_LARGE_PAGES */
5376	}
5377
5378
5379	/**
5380	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
5381	*
5382	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
5383	* signal and clear the out of memory condition. When contracted, this API is
5384	* used to try clear the condition when the user wants to resume.
5385	*
5386	* @returns The following VBox status codes.
5387	* @retval VINF_SUCCESS on success. FFs cleared.
5388	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
5389	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
5390	*
5391	* @param pVM The cross context VM structure.
5392	*
5393	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
5394	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
5395	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
5396	* handler.
5397	*/
5398	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
5399	{
5400	pgmLock(pVM);
5401
5402	/*
5403	* Allocate more pages, noting down the index of the first new page.
5404	*/
5405	uint32_t iClear = pVM->pgm.s.cHandyPages;
5406	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
5407	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
5408	int rcAlloc = VINF_SUCCESS;
5409	int rcSeed = VINF_SUCCESS;
5410	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5411	while (rc == VERR_GMM_SEED_ME)
5412	{
5413	void *pvChunk;
5414	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
5415	if (RT_SUCCESS(rc))
5416	{
5417	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
5418	if (RT_FAILURE(rc))
5419	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
5420	}
5421	if (RT_SUCCESS(rc))
5422	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5423	}
5424
5425	/** @todo we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
5426	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
5427	&& pVM->pgm.s.cHandyPages > 0)
5428	{
5429	/* Still handy pages left, so don't panic. */
5430	rc = VINF_SUCCESS;
5431	}
5432
5433	if (RT_SUCCESS(rc))
5434	{
5435	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
5436	Assert(pVM->pgm.s.cHandyPages > 0);
5437	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5438	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
5439
5440	#ifdef VBOX_STRICT
5441	uint32_t i;
5442	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
5443	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
5444	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
5445	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
5446	break;
5447	if (i != pVM->pgm.s.cHandyPages)
5448	{
5449	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
5450	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
5451	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
5452	RTAssertMsg2Add("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%\n", j,
5453	pVM->pgm.s.aHandyPages[j].idPage,
5454	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
5455	pVM->pgm.s.aHandyPages[j].idSharedPage,
5456	j == i ? " <---" : "");
5457	RTAssertPanic();
5458	}
5459	#endif
5460	/*
5461	* Clear the pages.
5462	*/
5463	while (iClear < pVM->pgm.s.cHandyPages)
5464	{
5465	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
5466	void *pv;
5467	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
5468	AssertLogRelMsgBreak(RT_SUCCESS(rc),
5469	("%u/%u: idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n",
5470	iClear, pVM->pgm.s.cHandyPages, pPage->idPage, pPage->HCPhysGCPhys, rc));
5471	ASMMemZeroPage(pv);
5472	iClear++;
5473	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
5474	}
5475	}
5476	else
5477	{
5478	uint64_t cAllocPages, cMaxPages, cBalloonPages;
5479
5480	/*
5481	* We should never get here unless there is a genuine shortage of
5482	* memory (or some internal error). Flag the error so the VM can be
5483	* suspended ASAP and the user informed. If we're totally out of
5484	* handy pages we will return failure.
5485	*/
5486	/* Report the failure. */
5487	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
5488	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
5489	rc, rcAlloc, rcSeed,
5490	pVM->pgm.s.cHandyPages,
5491	pVM->pgm.s.cAllPages,
5492	pVM->pgm.s.cPrivatePages,
5493	pVM->pgm.s.cSharedPages,
5494	pVM->pgm.s.cZeroPages));
5495
5496	if (GMMR3QueryMemoryStats(pVM, &cAllocPages, &cMaxPages, &cBalloonPages) == VINF_SUCCESS)
5497	{
5498	LogRel(("GMM: Statistics:\n"
5499	" Allocated pages: %RX64\n"
5500	" Maximum pages: %RX64\n"
5501	" Ballooned pages: %RX64\n", cAllocPages, cMaxPages, cBalloonPages));
5502	}
5503
5504	if ( rc != VERR_NO_MEMORY
5505	&& rc != VERR_NO_PHYS_MEMORY
5506	&& rc != VERR_LOCK_FAILED)
5507	{
5508	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5509	{
5510	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
5511	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
5512	pVM->pgm.s.aHandyPages[i].idSharedPage));
5513	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
5514	if (idPage != NIL_GMM_PAGEID)
5515	{
5516	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
5517	pRam;
5518	pRam = pRam->pNextR3)
5519	{
5520	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
5521	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5522	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
5523	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
5524	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
5525	}
5526	}
5527	}
5528	}
5529
5530	if (rc == VERR_NO_MEMORY)
5531	{
5532	uint64_t cbHostRamAvail = 0;
5533	int rc2 = RTSystemQueryAvailableRam(&cbHostRamAvail);
5534	if (RT_SUCCESS(rc2))
5535	LogRel(("Host RAM: %RU64MB available\n", cbHostRamAvail / _1M));
5536	else
5537	LogRel(("Cannot determine the amount of available host memory\n"));
5538	}
5539
5540	/* Set the FFs and adjust rc. */
5541	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5542	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
5543	if ( rc == VERR_NO_MEMORY
5544	\|\| rc == VERR_NO_PHYS_MEMORY
5545	\|\| rc == VERR_LOCK_FAILED)
5546	rc = VINF_EM_NO_MEMORY;
5547	}
5548
5549	pgmUnlock(pVM);
5550	return rc;
5551	}
5552
5553
5554	/**
5555	* Frees the specified RAM page and replaces it with the ZERO page.
5556	*
5557	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
5558	*
5559	* @param pVM The cross context VM structure.
5560	* @param pReq Pointer to the request.
5561	* @param pcPendingPages Where the number of pages waiting to be freed are
5562	* kept. This will normally be incremented.
5563	* @param pPage Pointer to the page structure.
5564	* @param GCPhys The guest physical address of the page, if applicable.
5565	* @param enmNewType New page type for NEM notification, since several
5566	* callers will change the type upon successful return.
5567	*
5568	* @remarks The caller must own the PGM lock.
5569	*/
5570	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
5571	PGMPAGETYPE enmNewType)
5572	{
5573	/*
5574	* Assert sanity.
5575	*/
5576	PGM_LOCK_ASSERT_OWNER(pVM);
5577	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
5578	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
5579	{
5580	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5581	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
5582	}
5583
5584	/** @todo What about ballooning of large pages??! */
5585	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
5586	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
5587
5588	if ( PGM_PAGE_IS_ZERO(pPage)
5589	\|\| PGM_PAGE_IS_BALLOONED(pPage))
5590	return VINF_SUCCESS;
5591
5592	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
5593	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
5594	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
5595	\|\| idPage > GMM_PAGEID_LAST
5596	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
5597	{
5598	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5599	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
5600	}
5601	const RTHCPHYS HCPhysPrev = PGM_PAGE_GET_HCPHYS(pPage);
5602
5603	/* update page count stats. */
5604	if (PGM_PAGE_IS_SHARED(pPage))
5605	pVM->pgm.s.cSharedPages--;
5606	else
5607	pVM->pgm.s.cPrivatePages--;
5608	pVM->pgm.s.cZeroPages++;
5609
5610	/* Deal with write monitored pages. */
5611	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
5612	{
5613	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
5614	pVM->pgm.s.cWrittenToPages++;
5615	}
5616
5617	/*
5618	* pPage = ZERO page.
5619	*/
5620	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
5621	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
5622	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
5623	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
5624	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5625	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5626
5627	/* Flush physical page map TLB entry. */
5628	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
5629
5630	/* Notify NEM. */
5631	/** @todo consider doing batch NEM notifications. */
5632	if (VM_IS_NEM_ENABLED(pVM))
5633	{
5634	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pPage);
5635	NEMHCNotifyPhysPageChanged(pVM, GCPhys, HCPhysPrev, pVM->pgm.s.HCPhysZeroPg,
5636	pgmPhysPageCalcNemProtection(pPage, enmNewType), enmNewType, &u2State);
5637	PGM_PAGE_SET_NEM_STATE(pPage, u2State);
5638	}
5639
5640	/*
5641	* Make sure it's not in the handy page array.
5642	*/
5643	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5644	{
5645	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
5646	{
5647	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
5648	break;
5649	}
5650	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
5651	{
5652	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
5653	break;
5654	}
5655	}
5656
5657	/*
5658	* Push it onto the page array.
5659	*/
5660	uint32_t iPage = *pcPendingPages;
5661	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
5662	*pcPendingPages += 1;
5663
5664	pReq->aPages[iPage].idPage = idPage;
5665
5666	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
5667	return VINF_SUCCESS;
5668
5669	/*
5670	* Flush the pages.
5671	*/
5672	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
5673	if (RT_SUCCESS(rc))
5674	{
5675	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
5676	*pcPendingPages = 0;
5677	}
5678	return rc;
5679	}
5680
5681
5682	/**
5683	* Converts a GC physical address to a HC ring-3 pointer, with some
5684	* additional checks.
5685	*
5686	* @returns VBox status code.
5687	* @retval VINF_SUCCESS on success.
5688	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
5689	* access handler of some kind.
5690	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
5691	* accesses or is odd in any way.
5692	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
5693	*
5694	* @param pVM The cross context VM structure.
5695	* @param GCPhys The GC physical address to convert. Since this is only
5696	* used for filling the REM TLB, the A20 mask must be
5697	* applied before calling this API.
5698	* @param fWritable Whether write access is required.
5699	* @param ppv Where to store the pointer corresponding to GCPhys on
5700	* success.
5701	*/
5702	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
5703	{
5704	pgmLock(pVM);
5705	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
5706
5707	PPGMRAMRANGE pRam;
5708	PPGMPAGE pPage;
5709	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
5710	if (RT_SUCCESS(rc))
5711	{
5712	if (PGM_PAGE_IS_BALLOONED(pPage))
5713	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5714	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
5715	rc = VINF_SUCCESS;
5716	else
5717	{
5718	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
5719	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5720	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
5721	{
5722	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
5723	* in -norawr0 mode. */
5724	if (fWritable)
5725	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5726	}
5727	else
5728	{
5729	/* Temporarily disabled physical handler(s), since the recompiler
5730	doesn't get notified when it's reset we'll have to pretend it's
5731	operating normally. */
5732	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
5733	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5734	else
5735	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5736	}
5737	}
5738	if (RT_SUCCESS(rc))
5739	{
5740	int rc2;
5741
5742	/* Make sure what we return is writable. */
5743	if (fWritable)
5744	switch (PGM_PAGE_GET_STATE(pPage))
5745	{
5746	case PGM_PAGE_STATE_ALLOCATED:
5747	break;
5748	case PGM_PAGE_STATE_BALLOONED:
5749	AssertFailed();
5750	break;
5751	case PGM_PAGE_STATE_ZERO:
5752	case PGM_PAGE_STATE_SHARED:
5753	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
5754	break;
5755	RT_FALL_THRU();
5756	case PGM_PAGE_STATE_WRITE_MONITORED:
5757	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
5758	AssertLogRelRCReturn(rc2, rc2);
5759	break;
5760	}
5761
5762	/* Get a ring-3 mapping of the address. */
5763	PPGMPAGER3MAPTLBE pTlbe;
5764	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
5765	AssertLogRelRCReturn(rc2, rc2);
5766	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
5767	/** @todo mapping/locking hell; this isn't horribly efficient since
5768	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
5769
5770	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
5771	}
5772	else
5773	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
5774
5775	/* else: handler catching all access, no pointer returned. */
5776	}
5777	else
5778	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
5779
5780	pgmUnlock(pVM);
5781	return rc;
5782	}
5783

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 77241

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