PGMPhys.cpp@ 80386

Last change on this file since 80386 was 80333, checked in by vboxsync, 5 years ago
VMM: Eliminating the VBOX_BUGREF_9217_PART_I preprocessor macro. bugref:9217
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1	/* $Id: PGMPhys.cpp 80333 2019-08-16 20:28:38Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/iem.h>
25	#include <VBox/vmm/iom.h>
26	#include <VBox/vmm/mm.h>
27	#include <VBox/vmm/nem.h>
28	#include <VBox/vmm/stam.h>
29	#ifdef VBOX_WITH_REM
30	# include <VBox/vmm/rem.h>
31	#endif
32	#include <VBox/vmm/pdmdev.h>
33	#include "PGMInternal.h"
34	#include <VBox/vmm/vmcc.h>
35
36	#include "PGMInline.h"
37
38	#include <VBox/sup.h>
39	#include <VBox/param.h>
40	#include <VBox/err.h>
41	#include <VBox/log.h>
42	#include <iprt/assert.h>
43	#include <iprt/alloc.h>
44	#include <iprt/asm.h>
45	#ifdef VBOX_STRICT
46	# include <iprt/crc.h>
47	#endif
48	#include <iprt/thread.h>
49	#include <iprt/string.h>
50	#include <iprt/system.h>
51
52
53	/*********************************************************************************************************************************
54	* Defined Constants And Macros *
55	*********************************************************************************************************************************/
56	/** The number of pages to free in one batch. */
57	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
58
59
60	/*
61	* PGMR3PhysReadU8-64
62	* PGMR3PhysWriteU8-64
63	*/
64	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
65	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
66	#define PGMPHYS_DATASIZE 1
67	#define PGMPHYS_DATATYPE uint8_t
68	#include "PGMPhysRWTmpl.h"
69
70	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
71	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
72	#define PGMPHYS_DATASIZE 2
73	#define PGMPHYS_DATATYPE uint16_t
74	#include "PGMPhysRWTmpl.h"
75
76	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
77	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
78	#define PGMPHYS_DATASIZE 4
79	#define PGMPHYS_DATATYPE uint32_t
80	#include "PGMPhysRWTmpl.h"
81
82	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
83	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
84	#define PGMPHYS_DATASIZE 8
85	#define PGMPHYS_DATATYPE uint64_t
86	#include "PGMPhysRWTmpl.h"
87
88
89	/**
90	* EMT worker for PGMR3PhysReadExternal.
91	*/
92	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
93	PGMACCESSORIGIN enmOrigin)
94	{
95	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
96	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
97	return VINF_SUCCESS;
98	}
99
100
101	/**
102	* Read from physical memory, external users.
103	*
104	* @returns VBox status code.
105	* @retval VINF_SUCCESS.
106	*
107	* @param pVM The cross context VM structure.
108	* @param GCPhys Physical address to read from.
109	* @param pvBuf Where to read into.
110	* @param cbRead How many bytes to read.
111	* @param enmOrigin Who is calling.
112	*
113	* @thread Any but EMTs.
114	*/
115	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
116	{
117	VM_ASSERT_OTHER_THREAD(pVM);
118
119	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
120	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
121
122	pgmLock(pVM);
123
124	/*
125	* Copy loop on ram ranges.
126	*/
127	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
128	for (;;)
129	{
130	/* Inside range or not? */
131	if (pRam && GCPhys >= pRam->GCPhys)
132	{
133	/*
134	* Must work our way thru this page by page.
135	*/
136	RTGCPHYS off = GCPhys - pRam->GCPhys;
137	while (off < pRam->cb)
138	{
139	unsigned iPage = off >> PAGE_SHIFT;
140	PPGMPAGE pPage = &pRam->aPages[iPage];
141
142	/*
143	* If the page has an ALL access handler, we'll have to
144	* delegate the job to EMT.
145	*/
146	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
147	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
148	{
149	pgmUnlock(pVM);
150
151	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
152	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
153	}
154	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
155
156	/*
157	* Simple stuff, go ahead.
158	*/
159	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
160	if (cb > cbRead)
161	cb = cbRead;
162	PGMPAGEMAPLOCK PgMpLck;
163	const void *pvSrc;
164	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
165	if (RT_SUCCESS(rc))
166	{
167	memcpy(pvBuf, pvSrc, cb);
168	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
169	}
170	else
171	{
172	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
173	pRam->GCPhys + off, pPage, rc));
174	memset(pvBuf, 0xff, cb);
175	}
176
177	/* next page */
178	if (cb >= cbRead)
179	{
180	pgmUnlock(pVM);
181	return VINF_SUCCESS;
182	}
183	cbRead -= cb;
184	off += cb;
185	GCPhys += cb;
186	pvBuf = (char *)pvBuf + cb;
187	} /* walk pages in ram range. */
188	}
189	else
190	{
191	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
192
193	/*
194	* Unassigned address space.
195	*/
196	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
197	if (cb >= cbRead)
198	{
199	memset(pvBuf, 0xff, cbRead);
200	break;
201	}
202	memset(pvBuf, 0xff, cb);
203
204	cbRead -= cb;
205	pvBuf = (char *)pvBuf + cb;
206	GCPhys += cb;
207	}
208
209	/* Advance range if necessary. */
210	while (pRam && GCPhys > pRam->GCPhysLast)
211	pRam = pRam->CTX_SUFF(pNext);
212	} /* Ram range walk */
213
214	pgmUnlock(pVM);
215
216	return VINF_SUCCESS;
217	}
218
219
220	/**
221	* EMT worker for PGMR3PhysWriteExternal.
222	*/
223	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
224	PGMACCESSORIGIN enmOrigin)
225	{
226	/** @todo VERR_EM_NO_MEMORY */
227	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
228	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
229	return VINF_SUCCESS;
230	}
231
232
233	/**
234	* Write to physical memory, external users.
235	*
236	* @returns VBox status code.
237	* @retval VINF_SUCCESS.
238	* @retval VERR_EM_NO_MEMORY.
239	*
240	* @param pVM The cross context VM structure.
241	* @param GCPhys Physical address to write to.
242	* @param pvBuf What to write.
243	* @param cbWrite How many bytes to write.
244	* @param enmOrigin Who is calling.
245	*
246	* @thread Any but EMTs.
247	*/
248	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
249	{
250	VM_ASSERT_OTHER_THREAD(pVM);
251
252	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
253	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
254	GCPhys, cbWrite, enmOrigin));
255	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
256	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
257
258	pgmLock(pVM);
259
260	/*
261	* Copy loop on ram ranges, stop when we hit something difficult.
262	*/
263	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
264	for (;;)
265	{
266	/* Inside range or not? */
267	if (pRam && GCPhys >= pRam->GCPhys)
268	{
269	/*
270	* Must work our way thru this page by page.
271	*/
272	RTGCPTR off = GCPhys - pRam->GCPhys;
273	while (off < pRam->cb)
274	{
275	RTGCPTR iPage = off >> PAGE_SHIFT;
276	PPGMPAGE pPage = &pRam->aPages[iPage];
277
278	/*
279	* Is the page problematic, we have to do the work on the EMT.
280	*
281	* Allocating writable pages and access handlers are
282	* problematic, write monitored pages are simple and can be
283	* dealt with here.
284	*/
285	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
286	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
287	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
288	{
289	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
290	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
291	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
292	else
293	{
294	pgmUnlock(pVM);
295
296	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
297	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
298	}
299	}
300	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
301
302	/*
303	* Simple stuff, go ahead.
304	*/
305	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
306	if (cb > cbWrite)
307	cb = cbWrite;
308	PGMPAGEMAPLOCK PgMpLck;
309	void *pvDst;
310	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
311	if (RT_SUCCESS(rc))
312	{
313	memcpy(pvDst, pvBuf, cb);
314	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
315	}
316	else
317	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
318	pRam->GCPhys + off, pPage, rc));
319
320	/* next page */
321	if (cb >= cbWrite)
322	{
323	pgmUnlock(pVM);
324	return VINF_SUCCESS;
325	}
326
327	cbWrite -= cb;
328	off += cb;
329	GCPhys += cb;
330	pvBuf = (const char *)pvBuf + cb;
331	} /* walk pages in ram range */
332	}
333	else
334	{
335	/*
336	* Unassigned address space, skip it.
337	*/
338	if (!pRam)
339	break;
340	size_t cb = pRam->GCPhys - GCPhys;
341	if (cb >= cbWrite)
342	break;
343	cbWrite -= cb;
344	pvBuf = (const char *)pvBuf + cb;
345	GCPhys += cb;
346	}
347
348	/* Advance range if necessary. */
349	while (pRam && GCPhys > pRam->GCPhysLast)
350	pRam = pRam->CTX_SUFF(pNext);
351	} /* Ram range walk */
352
353	pgmUnlock(pVM);
354	return VINF_SUCCESS;
355	}
356
357
358	/**
359	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
360	*
361	* @returns see PGMR3PhysGCPhys2CCPtrExternal
362	* @param pVM The cross context VM structure.
363	* @param pGCPhys Pointer to the guest physical address.
364	* @param ppv Where to store the mapping address.
365	* @param pLock Where to store the lock.
366	*/
367	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
368	{
369	/*
370	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
371	* an access handler after it succeeds.
372	*/
373	int rc = pgmLock(pVM);
374	AssertRCReturn(rc, rc);
375
376	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
377	if (RT_SUCCESS(rc))
378	{
379	PPGMPAGEMAPTLBE pTlbe;
380	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
381	AssertFatalRC(rc2);
382	PPGMPAGE pPage = pTlbe->pPage;
383	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
384	{
385	PGMPhysReleasePageMappingLock(pVM, pLock);
386	rc = VERR_PGM_PHYS_PAGE_RESERVED;
387	}
388	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
389	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
390	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
391	#endif
392	)
393	{
394	/* We must flush any corresponding pgm pool page here, otherwise we'll
395	* not be informed about writes and keep bogus gst->shw mappings around.
396	*/
397	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
398	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
399	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
400	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
401	}
402	}
403
404	pgmUnlock(pVM);
405	return rc;
406	}
407
408
409	/**
410	* Requests the mapping of a guest page into ring-3, external threads.
411	*
412	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
413	* release it.
414	*
415	* This API will assume your intention is to write to the page, and will
416	* therefore replace shared and zero pages. If you do not intend to modify the
417	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
418	*
419	* @returns VBox status code.
420	* @retval VINF_SUCCESS on success.
421	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
422	* backing or if the page has any active access handlers. The caller
423	* must fall back on using PGMR3PhysWriteExternal.
424	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
425	*
426	* @param pVM The cross context VM structure.
427	* @param GCPhys The guest physical address of the page that should be mapped.
428	* @param ppv Where to store the address corresponding to GCPhys.
429	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
430	*
431	* @remark Avoid calling this API from within critical sections (other than the
432	* PGM one) because of the deadlock risk when we have to delegating the
433	* task to an EMT.
434	* @thread Any.
435	*/
436	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
437	{
438	AssertPtr(ppv);
439	AssertPtr(pLock);
440
441	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
442
443	int rc = pgmLock(pVM);
444	AssertRCReturn(rc, rc);
445
446	/*
447	* Query the Physical TLB entry for the page (may fail).
448	*/
449	PPGMPAGEMAPTLBE pTlbe;
450	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
451	if (RT_SUCCESS(rc))
452	{
453	PPGMPAGE pPage = pTlbe->pPage;
454	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
455	rc = VERR_PGM_PHYS_PAGE_RESERVED;
456	else
457	{
458	/*
459	* If the page is shared, the zero page, or being write monitored
460	* it must be converted to an page that's writable if possible.
461	* We can only deal with write monitored pages here, the rest have
462	* to be on an EMT.
463	*/
464	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
465	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
466	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
467	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
468	#endif
469	)
470	{
471	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
472	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
473	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
474	&& !pgmPoolIsDirtyPage(pVM, GCPhys) /** @todo we're very likely doing this twice. */
475	#endif
476	)
477	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
478	else
479	{
480	pgmUnlock(pVM);
481
482	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
483	pVM, &GCPhys, ppv, pLock);
484	}
485	}
486
487	/*
488	* Now, just perform the locking and calculate the return address.
489	*/
490	PPGMPAGEMAP pMap = pTlbe->pMap;
491	if (pMap)
492	pMap->cRefs++;
493
494	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
495	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
496	{
497	if (cLocks == 0)
498	pVM->pgm.s.cWriteLockedPages++;
499	PGM_PAGE_INC_WRITE_LOCKS(pPage);
500	}
501	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
502	{
503	PGM_PAGE_INC_WRITE_LOCKS(pPage);
504	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
505	if (pMap)
506	pMap->cRefs++; /* Extra ref to prevent it from going away. */
507	}
508
509	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
510	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
511	pLock->pvMap = pMap;
512	}
513	}
514
515	pgmUnlock(pVM);
516	return rc;
517	}
518
519
520	/**
521	* Requests the mapping of a guest page into ring-3, external threads.
522	*
523	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
524	* release it.
525	*
526	* @returns VBox status code.
527	* @retval VINF_SUCCESS on success.
528	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
529	* backing or if the page as an active ALL access handler. The caller
530	* must fall back on using PGMPhysRead.
531	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
532	*
533	* @param pVM The cross context VM structure.
534	* @param GCPhys The guest physical address of the page that should be mapped.
535	* @param ppv Where to store the address corresponding to GCPhys.
536	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
537	*
538	* @remark Avoid calling this API from within critical sections (other than
539	* the PGM one) because of the deadlock risk.
540	* @thread Any.
541	*/
542	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
543	{
544	int rc = pgmLock(pVM);
545	AssertRCReturn(rc, rc);
546
547	/*
548	* Query the Physical TLB entry for the page (may fail).
549	*/
550	PPGMPAGEMAPTLBE pTlbe;
551	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
552	if (RT_SUCCESS(rc))
553	{
554	PPGMPAGE pPage = pTlbe->pPage;
555	#if 1
556	/* MMIO pages doesn't have any readable backing. */
557	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
558	rc = VERR_PGM_PHYS_PAGE_RESERVED;
559	#else
560	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
561	rc = VERR_PGM_PHYS_PAGE_RESERVED;
562	#endif
563	else
564	{
565	/*
566	* Now, just perform the locking and calculate the return address.
567	*/
568	PPGMPAGEMAP pMap = pTlbe->pMap;
569	if (pMap)
570	pMap->cRefs++;
571
572	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
573	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
574	{
575	if (cLocks == 0)
576	pVM->pgm.s.cReadLockedPages++;
577	PGM_PAGE_INC_READ_LOCKS(pPage);
578	}
579	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
580	{
581	PGM_PAGE_INC_READ_LOCKS(pPage);
582	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
583	if (pMap)
584	pMap->cRefs++; /* Extra ref to prevent it from going away. */
585	}
586
587	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
588	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
589	pLock->pvMap = pMap;
590	}
591	}
592
593	pgmUnlock(pVM);
594	return rc;
595	}
596
597
598	/**
599	* Requests the mapping of multiple guest page into ring-3, external threads.
600	*
601	* When you're done with the pages, call PGMPhysBulkReleasePageMappingLock()
602	* ASAP to release them.
603	*
604	* This API will assume your intention is to write to the pages, and will
605	* therefore replace shared and zero pages. If you do not intend to modify the
606	* pages, use the PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal() API.
607	*
608	* @returns VBox status code.
609	* @retval VINF_SUCCESS on success.
610	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
611	* backing or if any of the pages the page has any active access
612	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
613	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
614	* an invalid physical address.
615	*
616	* @param pVM The cross context VM structure.
617	* @param cPages Number of pages to lock.
618	* @param paGCPhysPages The guest physical address of the pages that
619	* should be mapped (@a cPages entries).
620	* @param papvPages Where to store the ring-3 mapping addresses
621	* corresponding to @a paGCPhysPages.
622	* @param paLocks Where to store the locking information that
623	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
624	* in length).
625	*
626	* @remark Avoid calling this API from within critical sections (other than the
627	* PGM one) because of the deadlock risk when we have to delegating the
628	* task to an EMT.
629	* @thread Any.
630	*/
631	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
632	void **papvPages, PPGMPAGEMAPLOCK paLocks)
633	{
634	Assert(cPages > 0);
635	AssertPtr(papvPages);
636	AssertPtr(paLocks);
637
638	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
639
640	int rc = pgmLock(pVM);
641	AssertRCReturn(rc, rc);
642
643	/*
644	* Lock the pages one by one.
645	* The loop body is similar to PGMR3PhysGCPhys2CCPtrExternal.
646	*/
647	int32_t cNextYield = 128;
648	uint32_t iPage;
649	for (iPage = 0; iPage < cPages; iPage++)
650	{
651	if (--cNextYield > 0)
652	{ /* likely */ }
653	else
654	{
655	pgmUnlock(pVM);
656	ASMNopPause();
657	pgmLock(pVM);
658	cNextYield = 128;
659	}
660
661	/*
662	* Query the Physical TLB entry for the page (may fail).
663	*/
664	PPGMPAGEMAPTLBE pTlbe;
665	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
666	if (RT_SUCCESS(rc))
667	{ }
668	else
669	break;
670	PPGMPAGE pPage = pTlbe->pPage;
671
672	/*
673	* No MMIO or active access handlers.
674	*/
675	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
676	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
677	{ }
678	else
679	{
680	rc = VERR_PGM_PHYS_PAGE_RESERVED;
681	break;
682	}
683
684	/*
685	* The page must be in the allocated state and not be a dirty pool page.
686	* We can handle converting a write monitored page to an allocated one, but
687	* anything more complicated must be delegated to an EMT.
688	*/
689	bool fDelegateToEmt = false;
690	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
691	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
692	fDelegateToEmt = pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]);
693	#else
694	fDelegateToEmt = false;
695	#endif
696	else if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
697	{
698	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
699	if (!pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]))
700	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, paGCPhysPages[iPage]);
701	else
702	fDelegateToEmt = true;
703	#endif
704	}
705	else
706	fDelegateToEmt = true;
707	if (!fDelegateToEmt)
708	{ }
709	else
710	{
711	/* We could do this delegation in bulk, but considered too much work vs gain. */
712	pgmUnlock(pVM);
713	rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
714	pVM, &paGCPhysPages[iPage], &papvPages[iPage], &paLocks[iPage]);
715	pgmLock(pVM);
716	if (RT_FAILURE(rc))
717	break;
718	cNextYield = 128;
719	}
720
721	/*
722	* Now, just perform the locking and address calculation.
723	*/
724	PPGMPAGEMAP pMap = pTlbe->pMap;
725	if (pMap)
726	pMap->cRefs++;
727
728	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
729	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
730	{
731	if (cLocks == 0)
732	pVM->pgm.s.cWriteLockedPages++;
733	PGM_PAGE_INC_WRITE_LOCKS(pPage);
734	}
735	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
736	{
737	PGM_PAGE_INC_WRITE_LOCKS(pPage);
738	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", paGCPhysPages[iPage], pPage));
739	if (pMap)
740	pMap->cRefs++; /* Extra ref to prevent it from going away. */
741	}
742
743	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
744	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
745	paLocks[iPage].pvMap = pMap;
746	}
747
748	pgmUnlock(pVM);
749
750	/*
751	* On failure we must unlock any pages we managed to get already.
752	*/
753	if (RT_FAILURE(rc) && iPage > 0)
754	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
755
756	return rc;
757	}
758
759
760	/**
761	* Requests the mapping of multiple guest page into ring-3, for reading only,
762	* external threads.
763	*
764	* When you're done with the pages, call PGMPhysReleasePageMappingLock() ASAP
765	* to release them.
766	*
767	* @returns VBox status code.
768	* @retval VINF_SUCCESS on success.
769	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
770	* backing or if any of the pages the page has an active ALL access
771	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
772	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
773	* an invalid physical address.
774	*
775	* @param pVM The cross context VM structure.
776	* @param cPages Number of pages to lock.
777	* @param paGCPhysPages The guest physical address of the pages that
778	* should be mapped (@a cPages entries).
779	* @param papvPages Where to store the ring-3 mapping addresses
780	* corresponding to @a paGCPhysPages.
781	* @param paLocks Where to store the lock information that
782	* pfnPhysReleasePageMappingLock needs (@a cPages
783	* in length).
784	*
785	* @remark Avoid calling this API from within critical sections (other than
786	* the PGM one) because of the deadlock risk.
787	* @thread Any.
788	*/
789	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
790	void const **papvPages, PPGMPAGEMAPLOCK paLocks)
791	{
792	Assert(cPages > 0);
793	AssertPtr(papvPages);
794	AssertPtr(paLocks);
795
796	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
797
798	int rc = pgmLock(pVM);
799	AssertRCReturn(rc, rc);
800
801	/*
802	* Lock the pages one by one.
803	* The loop body is similar to PGMR3PhysGCPhys2CCPtrReadOnlyExternal.
804	*/
805	int32_t cNextYield = 256;
806	uint32_t iPage;
807	for (iPage = 0; iPage < cPages; iPage++)
808	{
809	if (--cNextYield > 0)
810	{ /* likely */ }
811	else
812	{
813	pgmUnlock(pVM);
814	ASMNopPause();
815	pgmLock(pVM);
816	cNextYield = 256;
817	}
818
819	/*
820	* Query the Physical TLB entry for the page (may fail).
821	*/
822	PPGMPAGEMAPTLBE pTlbe;
823	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
824	if (RT_SUCCESS(rc))
825	{ }
826	else
827	break;
828	PPGMPAGE pPage = pTlbe->pPage;
829
830	/*
831	* No MMIO or active all access handlers, everything else can be accessed.
832	*/
833	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
834	&& !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
835	{ }
836	else
837	{
838	rc = VERR_PGM_PHYS_PAGE_RESERVED;
839	break;
840	}
841
842	/*
843	* Now, just perform the locking and address calculation.
844	*/
845	PPGMPAGEMAP pMap = pTlbe->pMap;
846	if (pMap)
847	pMap->cRefs++;
848
849	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
850	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
851	{
852	if (cLocks == 0)
853	pVM->pgm.s.cReadLockedPages++;
854	PGM_PAGE_INC_READ_LOCKS(pPage);
855	}
856	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
857	{
858	PGM_PAGE_INC_READ_LOCKS(pPage);
859	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", paGCPhysPages[iPage], pPage));
860	if (pMap)
861	pMap->cRefs++; /* Extra ref to prevent it from going away. */
862	}
863
864	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
865	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
866	paLocks[iPage].pvMap = pMap;
867	}
868
869	pgmUnlock(pVM);
870
871	/*
872	* On failure we must unlock any pages we managed to get already.
873	*/
874	if (RT_FAILURE(rc) && iPage > 0)
875	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
876
877	return rc;
878	}
879
880
881	#define MAKE_LEAF(a_pNode) \
882	do { \
883	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
884	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
885	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
886	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
887	} while (0)
888
889	#define INSERT_LEFT(a_pParent, a_pNode) \
890	do { \
891	(a_pParent)->pLeftR3 = (a_pNode); \
892	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
893	} while (0)
894	#define INSERT_RIGHT(a_pParent, a_pNode) \
895	do { \
896	(a_pParent)->pRightR3 = (a_pNode); \
897	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
898	} while (0)
899
900
901	/**
902	* Recursive tree builder.
903	*
904	* @param ppRam Pointer to the iterator variable.
905	* @param iDepth The current depth. Inserts a leaf node if 0.
906	*/
907	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
908	{
909	PPGMRAMRANGE pRam;
910	if (iDepth <= 0)
911	{
912	/*
913	* Leaf node.
914	*/
915	pRam = *ppRam;
916	if (pRam)
917	{
918	*ppRam = pRam->pNextR3;
919	MAKE_LEAF(pRam);
920	}
921	}
922	else
923	{
924
925	/*
926	* Intermediate node.
927	*/
928	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
929
930	pRam = *ppRam;
931	if (!pRam)
932	return pLeft;
933	*ppRam = pRam->pNextR3;
934	MAKE_LEAF(pRam);
935	INSERT_LEFT(pRam, pLeft);
936
937	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
938	if (pRight)
939	INSERT_RIGHT(pRam, pRight);
940	}
941	return pRam;
942	}
943
944
945	/**
946	* Rebuilds the RAM range search trees.
947	*
948	* @param pVM The cross context VM structure.
949	*/
950	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
951	{
952
953	/*
954	* Create the reasonably balanced tree in a sequential fashion.
955	* For simplicity (laziness) we use standard recursion here.
956	*/
957	int iDepth = 0;
958	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
959	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
960	while (pRam)
961	{
962	PPGMRAMRANGE pLeft = pRoot;
963
964	pRoot = pRam;
965	pRam = pRam->pNextR3;
966	MAKE_LEAF(pRoot);
967	INSERT_LEFT(pRoot, pLeft);
968
969	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
970	if (pRight)
971	INSERT_RIGHT(pRoot, pRight);
972	/** @todo else: rotate the tree. */
973
974	iDepth++;
975	}
976
977	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
978	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
979
980	#ifdef VBOX_STRICT
981	/*
982	* Verify that the above code works.
983	*/
984	unsigned cRanges = 0;
985	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
986	cRanges++;
987	Assert(cRanges > 0);
988
989	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
990	if ((1U << cMaxDepth) < cRanges)
991	cMaxDepth++;
992
993	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
994	{
995	unsigned cDepth = 0;
996	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
997	for (;;)
998	{
999	if (pRam == pRam2)
1000	break;
1001	Assert(pRam2);
1002	if (pRam->GCPhys < pRam2->GCPhys)
1003	pRam2 = pRam2->pLeftR3;
1004	else
1005	pRam2 = pRam2->pRightR3;
1006	}
1007	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
1008	}
1009	#endif /* VBOX_STRICT */
1010	}
1011
1012	#undef MAKE_LEAF
1013	#undef INSERT_LEFT
1014	#undef INSERT_RIGHT
1015
1016	/**
1017	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
1018	*
1019	* Called when anything was relocated.
1020	*
1021	* @param pVM The cross context VM structure.
1022	*/
1023	void pgmR3PhysRelinkRamRanges(PVM pVM)
1024	{
1025	PPGMRAMRANGE pCur;
1026
1027	#ifdef VBOX_STRICT
1028	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1029	{
1030	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
1031	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
1032	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1033	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
1034	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
1035	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
1036	Assert( pCur2 == pCur
1037	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
1038	}
1039	#endif
1040
1041	pCur = pVM->pgm.s.pRamRangesXR3;
1042	if (pCur)
1043	{
1044	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
1045
1046	for (; pCur->pNextR3; pCur = pCur->pNextR3)
1047	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
1048
1049	Assert(pCur->pNextR0 == NIL_RTR0PTR);
1050	}
1051	else
1052	{
1053	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
1054	}
1055	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1056
1057	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1058	}
1059
1060
1061	/**
1062	* Links a new RAM range into the list.
1063	*
1064	* @param pVM The cross context VM structure.
1065	* @param pNew Pointer to the new list entry.
1066	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1067	*/
1068	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
1069	{
1070	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
1071	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
1072
1073	pgmLock(pVM);
1074
1075	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
1076	pNew->pNextR3 = pRam;
1077	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
1078
1079	if (pPrev)
1080	{
1081	pPrev->pNextR3 = pNew;
1082	pPrev->pNextR0 = pNew->pSelfR0;
1083	}
1084	else
1085	{
1086	pVM->pgm.s.pRamRangesXR3 = pNew;
1087	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
1088	}
1089	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1090
1091	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1092	pgmUnlock(pVM);
1093	}
1094
1095
1096	/**
1097	* Unlink an existing RAM range from the list.
1098	*
1099	* @param pVM The cross context VM structure.
1100	* @param pRam Pointer to the new list entry.
1101	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1102	*/
1103	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
1104	{
1105	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
1106	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
1107
1108	pgmLock(pVM);
1109
1110	PPGMRAMRANGE pNext = pRam->pNextR3;
1111	if (pPrev)
1112	{
1113	pPrev->pNextR3 = pNext;
1114	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1115	}
1116	else
1117	{
1118	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
1119	pVM->pgm.s.pRamRangesXR3 = pNext;
1120	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1121	}
1122	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1123
1124	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1125	pgmUnlock(pVM);
1126	}
1127
1128
1129	/**
1130	* Unlink an existing RAM range from the list.
1131	*
1132	* @param pVM The cross context VM structure.
1133	* @param pRam Pointer to the new list entry.
1134	*/
1135	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
1136	{
1137	pgmLock(pVM);
1138
1139	/* find prev. */
1140	PPGMRAMRANGE pPrev = NULL;
1141	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
1142	while (pCur != pRam)
1143	{
1144	pPrev = pCur;
1145	pCur = pCur->pNextR3;
1146	}
1147	AssertFatal(pCur);
1148
1149	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
1150	pgmUnlock(pVM);
1151	}
1152
1153
1154	/**
1155	* Frees a range of pages, replacing them with ZERO pages of the specified type.
1156	*
1157	* @returns VBox status code.
1158	* @param pVM The cross context VM structure.
1159	* @param pRam The RAM range in which the pages resides.
1160	* @param GCPhys The address of the first page.
1161	* @param GCPhysLast The address of the last page.
1162	* @param enmType The page type to replace then with.
1163	*/
1164	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPAGETYPE enmType)
1165	{
1166	PGM_LOCK_ASSERT_OWNER(pVM);
1167	uint32_t cPendingPages = 0;
1168	PGMMFREEPAGESREQ pReq;
1169	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1170	AssertLogRelRCReturn(rc, rc);
1171
1172	/* Iterate the pages. */
1173	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1174	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1175	while (cPagesLeft-- > 0)
1176	{
1177	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys, enmType);
1178	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1179
1180	PGM_PAGE_SET_TYPE(pVM, pPageDst, enmType);
1181
1182	GCPhys += PAGE_SIZE;
1183	pPageDst++;
1184	}
1185
1186	if (cPendingPages)
1187	{
1188	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1189	AssertLogRelRCReturn(rc, rc);
1190	}
1191	GMMR3FreePagesCleanup(pReq);
1192
1193	return rc;
1194	}
1195
1196	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1197
1198	/**
1199	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
1200	*
1201	* This is only called on one of the EMTs while the other ones are waiting for
1202	* it to complete this function.
1203	*
1204	* @returns VINF_SUCCESS (VBox strict status code).
1205	* @param pVM The cross context VM structure.
1206	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1207	* @param pvUser User parameter
1208	*/
1209	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1210	{
1211	uintptr_t paUser = (uintptr_t )pvUser;
1212	bool fInflate = !!paUser[0];
1213	unsigned cPages = paUser[1];
1214	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
1215	uint32_t cPendingPages = 0;
1216	PGMMFREEPAGESREQ pReq;
1217	int rc;
1218
1219	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
1220	pgmLock(pVM);
1221
1222	if (fInflate)
1223	{
1224	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
1225	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
1226
1227	/* Replace pages with ZERO pages. */
1228	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1229	if (RT_FAILURE(rc))
1230	{
1231	pgmUnlock(pVM);
1232	AssertLogRelRC(rc);
1233	return rc;
1234	}
1235
1236	/* Iterate the pages. */
1237	for (unsigned i = 0; i < cPages; i++)
1238	{
1239	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1240	if ( pPage == NULL
1241	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
1242	{
1243	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
1244	break;
1245	}
1246
1247	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
1248
1249	/* Flush the shadow PT if this page was previously used as a guest page table. */
1250	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
1251
1252	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i], (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
1253	if (RT_FAILURE(rc))
1254	{
1255	pgmUnlock(pVM);
1256	AssertLogRelRC(rc);
1257	return rc;
1258	}
1259	Assert(PGM_PAGE_IS_ZERO(pPage));
1260	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
1261	}
1262
1263	if (cPendingPages)
1264	{
1265	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1266	if (RT_FAILURE(rc))
1267	{
1268	pgmUnlock(pVM);
1269	AssertLogRelRC(rc);
1270	return rc;
1271	}
1272	}
1273	GMMR3FreePagesCleanup(pReq);
1274	}
1275	else
1276	{
1277	/* Iterate the pages. */
1278	for (unsigned i = 0; i < cPages; i++)
1279	{
1280	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1281	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
1282
1283	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
1284
1285	Assert(PGM_PAGE_IS_BALLOONED(pPage));
1286
1287	/* Change back to zero page. (NEM does not need to be informed.) */
1288	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1289	}
1290
1291	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
1292	}
1293
1294	/* Notify GMM about the balloon change. */
1295	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
1296	if (RT_SUCCESS(rc))
1297	{
1298	if (!fInflate)
1299	{
1300	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
1301	pVM->pgm.s.cBalloonedPages -= cPages;
1302	}
1303	else
1304	pVM->pgm.s.cBalloonedPages += cPages;
1305	}
1306
1307	pgmUnlock(pVM);
1308
1309	/* Flush the recompiler's TLB as well. */
1310	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1311	CPUMSetChangedFlags(pVM->apCpusR3[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1312
1313	AssertLogRelRC(rc);
1314	return rc;
1315	}
1316
1317
1318	/**
1319	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
1320	*
1321	* @returns VBox status code.
1322	* @param pVM The cross context VM structure.
1323	* @param fInflate Inflate or deflate memory balloon
1324	* @param cPages Number of pages to free
1325	* @param paPhysPage Array of guest physical addresses
1326	*/
1327	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1328	{
1329	uintptr_t paUser[3];
1330
1331	paUser[0] = fInflate;
1332	paUser[1] = cPages;
1333	paUser[2] = (uintptr_t)paPhysPage;
1334	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1335	AssertRC(rc);
1336
1337	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
1338	RTMemFree(paPhysPage);
1339	}
1340
1341	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
1342
1343	/**
1344	* Inflate or deflate a memory balloon
1345	*
1346	* @returns VBox status code.
1347	* @param pVM The cross context VM structure.
1348	* @param fInflate Inflate or deflate memory balloon
1349	* @param cPages Number of pages to free
1350	* @param paPhysPage Array of guest physical addresses
1351	*/
1352	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1353	{
1354	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
1355	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1356	int rc;
1357
1358	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
1359	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
1360
1361	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
1362	* In the SMP case we post a request packet to postpone the job.
1363	*/
1364	if (pVM->cCpus > 1)
1365	{
1366	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
1367	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
1368	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
1369
1370	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
1371
1372	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
1373	AssertRC(rc);
1374	}
1375	else
1376	{
1377	uintptr_t paUser[3];
1378
1379	paUser[0] = fInflate;
1380	paUser[1] = cPages;
1381	paUser[2] = (uintptr_t)paPhysPage;
1382	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1383	AssertRC(rc);
1384	}
1385	return rc;
1386
1387	#else
1388	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
1389	return VERR_NOT_IMPLEMENTED;
1390	#endif
1391	}
1392
1393
1394	/**
1395	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
1396	* physical RAM.
1397	*
1398	* This is only called on one of the EMTs while the other ones are waiting for
1399	* it to complete this function.
1400	*
1401	* @returns VINF_SUCCESS (VBox strict status code).
1402	* @param pVM The cross context VM structure.
1403	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1404	* @param pvUser User parameter, unused.
1405	*/
1406	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1407	{
1408	int rc = VINF_SUCCESS;
1409	NOREF(pvUser); NOREF(pVCpu);
1410
1411	pgmLock(pVM);
1412	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1413	pgmPoolResetDirtyPages(pVM);
1414	#endif
1415
1416	/** @todo pointless to write protect the physical page pointed to by RSP. */
1417
1418	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1419	pRam;
1420	pRam = pRam->CTX_SUFF(pNext))
1421	{
1422	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1423	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1424	{
1425	PPGMPAGE pPage = &pRam->aPages[iPage];
1426	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1427
1428	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1429	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1430	{
1431	/*
1432	* A RAM page.
1433	*/
1434	switch (PGM_PAGE_GET_STATE(pPage))
1435	{
1436	case PGM_PAGE_STATE_ALLOCATED:
1437	/** @todo Optimize this: Don't always re-enable write
1438	* monitoring if the page is known to be very busy. */
1439	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
1440	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1441
1442	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1443	break;
1444
1445	case PGM_PAGE_STATE_SHARED:
1446	AssertFailed();
1447	break;
1448
1449	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
1450	default:
1451	break;
1452	}
1453	}
1454	}
1455	}
1456	pgmR3PoolWriteProtectPages(pVM);
1457	PGM_INVL_ALL_VCPU_TLBS(pVM);
1458	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1459	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1460
1461	pgmUnlock(pVM);
1462	return rc;
1463	}
1464
1465	/**
1466	* Protect all physical RAM to monitor writes
1467	*
1468	* @returns VBox status code.
1469	* @param pVM The cross context VM structure.
1470	*/
1471	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
1472	{
1473	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1474
1475	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
1476	AssertRC(rc);
1477	return rc;
1478	}
1479
1480
1481	/**
1482	* Gets the number of ram ranges.
1483	*
1484	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1485	* @param pVM The cross context VM structure.
1486	*/
1487	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1488	{
1489	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1490
1491	pgmLock(pVM);
1492	uint32_t cRamRanges = 0;
1493	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1494	cRamRanges++;
1495	pgmUnlock(pVM);
1496	return cRamRanges;
1497	}
1498
1499
1500	/**
1501	* Get information about a range.
1502	*
1503	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1504	* @param pVM The cross context VM structure.
1505	* @param iRange The ordinal of the range.
1506	* @param pGCPhysStart Where to return the start of the range. Optional.
1507	* @param pGCPhysLast Where to return the address of the last byte in the
1508	* range. Optional.
1509	* @param ppszDesc Where to return the range description. Optional.
1510	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1511	* Optional.
1512	*/
1513	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1514	const char *ppszDesc, bool pfIsMmio)
1515	{
1516	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1517
1518	pgmLock(pVM);
1519	uint32_t iCurRange = 0;
1520	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1521	if (iCurRange == iRange)
1522	{
1523	if (pGCPhysStart)
1524	*pGCPhysStart = pCur->GCPhys;
1525	if (pGCPhysLast)
1526	*pGCPhysLast = pCur->GCPhysLast;
1527	if (ppszDesc)
1528	*ppszDesc = pCur->pszDesc;
1529	if (pfIsMmio)
1530	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1531
1532	pgmUnlock(pVM);
1533	return VINF_SUCCESS;
1534	}
1535	pgmUnlock(pVM);
1536	return VERR_OUT_OF_RANGE;
1537	}
1538
1539
1540	/**
1541	* Query the amount of free memory inside VMMR0
1542	*
1543	* @returns VBox status code.
1544	* @param pUVM The user mode VM handle.
1545	* @param pcbAllocMem Where to return the amount of memory allocated
1546	* by VMs.
1547	* @param pcbFreeMem Where to return the amount of memory that is
1548	* allocated from the host but not currently used
1549	* by any VMs.
1550	* @param pcbBallonedMem Where to return the sum of memory that is
1551	* currently ballooned by the VMs.
1552	* @param pcbSharedMem Where to return the amount of memory that is
1553	* currently shared.
1554	*/
1555	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
1556	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
1557	{
1558	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1559	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
1560
1561	uint64_t cAllocPages = 0;
1562	uint64_t cFreePages = 0;
1563	uint64_t cBalloonPages = 0;
1564	uint64_t cSharedPages = 0;
1565	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
1566	AssertRCReturn(rc, rc);
1567
1568	if (pcbAllocMem)
1569	pcbAllocMem = cAllocPages _4K;
1570
1571	if (pcbFreeMem)
1572	pcbFreeMem = cFreePages _4K;
1573
1574	if (pcbBallonedMem)
1575	pcbBallonedMem = cBalloonPages _4K;
1576
1577	if (pcbSharedMem)
1578	pcbSharedMem = cSharedPages _4K;
1579
1580	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
1581	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
1582	return VINF_SUCCESS;
1583	}
1584
1585
1586	/**
1587	* Query memory stats for the VM.
1588	*
1589	* @returns VBox status code.
1590	* @param pUVM The user mode VM handle.
1591	* @param pcbTotalMem Where to return total amount memory the VM may
1592	* possibly use.
1593	* @param pcbPrivateMem Where to return the amount of private memory
1594	* currently allocated.
1595	* @param pcbSharedMem Where to return the amount of actually shared
1596	* memory currently used by the VM.
1597	* @param pcbZeroMem Where to return the amount of memory backed by
1598	* zero pages.
1599	*
1600	* @remarks The total mem is normally larger than the sum of the three
1601	* components. There are two reasons for this, first the amount of
1602	* shared memory is what we're sure is shared instead of what could
1603	* possibly be shared with someone. Secondly, because the total may
1604	* include some pure MMIO pages that doesn't go into any of the three
1605	* sub-counts.
1606	*
1607	* @todo Why do we return reused shared pages instead of anything that could
1608	* potentially be shared? Doesn't this mean the first VM gets a much
1609	* lower number of shared pages?
1610	*/
1611	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
1612	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
1613	{
1614	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1615	PVM pVM = pUVM->pVM;
1616	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1617
1618	if (pcbTotalMem)
1619	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
1620
1621	if (pcbPrivateMem)
1622	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
1623
1624	if (pcbSharedMem)
1625	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
1626
1627	if (pcbZeroMem)
1628	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
1629
1630	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
1631	return VINF_SUCCESS;
1632	}
1633
1634
1635	/**
1636	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1637	*
1638	* @param pVM The cross context VM structure.
1639	* @param pNew The new RAM range.
1640	* @param GCPhys The address of the RAM range.
1641	* @param GCPhysLast The last address of the RAM range.
1642	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
1643	* if in HMA.
1644	* @param R0PtrNew Ditto for R0.
1645	* @param pszDesc The description.
1646	* @param pPrev The previous RAM range (for linking).
1647	*/
1648	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1649	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
1650	{
1651	/*
1652	* Initialize the range.
1653	*/
1654	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
1655	pNew->GCPhys = GCPhys;
1656	pNew->GCPhysLast = GCPhysLast;
1657	pNew->cb = GCPhysLast - GCPhys + 1;
1658	pNew->pszDesc = pszDesc;
1659	pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
1660	pNew->pvR3 = NULL;
1661	pNew->paLSPages = NULL;
1662
1663	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1664	RTGCPHYS iPage = cPages;
1665	while (iPage-- > 0)
1666	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1667
1668	/* Update the page count stats. */
1669	pVM->pgm.s.cZeroPages += cPages;
1670	pVM->pgm.s.cAllPages += cPages;
1671
1672	/*
1673	* Link it.
1674	*/
1675	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1676	}
1677
1678
1679	#ifndef PGM_WITHOUT_MAPPINGS
1680	/**
1681	* @callback_method_impl{FNPGMRELOCATE, Relocate a floating RAM range.}
1682	* @sa pgmR3PhysMMIO2ExRangeRelocate
1683	*/
1684	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
1685	PGMRELOCATECALL enmMode, void *pvUser)
1686	{
1687	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
1688	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
1689	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE); RT_NOREF_PV(GCPtrOld);
1690
1691	switch (enmMode)
1692	{
1693	case PGMRELOCATECALL_SUGGEST:
1694	return true;
1695
1696	case PGMRELOCATECALL_RELOCATE:
1697	{
1698	/*
1699	* Update myself, then relink all the ranges and flush the RC TLB.
1700	*/
1701	pgmLock(pVM);
1702
1703	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
1704
1705	pgmR3PhysRelinkRamRanges(pVM);
1706	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
1707	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
1708
1709	pgmUnlock(pVM);
1710	return true;
1711	}
1712
1713	default:
1714	AssertFailedReturn(false);
1715	}
1716	}
1717	#endif /* !PGM_WITHOUT_MAPPINGS */
1718
1719
1720	/**
1721	* PGMR3PhysRegisterRam worker that registers a high chunk.
1722	*
1723	* @returns VBox status code.
1724	* @param pVM The cross context VM structure.
1725	* @param GCPhys The address of the RAM.
1726	* @param cRamPages The number of RAM pages to register.
1727	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
1728	* @param iChunk The chunk number.
1729	* @param pszDesc The RAM range description.
1730	* @param ppPrev Previous RAM range pointer. In/Out.
1731	*/
1732	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
1733	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
1734	PPGMRAMRANGE *ppPrev)
1735	{
1736	const char *pszDescChunk = iChunk == 0
1737	? pszDesc
1738	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1739	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1740
1741	/*
1742	* Allocate memory for the new chunk.
1743	*/
1744	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1745	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1746	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1747	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1748	void *pvChunk = NULL;
1749	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
1750	if (RT_SUCCESS(rc))
1751	{
1752	Assert(R0PtrChunk != NIL_RTR0PTR);
1753	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1754
1755	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1756
1757	/*
1758	* Create a mapping and map the pages into it.
1759	* We push these in below the HMA.
1760	*/
1761	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
1762	#ifndef PGM_WITHOUT_MAPPINGS
1763	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
1764	if (RT_SUCCESS(rc))
1765	#endif /* !PGM_WITHOUT_MAPPINGS */
1766	{
1767	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
1768
1769	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
1770	#ifndef PGM_WITHOUT_MAPPINGS
1771	RTGCPTR GCPtrPage = GCPtrChunk;
1772	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
1773	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
1774	if (RT_SUCCESS(rc))
1775	#endif /* !PGM_WITHOUT_MAPPINGS */
1776	{
1777	/*
1778	* Ok, init and link the range.
1779	*/
1780	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1781	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
1782	*ppPrev = pNew;
1783	}
1784	}
1785
1786	if (RT_FAILURE(rc))
1787	SUPR3PageFreeEx(pvChunk, cChunkPages);
1788	}
1789
1790	RTMemTmpFree(paChunkPages);
1791	return rc;
1792	}
1793
1794
1795	/**
1796	* Sets up a range RAM.
1797	*
1798	* This will check for conflicting registrations, make a resource
1799	* reservation for the memory (with GMM), and setup the per-page
1800	* tracking structures (PGMPAGE).
1801	*
1802	* @returns VBox status code.
1803	* @param pVM The cross context VM structure.
1804	* @param GCPhys The physical address of the RAM.
1805	* @param cb The size of the RAM.
1806	* @param pszDesc The description - not copied, so, don't free or change it.
1807	*/
1808	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1809	{
1810	/*
1811	* Validate input.
1812	*/
1813	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1814	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1815	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1816	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1817	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1818	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1819	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1820	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1821
1822	pgmLock(pVM);
1823
1824	/*
1825	* Find range location and check for conflicts.
1826	* (We don't lock here because the locking by EMT is only required on update.)
1827	*/
1828	PPGMRAMRANGE pPrev = NULL;
1829	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1830	while (pRam && GCPhysLast >= pRam->GCPhys)
1831	{
1832	if ( GCPhysLast >= pRam->GCPhys
1833	&& GCPhys <= pRam->GCPhysLast)
1834	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1835	GCPhys, GCPhysLast, pszDesc,
1836	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1837	VERR_PGM_RAM_CONFLICT);
1838
1839	/* next */
1840	pPrev = pRam;
1841	pRam = pRam->pNextR3;
1842	}
1843
1844	/*
1845	* Register it with GMM (the API bitches).
1846	*/
1847	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1848	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1849	if (RT_FAILURE(rc))
1850	{
1851	pgmUnlock(pVM);
1852	return rc;
1853	}
1854
1855	if ( GCPhys >= _4G
1856	&& cPages > 256)
1857	{
1858	/*
1859	* The PGMRAMRANGE structures for the high memory can get very big.
1860	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1861	* allocation size limit there and also to avoid being unable to find
1862	* guest mapping space for them, we split this memory up into 4MB in
1863	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1864	* mode.
1865	*
1866	* The first and last page of each mapping are guard pages and marked
1867	* not-present. So, we've got 4186112 and 16769024 bytes available for
1868	* the PGMRAMRANGE structure.
1869	*
1870	* Note! The sizes used here will influence the saved state.
1871	*/
1872	uint32_t cbChunk = 16U*_1M;
1873	uint32_t cPagesPerChunk = 1048048; /* max ~1048059 */
1874	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1875	AssertRelease(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1876
1877	RTGCPHYS cPagesLeft = cPages;
1878	RTGCPHYS GCPhysChunk = GCPhys;
1879	uint32_t iChunk = 0;
1880	while (cPagesLeft > 0)
1881	{
1882	uint32_t cPagesInChunk = cPagesLeft;
1883	if (cPagesInChunk > cPagesPerChunk)
1884	cPagesInChunk = cPagesPerChunk;
1885
1886	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1887	AssertRCReturn(rc, rc);
1888
1889	/* advance */
1890	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1891	cPagesLeft -= cPagesInChunk;
1892	iChunk++;
1893	}
1894	}
1895	else
1896	{
1897	/*
1898	* Allocate, initialize and link the new RAM range.
1899	*/
1900	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
1901	PPGMRAMRANGE pNew;
1902	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1903	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1904
1905	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1906	}
1907	pgmPhysInvalidatePageMapTLB(pVM);
1908
1909	/*
1910	* Notify NEM while holding the lock (experimental) and REM without (like always).
1911	*/
1912	rc = NEMR3NotifyPhysRamRegister(pVM, GCPhys, cb);
1913	pgmUnlock(pVM);
1914	#ifdef VBOX_WITH_REM
1915	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1916	#endif
1917	return rc;
1918	}
1919
1920
1921	/**
1922	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1923	*
1924	* We do this late in the init process so that all the ROM and MMIO ranges have
1925	* been registered already and we don't go wasting memory on them.
1926	*
1927	* @returns VBox status code.
1928	*
1929	* @param pVM The cross context VM structure.
1930	*/
1931	int pgmR3PhysRamPreAllocate(PVM pVM)
1932	{
1933	Assert(pVM->pgm.s.fRamPreAlloc);
1934	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1935
1936	/*
1937	* Walk the RAM ranges and allocate all RAM pages, halt at
1938	* the first allocation error.
1939	*/
1940	uint64_t cPages = 0;
1941	uint64_t NanoTS = RTTimeNanoTS();
1942	pgmLock(pVM);
1943	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1944	{
1945	PPGMPAGE pPage = &pRam->aPages[0];
1946	RTGCPHYS GCPhys = pRam->GCPhys;
1947	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1948	while (cLeft-- > 0)
1949	{
1950	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1951	{
1952	switch (PGM_PAGE_GET_STATE(pPage))
1953	{
1954	case PGM_PAGE_STATE_ZERO:
1955	{
1956	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1957	if (RT_FAILURE(rc))
1958	{
1959	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1960	pgmUnlock(pVM);
1961	return rc;
1962	}
1963	cPages++;
1964	break;
1965	}
1966
1967	case PGM_PAGE_STATE_BALLOONED:
1968	case PGM_PAGE_STATE_ALLOCATED:
1969	case PGM_PAGE_STATE_WRITE_MONITORED:
1970	case PGM_PAGE_STATE_SHARED:
1971	/* nothing to do here. */
1972	break;
1973	}
1974	}
1975
1976	/* next */
1977	pPage++;
1978	GCPhys += PAGE_SIZE;
1979	}
1980	}
1981	pgmUnlock(pVM);
1982	NanoTS = RTTimeNanoTS() - NanoTS;
1983
1984	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1985	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1986	return VINF_SUCCESS;
1987	}
1988
1989
1990	/**
1991	* Checks shared page checksums.
1992	*
1993	* @param pVM The cross context VM structure.
1994	*/
1995	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
1996	{
1997	#ifdef VBOX_STRICT
1998	pgmLock(pVM);
1999
2000	if (pVM->pgm.s.cSharedPages > 0)
2001	{
2002	/*
2003	* Walk the ram ranges.
2004	*/
2005	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2006	{
2007	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2008	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2009
2010	while (iPage-- > 0)
2011	{
2012	PPGMPAGE pPage = &pRam->aPages[iPage];
2013	if (PGM_PAGE_IS_SHARED(pPage))
2014	{
2015	uint32_t u32Checksum = pPage->s.u2Unused0/* \| ((uint32_t)pPage->s.u2Unused1 << 8)*/;
2016	if (!u32Checksum)
2017	{
2018	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2019	void const *pvPage;
2020	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
2021	if (RT_SUCCESS(rc))
2022	{
2023	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
2024	# if 0
2025	AssertMsg((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
2026	# else
2027	if ((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum)
2028	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
2029	else
2030	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
2031	# endif
2032	}
2033	else
2034	AssertRC(rc);
2035	}
2036	}
2037
2038	} /* for each page */
2039
2040	} /* for each ram range */
2041	}
2042
2043	pgmUnlock(pVM);
2044	#endif /* VBOX_STRICT */
2045	NOREF(pVM);
2046	}
2047
2048
2049	/**
2050	* Resets the physical memory state.
2051	*
2052	* ASSUMES that the caller owns the PGM lock.
2053	*
2054	* @returns VBox status code.
2055	* @param pVM The cross context VM structure.
2056	*/
2057	int pgmR3PhysRamReset(PVM pVM)
2058	{
2059	PGM_LOCK_ASSERT_OWNER(pVM);
2060
2061	/* Reset the memory balloon. */
2062	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2063	AssertRC(rc);
2064
2065	#ifdef VBOX_WITH_PAGE_SHARING
2066	/* Clear all registered shared modules. */
2067	pgmR3PhysAssertSharedPageChecksums(pVM);
2068	rc = GMMR3ResetSharedModules(pVM);
2069	AssertRC(rc);
2070	#endif
2071	/* Reset counters. */
2072	pVM->pgm.s.cReusedSharedPages = 0;
2073	pVM->pgm.s.cBalloonedPages = 0;
2074
2075	return VINF_SUCCESS;
2076	}
2077
2078
2079	/**
2080	* Resets (zeros) the RAM after all devices and components have been reset.
2081	*
2082	* ASSUMES that the caller owns the PGM lock.
2083	*
2084	* @returns VBox status code.
2085	* @param pVM The cross context VM structure.
2086	*/
2087	int pgmR3PhysRamZeroAll(PVM pVM)
2088	{
2089	PGM_LOCK_ASSERT_OWNER(pVM);
2090
2091	/*
2092	* We batch up pages that should be freed instead of calling GMM for
2093	* each and every one of them.
2094	*/
2095	uint32_t cPendingPages = 0;
2096	PGMMFREEPAGESREQ pReq;
2097	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2098	AssertLogRelRCReturn(rc, rc);
2099
2100	/*
2101	* Walk the ram ranges.
2102	*/
2103	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2104	{
2105	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2106	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2107
2108	if ( !pVM->pgm.s.fRamPreAlloc
2109	&& pVM->pgm.s.fZeroRamPagesOnReset)
2110	{
2111	/* Replace all RAM pages by ZERO pages. */
2112	while (iPage-- > 0)
2113	{
2114	PPGMPAGE pPage = &pRam->aPages[iPage];
2115	switch (PGM_PAGE_GET_TYPE(pPage))
2116	{
2117	case PGMPAGETYPE_RAM:
2118	/* Do not replace pages part of a 2 MB continuous range
2119	with zero pages, but zero them instead. */
2120	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
2121	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2122	{
2123	void *pvPage;
2124	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2125	AssertLogRelRCReturn(rc, rc);
2126	ASMMemZeroPage(pvPage);
2127	}
2128	else if (PGM_PAGE_IS_BALLOONED(pPage))
2129	{
2130	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2131	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2132	}
2133	else if (!PGM_PAGE_IS_ZERO(pPage))
2134	{
2135	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2136	PGMPAGETYPE_RAM);
2137	AssertLogRelRCReturn(rc, rc);
2138	}
2139	break;
2140
2141	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2142	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2143	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2144	true /fDoAccounting/);
2145	break;
2146
2147	case PGMPAGETYPE_MMIO2:
2148	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2149	case PGMPAGETYPE_ROM:
2150	case PGMPAGETYPE_MMIO:
2151	break;
2152	default:
2153	AssertFailed();
2154	}
2155	} /* for each page */
2156	}
2157	else
2158	{
2159	/* Zero the memory. */
2160	while (iPage-- > 0)
2161	{
2162	PPGMPAGE pPage = &pRam->aPages[iPage];
2163	switch (PGM_PAGE_GET_TYPE(pPage))
2164	{
2165	case PGMPAGETYPE_RAM:
2166	switch (PGM_PAGE_GET_STATE(pPage))
2167	{
2168	case PGM_PAGE_STATE_ZERO:
2169	break;
2170
2171	case PGM_PAGE_STATE_BALLOONED:
2172	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2173	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2174	break;
2175
2176	case PGM_PAGE_STATE_SHARED:
2177	case PGM_PAGE_STATE_WRITE_MONITORED:
2178	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2179	AssertLogRelRCReturn(rc, rc);
2180	RT_FALL_THRU();
2181
2182	case PGM_PAGE_STATE_ALLOCATED:
2183	if (pVM->pgm.s.fZeroRamPagesOnReset)
2184	{
2185	void *pvPage;
2186	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2187	AssertLogRelRCReturn(rc, rc);
2188	ASMMemZeroPage(pvPage);
2189	}
2190	break;
2191	}
2192	break;
2193
2194	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2195	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2196	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2197	true /fDoAccounting/);
2198	break;
2199
2200	case PGMPAGETYPE_MMIO2:
2201	case PGMPAGETYPE_ROM_SHADOW:
2202	case PGMPAGETYPE_ROM:
2203	case PGMPAGETYPE_MMIO:
2204	break;
2205	default:
2206	AssertFailed();
2207
2208	}
2209	} /* for each page */
2210	}
2211
2212	}
2213
2214	/*
2215	* Finish off any pages pending freeing.
2216	*/
2217	if (cPendingPages)
2218	{
2219	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2220	AssertLogRelRCReturn(rc, rc);
2221	}
2222	GMMR3FreePagesCleanup(pReq);
2223	return VINF_SUCCESS;
2224	}
2225
2226
2227	/**
2228	* Frees all RAM during VM termination
2229	*
2230	* ASSUMES that the caller owns the PGM lock.
2231	*
2232	* @returns VBox status code.
2233	* @param pVM The cross context VM structure.
2234	*/
2235	int pgmR3PhysRamTerm(PVM pVM)
2236	{
2237	PGM_LOCK_ASSERT_OWNER(pVM);
2238
2239	/* Reset the memory balloon. */
2240	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2241	AssertRC(rc);
2242
2243	#ifdef VBOX_WITH_PAGE_SHARING
2244	/*
2245	* Clear all registered shared modules.
2246	*/
2247	pgmR3PhysAssertSharedPageChecksums(pVM);
2248	rc = GMMR3ResetSharedModules(pVM);
2249	AssertRC(rc);
2250
2251	/*
2252	* Flush the handy pages updates to make sure no shared pages are hiding
2253	* in there. (No unlikely if the VM shuts down, apparently.)
2254	*/
2255	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2256	#endif
2257
2258	/*
2259	* We batch up pages that should be freed instead of calling GMM for
2260	* each and every one of them.
2261	*/
2262	uint32_t cPendingPages = 0;
2263	PGMMFREEPAGESREQ pReq;
2264	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2265	AssertLogRelRCReturn(rc, rc);
2266
2267	/*
2268	* Walk the ram ranges.
2269	*/
2270	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2271	{
2272	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2273	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2274
2275	while (iPage-- > 0)
2276	{
2277	PPGMPAGE pPage = &pRam->aPages[iPage];
2278	switch (PGM_PAGE_GET_TYPE(pPage))
2279	{
2280	case PGMPAGETYPE_RAM:
2281	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2282	/** @todo change this to explicitly free private pages here. */
2283	if (PGM_PAGE_IS_SHARED(pPage))
2284	{
2285	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2286	PGMPAGETYPE_RAM);
2287	AssertLogRelRCReturn(rc, rc);
2288	}
2289	break;
2290
2291	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2292	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2293	case PGMPAGETYPE_MMIO2:
2294	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2295	case PGMPAGETYPE_ROM:
2296	case PGMPAGETYPE_MMIO:
2297	break;
2298	default:
2299	AssertFailed();
2300	}
2301	} /* for each page */
2302	}
2303
2304	/*
2305	* Finish off any pages pending freeing.
2306	*/
2307	if (cPendingPages)
2308	{
2309	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2310	AssertLogRelRCReturn(rc, rc);
2311	}
2312	GMMR3FreePagesCleanup(pReq);
2313	return VINF_SUCCESS;
2314	}
2315
2316
2317	/**
2318	* This is the interface IOM is using to register an MMIO region.
2319	*
2320	* It will check for conflicts and ensure that a RAM range structure
2321	* is present before calling the PGMR3HandlerPhysicalRegister API to
2322	* register the callbacks.
2323	*
2324	* @returns VBox status code.
2325	*
2326	* @param pVM The cross context VM structure.
2327	* @param GCPhys The start of the MMIO region.
2328	* @param cb The size of the MMIO region.
2329	* @param hType The physical access handler type registration.
2330	* @param pvUserR3 The user argument for R3.
2331	* @param pvUserR0 The user argument for R0.
2332	* @param pvUserRC The user argument for RC.
2333	* @param pszDesc The description of the MMIO region.
2334	*/
2335	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2336	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2337	{
2338	/*
2339	* Assert on some assumption.
2340	*/
2341	VM_ASSERT_EMT(pVM);
2342	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2343	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2344	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2345	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2346	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2347
2348	int rc = pgmLock(pVM);
2349	AssertRCReturn(rc, rc);
2350
2351	/*
2352	* Make sure there's a RAM range structure for the region.
2353	*/
2354	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2355	bool fRamExists = false;
2356	PPGMRAMRANGE pRamPrev = NULL;
2357	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2358	while (pRam && GCPhysLast >= pRam->GCPhys)
2359	{
2360	if ( GCPhysLast >= pRam->GCPhys
2361	&& GCPhys <= pRam->GCPhysLast)
2362	{
2363	/* Simplification: all within the same range. */
2364	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2365	&& GCPhysLast <= pRam->GCPhysLast,
2366	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2367	GCPhys, GCPhysLast, pszDesc,
2368	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2369	pgmUnlock(pVM),
2370	VERR_PGM_RAM_CONFLICT);
2371
2372	/* Check that it's all RAM or MMIO pages. */
2373	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2374	uint32_t cLeft = cb >> PAGE_SHIFT;
2375	while (cLeft-- > 0)
2376	{
2377	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2378	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2379	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2380	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2381	pgmUnlock(pVM),
2382	VERR_PGM_RAM_CONFLICT);
2383	pPage++;
2384	}
2385
2386	/* Looks good. */
2387	fRamExists = true;
2388	break;
2389	}
2390
2391	/* next */
2392	pRamPrev = pRam;
2393	pRam = pRam->pNextR3;
2394	}
2395	PPGMRAMRANGE pNew;
2396	if (fRamExists)
2397	{
2398	pNew = NULL;
2399
2400	/*
2401	* Make all the pages in the range MMIO/ZERO pages, freeing any
2402	* RAM pages currently mapped here. This might not be 100% correct
2403	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2404	*/
2405	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
2406	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
2407
2408	/* Force a PGM pool flush as guest ram references have been changed. */
2409	/** @todo not entirely SMP safe; assuming for now the guest takes
2410	* care of this internally (not touch mapped mmio while changing the
2411	* mapping). */
2412	PVMCPU pVCpu = VMMGetCpu(pVM);
2413	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2414	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2415	}
2416	else
2417	{
2418
2419	/*
2420	* No RAM range, insert an ad hoc one.
2421	*
2422	* Note that we don't have to tell REM about this range because
2423	* PGMHandlerPhysicalRegisterEx will do that for us.
2424	*/
2425	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2426
2427	const uint32_t cPages = cb >> PAGE_SHIFT;
2428	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
2429	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2430	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), pgmUnlock(pVM), rc);
2431
2432	/* Initialize the range. */
2433	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2434	pNew->GCPhys = GCPhys;
2435	pNew->GCPhysLast = GCPhysLast;
2436	pNew->cb = cb;
2437	pNew->pszDesc = pszDesc;
2438	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2439	pNew->pvR3 = NULL;
2440	pNew->paLSPages = NULL;
2441
2442	uint32_t iPage = cPages;
2443	while (iPage-- > 0)
2444	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2445	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2446
2447	/* update the page count stats. */
2448	pVM->pgm.s.cPureMmioPages += cPages;
2449	pVM->pgm.s.cAllPages += cPages;
2450
2451	/* link it */
2452	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2453	}
2454
2455	/*
2456	* Register the access handler.
2457	*/
2458	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2459	if ( RT_FAILURE(rc)
2460	&& !fRamExists)
2461	{
2462	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2463	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2464
2465	/* remove the ad hoc range. */
2466	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2467	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2468	MMHyperFree(pVM, pRam);
2469	}
2470	pgmPhysInvalidatePageMapTLB(pVM);
2471
2472	pgmUnlock(pVM);
2473	return rc;
2474	}
2475
2476
2477	/**
2478	* This is the interface IOM is using to register an MMIO region.
2479	*
2480	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2481	* any ad hoc PGMRAMRANGE left behind.
2482	*
2483	* @returns VBox status code.
2484	* @param pVM The cross context VM structure.
2485	* @param GCPhys The start of the MMIO region.
2486	* @param cb The size of the MMIO region.
2487	*/
2488	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2489	{
2490	VM_ASSERT_EMT(pVM);
2491
2492	int rc = pgmLock(pVM);
2493	AssertRCReturn(rc, rc);
2494
2495	/*
2496	* First deregister the handler, then check if we should remove the ram range.
2497	*/
2498	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2499	if (RT_SUCCESS(rc))
2500	{
2501	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2502	PPGMRAMRANGE pRamPrev = NULL;
2503	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2504	while (pRam && GCPhysLast >= pRam->GCPhys)
2505	{
2506	/** @todo We're being a bit too careful here. rewrite. */
2507	if ( GCPhysLast == pRam->GCPhysLast
2508	&& GCPhys == pRam->GCPhys)
2509	{
2510	Assert(pRam->cb == cb);
2511
2512	/*
2513	* See if all the pages are dead MMIO pages.
2514	*/
2515	uint32_t const cPages = cb >> PAGE_SHIFT;
2516	bool fAllMMIO = true;
2517	uint32_t iPage = 0;
2518	uint32_t cLeft = cPages;
2519	while (cLeft-- > 0)
2520	{
2521	PPGMPAGE pPage = &pRam->aPages[iPage];
2522	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2523	/\|\| not-out-of-action later /)
2524	{
2525	fAllMMIO = false;
2526	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2527	break;
2528	}
2529	Assert( PGM_PAGE_IS_ZERO(pPage)
2530	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2531	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2532	pPage++;
2533	}
2534	if (fAllMMIO)
2535	{
2536	/*
2537	* Ad-hoc range, unlink and free it.
2538	*/
2539	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2540	GCPhys, GCPhysLast, pRam->pszDesc));
2541
2542	pVM->pgm.s.cAllPages -= cPages;
2543	pVM->pgm.s.cPureMmioPages -= cPages;
2544
2545	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2546	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2547	MMHyperFree(pVM, pRam);
2548	break;
2549	}
2550	}
2551
2552	/*
2553	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2554	*/
2555	if ( GCPhysLast >= pRam->GCPhys
2556	&& GCPhys <= pRam->GCPhysLast)
2557	{
2558	Assert(GCPhys >= pRam->GCPhys);
2559	Assert(GCPhysLast <= pRam->GCPhysLast);
2560
2561	/*
2562	* Turn the pages back into RAM pages.
2563	*/
2564	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2565	uint32_t cLeft = cb >> PAGE_SHIFT;
2566	while (cLeft--)
2567	{
2568	PPGMPAGE pPage = &pRam->aPages[iPage];
2569	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2570	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2571	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2572	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2573	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2574	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2575	}
2576	break;
2577	}
2578
2579	/* next */
2580	pRamPrev = pRam;
2581	pRam = pRam->pNextR3;
2582	}
2583	}
2584
2585	/* Force a PGM pool flush as guest ram references have been changed. */
2586	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2587	* this internally (not touch mapped mmio while changing the mapping). */
2588	PVMCPU pVCpu = VMMGetCpu(pVM);
2589	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2590	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2591
2592	pgmPhysInvalidatePageMapTLB(pVM);
2593	pgmPhysInvalidRamRangeTlbs(pVM);
2594	pgmUnlock(pVM);
2595	return rc;
2596	}
2597
2598
2599	/**
2600	* Locate a MMIO2 range.
2601	*
2602	* @returns Pointer to the MMIO2 range.
2603	* @param pVM The cross context VM structure.
2604	* @param pDevIns The device instance owning the region.
2605	* @param iSubDev The sub-device number.
2606	* @param iRegion The region.
2607	*/
2608	DECLINLINE(PPGMREGMMIORANGE) pgmR3PhysMMIOExFind(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion)
2609	{
2610	/*
2611	* Search the list. There shouldn't be many entries.
2612	*/
2613	/** @todo Optimize this lookup! There may now be many entries and it'll
2614	* become really slow when doing MMR3HyperMapMMIO2 and similar. */
2615	for (PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2616	if ( pCur->pDevInsR3 == pDevIns
2617	&& pCur->iRegion == iRegion
2618	&& pCur->iSubDev == iSubDev)
2619	return pCur;
2620	return NULL;
2621	}
2622
2623
2624	#ifndef PGM_WITHOUT_MAPPINGS
2625	/**
2626	* @callback_method_impl{FNPGMRELOCATE, Relocate a floating MMIO/MMIO2 range.}
2627	* @sa pgmR3PhysRamRangeRelocate
2628	*/
2629	static DECLCALLBACK(bool) pgmR3PhysMMIOExRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew,
2630	PGMRELOCATECALL enmMode, void *pvUser)
2631	{
2632	PPGMREGMMIORANGE pMmio = (PPGMREGMMIORANGE)pvUser;
2633	Assert(pMmio->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
2634	Assert(pMmio->RamRange.pSelfRC == GCPtrOld + PAGE_SIZE + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange)); RT_NOREF_PV(GCPtrOld);
2635
2636	switch (enmMode)
2637	{
2638	case PGMRELOCATECALL_SUGGEST:
2639	return true;
2640
2641	case PGMRELOCATECALL_RELOCATE:
2642	{
2643	/*
2644	* Update myself, then relink all the ranges and flush the RC TLB.
2645	*/
2646	pgmLock(pVM);
2647
2648	pMmio->RamRange.pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange));
2649
2650	pgmR3PhysRelinkRamRanges(pVM);
2651	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2652	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2653
2654	pgmUnlock(pVM);
2655	return true;
2656	}
2657
2658	default:
2659	AssertFailedReturn(false);
2660	}
2661	}
2662	#endif /* !PGM_WITHOUT_MAPPINGS */
2663
2664
2665	/**
2666	* Calculates the number of chunks
2667	*
2668	* @returns Number of registration chunk needed.
2669	* @param pVM The cross context VM structure.
2670	* @param cb The size of the MMIO/MMIO2 range.
2671	* @param pcPagesPerChunk Where to return the number of pages tracked by each
2672	* chunk. Optional.
2673	* @param pcbChunk Where to return the guest mapping size for a chunk.
2674	*/
2675	static uint16_t pgmR3PhysMMIOExCalcChunkCount(PVM pVM, RTGCPHYS cb, uint32_t pcPagesPerChunk, uint32_t pcbChunk)
2676	{
2677	RT_NOREF_PV(pVM); /* without raw mode */
2678
2679	/*
2680	* This is the same calculation as PGMR3PhysRegisterRam does, except we'll be
2681	* needing a few bytes extra the PGMREGMMIORANGE structure.
2682	*
2683	* Note! In additions, we've got a 24 bit sub-page range for MMIO2 ranges, leaving
2684	* us with an absolute maximum of 16777215 pages per chunk (close to 64 GB).
2685	*/
2686	uint32_t cbChunk = 16U*_1M;
2687	uint32_t cPagesPerChunk = 1048048; /* max ~1048059 */
2688	AssertCompile(sizeof(PGMREGMMIORANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
2689	AssertRelease(cPagesPerChunk <= PGM_MMIO2_MAX_PAGE_COUNT); /* See above note. */
2690	AssertRelease(RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
2691	if (pcbChunk)
2692	*pcbChunk = cbChunk;
2693	if (pcPagesPerChunk)
2694	*pcPagesPerChunk = cPagesPerChunk;
2695
2696	/* Calc the number of chunks we need. */
2697	RTGCPHYS const cPages = cb >> X86_PAGE_SHIFT;
2698	uint16_t cChunks = (uint16_t)((cPages + cPagesPerChunk - 1) / cPagesPerChunk);
2699	AssertRelease((RTGCPHYS)cChunks * cPagesPerChunk >= cPages);
2700	return cChunks;
2701	}
2702
2703
2704	/**
2705	* Worker for PGMR3PhysMMIOExPreRegister & PGMR3PhysMMIO2Register that allocates
2706	* and the PGMREGMMIORANGE structures and does basic initialization.
2707	*
2708	* Caller must set type specfic members and initialize the PGMPAGE structures.
2709	*
2710	* @returns VBox status code.
2711	* @param pVM The cross context VM structure.
2712	* @param pDevIns The device instance owning the region.
2713	* @param iSubDev The sub-device number (internal PCI config number).
2714	* @param iRegion The region number. If the MMIO2 memory is a PCI
2715	* I/O region this number has to be the number of that
2716	* region. Otherwise it can be any number safe
2717	* UINT8_MAX.
2718	* @param cb The size of the region. Must be page aligned.
2719	* @param pszDesc The description.
2720	* @param ppHeadRet Where to return the pointer to the first
2721	* registration chunk.
2722	*
2723	* @thread EMT
2724	*/
2725	static int pgmR3PhysMMIOExCreate(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2726	const char pszDesc, PPGMREGMMIORANGE ppHeadRet)
2727	{
2728	/*
2729	* Figure out how many chunks we need and of which size.
2730	*/
2731	uint32_t cPagesPerChunk;
2732	uint16_t cChunks = pgmR3PhysMMIOExCalcChunkCount(pVM, cb, &cPagesPerChunk, NULL);
2733	AssertReturn(cChunks, VERR_PGM_PHYS_MMIO_EX_IPE);
2734
2735	/*
2736	* Allocate the chunks.
2737	*/
2738	PPGMREGMMIORANGE *ppNext = ppHeadRet;
2739	*ppNext = NULL;
2740
2741	int rc = VINF_SUCCESS;
2742	uint32_t cPagesLeft = cb >> X86_PAGE_SHIFT;
2743	for (uint16_t iChunk = 0; iChunk < cChunks && RT_SUCCESS(rc); iChunk++)
2744	{
2745	/*
2746	* We currently do a single RAM range for the whole thing. This will
2747	* probably have to change once someone needs really large MMIO regions,
2748	* as we will be running into SUPR3PageAllocEx limitations and such.
2749	*/
2750	const uint32_t cPagesTrackedByChunk = RT_MIN(cPagesLeft, cPagesPerChunk);
2751	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPagesTrackedByChunk]);
2752	PPGMREGMMIORANGE pNew = NULL;
2753	if ( iChunk + 1 < cChunks
2754	\|\| cbRange >= _1M)
2755	{
2756	/*
2757	* Allocate memory for the registration structure.
2758	*/
2759	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2760	size_t const cbChunk = (1 + cChunkPages + 1) << PAGE_SHIFT;
2761	AssertLogRelBreakStmt(cbChunk == (uint32_t)cbChunk, rc = VERR_OUT_OF_RANGE);
2762	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
2763	AssertBreakStmt(paChunkPages, rc = VERR_NO_TMP_MEMORY);
2764	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
2765	void *pvChunk = NULL;
2766	rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
2767	AssertLogRelMsgRCBreakStmt(rc, ("rc=%Rrc, cChunkPages=%#zx\n", rc, cChunkPages), RTMemTmpFree(paChunkPages));
2768
2769	Assert(R0PtrChunk != NIL_RTR0PTR);
2770	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
2771
2772	pNew = (PPGMREGMMIORANGE)pvChunk;
2773	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_FLOATING;
2774	pNew->RamRange.pSelfR0 = R0PtrChunk + RT_UOFFSETOF(PGMREGMMIORANGE, RamRange);
2775
2776	RTMemTmpFree(paChunkPages);
2777	}
2778	/*
2779	* Not so big, do a one time hyper allocation.
2780	*/
2781	else
2782	{
2783	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2784	AssertLogRelMsgRCBreak(rc, ("cbRange=%zu\n", cbRange));
2785
2786	/*
2787	* Initialize allocation specific items.
2788	*/
2789	//pNew->RamRange.fFlags = 0;
2790	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2791	}
2792
2793	/*
2794	* Initialize the registration structure (caller does specific bits).
2795	*/
2796	pNew->pDevInsR3 = pDevIns;
2797	//pNew->pvR3 = NULL;
2798	//pNew->pNext = NULL;
2799	//pNew->fFlags = 0;
2800	if (iChunk == 0)
2801	pNew->fFlags \|= PGMREGMMIORANGE_F_FIRST_CHUNK;
2802	if (iChunk + 1 == cChunks)
2803	pNew->fFlags \|= PGMREGMMIORANGE_F_LAST_CHUNK;
2804	pNew->iSubDev = iSubDev;
2805	pNew->iRegion = iRegion;
2806	pNew->idSavedState = UINT8_MAX;
2807	pNew->idMmio2 = UINT8_MAX;
2808	//pNew->pPhysHandlerR3 = NULL;
2809	//pNew->paLSPages = NULL;
2810	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2811	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2812	pNew->RamRange.pszDesc = pszDesc;
2813	pNew->RamRange.cb = pNew->cbReal = (RTGCPHYS)cPagesTrackedByChunk << X86_PAGE_SHIFT;
2814	pNew->RamRange.fFlags \|= PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX;
2815	//pNew->RamRange.pvR3 = NULL;
2816	//pNew->RamRange.paLSPages = NULL;
2817
2818	*ppNext = pNew;
2819	ASMCompilerBarrier();
2820	cPagesLeft -= cPagesTrackedByChunk;
2821	ppNext = &pNew->pNextR3;
2822	}
2823	Assert(cPagesLeft == 0);
2824
2825	if (RT_SUCCESS(rc))
2826	{
2827	Assert((*ppHeadRet)->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
2828	return VINF_SUCCESS;
2829	}
2830
2831	/*
2832	* Free floating ranges.
2833	*/
2834	while (*ppHeadRet)
2835	{
2836	PPGMREGMMIORANGE pFree = *ppHeadRet;
2837	*ppHeadRet = pFree->pNextR3;
2838
2839	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
2840	{
2841	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
2842	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2843	SUPR3PageFreeEx(pFree, cChunkPages);
2844	}
2845	}
2846
2847	return rc;
2848	}
2849
2850
2851	/**
2852	* Common worker PGMR3PhysMMIOExPreRegister & PGMR3PhysMMIO2Register that links
2853	* a complete registration entry into the lists and lookup tables.
2854	*
2855	* @param pVM The cross context VM structure.
2856	* @param pNew The new MMIO / MMIO2 registration to link.
2857	*/
2858	static void pgmR3PhysMMIOExLink(PVM pVM, PPGMREGMMIORANGE pNew)
2859	{
2860	/*
2861	* Link it into the list (order doesn't matter, so insert it at the head).
2862	*
2863	* Note! The range we're link may consist of multiple chunks, so we have to
2864	* find the last one.
2865	*/
2866	PPGMREGMMIORANGE pLast = pNew;
2867	for (pLast = pNew; ; pLast = pLast->pNextR3)
2868	{
2869	if (pLast->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
2870	break;
2871	Assert(pLast->pNextR3);
2872	Assert(pLast->pNextR3->pDevInsR3 == pNew->pDevInsR3);
2873	Assert(pLast->pNextR3->iSubDev == pNew->iSubDev);
2874	Assert(pLast->pNextR3->iRegion == pNew->iRegion);
2875	Assert((pLast->pNextR3->fFlags & PGMREGMMIORANGE_F_MMIO2) == (pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
2876	Assert(pLast->pNextR3->idMmio2 == (pLast->fFlags & PGMREGMMIORANGE_F_MMIO2 ? pNew->idMmio2 + 1 : UINT8_MAX));
2877	}
2878
2879	pgmLock(pVM);
2880
2881	/* Link in the chain of ranges at the head of the list. */
2882	pLast->pNextR3 = pVM->pgm.s.pRegMmioRangesR3;
2883	pVM->pgm.s.pRegMmioRangesR3 = pNew;
2884
2885	/* If MMIO, insert the MMIO2 range/page IDs. */
2886	uint8_t idMmio2 = pNew->idMmio2;
2887	if (idMmio2 != UINT8_MAX)
2888	{
2889	for (;;)
2890	{
2891	Assert(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2);
2892	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
2893	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
2894	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
2895	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = pNew->RamRange.pSelfR0 - RT_UOFFSETOF(PGMREGMMIORANGE, RamRange);
2896	if (pNew->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
2897	break;
2898	pNew = pNew->pNextR3;
2899	}
2900	}
2901	else
2902	Assert(!(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
2903
2904	pgmPhysInvalidatePageMapTLB(pVM);
2905	pgmUnlock(pVM);
2906	}
2907
2908
2909	/**
2910	* Allocate and pre-register an MMIO region.
2911	*
2912	* This is currently the way to deal with large MMIO regions. It may in the
2913	* future be extended to be the way we deal with all MMIO regions, but that
2914	* means we'll have to do something about the simple list based approach we take
2915	* to tracking the registrations.
2916	*
2917	* @returns VBox status code.
2918	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2919	* memory.
2920	* @retval VERR_ALREADY_EXISTS if the region already exists.
2921	*
2922	* @param pVM The cross context VM structure.
2923	* @param pDevIns The device instance owning the region.
2924	* @param iSubDev The sub-device number.
2925	* @param iRegion The region number. If the MMIO2 memory is a PCI
2926	* I/O region this number has to be the number of that
2927	* region. Otherwise it can be any number safe
2928	* UINT8_MAX.
2929	* @param cbRegion The size of the region. Must be page aligned.
2930	* @param hType The physical handler callback type.
2931	* @param pvUserR3 User parameter for ring-3 context callbacks.
2932	* @param pvUserR0 User parameter for ring-0 context callbacks.
2933	* @param pvUserRC User parameter for raw-mode context callbacks.
2934	* @param pszDesc The description.
2935	*
2936	* @thread EMT
2937	*
2938	* @sa PGMR3PhysMMIORegister, PGMR3PhysMMIO2Register,
2939	* PGMR3PhysMMIOExMap, PGMR3PhysMMIOExUnmap, PGMR3PhysMMIOExDeregister.
2940	*/
2941	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion,
2942	PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
2943	const char *pszDesc)
2944	{
2945	/*
2946	* Validate input.
2947	*/
2948	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2949	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2950	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
2951	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2952	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2953	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2954	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion) == NULL, VERR_ALREADY_EXISTS);
2955	AssertReturn(!(cbRegion & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2956	AssertReturn(cbRegion, VERR_INVALID_PARAMETER);
2957
2958	const uint32_t cPages = cbRegion >> PAGE_SHIFT;
2959	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cbRegion, VERR_INVALID_PARAMETER);
2960	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
2961
2962	/*
2963	* For the 2nd+ instance, mangle the description string so it's unique.
2964	*/
2965	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
2966	{
2967	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
2968	if (!pszDesc)
2969	return VERR_NO_MEMORY;
2970	}
2971
2972	/*
2973	* Register the MMIO callbacks.
2974	*/
2975	PPGMPHYSHANDLER pPhysHandler;
2976	int rc = pgmHandlerPhysicalExCreate(pVM, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc, &pPhysHandler);
2977	if (RT_SUCCESS(rc))
2978	{
2979	/*
2980	* Create the registered MMIO range record for it.
2981	*/
2982	PPGMREGMMIORANGE pNew;
2983	rc = pgmR3PhysMMIOExCreate(pVM, pDevIns, iSubDev, iRegion, cbRegion, pszDesc, &pNew);
2984	if (RT_SUCCESS(rc))
2985	{
2986	Assert(!(pNew->fFlags & PGMREGMMIORANGE_F_MMIO2));
2987
2988	/*
2989	* Intialize the page structures and set up physical handlers (one for each chunk).
2990	*/
2991	for (PPGMREGMMIORANGE pCur = pNew; pCur != NULL && RT_SUCCESS(rc); pCur = pCur->pNextR3)
2992	{
2993	if (pCur == pNew)
2994	pCur->pPhysHandlerR3 = pPhysHandler;
2995	else
2996	rc = pgmHandlerPhysicalExDup(pVM, pPhysHandler, &pCur->pPhysHandlerR3);
2997
2998	uint32_t iPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
2999	while (iPage-- > 0)
3000	PGM_PAGE_INIT_ZERO(&pCur->RamRange.aPages[iPage], pVM, PGMPAGETYPE_MMIO);
3001	}
3002	if (RT_SUCCESS(rc))
3003	{
3004	/*
3005	* Update the page count stats, link the registration and we're done.
3006	*/
3007	pVM->pgm.s.cAllPages += cPages;
3008	pVM->pgm.s.cPureMmioPages += cPages;
3009
3010	pgmR3PhysMMIOExLink(pVM, pNew);
3011	return VINF_SUCCESS;
3012	}
3013
3014	/*
3015	* Clean up in case we're out of memory for extra access handlers.
3016	*/
3017	while (pNew != NULL)
3018	{
3019	PPGMREGMMIORANGE pFree = pNew;
3020	pNew = pFree->pNextR3;
3021
3022	if (pFree->pPhysHandlerR3)
3023	{
3024	pgmHandlerPhysicalExDestroy(pVM, pFree->pPhysHandlerR3);
3025	pFree->pPhysHandlerR3 = NULL;
3026	}
3027
3028	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3029	{
3030	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
3031	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3032	SUPR3PageFreeEx(pFree, cChunkPages);
3033	}
3034	}
3035	}
3036	else
3037	pgmHandlerPhysicalExDestroy(pVM, pPhysHandler);
3038	}
3039	return rc;
3040	}
3041
3042
3043	/**
3044	* Allocate and register an MMIO2 region.
3045	*
3046	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
3047	* associated with a device. It is also non-shared memory with a permanent
3048	* ring-3 mapping and page backing (presently).
3049	*
3050	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
3051	* the VM, in which case we'll drop the base memory pages. Presently we will
3052	* make no attempt to preserve anything that happens to be present in the base
3053	* memory that is replaced, this is of course incorrect but it's too much
3054	* effort.
3055	*
3056	* @returns VBox status code.
3057	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
3058	* memory.
3059	* @retval VERR_ALREADY_EXISTS if the region already exists.
3060	*
3061	* @param pVM The cross context VM structure.
3062	* @param pDevIns The device instance owning the region.
3063	* @param iSubDev The sub-device number.
3064	* @param iRegion The region number. If the MMIO2 memory is a PCI
3065	* I/O region this number has to be the number of that
3066	* region. Otherwise it can be any number safe
3067	* UINT8_MAX.
3068	* @param cb The size of the region. Must be page aligned.
3069	* @param fFlags Reserved for future use, must be zero.
3070	* @param ppv Where to store the pointer to the ring-3 mapping of
3071	* the memory.
3072	* @param pszDesc The description.
3073	* @thread EMT
3074	*/
3075	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
3076	uint32_t fFlags, void *ppv, const char pszDesc)
3077	{
3078	/*
3079	* Validate input.
3080	*/
3081	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3082	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3083	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3084	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3085	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
3086	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3087	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3088	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion) == NULL, VERR_ALREADY_EXISTS);
3089	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3090	AssertReturn(cb, VERR_INVALID_PARAMETER);
3091	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
3092
3093	const uint32_t cPages = cb >> PAGE_SHIFT;
3094	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
3095	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3096
3097	/*
3098	* For the 2nd+ instance, mangle the description string so it's unique.
3099	*/
3100	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3101	{
3102	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3103	if (!pszDesc)
3104	return VERR_NO_MEMORY;
3105	}
3106
3107	/*
3108	* Allocate an MMIO2 range ID (not freed on failure).
3109	*
3110	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID, so
3111	* the IDs goes from 1 thru PGM_MMIO2_MAX_RANGES.
3112	*/
3113	unsigned cChunks = pgmR3PhysMMIOExCalcChunkCount(pVM, cb, NULL, NULL);
3114	pgmLock(pVM);
3115	uint8_t idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
3116	unsigned cNewMmio2Regions = pVM->pgm.s.cMmio2Regions + cChunks;
3117	if (cNewMmio2Regions > PGM_MMIO2_MAX_RANGES)
3118	{
3119	pgmUnlock(pVM);
3120	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
3121	}
3122	pVM->pgm.s.cMmio2Regions = cNewMmio2Regions;
3123	pgmUnlock(pVM);
3124
3125	/*
3126	* Try reserve and allocate the backing memory first as this is what is
3127	* most likely to fail.
3128	*/
3129	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
3130	if (RT_SUCCESS(rc))
3131	{
3132	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
3133	if (RT_SUCCESS(rc))
3134	{
3135	void *pvPages;
3136	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
3137	if (RT_SUCCESS(rc))
3138	{
3139	memset(pvPages, 0, cPages * PAGE_SIZE);
3140
3141	/*
3142	* Create the registered MMIO range record for it.
3143	*/
3144	PPGMREGMMIORANGE pNew;
3145	rc = pgmR3PhysMMIOExCreate(pVM, pDevIns, iSubDev, iRegion, cb, pszDesc, &pNew);
3146	if (RT_SUCCESS(rc))
3147	{
3148	uint32_t iSrcPage = 0;
3149	uint8_t pbCurPages = (uint8_t )pvPages;
3150	for (PPGMREGMMIORANGE pCur = pNew; pCur; pCur = pCur->pNextR3)
3151	{
3152	pCur->pvR3 = pbCurPages;
3153	pCur->RamRange.pvR3 = pbCurPages;
3154	pCur->idMmio2 = idMmio2;
3155	pCur->fFlags \|= PGMREGMMIORANGE_F_MMIO2;
3156
3157	uint32_t iDstPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3158	while (iDstPage-- > 0)
3159	{
3160	PGM_PAGE_INIT(&pNew->RamRange.aPages[iDstPage],
3161	paPages[iDstPage + iSrcPage].Phys,
3162	PGM_MMIO2_PAGEID_MAKE(idMmio2, iDstPage),
3163	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
3164	}
3165
3166	/* advance. */
3167	iSrcPage += pCur->RamRange.cb >> X86_PAGE_SHIFT;
3168	pbCurPages += pCur->RamRange.cb;
3169	idMmio2++;
3170	}
3171
3172	RTMemTmpFree(paPages);
3173
3174	/*
3175	* Update the page count stats, link the registration and we're done.
3176	*/
3177	pVM->pgm.s.cAllPages += cPages;
3178	pVM->pgm.s.cPrivatePages += cPages;
3179
3180	pgmR3PhysMMIOExLink(pVM, pNew);
3181
3182	*ppv = pvPages;
3183	return VINF_SUCCESS;
3184	}
3185
3186	SUPR3PageFreeEx(pvPages, cPages);
3187	}
3188	}
3189	RTMemTmpFree(paPages);
3190	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
3191	}
3192	if (pDevIns->iInstance > 0)
3193	MMR3HeapFree((void *)pszDesc);
3194	return rc;
3195	}
3196
3197
3198	/**
3199	* Deregisters and frees an MMIO2 region or a pre-registered MMIO region
3200	*
3201	* Any physical (and virtual) access handlers registered for the region must
3202	* be deregistered before calling this function.
3203	*
3204	* @returns VBox status code.
3205	* @param pVM The cross context VM structure.
3206	* @param pDevIns The device instance owning the region.
3207	* @param iSubDev The sub-device number. Pass UINT32_MAX for wildcard
3208	* matching.
3209	* @param iRegion The region. Pass UINT32_MAX for wildcard matching.
3210	*/
3211	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion)
3212	{
3213	/*
3214	* Validate input.
3215	*/
3216	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3217	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3218	AssertReturn(iSubDev <= UINT8_MAX \|\| iSubDev == UINT32_MAX, VERR_INVALID_PARAMETER);
3219	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
3220
3221	/*
3222	* The loop here scanning all registrations will make sure that multi-chunk ranges
3223	* get properly deregistered, though it's original purpose was the wildcard iRegion.
3224	*/
3225	pgmLock(pVM);
3226	int rc = VINF_SUCCESS;
3227	unsigned cFound = 0;
3228	PPGMREGMMIORANGE pPrev = NULL;
3229	PPGMREGMMIORANGE pCur = pVM->pgm.s.pRegMmioRangesR3;
3230	while (pCur)
3231	{
3232	if ( pCur->pDevInsR3 == pDevIns
3233	&& ( iRegion == UINT32_MAX
3234	\|\| pCur->iRegion == iRegion)
3235	&& ( iSubDev == UINT32_MAX
3236	\|\| pCur->iSubDev == iSubDev) )
3237	{
3238	cFound++;
3239
3240	/*
3241	* Unmap it if it's mapped.
3242	*/
3243	if (pCur->fFlags & PGMREGMMIORANGE_F_MAPPED)
3244	{
3245	int rc2 = PGMR3PhysMMIOExUnmap(pVM, pCur->pDevInsR3, pCur->iSubDev, pCur->iRegion, pCur->RamRange.GCPhys);
3246	AssertRC(rc2);
3247	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3248	rc = rc2;
3249	}
3250
3251	/*
3252	* Must tell IOM about MMIO (first one only).
3253	*/
3254	if ((pCur->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK)) == PGMREGMMIORANGE_F_MMIO2)
3255	IOMR3MmioExNotifyDeregistered(pVM, pCur->pPhysHandlerR3->pvUserR3);
3256
3257	/*
3258	* Unlink it
3259	*/
3260	PPGMREGMMIORANGE pNext = pCur->pNextR3;
3261	if (pPrev)
3262	pPrev->pNextR3 = pNext;
3263	else
3264	pVM->pgm.s.pRegMmioRangesR3 = pNext;
3265	pCur->pNextR3 = NULL;
3266
3267	uint8_t idMmio2 = pCur->idMmio2;
3268	if (idMmio2 != UINT8_MAX)
3269	{
3270	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
3271	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
3272	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
3273	}
3274
3275	/*
3276	* Free the memory.
3277	*/
3278	uint32_t const cPages = pCur->cbReal >> PAGE_SHIFT;
3279	if (pCur->fFlags & PGMREGMMIORANGE_F_MMIO2)
3280	{
3281	int rc2 = SUPR3PageFreeEx(pCur->pvR3, cPages);
3282	AssertRC(rc2);
3283	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3284	rc = rc2;
3285
3286	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
3287	AssertRC(rc2);
3288	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3289	rc = rc2;
3290	}
3291
3292	/* we're leaking hyper memory here if done at runtime. */
3293	#ifdef VBOX_STRICT
3294	VMSTATE const enmState = VMR3GetState(pVM);
3295	AssertMsg( enmState == VMSTATE_POWERING_OFF
3296	\|\| enmState == VMSTATE_POWERING_OFF_LS
3297	\|\| enmState == VMSTATE_OFF
3298	\|\| enmState == VMSTATE_OFF_LS
3299	\|\| enmState == VMSTATE_DESTROYING
3300	\|\| enmState == VMSTATE_TERMINATED
3301	\|\| enmState == VMSTATE_CREATING
3302	, ("%s\n", VMR3GetStateName(enmState)));
3303	#endif
3304
3305	const bool fIsMmio2 = RT_BOOL(pCur->fFlags & PGMREGMMIORANGE_F_MMIO2);
3306	if (pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3307	{
3308	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIORANGE, RamRange.aPages[cPages]);
3309	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3310	SUPR3PageFreeEx(pCur, cChunkPages);
3311	}
3312	/*else
3313	{
3314	rc = MMHyperFree(pVM, pCur); - does not work, see the alloc call.
3315	AssertRCReturn(rc, rc);
3316	} */
3317
3318
3319	/* update page count stats */
3320	pVM->pgm.s.cAllPages -= cPages;
3321	if (fIsMmio2)
3322	pVM->pgm.s.cPrivatePages -= cPages;
3323	else
3324	pVM->pgm.s.cPureMmioPages -= cPages;
3325
3326	/* next */
3327	pCur = pNext;
3328	}
3329	else
3330	{
3331	pPrev = pCur;
3332	pCur = pCur->pNextR3;
3333	}
3334	}
3335	pgmPhysInvalidatePageMapTLB(pVM);
3336	pgmUnlock(pVM);
3337	return !cFound && iRegion != UINT32_MAX && iSubDev != UINT32_MAX ? VERR_NOT_FOUND : rc;
3338	}
3339
3340
3341	/**
3342	* Maps a MMIO2 region or a pre-registered MMIO region.
3343	*
3344	* This is done when a guest / the bios / state loading changes the
3345	* PCI config. The replacing of base memory has the same restrictions
3346	* as during registration, of course.
3347	*
3348	* @returns VBox status code.
3349	*
3350	* @param pVM The cross context VM structure.
3351	* @param pDevIns The device instance owning the region.
3352	* @param iSubDev The sub-device number of the registered region.
3353	* @param iRegion The index of the registered region.
3354	* @param GCPhys The guest-physical address to be remapped.
3355	*/
3356	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys)
3357	{
3358	/*
3359	* Validate input.
3360	*
3361	* Note! It's safe to walk the MMIO/MMIO2 list since registrations only
3362	* happens during VM construction.
3363	*/
3364	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3365	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3366	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3367	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3368	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3369	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3370	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3371
3372	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3373	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3374	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3375
3376	PPGMREGMMIORANGE pLastMmio = pFirstMmio;
3377	RTGCPHYS cbRange = 0;
3378	for (;;)
3379	{
3380	AssertReturn(!(pLastMmio->fFlags & PGMREGMMIORANGE_F_MAPPED), VERR_WRONG_ORDER);
3381	Assert(pLastMmio->RamRange.GCPhys == NIL_RTGCPHYS);
3382	Assert(pLastMmio->RamRange.GCPhysLast == NIL_RTGCPHYS);
3383	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3384	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3385	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3386	cbRange += pLastMmio->RamRange.cb;
3387	if (pLastMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3388	break;
3389	pLastMmio = pLastMmio->pNextR3;
3390	}
3391
3392	RTGCPHYS GCPhysLast = GCPhys + cbRange - 1;
3393	AssertLogRelReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3394
3395	/*
3396	* Find our location in the ram range list, checking for restriction
3397	* we don't bother implementing yet (partially overlapping, multiple
3398	* ram ranges).
3399	*/
3400	pgmLock(pVM);
3401
3402	AssertReturnStmt(!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED), pgmUnlock(pVM), VERR_WRONG_ORDER);
3403
3404	bool fRamExists = false;
3405	PPGMRAMRANGE pRamPrev = NULL;
3406	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3407	while (pRam && GCPhysLast >= pRam->GCPhys)
3408	{
3409	if ( GCPhys <= pRam->GCPhysLast
3410	&& GCPhysLast >= pRam->GCPhys)
3411	{
3412	/* Completely within? */
3413	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
3414	&& GCPhysLast <= pRam->GCPhysLast,
3415	("%RGp-%RGp (MMIOEx/%s) falls partly outside %RGp-%RGp (%s)\n",
3416	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc,
3417	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3418	pgmUnlock(pVM),
3419	VERR_PGM_RAM_CONFLICT);
3420
3421	/* Check that all the pages are RAM pages. */
3422	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3423	uint32_t cPagesLeft = cbRange >> PAGE_SHIFT;
3424	while (cPagesLeft-- > 0)
3425	{
3426	AssertLogRelMsgReturnStmt(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3427	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
3428	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc),
3429	pgmUnlock(pVM),
3430	VERR_PGM_RAM_CONFLICT);
3431	pPage++;
3432	}
3433
3434	/* There can only be one MMIO/MMIO2 chunk matching here! */
3435	AssertLogRelMsgReturnStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK,
3436	("%RGp-%RGp (MMIOEx/%s, flags %#X) consists of multiple chunks whereas the RAM somehow doesn't!\n",
3437	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3438	pgmUnlock(pVM),
3439	VERR_PGM_PHYS_MMIO_EX_IPE);
3440
3441	fRamExists = true;
3442	break;
3443	}
3444
3445	/* next */
3446	pRamPrev = pRam;
3447	pRam = pRam->pNextR3;
3448	}
3449	Log(("PGMR3PhysMMIOExMap: %RGp-%RGp fRamExists=%RTbool %s\n", GCPhys, GCPhysLast, fRamExists, pFirstMmio->RamRange.pszDesc));
3450
3451
3452	/*
3453	* Make the changes.
3454	*/
3455	RTGCPHYS GCPhysCur = GCPhys;
3456	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3457	{
3458	pCurMmio->RamRange.GCPhys = GCPhysCur;
3459	pCurMmio->RamRange.GCPhysLast = GCPhysCur + pCurMmio->RamRange.cb - 1;
3460	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3461	{
3462	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3463	break;
3464	}
3465	GCPhysCur += pCurMmio->RamRange.cb;
3466	}
3467
3468	if (fRamExists)
3469	{
3470	/*
3471	* Make all the pages in the range MMIO/ZERO pages, freeing any
3472	* RAM pages currently mapped here. This might not be 100% correct
3473	* for PCI memory, but we're doing the same thing for MMIO2 pages.
3474	*
3475	* We replace this MMIO/ZERO pages with real pages in the MMIO2 case.
3476	*/
3477	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK); /* Only one chunk */
3478
3479	int rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
3480	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
3481
3482	if (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2)
3483	{
3484	/* replace the pages, freeing all present RAM pages. */
3485	PPGMPAGE pPageSrc = &pFirstMmio->RamRange.aPages[0];
3486	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3487	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3488	while (cPagesLeft-- > 0)
3489	{
3490	Assert(PGM_PAGE_IS_MMIO(pPageDst));
3491
3492	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
3493	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
3494	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
3495	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
3496	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
3497	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
3498	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
3499	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
3500	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
3501	/* (We tell NEM at the end of the function.) */
3502
3503	pVM->pgm.s.cZeroPages--;
3504	GCPhys += PAGE_SIZE;
3505	pPageSrc++;
3506	pPageDst++;
3507	}
3508	}
3509
3510	/* Flush physical page map TLB. */
3511	pgmPhysInvalidatePageMapTLB(pVM);
3512
3513	/* Force a PGM pool flush as guest ram references have been changed. */
3514	/** @todo not entirely SMP safe; assuming for now the guest takes care of
3515	* this internally (not touch mapped mmio while changing the mapping). */
3516	PVMCPU pVCpu = VMMGetCpu(pVM);
3517	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3518	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3519	}
3520	else
3521	{
3522	/*
3523	* No RAM range, insert the ones prepared during registration.
3524	*/
3525	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3526	{
3527	/* Clear the tracking data of pages we're going to reactivate. */
3528	PPGMPAGE pPageSrc = &pCurMmio->RamRange.aPages[0];
3529	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3530	while (cPagesLeft-- > 0)
3531	{
3532	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
3533	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
3534	pPageSrc++;
3535	}
3536
3537	/* link in the ram range */
3538	pgmR3PhysLinkRamRange(pVM, &pCurMmio->RamRange, pRamPrev);
3539
3540	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3541	{
3542	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3543	break;
3544	}
3545	pRamPrev = &pCurMmio->RamRange;
3546	}
3547	}
3548
3549	/*
3550	* Register the access handler if plain MMIO.
3551	*
3552	* We must register access handlers for each range since the access handler
3553	* code refuses to deal with multiple ranges (and we can).
3554	*/
3555	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2))
3556	{
3557	int rc = VINF_SUCCESS;
3558	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3559	{
3560	Assert(!(pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED));
3561	rc = pgmHandlerPhysicalExRegister(pVM, pCurMmio->pPhysHandlerR3, pCurMmio->RamRange.GCPhys,
3562	pCurMmio->RamRange.GCPhysLast);
3563	if (RT_FAILURE(rc))
3564	break;
3565	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_MAPPED; /* Use this to mark that the handler is registered. */
3566	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3567	{
3568	rc = IOMR3MmioExNotifyMapped(pVM, pFirstMmio->pPhysHandlerR3->pvUserR3, GCPhys);
3569	break;
3570	}
3571	}
3572	if (RT_FAILURE(rc))
3573	{
3574	/* Almost impossible, but try clean up properly and get out of here. */
3575	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3576	{
3577	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED)
3578	{
3579	pCurMmio->fFlags &= ~PGMREGMMIORANGE_F_MAPPED;
3580	pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3, fRamExists);
3581	}
3582
3583	if (!fRamExists)
3584	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3585	else
3586	{
3587	Assert(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK); /* Only one chunk */
3588
3589	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3590	PPGMPAGE pPageDst = &pRam->aPages[(pCurMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3591	while (cPagesLeft-- > 0)
3592	{
3593	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3594	pPageDst++;
3595	}
3596	}
3597
3598	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3599	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3600	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3601	break;
3602	}
3603
3604	pgmUnlock(pVM);
3605	return rc;
3606	}
3607	}
3608
3609	/*
3610	* We're good, set the flags and invalid the mapping TLB.
3611	*/
3612	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3613	{
3614	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_MAPPED;
3615	if (fRamExists)
3616	pCurMmio->fFlags \|= PGMREGMMIORANGE_F_OVERLAPPING;
3617	else
3618	pCurMmio->fFlags &= ~PGMREGMMIORANGE_F_OVERLAPPING;
3619	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3620	break;
3621	}
3622	pgmPhysInvalidatePageMapTLB(pVM);
3623
3624	/*
3625	* Notify NEM while holding the lock (experimental) and REM without (like always).
3626	*/
3627	uint32_t const fNemNotify = (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0)
3628	\| (pFirstMmio->fFlags & PGMREGMMIORANGE_F_OVERLAPPING ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
3629	int rc = NEMR3NotifyPhysMmioExMap(pVM, GCPhys, cbRange, fNemNotify, pFirstMmio->pvR3);
3630
3631	pgmUnlock(pVM);
3632
3633	#ifdef VBOX_WITH_REM
3634	if (!fRamExists && (pFirstMmio->fFlags & PGMREGMMIORANGE_F_MMIO2)) /** @todo this doesn't look right. */
3635	REMR3NotifyPhysRamRegister(pVM, GCPhys, cbRange, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
3636	#endif
3637	return rc;
3638	}
3639
3640
3641	/**
3642	* Unmaps a MMIO2 or a pre-registered MMIO region.
3643	*
3644	* This is done when a guest / the bios / state loading changes the
3645	* PCI config. The replacing of base memory has the same restrictions
3646	* as during registration, of course.
3647	*/
3648	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys)
3649	{
3650	/*
3651	* Validate input
3652	*/
3653	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3654	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3655	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3656	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3657	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3658	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3659	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3660
3661	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3662	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3663	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3664
3665	PPGMREGMMIORANGE pLastMmio = pFirstMmio;
3666	RTGCPHYS cbRange = 0;
3667	for (;;)
3668	{
3669	AssertReturn(pLastMmio->fFlags & PGMREGMMIORANGE_F_MAPPED, VERR_WRONG_ORDER);
3670	AssertReturn(pLastMmio->RamRange.GCPhys == GCPhys + cbRange, VERR_INVALID_PARAMETER);
3671	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3672	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3673	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3674	cbRange += pLastMmio->RamRange.cb;
3675	if (pLastMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3676	break;
3677	pLastMmio = pLastMmio->pNextR3;
3678	}
3679
3680	Log(("PGMR3PhysMMIOExUnmap: %RGp-%RGp %s\n",
3681	pFirstMmio->RamRange.GCPhys, pLastMmio->RamRange.GCPhysLast, pFirstMmio->RamRange.pszDesc));
3682
3683	int rc = pgmLock(pVM);
3684	AssertRCReturn(rc, rc);
3685	uint16_t const fOldFlags = pFirstMmio->fFlags;
3686	AssertReturnStmt(fOldFlags & PGMREGMMIORANGE_F_MAPPED, pgmUnlock(pVM), VERR_WRONG_ORDER);
3687
3688	/*
3689	* If plain MMIO, we must deregister the handlers first.
3690	*/
3691	if (!(fOldFlags & PGMREGMMIORANGE_F_MMIO2))
3692	{
3693	PPGMREGMMIORANGE pCurMmio = pFirstMmio;
3694	rc = pgmHandlerPhysicalExDeregister(pVM, pFirstMmio->pPhysHandlerR3, RT_BOOL(fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING));
3695	AssertRCReturnStmt(rc, pgmUnlock(pVM), rc);
3696	while (!(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK))
3697	{
3698	pCurMmio = pCurMmio->pNextR3;
3699	rc = pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3, RT_BOOL(fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING));
3700	AssertRCReturnStmt(rc, pgmUnlock(pVM), VERR_PGM_PHYS_MMIO_EX_IPE);
3701	}
3702
3703	IOMR3MmioExNotifyUnmapped(pVM, pFirstMmio->pPhysHandlerR3->pvUserR3, GCPhys);
3704	}
3705
3706	/*
3707	* Unmap it.
3708	*/
3709	RTGCPHYS const GCPhysRangeNotify = pFirstMmio->RamRange.GCPhys;
3710	if (fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING)
3711	{
3712	/*
3713	* We've replaced RAM, replace with zero pages.
3714	*
3715	* Note! This is where we might differ a little from a real system, because
3716	* it's likely to just show the RAM pages as they were before the
3717	* MMIO/MMIO2 region was mapped here.
3718	*/
3719	/* Only one chunk allowed when overlapping! */
3720	Assert(fOldFlags & PGMREGMMIORANGE_F_LAST_CHUNK);
3721
3722	/* Restore the RAM pages we've replaced. */
3723	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3724	while (pRam->GCPhys > pFirstMmio->RamRange.GCPhysLast)
3725	pRam = pRam->pNextR3;
3726
3727	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3728	if (fOldFlags & PGMREGMMIORANGE_F_MMIO2)
3729	pVM->pgm.s.cZeroPages += cPagesLeft;
3730
3731	PPGMPAGE pPageDst = &pRam->aPages[(pFirstMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3732	while (cPagesLeft-- > 0)
3733	{
3734	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3735	pPageDst++;
3736	}
3737
3738	/* Flush physical page map TLB. */
3739	pgmPhysInvalidatePageMapTLB(pVM);
3740
3741	/* Update range state. */
3742	pFirstMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3743	pFirstMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3744	pFirstMmio->fFlags &= ~(PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MAPPED);
3745	}
3746	else
3747	{
3748	/*
3749	* Unlink the chunks related to the MMIO/MMIO2 region.
3750	*/
3751	for (PPGMREGMMIORANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3752	{
3753	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3754	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3755	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3756	pCurMmio->fFlags &= ~(PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MAPPED);
3757	if (pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK)
3758	break;
3759	}
3760	}
3761
3762	/* Force a PGM pool flush as guest ram references have been changed. */
3763	/** @todo not entirely SMP safe; assuming for now the guest takes care
3764	* of this internally (not touch mapped mmio while changing the
3765	* mapping). */
3766	PVMCPU pVCpu = VMMGetCpu(pVM);
3767	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3768	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3769
3770	pgmPhysInvalidatePageMapTLB(pVM);
3771	pgmPhysInvalidRamRangeTlbs(pVM);
3772
3773	/*
3774	* Notify NEM while holding the lock (experimental) and REM without (like always).
3775	*/
3776	uint32_t const fNemFlags = (fOldFlags & PGMREGMMIORANGE_F_MMIO2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0)
3777	\| (fOldFlags & PGMREGMMIORANGE_F_OVERLAPPING ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
3778	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhysRangeNotify, cbRange, fNemFlags);
3779	pgmUnlock(pVM);
3780	#ifdef VBOX_WITH_REM
3781	if ((fOldFlags & (PGMREGMMIORANGE_F_OVERLAPPING \| PGMREGMMIORANGE_F_MMIO2)) == PGMREGMMIORANGE_F_MMIO2)
3782	REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeNotify, cbRange);
3783	#endif
3784	return rc;
3785	}
3786
3787
3788	/**
3789	* Reduces the mapping size of a MMIO2 or pre-registered MMIO region.
3790	*
3791	* This is mainly for dealing with old saved states after changing the default
3792	* size of a mapping region. See PGMDevHlpMMIOExReduce and
3793	* PDMPCIDEV::pfnRegionLoadChangeHookR3.
3794	*
3795	* The region must not currently be mapped when making this call. The VM state
3796	* must be state restore or VM construction.
3797	*
3798	* @returns VBox status code.
3799	* @param pVM The cross context VM structure.
3800	* @param pDevIns The device instance owning the region.
3801	* @param iSubDev The sub-device number of the registered region.
3802	* @param iRegion The index of the registered region.
3803	* @param cbRegion The new mapping size.
3804	*/
3805	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion)
3806	{
3807	/*
3808	* Validate input
3809	*/
3810	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3811	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3812	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3813	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3814	AssertReturn(cbRegion >= X86_PAGE_SIZE, VERR_INVALID_PARAMETER);
3815	AssertReturn(!(cbRegion & X86_PAGE_OFFSET_MASK), VERR_UNSUPPORTED_ALIGNMENT);
3816	VMSTATE enmVmState = VMR3GetState(pVM);
3817	AssertLogRelMsgReturn( enmVmState == VMSTATE_CREATING
3818	\|\| enmVmState == VMSTATE_LOADING,
3819	("enmVmState=%d (%s)\n", enmVmState, VMR3GetStateName(enmVmState)),
3820	VERR_VM_INVALID_VM_STATE);
3821
3822	int rc = pgmLock(pVM);
3823	AssertRCReturn(rc, rc);
3824
3825	PPGMREGMMIORANGE pFirstMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3826	if (pFirstMmio)
3827	{
3828	Assert(pFirstMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3829	if (!(pFirstMmio->fFlags & PGMREGMMIORANGE_F_MAPPED))
3830	{
3831	/*
3832	* NOTE! Current implementation does not support multiple ranges.
3833	* Implement when there is a real world need and thus a testcase.
3834	*/
3835	AssertLogRelMsgStmt(pFirstMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK,
3836	("%s: %#x\n", pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3837	rc = VERR_NOT_SUPPORTED);
3838	if (RT_SUCCESS(rc))
3839	{
3840	/*
3841	* Make the change.
3842	*/
3843	Log(("PGMR3PhysMMIOExReduce: %s changes from %RGp bytes (%RGp) to %RGp bytes.\n",
3844	pFirstMmio->RamRange.pszDesc, pFirstMmio->RamRange.cb, pFirstMmio->cbReal, cbRegion));
3845
3846	AssertLogRelMsgStmt(cbRegion <= pFirstMmio->cbReal,
3847	("%s: cbRegion=%#RGp cbReal=%#RGp\n", pFirstMmio->RamRange.pszDesc, cbRegion, pFirstMmio->cbReal),
3848	rc = VERR_OUT_OF_RANGE);
3849	if (RT_SUCCESS(rc))
3850	{
3851	pFirstMmio->RamRange.cb = cbRegion;
3852	}
3853	}
3854	}
3855	else
3856	rc = VERR_WRONG_ORDER;
3857	}
3858	else
3859	rc = VERR_NOT_FOUND;
3860
3861	pgmUnlock(pVM);
3862	return rc;
3863	}
3864
3865
3866	/**
3867	* Checks if the given address is an MMIO2 or pre-registered MMIO base address
3868	* or not.
3869	*
3870	* @returns true/false accordingly.
3871	* @param pVM The cross context VM structure.
3872	* @param pDevIns The owner of the memory, optional.
3873	* @param GCPhys The address to check.
3874	*/
3875	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
3876	{
3877	/*
3878	* Validate input
3879	*/
3880	VM_ASSERT_EMT_RETURN(pVM, false);
3881	AssertPtrReturn(pDevIns, false);
3882	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
3883	AssertReturn(GCPhys != 0, false);
3884	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
3885
3886	/*
3887	* Search the list.
3888	*/
3889	pgmLock(pVM);
3890	for (PPGMREGMMIORANGE pCurMmio = pVM->pgm.s.pRegMmioRangesR3; pCurMmio; pCurMmio = pCurMmio->pNextR3)
3891	if (pCurMmio->RamRange.GCPhys == GCPhys)
3892	{
3893	Assert(pCurMmio->fFlags & PGMREGMMIORANGE_F_MAPPED);
3894	bool fRet = RT_BOOL(pCurMmio->fFlags & PGMREGMMIORANGE_F_FIRST_CHUNK);
3895	pgmUnlock(pVM);
3896	return fRet;
3897	}
3898	pgmUnlock(pVM);
3899	return false;
3900	}
3901
3902
3903	/**
3904	* Gets the HC physical address of a page in the MMIO2 region.
3905	*
3906	* This is API is intended for MMHyper and shouldn't be called
3907	* by anyone else...
3908	*
3909	* @returns VBox status code.
3910	* @param pVM The cross context VM structure.
3911	* @param pDevIns The owner of the memory, optional.
3912	* @param iSubDev Sub-device number.
3913	* @param iRegion The region.
3914	* @param off The page expressed an offset into the MMIO2 region.
3915	* @param pHCPhys Where to store the result.
3916	*/
3917	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
3918	RTGCPHYS off, PRTHCPHYS pHCPhys)
3919	{
3920	/*
3921	* Validate input
3922	*/
3923	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3924	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3925	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3926	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3927
3928	pgmLock(pVM);
3929	PPGMREGMMIORANGE pCurMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3930	AssertReturn(pCurMmio, VERR_NOT_FOUND);
3931	AssertReturn(pCurMmio->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK), VERR_WRONG_TYPE);
3932
3933	while ( off >= pCurMmio->RamRange.cb
3934	&& !(pCurMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK))
3935	{
3936	off -= pCurMmio->RamRange.cb;
3937	pCurMmio = pCurMmio->pNextR3;
3938	}
3939	AssertReturn(off < pCurMmio->RamRange.cb, VERR_INVALID_PARAMETER);
3940
3941	PCPGMPAGE pPage = &pCurMmio->RamRange.aPages[off >> PAGE_SHIFT];
3942	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3943	pgmUnlock(pVM);
3944	return VINF_SUCCESS;
3945	}
3946
3947
3948	/**
3949	* Maps a portion of an MMIO2 region into kernel space (host).
3950	*
3951	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
3952	* or the VM is terminated.
3953	*
3954	* @return VBox status code.
3955	*
3956	* @param pVM The cross context VM structure.
3957	* @param pDevIns The device owning the MMIO2 memory.
3958	* @param iSubDev The sub-device number.
3959	* @param iRegion The region.
3960	* @param off The offset into the region. Must be page aligned.
3961	* @param cb The number of bytes to map. Must be page aligned.
3962	* @param pszDesc Mapping description.
3963	* @param pR0Ptr Where to store the R0 address.
3964	*/
3965	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
3966	RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr)
3967	{
3968	/*
3969	* Validate input.
3970	*/
3971	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3972	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3973	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3974	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3975
3976	PPGMREGMMIORANGE pFirstRegMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
3977	AssertReturn(pFirstRegMmio, VERR_NOT_FOUND);
3978	AssertReturn(pFirstRegMmio->fFlags & (PGMREGMMIORANGE_F_MMIO2 \| PGMREGMMIORANGE_F_FIRST_CHUNK), VERR_WRONG_TYPE);
3979	AssertReturn(off < pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
3980	AssertReturn(cb <= pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
3981	AssertReturn(off + cb <= pFirstRegMmio->RamRange.cb, VERR_INVALID_PARAMETER);
3982	NOREF(pszDesc);
3983
3984	/*
3985	* Pass the request on to the support library/driver.
3986	*/
3987	#if defined(RT_OS_WINDOWS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_OS2) /** @todo Fully implement RTR0MemObjMapKernelEx everywhere. */
3988	AssertLogRelReturn(off == 0, VERR_NOT_SUPPORTED);
3989	AssertLogRelReturn(pFirstRegMmio->fFlags & PGMREGMMIORANGE_F_LAST_CHUNK, VERR_NOT_SUPPORTED);
3990	int rc = SUPR3PageMapKernel(pFirstRegMmio->pvR3, 0 /off/, pFirstRegMmio->RamRange.cb, 0 /fFlags/, pR0Ptr);
3991	#else
3992	int rc = SUPR3PageMapKernel(pFirstRegMmio->pvR3, off, cb, 0 /fFlags/, pR0Ptr);
3993	#endif
3994
3995	return rc;
3996	}
3997
3998
3999	/**
4000	* Changes the region number of an MMIO2 or pre-registered MMIO region.
4001	*
4002	* This is only for dealing with save state issues, nothing else.
4003	*
4004	* @return VBox status code.
4005	*
4006	* @param pVM The cross context VM structure.
4007	* @param pDevIns The device owning the MMIO2 memory.
4008	* @param iSubDev The sub-device number.
4009	* @param iRegion The region.
4010	* @param iNewRegion The new region index.
4011	*
4012	* @sa @bugref{9359}
4013	*/
4014	VMMR3_INT_DECL(int) PGMR3PhysMMIOExChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion,
4015	uint32_t iNewRegion)
4016	{
4017	/*
4018	* Validate input.
4019	*/
4020	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4021	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4022	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
4023	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4024	AssertReturn(iNewRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4025
4026	AssertReturn(pVM->enmVMState == VMSTATE_LOADING, VERR_INVALID_STATE);
4027
4028	PPGMREGMMIORANGE pFirstRegMmio = pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iRegion);
4029	AssertReturn(pFirstRegMmio, VERR_NOT_FOUND);
4030	AssertReturn(pgmR3PhysMMIOExFind(pVM, pDevIns, iSubDev, iNewRegion) == NULL, VERR_RESOURCE_IN_USE);
4031
4032	/*
4033	* Make the change.
4034	*/
4035	pFirstRegMmio->iRegion = (uint8_t)iNewRegion;
4036
4037	return VINF_SUCCESS;
4038	}
4039
4040
4041	/**
4042	* Worker for PGMR3PhysRomRegister.
4043	*
4044	* This is here to simplify lock management, i.e. the caller does all the
4045	* locking and we can simply return without needing to remember to unlock
4046	* anything first.
4047	*
4048	* @returns VBox status code.
4049	* @param pVM The cross context VM structure.
4050	* @param pDevIns The device instance owning the ROM.
4051	* @param GCPhys First physical address in the range.
4052	* Must be page aligned!
4053	* @param cb The size of the range (in bytes).
4054	* Must be page aligned!
4055	* @param pvBinary Pointer to the binary data backing the ROM image.
4056	* @param cbBinary The size of the binary data pvBinary points to.
4057	* This must be less or equal to @a cb.
4058	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4059	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4060	* @param pszDesc Pointer to description string. This must not be freed.
4061	*/
4062	static int pgmR3PhysRomRegisterLocked(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4063	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
4064	{
4065	/*
4066	* Validate input.
4067	*/
4068	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4069	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
4070	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
4071	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4072	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4073	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
4074	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
4075	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
4076	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
4077
4078	const uint32_t cPages = cb >> PAGE_SHIFT;
4079
4080	/*
4081	* Find the ROM location in the ROM list first.
4082	*/
4083	PPGMROMRANGE pRomPrev = NULL;
4084	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
4085	while (pRom && GCPhysLast >= pRom->GCPhys)
4086	{
4087	if ( GCPhys <= pRom->GCPhysLast
4088	&& GCPhysLast >= pRom->GCPhys)
4089	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
4090	GCPhys, GCPhysLast, pszDesc,
4091	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
4092	VERR_PGM_RAM_CONFLICT);
4093	/* next */
4094	pRomPrev = pRom;
4095	pRom = pRom->pNextR3;
4096	}
4097
4098	/*
4099	* Find the RAM location and check for conflicts.
4100	*
4101	* Conflict detection is a bit different than for RAM
4102	* registration since a ROM can be located within a RAM
4103	* range. So, what we have to check for is other memory
4104	* types (other than RAM that is) and that we don't span
4105	* more than one RAM range (layz).
4106	*/
4107	bool fRamExists = false;
4108	PPGMRAMRANGE pRamPrev = NULL;
4109	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4110	while (pRam && GCPhysLast >= pRam->GCPhys)
4111	{
4112	if ( GCPhys <= pRam->GCPhysLast
4113	&& GCPhysLast >= pRam->GCPhys)
4114	{
4115	/* completely within? */
4116	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
4117	&& GCPhysLast <= pRam->GCPhysLast,
4118	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
4119	GCPhys, GCPhysLast, pszDesc,
4120	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
4121	VERR_PGM_RAM_CONFLICT);
4122	fRamExists = true;
4123	break;
4124	}
4125
4126	/* next */
4127	pRamPrev = pRam;
4128	pRam = pRam->pNextR3;
4129	}
4130	if (fRamExists)
4131	{
4132	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4133	uint32_t cPagesLeft = cPages;
4134	while (cPagesLeft-- > 0)
4135	{
4136	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
4137	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
4138	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
4139	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
4140	Assert(PGM_PAGE_IS_ZERO(pPage));
4141	pPage++;
4142	}
4143	}
4144
4145	/*
4146	* Update the base memory reservation if necessary.
4147	*/
4148	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
4149	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4150	cExtraBaseCost += cPages;
4151	if (cExtraBaseCost)
4152	{
4153	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
4154	if (RT_FAILURE(rc))
4155	return rc;
4156	}
4157
4158	/*
4159	* Allocate memory for the virgin copy of the RAM.
4160	*/
4161	PGMMALLOCATEPAGESREQ pReq;
4162	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
4163	AssertRCReturn(rc, rc);
4164
4165	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4166	{
4167	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
4168	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
4169	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
4170	}
4171
4172	rc = GMMR3AllocatePagesPerform(pVM, pReq);
4173	if (RT_FAILURE(rc))
4174	{
4175	GMMR3AllocatePagesCleanup(pReq);
4176	return rc;
4177	}
4178
4179	/*
4180	* Allocate the new ROM range and RAM range (if necessary).
4181	*/
4182	PPGMROMRANGE pRomNew;
4183	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
4184	if (RT_SUCCESS(rc))
4185	{
4186	PPGMRAMRANGE pRamNew = NULL;
4187	if (!fRamExists)
4188	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
4189	if (RT_SUCCESS(rc))
4190	{
4191	/*
4192	* Initialize and insert the RAM range (if required).
4193	*/
4194	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
4195	if (!fRamExists)
4196	{
4197	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
4198	pRamNew->GCPhys = GCPhys;
4199	pRamNew->GCPhysLast = GCPhysLast;
4200	pRamNew->cb = cb;
4201	pRamNew->pszDesc = pszDesc;
4202	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
4203	pRamNew->pvR3 = NULL;
4204	pRamNew->paLSPages = NULL;
4205
4206	PPGMPAGE pPage = &pRamNew->aPages[0];
4207	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
4208	{
4209	PGM_PAGE_INIT(pPage,
4210	pReq->aPages[iPage].HCPhysGCPhys,
4211	pReq->aPages[iPage].idPage,
4212	PGMPAGETYPE_ROM,
4213	PGM_PAGE_STATE_ALLOCATED);
4214
4215	pRomPage->Virgin = *pPage;
4216	}
4217
4218	pVM->pgm.s.cAllPages += cPages;
4219	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
4220	}
4221	else
4222	{
4223	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4224	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
4225	{
4226	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_ROM);
4227	PGM_PAGE_SET_HCPHYS(pVM, pPage, pReq->aPages[iPage].HCPhysGCPhys);
4228	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
4229	PGM_PAGE_SET_PAGEID(pVM, pPage, pReq->aPages[iPage].idPage);
4230	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4231	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
4232	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
4233
4234	pRomPage->Virgin = *pPage;
4235	}
4236
4237	pRamNew = pRam;
4238
4239	pVM->pgm.s.cZeroPages -= cPages;
4240	}
4241	pVM->pgm.s.cPrivatePages += cPages;
4242
4243	/* Flush physical page map TLB. */
4244	pgmPhysInvalidatePageMapTLB(pVM);
4245
4246
4247	/* Notify NEM before we register handlers. */
4248	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_ROM_F_REPLACE : 0)
4249	\| (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED ? NEM_NOTIFY_PHYS_ROM_F_SHADOW : 0);
4250	rc = NEMR3NotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fNemNotify);
4251
4252	/*
4253	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
4254	*
4255	* If it's shadowed we'll register the handler after the ROM notification
4256	* so we get the access handler callbacks that we should. If it isn't
4257	* shadowed we'll do it the other way around to make REM use the built-in
4258	* ROM behavior and not the handler behavior (which is to route all access
4259	* to PGM atm).
4260	*/
4261	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4262	{
4263	#ifdef VBOX_WITH_REM
4264	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
4265	#endif
4266	if (RT_SUCCESS(rc))
4267	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4268	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
4269	pszDesc);
4270	}
4271	else
4272	{
4273	if (RT_SUCCESS(rc))
4274	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4275	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew),
4276	pszDesc);
4277	#ifdef VBOX_WITH_REM
4278	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
4279	#endif
4280	}
4281	if (RT_SUCCESS(rc))
4282	{
4283	/*
4284	* Copy the image over to the virgin pages.
4285	* This must be done after linking in the RAM range.
4286	*/
4287	size_t cbBinaryLeft = cbBinary;
4288	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
4289	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4290	{
4291	void *pvDstPage;
4292	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
4293	if (RT_FAILURE(rc))
4294	{
4295	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
4296	break;
4297	}
4298	if (cbBinaryLeft >= PAGE_SIZE)
4299	{
4300	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
4301	cbBinaryLeft -= PAGE_SIZE;
4302	}
4303	else
4304	{
4305	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
4306	if (cbBinaryLeft > 0)
4307	{
4308	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
4309	cbBinaryLeft = 0;
4310	}
4311	}
4312	}
4313	if (RT_SUCCESS(rc))
4314	{
4315	/*
4316	* Initialize the ROM range.
4317	* Note that the Virgin member of the pages has already been initialized above.
4318	*/
4319	pRomNew->GCPhys = GCPhys;
4320	pRomNew->GCPhysLast = GCPhysLast;
4321	pRomNew->cb = cb;
4322	pRomNew->fFlags = fFlags;
4323	pRomNew->idSavedState = UINT8_MAX;
4324	pRomNew->cbOriginal = cbBinary;
4325	pRomNew->pszDesc = pszDesc;
4326	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
4327	? pvBinary : RTMemDup(pvBinary, cbBinary);
4328	if (pRomNew->pvOriginal)
4329	{
4330	for (unsigned iPage = 0; iPage < cPages; iPage++)
4331	{
4332	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
4333	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
4334	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
4335	}
4336
4337	/* update the page count stats for the shadow pages. */
4338	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4339	{
4340	pVM->pgm.s.cZeroPages += cPages;
4341	pVM->pgm.s.cAllPages += cPages;
4342	}
4343
4344	/*
4345	* Insert the ROM range, tell REM and return successfully.
4346	*/
4347	pRomNew->pNextR3 = pRom;
4348	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4349
4350	if (pRomPrev)
4351	{
4352	pRomPrev->pNextR3 = pRomNew;
4353	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
4354	}
4355	else
4356	{
4357	pVM->pgm.s.pRomRangesR3 = pRomNew;
4358	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
4359	}
4360
4361	pgmPhysInvalidatePageMapTLB(pVM);
4362	GMMR3AllocatePagesCleanup(pReq);
4363
4364	/* Notify NEM again. */
4365	return NEMR3NotifyPhysRomRegisterLate(pVM, GCPhys, cb, fNemNotify);
4366	}
4367
4368	/* bail out */
4369	rc = VERR_NO_MEMORY;
4370	}
4371
4372	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
4373	AssertRC(rc2);
4374	}
4375
4376	if (!fRamExists)
4377	{
4378	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
4379	MMHyperFree(pVM, pRamNew);
4380	}
4381	}
4382	MMHyperFree(pVM, pRomNew);
4383	}
4384
4385	/** @todo Purge the mapping cache or something... */
4386	GMMR3FreeAllocatedPages(pVM, pReq);
4387	GMMR3AllocatePagesCleanup(pReq);
4388	return rc;
4389	}
4390
4391
4392	/**
4393	* Registers a ROM image.
4394	*
4395	* Shadowed ROM images requires double the amount of backing memory, so,
4396	* don't use that unless you have to. Shadowing of ROM images is process
4397	* where we can select where the reads go and where the writes go. On real
4398	* hardware the chipset provides means to configure this. We provide
4399	* PGMR3PhysProtectROM() for this purpose.
4400	*
4401	* A read-only copy of the ROM image will always be kept around while we
4402	* will allocate RAM pages for the changes on demand (unless all memory
4403	* is configured to be preallocated).
4404	*
4405	* @returns VBox status code.
4406	* @param pVM The cross context VM structure.
4407	* @param pDevIns The device instance owning the ROM.
4408	* @param GCPhys First physical address in the range.
4409	* Must be page aligned!
4410	* @param cb The size of the range (in bytes).
4411	* Must be page aligned!
4412	* @param pvBinary Pointer to the binary data backing the ROM image.
4413	* @param cbBinary The size of the binary data pvBinary points to.
4414	* This must be less or equal to @a cb.
4415	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4416	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4417	* @param pszDesc Pointer to description string. This must not be freed.
4418	*
4419	* @remark There is no way to remove the rom, automatically on device cleanup or
4420	* manually from the device yet. This isn't difficult in any way, it's
4421	* just not something we expect to be necessary for a while.
4422	*/
4423	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4424	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
4425	{
4426	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
4427	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
4428	pgmLock(pVM);
4429	int rc = pgmR3PhysRomRegisterLocked(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
4430	pgmUnlock(pVM);
4431	return rc;
4432	}
4433
4434
4435	/**
4436	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
4437	* that the virgin part is untouched.
4438	*
4439	* This is done after the normal memory has been cleared.
4440	*
4441	* ASSUMES that the caller owns the PGM lock.
4442	*
4443	* @param pVM The cross context VM structure.
4444	*/
4445	int pgmR3PhysRomReset(PVM pVM)
4446	{
4447	PGM_LOCK_ASSERT_OWNER(pVM);
4448	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4449	{
4450	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
4451
4452	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4453	{
4454	/*
4455	* Reset the physical handler.
4456	*/
4457	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
4458	AssertRCReturn(rc, rc);
4459
4460	/*
4461	* What we do with the shadow pages depends on the memory
4462	* preallocation option. If not enabled, we'll just throw
4463	* out all the dirty pages and replace them by the zero page.
4464	*/
4465	if (!pVM->pgm.s.fRamPreAlloc)
4466	{
4467	/* Free the dirty pages. */
4468	uint32_t cPendingPages = 0;
4469	PGMMFREEPAGESREQ pReq;
4470	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4471	AssertRCReturn(rc, rc);
4472
4473	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4474	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
4475	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
4476	{
4477	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
4478	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
4479	pRom->GCPhys + (iPage << PAGE_SHIFT),
4480	(PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pRom->aPages[iPage].Shadow));
4481	AssertLogRelRCReturn(rc, rc);
4482	}
4483
4484	if (cPendingPages)
4485	{
4486	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
4487	AssertLogRelRCReturn(rc, rc);
4488	}
4489	GMMR3FreePagesCleanup(pReq);
4490	}
4491	else
4492	{
4493	/* clear all the shadow pages. */
4494	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4495	{
4496	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
4497	continue;
4498	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
4499	void *pvDstPage;
4500	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4501	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
4502	if (RT_FAILURE(rc))
4503	break;
4504	ASMMemZeroPage(pvDstPage);
4505	}
4506	AssertRCReturn(rc, rc);
4507	}
4508	}
4509
4510	/*
4511	* Restore the original ROM pages after a saved state load.
4512	* Also, in strict builds check that ROM pages remain unmodified.
4513	*/
4514	#ifndef VBOX_STRICT
4515	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4516	#endif
4517	{
4518	size_t cbSrcLeft = pRom->cbOriginal;
4519	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
4520	uint32_t cRestored = 0;
4521	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
4522	{
4523	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4524	void const *pvDstPage;
4525	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
4526	if (RT_FAILURE(rc))
4527	break;
4528
4529	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
4530	{
4531	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4532	{
4533	void *pvDstPageW;
4534	rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPageW);
4535	AssertLogRelRCReturn(rc, rc);
4536	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
4537	cRestored++;
4538	}
4539	else
4540	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
4541	}
4542	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
4543	}
4544	if (cRestored > 0)
4545	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
4546	}
4547	}
4548
4549	/* Clear the ROM restore flag now as we only need to do this once after
4550	loading saved state. */
4551	pVM->pgm.s.fRestoreRomPagesOnReset = false;
4552
4553	return VINF_SUCCESS;
4554	}
4555
4556
4557	/**
4558	* Called by PGMR3Term to free resources.
4559	*
4560	* ASSUMES that the caller owns the PGM lock.
4561	*
4562	* @param pVM The cross context VM structure.
4563	*/
4564	void pgmR3PhysRomTerm(PVM pVM)
4565	{
4566	/*
4567	* Free the heap copy of the original bits.
4568	*/
4569	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4570	{
4571	if ( pRom->pvOriginal
4572	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
4573	{
4574	RTMemFree((void *)pRom->pvOriginal);
4575	pRom->pvOriginal = NULL;
4576	}
4577	}
4578	}
4579
4580
4581	/**
4582	* Change the shadowing of a range of ROM pages.
4583	*
4584	* This is intended for implementing chipset specific memory registers
4585	* and will not be very strict about the input. It will silently ignore
4586	* any pages that are not the part of a shadowed ROM.
4587	*
4588	* @returns VBox status code.
4589	* @retval VINF_PGM_SYNC_CR3
4590	*
4591	* @param pVM The cross context VM structure.
4592	* @param GCPhys Where to start. Page aligned.
4593	* @param cb How much to change. Page aligned.
4594	* @param enmProt The new ROM protection.
4595	*/
4596	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
4597	{
4598	/*
4599	* Check input
4600	*/
4601	if (!cb)
4602	return VINF_SUCCESS;
4603	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4604	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4605	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4606	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4607	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
4608
4609	/*
4610	* Process the request.
4611	*/
4612	pgmLock(pVM);
4613	int rc = VINF_SUCCESS;
4614	bool fFlushTLB = false;
4615	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4616	{
4617	if ( GCPhys <= pRom->GCPhysLast
4618	&& GCPhysLast >= pRom->GCPhys
4619	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
4620	{
4621	/*
4622	* Iterate the relevant pages and make necessary the changes.
4623	*/
4624	bool fChanges = false;
4625	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
4626	? pRom->cb >> PAGE_SHIFT
4627	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
4628	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
4629	iPage < cPages;
4630	iPage++)
4631	{
4632	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
4633	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
4634	{
4635	fChanges = true;
4636
4637	/* flush references to the page. */
4638	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT));
4639	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, pRom->GCPhys + (iPage << PAGE_SHIFT), pRamPage,
4640	true /fFlushPTEs/, &fFlushTLB);
4641	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
4642	rc = rc2;
4643	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pRamPage);
4644
4645	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
4646	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
4647
4648	pOld = pRamPage;
4649	pRamPage = pNew;
4650	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
4651
4652	/* Tell NEM about the backing and protection change. */
4653	if (VM_IS_NEM_ENABLED(pVM))
4654	{
4655	PGMPAGETYPE enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pNew);
4656	NEMHCNotifyPhysPageChanged(pVM, GCPhys, PGM_PAGE_GET_HCPHYS(pOld), PGM_PAGE_GET_HCPHYS(pNew),
4657	pgmPhysPageCalcNemProtection(pRamPage, enmType), enmType, &u2State);
4658	PGM_PAGE_SET_NEM_STATE(pRamPage, u2State);
4659	}
4660	}
4661	pRomPage->enmProt = enmProt;
4662	}
4663
4664	/*
4665	* Reset the access handler if we made changes, no need
4666	* to optimize this.
4667	*/
4668	if (fChanges)
4669	{
4670	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
4671	if (RT_FAILURE(rc2))
4672	{
4673	pgmUnlock(pVM);
4674	AssertRC(rc);
4675	return rc2;
4676	}
4677	}
4678
4679	/* Advance - cb isn't updated. */
4680	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
4681	}
4682	}
4683	pgmUnlock(pVM);
4684	if (fFlushTLB)
4685	PGM_INVL_ALL_VCPU_TLBS(pVM);
4686
4687	return rc;
4688	}
4689
4690
4691	/**
4692	* Sets the Address Gate 20 state.
4693	*
4694	* @param pVCpu The cross context virtual CPU structure.
4695	* @param fEnable True if the gate should be enabled.
4696	* False if the gate should be disabled.
4697	*/
4698	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
4699	{
4700	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
4701	if (pVCpu->pgm.s.fA20Enabled != fEnable)
4702	{
4703	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4704	PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
4705	if ( CPUMIsGuestInVmxRootMode(pCtx)
4706	&& !fEnable)
4707	{
4708	Log(("Cannot enter A20M mode while in VMX root mode\n"));
4709	return;
4710	}
4711	#endif
4712	pVCpu->pgm.s.fA20Enabled = fEnable;
4713	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
4714	#ifdef VBOX_WITH_REM
4715	REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
4716	#endif
4717	NEMR3NotifySetA20(pVCpu, fEnable);
4718	#ifdef PGM_WITH_A20
4719	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4720	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
4721	HMFlushTlb(pVCpu);
4722	#endif
4723	IEMTlbInvalidateAllPhysical(pVCpu);
4724	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
4725	}
4726	}
4727
4728
4729	/**
4730	* Tree enumeration callback for dealing with age rollover.
4731	* It will perform a simple compression of the current age.
4732	*/
4733	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
4734	{
4735	/* Age compression - ASSUMES iNow == 4. */
4736	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4737	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
4738	pChunk->iLastUsed = 3;
4739	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
4740	pChunk->iLastUsed = 2;
4741	else if (pChunk->iLastUsed)
4742	pChunk->iLastUsed = 1;
4743	else /* iLastUsed = 0 */
4744	pChunk->iLastUsed = 4;
4745
4746	NOREF(pvUser);
4747	return 0;
4748	}
4749
4750
4751	/**
4752	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
4753	*/
4754	typedef struct PGMR3PHYSCHUNKUNMAPCB
4755	{
4756	PVM pVM; /*< Pointer to the VM. /
4757	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
4758	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
4759
4760
4761	/**
4762	* Callback used to find the mapping that's been unused for
4763	* the longest time.
4764	*/
4765	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
4766	{
4767	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4768	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
4769
4770	/*
4771	* Check for locks and compare when last used.
4772	*/
4773	if (pChunk->cRefs)
4774	return 0;
4775	if (pChunk->cPermRefs)
4776	return 0;
4777	if ( pArg->pChunk
4778	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
4779	return 0;
4780
4781	/*
4782	* Check that it's not in any of the TLBs.
4783	*/
4784	PVM pVM = pArg->pVM;
4785	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
4786	== pChunk->Core.Key)
4787	{
4788	pChunk = NULL;
4789	return 0;
4790	}
4791	#ifdef VBOX_STRICT
4792	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
4793	{
4794	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
4795	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
4796	}
4797	#endif
4798
4799	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbR0.aEntries); i++)
4800	if (pVM->pgm.s.PhysTlbR0.aEntries[i].pMap == pChunk)
4801	return 0;
4802	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbR3.aEntries); i++)
4803	if (pVM->pgm.s.PhysTlbR3.aEntries[i].pMap == pChunk)
4804	return 0;
4805
4806	pArg->pChunk = pChunk;
4807	return 0;
4808	}
4809
4810
4811	/**
4812	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
4813	*
4814	* The candidate will not be part of any TLBs, so no need to flush
4815	* anything afterwards.
4816	*
4817	* @returns Chunk id.
4818	* @param pVM The cross context VM structure.
4819	*/
4820	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
4821	{
4822	PGM_LOCK_ASSERT_OWNER(pVM);
4823
4824	/*
4825	* Enumerate the age tree starting with the left most node.
4826	*/
4827	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4828	PGMR3PHYSCHUNKUNMAPCB Args;
4829	Args.pVM = pVM;
4830	Args.pChunk = NULL;
4831	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
4832	Assert(Args.pChunk);
4833	if (Args.pChunk)
4834	{
4835	Assert(Args.pChunk->cRefs == 0);
4836	Assert(Args.pChunk->cPermRefs == 0);
4837	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4838	return Args.pChunk->Core.Key;
4839	}
4840
4841	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkFindCandidate, a);
4842	return INT32_MAX;
4843	}
4844
4845
4846	/**
4847	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
4848	*
4849	* This is only called on one of the EMTs while the other ones are waiting for
4850	* it to complete this function.
4851	*
4852	* @returns VINF_SUCCESS (VBox strict status code).
4853	* @param pVM The cross context VM structure.
4854	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
4855	* @param pvUser User pointer. Unused
4856	*
4857	*/
4858	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
4859	{
4860	int rc = VINF_SUCCESS;
4861	pgmLock(pVM);
4862	NOREF(pVCpu); NOREF(pvUser);
4863
4864	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
4865	{
4866	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
4867	/** @todo also not really efficient to unmap a chunk that contains PD
4868	* or PT pages. */
4869	pgmR3PoolClearAllRendezvous(pVM, pVM->apCpusR3[0], NULL /* no need to flush the REM TLB as we already did that above */);
4870
4871	/*
4872	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
4873	*/
4874	GMMMAPUNMAPCHUNKREQ Req;
4875	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
4876	Req.Hdr.cbReq = sizeof(Req);
4877	Req.pvR3 = NULL;
4878	Req.idChunkMap = NIL_GMM_CHUNKID;
4879	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
4880	if (Req.idChunkUnmap != INT32_MAX)
4881	{
4882	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
4883	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
4884	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkUnmap, a);
4885	if (RT_SUCCESS(rc))
4886	{
4887	/*
4888	* Remove the unmapped one.
4889	*/
4890	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
4891	AssertRelease(pUnmappedChunk);
4892	AssertRelease(!pUnmappedChunk->cRefs);
4893	AssertRelease(!pUnmappedChunk->cPermRefs);
4894	pUnmappedChunk->pv = NULL;
4895	pUnmappedChunk->Core.Key = UINT32_MAX;
4896	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
4897	MMR3HeapFree(pUnmappedChunk);
4898	#else
4899	MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
4900	#endif
4901	pVM->pgm.s.ChunkR3Map.c--;
4902	pVM->pgm.s.cUnmappedChunks++;
4903
4904	/*
4905	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
4906	*/
4907	/** @todo We should not flush chunks which include cr3 mappings. */
4908	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4909	{
4910	PPGMCPU pPGM = &pVM->apCpusR3[idCpu]->pgm.s;
4911
4912	pPGM->pGst32BitPdR3 = NULL;
4913	pPGM->pGstPaePdptR3 = NULL;
4914	pPGM->pGstAmd64Pml4R3 = NULL;
4915	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4916	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
4917	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
4918	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
4919	#endif
4920	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
4921	{
4922	pPGM->apGstPaePDsR3[i] = NULL;
4923	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4924	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
4925	#endif
4926	}
4927
4928	/* Flush REM TLBs. */
4929	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
4930	}
4931	#ifdef VBOX_WITH_REM
4932	/* Flush REM translation blocks. */
4933	REMFlushTBs(pVM);
4934	#endif
4935	}
4936	}
4937	}
4938	pgmUnlock(pVM);
4939	return rc;
4940	}
4941
4942	/**
4943	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
4944	*
4945	* @returns VBox status code.
4946	* @param pVM The cross context VM structure.
4947	*/
4948	void pgmR3PhysUnmapChunk(PVM pVM)
4949	{
4950	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
4951	AssertRC(rc);
4952	}
4953
4954
4955	/**
4956	* Maps the given chunk into the ring-3 mapping cache.
4957	*
4958	* This will call ring-0.
4959	*
4960	* @returns VBox status code.
4961	* @param pVM The cross context VM structure.
4962	* @param idChunk The chunk in question.
4963	* @param ppChunk Where to store the chunk tracking structure.
4964	*
4965	* @remarks Called from within the PGM critical section.
4966	* @remarks Can be called from any thread!
4967	*/
4968	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
4969	{
4970	int rc;
4971
4972	PGM_LOCK_ASSERT_OWNER(pVM);
4973
4974	/*
4975	* Move the chunk time forward.
4976	*/
4977	pVM->pgm.s.ChunkR3Map.iNow++;
4978	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
4979	{
4980	pVM->pgm.s.ChunkR3Map.iNow = 4;
4981	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
4982	}
4983
4984	/*
4985	* Allocate a new tracking structure first.
4986	*/
4987	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
4988	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
4989	#else
4990	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
4991	#endif
4992	AssertReturn(pChunk, VERR_NO_MEMORY);
4993	pChunk->Core.Key = idChunk;
4994	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
4995
4996	/*
4997	* Request the ring-0 part to map the chunk in question.
4998	*/
4999	GMMMAPUNMAPCHUNKREQ Req;
5000	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5001	Req.Hdr.cbReq = sizeof(Req);
5002	Req.pvR3 = NULL;
5003	Req.idChunkMap = idChunk;
5004	Req.idChunkUnmap = NIL_GMM_CHUNKID;
5005
5006	/* Must be callable from any thread, so can't use VMMR3CallR0. */
5007	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
5008	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5009	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatChunkMap, a);
5010	if (RT_SUCCESS(rc))
5011	{
5012	pChunk->pv = Req.pvR3;
5013
5014	/*
5015	* If we're running out of virtual address space, then we should
5016	* unmap another chunk.
5017	*
5018	* Currently, an unmap operation requires that all other virtual CPUs
5019	* are idling and not by chance making use of the memory we're
5020	* unmapping. So, we create an async unmap operation here.
5021	*
5022	* Now, when creating or restoring a saved state this wont work very
5023	* well since we may want to restore all guest RAM + a little something.
5024	* So, we have to do the unmap synchronously. Fortunately for us
5025	* though, during these operations the other virtual CPUs are inactive
5026	* and it should be safe to do this.
5027	*/
5028	/** @todo Eventually we should lock all memory when used and do
5029	* map+unmap as one kernel call without any rendezvous or
5030	* other precautions. */
5031	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
5032	{
5033	switch (VMR3GetState(pVM))
5034	{
5035	case VMSTATE_LOADING:
5036	case VMSTATE_SAVING:
5037	{
5038	PVMCPU pVCpu = VMMGetCpu(pVM);
5039	if ( pVCpu
5040	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
5041	{
5042	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
5043	break;
5044	}
5045	}
5046	RT_FALL_THRU();
5047	default:
5048	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
5049	AssertRC(rc);
5050	break;
5051	}
5052	}
5053
5054	/*
5055	* Update the tree. We must do this after any unmapping to make sure
5056	* the chunk we're going to return isn't unmapped by accident.
5057	*/
5058	AssertPtr(Req.pvR3);
5059	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
5060	AssertRelease(fRc);
5061	pVM->pgm.s.ChunkR3Map.c++;
5062	pVM->pgm.s.cMappedChunks++;
5063	}
5064	else
5065	{
5066	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
5067	* should probably restrict ourselves on linux. */
5068	AssertRC(rc);
5069	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
5070	MMR3HeapFree(pChunk);
5071	#else
5072	MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
5073	#endif
5074	pChunk = NULL;
5075	}
5076
5077	*ppChunk = pChunk;
5078	return rc;
5079	}
5080
5081
5082	/**
5083	* For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
5084	*
5085	* @returns see pgmR3PhysChunkMap.
5086	* @param pVM The cross context VM structure.
5087	* @param idChunk The chunk to map.
5088	*/
5089	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
5090	{
5091	PPGMCHUNKR3MAP pChunk;
5092	int rc;
5093
5094	pgmLock(pVM);
5095	rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
5096	pgmUnlock(pVM);
5097	return rc;
5098	}
5099
5100
5101	/**
5102	* Invalidates the TLB for the ring-3 mapping cache.
5103	*
5104	* @param pVM The cross context VM structure.
5105	*/
5106	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
5107	{
5108	pgmLock(pVM);
5109	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5110	{
5111	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
5112	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
5113	}
5114	/* The page map TLB references chunks, so invalidate that one too. */
5115	pgmPhysInvalidatePageMapTLB(pVM);
5116	pgmUnlock(pVM);
5117	}
5118
5119
5120	/**
5121	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE to allocate a large
5122	* (2MB) page for use with a nested paging PDE.
5123	*
5124	* @returns The following VBox status codes.
5125	* @retval VINF_SUCCESS on success.
5126	* @retval VINF_EM_NO_MEMORY if we're out of memory.
5127	*
5128	* @param pVM The cross context VM structure.
5129	* @param GCPhys GC physical start address of the 2 MB range
5130	*/
5131	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys)
5132	{
5133	#ifdef PGM_WITH_LARGE_PAGES
5134	uint64_t u64TimeStamp1, u64TimeStamp2;
5135
5136	pgmLock(pVM);
5137
5138	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
5139	u64TimeStamp1 = RTTimeMilliTS();
5140	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
5141	u64TimeStamp2 = RTTimeMilliTS();
5142	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatAllocLargePage, a);
5143	if (RT_SUCCESS(rc))
5144	{
5145	Assert(pVM->pgm.s.cLargeHandyPages == 1);
5146
5147	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
5148	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
5149
5150	void *pv;
5151
5152	/* Map the large page into our address space.
5153	*
5154	* Note: assuming that within the 2 MB range:
5155	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
5156	* - user space mapping is continuous as well
5157	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
5158	*/
5159	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
5160	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", idPage, HCPhys, rc));
5161
5162	if (RT_SUCCESS(rc))
5163	{
5164	/*
5165	* Clear the pages.
5166	*/
5167	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
5168	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
5169	{
5170	ASMMemZeroPage(pv);
5171
5172	PPGMPAGE pPage;
5173	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
5174	AssertRC(rc);
5175
5176	Assert(PGM_PAGE_IS_ZERO(pPage));
5177	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRZPageReplaceZero);
5178	pVM->pgm.s.cZeroPages--;
5179
5180	/*
5181	* Do the PGMPAGE modifications.
5182	*/
5183	pVM->pgm.s.cPrivatePages++;
5184	PGM_PAGE_SET_HCPHYS(pVM, pPage, HCPhys);
5185	PGM_PAGE_SET_PAGEID(pVM, pPage, idPage);
5186	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
5187	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE);
5188	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5189	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5190
5191	/* Somewhat dirty assumption that page ids are increasing. */
5192	idPage++;
5193
5194	HCPhys += PAGE_SIZE;
5195	GCPhys += PAGE_SIZE;
5196
5197	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
5198
5199	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
5200	}
5201	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatClearLargePage, b);
5202
5203	/* Flush all TLBs. */
5204	PGM_INVL_ALL_VCPU_TLBS(pVM);
5205	pgmPhysInvalidatePageMapTLB(pVM);
5206	}
5207	pVM->pgm.s.cLargeHandyPages = 0;
5208	}
5209
5210	if (RT_SUCCESS(rc))
5211	{
5212	static uint32_t cTimeOut = 0;
5213	uint64_t u64TimeStampDelta = u64TimeStamp2 - u64TimeStamp1;
5214
5215	if (u64TimeStampDelta > 100)
5216	{
5217	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatLargePageOverflow);
5218	if ( ++cTimeOut > 10
5219	\|\| u64TimeStampDelta > 1000 /* more than one second forces an early retirement from allocating large pages. */)
5220	{
5221	/* If repeated attempts to allocate a large page takes more than 100 ms, then we fall back to normal 4k pages.
5222	* E.g. Vista 64 tries to move memory around, which takes a huge amount of time.
5223	*/
5224	LogRel(("PGMR3PhysAllocateLargePage: allocating large pages takes too long (last attempt %d ms; nr of timeouts %d); DISABLE\n", u64TimeStampDelta, cTimeOut));
5225	PGMSetLargePageUsage(pVM, false);
5226	}
5227	}
5228	else
5229	if (cTimeOut > 0)
5230	cTimeOut--;
5231	}
5232
5233	pgmUnlock(pVM);
5234	return rc;
5235	#else
5236	RT_NOREF(pVM, GCPhys);
5237	return VERR_NOT_IMPLEMENTED;
5238	#endif /* PGM_WITH_LARGE_PAGES */
5239	}
5240
5241
5242	/**
5243	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
5244	*
5245	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
5246	* signal and clear the out of memory condition. When contracted, this API is
5247	* used to try clear the condition when the user wants to resume.
5248	*
5249	* @returns The following VBox status codes.
5250	* @retval VINF_SUCCESS on success. FFs cleared.
5251	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
5252	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
5253	*
5254	* @param pVM The cross context VM structure.
5255	*
5256	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
5257	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
5258	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
5259	* handler.
5260	*/
5261	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
5262	{
5263	pgmLock(pVM);
5264
5265	/*
5266	* Allocate more pages, noting down the index of the first new page.
5267	*/
5268	uint32_t iClear = pVM->pgm.s.cHandyPages;
5269	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
5270	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
5271	int rcAlloc = VINF_SUCCESS;
5272	int rcSeed = VINF_SUCCESS;
5273	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5274	while (rc == VERR_GMM_SEED_ME)
5275	{
5276	void *pvChunk;
5277	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
5278	if (RT_SUCCESS(rc))
5279	{
5280	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
5281	if (RT_FAILURE(rc))
5282	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
5283	}
5284	if (RT_SUCCESS(rc))
5285	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5286	}
5287
5288	/** @todo we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
5289	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
5290	&& pVM->pgm.s.cHandyPages > 0)
5291	{
5292	/* Still handy pages left, so don't panic. */
5293	rc = VINF_SUCCESS;
5294	}
5295
5296	if (RT_SUCCESS(rc))
5297	{
5298	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
5299	Assert(pVM->pgm.s.cHandyPages > 0);
5300	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5301	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
5302
5303	#ifdef VBOX_STRICT
5304	uint32_t i;
5305	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
5306	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
5307	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
5308	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
5309	break;
5310	if (i != pVM->pgm.s.cHandyPages)
5311	{
5312	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
5313	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
5314	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
5315	RTAssertMsg2Add("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%\n", j,
5316	pVM->pgm.s.aHandyPages[j].idPage,
5317	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
5318	pVM->pgm.s.aHandyPages[j].idSharedPage,
5319	j == i ? " <---" : "");
5320	RTAssertPanic();
5321	}
5322	#endif
5323	/*
5324	* Clear the pages.
5325	*/
5326	while (iClear < pVM->pgm.s.cHandyPages)
5327	{
5328	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
5329	void *pv;
5330	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
5331	AssertLogRelMsgBreak(RT_SUCCESS(rc),
5332	("%u/%u: idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n",
5333	iClear, pVM->pgm.s.cHandyPages, pPage->idPage, pPage->HCPhysGCPhys, rc));
5334	ASMMemZeroPage(pv);
5335	iClear++;
5336	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
5337	}
5338	}
5339	else
5340	{
5341	uint64_t cAllocPages, cMaxPages, cBalloonPages;
5342
5343	/*
5344	* We should never get here unless there is a genuine shortage of
5345	* memory (or some internal error). Flag the error so the VM can be
5346	* suspended ASAP and the user informed. If we're totally out of
5347	* handy pages we will return failure.
5348	*/
5349	/* Report the failure. */
5350	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
5351	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
5352	rc, rcAlloc, rcSeed,
5353	pVM->pgm.s.cHandyPages,
5354	pVM->pgm.s.cAllPages,
5355	pVM->pgm.s.cPrivatePages,
5356	pVM->pgm.s.cSharedPages,
5357	pVM->pgm.s.cZeroPages));
5358
5359	if (GMMR3QueryMemoryStats(pVM, &cAllocPages, &cMaxPages, &cBalloonPages) == VINF_SUCCESS)
5360	{
5361	LogRel(("GMM: Statistics:\n"
5362	" Allocated pages: %RX64\n"
5363	" Maximum pages: %RX64\n"
5364	" Ballooned pages: %RX64\n", cAllocPages, cMaxPages, cBalloonPages));
5365	}
5366
5367	if ( rc != VERR_NO_MEMORY
5368	&& rc != VERR_NO_PHYS_MEMORY
5369	&& rc != VERR_LOCK_FAILED)
5370	{
5371	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5372	{
5373	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
5374	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
5375	pVM->pgm.s.aHandyPages[i].idSharedPage));
5376	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
5377	if (idPage != NIL_GMM_PAGEID)
5378	{
5379	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
5380	pRam;
5381	pRam = pRam->pNextR3)
5382	{
5383	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
5384	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5385	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
5386	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
5387	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
5388	}
5389	}
5390	}
5391	}
5392
5393	if (rc == VERR_NO_MEMORY)
5394	{
5395	uint64_t cbHostRamAvail = 0;
5396	int rc2 = RTSystemQueryAvailableRam(&cbHostRamAvail);
5397	if (RT_SUCCESS(rc2))
5398	LogRel(("Host RAM: %RU64MB available\n", cbHostRamAvail / _1M));
5399	else
5400	LogRel(("Cannot determine the amount of available host memory\n"));
5401	}
5402
5403	/* Set the FFs and adjust rc. */
5404	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5405	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
5406	if ( rc == VERR_NO_MEMORY
5407	\|\| rc == VERR_NO_PHYS_MEMORY
5408	\|\| rc == VERR_LOCK_FAILED)
5409	rc = VINF_EM_NO_MEMORY;
5410	}
5411
5412	pgmUnlock(pVM);
5413	return rc;
5414	}
5415
5416
5417	/**
5418	* Frees the specified RAM page and replaces it with the ZERO page.
5419	*
5420	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
5421	*
5422	* @param pVM The cross context VM structure.
5423	* @param pReq Pointer to the request.
5424	* @param pcPendingPages Where the number of pages waiting to be freed are
5425	* kept. This will normally be incremented.
5426	* @param pPage Pointer to the page structure.
5427	* @param GCPhys The guest physical address of the page, if applicable.
5428	* @param enmNewType New page type for NEM notification, since several
5429	* callers will change the type upon successful return.
5430	*
5431	* @remarks The caller must own the PGM lock.
5432	*/
5433	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
5434	PGMPAGETYPE enmNewType)
5435	{
5436	/*
5437	* Assert sanity.
5438	*/
5439	PGM_LOCK_ASSERT_OWNER(pVM);
5440	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
5441	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
5442	{
5443	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5444	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
5445	}
5446
5447	/** @todo What about ballooning of large pages??! */
5448	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
5449	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
5450
5451	if ( PGM_PAGE_IS_ZERO(pPage)
5452	\|\| PGM_PAGE_IS_BALLOONED(pPage))
5453	return VINF_SUCCESS;
5454
5455	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
5456	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
5457	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
5458	\|\| idPage > GMM_PAGEID_LAST
5459	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
5460	{
5461	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5462	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
5463	}
5464	const RTHCPHYS HCPhysPrev = PGM_PAGE_GET_HCPHYS(pPage);
5465
5466	/* update page count stats. */
5467	if (PGM_PAGE_IS_SHARED(pPage))
5468	pVM->pgm.s.cSharedPages--;
5469	else
5470	pVM->pgm.s.cPrivatePages--;
5471	pVM->pgm.s.cZeroPages++;
5472
5473	/* Deal with write monitored pages. */
5474	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
5475	{
5476	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
5477	pVM->pgm.s.cWrittenToPages++;
5478	}
5479
5480	/*
5481	* pPage = ZERO page.
5482	*/
5483	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
5484	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
5485	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
5486	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
5487	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5488	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5489
5490	/* Flush physical page map TLB entry. */
5491	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
5492
5493	/* Notify NEM. */
5494	/** @todo consider doing batch NEM notifications. */
5495	if (VM_IS_NEM_ENABLED(pVM))
5496	{
5497	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pPage);
5498	NEMHCNotifyPhysPageChanged(pVM, GCPhys, HCPhysPrev, pVM->pgm.s.HCPhysZeroPg,
5499	pgmPhysPageCalcNemProtection(pPage, enmNewType), enmNewType, &u2State);
5500	PGM_PAGE_SET_NEM_STATE(pPage, u2State);
5501	}
5502
5503	/*
5504	* Make sure it's not in the handy page array.
5505	*/
5506	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5507	{
5508	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
5509	{
5510	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
5511	break;
5512	}
5513	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
5514	{
5515	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
5516	break;
5517	}
5518	}
5519
5520	/*
5521	* Push it onto the page array.
5522	*/
5523	uint32_t iPage = *pcPendingPages;
5524	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
5525	*pcPendingPages += 1;
5526
5527	pReq->aPages[iPage].idPage = idPage;
5528
5529	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
5530	return VINF_SUCCESS;
5531
5532	/*
5533	* Flush the pages.
5534	*/
5535	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
5536	if (RT_SUCCESS(rc))
5537	{
5538	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
5539	*pcPendingPages = 0;
5540	}
5541	return rc;
5542	}
5543
5544
5545	/**
5546	* Converts a GC physical address to a HC ring-3 pointer, with some
5547	* additional checks.
5548	*
5549	* @returns VBox status code.
5550	* @retval VINF_SUCCESS on success.
5551	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
5552	* access handler of some kind.
5553	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
5554	* accesses or is odd in any way.
5555	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
5556	*
5557	* @param pVM The cross context VM structure.
5558	* @param GCPhys The GC physical address to convert. Since this is only
5559	* used for filling the REM TLB, the A20 mask must be
5560	* applied before calling this API.
5561	* @param fWritable Whether write access is required.
5562	* @param ppv Where to store the pointer corresponding to GCPhys on
5563	* success.
5564	*/
5565	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
5566	{
5567	pgmLock(pVM);
5568	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
5569
5570	PPGMRAMRANGE pRam;
5571	PPGMPAGE pPage;
5572	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
5573	if (RT_SUCCESS(rc))
5574	{
5575	if (PGM_PAGE_IS_BALLOONED(pPage))
5576	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5577	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
5578	rc = VINF_SUCCESS;
5579	else
5580	{
5581	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
5582	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5583	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
5584	{
5585	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
5586	* in -norawr0 mode. */
5587	if (fWritable)
5588	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5589	}
5590	else
5591	{
5592	/* Temporarily disabled physical handler(s), since the recompiler
5593	doesn't get notified when it's reset we'll have to pretend it's
5594	operating normally. */
5595	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
5596	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5597	else
5598	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5599	}
5600	}
5601	if (RT_SUCCESS(rc))
5602	{
5603	int rc2;
5604
5605	/* Make sure what we return is writable. */
5606	if (fWritable)
5607	switch (PGM_PAGE_GET_STATE(pPage))
5608	{
5609	case PGM_PAGE_STATE_ALLOCATED:
5610	break;
5611	case PGM_PAGE_STATE_BALLOONED:
5612	AssertFailed();
5613	break;
5614	case PGM_PAGE_STATE_ZERO:
5615	case PGM_PAGE_STATE_SHARED:
5616	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
5617	break;
5618	RT_FALL_THRU();
5619	case PGM_PAGE_STATE_WRITE_MONITORED:
5620	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
5621	AssertLogRelRCReturn(rc2, rc2);
5622	break;
5623	}
5624
5625	/* Get a ring-3 mapping of the address. */
5626	PPGMPAGER3MAPTLBE pTlbe;
5627	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
5628	AssertLogRelRCReturn(rc2, rc2);
5629	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
5630	/** @todo mapping/locking hell; this isn't horribly efficient since
5631	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
5632
5633	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
5634	}
5635	else
5636	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
5637
5638	/* else: handler catching all access, no pointer returned. */
5639	}
5640	else
5641	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
5642
5643	pgmUnlock(pVM);
5644	return rc;
5645	}
5646

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 80386

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