PGMPhys.cpp@ 91874

Last change on this file since 91874 was 91874, checked in by vboxsync, 3 years ago
VMM: Removed PGM_WITHOUT_MAPPINGS and associated mapping code. [regression fix] bugref:9517
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1	/* $Id: PGMPhys.cpp 91874 2021-10-20 09:11:06Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
24	#include <VBox/vmm/pgm.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/iom.h>
27	#include <VBox/vmm/mm.h>
28	#include <VBox/vmm/nem.h>
29	#include <VBox/vmm/stam.h>
30	#include <VBox/vmm/pdmdev.h>
31	#include "PGMInternal.h"
32	#include <VBox/vmm/vmcc.h>
33
34	#include "PGMInline.h"
35
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#ifdef VBOX_STRICT
44	# include <iprt/crc.h>
45	#endif
46	#include <iprt/thread.h>
47	#include <iprt/string.h>
48	#include <iprt/system.h>
49
50
51	/*********************************************************************************************************************************
52	* Defined Constants And Macros *
53	*********************************************************************************************************************************/
54	/** The number of pages to free in one batch. */
55	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
56
57
58	/*
59	* PGMR3PhysReadU8-64
60	* PGMR3PhysWriteU8-64
61	*/
62	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
63	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
64	#define PGMPHYS_DATASIZE 1
65	#define PGMPHYS_DATATYPE uint8_t
66	#include "PGMPhysRWTmpl.h"
67
68	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
69	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
70	#define PGMPHYS_DATASIZE 2
71	#define PGMPHYS_DATATYPE uint16_t
72	#include "PGMPhysRWTmpl.h"
73
74	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
75	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
76	#define PGMPHYS_DATASIZE 4
77	#define PGMPHYS_DATATYPE uint32_t
78	#include "PGMPhysRWTmpl.h"
79
80	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
81	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
82	#define PGMPHYS_DATASIZE 8
83	#define PGMPHYS_DATATYPE uint64_t
84	#include "PGMPhysRWTmpl.h"
85
86
87	/**
88	* EMT worker for PGMR3PhysReadExternal.
89	*/
90	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
91	PGMACCESSORIGIN enmOrigin)
92	{
93	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
94	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
95	return VINF_SUCCESS;
96	}
97
98
99	/**
100	* Read from physical memory, external users.
101	*
102	* @returns VBox status code.
103	* @retval VINF_SUCCESS.
104	*
105	* @param pVM The cross context VM structure.
106	* @param GCPhys Physical address to read from.
107	* @param pvBuf Where to read into.
108	* @param cbRead How many bytes to read.
109	* @param enmOrigin Who is calling.
110	*
111	* @thread Any but EMTs.
112	*/
113	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
114	{
115	VM_ASSERT_OTHER_THREAD(pVM);
116
117	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
118	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
119
120	PGM_LOCK_VOID(pVM);
121
122	/*
123	* Copy loop on ram ranges.
124	*/
125	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
126	for (;;)
127	{
128	/* Inside range or not? */
129	if (pRam && GCPhys >= pRam->GCPhys)
130	{
131	/*
132	* Must work our way thru this page by page.
133	*/
134	RTGCPHYS off = GCPhys - pRam->GCPhys;
135	while (off < pRam->cb)
136	{
137	unsigned iPage = off >> PAGE_SHIFT;
138	PPGMPAGE pPage = &pRam->aPages[iPage];
139
140	/*
141	* If the page has an ALL access handler, we'll have to
142	* delegate the job to EMT.
143	*/
144	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
145	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
146	{
147	PGM_UNLOCK(pVM);
148
149	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
150	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
151	}
152	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
153
154	/*
155	* Simple stuff, go ahead.
156	*/
157	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
158	if (cb > cbRead)
159	cb = cbRead;
160	PGMPAGEMAPLOCK PgMpLck;
161	const void *pvSrc;
162	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
163	if (RT_SUCCESS(rc))
164	{
165	memcpy(pvBuf, pvSrc, cb);
166	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
167	}
168	else
169	{
170	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
171	pRam->GCPhys + off, pPage, rc));
172	memset(pvBuf, 0xff, cb);
173	}
174
175	/* next page */
176	if (cb >= cbRead)
177	{
178	PGM_UNLOCK(pVM);
179	return VINF_SUCCESS;
180	}
181	cbRead -= cb;
182	off += cb;
183	GCPhys += cb;
184	pvBuf = (char *)pvBuf + cb;
185	} /* walk pages in ram range. */
186	}
187	else
188	{
189	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
190
191	/*
192	* Unassigned address space.
193	*/
194	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
195	if (cb >= cbRead)
196	{
197	memset(pvBuf, 0xff, cbRead);
198	break;
199	}
200	memset(pvBuf, 0xff, cb);
201
202	cbRead -= cb;
203	pvBuf = (char *)pvBuf + cb;
204	GCPhys += cb;
205	}
206
207	/* Advance range if necessary. */
208	while (pRam && GCPhys > pRam->GCPhysLast)
209	pRam = pRam->CTX_SUFF(pNext);
210	} /* Ram range walk */
211
212	PGM_UNLOCK(pVM);
213
214	return VINF_SUCCESS;
215	}
216
217
218	/**
219	* EMT worker for PGMR3PhysWriteExternal.
220	*/
221	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
222	PGMACCESSORIGIN enmOrigin)
223	{
224	/** @todo VERR_EM_NO_MEMORY */
225	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
226	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
227	return VINF_SUCCESS;
228	}
229
230
231	/**
232	* Write to physical memory, external users.
233	*
234	* @returns VBox status code.
235	* @retval VINF_SUCCESS.
236	* @retval VERR_EM_NO_MEMORY.
237	*
238	* @param pVM The cross context VM structure.
239	* @param GCPhys Physical address to write to.
240	* @param pvBuf What to write.
241	* @param cbWrite How many bytes to write.
242	* @param enmOrigin Who is calling.
243	*
244	* @thread Any but EMTs.
245	*/
246	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
247	{
248	VM_ASSERT_OTHER_THREAD(pVM);
249
250	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
251	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
252	GCPhys, cbWrite, enmOrigin));
253	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
254	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
255
256	PGM_LOCK_VOID(pVM);
257
258	/*
259	* Copy loop on ram ranges, stop when we hit something difficult.
260	*/
261	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
262	for (;;)
263	{
264	/* Inside range or not? */
265	if (pRam && GCPhys >= pRam->GCPhys)
266	{
267	/*
268	* Must work our way thru this page by page.
269	*/
270	RTGCPTR off = GCPhys - pRam->GCPhys;
271	while (off < pRam->cb)
272	{
273	RTGCPTR iPage = off >> PAGE_SHIFT;
274	PPGMPAGE pPage = &pRam->aPages[iPage];
275
276	/*
277	* Is the page problematic, we have to do the work on the EMT.
278	*
279	* Allocating writable pages and access handlers are
280	* problematic, write monitored pages are simple and can be
281	* dealt with here.
282	*/
283	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
284	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
285	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
286	{
287	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
288	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
289	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
290	else
291	{
292	PGM_UNLOCK(pVM);
293
294	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
295	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
296	}
297	}
298	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
299
300	/*
301	* Simple stuff, go ahead.
302	*/
303	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
304	if (cb > cbWrite)
305	cb = cbWrite;
306	PGMPAGEMAPLOCK PgMpLck;
307	void *pvDst;
308	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
309	if (RT_SUCCESS(rc))
310	{
311	memcpy(pvDst, pvBuf, cb);
312	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
313	}
314	else
315	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
316	pRam->GCPhys + off, pPage, rc));
317
318	/* next page */
319	if (cb >= cbWrite)
320	{
321	PGM_UNLOCK(pVM);
322	return VINF_SUCCESS;
323	}
324
325	cbWrite -= cb;
326	off += cb;
327	GCPhys += cb;
328	pvBuf = (const char *)pvBuf + cb;
329	} /* walk pages in ram range */
330	}
331	else
332	{
333	/*
334	* Unassigned address space, skip it.
335	*/
336	if (!pRam)
337	break;
338	size_t cb = pRam->GCPhys - GCPhys;
339	if (cb >= cbWrite)
340	break;
341	cbWrite -= cb;
342	pvBuf = (const char *)pvBuf + cb;
343	GCPhys += cb;
344	}
345
346	/* Advance range if necessary. */
347	while (pRam && GCPhys > pRam->GCPhysLast)
348	pRam = pRam->CTX_SUFF(pNext);
349	} /* Ram range walk */
350
351	PGM_UNLOCK(pVM);
352	return VINF_SUCCESS;
353	}
354
355
356	/**
357	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
358	*
359	* @returns see PGMR3PhysGCPhys2CCPtrExternal
360	* @param pVM The cross context VM structure.
361	* @param pGCPhys Pointer to the guest physical address.
362	* @param ppv Where to store the mapping address.
363	* @param pLock Where to store the lock.
364	*/
365	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
366	{
367	/*
368	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
369	* an access handler after it succeeds.
370	*/
371	int rc = PGM_LOCK(pVM);
372	AssertRCReturn(rc, rc);
373
374	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
375	if (RT_SUCCESS(rc))
376	{
377	PPGMPAGEMAPTLBE pTlbe;
378	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
379	AssertFatalRC(rc2);
380	PPGMPAGE pPage = pTlbe->pPage;
381	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
382	{
383	PGMPhysReleasePageMappingLock(pVM, pLock);
384	rc = VERR_PGM_PHYS_PAGE_RESERVED;
385	}
386	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
387	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
388	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
389	#endif
390	)
391	{
392	/* We must flush any corresponding pgm pool page here, otherwise we'll
393	* not be informed about writes and keep bogus gst->shw mappings around.
394	*/
395	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
396	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
397	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
398	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
399	}
400	}
401
402	PGM_UNLOCK(pVM);
403	return rc;
404	}
405
406
407	/**
408	* Requests the mapping of a guest page into ring-3, external threads.
409	*
410	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
411	* release it.
412	*
413	* This API will assume your intention is to write to the page, and will
414	* therefore replace shared and zero pages. If you do not intend to modify the
415	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
416	*
417	* @returns VBox status code.
418	* @retval VINF_SUCCESS on success.
419	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
420	* backing or if the page has any active access handlers. The caller
421	* must fall back on using PGMR3PhysWriteExternal.
422	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
423	*
424	* @param pVM The cross context VM structure.
425	* @param GCPhys The guest physical address of the page that should be mapped.
426	* @param ppv Where to store the address corresponding to GCPhys.
427	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
428	*
429	* @remark Avoid calling this API from within critical sections (other than the
430	* PGM one) because of the deadlock risk when we have to delegating the
431	* task to an EMT.
432	* @thread Any.
433	*/
434	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
435	{
436	AssertPtr(ppv);
437	AssertPtr(pLock);
438
439	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
440
441	int rc = PGM_LOCK(pVM);
442	AssertRCReturn(rc, rc);
443
444	/*
445	* Query the Physical TLB entry for the page (may fail).
446	*/
447	PPGMPAGEMAPTLBE pTlbe;
448	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
449	if (RT_SUCCESS(rc))
450	{
451	PPGMPAGE pPage = pTlbe->pPage;
452	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
453	rc = VERR_PGM_PHYS_PAGE_RESERVED;
454	else
455	{
456	/*
457	* If the page is shared, the zero page, or being write monitored
458	* it must be converted to an page that's writable if possible.
459	* We can only deal with write monitored pages here, the rest have
460	* to be on an EMT.
461	*/
462	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
463	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
464	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
465	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
466	#endif
467	)
468	{
469	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
470	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
471	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
472	&& !pgmPoolIsDirtyPage(pVM, GCPhys) /** @todo we're very likely doing this twice. */
473	#endif
474	)
475	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
476	else
477	{
478	PGM_UNLOCK(pVM);
479
480	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
481	pVM, &GCPhys, ppv, pLock);
482	}
483	}
484
485	/*
486	* Now, just perform the locking and calculate the return address.
487	*/
488	PPGMPAGEMAP pMap = pTlbe->pMap;
489	if (pMap)
490	pMap->cRefs++;
491
492	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
493	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
494	{
495	if (cLocks == 0)
496	pVM->pgm.s.cWriteLockedPages++;
497	PGM_PAGE_INC_WRITE_LOCKS(pPage);
498	}
499	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
500	{
501	PGM_PAGE_INC_WRITE_LOCKS(pPage);
502	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
503	if (pMap)
504	pMap->cRefs++; /* Extra ref to prevent it from going away. */
505	}
506
507	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
508	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
509	pLock->pvMap = pMap;
510	}
511	}
512
513	PGM_UNLOCK(pVM);
514	return rc;
515	}
516
517
518	/**
519	* Requests the mapping of a guest page into ring-3, external threads.
520	*
521	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
522	* release it.
523	*
524	* @returns VBox status code.
525	* @retval VINF_SUCCESS on success.
526	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
527	* backing or if the page as an active ALL access handler. The caller
528	* must fall back on using PGMPhysRead.
529	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
530	*
531	* @param pVM The cross context VM structure.
532	* @param GCPhys The guest physical address of the page that should be mapped.
533	* @param ppv Where to store the address corresponding to GCPhys.
534	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
535	*
536	* @remark Avoid calling this API from within critical sections (other than
537	* the PGM one) because of the deadlock risk.
538	* @thread Any.
539	*/
540	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
541	{
542	int rc = PGM_LOCK(pVM);
543	AssertRCReturn(rc, rc);
544
545	/*
546	* Query the Physical TLB entry for the page (may fail).
547	*/
548	PPGMPAGEMAPTLBE pTlbe;
549	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
550	if (RT_SUCCESS(rc))
551	{
552	PPGMPAGE pPage = pTlbe->pPage;
553	#if 1
554	/* MMIO pages doesn't have any readable backing. */
555	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
556	rc = VERR_PGM_PHYS_PAGE_RESERVED;
557	#else
558	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
559	rc = VERR_PGM_PHYS_PAGE_RESERVED;
560	#endif
561	else
562	{
563	/*
564	* Now, just perform the locking and calculate the return address.
565	*/
566	PPGMPAGEMAP pMap = pTlbe->pMap;
567	if (pMap)
568	pMap->cRefs++;
569
570	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
571	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
572	{
573	if (cLocks == 0)
574	pVM->pgm.s.cReadLockedPages++;
575	PGM_PAGE_INC_READ_LOCKS(pPage);
576	}
577	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
578	{
579	PGM_PAGE_INC_READ_LOCKS(pPage);
580	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
581	if (pMap)
582	pMap->cRefs++; /* Extra ref to prevent it from going away. */
583	}
584
585	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
586	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
587	pLock->pvMap = pMap;
588	}
589	}
590
591	PGM_UNLOCK(pVM);
592	return rc;
593	}
594
595
596	/**
597	* Requests the mapping of multiple guest page into ring-3, external threads.
598	*
599	* When you're done with the pages, call PGMPhysBulkReleasePageMappingLock()
600	* ASAP to release them.
601	*
602	* This API will assume your intention is to write to the pages, and will
603	* therefore replace shared and zero pages. If you do not intend to modify the
604	* pages, use the PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal() API.
605	*
606	* @returns VBox status code.
607	* @retval VINF_SUCCESS on success.
608	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
609	* backing or if any of the pages the page has any active access
610	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
611	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
612	* an invalid physical address.
613	*
614	* @param pVM The cross context VM structure.
615	* @param cPages Number of pages to lock.
616	* @param paGCPhysPages The guest physical address of the pages that
617	* should be mapped (@a cPages entries).
618	* @param papvPages Where to store the ring-3 mapping addresses
619	* corresponding to @a paGCPhysPages.
620	* @param paLocks Where to store the locking information that
621	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
622	* in length).
623	*
624	* @remark Avoid calling this API from within critical sections (other than the
625	* PGM one) because of the deadlock risk when we have to delegating the
626	* task to an EMT.
627	* @thread Any.
628	*/
629	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
630	void **papvPages, PPGMPAGEMAPLOCK paLocks)
631	{
632	Assert(cPages > 0);
633	AssertPtr(papvPages);
634	AssertPtr(paLocks);
635
636	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
637
638	int rc = PGM_LOCK(pVM);
639	AssertRCReturn(rc, rc);
640
641	/*
642	* Lock the pages one by one.
643	* The loop body is similar to PGMR3PhysGCPhys2CCPtrExternal.
644	*/
645	int32_t cNextYield = 128;
646	uint32_t iPage;
647	for (iPage = 0; iPage < cPages; iPage++)
648	{
649	if (--cNextYield > 0)
650	{ /* likely */ }
651	else
652	{
653	PGM_UNLOCK(pVM);
654	ASMNopPause();
655	PGM_LOCK_VOID(pVM);
656	cNextYield = 128;
657	}
658
659	/*
660	* Query the Physical TLB entry for the page (may fail).
661	*/
662	PPGMPAGEMAPTLBE pTlbe;
663	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
664	if (RT_SUCCESS(rc))
665	{ }
666	else
667	break;
668	PPGMPAGE pPage = pTlbe->pPage;
669
670	/*
671	* No MMIO or active access handlers.
672	*/
673	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
674	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
675	{ }
676	else
677	{
678	rc = VERR_PGM_PHYS_PAGE_RESERVED;
679	break;
680	}
681
682	/*
683	* The page must be in the allocated state and not be a dirty pool page.
684	* We can handle converting a write monitored page to an allocated one, but
685	* anything more complicated must be delegated to an EMT.
686	*/
687	bool fDelegateToEmt = false;
688	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
689	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
690	fDelegateToEmt = pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]);
691	#else
692	fDelegateToEmt = false;
693	#endif
694	else if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
695	{
696	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
697	if (!pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]))
698	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, paGCPhysPages[iPage]);
699	else
700	fDelegateToEmt = true;
701	#endif
702	}
703	else
704	fDelegateToEmt = true;
705	if (!fDelegateToEmt)
706	{ }
707	else
708	{
709	/* We could do this delegation in bulk, but considered too much work vs gain. */
710	PGM_UNLOCK(pVM);
711	rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
712	pVM, &paGCPhysPages[iPage], &papvPages[iPage], &paLocks[iPage]);
713	PGM_LOCK_VOID(pVM);
714	if (RT_FAILURE(rc))
715	break;
716	cNextYield = 128;
717	}
718
719	/*
720	* Now, just perform the locking and address calculation.
721	*/
722	PPGMPAGEMAP pMap = pTlbe->pMap;
723	if (pMap)
724	pMap->cRefs++;
725
726	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
727	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
728	{
729	if (cLocks == 0)
730	pVM->pgm.s.cWriteLockedPages++;
731	PGM_PAGE_INC_WRITE_LOCKS(pPage);
732	}
733	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
734	{
735	PGM_PAGE_INC_WRITE_LOCKS(pPage);
736	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", paGCPhysPages[iPage], pPage));
737	if (pMap)
738	pMap->cRefs++; /* Extra ref to prevent it from going away. */
739	}
740
741	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
742	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
743	paLocks[iPage].pvMap = pMap;
744	}
745
746	PGM_UNLOCK(pVM);
747
748	/*
749	* On failure we must unlock any pages we managed to get already.
750	*/
751	if (RT_FAILURE(rc) && iPage > 0)
752	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
753
754	return rc;
755	}
756
757
758	/**
759	* Requests the mapping of multiple guest page into ring-3, for reading only,
760	* external threads.
761	*
762	* When you're done with the pages, call PGMPhysReleasePageMappingLock() ASAP
763	* to release them.
764	*
765	* @returns VBox status code.
766	* @retval VINF_SUCCESS on success.
767	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
768	* backing or if any of the pages the page has an active ALL access
769	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
770	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
771	* an invalid physical address.
772	*
773	* @param pVM The cross context VM structure.
774	* @param cPages Number of pages to lock.
775	* @param paGCPhysPages The guest physical address of the pages that
776	* should be mapped (@a cPages entries).
777	* @param papvPages Where to store the ring-3 mapping addresses
778	* corresponding to @a paGCPhysPages.
779	* @param paLocks Where to store the lock information that
780	* pfnPhysReleasePageMappingLock needs (@a cPages
781	* in length).
782	*
783	* @remark Avoid calling this API from within critical sections (other than
784	* the PGM one) because of the deadlock risk.
785	* @thread Any.
786	*/
787	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
788	void const **papvPages, PPGMPAGEMAPLOCK paLocks)
789	{
790	Assert(cPages > 0);
791	AssertPtr(papvPages);
792	AssertPtr(paLocks);
793
794	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
795
796	int rc = PGM_LOCK(pVM);
797	AssertRCReturn(rc, rc);
798
799	/*
800	* Lock the pages one by one.
801	* The loop body is similar to PGMR3PhysGCPhys2CCPtrReadOnlyExternal.
802	*/
803	int32_t cNextYield = 256;
804	uint32_t iPage;
805	for (iPage = 0; iPage < cPages; iPage++)
806	{
807	if (--cNextYield > 0)
808	{ /* likely */ }
809	else
810	{
811	PGM_UNLOCK(pVM);
812	ASMNopPause();
813	PGM_LOCK_VOID(pVM);
814	cNextYield = 256;
815	}
816
817	/*
818	* Query the Physical TLB entry for the page (may fail).
819	*/
820	PPGMPAGEMAPTLBE pTlbe;
821	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
822	if (RT_SUCCESS(rc))
823	{ }
824	else
825	break;
826	PPGMPAGE pPage = pTlbe->pPage;
827
828	/*
829	* No MMIO or active all access handlers, everything else can be accessed.
830	*/
831	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
832	&& !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
833	{ }
834	else
835	{
836	rc = VERR_PGM_PHYS_PAGE_RESERVED;
837	break;
838	}
839
840	/*
841	* Now, just perform the locking and address calculation.
842	*/
843	PPGMPAGEMAP pMap = pTlbe->pMap;
844	if (pMap)
845	pMap->cRefs++;
846
847	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
848	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
849	{
850	if (cLocks == 0)
851	pVM->pgm.s.cReadLockedPages++;
852	PGM_PAGE_INC_READ_LOCKS(pPage);
853	}
854	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
855	{
856	PGM_PAGE_INC_READ_LOCKS(pPage);
857	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", paGCPhysPages[iPage], pPage));
858	if (pMap)
859	pMap->cRefs++; /* Extra ref to prevent it from going away. */
860	}
861
862	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
863	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
864	paLocks[iPage].pvMap = pMap;
865	}
866
867	PGM_UNLOCK(pVM);
868
869	/*
870	* On failure we must unlock any pages we managed to get already.
871	*/
872	if (RT_FAILURE(rc) && iPage > 0)
873	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
874
875	return rc;
876	}
877
878
879	#define MAKE_LEAF(a_pNode) \
880	do { \
881	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
882	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
883	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
884	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
885	} while (0)
886
887	#define INSERT_LEFT(a_pParent, a_pNode) \
888	do { \
889	(a_pParent)->pLeftR3 = (a_pNode); \
890	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
891	} while (0)
892	#define INSERT_RIGHT(a_pParent, a_pNode) \
893	do { \
894	(a_pParent)->pRightR3 = (a_pNode); \
895	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
896	} while (0)
897
898
899	/**
900	* Recursive tree builder.
901	*
902	* @param ppRam Pointer to the iterator variable.
903	* @param iDepth The current depth. Inserts a leaf node if 0.
904	*/
905	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
906	{
907	PPGMRAMRANGE pRam;
908	if (iDepth <= 0)
909	{
910	/*
911	* Leaf node.
912	*/
913	pRam = *ppRam;
914	if (pRam)
915	{
916	*ppRam = pRam->pNextR3;
917	MAKE_LEAF(pRam);
918	}
919	}
920	else
921	{
922
923	/*
924	* Intermediate node.
925	*/
926	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
927
928	pRam = *ppRam;
929	if (!pRam)
930	return pLeft;
931	*ppRam = pRam->pNextR3;
932	MAKE_LEAF(pRam);
933	INSERT_LEFT(pRam, pLeft);
934
935	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
936	if (pRight)
937	INSERT_RIGHT(pRam, pRight);
938	}
939	return pRam;
940	}
941
942
943	/**
944	* Rebuilds the RAM range search trees.
945	*
946	* @param pVM The cross context VM structure.
947	*/
948	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
949	{
950
951	/*
952	* Create the reasonably balanced tree in a sequential fashion.
953	* For simplicity (laziness) we use standard recursion here.
954	*/
955	int iDepth = 0;
956	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
957	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
958	while (pRam)
959	{
960	PPGMRAMRANGE pLeft = pRoot;
961
962	pRoot = pRam;
963	pRam = pRam->pNextR3;
964	MAKE_LEAF(pRoot);
965	INSERT_LEFT(pRoot, pLeft);
966
967	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
968	if (pRight)
969	INSERT_RIGHT(pRoot, pRight);
970	/** @todo else: rotate the tree. */
971
972	iDepth++;
973	}
974
975	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
976	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
977
978	#ifdef VBOX_STRICT
979	/*
980	* Verify that the above code works.
981	*/
982	unsigned cRanges = 0;
983	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
984	cRanges++;
985	Assert(cRanges > 0);
986
987	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
988	if ((1U << cMaxDepth) < cRanges)
989	cMaxDepth++;
990
991	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
992	{
993	unsigned cDepth = 0;
994	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
995	for (;;)
996	{
997	if (pRam == pRam2)
998	break;
999	Assert(pRam2);
1000	if (pRam->GCPhys < pRam2->GCPhys)
1001	pRam2 = pRam2->pLeftR3;
1002	else
1003	pRam2 = pRam2->pRightR3;
1004	}
1005	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
1006	}
1007	#endif /* VBOX_STRICT */
1008	}
1009
1010	#undef MAKE_LEAF
1011	#undef INSERT_LEFT
1012	#undef INSERT_RIGHT
1013
1014	/**
1015	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
1016	*
1017	* Called when anything was relocated.
1018	*
1019	* @param pVM The cross context VM structure.
1020	*/
1021	void pgmR3PhysRelinkRamRanges(PVM pVM)
1022	{
1023	PPGMRAMRANGE pCur;
1024
1025	#ifdef VBOX_STRICT
1026	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1027	{
1028	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
1029	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
1030	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1031	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
1032	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
1033	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
1034	Assert( pCur2 == pCur
1035	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
1036	}
1037	#endif
1038
1039	pCur = pVM->pgm.s.pRamRangesXR3;
1040	if (pCur)
1041	{
1042	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
1043
1044	for (; pCur->pNextR3; pCur = pCur->pNextR3)
1045	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
1046
1047	Assert(pCur->pNextR0 == NIL_RTR0PTR);
1048	}
1049	else
1050	{
1051	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
1052	}
1053	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1054
1055	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1056	}
1057
1058
1059	/**
1060	* Links a new RAM range into the list.
1061	*
1062	* @param pVM The cross context VM structure.
1063	* @param pNew Pointer to the new list entry.
1064	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1065	*/
1066	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
1067	{
1068	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
1069	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
1070
1071	PGM_LOCK_VOID(pVM);
1072
1073	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
1074	pNew->pNextR3 = pRam;
1075	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
1076
1077	if (pPrev)
1078	{
1079	pPrev->pNextR3 = pNew;
1080	pPrev->pNextR0 = pNew->pSelfR0;
1081	}
1082	else
1083	{
1084	pVM->pgm.s.pRamRangesXR3 = pNew;
1085	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
1086	}
1087	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1088
1089	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1090	PGM_UNLOCK(pVM);
1091	}
1092
1093
1094	/**
1095	* Unlink an existing RAM range from the list.
1096	*
1097	* @param pVM The cross context VM structure.
1098	* @param pRam Pointer to the new list entry.
1099	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1100	*/
1101	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
1102	{
1103	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
1104	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
1105
1106	PGM_LOCK_VOID(pVM);
1107
1108	PPGMRAMRANGE pNext = pRam->pNextR3;
1109	if (pPrev)
1110	{
1111	pPrev->pNextR3 = pNext;
1112	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1113	}
1114	else
1115	{
1116	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
1117	pVM->pgm.s.pRamRangesXR3 = pNext;
1118	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1119	}
1120	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1121
1122	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1123	PGM_UNLOCK(pVM);
1124	}
1125
1126
1127	/**
1128	* Unlink an existing RAM range from the list.
1129	*
1130	* @param pVM The cross context VM structure.
1131	* @param pRam Pointer to the new list entry.
1132	*/
1133	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
1134	{
1135	PGM_LOCK_VOID(pVM);
1136
1137	/* find prev. */
1138	PPGMRAMRANGE pPrev = NULL;
1139	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
1140	while (pCur != pRam)
1141	{
1142	pPrev = pCur;
1143	pCur = pCur->pNextR3;
1144	}
1145	AssertFatal(pCur);
1146
1147	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
1148	PGM_UNLOCK(pVM);
1149	}
1150
1151
1152	/**
1153	* Frees a range of pages, replacing them with ZERO pages of the specified type.
1154	*
1155	* @returns VBox status code.
1156	* @param pVM The cross context VM structure.
1157	* @param pRam The RAM range in which the pages resides.
1158	* @param GCPhys The address of the first page.
1159	* @param GCPhysLast The address of the last page.
1160	* @param pvMmio2 Pointer to the ring-3 mapping of any MMIO2 memory that
1161	* will replace the pages we're freeing up.
1162	*/
1163	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, void *pvMmio2)
1164	{
1165	PGM_LOCK_ASSERT_OWNER(pVM);
1166
1167	#ifdef VBOX_WITH_PGM_NEM_MODE
1168	/*
1169	* In simplified memory mode we don't actually free the memory,
1170	* we just unmap it and let NEM do any unlocking of it.
1171	*/
1172	if (pVM->pgm.s.fNemMode)
1173	{
1174	Assert(VM_IS_NEM_ENABLED(pVM));
1175	uint32_t const fNemNotify = (pvMmio2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0) \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE;
1176	uint8_t u2State = 0; /* (We don't support UINT8_MAX here.) */
1177	int rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify,
1178	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL,
1179	pvMmio2, &u2State);
1180	AssertLogRelRCReturn(rc, rc);
1181
1182	/* Iterate the pages. */
1183	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1184	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1185	while (cPagesLeft-- > 0)
1186	{
1187	rc = pgmPhysFreePage(pVM, NULL, NULL, pPageDst, GCPhys, PGMPAGETYPE_MMIO);
1188	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1189
1190	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO);
1191	PGM_PAGE_SET_NEM_STATE(pPageDst, u2State);
1192
1193	GCPhys += PAGE_SIZE;
1194	pPageDst++;
1195	}
1196	return rc;
1197	}
1198	#else /* !VBOX_WITH_PGM_NEM_MODE */
1199	RT_NOREF(pvMmio2);
1200	#endif /* !VBOX_WITH_PGM_NEM_MODE */
1201
1202	/*
1203	* Regular mode.
1204	*/
1205	/* Prepare. */
1206	uint32_t cPendingPages = 0;
1207	PGMMFREEPAGESREQ pReq;
1208	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1209	AssertLogRelRCReturn(rc, rc);
1210
1211	#ifdef VBOX_WITH_NATIVE_NEM
1212	/* Tell NEM up-front. */
1213	uint8_t u2State = UINT8_MAX;
1214	if (VM_IS_NEM_ENABLED(pVM))
1215	{
1216	uint32_t const fNemNotify = (pvMmio2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0) \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE;
1217	rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify, NULL, pvMmio2, &u2State);
1218	AssertLogRelRCReturnStmt(rc, GMMR3FreePagesCleanup(pReq), rc);
1219	}
1220	#endif
1221
1222	/* Iterate the pages. */
1223	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1224	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1225	while (cPagesLeft-- > 0)
1226	{
1227	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys, PGMPAGETYPE_MMIO);
1228	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1229
1230	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO);
1231	#ifdef VBOX_WITH_NATIVE_NEM
1232	if (u2State != UINT8_MAX)
1233	PGM_PAGE_SET_NEM_STATE(pPageDst, u2State);
1234	#endif
1235
1236	GCPhys += PAGE_SIZE;
1237	pPageDst++;
1238	}
1239
1240	/* Finish pending and cleanup. */
1241	if (cPendingPages)
1242	{
1243	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1244	AssertLogRelRCReturn(rc, rc);
1245	}
1246	GMMR3FreePagesCleanup(pReq);
1247
1248	return rc;
1249	}
1250
1251	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1252
1253	/**
1254	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
1255	*
1256	* This is only called on one of the EMTs while the other ones are waiting for
1257	* it to complete this function.
1258	*
1259	* @returns VINF_SUCCESS (VBox strict status code).
1260	* @param pVM The cross context VM structure.
1261	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1262	* @param pvUser User parameter
1263	*/
1264	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1265	{
1266	uintptr_t paUser = (uintptr_t )pvUser;
1267	bool fInflate = !!paUser[0];
1268	unsigned cPages = paUser[1];
1269	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
1270	uint32_t cPendingPages = 0;
1271	PGMMFREEPAGESREQ pReq;
1272	int rc;
1273
1274	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
1275	PGM_LOCK_VOID(pVM);
1276
1277	if (fInflate)
1278	{
1279	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
1280	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
1281
1282	/* Replace pages with ZERO pages. */
1283	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1284	if (RT_FAILURE(rc))
1285	{
1286	PGM_UNLOCK(pVM);
1287	AssertLogRelRC(rc);
1288	return rc;
1289	}
1290
1291	/* Iterate the pages. */
1292	for (unsigned i = 0; i < cPages; i++)
1293	{
1294	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1295	if ( pPage == NULL
1296	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
1297	{
1298	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
1299	break;
1300	}
1301
1302	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
1303
1304	/* Flush the shadow PT if this page was previously used as a guest page table. */
1305	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
1306
1307	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i], (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
1308	if (RT_FAILURE(rc))
1309	{
1310	PGM_UNLOCK(pVM);
1311	AssertLogRelRC(rc);
1312	return rc;
1313	}
1314	Assert(PGM_PAGE_IS_ZERO(pPage));
1315	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
1316	}
1317
1318	if (cPendingPages)
1319	{
1320	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1321	if (RT_FAILURE(rc))
1322	{
1323	PGM_UNLOCK(pVM);
1324	AssertLogRelRC(rc);
1325	return rc;
1326	}
1327	}
1328	GMMR3FreePagesCleanup(pReq);
1329	}
1330	else
1331	{
1332	/* Iterate the pages. */
1333	for (unsigned i = 0; i < cPages; i++)
1334	{
1335	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
1336	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
1337
1338	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
1339
1340	Assert(PGM_PAGE_IS_BALLOONED(pPage));
1341
1342	/* Change back to zero page. (NEM does not need to be informed.) */
1343	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1344	}
1345
1346	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
1347	}
1348
1349	/* Notify GMM about the balloon change. */
1350	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
1351	if (RT_SUCCESS(rc))
1352	{
1353	if (!fInflate)
1354	{
1355	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
1356	pVM->pgm.s.cBalloonedPages -= cPages;
1357	}
1358	else
1359	pVM->pgm.s.cBalloonedPages += cPages;
1360	}
1361
1362	PGM_UNLOCK(pVM);
1363
1364	/* Flush the recompiler's TLB as well. */
1365	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1366	CPUMSetChangedFlags(pVM->apCpusR3[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1367
1368	AssertLogRelRC(rc);
1369	return rc;
1370	}
1371
1372
1373	/**
1374	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
1375	*
1376	* @returns VBox status code.
1377	* @param pVM The cross context VM structure.
1378	* @param fInflate Inflate or deflate memory balloon
1379	* @param cPages Number of pages to free
1380	* @param paPhysPage Array of guest physical addresses
1381	*/
1382	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1383	{
1384	uintptr_t paUser[3];
1385
1386	paUser[0] = fInflate;
1387	paUser[1] = cPages;
1388	paUser[2] = (uintptr_t)paPhysPage;
1389	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1390	AssertRC(rc);
1391
1392	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
1393	RTMemFree(paPhysPage);
1394	}
1395
1396	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
1397
1398	/**
1399	* Inflate or deflate a memory balloon
1400	*
1401	* @returns VBox status code.
1402	* @param pVM The cross context VM structure.
1403	* @param fInflate Inflate or deflate memory balloon
1404	* @param cPages Number of pages to free
1405	* @param paPhysPage Array of guest physical addresses
1406	*/
1407	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
1408	{
1409	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
1410	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
1411	int rc;
1412
1413	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
1414	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
1415
1416	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
1417	* In the SMP case we post a request packet to postpone the job.
1418	*/
1419	if (pVM->cCpus > 1)
1420	{
1421	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
1422	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
1423	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
1424
1425	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
1426
1427	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
1428	AssertRC(rc);
1429	}
1430	else
1431	{
1432	uintptr_t paUser[3];
1433
1434	paUser[0] = fInflate;
1435	paUser[1] = cPages;
1436	paUser[2] = (uintptr_t)paPhysPage;
1437	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
1438	AssertRC(rc);
1439	}
1440	return rc;
1441
1442	#else
1443	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
1444	return VERR_NOT_IMPLEMENTED;
1445	#endif
1446	}
1447
1448
1449	/**
1450	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
1451	* physical RAM.
1452	*
1453	* This is only called on one of the EMTs while the other ones are waiting for
1454	* it to complete this function.
1455	*
1456	* @returns VINF_SUCCESS (VBox strict status code).
1457	* @param pVM The cross context VM structure.
1458	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
1459	* @param pvUser User parameter, unused.
1460	*/
1461	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
1462	{
1463	int rc = VINF_SUCCESS;
1464	NOREF(pvUser); NOREF(pVCpu);
1465
1466	PGM_LOCK_VOID(pVM);
1467	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1468	pgmPoolResetDirtyPages(pVM);
1469	#endif
1470
1471	/** @todo pointless to write protect the physical page pointed to by RSP. */
1472
1473	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1474	pRam;
1475	pRam = pRam->CTX_SUFF(pNext))
1476	{
1477	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
1478	for (uint32_t iPage = 0; iPage < cPages; iPage++)
1479	{
1480	PPGMPAGE pPage = &pRam->aPages[iPage];
1481	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
1482
1483	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
1484	\|\| enmPageType == PGMPAGETYPE_MMIO2)
1485	{
1486	/*
1487	* A RAM page.
1488	*/
1489	switch (PGM_PAGE_GET_STATE(pPage))
1490	{
1491	case PGM_PAGE_STATE_ALLOCATED:
1492	/** @todo Optimize this: Don't always re-enable write
1493	* monitoring if the page is known to be very busy. */
1494	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
1495	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1496
1497	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1498	break;
1499
1500	case PGM_PAGE_STATE_SHARED:
1501	AssertFailed();
1502	break;
1503
1504	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
1505	default:
1506	break;
1507	}
1508	}
1509	}
1510	}
1511	pgmR3PoolWriteProtectPages(pVM);
1512	PGM_INVL_ALL_VCPU_TLBS(pVM);
1513	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1514	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1515
1516	PGM_UNLOCK(pVM);
1517	return rc;
1518	}
1519
1520	/**
1521	* Protect all physical RAM to monitor writes
1522	*
1523	* @returns VBox status code.
1524	* @param pVM The cross context VM structure.
1525	*/
1526	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
1527	{
1528	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1529
1530	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
1531	AssertRC(rc);
1532	return rc;
1533	}
1534
1535
1536	/**
1537	* Gets the number of ram ranges.
1538	*
1539	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1540	* @param pVM The cross context VM structure.
1541	*/
1542	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1543	{
1544	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1545
1546	PGM_LOCK_VOID(pVM);
1547	uint32_t cRamRanges = 0;
1548	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1549	cRamRanges++;
1550	PGM_UNLOCK(pVM);
1551	return cRamRanges;
1552	}
1553
1554
1555	/**
1556	* Get information about a range.
1557	*
1558	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1559	* @param pVM The cross context VM structure.
1560	* @param iRange The ordinal of the range.
1561	* @param pGCPhysStart Where to return the start of the range. Optional.
1562	* @param pGCPhysLast Where to return the address of the last byte in the
1563	* range. Optional.
1564	* @param ppszDesc Where to return the range description. Optional.
1565	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1566	* Optional.
1567	*/
1568	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1569	const char *ppszDesc, bool pfIsMmio)
1570	{
1571	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1572
1573	PGM_LOCK_VOID(pVM);
1574	uint32_t iCurRange = 0;
1575	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1576	if (iCurRange == iRange)
1577	{
1578	if (pGCPhysStart)
1579	*pGCPhysStart = pCur->GCPhys;
1580	if (pGCPhysLast)
1581	*pGCPhysLast = pCur->GCPhysLast;
1582	if (ppszDesc)
1583	*ppszDesc = pCur->pszDesc;
1584	if (pfIsMmio)
1585	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1586
1587	PGM_UNLOCK(pVM);
1588	return VINF_SUCCESS;
1589	}
1590	PGM_UNLOCK(pVM);
1591	return VERR_OUT_OF_RANGE;
1592	}
1593
1594
1595	/**
1596	* Query the amount of free memory inside VMMR0
1597	*
1598	* @returns VBox status code.
1599	* @param pUVM The user mode VM handle.
1600	* @param pcbAllocMem Where to return the amount of memory allocated
1601	* by VMs.
1602	* @param pcbFreeMem Where to return the amount of memory that is
1603	* allocated from the host but not currently used
1604	* by any VMs.
1605	* @param pcbBallonedMem Where to return the sum of memory that is
1606	* currently ballooned by the VMs.
1607	* @param pcbSharedMem Where to return the amount of memory that is
1608	* currently shared.
1609	*/
1610	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
1611	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
1612	{
1613	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1614	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
1615
1616	uint64_t cAllocPages = 0;
1617	uint64_t cFreePages = 0;
1618	uint64_t cBalloonPages = 0;
1619	uint64_t cSharedPages = 0;
1620	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
1621	AssertRCReturn(rc, rc);
1622
1623	if (pcbAllocMem)
1624	pcbAllocMem = cAllocPages _4K;
1625
1626	if (pcbFreeMem)
1627	pcbFreeMem = cFreePages _4K;
1628
1629	if (pcbBallonedMem)
1630	pcbBallonedMem = cBalloonPages _4K;
1631
1632	if (pcbSharedMem)
1633	pcbSharedMem = cSharedPages _4K;
1634
1635	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
1636	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
1637	return VINF_SUCCESS;
1638	}
1639
1640
1641	/**
1642	* Query memory stats for the VM.
1643	*
1644	* @returns VBox status code.
1645	* @param pUVM The user mode VM handle.
1646	* @param pcbTotalMem Where to return total amount memory the VM may
1647	* possibly use.
1648	* @param pcbPrivateMem Where to return the amount of private memory
1649	* currently allocated.
1650	* @param pcbSharedMem Where to return the amount of actually shared
1651	* memory currently used by the VM.
1652	* @param pcbZeroMem Where to return the amount of memory backed by
1653	* zero pages.
1654	*
1655	* @remarks The total mem is normally larger than the sum of the three
1656	* components. There are two reasons for this, first the amount of
1657	* shared memory is what we're sure is shared instead of what could
1658	* possibly be shared with someone. Secondly, because the total may
1659	* include some pure MMIO pages that doesn't go into any of the three
1660	* sub-counts.
1661	*
1662	* @todo Why do we return reused shared pages instead of anything that could
1663	* potentially be shared? Doesn't this mean the first VM gets a much
1664	* lower number of shared pages?
1665	*/
1666	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
1667	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
1668	{
1669	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1670	PVM pVM = pUVM->pVM;
1671	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1672
1673	if (pcbTotalMem)
1674	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
1675
1676	if (pcbPrivateMem)
1677	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
1678
1679	if (pcbSharedMem)
1680	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
1681
1682	if (pcbZeroMem)
1683	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
1684
1685	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
1686	return VINF_SUCCESS;
1687	}
1688
1689
1690	/**
1691	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1692	*
1693	* In NEM mode, this will allocate the pages backing the RAM range and this may
1694	* fail. NEM registration may also fail. (In regular HM mode it won't fail.)
1695	*
1696	* @returns VBox status code.
1697	* @param pVM The cross context VM structure.
1698	* @param pNew The new RAM range.
1699	* @param GCPhys The address of the RAM range.
1700	* @param GCPhysLast The last address of the RAM range.
1701	* @param R0PtrNew Ditto for R0.
1702	* @param fFlags PGM_RAM_RANGE_FLAGS_FLOATING or zero.
1703	* @param pszDesc The description.
1704	* @param pPrev The previous RAM range (for linking).
1705	*/
1706	static int pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1707	RTR0PTR R0PtrNew, uint32_t fFlags, const char *pszDesc, PPGMRAMRANGE pPrev)
1708	{
1709	/*
1710	* Initialize the range.
1711	*/
1712	pNew->pSelfR0 = R0PtrNew;
1713	pNew->GCPhys = GCPhys;
1714	pNew->GCPhysLast = GCPhysLast;
1715	pNew->cb = GCPhysLast - GCPhys + 1;
1716	pNew->pszDesc = pszDesc;
1717	pNew->fFlags = fFlags;
1718	pNew->pvR3 = NULL;
1719	pNew->paLSPages = NULL;
1720
1721	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1722	#ifdef VBOX_WITH_PGM_NEM_MODE
1723	if (!pVM->pgm.s.fNemMode)
1724	#endif
1725	{
1726	RTGCPHYS iPage = cPages;
1727	while (iPage-- > 0)
1728	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1729
1730	/* Update the page count stats. */
1731	pVM->pgm.s.cZeroPages += cPages;
1732	pVM->pgm.s.cAllPages += cPages;
1733	}
1734	#ifdef VBOX_WITH_PGM_NEM_MODE
1735	else
1736	{
1737	int rc = SUPR3PageAlloc(cPages, &pNew->pvR3);
1738	if (RT_FAILURE(rc))
1739	return rc;
1740
1741	RTGCPHYS iPage = cPages;
1742	while (iPage-- > 0)
1743	PGM_PAGE_INIT(&pNew->aPages[iPage], UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
1744	PGMPAGETYPE_RAM, PGM_PAGE_STATE_ALLOCATED);
1745
1746	/* Update the page count stats. */
1747	pVM->pgm.s.cPrivatePages += cPages;
1748	pVM->pgm.s.cAllPages += cPages;
1749	}
1750	#endif
1751
1752	/*
1753	* Link it.
1754	*/
1755	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1756
1757	#ifdef VBOX_WITH_NATIVE_NEM
1758	/*
1759	* Notify NEM now that it has been linked.
1760	*/
1761	int rc = NEMR3NotifyPhysRamRegister(pVM, GCPhys, pNew->cb, pNew->pvR3);
1762	if (RT_FAILURE(rc))
1763	pgmR3PhysUnlinkRamRange2(pVM, pNew, pPrev);
1764	return rc;
1765	#else
1766	return VINF_SUCCESS;
1767	#endif
1768	}
1769
1770
1771	/**
1772	* PGMR3PhysRegisterRam worker that registers a high chunk.
1773	*
1774	* @returns VBox status code.
1775	* @param pVM The cross context VM structure.
1776	* @param GCPhys The address of the RAM.
1777	* @param cRamPages The number of RAM pages to register.
1778	* @param iChunk The chunk number.
1779	* @param pszDesc The RAM range description.
1780	* @param ppPrev Previous RAM range pointer. In/Out.
1781	*/
1782	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages, uint32_t iChunk,
1783	const char pszDesc, PPGMRAMRANGE ppPrev)
1784	{
1785	const char *pszDescChunk = iChunk == 0
1786	? pszDesc
1787	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1788	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1789
1790	/*
1791	* Allocate memory for the new chunk.
1792	*/
1793	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1794	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1795	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1796	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1797	void *pvChunk = NULL;
1798	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
1799	if (RT_SUCCESS(rc))
1800	{
1801	Assert(R0PtrChunk != NIL_RTR0PTR);
1802	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1803
1804	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1805
1806	/*
1807	* Ok, init and link the range.
1808	*/
1809	rc = pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1810	R0PtrChunk, PGM_RAM_RANGE_FLAGS_FLOATING, pszDescChunk, *ppPrev);
1811	if (RT_SUCCESS(rc))
1812	*ppPrev = pNew;
1813
1814	if (RT_FAILURE(rc))
1815	SUPR3PageFreeEx(pvChunk, cChunkPages);
1816	}
1817
1818	RTMemTmpFree(paChunkPages);
1819	return rc;
1820	}
1821
1822
1823	/**
1824	* Sets up a range RAM.
1825	*
1826	* This will check for conflicting registrations, make a resource
1827	* reservation for the memory (with GMM), and setup the per-page
1828	* tracking structures (PGMPAGE).
1829	*
1830	* @returns VBox status code.
1831	* @param pVM The cross context VM structure.
1832	* @param GCPhys The physical address of the RAM.
1833	* @param cb The size of the RAM.
1834	* @param pszDesc The description - not copied, so, don't free or change it.
1835	*/
1836	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1837	{
1838	/*
1839	* Validate input.
1840	*/
1841	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1842	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1843	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1844	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1845	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1846	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1847	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1848	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1849
1850	PGM_LOCK_VOID(pVM);
1851
1852	/*
1853	* Find range location and check for conflicts.
1854	*/
1855	PPGMRAMRANGE pPrev = NULL;
1856	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1857	while (pRam && GCPhysLast >= pRam->GCPhys)
1858	{
1859	AssertLogRelMsgReturnStmt( GCPhysLast < pRam->GCPhys
1860	\|\| GCPhys > pRam->GCPhysLast,
1861	("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1862	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1863	PGM_UNLOCK(pVM), VERR_PGM_RAM_CONFLICT);
1864
1865	/* next */
1866	pPrev = pRam;
1867	pRam = pRam->pNextR3;
1868	}
1869
1870	/*
1871	* Register it with GMM (the API bitches).
1872	*/
1873	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1874	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1875	if (RT_FAILURE(rc))
1876	{
1877	PGM_UNLOCK(pVM);
1878	return rc;
1879	}
1880
1881	if ( GCPhys >= _4G
1882	&& cPages > 256)
1883	{
1884	/*
1885	* The PGMRAMRANGE structures for the high memory can get very big.
1886	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1887	* allocation size limit there and also to avoid being unable to find
1888	* guest mapping space for them, we split this memory up into 4MB in
1889	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1890	* mode.
1891	*
1892	* The first and last page of each mapping are guard pages and marked
1893	* not-present. So, we've got 4186112 and 16769024 bytes available for
1894	* the PGMRAMRANGE structure.
1895	*
1896	* Note! The sizes used here will influence the saved state.
1897	*/
1898	uint32_t cbChunk = 16U*_1M;
1899	uint32_t cPagesPerChunk = 1048048; /* max ~1048059 */
1900	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1901	AssertRelease(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1902
1903	RTGCPHYS cPagesLeft = cPages;
1904	RTGCPHYS GCPhysChunk = GCPhys;
1905	uint32_t iChunk = 0;
1906	while (cPagesLeft > 0)
1907	{
1908	uint32_t cPagesInChunk = cPagesLeft;
1909	if (cPagesInChunk > cPagesPerChunk)
1910	cPagesInChunk = cPagesPerChunk;
1911
1912	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, iChunk, pszDesc, &pPrev);
1913	AssertRCReturn(rc, rc);
1914
1915	/* advance */
1916	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1917	cPagesLeft -= cPagesInChunk;
1918	iChunk++;
1919	}
1920	}
1921	else
1922	{
1923	/*
1924	* Allocate, initialize and link the new RAM range.
1925	*/
1926	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
1927	PPGMRAMRANGE pNew;
1928	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1929	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc cbRamRange=%zu\n", rc, cbRamRange), rc);
1930
1931	rc = pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, MMHyperCCToR0(pVM, pNew), 0 /fFlags/, pszDesc, pPrev);
1932	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc cbRamRange=%zu\n", rc, cbRamRange), rc);
1933	}
1934	pgmPhysInvalidatePageMapTLB(pVM);
1935
1936	PGM_UNLOCK(pVM);
1937	return rc;
1938	}
1939
1940
1941	/**
1942	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1943	*
1944	* We do this late in the init process so that all the ROM and MMIO ranges have
1945	* been registered already and we don't go wasting memory on them.
1946	*
1947	* @returns VBox status code.
1948	*
1949	* @param pVM The cross context VM structure.
1950	*/
1951	int pgmR3PhysRamPreAllocate(PVM pVM)
1952	{
1953	Assert(pVM->pgm.s.fRamPreAlloc);
1954	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1955	#ifdef VBOX_WITH_PGM_NEM_MODE
1956	AssertLogRelReturn(!pVM->pgm.s.fNemMode, VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
1957	#endif
1958
1959	/*
1960	* Walk the RAM ranges and allocate all RAM pages, halt at
1961	* the first allocation error.
1962	*/
1963	uint64_t cPages = 0;
1964	uint64_t NanoTS = RTTimeNanoTS();
1965	PGM_LOCK_VOID(pVM);
1966	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1967	{
1968	PPGMPAGE pPage = &pRam->aPages[0];
1969	RTGCPHYS GCPhys = pRam->GCPhys;
1970	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1971	while (cLeft-- > 0)
1972	{
1973	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1974	{
1975	switch (PGM_PAGE_GET_STATE(pPage))
1976	{
1977	case PGM_PAGE_STATE_ZERO:
1978	{
1979	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1980	if (RT_FAILURE(rc))
1981	{
1982	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1983	PGM_UNLOCK(pVM);
1984	return rc;
1985	}
1986	cPages++;
1987	break;
1988	}
1989
1990	case PGM_PAGE_STATE_BALLOONED:
1991	case PGM_PAGE_STATE_ALLOCATED:
1992	case PGM_PAGE_STATE_WRITE_MONITORED:
1993	case PGM_PAGE_STATE_SHARED:
1994	/* nothing to do here. */
1995	break;
1996	}
1997	}
1998
1999	/* next */
2000	pPage++;
2001	GCPhys += PAGE_SIZE;
2002	}
2003	}
2004	PGM_UNLOCK(pVM);
2005	NanoTS = RTTimeNanoTS() - NanoTS;
2006
2007	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
2008	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
2009	return VINF_SUCCESS;
2010	}
2011
2012
2013	/**
2014	* Checks shared page checksums.
2015	*
2016	* @param pVM The cross context VM structure.
2017	*/
2018	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
2019	{
2020	#ifdef VBOX_STRICT
2021	PGM_LOCK_VOID(pVM);
2022
2023	if (pVM->pgm.s.cSharedPages > 0)
2024	{
2025	/*
2026	* Walk the ram ranges.
2027	*/
2028	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2029	{
2030	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2031	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2032
2033	while (iPage-- > 0)
2034	{
2035	PPGMPAGE pPage = &pRam->aPages[iPage];
2036	if (PGM_PAGE_IS_SHARED(pPage))
2037	{
2038	uint32_t u32Checksum = pPage->s.u2Unused0/* \| ((uint32_t)pPage->s.u2Unused1 << 8)*/;
2039	if (!u32Checksum)
2040	{
2041	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2042	void const *pvPage;
2043	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
2044	if (RT_SUCCESS(rc))
2045	{
2046	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
2047	# if 0
2048	AssertMsg((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
2049	# else
2050	if ((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum)
2051	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
2052	else
2053	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
2054	# endif
2055	}
2056	else
2057	AssertRC(rc);
2058	}
2059	}
2060
2061	} /* for each page */
2062
2063	} /* for each ram range */
2064	}
2065
2066	PGM_UNLOCK(pVM);
2067	#endif /* VBOX_STRICT */
2068	NOREF(pVM);
2069	}
2070
2071
2072	/**
2073	* Resets the physical memory state.
2074	*
2075	* ASSUMES that the caller owns the PGM lock.
2076	*
2077	* @returns VBox status code.
2078	* @param pVM The cross context VM structure.
2079	*/
2080	int pgmR3PhysRamReset(PVM pVM)
2081	{
2082	PGM_LOCK_ASSERT_OWNER(pVM);
2083
2084	/* Reset the memory balloon. */
2085	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2086	AssertRC(rc);
2087
2088	#ifdef VBOX_WITH_PAGE_SHARING
2089	/* Clear all registered shared modules. */
2090	pgmR3PhysAssertSharedPageChecksums(pVM);
2091	rc = GMMR3ResetSharedModules(pVM);
2092	AssertRC(rc);
2093	#endif
2094	/* Reset counters. */
2095	pVM->pgm.s.cReusedSharedPages = 0;
2096	pVM->pgm.s.cBalloonedPages = 0;
2097
2098	return VINF_SUCCESS;
2099	}
2100
2101
2102	/**
2103	* Resets (zeros) the RAM after all devices and components have been reset.
2104	*
2105	* ASSUMES that the caller owns the PGM lock.
2106	*
2107	* @returns VBox status code.
2108	* @param pVM The cross context VM structure.
2109	*/
2110	int pgmR3PhysRamZeroAll(PVM pVM)
2111	{
2112	PGM_LOCK_ASSERT_OWNER(pVM);
2113
2114	/*
2115	* We batch up pages that should be freed instead of calling GMM for
2116	* each and every one of them.
2117	*/
2118	uint32_t cPendingPages = 0;
2119	PGMMFREEPAGESREQ pReq;
2120	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2121	AssertLogRelRCReturn(rc, rc);
2122
2123	/*
2124	* Walk the ram ranges.
2125	*/
2126	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2127	{
2128	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2129	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2130
2131	if ( !pVM->pgm.s.fRamPreAlloc
2132	#ifdef VBOX_WITH_PGM_NEM_MODE
2133	&& !pVM->pgm.s.fNemMode
2134	#endif
2135	&& pVM->pgm.s.fZeroRamPagesOnReset)
2136	{
2137	/* Replace all RAM pages by ZERO pages. */
2138	while (iPage-- > 0)
2139	{
2140	PPGMPAGE pPage = &pRam->aPages[iPage];
2141	switch (PGM_PAGE_GET_TYPE(pPage))
2142	{
2143	case PGMPAGETYPE_RAM:
2144	/* Do not replace pages part of a 2 MB continuous range
2145	with zero pages, but zero them instead. */
2146	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
2147	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2148	{
2149	void *pvPage;
2150	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2151	AssertLogRelRCReturn(rc, rc);
2152	ASMMemZeroPage(pvPage);
2153	}
2154	else if (PGM_PAGE_IS_BALLOONED(pPage))
2155	{
2156	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2157	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2158	}
2159	else if (!PGM_PAGE_IS_ZERO(pPage))
2160	{
2161	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2162	PGMPAGETYPE_RAM);
2163	AssertLogRelRCReturn(rc, rc);
2164	}
2165	break;
2166
2167	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2168	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2169	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2170	pRam, true /fDoAccounting/);
2171	break;
2172
2173	case PGMPAGETYPE_MMIO2:
2174	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2175	case PGMPAGETYPE_ROM:
2176	case PGMPAGETYPE_MMIO:
2177	break;
2178	default:
2179	AssertFailed();
2180	}
2181	} /* for each page */
2182	}
2183	else
2184	{
2185	/* Zero the memory. */
2186	while (iPage-- > 0)
2187	{
2188	PPGMPAGE pPage = &pRam->aPages[iPage];
2189	switch (PGM_PAGE_GET_TYPE(pPage))
2190	{
2191	case PGMPAGETYPE_RAM:
2192	switch (PGM_PAGE_GET_STATE(pPage))
2193	{
2194	case PGM_PAGE_STATE_ZERO:
2195	break;
2196
2197	case PGM_PAGE_STATE_BALLOONED:
2198	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2199	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2200	break;
2201
2202	case PGM_PAGE_STATE_SHARED:
2203	case PGM_PAGE_STATE_WRITE_MONITORED:
2204	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2205	AssertLogRelRCReturn(rc, rc);
2206	RT_FALL_THRU();
2207
2208	case PGM_PAGE_STATE_ALLOCATED:
2209	if (pVM->pgm.s.fZeroRamPagesOnReset)
2210	{
2211	void *pvPage;
2212	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2213	AssertLogRelRCReturn(rc, rc);
2214	ASMMemZeroPage(pvPage);
2215	}
2216	break;
2217	}
2218	break;
2219
2220	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2221	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2222	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2223	pRam, true /fDoAccounting/);
2224	break;
2225
2226	case PGMPAGETYPE_MMIO2:
2227	case PGMPAGETYPE_ROM_SHADOW:
2228	case PGMPAGETYPE_ROM:
2229	case PGMPAGETYPE_MMIO:
2230	break;
2231	default:
2232	AssertFailed();
2233
2234	}
2235	} /* for each page */
2236	}
2237
2238	}
2239
2240	/*
2241	* Finish off any pages pending freeing.
2242	*/
2243	if (cPendingPages)
2244	{
2245	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2246	AssertLogRelRCReturn(rc, rc);
2247	}
2248	GMMR3FreePagesCleanup(pReq);
2249	return VINF_SUCCESS;
2250	}
2251
2252
2253	/**
2254	* Frees all RAM during VM termination
2255	*
2256	* ASSUMES that the caller owns the PGM lock.
2257	*
2258	* @returns VBox status code.
2259	* @param pVM The cross context VM structure.
2260	*/
2261	int pgmR3PhysRamTerm(PVM pVM)
2262	{
2263	PGM_LOCK_ASSERT_OWNER(pVM);
2264
2265	/* Reset the memory balloon. */
2266	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2267	AssertRC(rc);
2268
2269	#ifdef VBOX_WITH_PAGE_SHARING
2270	/*
2271	* Clear all registered shared modules.
2272	*/
2273	pgmR3PhysAssertSharedPageChecksums(pVM);
2274	rc = GMMR3ResetSharedModules(pVM);
2275	AssertRC(rc);
2276
2277	/*
2278	* Flush the handy pages updates to make sure no shared pages are hiding
2279	* in there. (No unlikely if the VM shuts down, apparently.)
2280	*/
2281	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2282	#endif
2283
2284	/*
2285	* We batch up pages that should be freed instead of calling GMM for
2286	* each and every one of them.
2287	*/
2288	uint32_t cPendingPages = 0;
2289	PGMMFREEPAGESREQ pReq;
2290	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2291	AssertLogRelRCReturn(rc, rc);
2292
2293	/*
2294	* Walk the ram ranges.
2295	*/
2296	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2297	{
2298	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2299	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2300
2301	while (iPage-- > 0)
2302	{
2303	PPGMPAGE pPage = &pRam->aPages[iPage];
2304	switch (PGM_PAGE_GET_TYPE(pPage))
2305	{
2306	case PGMPAGETYPE_RAM:
2307	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2308	/** @todo change this to explicitly free private pages here. */
2309	if (PGM_PAGE_IS_SHARED(pPage))
2310	{
2311	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2312	PGMPAGETYPE_RAM);
2313	AssertLogRelRCReturn(rc, rc);
2314	}
2315	break;
2316
2317	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2318	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2319	case PGMPAGETYPE_MMIO2:
2320	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2321	case PGMPAGETYPE_ROM:
2322	case PGMPAGETYPE_MMIO:
2323	break;
2324	default:
2325	AssertFailed();
2326	}
2327	} /* for each page */
2328	}
2329
2330	/*
2331	* Finish off any pages pending freeing.
2332	*/
2333	if (cPendingPages)
2334	{
2335	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2336	AssertLogRelRCReturn(rc, rc);
2337	}
2338	GMMR3FreePagesCleanup(pReq);
2339	return VINF_SUCCESS;
2340	}
2341
2342
2343	/**
2344	* This is the interface IOM is using to register an MMIO region.
2345	*
2346	* It will check for conflicts and ensure that a RAM range structure
2347	* is present before calling the PGMR3HandlerPhysicalRegister API to
2348	* register the callbacks.
2349	*
2350	* @returns VBox status code.
2351	*
2352	* @param pVM The cross context VM structure.
2353	* @param GCPhys The start of the MMIO region.
2354	* @param cb The size of the MMIO region.
2355	* @param hType The physical access handler type registration.
2356	* @param pvUserR3 The user argument for R3.
2357	* @param pvUserR0 The user argument for R0.
2358	* @param pvUserRC The user argument for RC.
2359	* @param pszDesc The description of the MMIO region.
2360	*/
2361	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2362	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2363	{
2364	/*
2365	* Assert on some assumption.
2366	*/
2367	VM_ASSERT_EMT(pVM);
2368	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2369	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2370	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2371	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2372	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2373
2374	int rc = PGM_LOCK(pVM);
2375	AssertRCReturn(rc, rc);
2376
2377	/*
2378	* Make sure there's a RAM range structure for the region.
2379	*/
2380	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2381	bool fRamExists = false;
2382	PPGMRAMRANGE pRamPrev = NULL;
2383	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2384	while (pRam && GCPhysLast >= pRam->GCPhys)
2385	{
2386	if ( GCPhysLast >= pRam->GCPhys
2387	&& GCPhys <= pRam->GCPhysLast)
2388	{
2389	/* Simplification: all within the same range. */
2390	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2391	&& GCPhysLast <= pRam->GCPhysLast,
2392	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2393	GCPhys, GCPhysLast, pszDesc,
2394	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2395	PGM_UNLOCK(pVM),
2396	VERR_PGM_RAM_CONFLICT);
2397
2398	/* Check that it's all RAM or MMIO pages. */
2399	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2400	uint32_t cLeft = cb >> PAGE_SHIFT;
2401	while (cLeft-- > 0)
2402	{
2403	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2404	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2405	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2406	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2407	PGM_UNLOCK(pVM),
2408	VERR_PGM_RAM_CONFLICT);
2409	pPage++;
2410	}
2411
2412	/* Looks good. */
2413	fRamExists = true;
2414	break;
2415	}
2416
2417	/* next */
2418	pRamPrev = pRam;
2419	pRam = pRam->pNextR3;
2420	}
2421	PPGMRAMRANGE pNew;
2422	if (fRamExists)
2423	{
2424	pNew = NULL;
2425
2426	/*
2427	* Make all the pages in the range MMIO/ZERO pages, freeing any
2428	* RAM pages currently mapped here. This might not be 100% correct
2429	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2430	*/
2431	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, NULL);
2432	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
2433
2434	/* Force a PGM pool flush as guest ram references have been changed. */
2435	/** @todo not entirely SMP safe; assuming for now the guest takes
2436	* care of this internally (not touch mapped mmio while changing the
2437	* mapping). */
2438	PVMCPU pVCpu = VMMGetCpu(pVM);
2439	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2440	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2441	}
2442	else
2443	{
2444	/*
2445	* No RAM range, insert an ad hoc one.
2446	*
2447	* Note that we don't have to tell REM about this range because
2448	* PGMHandlerPhysicalRegisterEx will do that for us.
2449	*/
2450	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2451
2452	/* Alloc. */
2453	const uint32_t cPages = cb >> PAGE_SHIFT;
2454	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
2455	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2456	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), PGM_UNLOCK(pVM), rc);
2457
2458	#ifdef VBOX_WITH_NATIVE_NEM
2459	/* Notify NEM. */
2460	uint8_t u2State = 0; /* (must have valid state as there can't be anything to preserve) */
2461	if (VM_IS_NEM_ENABLED(pVM))
2462	{
2463	rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, cPages << PAGE_SHIFT, 0 /fFlags/, NULL, NULL, &u2State);
2464	AssertLogRelRCReturnStmt(rc, MMHyperFree(pVM, pNew), rc);
2465	}
2466	#endif
2467
2468	/* Initialize the range. */
2469	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2470	pNew->GCPhys = GCPhys;
2471	pNew->GCPhysLast = GCPhysLast;
2472	pNew->cb = cb;
2473	pNew->pszDesc = pszDesc;
2474	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2475	pNew->pvR3 = NULL;
2476	pNew->paLSPages = NULL;
2477
2478	uint32_t iPage = cPages;
2479	while (iPage-- > 0)
2480	{
2481	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2482	#ifdef VBOX_WITH_NATIVE_NEM
2483	PGM_PAGE_SET_NEM_STATE(&pNew->aPages[iPage], u2State);
2484	#endif
2485	}
2486	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2487
2488	/* update the page count stats. */
2489	pVM->pgm.s.cPureMmioPages += cPages;
2490	pVM->pgm.s.cAllPages += cPages;
2491
2492	/* link it */
2493	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2494	}
2495
2496	/*
2497	* Register the access handler.
2498	*/
2499	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2500	if (RT_SUCCESS(rc))
2501	{
2502	#ifdef VBOX_WITH_NATIVE_NEM
2503	/* Late NEM notification. */
2504	if (VM_IS_NEM_ENABLED(pVM))
2505	{
2506	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
2507	rc = NEMR3NotifyPhysMmioExMapLate(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify,
2508	fRamExists ? (uint8_t *)pRam->pvR3 + (uintptr_t)(GCPhys - pRam->GCPhys) : NULL,
2509	NULL);
2510	AssertLogRelRCReturn(rc, rc);
2511	}
2512	#endif
2513	}
2514	/** @todo the phys handler failure handling isn't complete, esp. wrt NEM. */
2515	else if (!fRamExists)
2516	{
2517	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2518	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2519
2520	/* remove the ad hoc range. */
2521	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2522	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2523	MMHyperFree(pVM, pRam);
2524	}
2525	pgmPhysInvalidatePageMapTLB(pVM);
2526
2527	PGM_UNLOCK(pVM);
2528	return rc;
2529	}
2530
2531
2532	/**
2533	* This is the interface IOM is using to register an MMIO region.
2534	*
2535	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2536	* any ad hoc PGMRAMRANGE left behind.
2537	*
2538	* @returns VBox status code.
2539	* @param pVM The cross context VM structure.
2540	* @param GCPhys The start of the MMIO region.
2541	* @param cb The size of the MMIO region.
2542	*/
2543	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2544	{
2545	VM_ASSERT_EMT(pVM);
2546
2547	int rc = PGM_LOCK(pVM);
2548	AssertRCReturn(rc, rc);
2549
2550	/*
2551	* First deregister the handler, then check if we should remove the ram range.
2552	*/
2553	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2554	if (RT_SUCCESS(rc))
2555	{
2556	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2557	PPGMRAMRANGE pRamPrev = NULL;
2558	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2559	while (pRam && GCPhysLast >= pRam->GCPhys)
2560	{
2561	/** @todo We're being a bit too careful here. rewrite. */
2562	if ( GCPhysLast == pRam->GCPhysLast
2563	&& GCPhys == pRam->GCPhys)
2564	{
2565	Assert(pRam->cb == cb);
2566
2567	/*
2568	* See if all the pages are dead MMIO pages.
2569	*/
2570	uint32_t const cPages = cb >> PAGE_SHIFT;
2571	bool fAllMMIO = true;
2572	uint32_t iPage = 0;
2573	uint32_t cLeft = cPages;
2574	while (cLeft-- > 0)
2575	{
2576	PPGMPAGE pPage = &pRam->aPages[iPage];
2577	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2578	/\|\| not-out-of-action later /)
2579	{
2580	fAllMMIO = false;
2581	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2582	break;
2583	}
2584	Assert( PGM_PAGE_IS_ZERO(pPage)
2585	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2586	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2587	pPage++;
2588	}
2589	if (fAllMMIO)
2590	{
2591	/*
2592	* Ad-hoc range, unlink and free it.
2593	*/
2594	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2595	GCPhys, GCPhysLast, pRam->pszDesc));
2596	/** @todo check the ad-hoc flags? */
2597
2598	#ifdef VBOX_WITH_NATIVE_NEM
2599	if (VM_IS_NEM_ENABLED(pVM)) /* Notify REM before we unlink the range. */
2600	{
2601	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhys, GCPhysLast - GCPhys + 1, 0 /fFlags/, NULL, NULL, NULL);
2602	AssertLogRelRCReturn(rc, rc);
2603	}
2604	#endif
2605
2606	pVM->pgm.s.cAllPages -= cPages;
2607	pVM->pgm.s.cPureMmioPages -= cPages;
2608
2609	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2610	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2611	MMHyperFree(pVM, pRam);
2612	break;
2613	}
2614	}
2615
2616	/*
2617	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2618	*/
2619	if ( GCPhysLast >= pRam->GCPhys
2620	&& GCPhys <= pRam->GCPhysLast)
2621	{
2622	Assert(GCPhys >= pRam->GCPhys);
2623	Assert(GCPhysLast <= pRam->GCPhysLast);
2624
2625	/*
2626	* Turn the pages back into RAM pages.
2627	*/
2628	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2629	uint32_t cLeft = cb >> PAGE_SHIFT;
2630	while (cLeft--)
2631	{
2632	PPGMPAGE pPage = &pRam->aPages[iPage];
2633	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2634	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2635	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2636	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2637	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2638	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2639	iPage++;
2640	}
2641
2642	#ifdef VBOX_WITH_NATIVE_NEM
2643	/* Notify REM (failure will probably leave things in a non-working state). */
2644	if (VM_IS_NEM_ENABLED(pVM))
2645	{
2646	uint8_t u2State = UINT8_MAX;
2647	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhys, GCPhysLast - GCPhys + 1, NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
2648	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL,
2649	NULL, &u2State);
2650	AssertLogRelRCReturn(rc, rc);
2651	if (u2State != UINT8_MAX)
2652	pgmPhysSetNemStateForPages(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT],
2653	cb >> PAGE_SHIFT, u2State);
2654	}
2655	#endif
2656	break;
2657	}
2658
2659	/* next */
2660	pRamPrev = pRam;
2661	pRam = pRam->pNextR3;
2662	}
2663	}
2664
2665	/* Force a PGM pool flush as guest ram references have been changed. */
2666	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2667	* this internally (not touch mapped mmio while changing the mapping). */
2668	PVMCPU pVCpu = VMMGetCpu(pVM);
2669	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2670	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2671
2672	pgmPhysInvalidatePageMapTLB(pVM);
2673	pgmPhysInvalidRamRangeTlbs(pVM);
2674	PGM_UNLOCK(pVM);
2675	return rc;
2676	}
2677
2678
2679	/**
2680	* Locate a MMIO2 range.
2681	*
2682	* @returns Pointer to the MMIO2 range.
2683	* @param pVM The cross context VM structure.
2684	* @param pDevIns The device instance owning the region.
2685	* @param iSubDev The sub-device number.
2686	* @param iRegion The region.
2687	* @param hMmio2 Handle to look up. If NIL, use the @a iSubDev and
2688	* @a iRegion.
2689	*/
2690	DECLINLINE(PPGMREGMMIO2RANGE) pgmR3PhysMmio2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev,
2691	uint32_t iRegion, PGMMMIO2HANDLE hMmio2)
2692	{
2693	if (hMmio2 != NIL_PGMMMIO2HANDLE)
2694	{
2695	if (hMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3) && hMmio2 != 0)
2696	{
2697	PPGMREGMMIO2RANGE pCur = pVM->pgm.s.apMmio2RangesR3[hMmio2 - 1];
2698	if (pCur && pCur->pDevInsR3 == pDevIns)
2699	{
2700	Assert(pCur->idMmio2 == hMmio2);
2701	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_MMIO2, NULL);
2702	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, NULL);
2703	return pCur;
2704	}
2705	Assert(!pCur);
2706	}
2707	for (PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2708	if (pCur->idMmio2 == hMmio2)
2709	{
2710	AssertBreak(pCur->pDevInsR3 == pDevIns);
2711	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_MMIO2, NULL);
2712	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, NULL);
2713	return pCur;
2714	}
2715	}
2716	else
2717	{
2718	/*
2719	* Search the list. There shouldn't be many entries.
2720	*/
2721	/** @todo Optimize this lookup! There may now be many entries and it'll
2722	* become really slow when doing MMR3HyperMapMMIO2 and similar. */
2723	for (PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2724	if ( pCur->pDevInsR3 == pDevIns
2725	&& pCur->iRegion == iRegion
2726	&& pCur->iSubDev == iSubDev)
2727	return pCur;
2728	}
2729	return NULL;
2730	}
2731
2732
2733	/**
2734	* Calculates the number of chunks
2735	*
2736	* @returns Number of registration chunk needed.
2737	* @param pVM The cross context VM structure.
2738	* @param cb The size of the MMIO/MMIO2 range.
2739	* @param pcPagesPerChunk Where to return the number of pages tracked by each
2740	* chunk. Optional.
2741	* @param pcbChunk Where to return the guest mapping size for a chunk.
2742	*/
2743	static uint16_t pgmR3PhysMmio2CalcChunkCount(PVM pVM, RTGCPHYS cb, uint32_t pcPagesPerChunk, uint32_t pcbChunk)
2744	{
2745	RT_NOREF_PV(pVM); /* without raw mode */
2746
2747	/*
2748	* This is the same calculation as PGMR3PhysRegisterRam does, except we'll be
2749	* needing a few bytes extra the PGMREGMMIO2RANGE structure.
2750	*
2751	* Note! In additions, we've got a 24 bit sub-page range for MMIO2 ranges, leaving
2752	* us with an absolute maximum of 16777215 pages per chunk (close to 64 GB).
2753	*/
2754	uint32_t cbChunk = 16U*_1M;
2755	uint32_t cPagesPerChunk = 1048048; /* max ~1048059 */
2756	AssertCompile(sizeof(PGMREGMMIO2RANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
2757	AssertRelease(cPagesPerChunk <= PGM_MMIO2_MAX_PAGE_COUNT); /* See above note. */
2758	AssertRelease(RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
2759	if (pcbChunk)
2760	*pcbChunk = cbChunk;
2761	if (pcPagesPerChunk)
2762	*pcPagesPerChunk = cPagesPerChunk;
2763
2764	/* Calc the number of chunks we need. */
2765	RTGCPHYS const cPages = cb >> X86_PAGE_SHIFT;
2766	uint16_t cChunks = (uint16_t)((cPages + cPagesPerChunk - 1) / cPagesPerChunk);
2767	AssertRelease((RTGCPHYS)cChunks * cPagesPerChunk >= cPages);
2768	return cChunks;
2769	}
2770
2771
2772	/**
2773	* Worker for PGMR3PhysMMIO2Register that allocates and the PGMREGMMIO2RANGE
2774	* structures and does basic initialization.
2775	*
2776	* Caller must set type specfic members and initialize the PGMPAGE structures.
2777	*
2778	* This was previously also used by PGMR3PhysMmio2PreRegister, a function for
2779	* pre-registering MMIO that was later (6.1) replaced by a new handle based IOM
2780	* interface. The reference to caller and type above is purely historical.
2781	*
2782	* @returns VBox status code.
2783	* @param pVM The cross context VM structure.
2784	* @param pDevIns The device instance owning the region.
2785	* @param iSubDev The sub-device number (internal PCI config number).
2786	* @param iRegion The region number. If the MMIO2 memory is a PCI
2787	* I/O region this number has to be the number of that
2788	* region. Otherwise it can be any number safe
2789	* UINT8_MAX.
2790	* @param cb The size of the region. Must be page aligned.
2791	* @param pszDesc The description.
2792	* @param ppHeadRet Where to return the pointer to the first
2793	* registration chunk.
2794	*
2795	* @thread EMT
2796	*/
2797	static int pgmR3PhysMmio2Create(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2798	const char pszDesc, PPGMREGMMIO2RANGE ppHeadRet)
2799	{
2800	/*
2801	* Figure out how many chunks we need and of which size.
2802	*/
2803	uint32_t cPagesPerChunk;
2804	uint16_t cChunks = pgmR3PhysMmio2CalcChunkCount(pVM, cb, &cPagesPerChunk, NULL);
2805	AssertReturn(cChunks, VERR_PGM_PHYS_MMIO_EX_IPE);
2806
2807	/*
2808	* Allocate the chunks.
2809	*/
2810	PPGMREGMMIO2RANGE *ppNext = ppHeadRet;
2811	*ppNext = NULL;
2812
2813	int rc = VINF_SUCCESS;
2814	uint32_t cPagesLeft = cb >> X86_PAGE_SHIFT;
2815	for (uint16_t iChunk = 0; iChunk < cChunks && RT_SUCCESS(rc); iChunk++)
2816	{
2817	/*
2818	* We currently do a single RAM range for the whole thing. This will
2819	* probably have to change once someone needs really large MMIO regions,
2820	* as we will be running into SUPR3PageAllocEx limitations and such.
2821	*/
2822	const uint32_t cPagesTrackedByChunk = RT_MIN(cPagesLeft, cPagesPerChunk);
2823	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPagesTrackedByChunk]);
2824	PPGMREGMMIO2RANGE pNew = NULL;
2825	if ( iChunk + 1 < cChunks
2826	\|\| cbRange >= _1M)
2827	{
2828	/*
2829	* Allocate memory for the registration structure.
2830	*/
2831	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2832	size_t const cbChunk = (1 + cChunkPages + 1) << PAGE_SHIFT;
2833	AssertLogRelBreakStmt(cbChunk == (uint32_t)cbChunk, rc = VERR_OUT_OF_RANGE);
2834	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
2835	AssertBreakStmt(paChunkPages, rc = VERR_NO_TMP_MEMORY);
2836	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
2837	void *pvChunk = NULL;
2838	rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
2839	AssertLogRelMsgRCBreakStmt(rc, ("rc=%Rrc, cChunkPages=%#zx\n", rc, cChunkPages), RTMemTmpFree(paChunkPages));
2840
2841	Assert(R0PtrChunk != NIL_RTR0PTR);
2842	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
2843
2844	pNew = (PPGMREGMMIO2RANGE)pvChunk;
2845	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_FLOATING;
2846	pNew->RamRange.pSelfR0 = R0PtrChunk + RT_UOFFSETOF(PGMREGMMIO2RANGE, RamRange);
2847
2848	RTMemTmpFree(paChunkPages);
2849	}
2850	/*
2851	* Not so big, do a one time hyper allocation.
2852	*/
2853	else
2854	{
2855	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2856	AssertLogRelMsgRCBreak(rc, ("cbRange=%zu\n", cbRange));
2857
2858	/*
2859	* Initialize allocation specific items.
2860	*/
2861	//pNew->RamRange.fFlags = 0;
2862	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2863	}
2864
2865	/*
2866	* Initialize the registration structure (caller does specific bits).
2867	*/
2868	pNew->pDevInsR3 = pDevIns;
2869	//pNew->pvR3 = NULL;
2870	//pNew->pNext = NULL;
2871	//pNew->fFlags = 0;
2872	if (iChunk == 0)
2873	pNew->fFlags \|= PGMREGMMIO2RANGE_F_FIRST_CHUNK;
2874	if (iChunk + 1 == cChunks)
2875	pNew->fFlags \|= PGMREGMMIO2RANGE_F_LAST_CHUNK;
2876	pNew->iSubDev = iSubDev;
2877	pNew->iRegion = iRegion;
2878	pNew->idSavedState = UINT8_MAX;
2879	pNew->idMmio2 = UINT8_MAX;
2880	//pNew->pPhysHandlerR3 = NULL;
2881	//pNew->paLSPages = NULL;
2882	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2883	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2884	pNew->RamRange.pszDesc = pszDesc;
2885	pNew->RamRange.cb = pNew->cbReal = (RTGCPHYS)cPagesTrackedByChunk << X86_PAGE_SHIFT;
2886	pNew->RamRange.fFlags \|= PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX;
2887	//pNew->RamRange.pvR3 = NULL;
2888	//pNew->RamRange.paLSPages = NULL;
2889
2890	*ppNext = pNew;
2891	ASMCompilerBarrier();
2892	cPagesLeft -= cPagesTrackedByChunk;
2893	ppNext = &pNew->pNextR3;
2894	}
2895	Assert(cPagesLeft == 0);
2896
2897	if (RT_SUCCESS(rc))
2898	{
2899	Assert((*ppHeadRet)->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
2900	return VINF_SUCCESS;
2901	}
2902
2903	/*
2904	* Free floating ranges.
2905	*/
2906	while (*ppHeadRet)
2907	{
2908	PPGMREGMMIO2RANGE pFree = *ppHeadRet;
2909	*ppHeadRet = pFree->pNextR3;
2910
2911	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
2912	{
2913	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
2914	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2915	SUPR3PageFreeEx(pFree, cChunkPages);
2916	}
2917	}
2918
2919	return rc;
2920	}
2921
2922
2923	/**
2924	* Common worker PGMR3PhysMmio2PreRegister & PGMR3PhysMMIO2Register that links a
2925	* complete registration entry into the lists and lookup tables.
2926	*
2927	* @param pVM The cross context VM structure.
2928	* @param pNew The new MMIO / MMIO2 registration to link.
2929	*/
2930	static void pgmR3PhysMmio2Link(PVM pVM, PPGMREGMMIO2RANGE pNew)
2931	{
2932	/*
2933	* Link it into the list (order doesn't matter, so insert it at the head).
2934	*
2935	* Note! The range we're linking may consist of multiple chunks, so we
2936	* have to find the last one.
2937	*/
2938	PPGMREGMMIO2RANGE pLast = pNew;
2939	for (pLast = pNew; ; pLast = pLast->pNextR3)
2940	{
2941	if (pLast->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2942	break;
2943	Assert(pLast->pNextR3);
2944	Assert(pLast->pNextR3->pDevInsR3 == pNew->pDevInsR3);
2945	Assert(pLast->pNextR3->iSubDev == pNew->iSubDev);
2946	Assert(pLast->pNextR3->iRegion == pNew->iRegion);
2947	Assert((pLast->pNextR3->fFlags & PGMREGMMIO2RANGE_F_MMIO2) == (pNew->fFlags & PGMREGMMIO2RANGE_F_MMIO2));
2948	Assert(pLast->pNextR3->idMmio2 == (pLast->fFlags & PGMREGMMIO2RANGE_F_MMIO2 ? pLast->idMmio2 + 1 : UINT8_MAX));
2949	}
2950
2951	PGM_LOCK_VOID(pVM);
2952
2953	/* Link in the chain of ranges at the head of the list. */
2954	pLast->pNextR3 = pVM->pgm.s.pRegMmioRangesR3;
2955	pVM->pgm.s.pRegMmioRangesR3 = pNew;
2956
2957	/* If MMIO, insert the MMIO2 range/page IDs. */
2958	uint8_t idMmio2 = pNew->idMmio2;
2959	if (idMmio2 != UINT8_MAX)
2960	{
2961	for (;;)
2962	{
2963	Assert(pNew->fFlags & PGMREGMMIO2RANGE_F_MMIO2);
2964	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
2965	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
2966	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
2967	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = pNew->RamRange.pSelfR0 - RT_UOFFSETOF(PGMREGMMIO2RANGE, RamRange);
2968	if (pNew->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2969	break;
2970	pNew = pNew->pNextR3;
2971	idMmio2++;
2972	}
2973	}
2974	else
2975	Assert(!(pNew->fFlags & PGMREGMMIO2RANGE_F_MMIO2));
2976
2977	pgmPhysInvalidatePageMapTLB(pVM);
2978	PGM_UNLOCK(pVM);
2979	}
2980
2981
2982	/**
2983	* Allocate and register an MMIO2 region.
2984	*
2985	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2986	* associated with a device. It is also non-shared memory with a permanent
2987	* ring-3 mapping and page backing (presently).
2988	*
2989	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
2990	* the VM, in which case we'll drop the base memory pages. Presently we will
2991	* make no attempt to preserve anything that happens to be present in the base
2992	* memory that is replaced, this is of course incorrect but it's too much
2993	* effort.
2994	*
2995	* @returns VBox status code.
2996	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2997	* memory.
2998	* @retval VERR_ALREADY_EXISTS if the region already exists.
2999	*
3000	* @param pVM The cross context VM structure.
3001	* @param pDevIns The device instance owning the region.
3002	* @param iSubDev The sub-device number.
3003	* @param iRegion The region number. If the MMIO2 memory is a PCI
3004	* I/O region this number has to be the number of that
3005	* region. Otherwise it can be any number save
3006	* UINT8_MAX.
3007	* @param cb The size of the region. Must be page aligned.
3008	* @param fFlags Reserved for future use, must be zero.
3009	* @param pszDesc The description.
3010	* @param ppv Where to store the pointer to the ring-3 mapping of
3011	* the memory.
3012	* @param phRegion Where to return the MMIO2 region handle. Optional.
3013	* @thread EMT
3014	*/
3015	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
3016	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion)
3017	{
3018	/*
3019	* Validate input.
3020	*/
3021	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
3022	*ppv = NULL;
3023	if (phRegion)
3024	{
3025	AssertPtrReturn(phRegion, VERR_INVALID_POINTER);
3026	*phRegion = NIL_PGMMMIO2HANDLE;
3027	}
3028	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3029	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3030	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3031	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3032	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3033	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3034	AssertReturn(pgmR3PhysMmio2Find(pVM, pDevIns, iSubDev, iRegion, NIL_PGMMMIO2HANDLE) == NULL, VERR_ALREADY_EXISTS);
3035	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3036	AssertReturn(cb, VERR_INVALID_PARAMETER);
3037	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
3038
3039	const uint32_t cPages = cb >> PAGE_SHIFT;
3040	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
3041	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3042	AssertLogRelReturn(cPages <= PGM_MMIO2_MAX_PAGE_COUNT, VERR_OUT_OF_RANGE);
3043
3044	/*
3045	* For the 2nd+ instance, mangle the description string so it's unique.
3046	*/
3047	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3048	{
3049	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3050	if (!pszDesc)
3051	return VERR_NO_MEMORY;
3052	}
3053
3054	/*
3055	* Allocate an MMIO2 range ID (not freed on failure).
3056	*
3057	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID, so
3058	* the IDs goes from 1 thru PGM_MMIO2_MAX_RANGES.
3059	*/
3060	unsigned cChunks = pgmR3PhysMmio2CalcChunkCount(pVM, cb, NULL, NULL);
3061	PGM_LOCK_VOID(pVM);
3062	uint8_t idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
3063	unsigned cNewMmio2Regions = pVM->pgm.s.cMmio2Regions + cChunks;
3064	if (cNewMmio2Regions > PGM_MMIO2_MAX_RANGES)
3065	{
3066	PGM_UNLOCK(pVM);
3067	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
3068	}
3069	pVM->pgm.s.cMmio2Regions = cNewMmio2Regions;
3070	PGM_UNLOCK(pVM);
3071
3072	/*
3073	* Try reserve and allocate the backing memory first as this is what is
3074	* most likely to fail.
3075	*/
3076	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
3077	if (RT_SUCCESS(rc))
3078	{
3079	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
3080	if (RT_SUCCESS(rc))
3081	{
3082	void *pvPages;
3083	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3084	RTR0PTR pvPagesR0;
3085	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, &pvPagesR0, paPages);
3086	#else
3087	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
3088	#endif
3089	if (RT_SUCCESS(rc))
3090	{
3091	memset(pvPages, 0, cPages * PAGE_SIZE);
3092
3093	/*
3094	* Create the registered MMIO range record for it.
3095	*/
3096	PPGMREGMMIO2RANGE pNew;
3097	rc = pgmR3PhysMmio2Create(pVM, pDevIns, iSubDev, iRegion, cb, pszDesc, &pNew);
3098	if (RT_SUCCESS(rc))
3099	{
3100	if (phRegion)
3101	phRegion = idMmio2; / The ID of the first chunk. */
3102
3103	uint32_t iSrcPage = 0;
3104	uint8_t pbCurPages = (uint8_t )pvPages;
3105	for (PPGMREGMMIO2RANGE pCur = pNew; pCur; pCur = pCur->pNextR3)
3106	{
3107	pCur->pvR3 = pbCurPages;
3108	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3109	pCur->pvR0 = pvPagesR0 + (iSrcPage << PAGE_SHIFT);
3110	#endif
3111	pCur->RamRange.pvR3 = pbCurPages;
3112	pCur->idMmio2 = idMmio2;
3113	pCur->fFlags \|= PGMREGMMIO2RANGE_F_MMIO2;
3114
3115	uint32_t iDstPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3116	while (iDstPage-- > 0)
3117	{
3118	PGM_PAGE_INIT(&pNew->RamRange.aPages[iDstPage],
3119	paPages[iDstPage + iSrcPage].Phys,
3120	PGM_MMIO2_PAGEID_MAKE(idMmio2, iDstPage),
3121	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
3122	}
3123
3124	/* advance. */
3125	iSrcPage += pCur->RamRange.cb >> X86_PAGE_SHIFT;
3126	pbCurPages += pCur->RamRange.cb;
3127	idMmio2++;
3128	}
3129
3130	RTMemTmpFree(paPages);
3131
3132	/*
3133	* Update the page count stats, link the registration and we're done.
3134	*/
3135	pVM->pgm.s.cAllPages += cPages;
3136	pVM->pgm.s.cPrivatePages += cPages;
3137
3138	pgmR3PhysMmio2Link(pVM, pNew);
3139
3140	*ppv = pvPages;
3141	return VINF_SUCCESS;
3142	}
3143
3144	SUPR3PageFreeEx(pvPages, cPages);
3145	}
3146	}
3147	RTMemTmpFree(paPages);
3148	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
3149	}
3150	if (pDevIns->iInstance > 0)
3151	MMR3HeapFree((void *)pszDesc);
3152	return rc;
3153	}
3154
3155
3156	/**
3157	* Deregisters and frees an MMIO2 region.
3158	*
3159	* Any physical access handlers registered for the region must be deregistered
3160	* before calling this function.
3161	*
3162	* @returns VBox status code.
3163	* @param pVM The cross context VM structure.
3164	* @param pDevIns The device instance owning the region.
3165	* @param hMmio2 The MMIO2 handle to deregister, or NIL if all
3166	* regions for the given device is to be deregistered.
3167	*/
3168	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3169	{
3170	/*
3171	* Validate input.
3172	*/
3173	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3174	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3175
3176	/*
3177	* The loop here scanning all registrations will make sure that multi-chunk ranges
3178	* get properly deregistered, though it's original purpose was the wildcard iRegion.
3179	*/
3180	PGM_LOCK_VOID(pVM);
3181	int rc = VINF_SUCCESS;
3182	unsigned cFound = 0;
3183	PPGMREGMMIO2RANGE pPrev = NULL;
3184	PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3;
3185	while (pCur)
3186	{
3187	uint32_t const fFlags = pCur->fFlags;
3188	if ( pCur->pDevInsR3 == pDevIns
3189	&& ( hMmio2 == NIL_PGMMMIO2HANDLE
3190	\|\| pCur->idMmio2 == hMmio2))
3191	{
3192	Assert(fFlags & PGMREGMMIO2RANGE_F_MMIO2);
3193	cFound++;
3194
3195	/*
3196	* Unmap it if it's mapped.
3197	*/
3198	if (fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3199	{
3200	int rc2 = PGMR3PhysMmio2Unmap(pVM, pCur->pDevInsR3, pCur->idMmio2, pCur->RamRange.GCPhys);
3201	AssertRC(rc2);
3202	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3203	rc = rc2;
3204	}
3205
3206	/*
3207	* Unlink it
3208	*/
3209	PPGMREGMMIO2RANGE pNext = pCur->pNextR3;
3210	if (pPrev)
3211	pPrev->pNextR3 = pNext;
3212	else
3213	pVM->pgm.s.pRegMmioRangesR3 = pNext;
3214	pCur->pNextR3 = NULL;
3215
3216	uint8_t idMmio2 = pCur->idMmio2;
3217	if (idMmio2 != UINT8_MAX)
3218	{
3219	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
3220	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
3221	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
3222	}
3223
3224	/*
3225	* Free the memory.
3226	*/
3227	const bool fIsMmio2 = RT_BOOL(fFlags & PGMREGMMIO2RANGE_F_MMIO2);
3228	uint32_t const cPages = pCur->cbReal >> PAGE_SHIFT;
3229	if (fIsMmio2)
3230	{
3231	int rc2 = SUPR3PageFreeEx(pCur->pvR3, cPages);
3232	AssertRC(rc2);
3233	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3234	rc = rc2;
3235
3236	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
3237	AssertRC(rc2);
3238	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3239	rc = rc2;
3240	}
3241
3242	/* we're leaking hyper memory here if done at runtime. */
3243	#ifdef VBOX_STRICT
3244	VMSTATE const enmState = VMR3GetState(pVM);
3245	AssertMsg( enmState == VMSTATE_POWERING_OFF
3246	\|\| enmState == VMSTATE_POWERING_OFF_LS
3247	\|\| enmState == VMSTATE_OFF
3248	\|\| enmState == VMSTATE_OFF_LS
3249	\|\| enmState == VMSTATE_DESTROYING
3250	\|\| enmState == VMSTATE_TERMINATED
3251	\|\| enmState == VMSTATE_CREATING
3252	, ("%s\n", VMR3GetStateName(enmState)));
3253	#endif
3254
3255	if (pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3256	{
3257	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPages]);
3258	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3259	SUPR3PageFreeEx(pCur, cChunkPages);
3260	}
3261	/*else
3262	{
3263	rc = MMHyperFree(pVM, pCur); - does not work, see the alloc call.
3264	AssertRCReturn(rc, rc);
3265	} */
3266
3267
3268	/* update page count stats */
3269	pVM->pgm.s.cAllPages -= cPages;
3270	if (fIsMmio2)
3271	pVM->pgm.s.cPrivatePages -= cPages;
3272	else
3273	pVM->pgm.s.cPureMmioPages -= cPages;
3274
3275	/* next */
3276	pCur = pNext;
3277	if (hMmio2 != NIL_PGMMMIO2HANDLE)
3278	{
3279	if (fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3280	break;
3281	hMmio2++;
3282	Assert(pCur->idMmio2 == hMmio2);
3283	Assert(pCur->pDevInsR3 == pDevIns);
3284	Assert(!(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK));
3285	}
3286	}
3287	else
3288	{
3289	pPrev = pCur;
3290	pCur = pCur->pNextR3;
3291	}
3292	}
3293	pgmPhysInvalidatePageMapTLB(pVM);
3294	PGM_UNLOCK(pVM);
3295	return !cFound && hMmio2 != NIL_PGMMMIO2HANDLE ? VERR_NOT_FOUND : rc;
3296	}
3297
3298
3299	/**
3300	* Maps a MMIO2 region.
3301	*
3302	* This is typically done when a guest / the bios / state loading changes the
3303	* PCI config. The replacing of base memory has the same restrictions as during
3304	* registration, of course.
3305	*
3306	* @returns VBox status code.
3307	*
3308	* @param pVM The cross context VM structure.
3309	* @param pDevIns The device instance owning the region.
3310	* @param hMmio2 The handle of the region to map.
3311	* @param GCPhys The guest-physical address to be remapped.
3312	*/
3313	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys)
3314	{
3315	/*
3316	* Validate input.
3317	*
3318	* Note! It's safe to walk the MMIO/MMIO2 list since registrations only
3319	* happens during VM construction.
3320	*/
3321	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3322	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3323	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3324	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3325	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3326	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3327
3328	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3329	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3330	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3331
3332	PPGMREGMMIO2RANGE pLastMmio = pFirstMmio;
3333	RTGCPHYS cbRange = 0;
3334	for (;;)
3335	{
3336	AssertReturn(!(pLastMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED), VERR_WRONG_ORDER);
3337	Assert(pLastMmio->RamRange.GCPhys == NIL_RTGCPHYS);
3338	Assert(pLastMmio->RamRange.GCPhysLast == NIL_RTGCPHYS);
3339	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3340	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3341	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3342	cbRange += pLastMmio->RamRange.cb;
3343	if (pLastMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3344	break;
3345	pLastMmio = pLastMmio->pNextR3;
3346	}
3347
3348	RTGCPHYS GCPhysLast = GCPhys + cbRange - 1;
3349	AssertLogRelReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3350
3351	/*
3352	* Find our location in the ram range list, checking for restriction
3353	* we don't bother implementing yet (partially overlapping, multiple
3354	* ram ranges).
3355	*/
3356	PGM_LOCK_VOID(pVM);
3357
3358	AssertReturnStmt(!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED), PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3359
3360	bool fRamExists = false;
3361	PPGMRAMRANGE pRamPrev = NULL;
3362	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3363	while (pRam && GCPhysLast >= pRam->GCPhys)
3364	{
3365	if ( GCPhys <= pRam->GCPhysLast
3366	&& GCPhysLast >= pRam->GCPhys)
3367	{
3368	/* Completely within? */
3369	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
3370	&& GCPhysLast <= pRam->GCPhysLast,
3371	("%RGp-%RGp (MMIOEx/%s) falls partly outside %RGp-%RGp (%s)\n",
3372	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc,
3373	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3374	PGM_UNLOCK(pVM),
3375	VERR_PGM_RAM_CONFLICT);
3376
3377	/* Check that all the pages are RAM pages. */
3378	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3379	uint32_t cPagesLeft = cbRange >> PAGE_SHIFT;
3380	while (cPagesLeft-- > 0)
3381	{
3382	AssertLogRelMsgReturnStmt(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3383	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
3384	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc),
3385	PGM_UNLOCK(pVM),
3386	VERR_PGM_RAM_CONFLICT);
3387	pPage++;
3388	}
3389
3390	/* There can only be one MMIO/MMIO2 chunk matching here! */
3391	AssertLogRelMsgReturnStmt(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK,
3392	("%RGp-%RGp (MMIOEx/%s, flags %#X) consists of multiple chunks whereas the RAM somehow doesn't!\n",
3393	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3394	PGM_UNLOCK(pVM),
3395	VERR_PGM_PHYS_MMIO_EX_IPE);
3396
3397	fRamExists = true;
3398	break;
3399	}
3400
3401	/* next */
3402	pRamPrev = pRam;
3403	pRam = pRam->pNextR3;
3404	}
3405	Log(("PGMR3PhysMmio2Map: %RGp-%RGp fRamExists=%RTbool %s\n", GCPhys, GCPhysLast, fRamExists, pFirstMmio->RamRange.pszDesc));
3406
3407
3408	/*
3409	* Make the changes.
3410	*/
3411	RTGCPHYS GCPhysCur = GCPhys;
3412	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3413	{
3414	pCurMmio->RamRange.GCPhys = GCPhysCur;
3415	pCurMmio->RamRange.GCPhysLast = GCPhysCur + pCurMmio->RamRange.cb - 1;
3416	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3417	{
3418	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3419	break;
3420	}
3421	GCPhysCur += pCurMmio->RamRange.cb;
3422	}
3423
3424	if (fRamExists)
3425	{
3426	/*
3427	* Make all the pages in the range MMIO/ZERO pages, freeing any
3428	* RAM pages currently mapped here. This might not be 100% correct
3429	* for PCI memory, but we're doing the same thing for MMIO2 pages.
3430	*
3431	* We replace these MMIO/ZERO pages with real pages in the MMIO2 case.
3432	*/
3433	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK); /* Only one chunk */
3434	Assert(pFirstMmio->pvR3 == pFirstMmio->RamRange.pvR3);
3435	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2
3436	? pFirstMmio->RamRange.pvR3 != NULL : pFirstMmio->RamRange.pvR3 == NULL);
3437
3438	#ifdef VBOX_WITH_PGM_NEM_MODE
3439	/* We cannot mix MMIO2 into a RAM range in simplified memory mode because pRam->pvR3 can't point
3440	both at the RAM and MMIO2, so we won't ever write & read from the actual MMIO2 memory if we try. */
3441	AssertLogRelMsgReturn(!pVM->pgm.s.fNemMode \|\| !(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2),
3442	("%s at %RGp-%RGp\n", pFirstMmio->RamRange.pszDesc, GCPhys, GCPhysLast),
3443	VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
3444	#endif
3445
3446	int rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, pFirstMmio->RamRange.pvR3);
3447	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3448
3449	if (pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2)
3450	{
3451	/* replace the pages, freeing all present RAM pages. */
3452	PPGMPAGE pPageSrc = &pFirstMmio->RamRange.aPages[0];
3453	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3454	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3455	while (cPagesLeft-- > 0)
3456	{
3457	Assert(PGM_PAGE_IS_MMIO(pPageDst));
3458
3459	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
3460	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
3461	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
3462	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
3463	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
3464	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
3465	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
3466	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
3467	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
3468	/* NEM state is set by pgmR3PhysFreePageRange. */
3469
3470	pVM->pgm.s.cZeroPages--;
3471	GCPhys += PAGE_SIZE;
3472	pPageSrc++;
3473	pPageDst++;
3474	}
3475	}
3476
3477	/* Flush physical page map TLB. */
3478	pgmPhysInvalidatePageMapTLB(pVM);
3479
3480	/* Force a PGM pool flush as guest ram references have been changed. */
3481	/** @todo not entirely SMP safe; assuming for now the guest takes care of
3482	* this internally (not touch mapped mmio while changing the mapping). */
3483	PVMCPU pVCpu = VMMGetCpu(pVM);
3484	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3485	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3486	}
3487	else
3488	{
3489	/*
3490	* No RAM range, insert the ones prepared during registration.
3491	*/
3492	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3493	{
3494	#ifdef VBOX_WITH_NATIVE_NEM
3495	/* Tell NEM and get the new NEM state for the pages. */
3496	uint8_t u2NemState = 0;
3497	if (VM_IS_NEM_ENABLED(pVM))
3498	{
3499	int rc = NEMR3NotifyPhysMmioExMapEarly(pVM, pCurMmio->RamRange.GCPhys,
3500	pCurMmio->RamRange.GCPhysLast - pCurMmio->RamRange.GCPhys + 1,
3501	pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2
3502	? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0,
3503	NULL, pCurMmio->RamRange.pvR3, &u2NemState);
3504	AssertLogRelRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3505	}
3506	#endif
3507
3508	/* Clear the tracking data of pages we're going to reactivate. */
3509	PPGMPAGE pPageSrc = &pCurMmio->RamRange.aPages[0];
3510	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3511	while (cPagesLeft-- > 0)
3512	{
3513	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
3514	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
3515	#ifdef VBOX_WITH_NATIVE_NEM
3516	PGM_PAGE_SET_NEM_STATE(pPageSrc, u2NemState);
3517	#endif
3518	pPageSrc++;
3519	}
3520
3521	/* link in the ram range */
3522	pgmR3PhysLinkRamRange(pVM, &pCurMmio->RamRange, pRamPrev);
3523
3524	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3525	{
3526	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3527	break;
3528	}
3529	pRamPrev = &pCurMmio->RamRange;
3530	}
3531	}
3532
3533	/*
3534	* Register the access handler if plain MMIO.
3535	*
3536	* We must register access handlers for each range since the access handler
3537	* code refuses to deal with multiple ranges (and we can).
3538	*/
3539	if (!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2))
3540	{
3541	AssertFailed();
3542	int rc = VINF_SUCCESS;
3543	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3544	{
3545	Assert(!(pCurMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED));
3546	rc = pgmHandlerPhysicalExRegister(pVM, pCurMmio->pPhysHandlerR3, pCurMmio->RamRange.GCPhys,
3547	pCurMmio->RamRange.GCPhysLast);
3548	if (RT_FAILURE(rc))
3549	break;
3550	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_MAPPED; /* Use this to mark that the handler is registered. */
3551	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3552	break;
3553	}
3554	if (RT_FAILURE(rc))
3555	{
3556	/* Almost impossible, but try clean up properly and get out of here. */
3557	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3558	{
3559	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3560	{
3561	pCurMmio->fFlags &= ~PGMREGMMIO2RANGE_F_MAPPED;
3562	pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3);
3563	}
3564
3565	if (!fRamExists)
3566	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3567	else
3568	{
3569	Assert(pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK); /* Only one chunk */
3570
3571	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3572	PPGMPAGE pPageDst = &pRam->aPages[(pCurMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3573	while (cPagesLeft-- > 0)
3574	{
3575	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3576	pPageDst++;
3577	}
3578	}
3579
3580	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3581	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3582	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3583	break;
3584	}
3585
3586	/** @todo NEM notification cleanup */
3587	PGM_UNLOCK(pVM);
3588	return rc;
3589	}
3590	}
3591
3592	/*
3593	* We're good, set the flags and invalid the mapping TLB.
3594	*/
3595	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3596	{
3597	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_MAPPED;
3598	if (fRamExists)
3599	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_OVERLAPPING;
3600	else
3601	pCurMmio->fFlags &= ~PGMREGMMIO2RANGE_F_OVERLAPPING;
3602	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3603	break;
3604	}
3605	pgmPhysInvalidatePageMapTLB(pVM);
3606
3607	#ifdef VBOX_WITH_NATIVE_NEM
3608	/*
3609	* Late NEM notification.
3610	*/
3611	if (VM_IS_NEM_ENABLED(pVM))
3612	{
3613	int rc;
3614	uint32_t fNemFlags = pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0;
3615	if (fRamExists)
3616	rc = NEMR3NotifyPhysMmioExMapLate(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemFlags \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
3617	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL, pFirstMmio->pvR3);
3618	else
3619	{
3620	rc = VINF_SUCCESS;
3621	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3622	{
3623	rc = NEMR3NotifyPhysMmioExMapLate(pVM, pCurMmio->RamRange.GCPhys, pCurMmio->RamRange.cb, fNemFlags,
3624	NULL, pCurMmio->RamRange.pvR3);
3625	if ((pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK) \|\| RT_FAILURE(rc))
3626	break;
3627	}
3628	}
3629	AssertLogRelRCReturnStmt(rc, PGMR3PhysMmio2Unmap(pVM, pDevIns, hMmio2, GCPhys); PGM_UNLOCK(pVM), rc);
3630	}
3631	#endif
3632
3633	PGM_UNLOCK(pVM);
3634
3635	return VINF_SUCCESS;
3636	}
3637
3638
3639	/**
3640	* Unmaps an MMIO2 region.
3641	*
3642	* This is typically done when a guest / the bios / state loading changes the
3643	* PCI config. The replacing of base memory has the same restrictions as during
3644	* registration, of course.
3645	*/
3646	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys)
3647	{
3648	/*
3649	* Validate input
3650	*/
3651	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3652	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3653	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3654	if (GCPhys != NIL_RTGCPHYS)
3655	{
3656	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3657	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3658	}
3659
3660	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3661	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3662	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3663
3664	int rc = PGM_LOCK(pVM);
3665	AssertRCReturn(rc, rc);
3666
3667	PPGMREGMMIO2RANGE pLastMmio = pFirstMmio;
3668	RTGCPHYS cbRange = 0;
3669	for (;;)
3670	{
3671	AssertReturnStmt(pLastMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED, PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3672	AssertReturnStmt(pLastMmio->RamRange.GCPhys == GCPhys + cbRange \|\| GCPhys == NIL_RTGCPHYS, PGM_UNLOCK(pVM), VERR_INVALID_PARAMETER);
3673	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3674	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3675	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3676	cbRange += pLastMmio->RamRange.cb;
3677	if (pLastMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3678	break;
3679	pLastMmio = pLastMmio->pNextR3;
3680	}
3681
3682	Log(("PGMR3PhysMmio2Unmap: %RGp-%RGp %s\n",
3683	pFirstMmio->RamRange.GCPhys, pLastMmio->RamRange.GCPhysLast, pFirstMmio->RamRange.pszDesc));
3684
3685	uint16_t const fOldFlags = pFirstMmio->fFlags;
3686	AssertReturnStmt(fOldFlags & PGMREGMMIO2RANGE_F_MAPPED, PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3687
3688	/*
3689	* If plain MMIO, we must deregister the handlers first.
3690	*/
3691	if (!(fOldFlags & PGMREGMMIO2RANGE_F_MMIO2))
3692	{
3693	AssertFailed();
3694
3695	PPGMREGMMIO2RANGE pCurMmio = pFirstMmio;
3696	rc = pgmHandlerPhysicalExDeregister(pVM, pFirstMmio->pPhysHandlerR3);
3697	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3698	while (!(pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK))
3699	{
3700	pCurMmio = pCurMmio->pNextR3;
3701	rc = pgmHandlerPhysicalExDeregister(pVM, pCurMmio->pPhysHandlerR3);
3702	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), VERR_PGM_PHYS_MMIO_EX_IPE);
3703	}
3704	}
3705
3706	/*
3707	* Unmap it.
3708	*/
3709	int rcRet = VINF_SUCCESS;
3710	#ifdef VBOX_WITH_NATIVE_NEM
3711	uint32_t const fNemFlags = pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0;
3712	#endif
3713	if (fOldFlags & PGMREGMMIO2RANGE_F_OVERLAPPING)
3714	{
3715	/*
3716	* We've replaced RAM, replace with zero pages.
3717	*
3718	* Note! This is where we might differ a little from a real system, because
3719	* it's likely to just show the RAM pages as they were before the
3720	* MMIO/MMIO2 region was mapped here.
3721	*/
3722	/* Only one chunk allowed when overlapping! */
3723	Assert(fOldFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK);
3724
3725	/* Restore the RAM pages we've replaced. */
3726	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3727	while (pRam->GCPhys > pFirstMmio->RamRange.GCPhysLast)
3728	pRam = pRam->pNextR3;
3729
3730	PPGMPAGE pPageDst = &pRam->aPages[(pFirstMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3731	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3732	if (fOldFlags & PGMREGMMIO2RANGE_F_MMIO2)
3733	pVM->pgm.s.cZeroPages += cPagesLeft;
3734
3735	#ifdef VBOX_WITH_NATIVE_NEM
3736	if (VM_IS_NEM_ENABLED(pVM)) /* Notify NEM. Note! we cannot be here in simple memory mode, see mapping function. */
3737	{
3738	uint8_t u2State = UINT8_MAX;
3739	rc = NEMR3NotifyPhysMmioExUnmap(pVM, pFirstMmio->RamRange.GCPhys, pFirstMmio->RamRange.cb,
3740	fNemFlags \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
3741	pRam->pvR3
3742	? (uint8_t *)pRam->pvR3 + pFirstMmio->RamRange.GCPhys - pRam->GCPhys : NULL,
3743	pFirstMmio->pvR3, &u2State);
3744	AssertRCStmt(rc, rcRet = rc);
3745	if (u2State != UINT8_MAX)
3746	pgmPhysSetNemStateForPages(pPageDst, cPagesLeft, u2State);
3747	}
3748	#endif
3749
3750	while (cPagesLeft-- > 0)
3751	{
3752	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3753	pPageDst++;
3754	}
3755
3756	/* Flush physical page map TLB. */
3757	pgmPhysInvalidatePageMapTLB(pVM);
3758
3759	/* Update range state. */
3760	pFirstMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3761	pFirstMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3762	pFirstMmio->fFlags &= ~(PGMREGMMIO2RANGE_F_OVERLAPPING \| PGMREGMMIO2RANGE_F_MAPPED);
3763	}
3764	else
3765	{
3766	/*
3767	* Unlink the chunks related to the MMIO/MMIO2 region.
3768	*/
3769	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3770	{
3771	#ifdef VBOX_WITH_NATIVE_NEM
3772	if (VM_IS_NEM_ENABLED(pVM)) /* Notify NEM. */
3773	{
3774	uint8_t u2State = UINT8_MAX;
3775	rc = NEMR3NotifyPhysMmioExUnmap(pVM, pCurMmio->RamRange.GCPhys, pCurMmio->RamRange.cb, fNemFlags,
3776	NULL, pCurMmio->pvR3, &u2State);
3777	AssertRCStmt(rc, rcRet = rc);
3778	if (u2State != UINT8_MAX)
3779	pgmPhysSetNemStateForPages(pCurMmio->RamRange.aPages, pCurMmio->RamRange.cb >> PAGE_SHIFT, u2State);
3780	}
3781	#endif
3782	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3783	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3784	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3785	pCurMmio->fFlags &= ~(PGMREGMMIO2RANGE_F_OVERLAPPING \| PGMREGMMIO2RANGE_F_MAPPED);
3786	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3787	break;
3788	}
3789	}
3790
3791	/* Force a PGM pool flush as guest ram references have been changed. */
3792	/** @todo not entirely SMP safe; assuming for now the guest takes care
3793	* of this internally (not touch mapped mmio while changing the
3794	* mapping). */
3795	PVMCPU pVCpu = VMMGetCpu(pVM);
3796	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3797	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3798
3799	pgmPhysInvalidatePageMapTLB(pVM);
3800	pgmPhysInvalidRamRangeTlbs(pVM);
3801
3802	PGM_UNLOCK(pVM);
3803	return rcRet;
3804	}
3805
3806
3807	/**
3808	* Reduces the mapping size of a MMIO2 region.
3809	*
3810	* This is mainly for dealing with old saved states after changing the default
3811	* size of a mapping region. See PGMDevHlpMMIOExReduce and
3812	* PDMPCIDEV::pfnRegionLoadChangeHookR3.
3813	*
3814	* The region must not currently be mapped when making this call. The VM state
3815	* must be state restore or VM construction.
3816	*
3817	* @returns VBox status code.
3818	* @param pVM The cross context VM structure.
3819	* @param pDevIns The device instance owning the region.
3820	* @param hMmio2 The handle of the region to reduce.
3821	* @param cbRegion The new mapping size.
3822	*/
3823	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion)
3824	{
3825	/*
3826	* Validate input
3827	*/
3828	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3829	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3830	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3831	AssertReturn(cbRegion >= X86_PAGE_SIZE, VERR_INVALID_PARAMETER);
3832	AssertReturn(!(cbRegion & X86_PAGE_OFFSET_MASK), VERR_UNSUPPORTED_ALIGNMENT);
3833	VMSTATE enmVmState = VMR3GetState(pVM);
3834	AssertLogRelMsgReturn( enmVmState == VMSTATE_CREATING
3835	\|\| enmVmState == VMSTATE_LOADING,
3836	("enmVmState=%d (%s)\n", enmVmState, VMR3GetStateName(enmVmState)),
3837	VERR_VM_INVALID_VM_STATE);
3838
3839	int rc = PGM_LOCK(pVM);
3840	AssertRCReturn(rc, rc);
3841
3842	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3843	if (pFirstMmio)
3844	{
3845	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3846	if (!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED))
3847	{
3848	/*
3849	* NOTE! Current implementation does not support multiple ranges.
3850	* Implement when there is a real world need and thus a testcase.
3851	*/
3852	AssertLogRelMsgStmt(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK,
3853	("%s: %#x\n", pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3854	rc = VERR_NOT_SUPPORTED);
3855	if (RT_SUCCESS(rc))
3856	{
3857	/*
3858	* Make the change.
3859	*/
3860	Log(("PGMR3PhysMmio2Reduce: %s changes from %RGp bytes (%RGp) to %RGp bytes.\n",
3861	pFirstMmio->RamRange.pszDesc, pFirstMmio->RamRange.cb, pFirstMmio->cbReal, cbRegion));
3862
3863	AssertLogRelMsgStmt(cbRegion <= pFirstMmio->cbReal,
3864	("%s: cbRegion=%#RGp cbReal=%#RGp\n", pFirstMmio->RamRange.pszDesc, cbRegion, pFirstMmio->cbReal),
3865	rc = VERR_OUT_OF_RANGE);
3866	if (RT_SUCCESS(rc))
3867	{
3868	pFirstMmio->RamRange.cb = cbRegion;
3869	}
3870	}
3871	}
3872	else
3873	rc = VERR_WRONG_ORDER;
3874	}
3875	else
3876	rc = VERR_NOT_FOUND;
3877
3878	PGM_UNLOCK(pVM);
3879	return rc;
3880	}
3881
3882
3883	/**
3884	* Validates @a hMmio2, making sure it belongs to @a pDevIns.
3885	*
3886	* @returns VBox status code.
3887	* @param pVM The cross context VM structure.
3888	* @param pDevIns The device which allegedly owns @a hMmio2.
3889	* @param hMmio2 The handle to validate.
3890	*/
3891	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3892	{
3893	/*
3894	* Validate input
3895	*/
3896	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3897	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
3898
3899	/*
3900	* Just do this the simple way. No need for locking as this is only taken at
3901	*/
3902	PGM_LOCK_VOID(pVM);
3903	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3904	PGM_UNLOCK(pVM);
3905	AssertReturn(pFirstMmio, VERR_INVALID_HANDLE);
3906	AssertReturn(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MMIO2, VERR_INVALID_HANDLE);
3907	AssertReturn(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, VERR_INVALID_HANDLE);
3908	return VINF_SUCCESS;
3909	}
3910
3911
3912	/**
3913	* Gets the mapping address of an MMIO2 region.
3914	*
3915	* @returns Mapping address, NIL_RTGCPHYS if not mapped or invalid handle.
3916	*
3917	* @param pVM The cross context VM structure.
3918	* @param pDevIns The device owning the MMIO2 handle.
3919	* @param hMmio2 The region handle.
3920	*/
3921	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3922	{
3923	AssertPtrReturn(pDevIns, NIL_RTGCPHYS);
3924
3925	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3926	AssertReturn(pFirstRegMmio, NIL_RTGCPHYS);
3927
3928	if (pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3929	return pFirstRegMmio->RamRange.GCPhys;
3930	return NIL_RTGCPHYS;
3931	}
3932
3933	/**
3934	* Changes the region number of an MMIO2 region.
3935	*
3936	* This is only for dealing with save state issues, nothing else.
3937	*
3938	* @return VBox status code.
3939	*
3940	* @param pVM The cross context VM structure.
3941	* @param pDevIns The device owning the MMIO2 memory.
3942	* @param hMmio2 The handle of the region.
3943	* @param iNewRegion The new region index.
3944	*
3945	* @thread EMT(0)
3946	* @sa @bugref{9359}
3947	*/
3948	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion)
3949	{
3950	/*
3951	* Validate input.
3952	*/
3953	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3954	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_LOADING, VERR_VM_INVALID_VM_STATE);
3955	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3956	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3957	AssertReturn(iNewRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3958
3959	AssertReturn(pVM->enmVMState == VMSTATE_LOADING, VERR_INVALID_STATE);
3960
3961	int rc = PGM_LOCK(pVM);
3962	AssertRCReturn(rc, rc);
3963
3964	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3965	AssertReturnStmt(pFirstRegMmio, PGM_UNLOCK(pVM), VERR_NOT_FOUND);
3966	AssertReturnStmt(pgmR3PhysMmio2Find(pVM, pDevIns, pFirstRegMmio->iSubDev, iNewRegion, NIL_PGMMMIO2HANDLE) == NULL,
3967	PGM_UNLOCK(pVM), VERR_RESOURCE_IN_USE);
3968
3969	/*
3970	* Make the change.
3971	*/
3972	pFirstRegMmio->iRegion = (uint8_t)iNewRegion;
3973
3974	PGM_UNLOCK(pVM);
3975	return VINF_SUCCESS;
3976	}
3977
3978
3979	/**
3980	* Worker for PGMR3PhysRomRegister.
3981	*
3982	* This is here to simplify lock management, i.e. the caller does all the
3983	* locking and we can simply return without needing to remember to unlock
3984	* anything first.
3985	*
3986	* @returns VBox status code.
3987	* @param pVM The cross context VM structure.
3988	* @param pDevIns The device instance owning the ROM.
3989	* @param GCPhys First physical address in the range.
3990	* Must be page aligned!
3991	* @param cb The size of the range (in bytes).
3992	* Must be page aligned!
3993	* @param pvBinary Pointer to the binary data backing the ROM image.
3994	* @param cbBinary The size of the binary data pvBinary points to.
3995	* This must be less or equal to @a cb.
3996	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
3997	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
3998	* @param pszDesc Pointer to description string. This must not be freed.
3999	*/
4000	static int pgmR3PhysRomRegisterLocked(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4001	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc)
4002	{
4003	/*
4004	* Validate input.
4005	*/
4006	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4007	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
4008	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
4009	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4010	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4011	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
4012	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
4013	AssertReturn(!(fFlags & ~PGMPHYS_ROM_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
4014	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
4015
4016	const uint32_t cPages = cb >> PAGE_SHIFT;
4017
4018	/*
4019	* Find the ROM location in the ROM list first.
4020	*/
4021	PPGMROMRANGE pRomPrev = NULL;
4022	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
4023	while (pRom && GCPhysLast >= pRom->GCPhys)
4024	{
4025	if ( GCPhys <= pRom->GCPhysLast
4026	&& GCPhysLast >= pRom->GCPhys)
4027	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
4028	GCPhys, GCPhysLast, pszDesc,
4029	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
4030	VERR_PGM_RAM_CONFLICT);
4031	/* next */
4032	pRomPrev = pRom;
4033	pRom = pRom->pNextR3;
4034	}
4035
4036	/*
4037	* Find the RAM location and check for conflicts.
4038	*
4039	* Conflict detection is a bit different than for RAM registration since a
4040	* ROM can be located within a RAM range. So, what we have to check for is
4041	* other memory types (other than RAM that is) and that we don't span more
4042	* than one RAM range (lazy).
4043	*/
4044	bool fRamExists = false;
4045	PPGMRAMRANGE pRamPrev = NULL;
4046	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4047	while (pRam && GCPhysLast >= pRam->GCPhys)
4048	{
4049	if ( GCPhys <= pRam->GCPhysLast
4050	&& GCPhysLast >= pRam->GCPhys)
4051	{
4052	/* completely within? */
4053	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
4054	&& GCPhysLast <= pRam->GCPhysLast,
4055	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
4056	GCPhys, GCPhysLast, pszDesc,
4057	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
4058	VERR_PGM_RAM_CONFLICT);
4059	fRamExists = true;
4060	break;
4061	}
4062
4063	/* next */
4064	pRamPrev = pRam;
4065	pRam = pRam->pNextR3;
4066	}
4067	if (fRamExists)
4068	{
4069	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4070	uint32_t cPagesLeft = cPages;
4071	while (cPagesLeft-- > 0)
4072	{
4073	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
4074	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
4075	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
4076	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
4077	Assert(PGM_PAGE_IS_ZERO(pPage) \|\| PGM_IS_IN_NEM_MODE(pVM));
4078	pPage++;
4079	}
4080	}
4081
4082	/*
4083	* Update the base memory reservation if necessary.
4084	*/
4085	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
4086	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4087	cExtraBaseCost += cPages;
4088	if (cExtraBaseCost)
4089	{
4090	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
4091	if (RT_FAILURE(rc))
4092	return rc;
4093	}
4094
4095	#ifdef VBOX_WITH_NATIVE_NEM
4096	/*
4097	* Early NEM notification before we've made any changes or anything.
4098	*/
4099	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_ROM_F_REPLACE : 0)
4100	\| (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED ? NEM_NOTIFY_PHYS_ROM_F_SHADOW : 0);
4101	uint8_t u2NemState = UINT8_MAX;
4102	if (VM_IS_NEM_ENABLED(pVM))
4103	{
4104	int rc = NEMR3NotifyPhysRomRegisterEarly(pVM, GCPhys, cPages << PAGE_SHIFT,
4105	fRamExists ? PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhys) : NULL,
4106	fNemNotify, &u2NemState);
4107	AssertLogRelRCReturn(rc, rc);
4108	}
4109	#endif
4110
4111	/*
4112	* Allocate memory for the virgin copy of the RAM. In simplified memory mode,
4113	* we allocate memory for any ad-hoc RAM range and for shadow pages.
4114	*/
4115	PGMMALLOCATEPAGESREQ pReq = NULL;
4116	#ifdef VBOX_WITH_PGM_NEM_MODE
4117	void *pvRam = NULL;
4118	void *pvAlt = NULL;
4119	if (pVM->pgm.s.fNemMode)
4120	{
4121	if (!fRamExists)
4122	{
4123	int rc = SUPR3PageAlloc(cPages, &pvRam);
4124	if (RT_FAILURE(rc))
4125	return rc;
4126	}
4127	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4128	{
4129	int rc = SUPR3PageAlloc(cPages, &pvAlt);
4130	if (RT_FAILURE(rc))
4131	{
4132	if (pvRam)
4133	SUPR3PageFree(pvRam, cPages);
4134	return rc;
4135	}
4136	}
4137	}
4138	else
4139	#endif
4140	{
4141	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
4142	AssertRCReturn(rc, rc);
4143
4144	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4145	{
4146	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
4147	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
4148	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
4149	}
4150
4151	rc = GMMR3AllocatePagesPerform(pVM, pReq);
4152	if (RT_FAILURE(rc))
4153	{
4154	GMMR3AllocatePagesCleanup(pReq);
4155	return rc;
4156	}
4157	}
4158
4159	/*
4160	* Allocate the new ROM range and RAM range (if necessary).
4161	*/
4162	PPGMROMRANGE pRomNew;
4163	int rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
4164	if (RT_SUCCESS(rc))
4165	{
4166	PPGMRAMRANGE pRamNew = NULL;
4167	if (!fRamExists)
4168	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
4169	if (RT_SUCCESS(rc))
4170	{
4171	/*
4172	* Initialize and insert the RAM range (if required).
4173	*/
4174	uint32_t const idxFirstRamPage = fRamExists ? (GCPhys - pRam->GCPhys) >> PAGE_SHIFT : 0;
4175	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
4176	if (!fRamExists)
4177	{
4178	/* New RAM range. */
4179	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
4180	pRamNew->GCPhys = GCPhys;
4181	pRamNew->GCPhysLast = GCPhysLast;
4182	pRamNew->cb = cb;
4183	pRamNew->pszDesc = pszDesc;
4184	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
4185	pRamNew->pvR3 = NULL;
4186	pRamNew->paLSPages = NULL;
4187
4188	PPGMPAGE pRamPage = &pRamNew->aPages[idxFirstRamPage];
4189	#ifdef VBOX_WITH_PGM_NEM_MODE
4190	if (pVM->pgm.s.fNemMode)
4191	{
4192	AssertPtr(pvRam); Assert(pReq == NULL);
4193	pRamNew->pvR3 = pvRam;
4194	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4195	{
4196	PGM_PAGE_INIT(pRamPage, UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
4197	PGMPAGETYPE_ROM, PGM_PAGE_STATE_ALLOCATED);
4198	pRomPage->Virgin = *pRamPage;
4199	}
4200	}
4201	else
4202	#endif
4203	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4204	{
4205	PGM_PAGE_INIT(pRamPage,
4206	pReq->aPages[iPage].HCPhysGCPhys,
4207	pReq->aPages[iPage].idPage,
4208	PGMPAGETYPE_ROM,
4209	PGM_PAGE_STATE_ALLOCATED);
4210
4211	pRomPage->Virgin = *pRamPage;
4212	}
4213
4214	pVM->pgm.s.cAllPages += cPages;
4215	pVM->pgm.s.cPrivatePages += cPages;
4216	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
4217	}
4218	else
4219	{
4220	/* Existing RAM range. */
4221	PPGMPAGE pRamPage = &pRam->aPages[idxFirstRamPage];
4222	#ifdef VBOX_WITH_PGM_NEM_MODE
4223	if (pVM->pgm.s.fNemMode)
4224	{
4225	Assert(pvRam == NULL); Assert(pReq == NULL);
4226	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4227	{
4228	Assert(PGM_PAGE_GET_HCPHYS(pRamPage) == UINT64_C(0x0000fffffffff000));
4229	Assert(PGM_PAGE_GET_PAGEID(pRamPage) == NIL_GMM_PAGEID);
4230	Assert(PGM_PAGE_GET_STATE(pRamPage) == PGM_PAGE_STATE_ALLOCATED);
4231	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_ROM);
4232	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4233	PGM_PAGE_SET_PDE_TYPE(pVM, pRamPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4234	PGM_PAGE_SET_PTE_INDEX(pVM, pRamPage, 0);
4235	PGM_PAGE_SET_TRACKING(pVM, pRamPage, 0);
4236
4237	pRomPage->Virgin = *pRamPage;
4238	}
4239	}
4240	else
4241	#endif
4242	{
4243	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4244	{
4245	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_ROM);
4246	PGM_PAGE_SET_HCPHYS(pVM, pRamPage, pReq->aPages[iPage].HCPhysGCPhys);
4247	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4248	PGM_PAGE_SET_PAGEID(pVM, pRamPage, pReq->aPages[iPage].idPage);
4249	PGM_PAGE_SET_PDE_TYPE(pVM, pRamPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4250	PGM_PAGE_SET_PTE_INDEX(pVM, pRamPage, 0);
4251	PGM_PAGE_SET_TRACKING(pVM, pRamPage, 0);
4252
4253	pRomPage->Virgin = *pRamPage;
4254	}
4255	pVM->pgm.s.cZeroPages -= cPages;
4256	pVM->pgm.s.cPrivatePages += cPages;
4257	}
4258	pRamNew = pRam;
4259	}
4260
4261	#ifdef VBOX_WITH_NATIVE_NEM
4262	/* Set the NEM state of the pages if needed. */
4263	if (u2NemState != UINT8_MAX)
4264	pgmPhysSetNemStateForPages(&pRamNew->aPages[idxFirstRamPage], cPages, u2NemState);
4265	#endif
4266
4267	/* Flush physical page map TLB. */
4268	pgmPhysInvalidatePageMapTLB(pVM);
4269
4270	/*
4271	* Register the ROM access handler.
4272	*/
4273	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4274	pRomNew, MMHyperCCToR0(pVM, pRomNew), MMHyperCCToRC(pVM, pRomNew), pszDesc);
4275	if (RT_SUCCESS(rc))
4276	{
4277	/*
4278	* Copy the image over to the virgin pages.
4279	* This must be done after linking in the RAM range.
4280	*/
4281	size_t cbBinaryLeft = cbBinary;
4282	PPGMPAGE pRamPage = &pRamNew->aPages[idxFirstRamPage];
4283	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4284	{
4285	void *pvDstPage;
4286	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
4287	if (RT_FAILURE(rc))
4288	{
4289	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
4290	break;
4291	}
4292	if (cbBinaryLeft >= PAGE_SIZE)
4293	{
4294	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
4295	cbBinaryLeft -= PAGE_SIZE;
4296	}
4297	else
4298	{
4299	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
4300	if (cbBinaryLeft > 0)
4301	{
4302	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
4303	cbBinaryLeft = 0;
4304	}
4305	}
4306	}
4307	if (RT_SUCCESS(rc))
4308	{
4309	/*
4310	* Initialize the ROM range.
4311	* Note that the Virgin member of the pages has already been initialized above.
4312	*/
4313	pRomNew->GCPhys = GCPhys;
4314	pRomNew->GCPhysLast = GCPhysLast;
4315	pRomNew->cb = cb;
4316	pRomNew->fFlags = fFlags;
4317	pRomNew->idSavedState = UINT8_MAX;
4318	pRomNew->cbOriginal = cbBinary;
4319	pRomNew->pszDesc = pszDesc;
4320	#ifdef VBOX_WITH_PGM_NEM_MODE
4321	pRomNew->pbR3Alternate = (uint8_t *)pvAlt;
4322	#endif
4323	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
4324	? pvBinary : RTMemDup(pvBinary, cbBinary);
4325	if (pRomNew->pvOriginal)
4326	{
4327	for (unsigned iPage = 0; iPage < cPages; iPage++)
4328	{
4329	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
4330	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
4331	#ifdef VBOX_WITH_PGM_NEM_MODE
4332	if (pVM->pgm.s.fNemMode)
4333	PGM_PAGE_INIT(&pPage->Shadow, UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
4334	PGMPAGETYPE_ROM_SHADOW, PGM_PAGE_STATE_ALLOCATED);
4335	else
4336	#endif
4337	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
4338	}
4339
4340	/* update the page count stats for the shadow pages. */
4341	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4342	{
4343	#ifdef VBOX_WITH_PGM_NEM_MODE
4344	if (pVM->pgm.s.fNemMode)
4345	pVM->pgm.s.cPrivatePages += cPages;
4346	else
4347	#endif
4348	pVM->pgm.s.cZeroPages += cPages;
4349	pVM->pgm.s.cAllPages += cPages;
4350	}
4351
4352	/*
4353	* Insert the ROM range, tell REM and return successfully.
4354	*/
4355	pRomNew->pNextR3 = pRom;
4356	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4357
4358	if (pRomPrev)
4359	{
4360	pRomPrev->pNextR3 = pRomNew;
4361	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
4362	}
4363	else
4364	{
4365	pVM->pgm.s.pRomRangesR3 = pRomNew;
4366	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
4367	}
4368
4369	pgmPhysInvalidatePageMapTLB(pVM);
4370	#ifdef VBOX_WITH_PGM_NEM_MODE
4371	if (!pVM->pgm.s.fNemMode)
4372	#endif
4373	GMMR3AllocatePagesCleanup(pReq);
4374
4375	#ifdef VBOX_WITH_NATIVE_NEM
4376	/*
4377	* Notify NEM again.
4378	*/
4379	u2NemState = UINT8_MAX;
4380	rc = NEMR3NotifyPhysRomRegisterLate(pVM, GCPhys, cb, PGM_RAMRANGE_CALC_PAGE_R3PTR(pRamNew, GCPhys),
4381	fNemNotify, &u2NemState);
4382	if (u2NemState != UINT8_MAX)
4383	pgmPhysSetNemStateForPages(&pRamNew->aPages[idxFirstRamPage], cPages, u2NemState);
4384	if (RT_SUCCESS(rc))
4385	#endif
4386	return rc;
4387
4388	/*
4389	* bail out
4390	*/
4391	#ifdef VBOX_WITH_NATIVE_NEM
4392	/* unlink */
4393	if (pRomPrev)
4394	{
4395	pRomPrev->pNextR3 = pRom;
4396	pRomPrev->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4397	}
4398	else
4399	{
4400	pVM->pgm.s.pRomRangesR3 = pRom;
4401	pVM->pgm.s.pRomRangesR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4402	}
4403
4404	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4405	{
4406	# ifdef VBOX_WITH_PGM_NEM_MODE
4407	if (pVM->pgm.s.fNemMode)
4408	pVM->pgm.s.cPrivatePages -= cPages;
4409	else
4410	# endif
4411	pVM->pgm.s.cZeroPages -= cPages;
4412	pVM->pgm.s.cAllPages -= cPages;
4413	}
4414	#endif
4415	}
4416	else
4417	rc = VERR_NO_MEMORY;
4418	}
4419
4420	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
4421	AssertRC(rc2);
4422	}
4423
4424	if (!fRamExists)
4425	{
4426	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
4427	MMHyperFree(pVM, pRamNew);
4428	}
4429	else
4430	{
4431	PPGMPAGE pRamPage = &pRam->aPages[idxFirstRamPage];
4432	#ifdef VBOX_WITH_PGM_NEM_MODE
4433	if (pVM->pgm.s.fNemMode)
4434	{
4435	Assert(pvRam == NULL); Assert(pReq == NULL);
4436	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4437	{
4438	Assert(PGM_PAGE_GET_HCPHYS(pRamPage) == UINT64_C(0x0000fffffffff000));
4439	Assert(PGM_PAGE_GET_PAGEID(pRamPage) == NIL_GMM_PAGEID);
4440	Assert(PGM_PAGE_GET_STATE(pRamPage) == PGM_PAGE_STATE_ALLOCATED);
4441	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_RAM);
4442	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4443	}
4444	}
4445	else
4446	#endif
4447	{
4448	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4449	PGM_PAGE_INIT_ZERO(pRamPage, pVM, PGMPAGETYPE_RAM);
4450	pVM->pgm.s.cZeroPages += cPages;
4451	pVM->pgm.s.cPrivatePages -= cPages;
4452	}
4453	}
4454	}
4455	MMHyperFree(pVM, pRomNew);
4456	}
4457
4458	/** @todo Purge the mapping cache or something... */
4459	#ifdef VBOX_WITH_PGM_NEM_MODE
4460	if (pVM->pgm.s.fNemMode)
4461	{
4462	Assert(!pReq);
4463	if (pvRam)
4464	SUPR3PageFree(pvRam, cPages);
4465	if (pvAlt)
4466	SUPR3PageFree(pvAlt, cPages);
4467	}
4468	else
4469	#endif
4470	{
4471	GMMR3FreeAllocatedPages(pVM, pReq);
4472	GMMR3AllocatePagesCleanup(pReq);
4473	}
4474	return rc;
4475	}
4476
4477
4478	/**
4479	* Registers a ROM image.
4480	*
4481	* Shadowed ROM images requires double the amount of backing memory, so,
4482	* don't use that unless you have to. Shadowing of ROM images is process
4483	* where we can select where the reads go and where the writes go. On real
4484	* hardware the chipset provides means to configure this. We provide
4485	* PGMR3PhysProtectROM() for this purpose.
4486	*
4487	* A read-only copy of the ROM image will always be kept around while we
4488	* will allocate RAM pages for the changes on demand (unless all memory
4489	* is configured to be preallocated).
4490	*
4491	* @returns VBox status code.
4492	* @param pVM The cross context VM structure.
4493	* @param pDevIns The device instance owning the ROM.
4494	* @param GCPhys First physical address in the range.
4495	* Must be page aligned!
4496	* @param cb The size of the range (in bytes).
4497	* Must be page aligned!
4498	* @param pvBinary Pointer to the binary data backing the ROM image.
4499	* @param cbBinary The size of the binary data pvBinary points to.
4500	* This must be less or equal to @a cb.
4501	* @param fFlags Mask of flags, PGMPHYS_ROM_FLAGS_XXX.
4502	* @param pszDesc Pointer to description string. This must not be freed.
4503	*
4504	* @remark There is no way to remove the rom, automatically on device cleanup or
4505	* manually from the device yet. This isn't difficult in any way, it's
4506	* just not something we expect to be necessary for a while.
4507	*/
4508	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4509	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc)
4510	{
4511	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
4512	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
4513	PGM_LOCK_VOID(pVM);
4514	int rc = pgmR3PhysRomRegisterLocked(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
4515	PGM_UNLOCK(pVM);
4516	return rc;
4517	}
4518
4519
4520	/**
4521	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
4522	* that the virgin part is untouched.
4523	*
4524	* This is done after the normal memory has been cleared.
4525	*
4526	* ASSUMES that the caller owns the PGM lock.
4527	*
4528	* @param pVM The cross context VM structure.
4529	*/
4530	int pgmR3PhysRomReset(PVM pVM)
4531	{
4532	PGM_LOCK_ASSERT_OWNER(pVM);
4533	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4534	{
4535	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
4536
4537	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4538	{
4539	/*
4540	* Reset the physical handler.
4541	*/
4542	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
4543	AssertRCReturn(rc, rc);
4544
4545	/*
4546	* What we do with the shadow pages depends on the memory
4547	* preallocation option. If not enabled, we'll just throw
4548	* out all the dirty pages and replace them by the zero page.
4549	*/
4550	#ifdef VBOX_WITH_PGM_NEM_MODE
4551	if (pVM->pgm.s.fNemMode)
4552	{
4553	/* Clear all the shadow pages (currently using alternate backing). */
4554	RT_BZERO(pRom->pbR3Alternate, pRom->cb);
4555	}
4556	else
4557	#endif
4558	if (!pVM->pgm.s.fRamPreAlloc)
4559	{
4560	/* Free the dirty pages. */
4561	uint32_t cPendingPages = 0;
4562	PGMMFREEPAGESREQ pReq;
4563	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4564	AssertRCReturn(rc, rc);
4565
4566	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4567	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
4568	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
4569	{
4570	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
4571	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
4572	pRom->GCPhys + (iPage << PAGE_SHIFT),
4573	(PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pRom->aPages[iPage].Shadow));
4574	AssertLogRelRCReturn(rc, rc);
4575	}
4576
4577	if (cPendingPages)
4578	{
4579	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
4580	AssertLogRelRCReturn(rc, rc);
4581	}
4582	GMMR3FreePagesCleanup(pReq);
4583	}
4584	else
4585	{
4586	/* clear all the shadow pages. */
4587	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4588	{
4589	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
4590	continue;
4591	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
4592	void *pvDstPage;
4593	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4594	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
4595	if (RT_FAILURE(rc))
4596	break;
4597	ASMMemZeroPage(pvDstPage);
4598	}
4599	AssertRCReturn(rc, rc);
4600	}
4601	}
4602
4603	/*
4604	* Restore the original ROM pages after a saved state load.
4605	* Also, in strict builds check that ROM pages remain unmodified.
4606	*/
4607	#ifndef VBOX_STRICT
4608	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4609	#endif
4610	{
4611	size_t cbSrcLeft = pRom->cbOriginal;
4612	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
4613	uint32_t cRestored = 0;
4614	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
4615	{
4616	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4617	void const *pvDstPage;
4618	int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
4619	if (RT_FAILURE(rc))
4620	break;
4621
4622	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
4623	{
4624	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4625	{
4626	void *pvDstPageW;
4627	rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPageW);
4628	AssertLogRelRCReturn(rc, rc);
4629	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
4630	cRestored++;
4631	}
4632	else
4633	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
4634	}
4635	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
4636	}
4637	if (cRestored > 0)
4638	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
4639	}
4640	}
4641
4642	/* Clear the ROM restore flag now as we only need to do this once after
4643	loading saved state. */
4644	pVM->pgm.s.fRestoreRomPagesOnReset = false;
4645
4646	return VINF_SUCCESS;
4647	}
4648
4649
4650	/**
4651	* Called by PGMR3Term to free resources.
4652	*
4653	* ASSUMES that the caller owns the PGM lock.
4654	*
4655	* @param pVM The cross context VM structure.
4656	*/
4657	void pgmR3PhysRomTerm(PVM pVM)
4658	{
4659	/*
4660	* Free the heap copy of the original bits.
4661	*/
4662	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4663	{
4664	if ( pRom->pvOriginal
4665	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
4666	{
4667	RTMemFree((void *)pRom->pvOriginal);
4668	pRom->pvOriginal = NULL;
4669	}
4670	}
4671	}
4672
4673
4674	/**
4675	* Change the shadowing of a range of ROM pages.
4676	*
4677	* This is intended for implementing chipset specific memory registers
4678	* and will not be very strict about the input. It will silently ignore
4679	* any pages that are not the part of a shadowed ROM.
4680	*
4681	* @returns VBox status code.
4682	* @retval VINF_PGM_SYNC_CR3
4683	*
4684	* @param pVM The cross context VM structure.
4685	* @param GCPhys Where to start. Page aligned.
4686	* @param cb How much to change. Page aligned.
4687	* @param enmProt The new ROM protection.
4688	*/
4689	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
4690	{
4691	/*
4692	* Check input
4693	*/
4694	if (!cb)
4695	return VINF_SUCCESS;
4696	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4697	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4698	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4699	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4700	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
4701
4702	/*
4703	* Process the request.
4704	*/
4705	PGM_LOCK_VOID(pVM);
4706	int rc = VINF_SUCCESS;
4707	bool fFlushTLB = false;
4708	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4709	{
4710	if ( GCPhys <= pRom->GCPhysLast
4711	&& GCPhysLast >= pRom->GCPhys
4712	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
4713	{
4714	/*
4715	* Iterate the relevant pages and make necessary the changes.
4716	*/
4717	#ifdef VBOX_WITH_NATIVE_NEM
4718	PPGMRAMRANGE const pRam = pgmPhysGetRange(pVM, GCPhys);
4719	AssertPtrReturn(pRam, VERR_INTERNAL_ERROR_3);
4720	#endif
4721	bool fChanges = false;
4722	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
4723	? pRom->cb >> PAGE_SHIFT
4724	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
4725	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
4726	iPage < cPages;
4727	iPage++)
4728	{
4729	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
4730	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
4731	{
4732	fChanges = true;
4733
4734	/* flush references to the page. */
4735	RTGCPHYS const GCPhysPage = pRom->GCPhys + (iPage << PAGE_SHIFT);
4736	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, GCPhysPage);
4737	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pRamPage, true /fFlushPTEs/, &fFlushTLB);
4738	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
4739	rc = rc2;
4740	#ifdef VBOX_WITH_NATIVE_NEM
4741	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pRamPage);
4742	#endif
4743
4744	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
4745	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
4746
4747	pOld = pRamPage;
4748	pRamPage = pNew;
4749	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
4750
4751	#ifdef VBOX_WITH_NATIVE_NEM
4752	# ifdef VBOX_WITH_PGM_NEM_MODE
4753	/* In simplified mode we have to switch the page data around too. */
4754	if (pVM->pgm.s.fNemMode)
4755	{
4756	uint8_t abPage[PAGE_SIZE];
4757	uint8_t * const pbRamPage = PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhysPage);
4758	memcpy(abPage, &pRom->pbR3Alternate[(size_t)iPage << PAGE_SHIFT], sizeof(abPage));
4759	memcpy(&pRom->pbR3Alternate[(size_t)iPage << PAGE_SHIFT], pbRamPage, sizeof(abPage));
4760	memcpy(pbRamPage, abPage, sizeof(abPage));
4761	}
4762	# endif
4763	/* Tell NEM about the backing and protection change. */
4764	if (VM_IS_NEM_ENABLED(pVM))
4765	{
4766	PGMPAGETYPE enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pNew);
4767	NEMHCNotifyPhysPageChanged(pVM, GCPhys, PGM_PAGE_GET_HCPHYS(pOld), PGM_PAGE_GET_HCPHYS(pNew),
4768	PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhysPage),
4769	pgmPhysPageCalcNemProtection(pRamPage, enmType), enmType, &u2State);
4770	PGM_PAGE_SET_NEM_STATE(pRamPage, u2State);
4771	}
4772	#endif
4773	}
4774	pRomPage->enmProt = enmProt;
4775	}
4776
4777	/*
4778	* Reset the access handler if we made changes, no need
4779	* to optimize this.
4780	*/
4781	if (fChanges)
4782	{
4783	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
4784	if (RT_FAILURE(rc2))
4785	{
4786	PGM_UNLOCK(pVM);
4787	AssertRC(rc);
4788	return rc2;
4789	}
4790	}
4791
4792	/* Advance - cb isn't updated. */
4793	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
4794	}
4795	}
4796	PGM_UNLOCK(pVM);
4797	if (fFlushTLB)
4798	PGM_INVL_ALL_VCPU_TLBS(pVM);
4799
4800	return rc;
4801	}
4802
4803
4804	/**
4805	* Sets the Address Gate 20 state.
4806	*
4807	* @param pVCpu The cross context virtual CPU structure.
4808	* @param fEnable True if the gate should be enabled.
4809	* False if the gate should be disabled.
4810	*/
4811	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
4812	{
4813	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
4814	if (pVCpu->pgm.s.fA20Enabled != fEnable)
4815	{
4816	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4817	PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
4818	if ( CPUMIsGuestInVmxRootMode(pCtx)
4819	&& !fEnable)
4820	{
4821	Log(("Cannot enter A20M mode while in VMX root mode\n"));
4822	return;
4823	}
4824	#endif
4825	pVCpu->pgm.s.fA20Enabled = fEnable;
4826	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
4827	NEMR3NotifySetA20(pVCpu, fEnable);
4828	#ifdef PGM_WITH_A20
4829	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4830	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
4831	HMFlushTlb(pVCpu);
4832	#endif
4833	IEMTlbInvalidateAllPhysical(pVCpu);
4834	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
4835	}
4836	}
4837
4838
4839	/**
4840	* Tree enumeration callback for dealing with age rollover.
4841	* It will perform a simple compression of the current age.
4842	*/
4843	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
4844	{
4845	/* Age compression - ASSUMES iNow == 4. */
4846	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4847	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
4848	pChunk->iLastUsed = 3;
4849	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
4850	pChunk->iLastUsed = 2;
4851	else if (pChunk->iLastUsed)
4852	pChunk->iLastUsed = 1;
4853	else /* iLastUsed = 0 */
4854	pChunk->iLastUsed = 4;
4855
4856	NOREF(pvUser);
4857	return 0;
4858	}
4859
4860
4861	/**
4862	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
4863	*/
4864	typedef struct PGMR3PHYSCHUNKUNMAPCB
4865	{
4866	PVM pVM; /*< Pointer to the VM. /
4867	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
4868	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
4869
4870
4871	/**
4872	* Callback used to find the mapping that's been unused for
4873	* the longest time.
4874	*/
4875	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
4876	{
4877	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
4878	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
4879
4880	/*
4881	* Check for locks and compare when last used.
4882	*/
4883	if (pChunk->cRefs)
4884	return 0;
4885	if (pChunk->cPermRefs)
4886	return 0;
4887	if ( pArg->pChunk
4888	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
4889	return 0;
4890
4891	/*
4892	* Check that it's not in any of the TLBs.
4893	*/
4894	PVM pVM = pArg->pVM;
4895	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
4896	== pChunk->Core.Key)
4897	{
4898	pChunk = NULL;
4899	return 0;
4900	}
4901	#ifdef VBOX_STRICT
4902	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
4903	{
4904	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
4905	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
4906	}
4907	#endif
4908
4909	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbR3.aEntries); i++)
4910	if (pVM->pgm.s.PhysTlbR3.aEntries[i].pMap == pChunk)
4911	return 0;
4912
4913	pArg->pChunk = pChunk;
4914	return 0;
4915	}
4916
4917
4918	/**
4919	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
4920	*
4921	* The candidate will not be part of any TLBs, so no need to flush
4922	* anything afterwards.
4923	*
4924	* @returns Chunk id.
4925	* @param pVM The cross context VM structure.
4926	*/
4927	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
4928	{
4929	PGM_LOCK_ASSERT_OWNER(pVM);
4930
4931	/*
4932	* Enumerate the age tree starting with the left most node.
4933	*/
4934	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
4935	PGMR3PHYSCHUNKUNMAPCB Args;
4936	Args.pVM = pVM;
4937	Args.pChunk = NULL;
4938	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
4939	Assert(Args.pChunk);
4940	if (Args.pChunk)
4941	{
4942	Assert(Args.pChunk->cRefs == 0);
4943	Assert(Args.pChunk->cPermRefs == 0);
4944	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
4945	return Args.pChunk->Core.Key;
4946	}
4947
4948	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
4949	return INT32_MAX;
4950	}
4951
4952
4953	/**
4954	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
4955	*
4956	* This is only called on one of the EMTs while the other ones are waiting for
4957	* it to complete this function.
4958	*
4959	* @returns VINF_SUCCESS (VBox strict status code).
4960	* @param pVM The cross context VM structure.
4961	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
4962	* @param pvUser User pointer. Unused
4963	*
4964	*/
4965	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
4966	{
4967	int rc = VINF_SUCCESS;
4968	PGM_LOCK_VOID(pVM);
4969	NOREF(pVCpu); NOREF(pvUser);
4970
4971	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
4972	{
4973	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
4974	/** @todo also not really efficient to unmap a chunk that contains PD
4975	* or PT pages. */
4976	pgmR3PoolClearAllRendezvous(pVM, pVM->apCpusR3[0], NULL /* no need to flush the REM TLB as we already did that above */);
4977
4978	/*
4979	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
4980	*/
4981	GMMMAPUNMAPCHUNKREQ Req;
4982	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
4983	Req.Hdr.cbReq = sizeof(Req);
4984	Req.pvR3 = NULL;
4985	Req.idChunkMap = NIL_GMM_CHUNKID;
4986	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
4987	if (Req.idChunkUnmap != INT32_MAX)
4988	{
4989	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkUnmap, a);
4990	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
4991	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkUnmap, a);
4992	if (RT_SUCCESS(rc))
4993	{
4994	/*
4995	* Remove the unmapped one.
4996	*/
4997	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
4998	AssertRelease(pUnmappedChunk);
4999	AssertRelease(!pUnmappedChunk->cRefs);
5000	AssertRelease(!pUnmappedChunk->cPermRefs);
5001	pUnmappedChunk->pv = NULL;
5002	pUnmappedChunk->Core.Key = UINT32_MAX;
5003	MMR3HeapFree(pUnmappedChunk);
5004	pVM->pgm.s.ChunkR3Map.c--;
5005	pVM->pgm.s.cUnmappedChunks++;
5006
5007	/*
5008	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
5009	*/
5010	/** @todo We should not flush chunks which include cr3 mappings. */
5011	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5012	{
5013	PPGMCPU pPGM = &pVM->apCpusR3[idCpu]->pgm.s;
5014
5015	pPGM->pGst32BitPdR3 = NULL;
5016	pPGM->pGstPaePdptR3 = NULL;
5017	pPGM->pGstAmd64Pml4R3 = NULL;
5018	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
5019	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
5020	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
5021	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
5022	{
5023	pPGM->apGstPaePDsR3[i] = NULL;
5024	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
5025	}
5026
5027	/* Flush REM TLBs. */
5028	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5029	}
5030	}
5031	}
5032	}
5033	PGM_UNLOCK(pVM);
5034	return rc;
5035	}
5036
5037	/**
5038	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
5039	*
5040	* @returns VBox status code.
5041	* @param pVM The cross context VM structure.
5042	*/
5043	static DECLCALLBACK(void) pgmR3PhysUnmapChunk(PVM pVM)
5044	{
5045	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
5046	AssertRC(rc);
5047	}
5048
5049
5050	/**
5051	* Maps the given chunk into the ring-3 mapping cache.
5052	*
5053	* This will call ring-0.
5054	*
5055	* @returns VBox status code.
5056	* @param pVM The cross context VM structure.
5057	* @param idChunk The chunk in question.
5058	* @param ppChunk Where to store the chunk tracking structure.
5059	*
5060	* @remarks Called from within the PGM critical section.
5061	* @remarks Can be called from any thread!
5062	*/
5063	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
5064	{
5065	int rc;
5066
5067	PGM_LOCK_ASSERT_OWNER(pVM);
5068
5069	/*
5070	* Move the chunk time forward.
5071	*/
5072	pVM->pgm.s.ChunkR3Map.iNow++;
5073	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
5074	{
5075	pVM->pgm.s.ChunkR3Map.iNow = 4;
5076	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
5077	}
5078
5079	/*
5080	* Allocate a new tracking structure first.
5081	*/
5082	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
5083	AssertReturn(pChunk, VERR_NO_MEMORY);
5084	pChunk->Core.Key = idChunk;
5085	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
5086
5087	/*
5088	* Request the ring-0 part to map the chunk in question.
5089	*/
5090	GMMMAPUNMAPCHUNKREQ Req;
5091	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5092	Req.Hdr.cbReq = sizeof(Req);
5093	Req.pvR3 = NULL;
5094	Req.idChunkMap = idChunk;
5095	Req.idChunkUnmap = NIL_GMM_CHUNKID;
5096
5097	/* Must be callable from any thread, so can't use VMMR3CallR0. */
5098	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkMap, a);
5099	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5100	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkMap, a);
5101	if (RT_SUCCESS(rc))
5102	{
5103	pChunk->pv = Req.pvR3;
5104
5105	/*
5106	* If we're running out of virtual address space, then we should
5107	* unmap another chunk.
5108	*
5109	* Currently, an unmap operation requires that all other virtual CPUs
5110	* are idling and not by chance making use of the memory we're
5111	* unmapping. So, we create an async unmap operation here.
5112	*
5113	* Now, when creating or restoring a saved state this wont work very
5114	* well since we may want to restore all guest RAM + a little something.
5115	* So, we have to do the unmap synchronously. Fortunately for us
5116	* though, during these operations the other virtual CPUs are inactive
5117	* and it should be safe to do this.
5118	*/
5119	/** @todo Eventually we should lock all memory when used and do
5120	* map+unmap as one kernel call without any rendezvous or
5121	* other precautions. */
5122	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
5123	{
5124	switch (VMR3GetState(pVM))
5125	{
5126	case VMSTATE_LOADING:
5127	case VMSTATE_SAVING:
5128	{
5129	PVMCPU pVCpu = VMMGetCpu(pVM);
5130	if ( pVCpu
5131	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
5132	{
5133	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
5134	break;
5135	}
5136	}
5137	RT_FALL_THRU();
5138	default:
5139	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
5140	AssertRC(rc);
5141	break;
5142	}
5143	}
5144
5145	/*
5146	* Update the tree. We must do this after any unmapping to make sure
5147	* the chunk we're going to return isn't unmapped by accident.
5148	*/
5149	AssertPtr(Req.pvR3);
5150	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
5151	AssertRelease(fRc);
5152	pVM->pgm.s.ChunkR3Map.c++;
5153	pVM->pgm.s.cMappedChunks++;
5154	}
5155	else
5156	{
5157	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
5158	* should probably restrict ourselves on linux. */
5159	AssertRC(rc);
5160	MMR3HeapFree(pChunk);
5161	pChunk = NULL;
5162	}
5163
5164	*ppChunk = pChunk;
5165	return rc;
5166	}
5167
5168
5169	/**
5170	* Invalidates the TLB for the ring-3 mapping cache.
5171	*
5172	* @param pVM The cross context VM structure.
5173	*/
5174	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
5175	{
5176	PGM_LOCK_VOID(pVM);
5177	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5178	{
5179	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
5180	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
5181	}
5182	/* The page map TLB references chunks, so invalidate that one too. */
5183	pgmPhysInvalidatePageMapTLB(pVM);
5184	PGM_UNLOCK(pVM);
5185	}
5186
5187
5188	/**
5189	* Response to VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE to allocate a large
5190	* (2MB) page for use with a nested paging PDE.
5191	*
5192	* @returns The following VBox status codes.
5193	* @retval VINF_SUCCESS on success.
5194	* @retval VINF_EM_NO_MEMORY if we're out of memory.
5195	*
5196	* @param pVM The cross context VM structure.
5197	* @param GCPhys GC physical start address of the 2 MB range
5198	*/
5199	VMMR3_INT_DECL(int) PGMR3PhysAllocateLargePage(PVM pVM, RTGCPHYS GCPhys)
5200	{
5201	#ifdef PGM_WITH_LARGE_PAGES
5202	PGM_LOCK_VOID(pVM);
5203
5204	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatAllocLargePage, a);
5205	uint64_t const msAllocStart = RTTimeMilliTS();
5206	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_LARGE_HANDY_PAGE, 0, NULL);
5207	uint64_t const cMsElapsed = RTTimeMilliTS() - msAllocStart;
5208	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatAllocLargePage, a);
5209	if (RT_SUCCESS(rc))
5210	{
5211	Assert(pVM->pgm.s.cLargeHandyPages == 1);
5212
5213	uint32_t idPage = pVM->pgm.s.aLargeHandyPage[0].idPage;
5214	RTHCPHYS HCPhys = pVM->pgm.s.aLargeHandyPage[0].HCPhysGCPhys;
5215
5216	void *pv;
5217
5218	/* Map the large page into our address space.
5219	*
5220	* Note: assuming that within the 2 MB range:
5221	* - GCPhys + PAGE_SIZE = HCPhys + PAGE_SIZE (whole point of this exercise)
5222	* - user space mapping is continuous as well
5223	* - page id (GCPhys) + 1 = page id (GCPhys + PAGE_SIZE)
5224	*/
5225	rc = pgmPhysPageMapByPageID(pVM, idPage, HCPhys, &pv);
5226	AssertLogRelMsg(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n", idPage, HCPhys, rc));
5227
5228	if (RT_SUCCESS(rc))
5229	{
5230	/*
5231	* Clear the pages.
5232	*/
5233	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatClearLargePage, b);
5234	for (unsigned i = 0; i < _2M/PAGE_SIZE; i++)
5235	{
5236	ASMMemZeroPage(pv);
5237
5238	PPGMPAGE pPage;
5239	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
5240	AssertRC(rc);
5241
5242	Assert(PGM_PAGE_IS_ZERO(pPage));
5243	STAM_COUNTER_INC(&pVM->pgm.s.Stats.StatRZPageReplaceZero);
5244	pVM->pgm.s.cZeroPages--;
5245
5246	/*
5247	* Do the PGMPAGE modifications.
5248	*/
5249	pVM->pgm.s.cPrivatePages++;
5250	PGM_PAGE_SET_HCPHYS(pVM, pPage, HCPhys);
5251	PGM_PAGE_SET_PAGEID(pVM, pPage, idPage);
5252	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
5253	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE);
5254	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5255	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5256
5257	/* Somewhat dirty assumption that page ids are increasing. */
5258	idPage++;
5259
5260	HCPhys += PAGE_SIZE;
5261	GCPhys += PAGE_SIZE;
5262
5263	pv = (void *)((uintptr_t)pv + PAGE_SIZE);
5264
5265	Log3(("PGMR3PhysAllocateLargePage: idPage=%#x HCPhys=%RGp\n", idPage, HCPhys));
5266	}
5267	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatClearLargePage, b);
5268
5269	/* Flush all TLBs. */
5270	PGM_INVL_ALL_VCPU_TLBS(pVM);
5271	pgmPhysInvalidatePageMapTLB(pVM);
5272	}
5273	pVM->pgm.s.cLargeHandyPages = 0;
5274	}
5275
5276	if (RT_SUCCESS(rc))
5277	{
5278	static uint32_t cTimeOut = 0;
5279	if (cMsElapsed > 100)
5280	{
5281	STAM_COUNTER_INC(&pVM->pgm.s.Stats.StatLargePageOverflow);
5282	if ( ++cTimeOut > 10
5283	\|\| cMsElapsed > 1000 /* more than one second forces an early retirement from allocating large pages. */)
5284	{
5285	/* If repeated attempts to allocate a large page takes more than 100 ms, then we fall back to normal 4k pages.
5286	* E.g. Vista 64 tries to move memory around, which takes a huge amount of time.
5287	*/
5288	LogRel(("PGMR3PhysAllocateLargePage: allocating large pages takes too long (last attempt %RU64 ms; nr of timeouts %d); DISABLE\n", cMsElapsed, cTimeOut));
5289	PGMSetLargePageUsage(pVM, false);
5290	}
5291	}
5292	else if (cTimeOut > 0)
5293	cTimeOut--;
5294	}
5295
5296	PGM_UNLOCK(pVM);
5297	return rc;
5298	#else
5299	RT_NOREF(pVM, GCPhys);
5300	return VERR_NOT_IMPLEMENTED;
5301	#endif /* PGM_WITH_LARGE_PAGES */
5302	}
5303
5304
5305	/**
5306	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
5307	*
5308	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
5309	* signal and clear the out of memory condition. When contracted, this API is
5310	* used to try clear the condition when the user wants to resume.
5311	*
5312	* @returns The following VBox status codes.
5313	* @retval VINF_SUCCESS on success. FFs cleared.
5314	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
5315	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
5316	*
5317	* @param pVM The cross context VM structure.
5318	*
5319	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
5320	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
5321	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
5322	* handler.
5323	*/
5324	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
5325	{
5326	PGM_LOCK_VOID(pVM);
5327
5328	/*
5329	* Allocate more pages, noting down the index of the first new page.
5330	*/
5331	uint32_t iClear = pVM->pgm.s.cHandyPages;
5332	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
5333	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
5334	int rcAlloc = VINF_SUCCESS;
5335	int rcSeed = VINF_SUCCESS;
5336	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5337	while (rc == VERR_GMM_SEED_ME)
5338	{
5339	void *pvChunk;
5340	rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
5341	if (RT_SUCCESS(rc))
5342	{
5343	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
5344	if (RT_FAILURE(rc))
5345	SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
5346	}
5347	if (RT_SUCCESS(rc))
5348	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5349	}
5350
5351	/** @todo we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
5352	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
5353	&& pVM->pgm.s.cHandyPages > 0)
5354	{
5355	/* Still handy pages left, so don't panic. */
5356	rc = VINF_SUCCESS;
5357	}
5358
5359	if (RT_SUCCESS(rc))
5360	{
5361	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
5362	Assert(pVM->pgm.s.cHandyPages > 0);
5363	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5364	VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
5365
5366	#ifdef VBOX_STRICT
5367	uint32_t i;
5368	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
5369	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
5370	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
5371	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
5372	break;
5373	if (i != pVM->pgm.s.cHandyPages)
5374	{
5375	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
5376	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
5377	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
5378	RTAssertMsg2Add("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%\n", j,
5379	pVM->pgm.s.aHandyPages[j].idPage,
5380	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
5381	pVM->pgm.s.aHandyPages[j].idSharedPage,
5382	j == i ? " <---" : "");
5383	RTAssertPanic();
5384	}
5385	#endif
5386	/*
5387	* Clear the pages.
5388	*/
5389	while (iClear < pVM->pgm.s.cHandyPages)
5390	{
5391	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
5392	void *pv;
5393	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
5394	AssertLogRelMsgBreak(RT_SUCCESS(rc),
5395	("%u/%u: idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc\n",
5396	iClear, pVM->pgm.s.cHandyPages, pPage->idPage, pPage->HCPhysGCPhys, rc));
5397	ASMMemZeroPage(pv);
5398	iClear++;
5399	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
5400	}
5401	}
5402	else
5403	{
5404	uint64_t cAllocPages, cMaxPages, cBalloonPages;
5405
5406	/*
5407	* We should never get here unless there is a genuine shortage of
5408	* memory (or some internal error). Flag the error so the VM can be
5409	* suspended ASAP and the user informed. If we're totally out of
5410	* handy pages we will return failure.
5411	*/
5412	/* Report the failure. */
5413	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
5414	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
5415	rc, rcAlloc, rcSeed,
5416	pVM->pgm.s.cHandyPages,
5417	pVM->pgm.s.cAllPages,
5418	pVM->pgm.s.cPrivatePages,
5419	pVM->pgm.s.cSharedPages,
5420	pVM->pgm.s.cZeroPages));
5421
5422	if (GMMR3QueryMemoryStats(pVM, &cAllocPages, &cMaxPages, &cBalloonPages) == VINF_SUCCESS)
5423	{
5424	LogRel(("GMM: Statistics:\n"
5425	" Allocated pages: %RX64\n"
5426	" Maximum pages: %RX64\n"
5427	" Ballooned pages: %RX64\n", cAllocPages, cMaxPages, cBalloonPages));
5428	}
5429
5430	if ( rc != VERR_NO_MEMORY
5431	&& rc != VERR_NO_PHYS_MEMORY
5432	&& rc != VERR_LOCK_FAILED)
5433	{
5434	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5435	{
5436	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
5437	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
5438	pVM->pgm.s.aHandyPages[i].idSharedPage));
5439	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
5440	if (idPage != NIL_GMM_PAGEID)
5441	{
5442	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
5443	pRam;
5444	pRam = pRam->pNextR3)
5445	{
5446	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
5447	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5448	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
5449	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
5450	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
5451	}
5452	}
5453	}
5454	}
5455
5456	if (rc == VERR_NO_MEMORY)
5457	{
5458	uint64_t cbHostRamAvail = 0;
5459	int rc2 = RTSystemQueryAvailableRam(&cbHostRamAvail);
5460	if (RT_SUCCESS(rc2))
5461	LogRel(("Host RAM: %RU64MB available\n", cbHostRamAvail / _1M));
5462	else
5463	LogRel(("Cannot determine the amount of available host memory\n"));
5464	}
5465
5466	/* Set the FFs and adjust rc. */
5467	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5468	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
5469	if ( rc == VERR_NO_MEMORY
5470	\|\| rc == VERR_NO_PHYS_MEMORY
5471	\|\| rc == VERR_LOCK_FAILED)
5472	rc = VINF_EM_NO_MEMORY;
5473	}
5474
5475	PGM_UNLOCK(pVM);
5476	return rc;
5477	}
5478
5479
5480	/**
5481	* Frees the specified RAM page and replaces it with the ZERO page.
5482	*
5483	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
5484	*
5485	* @param pVM The cross context VM structure.
5486	* @param pReq Pointer to the request. This is NULL when doing a
5487	* bulk free in NEM memory mode.
5488	* @param pcPendingPages Where the number of pages waiting to be freed are
5489	* kept. This will normally be incremented. This is
5490	* NULL when doing a bulk free in NEM memory mode.
5491	* @param pPage Pointer to the page structure.
5492	* @param GCPhys The guest physical address of the page, if applicable.
5493	* @param enmNewType New page type for NEM notification, since several
5494	* callers will change the type upon successful return.
5495	*
5496	* @remarks The caller must own the PGM lock.
5497	*/
5498	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
5499	PGMPAGETYPE enmNewType)
5500	{
5501	/*
5502	* Assert sanity.
5503	*/
5504	PGM_LOCK_ASSERT_OWNER(pVM);
5505	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
5506	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
5507	{
5508	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5509	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
5510	}
5511
5512	/** @todo What about ballooning of large pages??! */
5513	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
5514	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
5515
5516	if ( PGM_PAGE_IS_ZERO(pPage)
5517	\|\| PGM_PAGE_IS_BALLOONED(pPage))
5518	return VINF_SUCCESS;
5519
5520	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
5521	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
5522	if (RT_UNLIKELY(!PGM_IS_IN_NEM_MODE(pVM)
5523	? idPage == NIL_GMM_PAGEID
5524	\|\| idPage > GMM_PAGEID_LAST
5525	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID
5526	: idPage != NIL_GMM_PAGEID))
5527	{
5528	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
5529	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
5530	}
5531	#ifdef VBOX_WITH_NATIVE_NEM
5532	const RTHCPHYS HCPhysPrev = PGM_PAGE_GET_HCPHYS(pPage);
5533	#endif
5534
5535	/* update page count stats. */
5536	if (PGM_PAGE_IS_SHARED(pPage))
5537	pVM->pgm.s.cSharedPages--;
5538	else
5539	pVM->pgm.s.cPrivatePages--;
5540	pVM->pgm.s.cZeroPages++;
5541
5542	/* Deal with write monitored pages. */
5543	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
5544	{
5545	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
5546	pVM->pgm.s.cWrittenToPages++;
5547	}
5548
5549	/*
5550	* pPage = ZERO page.
5551	*/
5552	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
5553	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
5554	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
5555	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
5556	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
5557	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
5558
5559	/* Flush physical page map TLB entry. */
5560	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
5561
5562	#ifdef VBOX_WITH_PGM_NEM_MODE
5563	/*
5564	* Skip the rest if we're doing a bulk free in NEM memory mode.
5565	*/
5566	if (!pReq)
5567	return VINF_SUCCESS;
5568	AssertLogRelReturn(!pVM->pgm.s.fNemMode, VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
5569	#endif
5570
5571	#ifdef VBOX_WITH_NATIVE_NEM
5572	/* Notify NEM. */
5573	/** @todo Remove this one? */
5574	if (VM_IS_NEM_ENABLED(pVM))
5575	{
5576	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pPage);
5577	NEMHCNotifyPhysPageChanged(pVM, GCPhys, HCPhysPrev, pVM->pgm.s.HCPhysZeroPg, pVM->pgm.s.pvZeroPgR3,
5578	pgmPhysPageCalcNemProtection(pPage, enmNewType), enmNewType, &u2State);
5579	PGM_PAGE_SET_NEM_STATE(pPage, u2State);
5580	}
5581	#else
5582	RT_NOREF(enmNewType);
5583	#endif
5584
5585	/*
5586	* Make sure it's not in the handy page array.
5587	*/
5588	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5589	{
5590	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
5591	{
5592	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
5593	break;
5594	}
5595	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
5596	{
5597	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
5598	break;
5599	}
5600	}
5601
5602	/*
5603	* Push it onto the page array.
5604	*/
5605	uint32_t iPage = *pcPendingPages;
5606	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
5607	*pcPendingPages += 1;
5608
5609	pReq->aPages[iPage].idPage = idPage;
5610
5611	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
5612	return VINF_SUCCESS;
5613
5614	/*
5615	* Flush the pages.
5616	*/
5617	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
5618	if (RT_SUCCESS(rc))
5619	{
5620	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
5621	*pcPendingPages = 0;
5622	}
5623	return rc;
5624	}
5625
5626
5627	/**
5628	* Converts a GC physical address to a HC ring-3 pointer, with some
5629	* additional checks.
5630	*
5631	* @returns VBox status code.
5632	* @retval VINF_SUCCESS on success.
5633	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
5634	* access handler of some kind.
5635	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
5636	* accesses or is odd in any way.
5637	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
5638	*
5639	* @param pVM The cross context VM structure.
5640	* @param GCPhys The GC physical address to convert. Since this is only
5641	* used for filling the REM TLB, the A20 mask must be
5642	* applied before calling this API.
5643	* @param fWritable Whether write access is required.
5644	* @param ppv Where to store the pointer corresponding to GCPhys on
5645	* success.
5646	*/
5647	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
5648	{
5649	PGM_LOCK_VOID(pVM);
5650	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
5651
5652	PPGMRAMRANGE pRam;
5653	PPGMPAGE pPage;
5654	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
5655	if (RT_SUCCESS(rc))
5656	{
5657	if (PGM_PAGE_IS_BALLOONED(pPage))
5658	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5659	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
5660	rc = VINF_SUCCESS;
5661	else
5662	{
5663	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
5664	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5665	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
5666	{
5667	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
5668	* in -norawr0 mode. */
5669	if (fWritable)
5670	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5671	}
5672	else
5673	{
5674	/* Temporarily disabled physical handler(s), since the recompiler
5675	doesn't get notified when it's reset we'll have to pretend it's
5676	operating normally. */
5677	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
5678	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
5679	else
5680	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
5681	}
5682	}
5683	if (RT_SUCCESS(rc))
5684	{
5685	int rc2;
5686
5687	/* Make sure what we return is writable. */
5688	if (fWritable)
5689	switch (PGM_PAGE_GET_STATE(pPage))
5690	{
5691	case PGM_PAGE_STATE_ALLOCATED:
5692	break;
5693	case PGM_PAGE_STATE_BALLOONED:
5694	AssertFailed();
5695	break;
5696	case PGM_PAGE_STATE_ZERO:
5697	case PGM_PAGE_STATE_SHARED:
5698	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
5699	break;
5700	RT_FALL_THRU();
5701	case PGM_PAGE_STATE_WRITE_MONITORED:
5702	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
5703	AssertLogRelRCReturn(rc2, rc2);
5704	break;
5705	}
5706
5707	/* Get a ring-3 mapping of the address. */
5708	PPGMPAGER3MAPTLBE pTlbe;
5709	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
5710	AssertLogRelRCReturn(rc2, rc2);
5711	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
5712	/** @todo mapping/locking hell; this isn't horribly efficient since
5713	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
5714
5715	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
5716	}
5717	else
5718	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
5719
5720	/* else: handler catching all access, no pointer returned. */
5721	}
5722	else
5723	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
5724
5725	PGM_UNLOCK(pVM);
5726	return rc;
5727	}
5728

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 91874

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