PGMPhys.cpp@ 92392

Last change on this file since 92392 was 92391, checked in by vboxsync, 3 years ago
VMM/PGM,GMM: Made pgmR0PhysAllocateHandyPages & GMMR0AllocateHandyPages callable from ring-0 HM context, eliminating the need for the call-ring-3 fun. bugref:10093
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1	/* $Id: PGMPhys.cpp 92391 2021-11-12 09:47:48Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
24	#include <VBox/vmm/pgm.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/iom.h>
27	#include <VBox/vmm/mm.h>
28	#include <VBox/vmm/nem.h>
29	#include <VBox/vmm/stam.h>
30	#include <VBox/vmm/pdmdev.h>
31	#include "PGMInternal.h"
32	#include <VBox/vmm/vmcc.h>
33
34	#include "PGMInline.h"
35
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#ifdef VBOX_STRICT
44	# include <iprt/crc.h>
45	#endif
46	#include <iprt/thread.h>
47	#include <iprt/string.h>
48	#include <iprt/system.h>
49
50
51	/*********************************************************************************************************************************
52	* Defined Constants And Macros *
53	*********************************************************************************************************************************/
54	/** The number of pages to free in one batch. */
55	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
56
57
58
59	/*********************************************************************************************************************************
60	* Reading and Writing Guest Pysical Memory *
61	*********************************************************************************************************************************/
62
63	/*
64	* PGMR3PhysReadU8-64
65	* PGMR3PhysWriteU8-64
66	*/
67	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
68	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
69	#define PGMPHYS_DATASIZE 1
70	#define PGMPHYS_DATATYPE uint8_t
71	#include "PGMPhysRWTmpl.h"
72
73	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
74	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
75	#define PGMPHYS_DATASIZE 2
76	#define PGMPHYS_DATATYPE uint16_t
77	#include "PGMPhysRWTmpl.h"
78
79	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
80	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
81	#define PGMPHYS_DATASIZE 4
82	#define PGMPHYS_DATATYPE uint32_t
83	#include "PGMPhysRWTmpl.h"
84
85	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
86	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
87	#define PGMPHYS_DATASIZE 8
88	#define PGMPHYS_DATATYPE uint64_t
89	#include "PGMPhysRWTmpl.h"
90
91
92	/**
93	* EMT worker for PGMR3PhysReadExternal.
94	*/
95	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
96	PGMACCESSORIGIN enmOrigin)
97	{
98	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
99	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
100	return VINF_SUCCESS;
101	}
102
103
104	/**
105	* Read from physical memory, external users.
106	*
107	* @returns VBox status code.
108	* @retval VINF_SUCCESS.
109	*
110	* @param pVM The cross context VM structure.
111	* @param GCPhys Physical address to read from.
112	* @param pvBuf Where to read into.
113	* @param cbRead How many bytes to read.
114	* @param enmOrigin Who is calling.
115	*
116	* @thread Any but EMTs.
117	*/
118	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
119	{
120	VM_ASSERT_OTHER_THREAD(pVM);
121
122	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
123	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
124
125	PGM_LOCK_VOID(pVM);
126
127	/*
128	* Copy loop on ram ranges.
129	*/
130	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
131	for (;;)
132	{
133	/* Inside range or not? */
134	if (pRam && GCPhys >= pRam->GCPhys)
135	{
136	/*
137	* Must work our way thru this page by page.
138	*/
139	RTGCPHYS off = GCPhys - pRam->GCPhys;
140	while (off < pRam->cb)
141	{
142	unsigned iPage = off >> PAGE_SHIFT;
143	PPGMPAGE pPage = &pRam->aPages[iPage];
144
145	/*
146	* If the page has an ALL access handler, we'll have to
147	* delegate the job to EMT.
148	*/
149	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
150	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
151	{
152	PGM_UNLOCK(pVM);
153
154	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
155	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
156	}
157	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
158
159	/*
160	* Simple stuff, go ahead.
161	*/
162	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
163	if (cb > cbRead)
164	cb = cbRead;
165	PGMPAGEMAPLOCK PgMpLck;
166	const void *pvSrc;
167	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
168	if (RT_SUCCESS(rc))
169	{
170	memcpy(pvBuf, pvSrc, cb);
171	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
172	}
173	else
174	{
175	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
176	pRam->GCPhys + off, pPage, rc));
177	memset(pvBuf, 0xff, cb);
178	}
179
180	/* next page */
181	if (cb >= cbRead)
182	{
183	PGM_UNLOCK(pVM);
184	return VINF_SUCCESS;
185	}
186	cbRead -= cb;
187	off += cb;
188	GCPhys += cb;
189	pvBuf = (char *)pvBuf + cb;
190	} /* walk pages in ram range. */
191	}
192	else
193	{
194	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
195
196	/*
197	* Unassigned address space.
198	*/
199	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
200	if (cb >= cbRead)
201	{
202	memset(pvBuf, 0xff, cbRead);
203	break;
204	}
205	memset(pvBuf, 0xff, cb);
206
207	cbRead -= cb;
208	pvBuf = (char *)pvBuf + cb;
209	GCPhys += cb;
210	}
211
212	/* Advance range if necessary. */
213	while (pRam && GCPhys > pRam->GCPhysLast)
214	pRam = pRam->CTX_SUFF(pNext);
215	} /* Ram range walk */
216
217	PGM_UNLOCK(pVM);
218
219	return VINF_SUCCESS;
220	}
221
222
223	/**
224	* EMT worker for PGMR3PhysWriteExternal.
225	*/
226	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
227	PGMACCESSORIGIN enmOrigin)
228	{
229	/** @todo VERR_EM_NO_MEMORY */
230	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
231	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
232	return VINF_SUCCESS;
233	}
234
235
236	/**
237	* Write to physical memory, external users.
238	*
239	* @returns VBox status code.
240	* @retval VINF_SUCCESS.
241	* @retval VERR_EM_NO_MEMORY.
242	*
243	* @param pVM The cross context VM structure.
244	* @param GCPhys Physical address to write to.
245	* @param pvBuf What to write.
246	* @param cbWrite How many bytes to write.
247	* @param enmOrigin Who is calling.
248	*
249	* @thread Any but EMTs.
250	*/
251	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
252	{
253	VM_ASSERT_OTHER_THREAD(pVM);
254
255	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
256	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
257	GCPhys, cbWrite, enmOrigin));
258	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
259	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
260
261	PGM_LOCK_VOID(pVM);
262
263	/*
264	* Copy loop on ram ranges, stop when we hit something difficult.
265	*/
266	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
267	for (;;)
268	{
269	/* Inside range or not? */
270	if (pRam && GCPhys >= pRam->GCPhys)
271	{
272	/*
273	* Must work our way thru this page by page.
274	*/
275	RTGCPTR off = GCPhys - pRam->GCPhys;
276	while (off < pRam->cb)
277	{
278	RTGCPTR iPage = off >> PAGE_SHIFT;
279	PPGMPAGE pPage = &pRam->aPages[iPage];
280
281	/*
282	* Is the page problematic, we have to do the work on the EMT.
283	*
284	* Allocating writable pages and access handlers are
285	* problematic, write monitored pages are simple and can be
286	* dealt with here.
287	*/
288	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
289	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
290	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
291	{
292	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
293	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
294	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
295	else
296	{
297	PGM_UNLOCK(pVM);
298
299	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
300	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
301	}
302	}
303	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
304
305	/*
306	* Simple stuff, go ahead.
307	*/
308	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
309	if (cb > cbWrite)
310	cb = cbWrite;
311	PGMPAGEMAPLOCK PgMpLck;
312	void *pvDst;
313	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
314	if (RT_SUCCESS(rc))
315	{
316	memcpy(pvDst, pvBuf, cb);
317	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
318	}
319	else
320	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
321	pRam->GCPhys + off, pPage, rc));
322
323	/* next page */
324	if (cb >= cbWrite)
325	{
326	PGM_UNLOCK(pVM);
327	return VINF_SUCCESS;
328	}
329
330	cbWrite -= cb;
331	off += cb;
332	GCPhys += cb;
333	pvBuf = (const char *)pvBuf + cb;
334	} /* walk pages in ram range */
335	}
336	else
337	{
338	/*
339	* Unassigned address space, skip it.
340	*/
341	if (!pRam)
342	break;
343	size_t cb = pRam->GCPhys - GCPhys;
344	if (cb >= cbWrite)
345	break;
346	cbWrite -= cb;
347	pvBuf = (const char *)pvBuf + cb;
348	GCPhys += cb;
349	}
350
351	/* Advance range if necessary. */
352	while (pRam && GCPhys > pRam->GCPhysLast)
353	pRam = pRam->CTX_SUFF(pNext);
354	} /* Ram range walk */
355
356	PGM_UNLOCK(pVM);
357	return VINF_SUCCESS;
358	}
359
360
361	/*********************************************************************************************************************************
362	* Mapping Guest Physical Memory *
363	*********************************************************************************************************************************/
364
365	/**
366	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
367	*
368	* @returns see PGMR3PhysGCPhys2CCPtrExternal
369	* @param pVM The cross context VM structure.
370	* @param pGCPhys Pointer to the guest physical address.
371	* @param ppv Where to store the mapping address.
372	* @param pLock Where to store the lock.
373	*/
374	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
375	{
376	/*
377	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
378	* an access handler after it succeeds.
379	*/
380	int rc = PGM_LOCK(pVM);
381	AssertRCReturn(rc, rc);
382
383	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
384	if (RT_SUCCESS(rc))
385	{
386	PPGMPAGEMAPTLBE pTlbe;
387	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
388	AssertFatalRC(rc2);
389	PPGMPAGE pPage = pTlbe->pPage;
390	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
391	{
392	PGMPhysReleasePageMappingLock(pVM, pLock);
393	rc = VERR_PGM_PHYS_PAGE_RESERVED;
394	}
395	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
396	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
397	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
398	#endif
399	)
400	{
401	/* We must flush any corresponding pgm pool page here, otherwise we'll
402	* not be informed about writes and keep bogus gst->shw mappings around.
403	*/
404	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
405	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
406	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
407	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
408	}
409	}
410
411	PGM_UNLOCK(pVM);
412	return rc;
413	}
414
415
416	/**
417	* Requests the mapping of a guest page into ring-3, external threads.
418	*
419	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
420	* release it.
421	*
422	* This API will assume your intention is to write to the page, and will
423	* therefore replace shared and zero pages. If you do not intend to modify the
424	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
425	*
426	* @returns VBox status code.
427	* @retval VINF_SUCCESS on success.
428	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
429	* backing or if the page has any active access handlers. The caller
430	* must fall back on using PGMR3PhysWriteExternal.
431	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
432	*
433	* @param pVM The cross context VM structure.
434	* @param GCPhys The guest physical address of the page that should be mapped.
435	* @param ppv Where to store the address corresponding to GCPhys.
436	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
437	*
438	* @remark Avoid calling this API from within critical sections (other than the
439	* PGM one) because of the deadlock risk when we have to delegating the
440	* task to an EMT.
441	* @thread Any.
442	*/
443	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
444	{
445	AssertPtr(ppv);
446	AssertPtr(pLock);
447
448	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
449
450	int rc = PGM_LOCK(pVM);
451	AssertRCReturn(rc, rc);
452
453	/*
454	* Query the Physical TLB entry for the page (may fail).
455	*/
456	PPGMPAGEMAPTLBE pTlbe;
457	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
458	if (RT_SUCCESS(rc))
459	{
460	PPGMPAGE pPage = pTlbe->pPage;
461	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
462	rc = VERR_PGM_PHYS_PAGE_RESERVED;
463	else
464	{
465	/*
466	* If the page is shared, the zero page, or being write monitored
467	* it must be converted to an page that's writable if possible.
468	* We can only deal with write monitored pages here, the rest have
469	* to be on an EMT.
470	*/
471	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
472	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
473	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
474	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
475	#endif
476	)
477	{
478	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
479	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
480	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
481	&& !pgmPoolIsDirtyPage(pVM, GCPhys) /** @todo we're very likely doing this twice. */
482	#endif
483	)
484	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
485	else
486	{
487	PGM_UNLOCK(pVM);
488
489	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
490	pVM, &GCPhys, ppv, pLock);
491	}
492	}
493
494	/*
495	* Now, just perform the locking and calculate the return address.
496	*/
497	PPGMPAGEMAP pMap = pTlbe->pMap;
498	if (pMap)
499	pMap->cRefs++;
500
501	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
502	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
503	{
504	if (cLocks == 0)
505	pVM->pgm.s.cWriteLockedPages++;
506	PGM_PAGE_INC_WRITE_LOCKS(pPage);
507	}
508	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
509	{
510	PGM_PAGE_INC_WRITE_LOCKS(pPage);
511	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
512	if (pMap)
513	pMap->cRefs++; /* Extra ref to prevent it from going away. */
514	}
515
516	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
517	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
518	pLock->pvMap = pMap;
519	}
520	}
521
522	PGM_UNLOCK(pVM);
523	return rc;
524	}
525
526
527	/**
528	* Requests the mapping of a guest page into ring-3, external threads.
529	*
530	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
531	* release it.
532	*
533	* @returns VBox status code.
534	* @retval VINF_SUCCESS on success.
535	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
536	* backing or if the page as an active ALL access handler. The caller
537	* must fall back on using PGMPhysRead.
538	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
539	*
540	* @param pVM The cross context VM structure.
541	* @param GCPhys The guest physical address of the page that should be mapped.
542	* @param ppv Where to store the address corresponding to GCPhys.
543	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
544	*
545	* @remark Avoid calling this API from within critical sections (other than
546	* the PGM one) because of the deadlock risk.
547	* @thread Any.
548	*/
549	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
550	{
551	int rc = PGM_LOCK(pVM);
552	AssertRCReturn(rc, rc);
553
554	/*
555	* Query the Physical TLB entry for the page (may fail).
556	*/
557	PPGMPAGEMAPTLBE pTlbe;
558	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
559	if (RT_SUCCESS(rc))
560	{
561	PPGMPAGE pPage = pTlbe->pPage;
562	#if 1
563	/* MMIO pages doesn't have any readable backing. */
564	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
565	rc = VERR_PGM_PHYS_PAGE_RESERVED;
566	#else
567	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
568	rc = VERR_PGM_PHYS_PAGE_RESERVED;
569	#endif
570	else
571	{
572	/*
573	* Now, just perform the locking and calculate the return address.
574	*/
575	PPGMPAGEMAP pMap = pTlbe->pMap;
576	if (pMap)
577	pMap->cRefs++;
578
579	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
580	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
581	{
582	if (cLocks == 0)
583	pVM->pgm.s.cReadLockedPages++;
584	PGM_PAGE_INC_READ_LOCKS(pPage);
585	}
586	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
587	{
588	PGM_PAGE_INC_READ_LOCKS(pPage);
589	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
590	if (pMap)
591	pMap->cRefs++; /* Extra ref to prevent it from going away. */
592	}
593
594	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
595	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
596	pLock->pvMap = pMap;
597	}
598	}
599
600	PGM_UNLOCK(pVM);
601	return rc;
602	}
603
604
605	/**
606	* Requests the mapping of multiple guest page into ring-3, external threads.
607	*
608	* When you're done with the pages, call PGMPhysBulkReleasePageMappingLock()
609	* ASAP to release them.
610	*
611	* This API will assume your intention is to write to the pages, and will
612	* therefore replace shared and zero pages. If you do not intend to modify the
613	* pages, use the PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal() API.
614	*
615	* @returns VBox status code.
616	* @retval VINF_SUCCESS on success.
617	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
618	* backing or if any of the pages the page has any active access
619	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
620	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
621	* an invalid physical address.
622	*
623	* @param pVM The cross context VM structure.
624	* @param cPages Number of pages to lock.
625	* @param paGCPhysPages The guest physical address of the pages that
626	* should be mapped (@a cPages entries).
627	* @param papvPages Where to store the ring-3 mapping addresses
628	* corresponding to @a paGCPhysPages.
629	* @param paLocks Where to store the locking information that
630	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
631	* in length).
632	*
633	* @remark Avoid calling this API from within critical sections (other than the
634	* PGM one) because of the deadlock risk when we have to delegating the
635	* task to an EMT.
636	* @thread Any.
637	*/
638	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
639	void **papvPages, PPGMPAGEMAPLOCK paLocks)
640	{
641	Assert(cPages > 0);
642	AssertPtr(papvPages);
643	AssertPtr(paLocks);
644
645	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
646
647	int rc = PGM_LOCK(pVM);
648	AssertRCReturn(rc, rc);
649
650	/*
651	* Lock the pages one by one.
652	* The loop body is similar to PGMR3PhysGCPhys2CCPtrExternal.
653	*/
654	int32_t cNextYield = 128;
655	uint32_t iPage;
656	for (iPage = 0; iPage < cPages; iPage++)
657	{
658	if (--cNextYield > 0)
659	{ /* likely */ }
660	else
661	{
662	PGM_UNLOCK(pVM);
663	ASMNopPause();
664	PGM_LOCK_VOID(pVM);
665	cNextYield = 128;
666	}
667
668	/*
669	* Query the Physical TLB entry for the page (may fail).
670	*/
671	PPGMPAGEMAPTLBE pTlbe;
672	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
673	if (RT_SUCCESS(rc))
674	{ }
675	else
676	break;
677	PPGMPAGE pPage = pTlbe->pPage;
678
679	/*
680	* No MMIO or active access handlers.
681	*/
682	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
683	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
684	{ }
685	else
686	{
687	rc = VERR_PGM_PHYS_PAGE_RESERVED;
688	break;
689	}
690
691	/*
692	* The page must be in the allocated state and not be a dirty pool page.
693	* We can handle converting a write monitored page to an allocated one, but
694	* anything more complicated must be delegated to an EMT.
695	*/
696	bool fDelegateToEmt = false;
697	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
698	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
699	fDelegateToEmt = pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]);
700	#else
701	fDelegateToEmt = false;
702	#endif
703	else if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
704	{
705	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
706	if (!pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]))
707	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, paGCPhysPages[iPage]);
708	else
709	fDelegateToEmt = true;
710	#endif
711	}
712	else
713	fDelegateToEmt = true;
714	if (!fDelegateToEmt)
715	{ }
716	else
717	{
718	/* We could do this delegation in bulk, but considered too much work vs gain. */
719	PGM_UNLOCK(pVM);
720	rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
721	pVM, &paGCPhysPages[iPage], &papvPages[iPage], &paLocks[iPage]);
722	PGM_LOCK_VOID(pVM);
723	if (RT_FAILURE(rc))
724	break;
725	cNextYield = 128;
726	}
727
728	/*
729	* Now, just perform the locking and address calculation.
730	*/
731	PPGMPAGEMAP pMap = pTlbe->pMap;
732	if (pMap)
733	pMap->cRefs++;
734
735	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
736	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
737	{
738	if (cLocks == 0)
739	pVM->pgm.s.cWriteLockedPages++;
740	PGM_PAGE_INC_WRITE_LOCKS(pPage);
741	}
742	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
743	{
744	PGM_PAGE_INC_WRITE_LOCKS(pPage);
745	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", paGCPhysPages[iPage], pPage));
746	if (pMap)
747	pMap->cRefs++; /* Extra ref to prevent it from going away. */
748	}
749
750	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
751	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
752	paLocks[iPage].pvMap = pMap;
753	}
754
755	PGM_UNLOCK(pVM);
756
757	/*
758	* On failure we must unlock any pages we managed to get already.
759	*/
760	if (RT_FAILURE(rc) && iPage > 0)
761	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
762
763	return rc;
764	}
765
766
767	/**
768	* Requests the mapping of multiple guest page into ring-3, for reading only,
769	* external threads.
770	*
771	* When you're done with the pages, call PGMPhysReleasePageMappingLock() ASAP
772	* to release them.
773	*
774	* @returns VBox status code.
775	* @retval VINF_SUCCESS on success.
776	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
777	* backing or if any of the pages the page has an active ALL access
778	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
779	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
780	* an invalid physical address.
781	*
782	* @param pVM The cross context VM structure.
783	* @param cPages Number of pages to lock.
784	* @param paGCPhysPages The guest physical address of the pages that
785	* should be mapped (@a cPages entries).
786	* @param papvPages Where to store the ring-3 mapping addresses
787	* corresponding to @a paGCPhysPages.
788	* @param paLocks Where to store the lock information that
789	* pfnPhysReleasePageMappingLock needs (@a cPages
790	* in length).
791	*
792	* @remark Avoid calling this API from within critical sections (other than
793	* the PGM one) because of the deadlock risk.
794	* @thread Any.
795	*/
796	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
797	void const **papvPages, PPGMPAGEMAPLOCK paLocks)
798	{
799	Assert(cPages > 0);
800	AssertPtr(papvPages);
801	AssertPtr(paLocks);
802
803	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
804
805	int rc = PGM_LOCK(pVM);
806	AssertRCReturn(rc, rc);
807
808	/*
809	* Lock the pages one by one.
810	* The loop body is similar to PGMR3PhysGCPhys2CCPtrReadOnlyExternal.
811	*/
812	int32_t cNextYield = 256;
813	uint32_t iPage;
814	for (iPage = 0; iPage < cPages; iPage++)
815	{
816	if (--cNextYield > 0)
817	{ /* likely */ }
818	else
819	{
820	PGM_UNLOCK(pVM);
821	ASMNopPause();
822	PGM_LOCK_VOID(pVM);
823	cNextYield = 256;
824	}
825
826	/*
827	* Query the Physical TLB entry for the page (may fail).
828	*/
829	PPGMPAGEMAPTLBE pTlbe;
830	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
831	if (RT_SUCCESS(rc))
832	{ }
833	else
834	break;
835	PPGMPAGE pPage = pTlbe->pPage;
836
837	/*
838	* No MMIO or active all access handlers, everything else can be accessed.
839	*/
840	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
841	&& !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
842	{ }
843	else
844	{
845	rc = VERR_PGM_PHYS_PAGE_RESERVED;
846	break;
847	}
848
849	/*
850	* Now, just perform the locking and address calculation.
851	*/
852	PPGMPAGEMAP pMap = pTlbe->pMap;
853	if (pMap)
854	pMap->cRefs++;
855
856	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
857	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
858	{
859	if (cLocks == 0)
860	pVM->pgm.s.cReadLockedPages++;
861	PGM_PAGE_INC_READ_LOCKS(pPage);
862	}
863	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
864	{
865	PGM_PAGE_INC_READ_LOCKS(pPage);
866	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", paGCPhysPages[iPage], pPage));
867	if (pMap)
868	pMap->cRefs++; /* Extra ref to prevent it from going away. */
869	}
870
871	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
872	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
873	paLocks[iPage].pvMap = pMap;
874	}
875
876	PGM_UNLOCK(pVM);
877
878	/*
879	* On failure we must unlock any pages we managed to get already.
880	*/
881	if (RT_FAILURE(rc) && iPage > 0)
882	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
883
884	return rc;
885	}
886
887
888	/**
889	* Converts a GC physical address to a HC ring-3 pointer, with some
890	* additional checks.
891	*
892	* @returns VBox status code.
893	* @retval VINF_SUCCESS on success.
894	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
895	* access handler of some kind.
896	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
897	* accesses or is odd in any way.
898	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
899	*
900	* @param pVM The cross context VM structure.
901	* @param GCPhys The GC physical address to convert. Since this is only
902	* used for filling the REM TLB, the A20 mask must be
903	* applied before calling this API.
904	* @param fWritable Whether write access is required.
905	* @param ppv Where to store the pointer corresponding to GCPhys on
906	* success.
907	*/
908	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
909	{
910	PGM_LOCK_VOID(pVM);
911	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
912
913	PPGMRAMRANGE pRam;
914	PPGMPAGE pPage;
915	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
916	if (RT_SUCCESS(rc))
917	{
918	if (PGM_PAGE_IS_BALLOONED(pPage))
919	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
920	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
921	rc = VINF_SUCCESS;
922	else
923	{
924	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
925	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
926	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
927	{
928	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
929	* in -norawr0 mode. */
930	if (fWritable)
931	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
932	}
933	else
934	{
935	/* Temporarily disabled physical handler(s), since the recompiler
936	doesn't get notified when it's reset we'll have to pretend it's
937	operating normally. */
938	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
939	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
940	else
941	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
942	}
943	}
944	if (RT_SUCCESS(rc))
945	{
946	int rc2;
947
948	/* Make sure what we return is writable. */
949	if (fWritable)
950	switch (PGM_PAGE_GET_STATE(pPage))
951	{
952	case PGM_PAGE_STATE_ALLOCATED:
953	break;
954	case PGM_PAGE_STATE_BALLOONED:
955	AssertFailed();
956	break;
957	case PGM_PAGE_STATE_ZERO:
958	case PGM_PAGE_STATE_SHARED:
959	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
960	break;
961	RT_FALL_THRU();
962	case PGM_PAGE_STATE_WRITE_MONITORED:
963	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
964	AssertLogRelRCReturn(rc2, rc2);
965	break;
966	}
967
968	/* Get a ring-3 mapping of the address. */
969	PPGMPAGER3MAPTLBE pTlbe;
970	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
971	AssertLogRelRCReturn(rc2, rc2);
972	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
973	/** @todo mapping/locking hell; this isn't horribly efficient since
974	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
975
976	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
977	}
978	else
979	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
980
981	/* else: handler catching all access, no pointer returned. */
982	}
983	else
984	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
985
986	PGM_UNLOCK(pVM);
987	return rc;
988	}
989
990
991
992	/*********************************************************************************************************************************
993	* RAM Range Management *
994	*********************************************************************************************************************************/
995
996	#define MAKE_LEAF(a_pNode) \
997	do { \
998	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
999	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
1000	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
1001	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
1002	} while (0)
1003
1004	#define INSERT_LEFT(a_pParent, a_pNode) \
1005	do { \
1006	(a_pParent)->pLeftR3 = (a_pNode); \
1007	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
1008	} while (0)
1009	#define INSERT_RIGHT(a_pParent, a_pNode) \
1010	do { \
1011	(a_pParent)->pRightR3 = (a_pNode); \
1012	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
1013	} while (0)
1014
1015
1016	/**
1017	* Recursive tree builder.
1018	*
1019	* @param ppRam Pointer to the iterator variable.
1020	* @param iDepth The current depth. Inserts a leaf node if 0.
1021	*/
1022	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
1023	{
1024	PPGMRAMRANGE pRam;
1025	if (iDepth <= 0)
1026	{
1027	/*
1028	* Leaf node.
1029	*/
1030	pRam = *ppRam;
1031	if (pRam)
1032	{
1033	*ppRam = pRam->pNextR3;
1034	MAKE_LEAF(pRam);
1035	}
1036	}
1037	else
1038	{
1039
1040	/*
1041	* Intermediate node.
1042	*/
1043	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
1044
1045	pRam = *ppRam;
1046	if (!pRam)
1047	return pLeft;
1048	*ppRam = pRam->pNextR3;
1049	MAKE_LEAF(pRam);
1050	INSERT_LEFT(pRam, pLeft);
1051
1052	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
1053	if (pRight)
1054	INSERT_RIGHT(pRam, pRight);
1055	}
1056	return pRam;
1057	}
1058
1059
1060	/**
1061	* Rebuilds the RAM range search trees.
1062	*
1063	* @param pVM The cross context VM structure.
1064	*/
1065	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
1066	{
1067
1068	/*
1069	* Create the reasonably balanced tree in a sequential fashion.
1070	* For simplicity (laziness) we use standard recursion here.
1071	*/
1072	int iDepth = 0;
1073	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1074	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
1075	while (pRam)
1076	{
1077	PPGMRAMRANGE pLeft = pRoot;
1078
1079	pRoot = pRam;
1080	pRam = pRam->pNextR3;
1081	MAKE_LEAF(pRoot);
1082	INSERT_LEFT(pRoot, pLeft);
1083
1084	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
1085	if (pRight)
1086	INSERT_RIGHT(pRoot, pRight);
1087	/** @todo else: rotate the tree. */
1088
1089	iDepth++;
1090	}
1091
1092	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
1093	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
1094
1095	#ifdef VBOX_STRICT
1096	/*
1097	* Verify that the above code works.
1098	*/
1099	unsigned cRanges = 0;
1100	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1101	cRanges++;
1102	Assert(cRanges > 0);
1103
1104	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
1105	if ((1U << cMaxDepth) < cRanges)
1106	cMaxDepth++;
1107
1108	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1109	{
1110	unsigned cDepth = 0;
1111	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
1112	for (;;)
1113	{
1114	if (pRam == pRam2)
1115	break;
1116	Assert(pRam2);
1117	if (pRam->GCPhys < pRam2->GCPhys)
1118	pRam2 = pRam2->pLeftR3;
1119	else
1120	pRam2 = pRam2->pRightR3;
1121	}
1122	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
1123	}
1124	#endif /* VBOX_STRICT */
1125	}
1126
1127	#undef MAKE_LEAF
1128	#undef INSERT_LEFT
1129	#undef INSERT_RIGHT
1130
1131	/**
1132	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
1133	*
1134	* Called when anything was relocated.
1135	*
1136	* @param pVM The cross context VM structure.
1137	*/
1138	void pgmR3PhysRelinkRamRanges(PVM pVM)
1139	{
1140	PPGMRAMRANGE pCur;
1141
1142	#ifdef VBOX_STRICT
1143	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1144	{
1145	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
1146	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
1147	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1148	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
1149	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
1150	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
1151	Assert( pCur2 == pCur
1152	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
1153	}
1154	#endif
1155
1156	pCur = pVM->pgm.s.pRamRangesXR3;
1157	if (pCur)
1158	{
1159	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
1160
1161	for (; pCur->pNextR3; pCur = pCur->pNextR3)
1162	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
1163
1164	Assert(pCur->pNextR0 == NIL_RTR0PTR);
1165	}
1166	else
1167	{
1168	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
1169	}
1170	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1171
1172	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1173	}
1174
1175
1176	/**
1177	* Links a new RAM range into the list.
1178	*
1179	* @param pVM The cross context VM structure.
1180	* @param pNew Pointer to the new list entry.
1181	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1182	*/
1183	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
1184	{
1185	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
1186	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
1187
1188	PGM_LOCK_VOID(pVM);
1189
1190	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
1191	pNew->pNextR3 = pRam;
1192	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
1193
1194	if (pPrev)
1195	{
1196	pPrev->pNextR3 = pNew;
1197	pPrev->pNextR0 = pNew->pSelfR0;
1198	}
1199	else
1200	{
1201	pVM->pgm.s.pRamRangesXR3 = pNew;
1202	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
1203	}
1204	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1205
1206	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1207	PGM_UNLOCK(pVM);
1208	}
1209
1210
1211	/**
1212	* Unlink an existing RAM range from the list.
1213	*
1214	* @param pVM The cross context VM structure.
1215	* @param pRam Pointer to the new list entry.
1216	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1217	*/
1218	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
1219	{
1220	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
1221	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
1222
1223	PGM_LOCK_VOID(pVM);
1224
1225	PPGMRAMRANGE pNext = pRam->pNextR3;
1226	if (pPrev)
1227	{
1228	pPrev->pNextR3 = pNext;
1229	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1230	}
1231	else
1232	{
1233	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
1234	pVM->pgm.s.pRamRangesXR3 = pNext;
1235	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1236	}
1237	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1238
1239	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1240	PGM_UNLOCK(pVM);
1241	}
1242
1243
1244	/**
1245	* Unlink an existing RAM range from the list.
1246	*
1247	* @param pVM The cross context VM structure.
1248	* @param pRam Pointer to the new list entry.
1249	*/
1250	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
1251	{
1252	PGM_LOCK_VOID(pVM);
1253
1254	/* find prev. */
1255	PPGMRAMRANGE pPrev = NULL;
1256	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
1257	while (pCur != pRam)
1258	{
1259	pPrev = pCur;
1260	pCur = pCur->pNextR3;
1261	}
1262	AssertFatal(pCur);
1263
1264	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
1265	PGM_UNLOCK(pVM);
1266	}
1267
1268
1269	/**
1270	* Gets the number of ram ranges.
1271	*
1272	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1273	* @param pVM The cross context VM structure.
1274	*/
1275	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1276	{
1277	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1278
1279	PGM_LOCK_VOID(pVM);
1280	uint32_t cRamRanges = 0;
1281	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1282	cRamRanges++;
1283	PGM_UNLOCK(pVM);
1284	return cRamRanges;
1285	}
1286
1287
1288	/**
1289	* Get information about a range.
1290	*
1291	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1292	* @param pVM The cross context VM structure.
1293	* @param iRange The ordinal of the range.
1294	* @param pGCPhysStart Where to return the start of the range. Optional.
1295	* @param pGCPhysLast Where to return the address of the last byte in the
1296	* range. Optional.
1297	* @param ppszDesc Where to return the range description. Optional.
1298	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1299	* Optional.
1300	*/
1301	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1302	const char *ppszDesc, bool pfIsMmio)
1303	{
1304	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1305
1306	PGM_LOCK_VOID(pVM);
1307	uint32_t iCurRange = 0;
1308	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1309	if (iCurRange == iRange)
1310	{
1311	if (pGCPhysStart)
1312	*pGCPhysStart = pCur->GCPhys;
1313	if (pGCPhysLast)
1314	*pGCPhysLast = pCur->GCPhysLast;
1315	if (ppszDesc)
1316	*ppszDesc = pCur->pszDesc;
1317	if (pfIsMmio)
1318	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1319
1320	PGM_UNLOCK(pVM);
1321	return VINF_SUCCESS;
1322	}
1323	PGM_UNLOCK(pVM);
1324	return VERR_OUT_OF_RANGE;
1325	}
1326
1327
1328	/*********************************************************************************************************************************
1329	* RAM *
1330	*********************************************************************************************************************************/
1331
1332	/**
1333	* Frees the specified RAM page and replaces it with the ZERO page.
1334	*
1335	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
1336	*
1337	* @param pVM The cross context VM structure.
1338	* @param pReq Pointer to the request. This is NULL when doing a
1339	* bulk free in NEM memory mode.
1340	* @param pcPendingPages Where the number of pages waiting to be freed are
1341	* kept. This will normally be incremented. This is
1342	* NULL when doing a bulk free in NEM memory mode.
1343	* @param pPage Pointer to the page structure.
1344	* @param GCPhys The guest physical address of the page, if applicable.
1345	* @param enmNewType New page type for NEM notification, since several
1346	* callers will change the type upon successful return.
1347	*
1348	* @remarks The caller must own the PGM lock.
1349	*/
1350	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
1351	PGMPAGETYPE enmNewType)
1352	{
1353	/*
1354	* Assert sanity.
1355	*/
1356	PGM_LOCK_ASSERT_OWNER(pVM);
1357	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
1358	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
1359	{
1360	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
1361	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
1362	}
1363
1364	/** @todo What about ballooning of large pages??! */
1365	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
1366	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
1367
1368	if ( PGM_PAGE_IS_ZERO(pPage)
1369	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1370	return VINF_SUCCESS;
1371
1372	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
1373	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
1374	if (RT_UNLIKELY(!PGM_IS_IN_NEM_MODE(pVM)
1375	? idPage == NIL_GMM_PAGEID
1376	\|\| idPage > GMM_PAGEID_LAST
1377	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID
1378	: idPage != NIL_GMM_PAGEID))
1379	{
1380	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
1381	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
1382	}
1383	#ifdef VBOX_WITH_NATIVE_NEM
1384	const RTHCPHYS HCPhysPrev = PGM_PAGE_GET_HCPHYS(pPage);
1385	#endif
1386
1387	/* update page count stats. */
1388	if (PGM_PAGE_IS_SHARED(pPage))
1389	pVM->pgm.s.cSharedPages--;
1390	else
1391	pVM->pgm.s.cPrivatePages--;
1392	pVM->pgm.s.cZeroPages++;
1393
1394	/* Deal with write monitored pages. */
1395	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1396	{
1397	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
1398	pVM->pgm.s.cWrittenToPages++;
1399	}
1400
1401	/*
1402	* pPage = ZERO page.
1403	*/
1404	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
1405	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1406	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
1407	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
1408	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
1409	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
1410
1411	/* Flush physical page map TLB entry. */
1412	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
1413
1414	#ifdef VBOX_WITH_PGM_NEM_MODE
1415	/*
1416	* Skip the rest if we're doing a bulk free in NEM memory mode.
1417	*/
1418	if (!pReq)
1419	return VINF_SUCCESS;
1420	AssertLogRelReturn(!pVM->pgm.s.fNemMode, VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
1421	#endif
1422
1423	#ifdef VBOX_WITH_NATIVE_NEM
1424	/* Notify NEM. */
1425	/** @todo Remove this one? */
1426	if (VM_IS_NEM_ENABLED(pVM))
1427	{
1428	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pPage);
1429	NEMHCNotifyPhysPageChanged(pVM, GCPhys, HCPhysPrev, pVM->pgm.s.HCPhysZeroPg, pVM->pgm.s.pvZeroPgR3,
1430	pgmPhysPageCalcNemProtection(pPage, enmNewType), enmNewType, &u2State);
1431	PGM_PAGE_SET_NEM_STATE(pPage, u2State);
1432	}
1433	#else
1434	RT_NOREF(enmNewType);
1435	#endif
1436
1437	/*
1438	* Make sure it's not in the handy page array.
1439	*/
1440	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1441	{
1442	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
1443	{
1444	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1445	break;
1446	}
1447	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
1448	{
1449	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1450	break;
1451	}
1452	}
1453
1454	/*
1455	* Push it onto the page array.
1456	*/
1457	uint32_t iPage = *pcPendingPages;
1458	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
1459	*pcPendingPages += 1;
1460
1461	pReq->aPages[iPage].idPage = idPage;
1462
1463	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
1464	return VINF_SUCCESS;
1465
1466	/*
1467	* Flush the pages.
1468	*/
1469	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
1470	if (RT_SUCCESS(rc))
1471	{
1472	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1473	*pcPendingPages = 0;
1474	}
1475	return rc;
1476	}
1477
1478
1479	/**
1480	* Frees a range of pages, replacing them with ZERO pages of the specified type.
1481	*
1482	* @returns VBox status code.
1483	* @param pVM The cross context VM structure.
1484	* @param pRam The RAM range in which the pages resides.
1485	* @param GCPhys The address of the first page.
1486	* @param GCPhysLast The address of the last page.
1487	* @param pvMmio2 Pointer to the ring-3 mapping of any MMIO2 memory that
1488	* will replace the pages we're freeing up.
1489	*/
1490	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, void *pvMmio2)
1491	{
1492	PGM_LOCK_ASSERT_OWNER(pVM);
1493
1494	#ifdef VBOX_WITH_PGM_NEM_MODE
1495	/*
1496	* In simplified memory mode we don't actually free the memory,
1497	* we just unmap it and let NEM do any unlocking of it.
1498	*/
1499	if (pVM->pgm.s.fNemMode)
1500	{
1501	Assert(VM_IS_NEM_ENABLED(pVM));
1502	uint32_t const fNemNotify = (pvMmio2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0) \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE;
1503	uint8_t u2State = 0; /* (We don't support UINT8_MAX here.) */
1504	int rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify,
1505	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL,
1506	pvMmio2, &u2State, NULL /puNemRange/);
1507	AssertLogRelRCReturn(rc, rc);
1508
1509	/* Iterate the pages. */
1510	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1511	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1512	while (cPagesLeft-- > 0)
1513	{
1514	rc = pgmPhysFreePage(pVM, NULL, NULL, pPageDst, GCPhys, PGMPAGETYPE_MMIO);
1515	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1516
1517	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO);
1518	PGM_PAGE_SET_NEM_STATE(pPageDst, u2State);
1519
1520	GCPhys += PAGE_SIZE;
1521	pPageDst++;
1522	}
1523	return rc;
1524	}
1525	#else /* !VBOX_WITH_PGM_NEM_MODE */
1526	RT_NOREF(pvMmio2);
1527	#endif /* !VBOX_WITH_PGM_NEM_MODE */
1528
1529	/*
1530	* Regular mode.
1531	*/
1532	/* Prepare. */
1533	uint32_t cPendingPages = 0;
1534	PGMMFREEPAGESREQ pReq;
1535	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1536	AssertLogRelRCReturn(rc, rc);
1537
1538	#ifdef VBOX_WITH_NATIVE_NEM
1539	/* Tell NEM up-front. */
1540	uint8_t u2State = UINT8_MAX;
1541	if (VM_IS_NEM_ENABLED(pVM))
1542	{
1543	uint32_t const fNemNotify = (pvMmio2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0) \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE;
1544	rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify, NULL, pvMmio2,
1545	&u2State, NULL /puNemRange/);
1546	AssertLogRelRCReturnStmt(rc, GMMR3FreePagesCleanup(pReq), rc);
1547	}
1548	#endif
1549
1550	/* Iterate the pages. */
1551	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1552	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1553	while (cPagesLeft-- > 0)
1554	{
1555	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys, PGMPAGETYPE_MMIO);
1556	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1557
1558	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO);
1559	#ifdef VBOX_WITH_NATIVE_NEM
1560	if (u2State != UINT8_MAX)
1561	PGM_PAGE_SET_NEM_STATE(pPageDst, u2State);
1562	#endif
1563
1564	GCPhys += PAGE_SIZE;
1565	pPageDst++;
1566	}
1567
1568	/* Finish pending and cleanup. */
1569	if (cPendingPages)
1570	{
1571	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1572	AssertLogRelRCReturn(rc, rc);
1573	}
1574	GMMR3FreePagesCleanup(pReq);
1575
1576	return rc;
1577	}
1578
1579
1580	/**
1581	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1582	*
1583	* In NEM mode, this will allocate the pages backing the RAM range and this may
1584	* fail. NEM registration may also fail. (In regular HM mode it won't fail.)
1585	*
1586	* @returns VBox status code.
1587	* @param pVM The cross context VM structure.
1588	* @param pNew The new RAM range.
1589	* @param GCPhys The address of the RAM range.
1590	* @param GCPhysLast The last address of the RAM range.
1591	* @param R0PtrNew Ditto for R0.
1592	* @param fFlags PGM_RAM_RANGE_FLAGS_FLOATING or zero.
1593	* @param pszDesc The description.
1594	* @param pPrev The previous RAM range (for linking).
1595	*/
1596	static int pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1597	RTR0PTR R0PtrNew, uint32_t fFlags, const char *pszDesc, PPGMRAMRANGE pPrev)
1598	{
1599	/*
1600	* Initialize the range.
1601	*/
1602	pNew->pSelfR0 = R0PtrNew;
1603	pNew->GCPhys = GCPhys;
1604	pNew->GCPhysLast = GCPhysLast;
1605	pNew->cb = GCPhysLast - GCPhys + 1;
1606	pNew->pszDesc = pszDesc;
1607	pNew->fFlags = fFlags;
1608	pNew->uNemRange = UINT32_MAX;
1609	pNew->pvR3 = NULL;
1610	pNew->paLSPages = NULL;
1611
1612	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1613	#ifdef VBOX_WITH_PGM_NEM_MODE
1614	if (!pVM->pgm.s.fNemMode)
1615	#endif
1616	{
1617	RTGCPHYS iPage = cPages;
1618	while (iPage-- > 0)
1619	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1620
1621	/* Update the page count stats. */
1622	pVM->pgm.s.cZeroPages += cPages;
1623	pVM->pgm.s.cAllPages += cPages;
1624	}
1625	#ifdef VBOX_WITH_PGM_NEM_MODE
1626	else
1627	{
1628	int rc = SUPR3PageAlloc(cPages, &pNew->pvR3);
1629	if (RT_FAILURE(rc))
1630	return rc;
1631
1632	RTGCPHYS iPage = cPages;
1633	while (iPage-- > 0)
1634	PGM_PAGE_INIT(&pNew->aPages[iPage], UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
1635	PGMPAGETYPE_RAM, PGM_PAGE_STATE_ALLOCATED);
1636
1637	/* Update the page count stats. */
1638	pVM->pgm.s.cPrivatePages += cPages;
1639	pVM->pgm.s.cAllPages += cPages;
1640	}
1641	#endif
1642
1643	/*
1644	* Link it.
1645	*/
1646	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1647
1648	#ifdef VBOX_WITH_NATIVE_NEM
1649	/*
1650	* Notify NEM now that it has been linked.
1651	*/
1652	if (VM_IS_NEM_ENABLED(pVM))
1653	{
1654	uint8_t u2State = UINT8_MAX;
1655	int rc = NEMR3NotifyPhysRamRegister(pVM, GCPhys, pNew->cb, pNew->pvR3, &u2State, &pNew->uNemRange);
1656	if (RT_SUCCESS(rc))
1657	{
1658	if (u2State != UINT8_MAX)
1659	pgmPhysSetNemStateForPages(&pNew->aPages[0], cPages, u2State);
1660	}
1661	else
1662	pgmR3PhysUnlinkRamRange2(pVM, pNew, pPrev);
1663	return rc;
1664	}
1665	#endif
1666	return VINF_SUCCESS;
1667	}
1668
1669
1670	/**
1671	* PGMR3PhysRegisterRam worker that registers a high chunk.
1672	*
1673	* @returns VBox status code.
1674	* @param pVM The cross context VM structure.
1675	* @param GCPhys The address of the RAM.
1676	* @param cRamPages The number of RAM pages to register.
1677	* @param iChunk The chunk number.
1678	* @param pszDesc The RAM range description.
1679	* @param ppPrev Previous RAM range pointer. In/Out.
1680	*/
1681	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages, uint32_t iChunk,
1682	const char pszDesc, PPGMRAMRANGE ppPrev)
1683	{
1684	const char *pszDescChunk = iChunk == 0
1685	? pszDesc
1686	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1687	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1688
1689	/*
1690	* Allocate memory for the new chunk.
1691	*/
1692	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1693	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1694	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1695	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1696	void *pvChunk = NULL;
1697	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
1698	if (RT_SUCCESS(rc))
1699	{
1700	Assert(R0PtrChunk != NIL_RTR0PTR);
1701	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1702
1703	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1704
1705	/*
1706	* Ok, init and link the range.
1707	*/
1708	rc = pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1709	R0PtrChunk, PGM_RAM_RANGE_FLAGS_FLOATING, pszDescChunk, *ppPrev);
1710	if (RT_SUCCESS(rc))
1711	*ppPrev = pNew;
1712
1713	if (RT_FAILURE(rc))
1714	SUPR3PageFreeEx(pvChunk, cChunkPages);
1715	}
1716
1717	RTMemTmpFree(paChunkPages);
1718	return rc;
1719	}
1720
1721
1722	/**
1723	* Sets up a range RAM.
1724	*
1725	* This will check for conflicting registrations, make a resource
1726	* reservation for the memory (with GMM), and setup the per-page
1727	* tracking structures (PGMPAGE).
1728	*
1729	* @returns VBox status code.
1730	* @param pVM The cross context VM structure.
1731	* @param GCPhys The physical address of the RAM.
1732	* @param cb The size of the RAM.
1733	* @param pszDesc The description - not copied, so, don't free or change it.
1734	*/
1735	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1736	{
1737	/*
1738	* Validate input.
1739	*/
1740	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1741	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1742	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1743	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1744	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1745	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1746	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1747	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1748
1749	PGM_LOCK_VOID(pVM);
1750
1751	/*
1752	* Find range location and check for conflicts.
1753	*/
1754	PPGMRAMRANGE pPrev = NULL;
1755	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1756	while (pRam && GCPhysLast >= pRam->GCPhys)
1757	{
1758	AssertLogRelMsgReturnStmt( GCPhysLast < pRam->GCPhys
1759	\|\| GCPhys > pRam->GCPhysLast,
1760	("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1761	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1762	PGM_UNLOCK(pVM), VERR_PGM_RAM_CONFLICT);
1763
1764	/* next */
1765	pPrev = pRam;
1766	pRam = pRam->pNextR3;
1767	}
1768
1769	/*
1770	* Register it with GMM (the API bitches).
1771	*/
1772	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1773	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1774	if (RT_FAILURE(rc))
1775	{
1776	PGM_UNLOCK(pVM);
1777	return rc;
1778	}
1779
1780	if ( GCPhys >= _4G
1781	&& cPages > 256)
1782	{
1783	/*
1784	* The PGMRAMRANGE structures for the high memory can get very big.
1785	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1786	* allocation size limit there and also to avoid being unable to find
1787	* guest mapping space for them, we split this memory up into 4MB in
1788	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1789	* mode.
1790	*
1791	* The first and last page of each mapping are guard pages and marked
1792	* not-present. So, we've got 4186112 and 16769024 bytes available for
1793	* the PGMRAMRANGE structure.
1794	*
1795	* Note! The sizes used here will influence the saved state.
1796	*/
1797	uint32_t cbChunk = 16U*_1M;
1798	uint32_t cPagesPerChunk = 1048048; /* max ~1048059 */
1799	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1800	AssertRelease(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1801
1802	RTGCPHYS cPagesLeft = cPages;
1803	RTGCPHYS GCPhysChunk = GCPhys;
1804	uint32_t iChunk = 0;
1805	while (cPagesLeft > 0)
1806	{
1807	uint32_t cPagesInChunk = cPagesLeft;
1808	if (cPagesInChunk > cPagesPerChunk)
1809	cPagesInChunk = cPagesPerChunk;
1810
1811	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, iChunk, pszDesc, &pPrev);
1812	AssertRCReturn(rc, rc);
1813
1814	/* advance */
1815	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1816	cPagesLeft -= cPagesInChunk;
1817	iChunk++;
1818	}
1819	}
1820	else
1821	{
1822	/*
1823	* Allocate, initialize and link the new RAM range.
1824	*/
1825	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
1826	PPGMRAMRANGE pNew;
1827	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1828	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc cbRamRange=%zu\n", rc, cbRamRange), rc);
1829
1830	rc = pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, MMHyperCCToR0(pVM, pNew), 0 /fFlags/, pszDesc, pPrev);
1831	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc cbRamRange=%zu\n", rc, cbRamRange), rc);
1832	}
1833	pgmPhysInvalidatePageMapTLB(pVM);
1834
1835	PGM_UNLOCK(pVM);
1836	return rc;
1837	}
1838
1839
1840	/**
1841	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1842	*
1843	* We do this late in the init process so that all the ROM and MMIO ranges have
1844	* been registered already and we don't go wasting memory on them.
1845	*
1846	* @returns VBox status code.
1847	*
1848	* @param pVM The cross context VM structure.
1849	*/
1850	int pgmR3PhysRamPreAllocate(PVM pVM)
1851	{
1852	Assert(pVM->pgm.s.fRamPreAlloc);
1853	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1854	#ifdef VBOX_WITH_PGM_NEM_MODE
1855	AssertLogRelReturn(!pVM->pgm.s.fNemMode, VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
1856	#endif
1857
1858	/*
1859	* Walk the RAM ranges and allocate all RAM pages, halt at
1860	* the first allocation error.
1861	*/
1862	uint64_t cPages = 0;
1863	uint64_t NanoTS = RTTimeNanoTS();
1864	PGM_LOCK_VOID(pVM);
1865	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1866	{
1867	PPGMPAGE pPage = &pRam->aPages[0];
1868	RTGCPHYS GCPhys = pRam->GCPhys;
1869	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1870	while (cLeft-- > 0)
1871	{
1872	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1873	{
1874	switch (PGM_PAGE_GET_STATE(pPage))
1875	{
1876	case PGM_PAGE_STATE_ZERO:
1877	{
1878	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1879	if (RT_FAILURE(rc))
1880	{
1881	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1882	PGM_UNLOCK(pVM);
1883	return rc;
1884	}
1885	cPages++;
1886	break;
1887	}
1888
1889	case PGM_PAGE_STATE_BALLOONED:
1890	case PGM_PAGE_STATE_ALLOCATED:
1891	case PGM_PAGE_STATE_WRITE_MONITORED:
1892	case PGM_PAGE_STATE_SHARED:
1893	/* nothing to do here. */
1894	break;
1895	}
1896	}
1897
1898	/* next */
1899	pPage++;
1900	GCPhys += PAGE_SIZE;
1901	}
1902	}
1903	PGM_UNLOCK(pVM);
1904	NanoTS = RTTimeNanoTS() - NanoTS;
1905
1906	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1907	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1908	return VINF_SUCCESS;
1909	}
1910
1911
1912	/**
1913	* Checks shared page checksums.
1914	*
1915	* @param pVM The cross context VM structure.
1916	*/
1917	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
1918	{
1919	#ifdef VBOX_STRICT
1920	PGM_LOCK_VOID(pVM);
1921
1922	if (pVM->pgm.s.cSharedPages > 0)
1923	{
1924	/*
1925	* Walk the ram ranges.
1926	*/
1927	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1928	{
1929	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1930	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1931
1932	while (iPage-- > 0)
1933	{
1934	PPGMPAGE pPage = &pRam->aPages[iPage];
1935	if (PGM_PAGE_IS_SHARED(pPage))
1936	{
1937	uint32_t u32Checksum = pPage->s.u2Unused0/* \| ((uint32_t)pPage->s.u2Unused1 << 8)*/;
1938	if (!u32Checksum)
1939	{
1940	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1941	void const *pvPage;
1942	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
1943	if (RT_SUCCESS(rc))
1944	{
1945	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
1946	# if 0
1947	AssertMsg((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
1948	# else
1949	if ((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum)
1950	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1951	else
1952	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1953	# endif
1954	}
1955	else
1956	AssertRC(rc);
1957	}
1958	}
1959
1960	} /* for each page */
1961
1962	} /* for each ram range */
1963	}
1964
1965	PGM_UNLOCK(pVM);
1966	#endif /* VBOX_STRICT */
1967	NOREF(pVM);
1968	}
1969
1970
1971	/**
1972	* Resets the physical memory state.
1973	*
1974	* ASSUMES that the caller owns the PGM lock.
1975	*
1976	* @returns VBox status code.
1977	* @param pVM The cross context VM structure.
1978	*/
1979	int pgmR3PhysRamReset(PVM pVM)
1980	{
1981	PGM_LOCK_ASSERT_OWNER(pVM);
1982
1983	/* Reset the memory balloon. */
1984	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1985	AssertRC(rc);
1986
1987	#ifdef VBOX_WITH_PAGE_SHARING
1988	/* Clear all registered shared modules. */
1989	pgmR3PhysAssertSharedPageChecksums(pVM);
1990	rc = GMMR3ResetSharedModules(pVM);
1991	AssertRC(rc);
1992	#endif
1993	/* Reset counters. */
1994	pVM->pgm.s.cReusedSharedPages = 0;
1995	pVM->pgm.s.cBalloonedPages = 0;
1996
1997	return VINF_SUCCESS;
1998	}
1999
2000
2001	/**
2002	* Resets (zeros) the RAM after all devices and components have been reset.
2003	*
2004	* ASSUMES that the caller owns the PGM lock.
2005	*
2006	* @returns VBox status code.
2007	* @param pVM The cross context VM structure.
2008	*/
2009	int pgmR3PhysRamZeroAll(PVM pVM)
2010	{
2011	PGM_LOCK_ASSERT_OWNER(pVM);
2012
2013	/*
2014	* We batch up pages that should be freed instead of calling GMM for
2015	* each and every one of them.
2016	*/
2017	uint32_t cPendingPages = 0;
2018	PGMMFREEPAGESREQ pReq;
2019	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2020	AssertLogRelRCReturn(rc, rc);
2021
2022	/*
2023	* Walk the ram ranges.
2024	*/
2025	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2026	{
2027	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2028	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2029
2030	if ( !pVM->pgm.s.fRamPreAlloc
2031	#ifdef VBOX_WITH_PGM_NEM_MODE
2032	&& !pVM->pgm.s.fNemMode
2033	#endif
2034	&& pVM->pgm.s.fZeroRamPagesOnReset)
2035	{
2036	/* Replace all RAM pages by ZERO pages. */
2037	while (iPage-- > 0)
2038	{
2039	PPGMPAGE pPage = &pRam->aPages[iPage];
2040	switch (PGM_PAGE_GET_TYPE(pPage))
2041	{
2042	case PGMPAGETYPE_RAM:
2043	/* Do not replace pages part of a 2 MB continuous range
2044	with zero pages, but zero them instead. */
2045	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
2046	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2047	{
2048	void *pvPage;
2049	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2050	AssertLogRelRCReturn(rc, rc);
2051	ASMMemZeroPage(pvPage);
2052	}
2053	else if (PGM_PAGE_IS_BALLOONED(pPage))
2054	{
2055	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2056	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2057	}
2058	else if (!PGM_PAGE_IS_ZERO(pPage))
2059	{
2060	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2061	PGMPAGETYPE_RAM);
2062	AssertLogRelRCReturn(rc, rc);
2063	}
2064	break;
2065
2066	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2067	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2068	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2069	pRam, true /fDoAccounting/);
2070	break;
2071
2072	case PGMPAGETYPE_MMIO2:
2073	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2074	case PGMPAGETYPE_ROM:
2075	case PGMPAGETYPE_MMIO:
2076	break;
2077	default:
2078	AssertFailed();
2079	}
2080	} /* for each page */
2081	}
2082	else
2083	{
2084	/* Zero the memory. */
2085	while (iPage-- > 0)
2086	{
2087	PPGMPAGE pPage = &pRam->aPages[iPage];
2088	switch (PGM_PAGE_GET_TYPE(pPage))
2089	{
2090	case PGMPAGETYPE_RAM:
2091	switch (PGM_PAGE_GET_STATE(pPage))
2092	{
2093	case PGM_PAGE_STATE_ZERO:
2094	break;
2095
2096	case PGM_PAGE_STATE_BALLOONED:
2097	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2098	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2099	break;
2100
2101	case PGM_PAGE_STATE_SHARED:
2102	case PGM_PAGE_STATE_WRITE_MONITORED:
2103	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2104	AssertLogRelRCReturn(rc, rc);
2105	RT_FALL_THRU();
2106
2107	case PGM_PAGE_STATE_ALLOCATED:
2108	if (pVM->pgm.s.fZeroRamPagesOnReset)
2109	{
2110	void *pvPage;
2111	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2112	AssertLogRelRCReturn(rc, rc);
2113	ASMMemZeroPage(pvPage);
2114	}
2115	break;
2116	}
2117	break;
2118
2119	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2120	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2121	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2122	pRam, true /fDoAccounting/);
2123	break;
2124
2125	case PGMPAGETYPE_MMIO2:
2126	case PGMPAGETYPE_ROM_SHADOW:
2127	case PGMPAGETYPE_ROM:
2128	case PGMPAGETYPE_MMIO:
2129	break;
2130	default:
2131	AssertFailed();
2132
2133	}
2134	} /* for each page */
2135	}
2136
2137	}
2138
2139	/*
2140	* Finish off any pages pending freeing.
2141	*/
2142	if (cPendingPages)
2143	{
2144	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2145	AssertLogRelRCReturn(rc, rc);
2146	}
2147	GMMR3FreePagesCleanup(pReq);
2148	return VINF_SUCCESS;
2149	}
2150
2151
2152	/**
2153	* Frees all RAM during VM termination
2154	*
2155	* ASSUMES that the caller owns the PGM lock.
2156	*
2157	* @returns VBox status code.
2158	* @param pVM The cross context VM structure.
2159	*/
2160	int pgmR3PhysRamTerm(PVM pVM)
2161	{
2162	PGM_LOCK_ASSERT_OWNER(pVM);
2163
2164	/* Reset the memory balloon. */
2165	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2166	AssertRC(rc);
2167
2168	#ifdef VBOX_WITH_PAGE_SHARING
2169	/*
2170	* Clear all registered shared modules.
2171	*/
2172	pgmR3PhysAssertSharedPageChecksums(pVM);
2173	rc = GMMR3ResetSharedModules(pVM);
2174	AssertRC(rc);
2175
2176	/*
2177	* Flush the handy pages updates to make sure no shared pages are hiding
2178	* in there. (Not unlikely if the VM shuts down, apparently.)
2179	*/
2180	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2181	#endif
2182
2183	/*
2184	* We batch up pages that should be freed instead of calling GMM for
2185	* each and every one of them.
2186	*/
2187	uint32_t cPendingPages = 0;
2188	PGMMFREEPAGESREQ pReq;
2189	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2190	AssertLogRelRCReturn(rc, rc);
2191
2192	/*
2193	* Walk the ram ranges.
2194	*/
2195	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2196	{
2197	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2198	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2199
2200	while (iPage-- > 0)
2201	{
2202	PPGMPAGE pPage = &pRam->aPages[iPage];
2203	switch (PGM_PAGE_GET_TYPE(pPage))
2204	{
2205	case PGMPAGETYPE_RAM:
2206	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2207	/** @todo change this to explicitly free private pages here. */
2208	if (PGM_PAGE_IS_SHARED(pPage))
2209	{
2210	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2211	PGMPAGETYPE_RAM);
2212	AssertLogRelRCReturn(rc, rc);
2213	}
2214	break;
2215
2216	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2217	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2218	case PGMPAGETYPE_MMIO2:
2219	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2220	case PGMPAGETYPE_ROM:
2221	case PGMPAGETYPE_MMIO:
2222	break;
2223	default:
2224	AssertFailed();
2225	}
2226	} /* for each page */
2227	}
2228
2229	/*
2230	* Finish off any pages pending freeing.
2231	*/
2232	if (cPendingPages)
2233	{
2234	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2235	AssertLogRelRCReturn(rc, rc);
2236	}
2237	GMMR3FreePagesCleanup(pReq);
2238	return VINF_SUCCESS;
2239	}
2240
2241
2242
2243	/*********************************************************************************************************************************
2244	* MMIO *
2245	*********************************************************************************************************************************/
2246
2247	/**
2248	* This is the interface IOM is using to register an MMIO region.
2249	*
2250	* It will check for conflicts and ensure that a RAM range structure
2251	* is present before calling the PGMR3HandlerPhysicalRegister API to
2252	* register the callbacks.
2253	*
2254	* @returns VBox status code.
2255	*
2256	* @param pVM The cross context VM structure.
2257	* @param GCPhys The start of the MMIO region.
2258	* @param cb The size of the MMIO region.
2259	* @param hType The physical access handler type registration.
2260	* @param pvUserR3 The user argument for R3.
2261	* @param pvUserR0 The user argument for R0.
2262	* @param pvUserRC The user argument for RC.
2263	* @param pszDesc The description of the MMIO region.
2264	*/
2265	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2266	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2267	{
2268	/*
2269	* Assert on some assumption.
2270	*/
2271	VM_ASSERT_EMT(pVM);
2272	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2273	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2274	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2275	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2276	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2277
2278	int rc = PGM_LOCK(pVM);
2279	AssertRCReturn(rc, rc);
2280
2281	/*
2282	* Make sure there's a RAM range structure for the region.
2283	*/
2284	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2285	bool fRamExists = false;
2286	PPGMRAMRANGE pRamPrev = NULL;
2287	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2288	while (pRam && GCPhysLast >= pRam->GCPhys)
2289	{
2290	if ( GCPhysLast >= pRam->GCPhys
2291	&& GCPhys <= pRam->GCPhysLast)
2292	{
2293	/* Simplification: all within the same range. */
2294	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2295	&& GCPhysLast <= pRam->GCPhysLast,
2296	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2297	GCPhys, GCPhysLast, pszDesc,
2298	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2299	PGM_UNLOCK(pVM),
2300	VERR_PGM_RAM_CONFLICT);
2301
2302	/* Check that it's all RAM or MMIO pages. */
2303	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2304	uint32_t cLeft = cb >> PAGE_SHIFT;
2305	while (cLeft-- > 0)
2306	{
2307	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2308	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2309	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2310	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2311	PGM_UNLOCK(pVM),
2312	VERR_PGM_RAM_CONFLICT);
2313	pPage++;
2314	}
2315
2316	/* Looks good. */
2317	fRamExists = true;
2318	break;
2319	}
2320
2321	/* next */
2322	pRamPrev = pRam;
2323	pRam = pRam->pNextR3;
2324	}
2325	PPGMRAMRANGE pNew;
2326	if (fRamExists)
2327	{
2328	pNew = NULL;
2329
2330	/*
2331	* Make all the pages in the range MMIO/ZERO pages, freeing any
2332	* RAM pages currently mapped here. This might not be 100% correct
2333	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2334	*/
2335	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, NULL);
2336	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
2337
2338	/* Force a PGM pool flush as guest ram references have been changed. */
2339	/** @todo not entirely SMP safe; assuming for now the guest takes
2340	* care of this internally (not touch mapped mmio while changing the
2341	* mapping). */
2342	PVMCPU pVCpu = VMMGetCpu(pVM);
2343	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2344	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2345	}
2346	else
2347	{
2348	/*
2349	* No RAM range, insert an ad hoc one.
2350	*
2351	* Note that we don't have to tell REM about this range because
2352	* PGMHandlerPhysicalRegisterEx will do that for us.
2353	*/
2354	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2355
2356	/* Alloc. */
2357	const uint32_t cPages = cb >> PAGE_SHIFT;
2358	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
2359	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2360	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), PGM_UNLOCK(pVM), rc);
2361
2362	#ifdef VBOX_WITH_NATIVE_NEM
2363	/* Notify NEM. */
2364	uint8_t u2State = 0; /* (must have valid state as there can't be anything to preserve) */
2365	if (VM_IS_NEM_ENABLED(pVM))
2366	{
2367	rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, cPages << PAGE_SHIFT, 0 /fFlags/, NULL, NULL,
2368	&u2State, &pNew->uNemRange);
2369	AssertLogRelRCReturnStmt(rc, MMHyperFree(pVM, pNew), rc);
2370	}
2371	#endif
2372
2373	/* Initialize the range. */
2374	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2375	pNew->GCPhys = GCPhys;
2376	pNew->GCPhysLast = GCPhysLast;
2377	pNew->cb = cb;
2378	pNew->pszDesc = pszDesc;
2379	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2380	pNew->pvR3 = NULL;
2381	pNew->paLSPages = NULL;
2382
2383	uint32_t iPage = cPages;
2384	while (iPage-- > 0)
2385	{
2386	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2387	#ifdef VBOX_WITH_NATIVE_NEM
2388	PGM_PAGE_SET_NEM_STATE(&pNew->aPages[iPage], u2State);
2389	#endif
2390	}
2391	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2392
2393	/* update the page count stats. */
2394	pVM->pgm.s.cPureMmioPages += cPages;
2395	pVM->pgm.s.cAllPages += cPages;
2396
2397	/* link it */
2398	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2399	}
2400
2401	/*
2402	* Register the access handler.
2403	*/
2404	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2405	if (RT_SUCCESS(rc))
2406	{
2407	#ifdef VBOX_WITH_NATIVE_NEM
2408	/* Late NEM notification. */
2409	if (VM_IS_NEM_ENABLED(pVM))
2410	{
2411	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
2412	rc = NEMR3NotifyPhysMmioExMapLate(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify,
2413	fRamExists ? (uint8_t *)pRam->pvR3 + (uintptr_t)(GCPhys - pRam->GCPhys) : NULL,
2414	NULL, !fRamExists ? &pRam->uNemRange : NULL);
2415	AssertLogRelRCReturn(rc, rc);
2416	}
2417	#endif
2418	}
2419	/** @todo the phys handler failure handling isn't complete, esp. wrt NEM. */
2420	else if (!fRamExists)
2421	{
2422	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2423	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2424
2425	/* remove the ad hoc range. */
2426	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2427	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2428	MMHyperFree(pVM, pRam);
2429	}
2430	pgmPhysInvalidatePageMapTLB(pVM);
2431
2432	PGM_UNLOCK(pVM);
2433	return rc;
2434	}
2435
2436
2437	/**
2438	* This is the interface IOM is using to register an MMIO region.
2439	*
2440	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2441	* any ad hoc PGMRAMRANGE left behind.
2442	*
2443	* @returns VBox status code.
2444	* @param pVM The cross context VM structure.
2445	* @param GCPhys The start of the MMIO region.
2446	* @param cb The size of the MMIO region.
2447	*/
2448	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2449	{
2450	VM_ASSERT_EMT(pVM);
2451
2452	int rc = PGM_LOCK(pVM);
2453	AssertRCReturn(rc, rc);
2454
2455	/*
2456	* First deregister the handler, then check if we should remove the ram range.
2457	*/
2458	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2459	if (RT_SUCCESS(rc))
2460	{
2461	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2462	PPGMRAMRANGE pRamPrev = NULL;
2463	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2464	while (pRam && GCPhysLast >= pRam->GCPhys)
2465	{
2466	/** @todo We're being a bit too careful here. rewrite. */
2467	if ( GCPhysLast == pRam->GCPhysLast
2468	&& GCPhys == pRam->GCPhys)
2469	{
2470	Assert(pRam->cb == cb);
2471
2472	/*
2473	* See if all the pages are dead MMIO pages.
2474	*/
2475	uint32_t const cPages = cb >> PAGE_SHIFT;
2476	bool fAllMMIO = true;
2477	uint32_t iPage = 0;
2478	uint32_t cLeft = cPages;
2479	while (cLeft-- > 0)
2480	{
2481	PPGMPAGE pPage = &pRam->aPages[iPage];
2482	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2483	/\|\| not-out-of-action later /)
2484	{
2485	fAllMMIO = false;
2486	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2487	break;
2488	}
2489	Assert( PGM_PAGE_IS_ZERO(pPage)
2490	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2491	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2492	pPage++;
2493	}
2494	if (fAllMMIO)
2495	{
2496	/*
2497	* Ad-hoc range, unlink and free it.
2498	*/
2499	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2500	GCPhys, GCPhysLast, pRam->pszDesc));
2501	/** @todo check the ad-hoc flags? */
2502
2503	#ifdef VBOX_WITH_NATIVE_NEM
2504	if (VM_IS_NEM_ENABLED(pVM)) /* Notify REM before we unlink the range. */
2505	{
2506	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhys, GCPhysLast - GCPhys + 1, 0 /fFlags/, NULL, NULL, NULL);
2507	AssertLogRelRCReturn(rc, rc);
2508	}
2509	#endif
2510
2511	pVM->pgm.s.cAllPages -= cPages;
2512	pVM->pgm.s.cPureMmioPages -= cPages;
2513
2514	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2515	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2516	MMHyperFree(pVM, pRam);
2517	break;
2518	}
2519	}
2520
2521	/*
2522	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2523	*/
2524	if ( GCPhysLast >= pRam->GCPhys
2525	&& GCPhys <= pRam->GCPhysLast)
2526	{
2527	Assert(GCPhys >= pRam->GCPhys);
2528	Assert(GCPhysLast <= pRam->GCPhysLast);
2529
2530	/*
2531	* Turn the pages back into RAM pages.
2532	*/
2533	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2534	uint32_t cLeft = cb >> PAGE_SHIFT;
2535	while (cLeft--)
2536	{
2537	PPGMPAGE pPage = &pRam->aPages[iPage];
2538	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2539	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2540	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2541	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2542	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2543	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2544	iPage++;
2545	}
2546
2547	#ifdef VBOX_WITH_NATIVE_NEM
2548	/* Notify REM (failure will probably leave things in a non-working state). */
2549	if (VM_IS_NEM_ENABLED(pVM))
2550	{
2551	uint8_t u2State = UINT8_MAX;
2552	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhys, GCPhysLast - GCPhys + 1, NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
2553	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL,
2554	NULL, &u2State);
2555	AssertLogRelRCReturn(rc, rc);
2556	if (u2State != UINT8_MAX)
2557	pgmPhysSetNemStateForPages(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT],
2558	cb >> PAGE_SHIFT, u2State);
2559	}
2560	#endif
2561	break;
2562	}
2563
2564	/* next */
2565	pRamPrev = pRam;
2566	pRam = pRam->pNextR3;
2567	}
2568	}
2569
2570	/* Force a PGM pool flush as guest ram references have been changed. */
2571	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2572	* this internally (not touch mapped mmio while changing the mapping). */
2573	PVMCPU pVCpu = VMMGetCpu(pVM);
2574	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2575	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2576
2577	pgmPhysInvalidatePageMapTLB(pVM);
2578	pgmPhysInvalidRamRangeTlbs(pVM);
2579	PGM_UNLOCK(pVM);
2580	return rc;
2581	}
2582
2583
2584
2585	/*********************************************************************************************************************************
2586	* MMIO2 *
2587	*********************************************************************************************************************************/
2588
2589	/**
2590	* Locate a MMIO2 range.
2591	*
2592	* @returns Pointer to the MMIO2 range.
2593	* @param pVM The cross context VM structure.
2594	* @param pDevIns The device instance owning the region.
2595	* @param iSubDev The sub-device number.
2596	* @param iRegion The region.
2597	* @param hMmio2 Handle to look up. If NIL, use the @a iSubDev and
2598	* @a iRegion.
2599	*/
2600	DECLINLINE(PPGMREGMMIO2RANGE) pgmR3PhysMmio2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev,
2601	uint32_t iRegion, PGMMMIO2HANDLE hMmio2)
2602	{
2603	if (hMmio2 != NIL_PGMMMIO2HANDLE)
2604	{
2605	if (hMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3) && hMmio2 != 0)
2606	{
2607	PPGMREGMMIO2RANGE pCur = pVM->pgm.s.apMmio2RangesR3[hMmio2 - 1];
2608	if (pCur && pCur->pDevInsR3 == pDevIns)
2609	{
2610	Assert(pCur->idMmio2 == hMmio2);
2611	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, NULL);
2612	return pCur;
2613	}
2614	Assert(!pCur);
2615	}
2616	for (PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2617	if (pCur->idMmio2 == hMmio2)
2618	{
2619	AssertBreak(pCur->pDevInsR3 == pDevIns);
2620	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, NULL);
2621	return pCur;
2622	}
2623	}
2624	else
2625	{
2626	/*
2627	* Search the list. There shouldn't be many entries.
2628	*/
2629	/** @todo Optimize this lookup! There may now be many entries and it'll
2630	* become really slow when doing MMR3HyperMapMMIO2 and similar. */
2631	for (PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2632	if ( pCur->pDevInsR3 == pDevIns
2633	&& pCur->iRegion == iRegion
2634	&& pCur->iSubDev == iSubDev)
2635	return pCur;
2636	}
2637	return NULL;
2638	}
2639
2640
2641	/**
2642	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking and PGMR3PhysMmio2Map.
2643	*/
2644	static int pgmR3PhysMmio2EnableDirtyPageTracing(PVM pVM, PPGMREGMMIO2RANGE pFirstMmio2)
2645	{
2646	int rc = VINF_SUCCESS;
2647	for (PPGMREGMMIO2RANGE pCurMmio2 = pFirstMmio2; pCurMmio2; pCurMmio2 = pCurMmio2->pNextR3)
2648	{
2649	Assert(!(pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_IS_TRACKING));
2650	int rc2 = pgmHandlerPhysicalExRegister(pVM, pCurMmio2->pPhysHandlerR3, pCurMmio2->RamRange.GCPhys,
2651	pCurMmio2->RamRange.GCPhysLast);
2652	AssertLogRelMsgRC(rc2, ("%#RGp-%#RGp %s failed -> %Rrc\n", pCurMmio2->RamRange.GCPhys, pCurMmio2->RamRange.GCPhysLast,
2653	pCurMmio2->RamRange.pszDesc, rc2));
2654	if (RT_SUCCESS(rc2))
2655	pCurMmio2->fFlags \|= PGMREGMMIO2RANGE_F_IS_TRACKING;
2656	else if (RT_SUCCESS(rc))
2657	rc = rc2;
2658	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2659	return rc;
2660	}
2661	AssertFailed();
2662	return rc;
2663	}
2664
2665
2666	/**
2667	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking and PGMR3PhysMmio2Unmap.
2668	*/
2669	static int pgmR3PhysMmio2DisableDirtyPageTracing(PVM pVM, PPGMREGMMIO2RANGE pFirstMmio2)
2670	{
2671	for (PPGMREGMMIO2RANGE pCurMmio2 = pFirstMmio2; pCurMmio2; pCurMmio2 = pCurMmio2->pNextR3)
2672	{
2673	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_IS_TRACKING)
2674	{
2675	int rc2 = pgmHandlerPhysicalExDeregister(pVM, pCurMmio2->pPhysHandlerR3);
2676	AssertLogRelMsgRC(rc2, ("%#RGp-%#RGp %s failed -> %Rrc\n", pCurMmio2->RamRange.GCPhys, pCurMmio2->RamRange.GCPhysLast,
2677	pCurMmio2->RamRange.pszDesc, rc2));
2678	pCurMmio2->fFlags &= ~PGMREGMMIO2RANGE_F_IS_TRACKING;
2679	}
2680	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2681	return VINF_SUCCESS;
2682	}
2683	AssertFailed();
2684	return VINF_SUCCESS;
2685
2686	}
2687
2688
2689	/**
2690	* Calculates the number of chunks
2691	*
2692	* @returns Number of registration chunk needed.
2693	* @param pVM The cross context VM structure.
2694	* @param cb The size of the MMIO/MMIO2 range.
2695	* @param pcPagesPerChunk Where to return the number of pages tracked by each
2696	* chunk. Optional.
2697	* @param pcbChunk Where to return the guest mapping size for a chunk.
2698	*/
2699	static uint16_t pgmR3PhysMmio2CalcChunkCount(PVM pVM, RTGCPHYS cb, uint32_t pcPagesPerChunk, uint32_t pcbChunk)
2700	{
2701	RT_NOREF_PV(pVM); /* without raw mode */
2702
2703	/*
2704	* This is the same calculation as PGMR3PhysRegisterRam does, except we'll be
2705	* needing a few bytes extra the PGMREGMMIO2RANGE structure.
2706	*
2707	* Note! In additions, we've got a 24 bit sub-page range for MMIO2 ranges, leaving
2708	* us with an absolute maximum of 16777215 pages per chunk (close to 64 GB).
2709	*
2710	* P.S. If we want to include a dirty bitmap, we'd have to drop down to 1040384 pages.
2711	*/
2712	uint32_t cbChunk = 16U*_1M;
2713	uint32_t cPagesPerChunk = 1048000; /* max ~1048059 */
2714	Assert(cPagesPerChunk / 64 * 64 == cPagesPerChunk); /* (NEM requirement) */
2715	AssertCompile(sizeof(PGMREGMMIO2RANGE) + sizeof(PGMPAGE) * 1048000 < 16U_1M - PAGE_SIZE 2);
2716	AssertRelease(cPagesPerChunk <= PGM_MMIO2_MAX_PAGE_COUNT); /* See above note. */
2717	AssertRelease(RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
2718	if (pcbChunk)
2719	*pcbChunk = cbChunk;
2720	if (pcPagesPerChunk)
2721	*pcPagesPerChunk = cPagesPerChunk;
2722
2723	/* Calc the number of chunks we need. */
2724	RTGCPHYS const cPages = cb >> X86_PAGE_SHIFT;
2725	uint16_t cChunks = (uint16_t)((cPages + cPagesPerChunk - 1) / cPagesPerChunk);
2726	AssertRelease((RTGCPHYS)cChunks * cPagesPerChunk >= cPages);
2727	return cChunks;
2728	}
2729
2730
2731	/**
2732	* Worker for PGMR3PhysMMIO2Register that allocates and the PGMREGMMIO2RANGE
2733	* structures and does basic initialization.
2734	*
2735	* Caller must set type specfic members and initialize the PGMPAGE structures.
2736	*
2737	* This was previously also used by PGMR3PhysMmio2PreRegister, a function for
2738	* pre-registering MMIO that was later (6.1) replaced by a new handle based IOM
2739	* interface. The reference to caller and type above is purely historical.
2740	*
2741	* @returns VBox status code.
2742	* @param pVM The cross context VM structure.
2743	* @param pDevIns The device instance owning the region.
2744	* @param iSubDev The sub-device number (internal PCI config number).
2745	* @param iRegion The region number. If the MMIO2 memory is a PCI
2746	* I/O region this number has to be the number of that
2747	* region. Otherwise it can be any number safe
2748	* UINT8_MAX.
2749	* @param cb The size of the region. Must be page aligned.
2750	* @param fFlags PGMPHYS_MMIO2_FLAGS_XXX.
2751	* @param idMmio2 The MMIO2 ID for the first chunk.
2752	* @param pszDesc The description.
2753	* @param ppHeadRet Where to return the pointer to the first
2754	* registration chunk.
2755	*
2756	* @thread EMT
2757	*/
2758	static int pgmR3PhysMmio2Create(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags,
2759	uint8_t idMmio2, const char pszDesc, PPGMREGMMIO2RANGE ppHeadRet)
2760	{
2761	/*
2762	* Figure out how many chunks we need and of which size.
2763	*/
2764	uint32_t cPagesPerChunk;
2765	uint16_t cChunks = pgmR3PhysMmio2CalcChunkCount(pVM, cb, &cPagesPerChunk, NULL);
2766	AssertReturn(cChunks, VERR_PGM_PHYS_MMIO_EX_IPE);
2767
2768	/*
2769	* Allocate the chunks.
2770	*/
2771	PPGMREGMMIO2RANGE *ppNext = ppHeadRet;
2772	*ppNext = NULL;
2773
2774	int rc = VINF_SUCCESS;
2775	uint32_t cPagesLeft = cb >> X86_PAGE_SHIFT;
2776	for (uint16_t iChunk = 0; iChunk < cChunks && RT_SUCCESS(rc); iChunk++, idMmio2++)
2777	{
2778	/*
2779	* We currently do a single RAM range for the whole thing. This will
2780	* probably have to change once someone needs really large MMIO regions,
2781	* as we will be running into SUPR3PageAllocEx limitations and such.
2782	*/
2783	const uint32_t cPagesTrackedByChunk = RT_MIN(cPagesLeft, cPagesPerChunk);
2784	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPagesTrackedByChunk]);
2785	PPGMREGMMIO2RANGE pNew = NULL;
2786	if ( iChunk + 1 < cChunks
2787	\|\| cbRange >= _1M)
2788	{
2789	/*
2790	* Allocate memory for the registration structure.
2791	*/
2792	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2793	size_t const cbChunk = (1 + cChunkPages + 1) << PAGE_SHIFT;
2794	AssertLogRelBreakStmt(cbChunk == (uint32_t)cbChunk, rc = VERR_OUT_OF_RANGE);
2795	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
2796	AssertBreakStmt(paChunkPages, rc = VERR_NO_TMP_MEMORY);
2797	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
2798	void *pvChunk = NULL;
2799	rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
2800	AssertLogRelMsgRCBreakStmt(rc, ("rc=%Rrc, cChunkPages=%#zx\n", rc, cChunkPages), RTMemTmpFree(paChunkPages));
2801
2802	Assert(R0PtrChunk != NIL_RTR0PTR);
2803	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
2804
2805	pNew = (PPGMREGMMIO2RANGE)pvChunk;
2806	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_FLOATING;
2807	pNew->RamRange.pSelfR0 = R0PtrChunk + RT_UOFFSETOF(PGMREGMMIO2RANGE, RamRange);
2808
2809	RTMemTmpFree(paChunkPages);
2810	}
2811	/*
2812	* Not so big, do a one time hyper allocation.
2813	*/
2814	else
2815	{
2816	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2817	AssertLogRelMsgRCBreak(rc, ("cbRange=%zu\n", cbRange));
2818
2819	/*
2820	* Initialize allocation specific items.
2821	*/
2822	//pNew->RamRange.fFlags = 0;
2823	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2824	}
2825
2826	/*
2827	* Initialize the registration structure (caller does specific bits).
2828	*/
2829	pNew->pDevInsR3 = pDevIns;
2830	//pNew->pvR3 = NULL;
2831	//pNew->pNext = NULL;
2832	if (iChunk == 0)
2833	pNew->fFlags \|= PGMREGMMIO2RANGE_F_FIRST_CHUNK;
2834	if (iChunk + 1 == cChunks)
2835	pNew->fFlags \|= PGMREGMMIO2RANGE_F_LAST_CHUNK;
2836	if (fFlags & PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES)
2837	pNew->fFlags \|= PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES;
2838	pNew->iSubDev = iSubDev;
2839	pNew->iRegion = iRegion;
2840	pNew->idSavedState = UINT8_MAX;
2841	pNew->idMmio2 = idMmio2;
2842	//pNew->pPhysHandlerR3 = NULL;
2843	//pNew->paLSPages = NULL;
2844	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2845	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2846	pNew->RamRange.pszDesc = pszDesc;
2847	pNew->RamRange.cb = pNew->cbReal = (RTGCPHYS)cPagesTrackedByChunk << X86_PAGE_SHIFT;
2848	pNew->RamRange.fFlags \|= PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX;
2849	pNew->RamRange.uNemRange = UINT32_MAX;
2850	//pNew->RamRange.pvR3 = NULL;
2851	//pNew->RamRange.paLSPages = NULL;
2852
2853	*ppNext = pNew;
2854	ASMCompilerBarrier();
2855	cPagesLeft -= cPagesTrackedByChunk;
2856	ppNext = &pNew->pNextR3;
2857
2858	/*
2859	* Pre-allocate a handler if we're tracking dirty pages, unless NEM takes care of this.
2860	*/
2861	if ( (fFlags & PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES)
2862	#ifdef VBOX_WITH_PGM_NEM_MODE
2863	&& !NEMR3IsMmio2DirtyPageTrackingSupported(pVM)
2864	#endif
2865	)
2866
2867	{
2868	rc = pgmHandlerPhysicalExCreate(pVM, pVM->pgm.s.hMmio2DirtyPhysHandlerType,
2869	(RTR3PTR)(uintptr_t)idMmio2, idMmio2, idMmio2, pszDesc, &pNew->pPhysHandlerR3);
2870	AssertLogRelMsgRCBreak(rc, ("idMmio2=%zu\n", idMmio2));
2871	}
2872	}
2873	Assert(cPagesLeft == 0);
2874
2875	if (RT_SUCCESS(rc))
2876	{
2877	Assert((*ppHeadRet)->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
2878	return VINF_SUCCESS;
2879	}
2880
2881	/*
2882	* Free floating ranges.
2883	*/
2884	while (*ppHeadRet)
2885	{
2886	PPGMREGMMIO2RANGE pFree = *ppHeadRet;
2887	*ppHeadRet = pFree->pNextR3;
2888
2889	if (pFree->pPhysHandlerR3)
2890	{
2891	pgmHandlerPhysicalExDestroy(pVM, pFree->pPhysHandlerR3);
2892	pFree->pPhysHandlerR3 = NULL;
2893	}
2894
2895	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
2896	{
2897	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
2898	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2899	SUPR3PageFreeEx(pFree, cChunkPages);
2900	}
2901	}
2902
2903	return rc;
2904	}
2905
2906
2907	/**
2908	* Common worker PGMR3PhysMmio2PreRegister & PGMR3PhysMMIO2Register that links a
2909	* complete registration entry into the lists and lookup tables.
2910	*
2911	* @param pVM The cross context VM structure.
2912	* @param pNew The new MMIO / MMIO2 registration to link.
2913	*/
2914	static void pgmR3PhysMmio2Link(PVM pVM, PPGMREGMMIO2RANGE pNew)
2915	{
2916	Assert(pNew->idMmio2 != UINT8_MAX);
2917
2918	/*
2919	* Link it into the list (order doesn't matter, so insert it at the head).
2920	*
2921	* Note! The range we're linking may consist of multiple chunks, so we
2922	* have to find the last one.
2923	*/
2924	PPGMREGMMIO2RANGE pLast = pNew;
2925	for (pLast = pNew; ; pLast = pLast->pNextR3)
2926	{
2927	if (pLast->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2928	break;
2929	Assert(pLast->pNextR3);
2930	Assert(pLast->pNextR3->pDevInsR3 == pNew->pDevInsR3);
2931	Assert(pLast->pNextR3->iSubDev == pNew->iSubDev);
2932	Assert(pLast->pNextR3->iRegion == pNew->iRegion);
2933	Assert(pLast->pNextR3->idMmio2 == pLast->idMmio2 + 1);
2934	}
2935
2936	PGM_LOCK_VOID(pVM);
2937
2938	/* Link in the chain of ranges at the head of the list. */
2939	pLast->pNextR3 = pVM->pgm.s.pRegMmioRangesR3;
2940	pVM->pgm.s.pRegMmioRangesR3 = pNew;
2941
2942	/* Insert the MMIO2 range/page IDs. */
2943	uint8_t idMmio2 = pNew->idMmio2;
2944	for (;;)
2945	{
2946	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
2947	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
2948	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
2949	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = pNew->RamRange.pSelfR0 - RT_UOFFSETOF(PGMREGMMIO2RANGE, RamRange);
2950	if (pNew->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2951	break;
2952	pNew = pNew->pNextR3;
2953	idMmio2++;
2954	}
2955
2956	pgmPhysInvalidatePageMapTLB(pVM);
2957	PGM_UNLOCK(pVM);
2958	}
2959
2960
2961	/**
2962	* Allocate and register an MMIO2 region.
2963	*
2964	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2965	* associated with a device. It is also non-shared memory with a permanent
2966	* ring-3 mapping and page backing (presently).
2967	*
2968	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
2969	* the VM, in which case we'll drop the base memory pages. Presently we will
2970	* make no attempt to preserve anything that happens to be present in the base
2971	* memory that is replaced, this is of course incorrect but it's too much
2972	* effort.
2973	*
2974	* @returns VBox status code.
2975	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2976	* memory.
2977	* @retval VERR_ALREADY_EXISTS if the region already exists.
2978	*
2979	* @param pVM The cross context VM structure.
2980	* @param pDevIns The device instance owning the region.
2981	* @param iSubDev The sub-device number.
2982	* @param iRegion The region number. If the MMIO2 memory is a PCI
2983	* I/O region this number has to be the number of that
2984	* region. Otherwise it can be any number save
2985	* UINT8_MAX.
2986	* @param cb The size of the region. Must be page aligned.
2987	* @param fFlags Reserved for future use, must be zero.
2988	* @param pszDesc The description.
2989	* @param ppv Where to store the pointer to the ring-3 mapping of
2990	* the memory.
2991	* @param phRegion Where to return the MMIO2 region handle. Optional.
2992	* @thread EMT
2993	*/
2994	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2995	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion)
2996	{
2997	/*
2998	* Validate input.
2999	*/
3000	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
3001	*ppv = NULL;
3002	if (phRegion)
3003	{
3004	AssertPtrReturn(phRegion, VERR_INVALID_POINTER);
3005	*phRegion = NIL_PGMMMIO2HANDLE;
3006	}
3007	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3008	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3009	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3010	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3011	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3012	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3013	AssertReturn(pgmR3PhysMmio2Find(pVM, pDevIns, iSubDev, iRegion, NIL_PGMMMIO2HANDLE) == NULL, VERR_ALREADY_EXISTS);
3014	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3015	AssertReturn(cb, VERR_INVALID_PARAMETER);
3016	AssertReturn(!(fFlags & ~PGMPHYS_MMIO2_FLAGS_VALID_MASK), VERR_INVALID_FLAGS);
3017
3018	const uint32_t cPages = cb >> PAGE_SHIFT;
3019	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
3020	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3021	AssertLogRelReturn(cPages <= PGM_MMIO2_MAX_PAGE_COUNT, VERR_OUT_OF_RANGE);
3022
3023	/*
3024	* For the 2nd+ instance, mangle the description string so it's unique.
3025	*/
3026	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3027	{
3028	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3029	if (!pszDesc)
3030	return VERR_NO_MEMORY;
3031	}
3032
3033	/*
3034	* Allocate an MMIO2 range ID (not freed on failure).
3035	*
3036	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID, so
3037	* the IDs goes from 1 thru PGM_MMIO2_MAX_RANGES.
3038	*/
3039	unsigned cChunks = pgmR3PhysMmio2CalcChunkCount(pVM, cb, NULL, NULL);
3040
3041	PGM_LOCK_VOID(pVM);
3042	AssertCompile(PGM_MMIO2_MAX_RANGES < 255);
3043	uint8_t const idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
3044	unsigned const cNewMmio2Regions = pVM->pgm.s.cMmio2Regions + cChunks;
3045	if (cNewMmio2Regions > PGM_MMIO2_MAX_RANGES)
3046	{
3047	PGM_UNLOCK(pVM);
3048	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
3049	}
3050	pVM->pgm.s.cMmio2Regions = cNewMmio2Regions;
3051	PGM_UNLOCK(pVM);
3052
3053	/*
3054	* Try reserve and allocate the backing memory first as this is what is
3055	* most likely to fail.
3056	*/
3057	int rc = VINF_SUCCESS;
3058	#ifdef VBOX_WITH_PGM_NEM_MODE
3059	if (!pVM->pgm.s.fNemMode)
3060	#endif
3061	rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
3062	if (RT_SUCCESS(rc))
3063	{
3064	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
3065	if (RT_SUCCESS(rc))
3066	{
3067	void *pvPages;
3068	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3069	RTR0PTR pvPagesR0 = NIL_RTR0PTR;
3070	#endif
3071
3072	#ifdef VBOX_WITH_PGM_NEM_MODE
3073	if (!pVM->pgm.s.fNemMode)
3074	#endif
3075	{
3076	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3077	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, &pvPagesR0, paPages);
3078	#else
3079	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
3080	#endif
3081	}
3082	#ifdef VBOX_WITH_PGM_NEM_MODE
3083	else
3084	{
3085	rc = SUPR3PageAlloc(cPages, &pvPages);
3086	if (RT_SUCCESS(rc))
3087	for (uint32_t i = 0; i < cPages; i++)
3088	paPages[i].Phys = UINT64_C(0x0000fffffffff000);
3089	}
3090	#endif
3091	if (RT_SUCCESS(rc))
3092	{
3093	memset(pvPages, 0, cPages * PAGE_SIZE);
3094
3095	/*
3096	* Create the registered MMIO range record for it.
3097	*/
3098	PPGMREGMMIO2RANGE pNew;
3099	rc = pgmR3PhysMmio2Create(pVM, pDevIns, iSubDev, iRegion, cb, fFlags, idMmio2, pszDesc, &pNew);
3100	if (RT_SUCCESS(rc))
3101	{
3102	if (phRegion)
3103	phRegion = idMmio2; / The ID of the first chunk. */
3104
3105	uint32_t iSrcPage = 0;
3106	uint8_t pbCurPages = (uint8_t )pvPages;
3107	for (PPGMREGMMIO2RANGE pCur = pNew; pCur; pCur = pCur->pNextR3)
3108	{
3109	pCur->pvR3 = pbCurPages;
3110	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3111	pCur->pvR0 = pvPagesR0 + (iSrcPage << PAGE_SHIFT);
3112	#endif
3113	pCur->RamRange.pvR3 = pbCurPages;
3114
3115	uint32_t iDstPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3116	while (iDstPage-- > 0)
3117	{
3118	PGM_PAGE_INIT(&pNew->RamRange.aPages[iDstPage],
3119	paPages[iDstPage + iSrcPage].Phys,
3120	PGM_MMIO2_PAGEID_MAKE(idMmio2, iDstPage),
3121	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
3122	}
3123
3124	/* advance. */
3125	iSrcPage += pCur->RamRange.cb >> X86_PAGE_SHIFT;
3126	pbCurPages += pCur->RamRange.cb;
3127	}
3128
3129	RTMemTmpFree(paPages);
3130
3131	/*
3132	* Update the page count stats, link the registration and we're done.
3133	*/
3134	pVM->pgm.s.cAllPages += cPages;
3135	pVM->pgm.s.cPrivatePages += cPages;
3136
3137	pgmR3PhysMmio2Link(pVM, pNew);
3138
3139	*ppv = pvPages;
3140	return VINF_SUCCESS;
3141	}
3142
3143	SUPR3PageFreeEx(pvPages, cPages);
3144	}
3145	}
3146	RTMemTmpFree(paPages);
3147	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
3148	}
3149	if (pDevIns->iInstance > 0)
3150	MMR3HeapFree((void *)pszDesc);
3151	return rc;
3152	}
3153
3154
3155	/**
3156	* Deregisters and frees an MMIO2 region.
3157	*
3158	* Any physical access handlers registered for the region must be deregistered
3159	* before calling this function.
3160	*
3161	* @returns VBox status code.
3162	* @param pVM The cross context VM structure.
3163	* @param pDevIns The device instance owning the region.
3164	* @param hMmio2 The MMIO2 handle to deregister, or NIL if all
3165	* regions for the given device is to be deregistered.
3166	*/
3167	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3168	{
3169	/*
3170	* Validate input.
3171	*/
3172	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3173	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3174
3175	/*
3176	* The loop here scanning all registrations will make sure that multi-chunk ranges
3177	* get properly deregistered, though it's original purpose was the wildcard iRegion.
3178	*/
3179	PGM_LOCK_VOID(pVM);
3180	int rc = VINF_SUCCESS;
3181	unsigned cFound = 0;
3182	PPGMREGMMIO2RANGE pPrev = NULL;
3183	PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3;
3184	while (pCur)
3185	{
3186	uint32_t const fFlags = pCur->fFlags;
3187	if ( pCur->pDevInsR3 == pDevIns
3188	&& ( hMmio2 == NIL_PGMMMIO2HANDLE
3189	\|\| pCur->idMmio2 == hMmio2))
3190	{
3191	cFound++;
3192
3193	/*
3194	* Unmap it if it's mapped.
3195	*/
3196	if (fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3197	{
3198	int rc2 = PGMR3PhysMmio2Unmap(pVM, pCur->pDevInsR3, pCur->idMmio2, pCur->RamRange.GCPhys);
3199	AssertRC(rc2);
3200	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3201	rc = rc2;
3202	}
3203
3204	/*
3205	* Unlink it
3206	*/
3207	PPGMREGMMIO2RANGE pNext = pCur->pNextR3;
3208	if (pPrev)
3209	pPrev->pNextR3 = pNext;
3210	else
3211	pVM->pgm.s.pRegMmioRangesR3 = pNext;
3212	pCur->pNextR3 = NULL;
3213
3214	uint8_t idMmio2 = pCur->idMmio2;
3215	Assert(idMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3));
3216	if (idMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3))
3217	{
3218	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
3219	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
3220	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
3221	}
3222
3223	/*
3224	* Free the memory.
3225	*/
3226	uint32_t const cPages = pCur->cbReal >> PAGE_SHIFT;
3227	#ifdef VBOX_WITH_PGM_NEM_MODE
3228	if (!pVM->pgm.s.fNemMode)
3229	#endif
3230	{
3231	int rc2 = SUPR3PageFreeEx(pCur->pvR3, cPages);
3232	AssertRC(rc2);
3233	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3234	rc = rc2;
3235
3236	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
3237	AssertRC(rc2);
3238	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3239	rc = rc2;
3240	}
3241	#ifdef VBOX_WITH_PGM_NEM_MODE
3242	else
3243	{
3244	int rc2 = SUPR3PageFree(pCur->pvR3, cPages);
3245	AssertRC(rc2);
3246	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3247	rc = rc2;
3248	}
3249	#endif
3250
3251	if (pCur->pPhysHandlerR3)
3252	{
3253	pgmHandlerPhysicalExDestroy(pVM, pCur->pPhysHandlerR3);
3254	pCur->pPhysHandlerR3 = NULL;
3255	}
3256
3257	/* we're leaking hyper memory here if done at runtime. */
3258	#ifdef VBOX_STRICT
3259	VMSTATE const enmState = VMR3GetState(pVM);
3260	AssertMsg( enmState == VMSTATE_POWERING_OFF
3261	\|\| enmState == VMSTATE_POWERING_OFF_LS
3262	\|\| enmState == VMSTATE_OFF
3263	\|\| enmState == VMSTATE_OFF_LS
3264	\|\| enmState == VMSTATE_DESTROYING
3265	\|\| enmState == VMSTATE_TERMINATED
3266	\|\| enmState == VMSTATE_CREATING
3267	, ("%s\n", VMR3GetStateName(enmState)));
3268	#endif
3269
3270	if (pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3271	{
3272	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPages]);
3273	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3274	SUPR3PageFreeEx(pCur, cChunkPages);
3275	}
3276	/*else
3277	{
3278	rc = MMHyperFree(pVM, pCur); - does not work, see the alloc call.
3279	AssertRCReturn(rc, rc);
3280	} */
3281
3282
3283	/* update page count stats */
3284	pVM->pgm.s.cAllPages -= cPages;
3285	pVM->pgm.s.cPrivatePages -= cPages;
3286
3287	/* next */
3288	pCur = pNext;
3289	if (hMmio2 != NIL_PGMMMIO2HANDLE)
3290	{
3291	if (fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3292	break;
3293	hMmio2++;
3294	Assert(pCur->idMmio2 == hMmio2);
3295	Assert(pCur->pDevInsR3 == pDevIns);
3296	Assert(!(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK));
3297	}
3298	}
3299	else
3300	{
3301	pPrev = pCur;
3302	pCur = pCur->pNextR3;
3303	}
3304	}
3305	pgmPhysInvalidatePageMapTLB(pVM);
3306	PGM_UNLOCK(pVM);
3307	return !cFound && hMmio2 != NIL_PGMMMIO2HANDLE ? VERR_NOT_FOUND : rc;
3308	}
3309
3310
3311	/**
3312	* Maps a MMIO2 region.
3313	*
3314	* This is typically done when a guest / the bios / state loading changes the
3315	* PCI config. The replacing of base memory has the same restrictions as during
3316	* registration, of course.
3317	*
3318	* @returns VBox status code.
3319	*
3320	* @param pVM The cross context VM structure.
3321	* @param pDevIns The device instance owning the region.
3322	* @param hMmio2 The handle of the region to map.
3323	* @param GCPhys The guest-physical address to be remapped.
3324	*/
3325	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys)
3326	{
3327	/*
3328	* Validate input.
3329	*
3330	* Note! It's safe to walk the MMIO/MMIO2 list since registrations only
3331	* happens during VM construction.
3332	*/
3333	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3334	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3335	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3336	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3337	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3338	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3339
3340	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3341	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3342	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3343
3344	PPGMREGMMIO2RANGE pLastMmio = pFirstMmio;
3345	RTGCPHYS cbRange = 0;
3346	for (;;)
3347	{
3348	AssertReturn(!(pLastMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED), VERR_WRONG_ORDER);
3349	Assert(pLastMmio->RamRange.GCPhys == NIL_RTGCPHYS);
3350	Assert(pLastMmio->RamRange.GCPhysLast == NIL_RTGCPHYS);
3351	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3352	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3353	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3354	cbRange += pLastMmio->RamRange.cb;
3355	if (pLastMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3356	break;
3357	pLastMmio = pLastMmio->pNextR3;
3358	}
3359
3360	RTGCPHYS GCPhysLast = GCPhys + cbRange - 1;
3361	AssertLogRelReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3362
3363	/*
3364	* Find our location in the ram range list, checking for restriction
3365	* we don't bother implementing yet (partially overlapping, multiple
3366	* ram ranges).
3367	*/
3368	PGM_LOCK_VOID(pVM);
3369
3370	AssertReturnStmt(!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED), PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3371
3372	bool fRamExists = false;
3373	PPGMRAMRANGE pRamPrev = NULL;
3374	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3375	while (pRam && GCPhysLast >= pRam->GCPhys)
3376	{
3377	if ( GCPhys <= pRam->GCPhysLast
3378	&& GCPhysLast >= pRam->GCPhys)
3379	{
3380	/* Completely within? */
3381	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
3382	&& GCPhysLast <= pRam->GCPhysLast,
3383	("%RGp-%RGp (MMIOEx/%s) falls partly outside %RGp-%RGp (%s)\n",
3384	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc,
3385	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3386	PGM_UNLOCK(pVM),
3387	VERR_PGM_RAM_CONFLICT);
3388
3389	/* Check that all the pages are RAM pages. */
3390	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3391	uint32_t cPagesLeft = cbRange >> PAGE_SHIFT;
3392	while (cPagesLeft-- > 0)
3393	{
3394	AssertLogRelMsgReturnStmt(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3395	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
3396	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc),
3397	PGM_UNLOCK(pVM),
3398	VERR_PGM_RAM_CONFLICT);
3399	pPage++;
3400	}
3401
3402	/* There can only be one MMIO/MMIO2 chunk matching here! */
3403	AssertLogRelMsgReturnStmt(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK,
3404	("%RGp-%RGp (MMIOEx/%s, flags %#X) consists of multiple chunks whereas the RAM somehow doesn't!\n",
3405	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3406	PGM_UNLOCK(pVM),
3407	VERR_PGM_PHYS_MMIO_EX_IPE);
3408
3409	fRamExists = true;
3410	break;
3411	}
3412
3413	/* next */
3414	pRamPrev = pRam;
3415	pRam = pRam->pNextR3;
3416	}
3417	Log(("PGMR3PhysMmio2Map: %RGp-%RGp fRamExists=%RTbool %s\n", GCPhys, GCPhysLast, fRamExists, pFirstMmio->RamRange.pszDesc));
3418
3419
3420	/*
3421	* Make the changes.
3422	*/
3423	RTGCPHYS GCPhysCur = GCPhys;
3424	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3425	{
3426	pCurMmio->RamRange.GCPhys = GCPhysCur;
3427	pCurMmio->RamRange.GCPhysLast = GCPhysCur + pCurMmio->RamRange.cb - 1;
3428	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3429	{
3430	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3431	break;
3432	}
3433	GCPhysCur += pCurMmio->RamRange.cb;
3434	}
3435
3436	if (fRamExists)
3437	{
3438	/*
3439	* Make all the pages in the range MMIO/ZERO pages, freeing any
3440	* RAM pages currently mapped here. This might not be 100% correct
3441	* for PCI memory, but we're doing the same thing for MMIO2 pages.
3442	*
3443	* We replace these MMIO/ZERO pages with real pages in the MMIO2 case.
3444	*/
3445	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK); /* Only one chunk */
3446	Assert(pFirstMmio->pvR3 == pFirstMmio->RamRange.pvR3);
3447	Assert(pFirstMmio->RamRange.pvR3 != NULL);
3448
3449	#ifdef VBOX_WITH_PGM_NEM_MODE
3450	/* We cannot mix MMIO2 into a RAM range in simplified memory mode because pRam->pvR3 can't point
3451	both at the RAM and MMIO2, so we won't ever write & read from the actual MMIO2 memory if we try. */
3452	AssertLogRelMsgReturn(!pVM->pgm.s.fNemMode, ("%s at %RGp-%RGp\n", pFirstMmio->RamRange.pszDesc, GCPhys, GCPhysLast),
3453	VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
3454	#endif
3455
3456	int rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, pFirstMmio->RamRange.pvR3);
3457	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3458
3459	/* Replace the pages, freeing all present RAM pages. */
3460	PPGMPAGE pPageSrc = &pFirstMmio->RamRange.aPages[0];
3461	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3462	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3463	while (cPagesLeft-- > 0)
3464	{
3465	Assert(PGM_PAGE_IS_MMIO(pPageDst));
3466
3467	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
3468	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
3469	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
3470	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
3471	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
3472	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
3473	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
3474	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
3475	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
3476	/* NEM state is set by pgmR3PhysFreePageRange. */
3477
3478	pVM->pgm.s.cZeroPages--;
3479	GCPhys += PAGE_SIZE;
3480	pPageSrc++;
3481	pPageDst++;
3482	}
3483
3484	/* Flush physical page map TLB. */
3485	pgmPhysInvalidatePageMapTLB(pVM);
3486
3487	/* Force a PGM pool flush as guest ram references have been changed. */
3488	/** @todo not entirely SMP safe; assuming for now the guest takes care of
3489	* this internally (not touch mapped mmio while changing the mapping). */
3490	PVMCPU pVCpu = VMMGetCpu(pVM);
3491	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3492	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3493	}
3494	else
3495	{
3496	/*
3497	* No RAM range, insert the ones prepared during registration.
3498	*/
3499	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3500	{
3501	#ifdef VBOX_WITH_NATIVE_NEM
3502	/* Tell NEM and get the new NEM state for the pages. */
3503	uint8_t u2NemState = 0;
3504	if (VM_IS_NEM_ENABLED(pVM))
3505	{
3506	int rc = NEMR3NotifyPhysMmioExMapEarly(pVM, pCurMmio->RamRange.GCPhys,
3507	pCurMmio->RamRange.GCPhysLast - pCurMmio->RamRange.GCPhys + 1,
3508	NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2
3509	\| (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
3510	? NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES : 0),
3511	NULL /pvRam/, pCurMmio->RamRange.pvR3,
3512	&u2NemState, &pCurMmio->RamRange.uNemRange);
3513	AssertLogRelRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3514	}
3515	#endif
3516
3517	/* Clear the tracking data of pages we're going to reactivate. */
3518	PPGMPAGE pPageSrc = &pCurMmio->RamRange.aPages[0];
3519	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3520	while (cPagesLeft-- > 0)
3521	{
3522	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
3523	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
3524	#ifdef VBOX_WITH_NATIVE_NEM
3525	PGM_PAGE_SET_NEM_STATE(pPageSrc, u2NemState);
3526	#endif
3527	pPageSrc++;
3528	}
3529
3530	/* link in the ram range */
3531	pgmR3PhysLinkRamRange(pVM, &pCurMmio->RamRange, pRamPrev);
3532
3533	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3534	{
3535	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3536	break;
3537	}
3538	pRamPrev = &pCurMmio->RamRange;
3539	}
3540	}
3541
3542	/*
3543	* If the range have dirty page monitoring enabled, enable that.
3544	*
3545	* We ignore failures here for now because if we fail, the whole mapping
3546	* will have to be reversed and we'll end up with nothing at all on the
3547	* screen and a grumpy guest, whereas if we just go on, we'll only have
3548	* visual distortions to gripe about. There will be something in the
3549	* release log.
3550	*/
3551	if ( pFirstMmio->pPhysHandlerR3
3552	&& (pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3553	pgmR3PhysMmio2EnableDirtyPageTracing(pVM, pFirstMmio);
3554
3555	/*
3556	* We're good, set the flags and invalid the mapping TLB.
3557	*/
3558	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3559	{
3560	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_MAPPED;
3561	if (fRamExists)
3562	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_OVERLAPPING;
3563	else
3564	pCurMmio->fFlags &= ~PGMREGMMIO2RANGE_F_OVERLAPPING;
3565	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3566	break;
3567	}
3568	pgmPhysInvalidatePageMapTLB(pVM);
3569
3570	#ifdef VBOX_WITH_NATIVE_NEM
3571	/*
3572	* Late NEM notification.
3573	*/
3574	if (VM_IS_NEM_ENABLED(pVM))
3575	{
3576	int rc;
3577	uint32_t fNemFlags = NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2;
3578	if (pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES)
3579	fNemFlags \|= NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES;
3580	if (fRamExists)
3581	rc = NEMR3NotifyPhysMmioExMapLate(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemFlags \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
3582	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL, pFirstMmio->pvR3,
3583	NULL /puNemRange/);
3584	else
3585	{
3586	rc = VINF_SUCCESS;
3587	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3588	{
3589	rc = NEMR3NotifyPhysMmioExMapLate(pVM, pCurMmio->RamRange.GCPhys, pCurMmio->RamRange.cb, fNemFlags,
3590	NULL, pCurMmio->RamRange.pvR3, &pCurMmio->RamRange.uNemRange);
3591	if ((pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK) \|\| RT_FAILURE(rc))
3592	break;
3593	}
3594	}
3595	AssertLogRelRCReturnStmt(rc, PGMR3PhysMmio2Unmap(pVM, pDevIns, hMmio2, GCPhys); PGM_UNLOCK(pVM), rc);
3596	}
3597	#endif
3598
3599	PGM_UNLOCK(pVM);
3600
3601	return VINF_SUCCESS;
3602	}
3603
3604
3605	/**
3606	* Unmaps an MMIO2 region.
3607	*
3608	* This is typically done when a guest / the bios / state loading changes the
3609	* PCI config. The replacing of base memory has the same restrictions as during
3610	* registration, of course.
3611	*/
3612	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys)
3613	{
3614	/*
3615	* Validate input
3616	*/
3617	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3618	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3619	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3620	if (GCPhys != NIL_RTGCPHYS)
3621	{
3622	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3623	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3624	}
3625
3626	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3627	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3628	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3629
3630	int rc = PGM_LOCK(pVM);
3631	AssertRCReturn(rc, rc);
3632
3633	PPGMREGMMIO2RANGE pLastMmio = pFirstMmio;
3634	RTGCPHYS cbRange = 0;
3635	for (;;)
3636	{
3637	AssertReturnStmt(pLastMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED, PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3638	AssertReturnStmt(pLastMmio->RamRange.GCPhys == GCPhys + cbRange \|\| GCPhys == NIL_RTGCPHYS, PGM_UNLOCK(pVM), VERR_INVALID_PARAMETER);
3639	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3640	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3641	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3642	cbRange += pLastMmio->RamRange.cb;
3643	if (pLastMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3644	break;
3645	pLastMmio = pLastMmio->pNextR3;
3646	}
3647
3648	Log(("PGMR3PhysMmio2Unmap: %RGp-%RGp %s\n",
3649	pFirstMmio->RamRange.GCPhys, pLastMmio->RamRange.GCPhysLast, pFirstMmio->RamRange.pszDesc));
3650
3651	uint16_t const fOldFlags = pFirstMmio->fFlags;
3652	AssertReturnStmt(fOldFlags & PGMREGMMIO2RANGE_F_MAPPED, PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3653
3654	/*
3655	* If monitoring dirty pages, we must deregister the handlers first.
3656	*/
3657	if ( pFirstMmio->pPhysHandlerR3
3658	&& (fOldFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3659	pgmR3PhysMmio2DisableDirtyPageTracing(pVM, pFirstMmio);
3660
3661	/*
3662	* Unmap it.
3663	*/
3664	int rcRet = VINF_SUCCESS;
3665	#ifdef VBOX_WITH_NATIVE_NEM
3666	uint32_t const fNemFlags = NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2
3667	\| (fOldFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
3668	? NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES : 0);
3669	#endif
3670	if (fOldFlags & PGMREGMMIO2RANGE_F_OVERLAPPING)
3671	{
3672	/*
3673	* We've replaced RAM, replace with zero pages.
3674	*
3675	* Note! This is where we might differ a little from a real system, because
3676	* it's likely to just show the RAM pages as they were before the
3677	* MMIO/MMIO2 region was mapped here.
3678	*/
3679	/* Only one chunk allowed when overlapping! */
3680	Assert(fOldFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK);
3681
3682	/* Restore the RAM pages we've replaced. */
3683	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3684	while (pRam->GCPhys > pFirstMmio->RamRange.GCPhysLast)
3685	pRam = pRam->pNextR3;
3686
3687	PPGMPAGE pPageDst = &pRam->aPages[(pFirstMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3688	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3689	pVM->pgm.s.cZeroPages += cPagesLeft; /** @todo not correct for NEM mode */
3690
3691	#ifdef VBOX_WITH_NATIVE_NEM
3692	if (VM_IS_NEM_ENABLED(pVM)) /* Notify NEM. Note! we cannot be here in simple memory mode, see mapping function. */
3693	{
3694	uint8_t u2State = UINT8_MAX;
3695	rc = NEMR3NotifyPhysMmioExUnmap(pVM, pFirstMmio->RamRange.GCPhys, pFirstMmio->RamRange.cb,
3696	fNemFlags \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
3697	pRam->pvR3
3698	? (uint8_t *)pRam->pvR3 + pFirstMmio->RamRange.GCPhys - pRam->GCPhys : NULL,
3699	pFirstMmio->pvR3, &u2State);
3700	AssertRCStmt(rc, rcRet = rc);
3701	if (u2State != UINT8_MAX)
3702	pgmPhysSetNemStateForPages(pPageDst, cPagesLeft, u2State);
3703	}
3704	#endif
3705
3706	while (cPagesLeft-- > 0)
3707	{
3708	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3709	pPageDst++;
3710	}
3711
3712	/* Flush physical page map TLB. */
3713	pgmPhysInvalidatePageMapTLB(pVM);
3714
3715	/* Update range state. */
3716	pFirstMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3717	pFirstMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3718	pFirstMmio->fFlags &= ~(PGMREGMMIO2RANGE_F_OVERLAPPING \| PGMREGMMIO2RANGE_F_MAPPED);
3719	}
3720	else
3721	{
3722	/*
3723	* Unlink the chunks related to the MMIO/MMIO2 region.
3724	*/
3725	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3726	{
3727	#ifdef VBOX_WITH_NATIVE_NEM
3728	if (VM_IS_NEM_ENABLED(pVM)) /* Notify NEM. */
3729	{
3730	uint8_t u2State = UINT8_MAX;
3731	rc = NEMR3NotifyPhysMmioExUnmap(pVM, pCurMmio->RamRange.GCPhys, pCurMmio->RamRange.cb, fNemFlags,
3732	NULL, pCurMmio->pvR3, &u2State);
3733	AssertRCStmt(rc, rcRet = rc);
3734	if (u2State != UINT8_MAX)
3735	pgmPhysSetNemStateForPages(pCurMmio->RamRange.aPages, pCurMmio->RamRange.cb >> PAGE_SHIFT, u2State);
3736	}
3737	#endif
3738	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3739	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3740	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3741	pCurMmio->fFlags &= ~(PGMREGMMIO2RANGE_F_OVERLAPPING \| PGMREGMMIO2RANGE_F_MAPPED);
3742	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3743	break;
3744	}
3745	}
3746
3747	/* Force a PGM pool flush as guest ram references have been changed. */
3748	/** @todo not entirely SMP safe; assuming for now the guest takes care
3749	* of this internally (not touch mapped mmio while changing the
3750	* mapping). */
3751	PVMCPU pVCpu = VMMGetCpu(pVM);
3752	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3753	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3754
3755	pgmPhysInvalidatePageMapTLB(pVM);
3756	pgmPhysInvalidRamRangeTlbs(pVM);
3757
3758	PGM_UNLOCK(pVM);
3759	return rcRet;
3760	}
3761
3762
3763	/**
3764	* Reduces the mapping size of a MMIO2 region.
3765	*
3766	* This is mainly for dealing with old saved states after changing the default
3767	* size of a mapping region. See PGMDevHlpMMIOExReduce and
3768	* PDMPCIDEV::pfnRegionLoadChangeHookR3.
3769	*
3770	* The region must not currently be mapped when making this call. The VM state
3771	* must be state restore or VM construction.
3772	*
3773	* @returns VBox status code.
3774	* @param pVM The cross context VM structure.
3775	* @param pDevIns The device instance owning the region.
3776	* @param hMmio2 The handle of the region to reduce.
3777	* @param cbRegion The new mapping size.
3778	*/
3779	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion)
3780	{
3781	/*
3782	* Validate input
3783	*/
3784	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3785	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3786	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3787	AssertReturn(cbRegion >= X86_PAGE_SIZE, VERR_INVALID_PARAMETER);
3788	AssertReturn(!(cbRegion & X86_PAGE_OFFSET_MASK), VERR_UNSUPPORTED_ALIGNMENT);
3789	VMSTATE enmVmState = VMR3GetState(pVM);
3790	AssertLogRelMsgReturn( enmVmState == VMSTATE_CREATING
3791	\|\| enmVmState == VMSTATE_LOADING,
3792	("enmVmState=%d (%s)\n", enmVmState, VMR3GetStateName(enmVmState)),
3793	VERR_VM_INVALID_VM_STATE);
3794
3795	int rc = PGM_LOCK(pVM);
3796	AssertRCReturn(rc, rc);
3797
3798	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3799	if (pFirstMmio)
3800	{
3801	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3802	if (!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED))
3803	{
3804	/*
3805	* NOTE! Current implementation does not support multiple ranges.
3806	* Implement when there is a real world need and thus a testcase.
3807	*/
3808	AssertLogRelMsgStmt(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK,
3809	("%s: %#x\n", pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3810	rc = VERR_NOT_SUPPORTED);
3811	if (RT_SUCCESS(rc))
3812	{
3813	/*
3814	* Make the change.
3815	*/
3816	Log(("PGMR3PhysMmio2Reduce: %s changes from %RGp bytes (%RGp) to %RGp bytes.\n",
3817	pFirstMmio->RamRange.pszDesc, pFirstMmio->RamRange.cb, pFirstMmio->cbReal, cbRegion));
3818
3819	AssertLogRelMsgStmt(cbRegion <= pFirstMmio->cbReal,
3820	("%s: cbRegion=%#RGp cbReal=%#RGp\n", pFirstMmio->RamRange.pszDesc, cbRegion, pFirstMmio->cbReal),
3821	rc = VERR_OUT_OF_RANGE);
3822	if (RT_SUCCESS(rc))
3823	{
3824	pFirstMmio->RamRange.cb = cbRegion;
3825	}
3826	}
3827	}
3828	else
3829	rc = VERR_WRONG_ORDER;
3830	}
3831	else
3832	rc = VERR_NOT_FOUND;
3833
3834	PGM_UNLOCK(pVM);
3835	return rc;
3836	}
3837
3838
3839	/**
3840	* Validates @a hMmio2, making sure it belongs to @a pDevIns.
3841	*
3842	* @returns VBox status code.
3843	* @param pVM The cross context VM structure.
3844	* @param pDevIns The device which allegedly owns @a hMmio2.
3845	* @param hMmio2 The handle to validate.
3846	*/
3847	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3848	{
3849	/*
3850	* Validate input
3851	*/
3852	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3853	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
3854
3855	/*
3856	* Just do this the simple way. No need for locking as this is only taken at
3857	*/
3858	PGM_LOCK_VOID(pVM);
3859	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3860	PGM_UNLOCK(pVM);
3861	AssertReturn(pFirstMmio, VERR_INVALID_HANDLE);
3862	AssertReturn(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, VERR_INVALID_HANDLE);
3863	return VINF_SUCCESS;
3864	}
3865
3866
3867	/**
3868	* Gets the mapping address of an MMIO2 region.
3869	*
3870	* @returns Mapping address, NIL_RTGCPHYS if not mapped or invalid handle.
3871	*
3872	* @param pVM The cross context VM structure.
3873	* @param pDevIns The device owning the MMIO2 handle.
3874	* @param hMmio2 The region handle.
3875	*/
3876	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3877	{
3878	AssertPtrReturn(pDevIns, NIL_RTGCPHYS);
3879
3880	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3881	AssertReturn(pFirstRegMmio, NIL_RTGCPHYS);
3882
3883	if (pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3884	return pFirstRegMmio->RamRange.GCPhys;
3885	return NIL_RTGCPHYS;
3886	}
3887
3888
3889	/**
3890	* Worker for PGMR3PhysMmio2QueryAndResetDirtyBitmap.
3891	*
3892	* Called holding the PGM lock.
3893	*/
3894	static int pgmR3PhysMmio2QueryAndResetDirtyBitmapLocked(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
3895	void *pvBitmap, size_t cbBitmap)
3896	{
3897	/*
3898	* Continue validation.
3899	*/
3900	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3901	AssertReturn(pFirstRegMmio, VERR_INVALID_HANDLE);
3902	AssertReturn( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
3903	== (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK),
3904	VERR_INVALID_FUNCTION);
3905	AssertReturn(pDevIns == pFirstRegMmio->pDevInsR3, VERR_NOT_OWNER);
3906
3907	RTGCPHYS cbTotal = 0;
3908	uint16_t fTotalDirty = 0;
3909	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio;;)
3910	{
3911	cbTotal += pCur->RamRange.cb; /* Not using cbReal here, because NEM is not in on the creating, only the mapping. */
3912	fTotalDirty \|= pCur->fFlags;
3913	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3914	break;
3915	pCur = pCur->pNextR3;
3916	AssertPtrReturn(pCur, VERR_INTERNAL_ERROR_5);
3917	AssertReturn( (pCur->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
3918	== PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES,
3919	VERR_INTERNAL_ERROR_4);
3920	}
3921	size_t const cbTotalBitmap = RT_ALIGN_T(cbTotal, PAGE_SIZE * 64, RTGCPHYS) / PAGE_SIZE / 8;
3922
3923	if (cbBitmap)
3924	{
3925	AssertPtrReturn(pvBitmap, VERR_INVALID_POINTER);
3926	AssertReturn(RT_ALIGN_P(pvBitmap, sizeof(uint64_t)) == pvBitmap, VERR_INVALID_POINTER);
3927	AssertReturn(cbBitmap == cbTotalBitmap, VERR_INVALID_PARAMETER);
3928	}
3929
3930	/*
3931	* Do the work.
3932	*/
3933	int rc = VINF_SUCCESS;
3934	if (pvBitmap)
3935	{
3936	#ifdef VBOX_WITH_PGM_NEM_MODE
3937	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
3938	{
3939	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
3940	uint8_t pbBitmap = (uint8_t )pvBitmap;
3941	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3942	{
3943	size_t const cbBitmapChunk = pCur->RamRange.cb / PAGE_SIZE / 8;
3944	Assert((RTGCPHYS)cbBitmapChunk * PAGE_SIZE * 8 == pCur->RamRange.cb);
3945	int rc2 = NEMR3PhysMmio2QueryAndResetDirtyBitmap(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb,
3946	pCur->RamRange.uNemRange, pbBitmap, cbBitmapChunk);
3947	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3948	rc = rc2;
3949	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3950	break;
3951	pbBitmap += pCur->RamRange.cb / PAGE_SIZE / 8;
3952	}
3953	}
3954	else
3955	#endif
3956	if (fTotalDirty & PGMREGMMIO2RANGE_F_IS_DIRTY)
3957	{
3958	if ( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3959	== (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3960	{
3961	/*
3962	* Reset each chunk, gathering dirty bits.
3963	*/
3964	RT_BZERO(pvBitmap, cbBitmap); /* simpler for now. */
3965	uint32_t iPageNo = 0;
3966	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3967	{
3968	if (pCur->fFlags & PGMREGMMIO2RANGE_F_IS_DIRTY)
3969	{
3970	int rc2 = pgmHandlerPhysicalResetMmio2WithBitmap(pVM, pCur->RamRange.GCPhys, pvBitmap, iPageNo);
3971	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3972	rc = rc2;
3973	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
3974	}
3975	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3976	break;
3977	iPageNo += pCur->RamRange.cb >> PAGE_SHIFT;
3978	}
3979	}
3980	else
3981	{
3982	/*
3983	* If not mapped or tracking is disabled, we return the
3984	* PGMREGMMIO2RANGE_F_IS_DIRTY status for all pages. We cannot
3985	* get more accurate data than that after unmapping or disabling.
3986	*/
3987	RT_BZERO(pvBitmap, cbBitmap);
3988	uint32_t iPageNo = 0;
3989	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3990	{
3991	if (pCur->fFlags & PGMREGMMIO2RANGE_F_IS_DIRTY)
3992	{
3993	ASMBitSetRange(pvBitmap, iPageNo, iPageNo + (pCur->RamRange.cb >> PAGE_SHIFT));
3994	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
3995	}
3996	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3997	break;
3998	iPageNo += pCur->RamRange.cb >> PAGE_SHIFT;
3999	}
4000	}
4001	}
4002	/*
4003	* No dirty chunks.
4004	*/
4005	else
4006	RT_BZERO(pvBitmap, cbBitmap);
4007	}
4008	/*
4009	* No bitmap. Reset the region if tracking is currently enabled.
4010	*/
4011	else if ( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4012	== (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4013	{
4014	#ifdef VBOX_WITH_PGM_NEM_MODE
4015	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
4016	{
4017	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
4018	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
4019	{
4020	int rc2 = NEMR3PhysMmio2QueryAndResetDirtyBitmap(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb,
4021	pCur->RamRange.uNemRange, NULL, 0);
4022	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4023	rc = rc2;
4024	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4025	break;
4026	}
4027	}
4028	else
4029	#endif
4030	{
4031	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
4032	{
4033	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
4034	int rc2 = PGMHandlerPhysicalReset(pVM, pCur->RamRange.GCPhys);
4035	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4036	rc = rc2;
4037	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4038	break;
4039	}
4040	}
4041	}
4042
4043	return rc;
4044	}
4045
4046
4047	/**
4048	* Queries the dirty page bitmap and resets the monitoring.
4049	*
4050	* The PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag must be specified when
4051	* creating the range for this to work.
4052	*
4053	* @returns VBox status code.
4054	* @retval VERR_INVALID_FUNCTION if not created using
4055	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES.
4056	* @param pVM The cross context VM structure.
4057	* @param pDevIns The device owning the MMIO2 handle.
4058	* @param hMmio2 The region handle.
4059	* @param pvBitmap The output bitmap. Must be 8-byte aligned. Ignored
4060	* when @a cbBitmap is zero.
4061	* @param cbBitmap The size of the bitmap. Must be the size of the whole
4062	* MMIO2 range, rounded up to the nearest 8 bytes.
4063	* When zero only a reset is done.
4064	*/
4065	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
4066	void *pvBitmap, size_t cbBitmap)
4067	{
4068	/*
4069	* Do some basic validation before grapping the PGM lock and continuing.
4070	*/
4071	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
4072	AssertReturn(RT_ALIGN_Z(cbBitmap, sizeof(uint64_t)) == cbBitmap, VERR_INVALID_PARAMETER);
4073	int rc = PGM_LOCK(pVM);
4074	if (RT_SUCCESS(rc))
4075	{
4076	STAM_PROFILE_START(&pVM->pgm.s.StatMmio2QueryAndResetDirtyBitmap, a);
4077	rc = pgmR3PhysMmio2QueryAndResetDirtyBitmapLocked(pVM, pDevIns, hMmio2, pvBitmap, cbBitmap);
4078	STAM_PROFILE_STOP(&pVM->pgm.s.StatMmio2QueryAndResetDirtyBitmap, a);
4079	PGM_UNLOCK(pVM);
4080	}
4081	return rc;
4082	}
4083
4084	/**
4085	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking
4086	*
4087	* Called owning the PGM lock.
4088	*/
4089	static int pgmR3PhysMmio2ControlDirtyPageTrackingLocked(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled)
4090	{
4091	/*
4092	* Continue validation.
4093	*/
4094	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
4095	AssertReturn(pFirstRegMmio, VERR_INVALID_HANDLE);
4096	AssertReturn( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
4097	== (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK)
4098	, VERR_INVALID_FUNCTION);
4099	AssertReturn(pDevIns == pFirstRegMmio->pDevInsR3, VERR_NOT_OWNER);
4100
4101	#ifdef VBOX_WITH_PGM_NEM_MODE
4102	/*
4103	* This is a nop if NEM is responsible for doing the tracking, we simply
4104	* leave the tracking on all the time there.
4105	*/
4106	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
4107	{
4108	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
4109	return VINF_SUCCESS;
4110	}
4111	#endif
4112
4113	/*
4114	* Anyting needing doing?
4115	*/
4116	if (fEnabled != RT_BOOL(pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4117	{
4118	LogFlowFunc(("fEnabled=%RTbool %s\n", fEnabled, pFirstRegMmio->RamRange.pszDesc));
4119
4120	/*
4121	* Update the PGMREGMMIO2RANGE_F_TRACKING_ENABLED flag.
4122	*/
4123	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio;;)
4124	{
4125	if (fEnabled)
4126	pCur->fFlags \|= PGMREGMMIO2RANGE_F_TRACKING_ENABLED;
4127	else
4128	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_TRACKING_ENABLED;
4129	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4130	break;
4131	pCur = pCur->pNextR3;
4132	AssertPtrReturn(pCur, VERR_INTERNAL_ERROR_5);
4133	AssertReturn( (pCur->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
4134	== PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
4135	, VERR_INTERNAL_ERROR_4);
4136	}
4137
4138	/*
4139	* Enable/disable handlers if currently mapped.
4140	*
4141	* We ignore status codes here as we've already changed the flags and
4142	* returning a failure status now would be confusing. Besides, the two
4143	* functions will continue past failures. As argued in the mapping code,
4144	* it's in the release log.
4145	*/
4146	if (pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED)
4147	{
4148	if (fEnabled)
4149	pgmR3PhysMmio2EnableDirtyPageTracing(pVM, pFirstRegMmio);
4150	else
4151	pgmR3PhysMmio2DisableDirtyPageTracing(pVM, pFirstRegMmio);
4152	}
4153	}
4154	else
4155	LogFlowFunc(("fEnabled=%RTbool %s - no change\n", fEnabled, pFirstRegMmio->RamRange.pszDesc));
4156
4157	return VINF_SUCCESS;
4158	}
4159
4160
4161	/**
4162	* Controls the dirty page tracking for an MMIO2 range.
4163	*
4164	* @returns VBox status code.
4165	* @param pVM The cross context VM structure.
4166	* @param pDevIns The device owning the MMIO2 memory.
4167	* @param hMmio2 The handle of the region.
4168	* @param fEnabled The new tracking state.
4169	*/
4170	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled)
4171	{
4172	/*
4173	* Do some basic validation before grapping the PGM lock and continuing.
4174	*/
4175	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
4176	int rc = PGM_LOCK(pVM);
4177	if (RT_SUCCESS(rc))
4178	{
4179	rc = pgmR3PhysMmio2ControlDirtyPageTrackingLocked(pVM, pDevIns, hMmio2, fEnabled);
4180	PGM_UNLOCK(pVM);
4181	}
4182	return rc;
4183	}
4184
4185
4186	/**
4187	* Changes the region number of an MMIO2 region.
4188	*
4189	* This is only for dealing with save state issues, nothing else.
4190	*
4191	* @return VBox status code.
4192	*
4193	* @param pVM The cross context VM structure.
4194	* @param pDevIns The device owning the MMIO2 memory.
4195	* @param hMmio2 The handle of the region.
4196	* @param iNewRegion The new region index.
4197	*
4198	* @thread EMT(0)
4199	* @sa @bugref{9359}
4200	*/
4201	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion)
4202	{
4203	/*
4204	* Validate input.
4205	*/
4206	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4207	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_LOADING, VERR_VM_INVALID_VM_STATE);
4208	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4209	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
4210	AssertReturn(iNewRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4211
4212	AssertReturn(pVM->enmVMState == VMSTATE_LOADING, VERR_INVALID_STATE);
4213
4214	int rc = PGM_LOCK(pVM);
4215	AssertRCReturn(rc, rc);
4216
4217	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
4218	AssertReturnStmt(pFirstRegMmio, PGM_UNLOCK(pVM), VERR_NOT_FOUND);
4219	AssertReturnStmt(pgmR3PhysMmio2Find(pVM, pDevIns, pFirstRegMmio->iSubDev, iNewRegion, NIL_PGMMMIO2HANDLE) == NULL,
4220	PGM_UNLOCK(pVM), VERR_RESOURCE_IN_USE);
4221
4222	/*
4223	* Make the change.
4224	*/
4225	pFirstRegMmio->iRegion = (uint8_t)iNewRegion;
4226
4227	PGM_UNLOCK(pVM);
4228	return VINF_SUCCESS;
4229	}
4230
4231
4232
4233	/*********************************************************************************************************************************
4234	* ROM *
4235	*********************************************************************************************************************************/
4236
4237	/**
4238	* Worker for PGMR3PhysRomRegister.
4239	*
4240	* This is here to simplify lock management, i.e. the caller does all the
4241	* locking and we can simply return without needing to remember to unlock
4242	* anything first.
4243	*
4244	* @returns VBox status code.
4245	* @param pVM The cross context VM structure.
4246	* @param pDevIns The device instance owning the ROM.
4247	* @param GCPhys First physical address in the range.
4248	* Must be page aligned!
4249	* @param cb The size of the range (in bytes).
4250	* Must be page aligned!
4251	* @param pvBinary Pointer to the binary data backing the ROM image.
4252	* @param cbBinary The size of the binary data pvBinary points to.
4253	* This must be less or equal to @a cb.
4254	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4255	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4256	* @param pszDesc Pointer to description string. This must not be freed.
4257	*/
4258	static int pgmR3PhysRomRegisterLocked(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4259	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc)
4260	{
4261	/*
4262	* Validate input.
4263	*/
4264	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4265	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
4266	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
4267	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4268	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4269	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
4270	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
4271	AssertReturn(!(fFlags & ~PGMPHYS_ROM_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
4272	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
4273
4274	const uint32_t cPages = cb >> PAGE_SHIFT;
4275
4276	/*
4277	* Find the ROM location in the ROM list first.
4278	*/
4279	PPGMROMRANGE pRomPrev = NULL;
4280	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
4281	while (pRom && GCPhysLast >= pRom->GCPhys)
4282	{
4283	if ( GCPhys <= pRom->GCPhysLast
4284	&& GCPhysLast >= pRom->GCPhys)
4285	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
4286	GCPhys, GCPhysLast, pszDesc,
4287	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
4288	VERR_PGM_RAM_CONFLICT);
4289	/* next */
4290	pRomPrev = pRom;
4291	pRom = pRom->pNextR3;
4292	}
4293
4294	/*
4295	* Find the RAM location and check for conflicts.
4296	*
4297	* Conflict detection is a bit different than for RAM registration since a
4298	* ROM can be located within a RAM range. So, what we have to check for is
4299	* other memory types (other than RAM that is) and that we don't span more
4300	* than one RAM range (lazy).
4301	*/
4302	bool fRamExists = false;
4303	PPGMRAMRANGE pRamPrev = NULL;
4304	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4305	while (pRam && GCPhysLast >= pRam->GCPhys)
4306	{
4307	if ( GCPhys <= pRam->GCPhysLast
4308	&& GCPhysLast >= pRam->GCPhys)
4309	{
4310	/* completely within? */
4311	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
4312	&& GCPhysLast <= pRam->GCPhysLast,
4313	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
4314	GCPhys, GCPhysLast, pszDesc,
4315	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
4316	VERR_PGM_RAM_CONFLICT);
4317	fRamExists = true;
4318	break;
4319	}
4320
4321	/* next */
4322	pRamPrev = pRam;
4323	pRam = pRam->pNextR3;
4324	}
4325	if (fRamExists)
4326	{
4327	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4328	uint32_t cPagesLeft = cPages;
4329	while (cPagesLeft-- > 0)
4330	{
4331	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
4332	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
4333	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
4334	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
4335	Assert(PGM_PAGE_IS_ZERO(pPage) \|\| PGM_IS_IN_NEM_MODE(pVM));
4336	pPage++;
4337	}
4338	}
4339
4340	/*
4341	* Update the base memory reservation if necessary.
4342	*/
4343	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
4344	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4345	cExtraBaseCost += cPages;
4346	if (cExtraBaseCost)
4347	{
4348	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
4349	if (RT_FAILURE(rc))
4350	return rc;
4351	}
4352
4353	#ifdef VBOX_WITH_NATIVE_NEM
4354	/*
4355	* Early NEM notification before we've made any changes or anything.
4356	*/
4357	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_ROM_F_REPLACE : 0)
4358	\| (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED ? NEM_NOTIFY_PHYS_ROM_F_SHADOW : 0);
4359	uint8_t u2NemState = UINT8_MAX;
4360	if (VM_IS_NEM_ENABLED(pVM))
4361	{
4362	int rc = NEMR3NotifyPhysRomRegisterEarly(pVM, GCPhys, cPages << PAGE_SHIFT,
4363	fRamExists ? PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhys) : NULL,
4364	fNemNotify, &u2NemState);
4365	AssertLogRelRCReturn(rc, rc);
4366	}
4367	#endif
4368
4369	/*
4370	* Allocate memory for the virgin copy of the RAM. In simplified memory mode,
4371	* we allocate memory for any ad-hoc RAM range and for shadow pages.
4372	*/
4373	PGMMALLOCATEPAGESREQ pReq = NULL;
4374	#ifdef VBOX_WITH_PGM_NEM_MODE
4375	void *pvRam = NULL;
4376	void *pvAlt = NULL;
4377	if (pVM->pgm.s.fNemMode)
4378	{
4379	if (!fRamExists)
4380	{
4381	int rc = SUPR3PageAlloc(cPages, &pvRam);
4382	if (RT_FAILURE(rc))
4383	return rc;
4384	}
4385	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4386	{
4387	int rc = SUPR3PageAlloc(cPages, &pvAlt);
4388	if (RT_FAILURE(rc))
4389	{
4390	if (pvRam)
4391	SUPR3PageFree(pvRam, cPages);
4392	return rc;
4393	}
4394	}
4395	}
4396	else
4397	#endif
4398	{
4399	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
4400	AssertRCReturn(rc, rc);
4401
4402	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4403	{
4404	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
4405	pReq->aPages[iPage].fZeroed = false;
4406	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
4407	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
4408	}
4409
4410	rc = GMMR3AllocatePagesPerform(pVM, pReq);
4411	if (RT_FAILURE(rc))
4412	{
4413	GMMR3AllocatePagesCleanup(pReq);
4414	return rc;
4415	}
4416	}
4417
4418	/*
4419	* Allocate the new ROM range and RAM range (if necessary).
4420	*/
4421	PPGMROMRANGE pRomNew;
4422	int rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
4423	if (RT_SUCCESS(rc))
4424	{
4425	PPGMRAMRANGE pRamNew = NULL;
4426	if (!fRamExists)
4427	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
4428	if (RT_SUCCESS(rc))
4429	{
4430	/*
4431	* Initialize and insert the RAM range (if required).
4432	*/
4433	uint32_t const idxFirstRamPage = fRamExists ? (GCPhys - pRam->GCPhys) >> PAGE_SHIFT : 0;
4434	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
4435	if (!fRamExists)
4436	{
4437	/* New RAM range. */
4438	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
4439	pRamNew->GCPhys = GCPhys;
4440	pRamNew->GCPhysLast = GCPhysLast;
4441	pRamNew->cb = cb;
4442	pRamNew->pszDesc = pszDesc;
4443	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
4444	pRamNew->pvR3 = NULL;
4445	pRamNew->paLSPages = NULL;
4446
4447	PPGMPAGE pRamPage = &pRamNew->aPages[idxFirstRamPage];
4448	#ifdef VBOX_WITH_PGM_NEM_MODE
4449	if (pVM->pgm.s.fNemMode)
4450	{
4451	AssertPtr(pvRam); Assert(pReq == NULL);
4452	pRamNew->pvR3 = pvRam;
4453	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4454	{
4455	PGM_PAGE_INIT(pRamPage, UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
4456	PGMPAGETYPE_ROM, PGM_PAGE_STATE_ALLOCATED);
4457	pRomPage->Virgin = *pRamPage;
4458	}
4459	}
4460	else
4461	#endif
4462	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4463	{
4464	PGM_PAGE_INIT(pRamPage,
4465	pReq->aPages[iPage].HCPhysGCPhys,
4466	pReq->aPages[iPage].idPage,
4467	PGMPAGETYPE_ROM,
4468	PGM_PAGE_STATE_ALLOCATED);
4469
4470	pRomPage->Virgin = *pRamPage;
4471	}
4472
4473	pVM->pgm.s.cAllPages += cPages;
4474	pVM->pgm.s.cPrivatePages += cPages;
4475	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
4476	}
4477	else
4478	{
4479	/* Existing RAM range. */
4480	PPGMPAGE pRamPage = &pRam->aPages[idxFirstRamPage];
4481	#ifdef VBOX_WITH_PGM_NEM_MODE
4482	if (pVM->pgm.s.fNemMode)
4483	{
4484	Assert(pvRam == NULL); Assert(pReq == NULL);
4485	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4486	{
4487	Assert(PGM_PAGE_GET_HCPHYS(pRamPage) == UINT64_C(0x0000fffffffff000));
4488	Assert(PGM_PAGE_GET_PAGEID(pRamPage) == NIL_GMM_PAGEID);
4489	Assert(PGM_PAGE_GET_STATE(pRamPage) == PGM_PAGE_STATE_ALLOCATED);
4490	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_ROM);
4491	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4492	PGM_PAGE_SET_PDE_TYPE(pVM, pRamPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4493	PGM_PAGE_SET_PTE_INDEX(pVM, pRamPage, 0);
4494	PGM_PAGE_SET_TRACKING(pVM, pRamPage, 0);
4495
4496	pRomPage->Virgin = *pRamPage;
4497	}
4498	}
4499	else
4500	#endif
4501	{
4502	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4503	{
4504	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_ROM);
4505	PGM_PAGE_SET_HCPHYS(pVM, pRamPage, pReq->aPages[iPage].HCPhysGCPhys);
4506	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4507	PGM_PAGE_SET_PAGEID(pVM, pRamPage, pReq->aPages[iPage].idPage);
4508	PGM_PAGE_SET_PDE_TYPE(pVM, pRamPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4509	PGM_PAGE_SET_PTE_INDEX(pVM, pRamPage, 0);
4510	PGM_PAGE_SET_TRACKING(pVM, pRamPage, 0);
4511
4512	pRomPage->Virgin = *pRamPage;
4513	}
4514	pVM->pgm.s.cZeroPages -= cPages;
4515	pVM->pgm.s.cPrivatePages += cPages;
4516	}
4517	pRamNew = pRam;
4518	}
4519
4520	#ifdef VBOX_WITH_NATIVE_NEM
4521	/* Set the NEM state of the pages if needed. */
4522	if (u2NemState != UINT8_MAX)
4523	pgmPhysSetNemStateForPages(&pRamNew->aPages[idxFirstRamPage], cPages, u2NemState);
4524	#endif
4525
4526	/* Flush physical page map TLB. */
4527	pgmPhysInvalidatePageMapTLB(pVM);
4528
4529	/*
4530	* Register the ROM access handler.
4531	*/
4532	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4533	pRomNew, MMHyperCCToR0(pVM, pRomNew), NIL_RTRCPTR, pszDesc);
4534	if (RT_SUCCESS(rc))
4535	{
4536	/*
4537	* Copy the image over to the virgin pages.
4538	* This must be done after linking in the RAM range.
4539	*/
4540	size_t cbBinaryLeft = cbBinary;
4541	PPGMPAGE pRamPage = &pRamNew->aPages[idxFirstRamPage];
4542	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4543	{
4544	void *pvDstPage;
4545	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
4546	if (RT_FAILURE(rc))
4547	{
4548	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
4549	break;
4550	}
4551	if (cbBinaryLeft >= PAGE_SIZE)
4552	{
4553	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
4554	cbBinaryLeft -= PAGE_SIZE;
4555	}
4556	else
4557	{
4558	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
4559	if (cbBinaryLeft > 0)
4560	{
4561	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
4562	cbBinaryLeft = 0;
4563	}
4564	}
4565	}
4566	if (RT_SUCCESS(rc))
4567	{
4568	/*
4569	* Initialize the ROM range.
4570	* Note that the Virgin member of the pages has already been initialized above.
4571	*/
4572	pRomNew->GCPhys = GCPhys;
4573	pRomNew->GCPhysLast = GCPhysLast;
4574	pRomNew->cb = cb;
4575	pRomNew->fFlags = fFlags;
4576	pRomNew->idSavedState = UINT8_MAX;
4577	pRomNew->cbOriginal = cbBinary;
4578	pRomNew->pszDesc = pszDesc;
4579	#ifdef VBOX_WITH_PGM_NEM_MODE
4580	pRomNew->pbR3Alternate = (uint8_t *)pvAlt;
4581	#endif
4582	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
4583	? pvBinary : RTMemDup(pvBinary, cbBinary);
4584	if (pRomNew->pvOriginal)
4585	{
4586	for (unsigned iPage = 0; iPage < cPages; iPage++)
4587	{
4588	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
4589	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
4590	#ifdef VBOX_WITH_PGM_NEM_MODE
4591	if (pVM->pgm.s.fNemMode)
4592	PGM_PAGE_INIT(&pPage->Shadow, UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
4593	PGMPAGETYPE_ROM_SHADOW, PGM_PAGE_STATE_ALLOCATED);
4594	else
4595	#endif
4596	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
4597	}
4598
4599	/* update the page count stats for the shadow pages. */
4600	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4601	{
4602	#ifdef VBOX_WITH_PGM_NEM_MODE
4603	if (pVM->pgm.s.fNemMode)
4604	pVM->pgm.s.cPrivatePages += cPages;
4605	else
4606	#endif
4607	pVM->pgm.s.cZeroPages += cPages;
4608	pVM->pgm.s.cAllPages += cPages;
4609	}
4610
4611	/*
4612	* Insert the ROM range, tell REM and return successfully.
4613	*/
4614	pRomNew->pNextR3 = pRom;
4615	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4616
4617	if (pRomPrev)
4618	{
4619	pRomPrev->pNextR3 = pRomNew;
4620	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
4621	}
4622	else
4623	{
4624	pVM->pgm.s.pRomRangesR3 = pRomNew;
4625	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
4626	}
4627
4628	pgmPhysInvalidatePageMapTLB(pVM);
4629	#ifdef VBOX_WITH_PGM_NEM_MODE
4630	if (!pVM->pgm.s.fNemMode)
4631	#endif
4632	GMMR3AllocatePagesCleanup(pReq);
4633
4634	#ifdef VBOX_WITH_NATIVE_NEM
4635	/*
4636	* Notify NEM again.
4637	*/
4638	if (VM_IS_NEM_ENABLED(pVM))
4639	{
4640	u2NemState = UINT8_MAX;
4641	rc = NEMR3NotifyPhysRomRegisterLate(pVM, GCPhys, cb, PGM_RAMRANGE_CALC_PAGE_R3PTR(pRamNew, GCPhys),
4642	fNemNotify, &u2NemState);
4643	if (u2NemState != UINT8_MAX)
4644	pgmPhysSetNemStateForPages(&pRamNew->aPages[idxFirstRamPage], cPages, u2NemState);
4645	if (RT_SUCCESS(rc))
4646	return rc;
4647	}
4648	else
4649	#endif
4650	return rc;
4651
4652	/*
4653	* bail out
4654	*/
4655	#ifdef VBOX_WITH_NATIVE_NEM
4656	/* unlink */
4657	if (pRomPrev)
4658	{
4659	pRomPrev->pNextR3 = pRom;
4660	pRomPrev->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4661	}
4662	else
4663	{
4664	pVM->pgm.s.pRomRangesR3 = pRom;
4665	pVM->pgm.s.pRomRangesR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4666	}
4667
4668	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4669	{
4670	# ifdef VBOX_WITH_PGM_NEM_MODE
4671	if (pVM->pgm.s.fNemMode)
4672	pVM->pgm.s.cPrivatePages -= cPages;
4673	else
4674	# endif
4675	pVM->pgm.s.cZeroPages -= cPages;
4676	pVM->pgm.s.cAllPages -= cPages;
4677	}
4678	#endif
4679	}
4680	else
4681	rc = VERR_NO_MEMORY;
4682	}
4683
4684	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
4685	AssertRC(rc2);
4686	}
4687
4688	if (!fRamExists)
4689	{
4690	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
4691	MMHyperFree(pVM, pRamNew);
4692	}
4693	else
4694	{
4695	PPGMPAGE pRamPage = &pRam->aPages[idxFirstRamPage];
4696	#ifdef VBOX_WITH_PGM_NEM_MODE
4697	if (pVM->pgm.s.fNemMode)
4698	{
4699	Assert(pvRam == NULL); Assert(pReq == NULL);
4700	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4701	{
4702	Assert(PGM_PAGE_GET_HCPHYS(pRamPage) == UINT64_C(0x0000fffffffff000));
4703	Assert(PGM_PAGE_GET_PAGEID(pRamPage) == NIL_GMM_PAGEID);
4704	Assert(PGM_PAGE_GET_STATE(pRamPage) == PGM_PAGE_STATE_ALLOCATED);
4705	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_RAM);
4706	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4707	}
4708	}
4709	else
4710	#endif
4711	{
4712	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4713	PGM_PAGE_INIT_ZERO(pRamPage, pVM, PGMPAGETYPE_RAM);
4714	pVM->pgm.s.cZeroPages += cPages;
4715	pVM->pgm.s.cPrivatePages -= cPages;
4716	}
4717	}
4718	}
4719	MMHyperFree(pVM, pRomNew);
4720	}
4721
4722	/** @todo Purge the mapping cache or something... */
4723	#ifdef VBOX_WITH_PGM_NEM_MODE
4724	if (pVM->pgm.s.fNemMode)
4725	{
4726	Assert(!pReq);
4727	if (pvRam)
4728	SUPR3PageFree(pvRam, cPages);
4729	if (pvAlt)
4730	SUPR3PageFree(pvAlt, cPages);
4731	}
4732	else
4733	#endif
4734	{
4735	GMMR3FreeAllocatedPages(pVM, pReq);
4736	GMMR3AllocatePagesCleanup(pReq);
4737	}
4738	return rc;
4739	}
4740
4741
4742	/**
4743	* Registers a ROM image.
4744	*
4745	* Shadowed ROM images requires double the amount of backing memory, so,
4746	* don't use that unless you have to. Shadowing of ROM images is process
4747	* where we can select where the reads go and where the writes go. On real
4748	* hardware the chipset provides means to configure this. We provide
4749	* PGMR3PhysProtectROM() for this purpose.
4750	*
4751	* A read-only copy of the ROM image will always be kept around while we
4752	* will allocate RAM pages for the changes on demand (unless all memory
4753	* is configured to be preallocated).
4754	*
4755	* @returns VBox status code.
4756	* @param pVM The cross context VM structure.
4757	* @param pDevIns The device instance owning the ROM.
4758	* @param GCPhys First physical address in the range.
4759	* Must be page aligned!
4760	* @param cb The size of the range (in bytes).
4761	* Must be page aligned!
4762	* @param pvBinary Pointer to the binary data backing the ROM image.
4763	* @param cbBinary The size of the binary data pvBinary points to.
4764	* This must be less or equal to @a cb.
4765	* @param fFlags Mask of flags, PGMPHYS_ROM_FLAGS_XXX.
4766	* @param pszDesc Pointer to description string. This must not be freed.
4767	*
4768	* @remark There is no way to remove the rom, automatically on device cleanup or
4769	* manually from the device yet. This isn't difficult in any way, it's
4770	* just not something we expect to be necessary for a while.
4771	*/
4772	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4773	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc)
4774	{
4775	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
4776	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
4777	PGM_LOCK_VOID(pVM);
4778	int rc = pgmR3PhysRomRegisterLocked(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
4779	PGM_UNLOCK(pVM);
4780	return rc;
4781	}
4782
4783
4784	/**
4785	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
4786	* that the virgin part is untouched.
4787	*
4788	* This is done after the normal memory has been cleared.
4789	*
4790	* ASSUMES that the caller owns the PGM lock.
4791	*
4792	* @param pVM The cross context VM structure.
4793	*/
4794	int pgmR3PhysRomReset(PVM pVM)
4795	{
4796	PGM_LOCK_ASSERT_OWNER(pVM);
4797	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4798	{
4799	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
4800
4801	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4802	{
4803	/*
4804	* Reset the physical handler.
4805	*/
4806	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
4807	AssertRCReturn(rc, rc);
4808
4809	/*
4810	* What we do with the shadow pages depends on the memory
4811	* preallocation option. If not enabled, we'll just throw
4812	* out all the dirty pages and replace them by the zero page.
4813	*/
4814	#ifdef VBOX_WITH_PGM_NEM_MODE
4815	if (pVM->pgm.s.fNemMode)
4816	{
4817	/* Clear all the shadow pages (currently using alternate backing). */
4818	RT_BZERO(pRom->pbR3Alternate, pRom->cb);
4819	}
4820	else
4821	#endif
4822	if (!pVM->pgm.s.fRamPreAlloc)
4823	{
4824	/* Free the dirty pages. */
4825	uint32_t cPendingPages = 0;
4826	PGMMFREEPAGESREQ pReq;
4827	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4828	AssertRCReturn(rc, rc);
4829
4830	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4831	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
4832	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
4833	{
4834	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
4835	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
4836	pRom->GCPhys + (iPage << PAGE_SHIFT),
4837	(PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pRom->aPages[iPage].Shadow));
4838	AssertLogRelRCReturn(rc, rc);
4839	}
4840
4841	if (cPendingPages)
4842	{
4843	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
4844	AssertLogRelRCReturn(rc, rc);
4845	}
4846	GMMR3FreePagesCleanup(pReq);
4847	}
4848	else
4849	{
4850	/* clear all the shadow pages. */
4851	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4852	{
4853	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
4854	continue;
4855	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
4856	void *pvDstPage;
4857	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4858	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
4859	if (RT_FAILURE(rc))
4860	break;
4861	ASMMemZeroPage(pvDstPage);
4862	}
4863	AssertRCReturn(rc, rc);
4864	}
4865	}
4866
4867	/*
4868	* Restore the original ROM pages after a saved state load.
4869	* Also, in strict builds check that ROM pages remain unmodified.
4870	*/
4871	#ifndef VBOX_STRICT
4872	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4873	#endif
4874	{
4875	size_t cbSrcLeft = pRom->cbOriginal;
4876	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
4877	uint32_t cRestored = 0;
4878	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
4879	{
4880	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4881	PPGMPAGE const pPage = pgmPhysGetPage(pVM, GCPhys);
4882	void const *pvDstPage = NULL;
4883	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvDstPage);
4884	if (RT_FAILURE(rc))
4885	break;
4886
4887	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
4888	{
4889	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4890	{
4891	void *pvDstPageW = NULL;
4892	rc = pgmPhysPageMap(pVM, pPage, GCPhys, &pvDstPageW);
4893	AssertLogRelRCReturn(rc, rc);
4894	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
4895	cRestored++;
4896	}
4897	else
4898	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
4899	}
4900	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
4901	}
4902	if (cRestored > 0)
4903	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
4904	}
4905	}
4906
4907	/* Clear the ROM restore flag now as we only need to do this once after
4908	loading saved state. */
4909	pVM->pgm.s.fRestoreRomPagesOnReset = false;
4910
4911	return VINF_SUCCESS;
4912	}
4913
4914
4915	/**
4916	* Called by PGMR3Term to free resources.
4917	*
4918	* ASSUMES that the caller owns the PGM lock.
4919	*
4920	* @param pVM The cross context VM structure.
4921	*/
4922	void pgmR3PhysRomTerm(PVM pVM)
4923	{
4924	/*
4925	* Free the heap copy of the original bits.
4926	*/
4927	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4928	{
4929	if ( pRom->pvOriginal
4930	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
4931	{
4932	RTMemFree((void *)pRom->pvOriginal);
4933	pRom->pvOriginal = NULL;
4934	}
4935	}
4936	}
4937
4938
4939	/**
4940	* Change the shadowing of a range of ROM pages.
4941	*
4942	* This is intended for implementing chipset specific memory registers
4943	* and will not be very strict about the input. It will silently ignore
4944	* any pages that are not the part of a shadowed ROM.
4945	*
4946	* @returns VBox status code.
4947	* @retval VINF_PGM_SYNC_CR3
4948	*
4949	* @param pVM The cross context VM structure.
4950	* @param GCPhys Where to start. Page aligned.
4951	* @param cb How much to change. Page aligned.
4952	* @param enmProt The new ROM protection.
4953	*/
4954	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
4955	{
4956	/*
4957	* Check input
4958	*/
4959	if (!cb)
4960	return VINF_SUCCESS;
4961	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4962	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4963	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4964	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4965	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
4966
4967	/*
4968	* Process the request.
4969	*/
4970	PGM_LOCK_VOID(pVM);
4971	int rc = VINF_SUCCESS;
4972	bool fFlushTLB = false;
4973	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4974	{
4975	if ( GCPhys <= pRom->GCPhysLast
4976	&& GCPhysLast >= pRom->GCPhys
4977	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
4978	{
4979	/*
4980	* Iterate the relevant pages and make necessary the changes.
4981	*/
4982	#ifdef VBOX_WITH_NATIVE_NEM
4983	PPGMRAMRANGE const pRam = pgmPhysGetRange(pVM, GCPhys);
4984	AssertPtrReturn(pRam, VERR_INTERNAL_ERROR_3);
4985	#endif
4986	bool fChanges = false;
4987	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
4988	? pRom->cb >> PAGE_SHIFT
4989	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
4990	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
4991	iPage < cPages;
4992	iPage++)
4993	{
4994	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
4995	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
4996	{
4997	fChanges = true;
4998
4999	/* flush references to the page. */
5000	RTGCPHYS const GCPhysPage = pRom->GCPhys + (iPage << PAGE_SHIFT);
5001	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, GCPhysPage);
5002	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pRamPage, true /fFlushPTEs/, &fFlushTLB);
5003	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
5004	rc = rc2;
5005	#ifdef VBOX_WITH_NATIVE_NEM
5006	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pRamPage);
5007	#endif
5008
5009	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
5010	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
5011
5012	pOld = pRamPage;
5013	pRamPage = pNew;
5014	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
5015
5016	#ifdef VBOX_WITH_NATIVE_NEM
5017	# ifdef VBOX_WITH_PGM_NEM_MODE
5018	/* In simplified mode we have to switch the page data around too. */
5019	if (pVM->pgm.s.fNemMode)
5020	{
5021	uint8_t abPage[PAGE_SIZE];
5022	uint8_t * const pbRamPage = PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhysPage);
5023	memcpy(abPage, &pRom->pbR3Alternate[(size_t)iPage << PAGE_SHIFT], sizeof(abPage));
5024	memcpy(&pRom->pbR3Alternate[(size_t)iPage << PAGE_SHIFT], pbRamPage, sizeof(abPage));
5025	memcpy(pbRamPage, abPage, sizeof(abPage));
5026	}
5027	# endif
5028	/* Tell NEM about the backing and protection change. */
5029	if (VM_IS_NEM_ENABLED(pVM))
5030	{
5031	PGMPAGETYPE enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pNew);
5032	NEMHCNotifyPhysPageChanged(pVM, GCPhys, PGM_PAGE_GET_HCPHYS(pOld), PGM_PAGE_GET_HCPHYS(pNew),
5033	PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhysPage),
5034	pgmPhysPageCalcNemProtection(pRamPage, enmType), enmType, &u2State);
5035	PGM_PAGE_SET_NEM_STATE(pRamPage, u2State);
5036	}
5037	#endif
5038	}
5039	pRomPage->enmProt = enmProt;
5040	}
5041
5042	/*
5043	* Reset the access handler if we made changes, no need
5044	* to optimize this.
5045	*/
5046	if (fChanges)
5047	{
5048	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
5049	if (RT_FAILURE(rc2))
5050	{
5051	PGM_UNLOCK(pVM);
5052	AssertRC(rc);
5053	return rc2;
5054	}
5055	}
5056
5057	/* Advance - cb isn't updated. */
5058	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
5059	}
5060	}
5061	PGM_UNLOCK(pVM);
5062	if (fFlushTLB)
5063	PGM_INVL_ALL_VCPU_TLBS(pVM);
5064
5065	return rc;
5066	}
5067
5068
5069
5070	/*********************************************************************************************************************************
5071	* Ballooning *
5072	*********************************************************************************************************************************/
5073
5074	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
5075
5076	/**
5077	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
5078	*
5079	* This is only called on one of the EMTs while the other ones are waiting for
5080	* it to complete this function.
5081	*
5082	* @returns VINF_SUCCESS (VBox strict status code).
5083	* @param pVM The cross context VM structure.
5084	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5085	* @param pvUser User parameter
5086	*/
5087	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5088	{
5089	uintptr_t paUser = (uintptr_t )pvUser;
5090	bool fInflate = !!paUser[0];
5091	unsigned cPages = paUser[1];
5092	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
5093	uint32_t cPendingPages = 0;
5094	PGMMFREEPAGESREQ pReq;
5095	int rc;
5096
5097	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
5098	PGM_LOCK_VOID(pVM);
5099
5100	if (fInflate)
5101	{
5102	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
5103	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
5104
5105	/* Replace pages with ZERO pages. */
5106	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
5107	if (RT_FAILURE(rc))
5108	{
5109	PGM_UNLOCK(pVM);
5110	AssertLogRelRC(rc);
5111	return rc;
5112	}
5113
5114	/* Iterate the pages. */
5115	for (unsigned i = 0; i < cPages; i++)
5116	{
5117	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
5118	if ( pPage == NULL
5119	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
5120	{
5121	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
5122	break;
5123	}
5124
5125	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
5126
5127	/* Flush the shadow PT if this page was previously used as a guest page table. */
5128	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
5129
5130	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i], (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
5131	if (RT_FAILURE(rc))
5132	{
5133	PGM_UNLOCK(pVM);
5134	AssertLogRelRC(rc);
5135	return rc;
5136	}
5137	Assert(PGM_PAGE_IS_ZERO(pPage));
5138	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
5139	}
5140
5141	if (cPendingPages)
5142	{
5143	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
5144	if (RT_FAILURE(rc))
5145	{
5146	PGM_UNLOCK(pVM);
5147	AssertLogRelRC(rc);
5148	return rc;
5149	}
5150	}
5151	GMMR3FreePagesCleanup(pReq);
5152	}
5153	else
5154	{
5155	/* Iterate the pages. */
5156	for (unsigned i = 0; i < cPages; i++)
5157	{
5158	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
5159	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
5160
5161	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
5162
5163	Assert(PGM_PAGE_IS_BALLOONED(pPage));
5164
5165	/* Change back to zero page. (NEM does not need to be informed.) */
5166	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
5167	}
5168
5169	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
5170	}
5171
5172	/* Notify GMM about the balloon change. */
5173	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
5174	if (RT_SUCCESS(rc))
5175	{
5176	if (!fInflate)
5177	{
5178	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
5179	pVM->pgm.s.cBalloonedPages -= cPages;
5180	}
5181	else
5182	pVM->pgm.s.cBalloonedPages += cPages;
5183	}
5184
5185	PGM_UNLOCK(pVM);
5186
5187	/* Flush the recompiler's TLB as well. */
5188	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5189	CPUMSetChangedFlags(pVM->apCpusR3[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5190
5191	AssertLogRelRC(rc);
5192	return rc;
5193	}
5194
5195
5196	/**
5197	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
5198	*
5199	* @returns VBox status code.
5200	* @param pVM The cross context VM structure.
5201	* @param fInflate Inflate or deflate memory balloon
5202	* @param cPages Number of pages to free
5203	* @param paPhysPage Array of guest physical addresses
5204	*/
5205	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
5206	{
5207	uintptr_t paUser[3];
5208
5209	paUser[0] = fInflate;
5210	paUser[1] = cPages;
5211	paUser[2] = (uintptr_t)paPhysPage;
5212	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
5213	AssertRC(rc);
5214
5215	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
5216	RTMemFree(paPhysPage);
5217	}
5218
5219	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
5220
5221	/**
5222	* Inflate or deflate a memory balloon
5223	*
5224	* @returns VBox status code.
5225	* @param pVM The cross context VM structure.
5226	* @param fInflate Inflate or deflate memory balloon
5227	* @param cPages Number of pages to free
5228	* @param paPhysPage Array of guest physical addresses
5229	*/
5230	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
5231	{
5232	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
5233	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
5234	int rc;
5235
5236	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
5237	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
5238
5239	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
5240	* In the SMP case we post a request packet to postpone the job.
5241	*/
5242	if (pVM->cCpus > 1)
5243	{
5244	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
5245	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
5246	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
5247
5248	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
5249
5250	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
5251	AssertRC(rc);
5252	}
5253	else
5254	{
5255	uintptr_t paUser[3];
5256
5257	paUser[0] = fInflate;
5258	paUser[1] = cPages;
5259	paUser[2] = (uintptr_t)paPhysPage;
5260	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
5261	AssertRC(rc);
5262	}
5263	return rc;
5264
5265	#else
5266	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
5267	return VERR_NOT_IMPLEMENTED;
5268	#endif
5269	}
5270
5271
5272	/*********************************************************************************************************************************
5273	* Write Monitoring *
5274	*********************************************************************************************************************************/
5275
5276	/**
5277	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
5278	* physical RAM.
5279	*
5280	* This is only called on one of the EMTs while the other ones are waiting for
5281	* it to complete this function.
5282	*
5283	* @returns VINF_SUCCESS (VBox strict status code).
5284	* @param pVM The cross context VM structure.
5285	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5286	* @param pvUser User parameter, unused.
5287	*/
5288	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5289	{
5290	int rc = VINF_SUCCESS;
5291	NOREF(pvUser); NOREF(pVCpu);
5292
5293	PGM_LOCK_VOID(pVM);
5294	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5295	pgmPoolResetDirtyPages(pVM);
5296	#endif
5297
5298	/** @todo pointless to write protect the physical page pointed to by RSP. */
5299
5300	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
5301	pRam;
5302	pRam = pRam->CTX_SUFF(pNext))
5303	{
5304	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
5305	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5306	{
5307	PPGMPAGE pPage = &pRam->aPages[iPage];
5308	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
5309
5310	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
5311	\|\| enmPageType == PGMPAGETYPE_MMIO2)
5312	{
5313	/*
5314	* A RAM page.
5315	*/
5316	switch (PGM_PAGE_GET_STATE(pPage))
5317	{
5318	case PGM_PAGE_STATE_ALLOCATED:
5319	/** @todo Optimize this: Don't always re-enable write
5320	* monitoring if the page is known to be very busy. */
5321	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
5322	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
5323
5324	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
5325	break;
5326
5327	case PGM_PAGE_STATE_SHARED:
5328	AssertFailed();
5329	break;
5330
5331	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
5332	default:
5333	break;
5334	}
5335	}
5336	}
5337	}
5338	pgmR3PoolWriteProtectPages(pVM);
5339	PGM_INVL_ALL_VCPU_TLBS(pVM);
5340	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5341	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5342
5343	PGM_UNLOCK(pVM);
5344	return rc;
5345	}
5346
5347	/**
5348	* Protect all physical RAM to monitor writes
5349	*
5350	* @returns VBox status code.
5351	* @param pVM The cross context VM structure.
5352	*/
5353	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
5354	{
5355	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
5356
5357	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
5358	AssertRC(rc);
5359	return rc;
5360	}
5361
5362
5363	/*********************************************************************************************************************************
5364	* Stats. *
5365	*********************************************************************************************************************************/
5366
5367	/**
5368	* Query the amount of free memory inside VMMR0
5369	*
5370	* @returns VBox status code.
5371	* @param pUVM The user mode VM handle.
5372	* @param pcbAllocMem Where to return the amount of memory allocated
5373	* by VMs.
5374	* @param pcbFreeMem Where to return the amount of memory that is
5375	* allocated from the host but not currently used
5376	* by any VMs.
5377	* @param pcbBallonedMem Where to return the sum of memory that is
5378	* currently ballooned by the VMs.
5379	* @param pcbSharedMem Where to return the amount of memory that is
5380	* currently shared.
5381	*/
5382	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
5383	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
5384	{
5385	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
5386	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
5387
5388	uint64_t cAllocPages = 0;
5389	uint64_t cFreePages = 0;
5390	uint64_t cBalloonPages = 0;
5391	uint64_t cSharedPages = 0;
5392	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
5393	AssertRCReturn(rc, rc);
5394
5395	if (pcbAllocMem)
5396	pcbAllocMem = cAllocPages _4K;
5397
5398	if (pcbFreeMem)
5399	pcbFreeMem = cFreePages _4K;
5400
5401	if (pcbBallonedMem)
5402	pcbBallonedMem = cBalloonPages _4K;
5403
5404	if (pcbSharedMem)
5405	pcbSharedMem = cSharedPages _4K;
5406
5407	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
5408	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
5409	return VINF_SUCCESS;
5410	}
5411
5412
5413	/**
5414	* Query memory stats for the VM.
5415	*
5416	* @returns VBox status code.
5417	* @param pUVM The user mode VM handle.
5418	* @param pcbTotalMem Where to return total amount memory the VM may
5419	* possibly use.
5420	* @param pcbPrivateMem Where to return the amount of private memory
5421	* currently allocated.
5422	* @param pcbSharedMem Where to return the amount of actually shared
5423	* memory currently used by the VM.
5424	* @param pcbZeroMem Where to return the amount of memory backed by
5425	* zero pages.
5426	*
5427	* @remarks The total mem is normally larger than the sum of the three
5428	* components. There are two reasons for this, first the amount of
5429	* shared memory is what we're sure is shared instead of what could
5430	* possibly be shared with someone. Secondly, because the total may
5431	* include some pure MMIO pages that doesn't go into any of the three
5432	* sub-counts.
5433	*
5434	* @todo Why do we return reused shared pages instead of anything that could
5435	* potentially be shared? Doesn't this mean the first VM gets a much
5436	* lower number of shared pages?
5437	*/
5438	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
5439	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
5440	{
5441	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
5442	PVM pVM = pUVM->pVM;
5443	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
5444
5445	if (pcbTotalMem)
5446	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
5447
5448	if (pcbPrivateMem)
5449	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
5450
5451	if (pcbSharedMem)
5452	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
5453
5454	if (pcbZeroMem)
5455	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
5456
5457	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
5458	return VINF_SUCCESS;
5459	}
5460
5461
5462
5463	/*********************************************************************************************************************************
5464	* Chunk Mappings and Page Allocation *
5465	*********************************************************************************************************************************/
5466
5467	/**
5468	* Tree enumeration callback for dealing with age rollover.
5469	* It will perform a simple compression of the current age.
5470	*/
5471	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
5472	{
5473	/* Age compression - ASSUMES iNow == 4. */
5474	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
5475	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
5476	pChunk->iLastUsed = 3;
5477	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
5478	pChunk->iLastUsed = 2;
5479	else if (pChunk->iLastUsed)
5480	pChunk->iLastUsed = 1;
5481	else /* iLastUsed = 0 */
5482	pChunk->iLastUsed = 4;
5483
5484	NOREF(pvUser);
5485	return 0;
5486	}
5487
5488
5489	/**
5490	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
5491	*/
5492	typedef struct PGMR3PHYSCHUNKUNMAPCB
5493	{
5494	PVM pVM; /*< Pointer to the VM. /
5495	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
5496	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
5497
5498
5499	/**
5500	* Callback used to find the mapping that's been unused for
5501	* the longest time.
5502	*/
5503	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
5504	{
5505	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
5506	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
5507
5508	/*
5509	* Check for locks and compare when last used.
5510	*/
5511	if (pChunk->cRefs)
5512	return 0;
5513	if (pChunk->cPermRefs)
5514	return 0;
5515	if ( pArg->pChunk
5516	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
5517	return 0;
5518
5519	/*
5520	* Check that it's not in any of the TLBs.
5521	*/
5522	PVM pVM = pArg->pVM;
5523	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
5524	== pChunk->Core.Key)
5525	{
5526	pChunk = NULL;
5527	return 0;
5528	}
5529	#ifdef VBOX_STRICT
5530	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5531	{
5532	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
5533	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
5534	}
5535	#endif
5536
5537	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbR3.aEntries); i++)
5538	if (pVM->pgm.s.PhysTlbR3.aEntries[i].pMap == pChunk)
5539	return 0;
5540
5541	pArg->pChunk = pChunk;
5542	return 0;
5543	}
5544
5545
5546	/**
5547	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
5548	*
5549	* The candidate will not be part of any TLBs, so no need to flush
5550	* anything afterwards.
5551	*
5552	* @returns Chunk id.
5553	* @param pVM The cross context VM structure.
5554	*/
5555	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
5556	{
5557	PGM_LOCK_ASSERT_OWNER(pVM);
5558
5559	/*
5560	* Enumerate the age tree starting with the left most node.
5561	*/
5562	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5563	PGMR3PHYSCHUNKUNMAPCB Args;
5564	Args.pVM = pVM;
5565	Args.pChunk = NULL;
5566	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
5567	Assert(Args.pChunk);
5568	if (Args.pChunk)
5569	{
5570	Assert(Args.pChunk->cRefs == 0);
5571	Assert(Args.pChunk->cPermRefs == 0);
5572	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5573	return Args.pChunk->Core.Key;
5574	}
5575
5576	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5577	return INT32_MAX;
5578	}
5579
5580
5581	/**
5582	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
5583	*
5584	* This is only called on one of the EMTs while the other ones are waiting for
5585	* it to complete this function.
5586	*
5587	* @returns VINF_SUCCESS (VBox strict status code).
5588	* @param pVM The cross context VM structure.
5589	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5590	* @param pvUser User pointer. Unused
5591	*
5592	*/
5593	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5594	{
5595	int rc = VINF_SUCCESS;
5596	PGM_LOCK_VOID(pVM);
5597	NOREF(pVCpu); NOREF(pvUser);
5598
5599	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
5600	{
5601	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
5602	/** @todo also not really efficient to unmap a chunk that contains PD
5603	* or PT pages. */
5604	pgmR3PoolClearAllRendezvous(pVM, pVM->apCpusR3[0], NULL /* no need to flush the REM TLB as we already did that above */);
5605
5606	/*
5607	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
5608	*/
5609	GMMMAPUNMAPCHUNKREQ Req;
5610	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5611	Req.Hdr.cbReq = sizeof(Req);
5612	Req.pvR3 = NULL;
5613	Req.idChunkMap = NIL_GMM_CHUNKID;
5614	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
5615	if (Req.idChunkUnmap != INT32_MAX)
5616	{
5617	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkUnmap, a);
5618	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5619	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkUnmap, a);
5620	if (RT_SUCCESS(rc))
5621	{
5622	/*
5623	* Remove the unmapped one.
5624	*/
5625	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
5626	AssertRelease(pUnmappedChunk);
5627	AssertRelease(!pUnmappedChunk->cRefs);
5628	AssertRelease(!pUnmappedChunk->cPermRefs);
5629	pUnmappedChunk->pv = NULL;
5630	pUnmappedChunk->Core.Key = UINT32_MAX;
5631	MMR3HeapFree(pUnmappedChunk);
5632	pVM->pgm.s.ChunkR3Map.c--;
5633	pVM->pgm.s.cUnmappedChunks++;
5634
5635	/*
5636	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
5637	*/
5638	/** @todo We should not flush chunks which include cr3 mappings. */
5639	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5640	{
5641	PPGMCPU pPGM = &pVM->apCpusR3[idCpu]->pgm.s;
5642
5643	pPGM->pGst32BitPdR3 = NULL;
5644	pPGM->pGstPaePdptR3 = NULL;
5645	pPGM->pGstAmd64Pml4R3 = NULL;
5646	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
5647	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
5648	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
5649	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
5650	{
5651	pPGM->apGstPaePDsR3[i] = NULL;
5652	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
5653	}
5654
5655	/* Flush REM TLBs. */
5656	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5657	}
5658	}
5659	}
5660	}
5661	PGM_UNLOCK(pVM);
5662	return rc;
5663	}
5664
5665	/**
5666	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
5667	*
5668	* @returns VBox status code.
5669	* @param pVM The cross context VM structure.
5670	*/
5671	static DECLCALLBACK(void) pgmR3PhysUnmapChunk(PVM pVM)
5672	{
5673	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
5674	AssertRC(rc);
5675	}
5676
5677
5678	/**
5679	* Maps the given chunk into the ring-3 mapping cache.
5680	*
5681	* This will call ring-0.
5682	*
5683	* @returns VBox status code.
5684	* @param pVM The cross context VM structure.
5685	* @param idChunk The chunk in question.
5686	* @param ppChunk Where to store the chunk tracking structure.
5687	*
5688	* @remarks Called from within the PGM critical section.
5689	* @remarks Can be called from any thread!
5690	*/
5691	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
5692	{
5693	int rc;
5694
5695	PGM_LOCK_ASSERT_OWNER(pVM);
5696
5697	/*
5698	* Move the chunk time forward.
5699	*/
5700	pVM->pgm.s.ChunkR3Map.iNow++;
5701	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
5702	{
5703	pVM->pgm.s.ChunkR3Map.iNow = 4;
5704	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
5705	}
5706
5707	/*
5708	* Allocate a new tracking structure first.
5709	*/
5710	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
5711	AssertReturn(pChunk, VERR_NO_MEMORY);
5712	pChunk->Core.Key = idChunk;
5713	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
5714
5715	/*
5716	* Request the ring-0 part to map the chunk in question.
5717	*/
5718	GMMMAPUNMAPCHUNKREQ Req;
5719	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5720	Req.Hdr.cbReq = sizeof(Req);
5721	Req.pvR3 = NULL;
5722	Req.idChunkMap = idChunk;
5723	Req.idChunkUnmap = NIL_GMM_CHUNKID;
5724
5725	/* Must be callable from any thread, so can't use VMMR3CallR0. */
5726	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkMap, a);
5727	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5728	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkMap, a);
5729	if (RT_SUCCESS(rc))
5730	{
5731	pChunk->pv = Req.pvR3;
5732
5733	/*
5734	* If we're running out of virtual address space, then we should
5735	* unmap another chunk.
5736	*
5737	* Currently, an unmap operation requires that all other virtual CPUs
5738	* are idling and not by chance making use of the memory we're
5739	* unmapping. So, we create an async unmap operation here.
5740	*
5741	* Now, when creating or restoring a saved state this wont work very
5742	* well since we may want to restore all guest RAM + a little something.
5743	* So, we have to do the unmap synchronously. Fortunately for us
5744	* though, during these operations the other virtual CPUs are inactive
5745	* and it should be safe to do this.
5746	*/
5747	/** @todo Eventually we should lock all memory when used and do
5748	* map+unmap as one kernel call without any rendezvous or
5749	* other precautions. */
5750	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
5751	{
5752	switch (VMR3GetState(pVM))
5753	{
5754	case VMSTATE_LOADING:
5755	case VMSTATE_SAVING:
5756	{
5757	PVMCPU pVCpu = VMMGetCpu(pVM);
5758	if ( pVCpu
5759	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
5760	{
5761	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
5762	break;
5763	}
5764	}
5765	RT_FALL_THRU();
5766	default:
5767	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
5768	AssertRC(rc);
5769	break;
5770	}
5771	}
5772
5773	/*
5774	* Update the tree. We must do this after any unmapping to make sure
5775	* the chunk we're going to return isn't unmapped by accident.
5776	*/
5777	AssertPtr(Req.pvR3);
5778	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
5779	AssertRelease(fRc);
5780	pVM->pgm.s.ChunkR3Map.c++;
5781	pVM->pgm.s.cMappedChunks++;
5782	}
5783	else
5784	{
5785	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
5786	* should probably restrict ourselves on linux. */
5787	AssertRC(rc);
5788	MMR3HeapFree(pChunk);
5789	pChunk = NULL;
5790	}
5791
5792	*ppChunk = pChunk;
5793	return rc;
5794	}
5795
5796
5797	/**
5798	* Invalidates the TLB for the ring-3 mapping cache.
5799	*
5800	* @param pVM The cross context VM structure.
5801	*/
5802	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
5803	{
5804	PGM_LOCK_VOID(pVM);
5805	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5806	{
5807	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
5808	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
5809	}
5810	/* The page map TLB references chunks, so invalidate that one too. */
5811	pgmPhysInvalidatePageMapTLB(pVM);
5812	PGM_UNLOCK(pVM);
5813	}
5814
5815
5816	/**
5817	* Response to VM_FF_PGM_NEED_HANDY_PAGES and helper for pgmPhysEnsureHandyPage.
5818	*
5819	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
5820	* signal and clear the out of memory condition. When called, this API is used
5821	* to try clear the condition when the user wants to resume.
5822	*
5823	* @returns The following VBox status codes.
5824	* @retval VINF_SUCCESS on success. FFs cleared.
5825	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
5826	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
5827	*
5828	* @param pVM The cross context VM structure.
5829	*
5830	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
5831	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
5832	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
5833	* handler.
5834	*/
5835	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
5836	{
5837	PGM_LOCK_VOID(pVM);
5838
5839	/*
5840	* Allocate more pages, noting down the index of the first new page.
5841	*/
5842	uint32_t iClear = pVM->pgm.s.cHandyPages;
5843	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
5844	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
5845	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5846	/** @todo we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
5847	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
5848	&& pVM->pgm.s.cHandyPages > 0)
5849	{
5850	/* Still handy pages left, so don't panic. */
5851	rc = VINF_SUCCESS;
5852	}
5853
5854	if (RT_SUCCESS(rc))
5855	{
5856	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
5857	Assert(pVM->pgm.s.cHandyPages > 0);
5858	#ifdef VBOX_STRICT
5859	uint32_t i;
5860	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
5861	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
5862	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
5863	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
5864	break;
5865	if (i != pVM->pgm.s.cHandyPages)
5866	{
5867	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
5868	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
5869	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
5870	RTAssertMsg2Add("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%s\n", j,
5871	pVM->pgm.s.aHandyPages[j].idPage,
5872	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
5873	pVM->pgm.s.aHandyPages[j].idSharedPage,
5874	j == i ? " <---" : "");
5875	RTAssertPanic();
5876	}
5877	#endif
5878	}
5879	else
5880	{
5881	/*
5882	* We should never get here unless there is a genuine shortage of
5883	* memory (or some internal error). Flag the error so the VM can be
5884	* suspended ASAP and the user informed. If we're totally out of
5885	* handy pages we will return failure.
5886	*/
5887	/* Report the failure. */
5888	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc cHandyPages=%#x\n"
5889	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
5890	rc, pVM->pgm.s.cHandyPages,
5891	pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cSharedPages, pVM->pgm.s.cZeroPages));
5892
5893	if ( rc != VERR_NO_MEMORY
5894	&& rc != VERR_NO_PHYS_MEMORY
5895	&& rc != VERR_LOCK_FAILED)
5896	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5897	{
5898	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
5899	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
5900	pVM->pgm.s.aHandyPages[i].idSharedPage));
5901	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
5902	if (idPage != NIL_GMM_PAGEID)
5903	{
5904	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
5905	pRam;
5906	pRam = pRam->pNextR3)
5907	{
5908	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
5909	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5910	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
5911	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
5912	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
5913	}
5914	}
5915	}
5916
5917	if (rc == VERR_NO_MEMORY)
5918	{
5919	uint64_t cbHostRamAvail = 0;
5920	int rc2 = RTSystemQueryAvailableRam(&cbHostRamAvail);
5921	if (RT_SUCCESS(rc2))
5922	LogRel(("Host RAM: %RU64MB available\n", cbHostRamAvail / _1M));
5923	else
5924	LogRel(("Cannot determine the amount of available host memory\n"));
5925	}
5926
5927	/* Set the FFs and adjust rc. */
5928	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5929	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
5930	if ( rc == VERR_NO_MEMORY
5931	\|\| rc == VERR_NO_PHYS_MEMORY
5932	\|\| rc == VERR_LOCK_FAILED)
5933	rc = VINF_EM_NO_MEMORY;
5934	}
5935
5936	PGM_UNLOCK(pVM);
5937	return rc;
5938	}
5939
5940
5941	/*********************************************************************************************************************************
5942	* Other Stuff *
5943	*********************************************************************************************************************************/
5944
5945	/**
5946	* Sets the Address Gate 20 state.
5947	*
5948	* @param pVCpu The cross context virtual CPU structure.
5949	* @param fEnable True if the gate should be enabled.
5950	* False if the gate should be disabled.
5951	*/
5952	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
5953	{
5954	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
5955	if (pVCpu->pgm.s.fA20Enabled != fEnable)
5956	{
5957	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5958	PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
5959	if ( CPUMIsGuestInVmxRootMode(pCtx)
5960	&& !fEnable)
5961	{
5962	Log(("Cannot enter A20M mode while in VMX root mode\n"));
5963	return;
5964	}
5965	#endif
5966	pVCpu->pgm.s.fA20Enabled = fEnable;
5967	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
5968	if (VM_IS_NEM_ENABLED(pVCpu->CTX_SUFF(pVM)))
5969	NEMR3NotifySetA20(pVCpu, fEnable);
5970	#ifdef PGM_WITH_A20
5971	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5972	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
5973	HMFlushTlb(pVCpu);
5974	#endif
5975	IEMTlbInvalidateAllPhysical(pVCpu);
5976	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
5977	}
5978	}
5979

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 92392

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