PGMPhys.cpp@ 92424

Last change on this file since 92424 was 92424, checked in by vboxsync, 3 years ago
VMM/PGM: Adjusted the ram range sizes again so they better align with 2MiB large pages. bugref:10122
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1	/* $Id: PGMPhys.cpp 92424 2021-11-15 13:09:17Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
24	#include <VBox/vmm/pgm.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/iom.h>
27	#include <VBox/vmm/mm.h>
28	#include <VBox/vmm/nem.h>
29	#include <VBox/vmm/stam.h>
30	#include <VBox/vmm/pdmdev.h>
31	#include "PGMInternal.h"
32	#include <VBox/vmm/vmcc.h>
33
34	#include "PGMInline.h"
35
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#ifdef VBOX_STRICT
44	# include <iprt/crc.h>
45	#endif
46	#include <iprt/thread.h>
47	#include <iprt/string.h>
48	#include <iprt/system.h>
49
50
51	/*********************************************************************************************************************************
52	* Defined Constants And Macros *
53	*********************************************************************************************************************************/
54	/** The number of pages to free in one batch. */
55	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
56
57
58
59	/*********************************************************************************************************************************
60	* Reading and Writing Guest Pysical Memory *
61	*********************************************************************************************************************************/
62
63	/*
64	* PGMR3PhysReadU8-64
65	* PGMR3PhysWriteU8-64
66	*/
67	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
68	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
69	#define PGMPHYS_DATASIZE 1
70	#define PGMPHYS_DATATYPE uint8_t
71	#include "PGMPhysRWTmpl.h"
72
73	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
74	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
75	#define PGMPHYS_DATASIZE 2
76	#define PGMPHYS_DATATYPE uint16_t
77	#include "PGMPhysRWTmpl.h"
78
79	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
80	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
81	#define PGMPHYS_DATASIZE 4
82	#define PGMPHYS_DATATYPE uint32_t
83	#include "PGMPhysRWTmpl.h"
84
85	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
86	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
87	#define PGMPHYS_DATASIZE 8
88	#define PGMPHYS_DATATYPE uint64_t
89	#include "PGMPhysRWTmpl.h"
90
91
92	/**
93	* EMT worker for PGMR3PhysReadExternal.
94	*/
95	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
96	PGMACCESSORIGIN enmOrigin)
97	{
98	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
99	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
100	return VINF_SUCCESS;
101	}
102
103
104	/**
105	* Read from physical memory, external users.
106	*
107	* @returns VBox status code.
108	* @retval VINF_SUCCESS.
109	*
110	* @param pVM The cross context VM structure.
111	* @param GCPhys Physical address to read from.
112	* @param pvBuf Where to read into.
113	* @param cbRead How many bytes to read.
114	* @param enmOrigin Who is calling.
115	*
116	* @thread Any but EMTs.
117	*/
118	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
119	{
120	VM_ASSERT_OTHER_THREAD(pVM);
121
122	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
123	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
124
125	PGM_LOCK_VOID(pVM);
126
127	/*
128	* Copy loop on ram ranges.
129	*/
130	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
131	for (;;)
132	{
133	/* Inside range or not? */
134	if (pRam && GCPhys >= pRam->GCPhys)
135	{
136	/*
137	* Must work our way thru this page by page.
138	*/
139	RTGCPHYS off = GCPhys - pRam->GCPhys;
140	while (off < pRam->cb)
141	{
142	unsigned iPage = off >> PAGE_SHIFT;
143	PPGMPAGE pPage = &pRam->aPages[iPage];
144
145	/*
146	* If the page has an ALL access handler, we'll have to
147	* delegate the job to EMT.
148	*/
149	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
150	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
151	{
152	PGM_UNLOCK(pVM);
153
154	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
155	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
156	}
157	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
158
159	/*
160	* Simple stuff, go ahead.
161	*/
162	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
163	if (cb > cbRead)
164	cb = cbRead;
165	PGMPAGEMAPLOCK PgMpLck;
166	const void *pvSrc;
167	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
168	if (RT_SUCCESS(rc))
169	{
170	memcpy(pvBuf, pvSrc, cb);
171	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
172	}
173	else
174	{
175	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
176	pRam->GCPhys + off, pPage, rc));
177	memset(pvBuf, 0xff, cb);
178	}
179
180	/* next page */
181	if (cb >= cbRead)
182	{
183	PGM_UNLOCK(pVM);
184	return VINF_SUCCESS;
185	}
186	cbRead -= cb;
187	off += cb;
188	GCPhys += cb;
189	pvBuf = (char *)pvBuf + cb;
190	} /* walk pages in ram range. */
191	}
192	else
193	{
194	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
195
196	/*
197	* Unassigned address space.
198	*/
199	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
200	if (cb >= cbRead)
201	{
202	memset(pvBuf, 0xff, cbRead);
203	break;
204	}
205	memset(pvBuf, 0xff, cb);
206
207	cbRead -= cb;
208	pvBuf = (char *)pvBuf + cb;
209	GCPhys += cb;
210	}
211
212	/* Advance range if necessary. */
213	while (pRam && GCPhys > pRam->GCPhysLast)
214	pRam = pRam->CTX_SUFF(pNext);
215	} /* Ram range walk */
216
217	PGM_UNLOCK(pVM);
218
219	return VINF_SUCCESS;
220	}
221
222
223	/**
224	* EMT worker for PGMR3PhysWriteExternal.
225	*/
226	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
227	PGMACCESSORIGIN enmOrigin)
228	{
229	/** @todo VERR_EM_NO_MEMORY */
230	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
231	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
232	return VINF_SUCCESS;
233	}
234
235
236	/**
237	* Write to physical memory, external users.
238	*
239	* @returns VBox status code.
240	* @retval VINF_SUCCESS.
241	* @retval VERR_EM_NO_MEMORY.
242	*
243	* @param pVM The cross context VM structure.
244	* @param GCPhys Physical address to write to.
245	* @param pvBuf What to write.
246	* @param cbWrite How many bytes to write.
247	* @param enmOrigin Who is calling.
248	*
249	* @thread Any but EMTs.
250	*/
251	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
252	{
253	VM_ASSERT_OTHER_THREAD(pVM);
254
255	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
256	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
257	GCPhys, cbWrite, enmOrigin));
258	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
259	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
260
261	PGM_LOCK_VOID(pVM);
262
263	/*
264	* Copy loop on ram ranges, stop when we hit something difficult.
265	*/
266	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
267	for (;;)
268	{
269	/* Inside range or not? */
270	if (pRam && GCPhys >= pRam->GCPhys)
271	{
272	/*
273	* Must work our way thru this page by page.
274	*/
275	RTGCPTR off = GCPhys - pRam->GCPhys;
276	while (off < pRam->cb)
277	{
278	RTGCPTR iPage = off >> PAGE_SHIFT;
279	PPGMPAGE pPage = &pRam->aPages[iPage];
280
281	/*
282	* Is the page problematic, we have to do the work on the EMT.
283	*
284	* Allocating writable pages and access handlers are
285	* problematic, write monitored pages are simple and can be
286	* dealt with here.
287	*/
288	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
289	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
290	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
291	{
292	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
293	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
294	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
295	else
296	{
297	PGM_UNLOCK(pVM);
298
299	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
300	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
301	}
302	}
303	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
304
305	/*
306	* Simple stuff, go ahead.
307	*/
308	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
309	if (cb > cbWrite)
310	cb = cbWrite;
311	PGMPAGEMAPLOCK PgMpLck;
312	void *pvDst;
313	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
314	if (RT_SUCCESS(rc))
315	{
316	memcpy(pvDst, pvBuf, cb);
317	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
318	}
319	else
320	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
321	pRam->GCPhys + off, pPage, rc));
322
323	/* next page */
324	if (cb >= cbWrite)
325	{
326	PGM_UNLOCK(pVM);
327	return VINF_SUCCESS;
328	}
329
330	cbWrite -= cb;
331	off += cb;
332	GCPhys += cb;
333	pvBuf = (const char *)pvBuf + cb;
334	} /* walk pages in ram range */
335	}
336	else
337	{
338	/*
339	* Unassigned address space, skip it.
340	*/
341	if (!pRam)
342	break;
343	size_t cb = pRam->GCPhys - GCPhys;
344	if (cb >= cbWrite)
345	break;
346	cbWrite -= cb;
347	pvBuf = (const char *)pvBuf + cb;
348	GCPhys += cb;
349	}
350
351	/* Advance range if necessary. */
352	while (pRam && GCPhys > pRam->GCPhysLast)
353	pRam = pRam->CTX_SUFF(pNext);
354	} /* Ram range walk */
355
356	PGM_UNLOCK(pVM);
357	return VINF_SUCCESS;
358	}
359
360
361	/*********************************************************************************************************************************
362	* Mapping Guest Physical Memory *
363	*********************************************************************************************************************************/
364
365	/**
366	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
367	*
368	* @returns see PGMR3PhysGCPhys2CCPtrExternal
369	* @param pVM The cross context VM structure.
370	* @param pGCPhys Pointer to the guest physical address.
371	* @param ppv Where to store the mapping address.
372	* @param pLock Where to store the lock.
373	*/
374	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
375	{
376	/*
377	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
378	* an access handler after it succeeds.
379	*/
380	int rc = PGM_LOCK(pVM);
381	AssertRCReturn(rc, rc);
382
383	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
384	if (RT_SUCCESS(rc))
385	{
386	PPGMPAGEMAPTLBE pTlbe;
387	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
388	AssertFatalRC(rc2);
389	PPGMPAGE pPage = pTlbe->pPage;
390	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
391	{
392	PGMPhysReleasePageMappingLock(pVM, pLock);
393	rc = VERR_PGM_PHYS_PAGE_RESERVED;
394	}
395	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
396	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
397	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
398	#endif
399	)
400	{
401	/* We must flush any corresponding pgm pool page here, otherwise we'll
402	* not be informed about writes and keep bogus gst->shw mappings around.
403	*/
404	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
405	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
406	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
407	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
408	}
409	}
410
411	PGM_UNLOCK(pVM);
412	return rc;
413	}
414
415
416	/**
417	* Requests the mapping of a guest page into ring-3, external threads.
418	*
419	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
420	* release it.
421	*
422	* This API will assume your intention is to write to the page, and will
423	* therefore replace shared and zero pages. If you do not intend to modify the
424	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
425	*
426	* @returns VBox status code.
427	* @retval VINF_SUCCESS on success.
428	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
429	* backing or if the page has any active access handlers. The caller
430	* must fall back on using PGMR3PhysWriteExternal.
431	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
432	*
433	* @param pVM The cross context VM structure.
434	* @param GCPhys The guest physical address of the page that should be mapped.
435	* @param ppv Where to store the address corresponding to GCPhys.
436	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
437	*
438	* @remark Avoid calling this API from within critical sections (other than the
439	* PGM one) because of the deadlock risk when we have to delegating the
440	* task to an EMT.
441	* @thread Any.
442	*/
443	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
444	{
445	AssertPtr(ppv);
446	AssertPtr(pLock);
447
448	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
449
450	int rc = PGM_LOCK(pVM);
451	AssertRCReturn(rc, rc);
452
453	/*
454	* Query the Physical TLB entry for the page (may fail).
455	*/
456	PPGMPAGEMAPTLBE pTlbe;
457	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
458	if (RT_SUCCESS(rc))
459	{
460	PPGMPAGE pPage = pTlbe->pPage;
461	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
462	rc = VERR_PGM_PHYS_PAGE_RESERVED;
463	else
464	{
465	/*
466	* If the page is shared, the zero page, or being write monitored
467	* it must be converted to an page that's writable if possible.
468	* We can only deal with write monitored pages here, the rest have
469	* to be on an EMT.
470	*/
471	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
472	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
473	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
474	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
475	#endif
476	)
477	{
478	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
479	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
480	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
481	&& !pgmPoolIsDirtyPage(pVM, GCPhys) /** @todo we're very likely doing this twice. */
482	#endif
483	)
484	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
485	else
486	{
487	PGM_UNLOCK(pVM);
488
489	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
490	pVM, &GCPhys, ppv, pLock);
491	}
492	}
493
494	/*
495	* Now, just perform the locking and calculate the return address.
496	*/
497	PPGMPAGEMAP pMap = pTlbe->pMap;
498	if (pMap)
499	pMap->cRefs++;
500
501	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
502	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
503	{
504	if (cLocks == 0)
505	pVM->pgm.s.cWriteLockedPages++;
506	PGM_PAGE_INC_WRITE_LOCKS(pPage);
507	}
508	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
509	{
510	PGM_PAGE_INC_WRITE_LOCKS(pPage);
511	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
512	if (pMap)
513	pMap->cRefs++; /* Extra ref to prevent it from going away. */
514	}
515
516	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
517	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
518	pLock->pvMap = pMap;
519	}
520	}
521
522	PGM_UNLOCK(pVM);
523	return rc;
524	}
525
526
527	/**
528	* Requests the mapping of a guest page into ring-3, external threads.
529	*
530	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
531	* release it.
532	*
533	* @returns VBox status code.
534	* @retval VINF_SUCCESS on success.
535	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
536	* backing or if the page as an active ALL access handler. The caller
537	* must fall back on using PGMPhysRead.
538	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
539	*
540	* @param pVM The cross context VM structure.
541	* @param GCPhys The guest physical address of the page that should be mapped.
542	* @param ppv Where to store the address corresponding to GCPhys.
543	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
544	*
545	* @remark Avoid calling this API from within critical sections (other than
546	* the PGM one) because of the deadlock risk.
547	* @thread Any.
548	*/
549	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
550	{
551	int rc = PGM_LOCK(pVM);
552	AssertRCReturn(rc, rc);
553
554	/*
555	* Query the Physical TLB entry for the page (may fail).
556	*/
557	PPGMPAGEMAPTLBE pTlbe;
558	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
559	if (RT_SUCCESS(rc))
560	{
561	PPGMPAGE pPage = pTlbe->pPage;
562	#if 1
563	/* MMIO pages doesn't have any readable backing. */
564	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
565	rc = VERR_PGM_PHYS_PAGE_RESERVED;
566	#else
567	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
568	rc = VERR_PGM_PHYS_PAGE_RESERVED;
569	#endif
570	else
571	{
572	/*
573	* Now, just perform the locking and calculate the return address.
574	*/
575	PPGMPAGEMAP pMap = pTlbe->pMap;
576	if (pMap)
577	pMap->cRefs++;
578
579	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
580	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
581	{
582	if (cLocks == 0)
583	pVM->pgm.s.cReadLockedPages++;
584	PGM_PAGE_INC_READ_LOCKS(pPage);
585	}
586	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
587	{
588	PGM_PAGE_INC_READ_LOCKS(pPage);
589	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
590	if (pMap)
591	pMap->cRefs++; /* Extra ref to prevent it from going away. */
592	}
593
594	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
595	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
596	pLock->pvMap = pMap;
597	}
598	}
599
600	PGM_UNLOCK(pVM);
601	return rc;
602	}
603
604
605	/**
606	* Requests the mapping of multiple guest page into ring-3, external threads.
607	*
608	* When you're done with the pages, call PGMPhysBulkReleasePageMappingLock()
609	* ASAP to release them.
610	*
611	* This API will assume your intention is to write to the pages, and will
612	* therefore replace shared and zero pages. If you do not intend to modify the
613	* pages, use the PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal() API.
614	*
615	* @returns VBox status code.
616	* @retval VINF_SUCCESS on success.
617	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
618	* backing or if any of the pages the page has any active access
619	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
620	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
621	* an invalid physical address.
622	*
623	* @param pVM The cross context VM structure.
624	* @param cPages Number of pages to lock.
625	* @param paGCPhysPages The guest physical address of the pages that
626	* should be mapped (@a cPages entries).
627	* @param papvPages Where to store the ring-3 mapping addresses
628	* corresponding to @a paGCPhysPages.
629	* @param paLocks Where to store the locking information that
630	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
631	* in length).
632	*
633	* @remark Avoid calling this API from within critical sections (other than the
634	* PGM one) because of the deadlock risk when we have to delegating the
635	* task to an EMT.
636	* @thread Any.
637	*/
638	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
639	void **papvPages, PPGMPAGEMAPLOCK paLocks)
640	{
641	Assert(cPages > 0);
642	AssertPtr(papvPages);
643	AssertPtr(paLocks);
644
645	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
646
647	int rc = PGM_LOCK(pVM);
648	AssertRCReturn(rc, rc);
649
650	/*
651	* Lock the pages one by one.
652	* The loop body is similar to PGMR3PhysGCPhys2CCPtrExternal.
653	*/
654	int32_t cNextYield = 128;
655	uint32_t iPage;
656	for (iPage = 0; iPage < cPages; iPage++)
657	{
658	if (--cNextYield > 0)
659	{ /* likely */ }
660	else
661	{
662	PGM_UNLOCK(pVM);
663	ASMNopPause();
664	PGM_LOCK_VOID(pVM);
665	cNextYield = 128;
666	}
667
668	/*
669	* Query the Physical TLB entry for the page (may fail).
670	*/
671	PPGMPAGEMAPTLBE pTlbe;
672	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
673	if (RT_SUCCESS(rc))
674	{ }
675	else
676	break;
677	PPGMPAGE pPage = pTlbe->pPage;
678
679	/*
680	* No MMIO or active access handlers.
681	*/
682	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
683	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
684	{ }
685	else
686	{
687	rc = VERR_PGM_PHYS_PAGE_RESERVED;
688	break;
689	}
690
691	/*
692	* The page must be in the allocated state and not be a dirty pool page.
693	* We can handle converting a write monitored page to an allocated one, but
694	* anything more complicated must be delegated to an EMT.
695	*/
696	bool fDelegateToEmt = false;
697	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
698	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
699	fDelegateToEmt = pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]);
700	#else
701	fDelegateToEmt = false;
702	#endif
703	else if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
704	{
705	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
706	if (!pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]))
707	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, paGCPhysPages[iPage]);
708	else
709	fDelegateToEmt = true;
710	#endif
711	}
712	else
713	fDelegateToEmt = true;
714	if (!fDelegateToEmt)
715	{ }
716	else
717	{
718	/* We could do this delegation in bulk, but considered too much work vs gain. */
719	PGM_UNLOCK(pVM);
720	rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
721	pVM, &paGCPhysPages[iPage], &papvPages[iPage], &paLocks[iPage]);
722	PGM_LOCK_VOID(pVM);
723	if (RT_FAILURE(rc))
724	break;
725	cNextYield = 128;
726	}
727
728	/*
729	* Now, just perform the locking and address calculation.
730	*/
731	PPGMPAGEMAP pMap = pTlbe->pMap;
732	if (pMap)
733	pMap->cRefs++;
734
735	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
736	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
737	{
738	if (cLocks == 0)
739	pVM->pgm.s.cWriteLockedPages++;
740	PGM_PAGE_INC_WRITE_LOCKS(pPage);
741	}
742	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
743	{
744	PGM_PAGE_INC_WRITE_LOCKS(pPage);
745	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", paGCPhysPages[iPage], pPage));
746	if (pMap)
747	pMap->cRefs++; /* Extra ref to prevent it from going away. */
748	}
749
750	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
751	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
752	paLocks[iPage].pvMap = pMap;
753	}
754
755	PGM_UNLOCK(pVM);
756
757	/*
758	* On failure we must unlock any pages we managed to get already.
759	*/
760	if (RT_FAILURE(rc) && iPage > 0)
761	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
762
763	return rc;
764	}
765
766
767	/**
768	* Requests the mapping of multiple guest page into ring-3, for reading only,
769	* external threads.
770	*
771	* When you're done with the pages, call PGMPhysReleasePageMappingLock() ASAP
772	* to release them.
773	*
774	* @returns VBox status code.
775	* @retval VINF_SUCCESS on success.
776	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
777	* backing or if any of the pages the page has an active ALL access
778	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
779	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
780	* an invalid physical address.
781	*
782	* @param pVM The cross context VM structure.
783	* @param cPages Number of pages to lock.
784	* @param paGCPhysPages The guest physical address of the pages that
785	* should be mapped (@a cPages entries).
786	* @param papvPages Where to store the ring-3 mapping addresses
787	* corresponding to @a paGCPhysPages.
788	* @param paLocks Where to store the lock information that
789	* pfnPhysReleasePageMappingLock needs (@a cPages
790	* in length).
791	*
792	* @remark Avoid calling this API from within critical sections (other than
793	* the PGM one) because of the deadlock risk.
794	* @thread Any.
795	*/
796	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
797	void const **papvPages, PPGMPAGEMAPLOCK paLocks)
798	{
799	Assert(cPages > 0);
800	AssertPtr(papvPages);
801	AssertPtr(paLocks);
802
803	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
804
805	int rc = PGM_LOCK(pVM);
806	AssertRCReturn(rc, rc);
807
808	/*
809	* Lock the pages one by one.
810	* The loop body is similar to PGMR3PhysGCPhys2CCPtrReadOnlyExternal.
811	*/
812	int32_t cNextYield = 256;
813	uint32_t iPage;
814	for (iPage = 0; iPage < cPages; iPage++)
815	{
816	if (--cNextYield > 0)
817	{ /* likely */ }
818	else
819	{
820	PGM_UNLOCK(pVM);
821	ASMNopPause();
822	PGM_LOCK_VOID(pVM);
823	cNextYield = 256;
824	}
825
826	/*
827	* Query the Physical TLB entry for the page (may fail).
828	*/
829	PPGMPAGEMAPTLBE pTlbe;
830	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
831	if (RT_SUCCESS(rc))
832	{ }
833	else
834	break;
835	PPGMPAGE pPage = pTlbe->pPage;
836
837	/*
838	* No MMIO or active all access handlers, everything else can be accessed.
839	*/
840	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
841	&& !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
842	{ }
843	else
844	{
845	rc = VERR_PGM_PHYS_PAGE_RESERVED;
846	break;
847	}
848
849	/*
850	* Now, just perform the locking and address calculation.
851	*/
852	PPGMPAGEMAP pMap = pTlbe->pMap;
853	if (pMap)
854	pMap->cRefs++;
855
856	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
857	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
858	{
859	if (cLocks == 0)
860	pVM->pgm.s.cReadLockedPages++;
861	PGM_PAGE_INC_READ_LOCKS(pPage);
862	}
863	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
864	{
865	PGM_PAGE_INC_READ_LOCKS(pPage);
866	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", paGCPhysPages[iPage], pPage));
867	if (pMap)
868	pMap->cRefs++; /* Extra ref to prevent it from going away. */
869	}
870
871	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
872	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
873	paLocks[iPage].pvMap = pMap;
874	}
875
876	PGM_UNLOCK(pVM);
877
878	/*
879	* On failure we must unlock any pages we managed to get already.
880	*/
881	if (RT_FAILURE(rc) && iPage > 0)
882	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
883
884	return rc;
885	}
886
887
888	/**
889	* Converts a GC physical address to a HC ring-3 pointer, with some
890	* additional checks.
891	*
892	* @returns VBox status code.
893	* @retval VINF_SUCCESS on success.
894	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
895	* access handler of some kind.
896	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
897	* accesses or is odd in any way.
898	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
899	*
900	* @param pVM The cross context VM structure.
901	* @param GCPhys The GC physical address to convert. Since this is only
902	* used for filling the REM TLB, the A20 mask must be
903	* applied before calling this API.
904	* @param fWritable Whether write access is required.
905	* @param ppv Where to store the pointer corresponding to GCPhys on
906	* success.
907	*/
908	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
909	{
910	PGM_LOCK_VOID(pVM);
911	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
912
913	PPGMRAMRANGE pRam;
914	PPGMPAGE pPage;
915	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
916	if (RT_SUCCESS(rc))
917	{
918	if (PGM_PAGE_IS_BALLOONED(pPage))
919	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
920	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
921	rc = VINF_SUCCESS;
922	else
923	{
924	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
925	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
926	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
927	{
928	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
929	* in -norawr0 mode. */
930	if (fWritable)
931	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
932	}
933	else
934	{
935	/* Temporarily disabled physical handler(s), since the recompiler
936	doesn't get notified when it's reset we'll have to pretend it's
937	operating normally. */
938	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
939	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
940	else
941	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
942	}
943	}
944	if (RT_SUCCESS(rc))
945	{
946	int rc2;
947
948	/* Make sure what we return is writable. */
949	if (fWritable)
950	switch (PGM_PAGE_GET_STATE(pPage))
951	{
952	case PGM_PAGE_STATE_ALLOCATED:
953	break;
954	case PGM_PAGE_STATE_BALLOONED:
955	AssertFailed();
956	break;
957	case PGM_PAGE_STATE_ZERO:
958	case PGM_PAGE_STATE_SHARED:
959	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
960	break;
961	RT_FALL_THRU();
962	case PGM_PAGE_STATE_WRITE_MONITORED:
963	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
964	AssertLogRelRCReturn(rc2, rc2);
965	break;
966	}
967
968	/* Get a ring-3 mapping of the address. */
969	PPGMPAGER3MAPTLBE pTlbe;
970	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
971	AssertLogRelRCReturn(rc2, rc2);
972	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
973	/** @todo mapping/locking hell; this isn't horribly efficient since
974	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
975
976	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
977	}
978	else
979	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
980
981	/* else: handler catching all access, no pointer returned. */
982	}
983	else
984	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
985
986	PGM_UNLOCK(pVM);
987	return rc;
988	}
989
990
991
992	/*********************************************************************************************************************************
993	* RAM Range Management *
994	*********************************************************************************************************************************/
995
996	#define MAKE_LEAF(a_pNode) \
997	do { \
998	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
999	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
1000	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
1001	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
1002	} while (0)
1003
1004	#define INSERT_LEFT(a_pParent, a_pNode) \
1005	do { \
1006	(a_pParent)->pLeftR3 = (a_pNode); \
1007	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
1008	} while (0)
1009	#define INSERT_RIGHT(a_pParent, a_pNode) \
1010	do { \
1011	(a_pParent)->pRightR3 = (a_pNode); \
1012	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
1013	} while (0)
1014
1015
1016	/**
1017	* Recursive tree builder.
1018	*
1019	* @param ppRam Pointer to the iterator variable.
1020	* @param iDepth The current depth. Inserts a leaf node if 0.
1021	*/
1022	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
1023	{
1024	PPGMRAMRANGE pRam;
1025	if (iDepth <= 0)
1026	{
1027	/*
1028	* Leaf node.
1029	*/
1030	pRam = *ppRam;
1031	if (pRam)
1032	{
1033	*ppRam = pRam->pNextR3;
1034	MAKE_LEAF(pRam);
1035	}
1036	}
1037	else
1038	{
1039
1040	/*
1041	* Intermediate node.
1042	*/
1043	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
1044
1045	pRam = *ppRam;
1046	if (!pRam)
1047	return pLeft;
1048	*ppRam = pRam->pNextR3;
1049	MAKE_LEAF(pRam);
1050	INSERT_LEFT(pRam, pLeft);
1051
1052	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
1053	if (pRight)
1054	INSERT_RIGHT(pRam, pRight);
1055	}
1056	return pRam;
1057	}
1058
1059
1060	/**
1061	* Rebuilds the RAM range search trees.
1062	*
1063	* @param pVM The cross context VM structure.
1064	*/
1065	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
1066	{
1067
1068	/*
1069	* Create the reasonably balanced tree in a sequential fashion.
1070	* For simplicity (laziness) we use standard recursion here.
1071	*/
1072	int iDepth = 0;
1073	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1074	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
1075	while (pRam)
1076	{
1077	PPGMRAMRANGE pLeft = pRoot;
1078
1079	pRoot = pRam;
1080	pRam = pRam->pNextR3;
1081	MAKE_LEAF(pRoot);
1082	INSERT_LEFT(pRoot, pLeft);
1083
1084	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
1085	if (pRight)
1086	INSERT_RIGHT(pRoot, pRight);
1087	/** @todo else: rotate the tree. */
1088
1089	iDepth++;
1090	}
1091
1092	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
1093	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
1094
1095	#ifdef VBOX_STRICT
1096	/*
1097	* Verify that the above code works.
1098	*/
1099	unsigned cRanges = 0;
1100	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1101	cRanges++;
1102	Assert(cRanges > 0);
1103
1104	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
1105	if ((1U << cMaxDepth) < cRanges)
1106	cMaxDepth++;
1107
1108	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1109	{
1110	unsigned cDepth = 0;
1111	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
1112	for (;;)
1113	{
1114	if (pRam == pRam2)
1115	break;
1116	Assert(pRam2);
1117	if (pRam->GCPhys < pRam2->GCPhys)
1118	pRam2 = pRam2->pLeftR3;
1119	else
1120	pRam2 = pRam2->pRightR3;
1121	}
1122	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
1123	}
1124	#endif /* VBOX_STRICT */
1125	}
1126
1127	#undef MAKE_LEAF
1128	#undef INSERT_LEFT
1129	#undef INSERT_RIGHT
1130
1131	/**
1132	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
1133	*
1134	* Called when anything was relocated.
1135	*
1136	* @param pVM The cross context VM structure.
1137	*/
1138	void pgmR3PhysRelinkRamRanges(PVM pVM)
1139	{
1140	PPGMRAMRANGE pCur;
1141
1142	#ifdef VBOX_STRICT
1143	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1144	{
1145	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
1146	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
1147	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1148	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
1149	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
1150	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
1151	Assert( pCur2 == pCur
1152	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
1153	}
1154	#endif
1155
1156	pCur = pVM->pgm.s.pRamRangesXR3;
1157	if (pCur)
1158	{
1159	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
1160
1161	for (; pCur->pNextR3; pCur = pCur->pNextR3)
1162	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
1163
1164	Assert(pCur->pNextR0 == NIL_RTR0PTR);
1165	}
1166	else
1167	{
1168	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
1169	}
1170	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1171
1172	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1173	}
1174
1175
1176	/**
1177	* Links a new RAM range into the list.
1178	*
1179	* @param pVM The cross context VM structure.
1180	* @param pNew Pointer to the new list entry.
1181	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1182	*/
1183	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
1184	{
1185	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
1186	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
1187
1188	PGM_LOCK_VOID(pVM);
1189
1190	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
1191	pNew->pNextR3 = pRam;
1192	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
1193
1194	if (pPrev)
1195	{
1196	pPrev->pNextR3 = pNew;
1197	pPrev->pNextR0 = pNew->pSelfR0;
1198	}
1199	else
1200	{
1201	pVM->pgm.s.pRamRangesXR3 = pNew;
1202	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
1203	}
1204	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1205
1206	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1207	PGM_UNLOCK(pVM);
1208	}
1209
1210
1211	/**
1212	* Unlink an existing RAM range from the list.
1213	*
1214	* @param pVM The cross context VM structure.
1215	* @param pRam Pointer to the new list entry.
1216	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1217	*/
1218	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
1219	{
1220	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
1221	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
1222
1223	PGM_LOCK_VOID(pVM);
1224
1225	PPGMRAMRANGE pNext = pRam->pNextR3;
1226	if (pPrev)
1227	{
1228	pPrev->pNextR3 = pNext;
1229	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1230	}
1231	else
1232	{
1233	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
1234	pVM->pgm.s.pRamRangesXR3 = pNext;
1235	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1236	}
1237	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1238
1239	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1240	PGM_UNLOCK(pVM);
1241	}
1242
1243
1244	/**
1245	* Unlink an existing RAM range from the list.
1246	*
1247	* @param pVM The cross context VM structure.
1248	* @param pRam Pointer to the new list entry.
1249	*/
1250	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
1251	{
1252	PGM_LOCK_VOID(pVM);
1253
1254	/* find prev. */
1255	PPGMRAMRANGE pPrev = NULL;
1256	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
1257	while (pCur != pRam)
1258	{
1259	pPrev = pCur;
1260	pCur = pCur->pNextR3;
1261	}
1262	AssertFatal(pCur);
1263
1264	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
1265	PGM_UNLOCK(pVM);
1266	}
1267
1268
1269	/**
1270	* Gets the number of ram ranges.
1271	*
1272	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1273	* @param pVM The cross context VM structure.
1274	*/
1275	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1276	{
1277	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1278
1279	PGM_LOCK_VOID(pVM);
1280	uint32_t cRamRanges = 0;
1281	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1282	cRamRanges++;
1283	PGM_UNLOCK(pVM);
1284	return cRamRanges;
1285	}
1286
1287
1288	/**
1289	* Get information about a range.
1290	*
1291	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1292	* @param pVM The cross context VM structure.
1293	* @param iRange The ordinal of the range.
1294	* @param pGCPhysStart Where to return the start of the range. Optional.
1295	* @param pGCPhysLast Where to return the address of the last byte in the
1296	* range. Optional.
1297	* @param ppszDesc Where to return the range description. Optional.
1298	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1299	* Optional.
1300	*/
1301	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1302	const char *ppszDesc, bool pfIsMmio)
1303	{
1304	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1305
1306	PGM_LOCK_VOID(pVM);
1307	uint32_t iCurRange = 0;
1308	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1309	if (iCurRange == iRange)
1310	{
1311	if (pGCPhysStart)
1312	*pGCPhysStart = pCur->GCPhys;
1313	if (pGCPhysLast)
1314	*pGCPhysLast = pCur->GCPhysLast;
1315	if (ppszDesc)
1316	*ppszDesc = pCur->pszDesc;
1317	if (pfIsMmio)
1318	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1319
1320	PGM_UNLOCK(pVM);
1321	return VINF_SUCCESS;
1322	}
1323	PGM_UNLOCK(pVM);
1324	return VERR_OUT_OF_RANGE;
1325	}
1326
1327
1328	/*********************************************************************************************************************************
1329	* RAM *
1330	*********************************************************************************************************************************/
1331
1332	/**
1333	* Frees the specified RAM page and replaces it with the ZERO page.
1334	*
1335	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
1336	*
1337	* @param pVM The cross context VM structure.
1338	* @param pReq Pointer to the request. This is NULL when doing a
1339	* bulk free in NEM memory mode.
1340	* @param pcPendingPages Where the number of pages waiting to be freed are
1341	* kept. This will normally be incremented. This is
1342	* NULL when doing a bulk free in NEM memory mode.
1343	* @param pPage Pointer to the page structure.
1344	* @param GCPhys The guest physical address of the page, if applicable.
1345	* @param enmNewType New page type for NEM notification, since several
1346	* callers will change the type upon successful return.
1347	*
1348	* @remarks The caller must own the PGM lock.
1349	*/
1350	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
1351	PGMPAGETYPE enmNewType)
1352	{
1353	/*
1354	* Assert sanity.
1355	*/
1356	PGM_LOCK_ASSERT_OWNER(pVM);
1357	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
1358	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
1359	{
1360	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
1361	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
1362	}
1363
1364	/** @todo What about ballooning of large pages??! */
1365	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
1366	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
1367
1368	if ( PGM_PAGE_IS_ZERO(pPage)
1369	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1370	return VINF_SUCCESS;
1371
1372	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
1373	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
1374	if (RT_UNLIKELY(!PGM_IS_IN_NEM_MODE(pVM)
1375	? idPage == NIL_GMM_PAGEID
1376	\|\| idPage > GMM_PAGEID_LAST
1377	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID
1378	: idPage != NIL_GMM_PAGEID))
1379	{
1380	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
1381	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
1382	}
1383	#ifdef VBOX_WITH_NATIVE_NEM
1384	const RTHCPHYS HCPhysPrev = PGM_PAGE_GET_HCPHYS(pPage);
1385	#endif
1386
1387	/* update page count stats. */
1388	if (PGM_PAGE_IS_SHARED(pPage))
1389	pVM->pgm.s.cSharedPages--;
1390	else
1391	pVM->pgm.s.cPrivatePages--;
1392	pVM->pgm.s.cZeroPages++;
1393
1394	/* Deal with write monitored pages. */
1395	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1396	{
1397	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
1398	pVM->pgm.s.cWrittenToPages++;
1399	}
1400
1401	/*
1402	* pPage = ZERO page.
1403	*/
1404	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
1405	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1406	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
1407	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
1408	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
1409	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
1410
1411	/* Flush physical page map TLB entry. */
1412	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
1413
1414	#ifdef VBOX_WITH_PGM_NEM_MODE
1415	/*
1416	* Skip the rest if we're doing a bulk free in NEM memory mode.
1417	*/
1418	if (!pReq)
1419	return VINF_SUCCESS;
1420	AssertLogRelReturn(!pVM->pgm.s.fNemMode, VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
1421	#endif
1422
1423	#ifdef VBOX_WITH_NATIVE_NEM
1424	/* Notify NEM. */
1425	/** @todo Remove this one? */
1426	if (VM_IS_NEM_ENABLED(pVM))
1427	{
1428	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pPage);
1429	NEMHCNotifyPhysPageChanged(pVM, GCPhys, HCPhysPrev, pVM->pgm.s.HCPhysZeroPg, pVM->pgm.s.pvZeroPgR3,
1430	pgmPhysPageCalcNemProtection(pPage, enmNewType), enmNewType, &u2State);
1431	PGM_PAGE_SET_NEM_STATE(pPage, u2State);
1432	}
1433	#else
1434	RT_NOREF(enmNewType);
1435	#endif
1436
1437	/*
1438	* Make sure it's not in the handy page array.
1439	*/
1440	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1441	{
1442	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
1443	{
1444	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1445	break;
1446	}
1447	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
1448	{
1449	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1450	break;
1451	}
1452	}
1453
1454	/*
1455	* Push it onto the page array.
1456	*/
1457	uint32_t iPage = *pcPendingPages;
1458	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
1459	*pcPendingPages += 1;
1460
1461	pReq->aPages[iPage].idPage = idPage;
1462
1463	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
1464	return VINF_SUCCESS;
1465
1466	/*
1467	* Flush the pages.
1468	*/
1469	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
1470	if (RT_SUCCESS(rc))
1471	{
1472	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1473	*pcPendingPages = 0;
1474	}
1475	return rc;
1476	}
1477
1478
1479	/**
1480	* Frees a range of pages, replacing them with ZERO pages of the specified type.
1481	*
1482	* @returns VBox status code.
1483	* @param pVM The cross context VM structure.
1484	* @param pRam The RAM range in which the pages resides.
1485	* @param GCPhys The address of the first page.
1486	* @param GCPhysLast The address of the last page.
1487	* @param pvMmio2 Pointer to the ring-3 mapping of any MMIO2 memory that
1488	* will replace the pages we're freeing up.
1489	*/
1490	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, void *pvMmio2)
1491	{
1492	PGM_LOCK_ASSERT_OWNER(pVM);
1493
1494	#ifdef VBOX_WITH_PGM_NEM_MODE
1495	/*
1496	* In simplified memory mode we don't actually free the memory,
1497	* we just unmap it and let NEM do any unlocking of it.
1498	*/
1499	if (pVM->pgm.s.fNemMode)
1500	{
1501	Assert(VM_IS_NEM_ENABLED(pVM));
1502	uint32_t const fNemNotify = (pvMmio2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0) \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE;
1503	uint8_t u2State = 0; /* (We don't support UINT8_MAX here.) */
1504	int rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify,
1505	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL,
1506	pvMmio2, &u2State, NULL /puNemRange/);
1507	AssertLogRelRCReturn(rc, rc);
1508
1509	/* Iterate the pages. */
1510	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1511	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1512	while (cPagesLeft-- > 0)
1513	{
1514	rc = pgmPhysFreePage(pVM, NULL, NULL, pPageDst, GCPhys, PGMPAGETYPE_MMIO);
1515	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1516
1517	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO);
1518	PGM_PAGE_SET_NEM_STATE(pPageDst, u2State);
1519
1520	GCPhys += PAGE_SIZE;
1521	pPageDst++;
1522	}
1523	return rc;
1524	}
1525	#else /* !VBOX_WITH_PGM_NEM_MODE */
1526	RT_NOREF(pvMmio2);
1527	#endif /* !VBOX_WITH_PGM_NEM_MODE */
1528
1529	/*
1530	* Regular mode.
1531	*/
1532	/* Prepare. */
1533	uint32_t cPendingPages = 0;
1534	PGMMFREEPAGESREQ pReq;
1535	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1536	AssertLogRelRCReturn(rc, rc);
1537
1538	#ifdef VBOX_WITH_NATIVE_NEM
1539	/* Tell NEM up-front. */
1540	uint8_t u2State = UINT8_MAX;
1541	if (VM_IS_NEM_ENABLED(pVM))
1542	{
1543	uint32_t const fNemNotify = (pvMmio2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0) \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE;
1544	rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify, NULL, pvMmio2,
1545	&u2State, NULL /puNemRange/);
1546	AssertLogRelRCReturnStmt(rc, GMMR3FreePagesCleanup(pReq), rc);
1547	}
1548	#endif
1549
1550	/* Iterate the pages. */
1551	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1552	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1553	while (cPagesLeft-- > 0)
1554	{
1555	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys, PGMPAGETYPE_MMIO);
1556	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1557
1558	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO);
1559	#ifdef VBOX_WITH_NATIVE_NEM
1560	if (u2State != UINT8_MAX)
1561	PGM_PAGE_SET_NEM_STATE(pPageDst, u2State);
1562	#endif
1563
1564	GCPhys += PAGE_SIZE;
1565	pPageDst++;
1566	}
1567
1568	/* Finish pending and cleanup. */
1569	if (cPendingPages)
1570	{
1571	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1572	AssertLogRelRCReturn(rc, rc);
1573	}
1574	GMMR3FreePagesCleanup(pReq);
1575
1576	return rc;
1577	}
1578
1579
1580	/**
1581	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1582	*
1583	* In NEM mode, this will allocate the pages backing the RAM range and this may
1584	* fail. NEM registration may also fail. (In regular HM mode it won't fail.)
1585	*
1586	* @returns VBox status code.
1587	* @param pVM The cross context VM structure.
1588	* @param pNew The new RAM range.
1589	* @param GCPhys The address of the RAM range.
1590	* @param GCPhysLast The last address of the RAM range.
1591	* @param R0PtrNew Ditto for R0.
1592	* @param fFlags PGM_RAM_RANGE_FLAGS_FLOATING or zero.
1593	* @param pszDesc The description.
1594	* @param pPrev The previous RAM range (for linking).
1595	*/
1596	static int pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1597	RTR0PTR R0PtrNew, uint32_t fFlags, const char *pszDesc, PPGMRAMRANGE pPrev)
1598	{
1599	/*
1600	* Initialize the range.
1601	*/
1602	pNew->pSelfR0 = R0PtrNew;
1603	pNew->GCPhys = GCPhys;
1604	pNew->GCPhysLast = GCPhysLast;
1605	pNew->cb = GCPhysLast - GCPhys + 1;
1606	pNew->pszDesc = pszDesc;
1607	pNew->fFlags = fFlags;
1608	pNew->uNemRange = UINT32_MAX;
1609	pNew->pvR3 = NULL;
1610	pNew->paLSPages = NULL;
1611
1612	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1613	#ifdef VBOX_WITH_PGM_NEM_MODE
1614	if (!pVM->pgm.s.fNemMode)
1615	#endif
1616	{
1617	RTGCPHYS iPage = cPages;
1618	while (iPage-- > 0)
1619	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1620
1621	/* Update the page count stats. */
1622	pVM->pgm.s.cZeroPages += cPages;
1623	pVM->pgm.s.cAllPages += cPages;
1624	}
1625	#ifdef VBOX_WITH_PGM_NEM_MODE
1626	else
1627	{
1628	int rc = SUPR3PageAlloc(cPages, &pNew->pvR3);
1629	if (RT_FAILURE(rc))
1630	return rc;
1631
1632	RTGCPHYS iPage = cPages;
1633	while (iPage-- > 0)
1634	PGM_PAGE_INIT(&pNew->aPages[iPage], UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
1635	PGMPAGETYPE_RAM, PGM_PAGE_STATE_ALLOCATED);
1636
1637	/* Update the page count stats. */
1638	pVM->pgm.s.cPrivatePages += cPages;
1639	pVM->pgm.s.cAllPages += cPages;
1640	}
1641	#endif
1642
1643	/*
1644	* Link it.
1645	*/
1646	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1647
1648	#ifdef VBOX_WITH_NATIVE_NEM
1649	/*
1650	* Notify NEM now that it has been linked.
1651	*/
1652	if (VM_IS_NEM_ENABLED(pVM))
1653	{
1654	uint8_t u2State = UINT8_MAX;
1655	int rc = NEMR3NotifyPhysRamRegister(pVM, GCPhys, pNew->cb, pNew->pvR3, &u2State, &pNew->uNemRange);
1656	if (RT_SUCCESS(rc))
1657	{
1658	if (u2State != UINT8_MAX)
1659	pgmPhysSetNemStateForPages(&pNew->aPages[0], cPages, u2State);
1660	}
1661	else
1662	pgmR3PhysUnlinkRamRange2(pVM, pNew, pPrev);
1663	return rc;
1664	}
1665	#endif
1666	return VINF_SUCCESS;
1667	}
1668
1669
1670	/**
1671	* PGMR3PhysRegisterRam worker that registers a high chunk.
1672	*
1673	* @returns VBox status code.
1674	* @param pVM The cross context VM structure.
1675	* @param GCPhys The address of the RAM.
1676	* @param cRamPages The number of RAM pages to register.
1677	* @param iChunk The chunk number.
1678	* @param pszDesc The RAM range description.
1679	* @param ppPrev Previous RAM range pointer. In/Out.
1680	*/
1681	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages, uint32_t iChunk,
1682	const char pszDesc, PPGMRAMRANGE ppPrev)
1683	{
1684	const char *pszDescChunk = iChunk == 0
1685	? pszDesc
1686	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1687	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1688
1689	/*
1690	* Allocate memory for the new chunk.
1691	*/
1692	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1693	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1694	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1695	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1696	void *pvChunk = NULL;
1697	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
1698	if (RT_SUCCESS(rc))
1699	{
1700	Assert(R0PtrChunk != NIL_RTR0PTR);
1701	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1702
1703	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1704
1705	/*
1706	* Ok, init and link the range.
1707	*/
1708	rc = pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1709	R0PtrChunk, PGM_RAM_RANGE_FLAGS_FLOATING, pszDescChunk, *ppPrev);
1710	if (RT_SUCCESS(rc))
1711	*ppPrev = pNew;
1712
1713	if (RT_FAILURE(rc))
1714	SUPR3PageFreeEx(pvChunk, cChunkPages);
1715	}
1716
1717	RTMemTmpFree(paChunkPages);
1718	return rc;
1719	}
1720
1721
1722	/**
1723	* Sets up a range RAM.
1724	*
1725	* This will check for conflicting registrations, make a resource
1726	* reservation for the memory (with GMM), and setup the per-page
1727	* tracking structures (PGMPAGE).
1728	*
1729	* @returns VBox status code.
1730	* @param pVM The cross context VM structure.
1731	* @param GCPhys The physical address of the RAM.
1732	* @param cb The size of the RAM.
1733	* @param pszDesc The description - not copied, so, don't free or change it.
1734	*/
1735	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1736	{
1737	/*
1738	* Validate input.
1739	*/
1740	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1741	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1742	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1743	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1744	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1745	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1746	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1747	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1748
1749	PGM_LOCK_VOID(pVM);
1750
1751	/*
1752	* Find range location and check for conflicts.
1753	*/
1754	PPGMRAMRANGE pPrev = NULL;
1755	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1756	while (pRam && GCPhysLast >= pRam->GCPhys)
1757	{
1758	AssertLogRelMsgReturnStmt( GCPhysLast < pRam->GCPhys
1759	\|\| GCPhys > pRam->GCPhysLast,
1760	("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1761	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1762	PGM_UNLOCK(pVM), VERR_PGM_RAM_CONFLICT);
1763
1764	/* next */
1765	pPrev = pRam;
1766	pRam = pRam->pNextR3;
1767	}
1768
1769	/*
1770	* Register it with GMM (the API bitches).
1771	*/
1772	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1773	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1774	if (RT_FAILURE(rc))
1775	{
1776	PGM_UNLOCK(pVM);
1777	return rc;
1778	}
1779
1780	if ( GCPhys >= _4G
1781	&& cPages > 256)
1782	{
1783	/*
1784	* The PGMRAMRANGE structures for the high memory can get very big.
1785	* In order to avoid SUPR3PageAllocEx allocation failures due to the
1786	* allocation size limit there and also to avoid being unable to find
1787	* guest mapping space for them, we split this memory up into 4MB in
1788	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
1789	* mode.
1790	*
1791	* The first and last page of each mapping are guard pages and marked
1792	* not-present. So, we've got 4186112 and 16769024 bytes available for
1793	* the PGMRAMRANGE structure.
1794	*
1795	* See also pgmR3PhysMmio2CalcChunkCount.
1796	*
1797	* Note! The sizes used here will influence the saved state.
1798	*/
1799	uint32_t cbChunk = 16U*_1M;
1800	uint32_t cPagesPerChunk = 1047552; /* max ~1048059 */
1801	Assert(cPagesPerChunk / 512 * 512 == cPagesPerChunk); /* NEM large page requirement */
1802	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1047552 < 16U_1M - PAGE_SIZE 2);
1803	AssertRelease(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1804
1805	RTGCPHYS cPagesLeft = cPages;
1806	RTGCPHYS GCPhysChunk = GCPhys;
1807	uint32_t iChunk = 0;
1808	while (cPagesLeft > 0)
1809	{
1810	uint32_t cPagesInChunk = cPagesLeft;
1811	if (cPagesInChunk > cPagesPerChunk)
1812	cPagesInChunk = cPagesPerChunk;
1813
1814	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, iChunk, pszDesc, &pPrev);
1815	AssertRCReturn(rc, rc);
1816
1817	/* advance */
1818	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1819	cPagesLeft -= cPagesInChunk;
1820	iChunk++;
1821	}
1822	}
1823	else
1824	{
1825	/*
1826	* Allocate, initialize and link the new RAM range.
1827	*/
1828	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
1829	PPGMRAMRANGE pNew;
1830	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1831	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc cbRamRange=%zu\n", rc, cbRamRange), rc);
1832
1833	rc = pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, MMHyperCCToR0(pVM, pNew), 0 /fFlags/, pszDesc, pPrev);
1834	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc cbRamRange=%zu\n", rc, cbRamRange), rc);
1835	}
1836	pgmPhysInvalidatePageMapTLB(pVM);
1837
1838	PGM_UNLOCK(pVM);
1839	return rc;
1840	}
1841
1842
1843	/**
1844	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1845	*
1846	* We do this late in the init process so that all the ROM and MMIO ranges have
1847	* been registered already and we don't go wasting memory on them.
1848	*
1849	* @returns VBox status code.
1850	*
1851	* @param pVM The cross context VM structure.
1852	*/
1853	int pgmR3PhysRamPreAllocate(PVM pVM)
1854	{
1855	Assert(pVM->pgm.s.fRamPreAlloc);
1856	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1857	#ifdef VBOX_WITH_PGM_NEM_MODE
1858	AssertLogRelReturn(!pVM->pgm.s.fNemMode, VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
1859	#endif
1860
1861	/*
1862	* Walk the RAM ranges and allocate all RAM pages, halt at
1863	* the first allocation error.
1864	*/
1865	uint64_t cPages = 0;
1866	uint64_t NanoTS = RTTimeNanoTS();
1867	PGM_LOCK_VOID(pVM);
1868	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1869	{
1870	PPGMPAGE pPage = &pRam->aPages[0];
1871	RTGCPHYS GCPhys = pRam->GCPhys;
1872	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1873	while (cLeft-- > 0)
1874	{
1875	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1876	{
1877	switch (PGM_PAGE_GET_STATE(pPage))
1878	{
1879	case PGM_PAGE_STATE_ZERO:
1880	{
1881	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1882	if (RT_FAILURE(rc))
1883	{
1884	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1885	PGM_UNLOCK(pVM);
1886	return rc;
1887	}
1888	cPages++;
1889	break;
1890	}
1891
1892	case PGM_PAGE_STATE_BALLOONED:
1893	case PGM_PAGE_STATE_ALLOCATED:
1894	case PGM_PAGE_STATE_WRITE_MONITORED:
1895	case PGM_PAGE_STATE_SHARED:
1896	/* nothing to do here. */
1897	break;
1898	}
1899	}
1900
1901	/* next */
1902	pPage++;
1903	GCPhys += PAGE_SIZE;
1904	}
1905	}
1906	PGM_UNLOCK(pVM);
1907	NanoTS = RTTimeNanoTS() - NanoTS;
1908
1909	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1910	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1911	return VINF_SUCCESS;
1912	}
1913
1914
1915	/**
1916	* Checks shared page checksums.
1917	*
1918	* @param pVM The cross context VM structure.
1919	*/
1920	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
1921	{
1922	#ifdef VBOX_STRICT
1923	PGM_LOCK_VOID(pVM);
1924
1925	if (pVM->pgm.s.cSharedPages > 0)
1926	{
1927	/*
1928	* Walk the ram ranges.
1929	*/
1930	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1931	{
1932	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1933	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1934
1935	while (iPage-- > 0)
1936	{
1937	PPGMPAGE pPage = &pRam->aPages[iPage];
1938	if (PGM_PAGE_IS_SHARED(pPage))
1939	{
1940	uint32_t u32Checksum = pPage->s.u2Unused0/* \| ((uint32_t)pPage->s.u2Unused1 << 8)*/;
1941	if (!u32Checksum)
1942	{
1943	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1944	void const *pvPage;
1945	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
1946	if (RT_SUCCESS(rc))
1947	{
1948	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
1949	# if 0
1950	AssertMsg((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
1951	# else
1952	if ((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum)
1953	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1954	else
1955	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1956	# endif
1957	}
1958	else
1959	AssertRC(rc);
1960	}
1961	}
1962
1963	} /* for each page */
1964
1965	} /* for each ram range */
1966	}
1967
1968	PGM_UNLOCK(pVM);
1969	#endif /* VBOX_STRICT */
1970	NOREF(pVM);
1971	}
1972
1973
1974	/**
1975	* Resets the physical memory state.
1976	*
1977	* ASSUMES that the caller owns the PGM lock.
1978	*
1979	* @returns VBox status code.
1980	* @param pVM The cross context VM structure.
1981	*/
1982	int pgmR3PhysRamReset(PVM pVM)
1983	{
1984	PGM_LOCK_ASSERT_OWNER(pVM);
1985
1986	/* Reset the memory balloon. */
1987	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1988	AssertRC(rc);
1989
1990	#ifdef VBOX_WITH_PAGE_SHARING
1991	/* Clear all registered shared modules. */
1992	pgmR3PhysAssertSharedPageChecksums(pVM);
1993	rc = GMMR3ResetSharedModules(pVM);
1994	AssertRC(rc);
1995	#endif
1996	/* Reset counters. */
1997	pVM->pgm.s.cReusedSharedPages = 0;
1998	pVM->pgm.s.cBalloonedPages = 0;
1999
2000	return VINF_SUCCESS;
2001	}
2002
2003
2004	/**
2005	* Resets (zeros) the RAM after all devices and components have been reset.
2006	*
2007	* ASSUMES that the caller owns the PGM lock.
2008	*
2009	* @returns VBox status code.
2010	* @param pVM The cross context VM structure.
2011	*/
2012	int pgmR3PhysRamZeroAll(PVM pVM)
2013	{
2014	PGM_LOCK_ASSERT_OWNER(pVM);
2015
2016	/*
2017	* We batch up pages that should be freed instead of calling GMM for
2018	* each and every one of them.
2019	*/
2020	uint32_t cPendingPages = 0;
2021	PGMMFREEPAGESREQ pReq;
2022	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2023	AssertLogRelRCReturn(rc, rc);
2024
2025	/*
2026	* Walk the ram ranges.
2027	*/
2028	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2029	{
2030	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2031	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2032
2033	if ( !pVM->pgm.s.fRamPreAlloc
2034	#ifdef VBOX_WITH_PGM_NEM_MODE
2035	&& !pVM->pgm.s.fNemMode
2036	#endif
2037	&& pVM->pgm.s.fZeroRamPagesOnReset)
2038	{
2039	/* Replace all RAM pages by ZERO pages. */
2040	while (iPage-- > 0)
2041	{
2042	PPGMPAGE pPage = &pRam->aPages[iPage];
2043	switch (PGM_PAGE_GET_TYPE(pPage))
2044	{
2045	case PGMPAGETYPE_RAM:
2046	/* Do not replace pages part of a 2 MB continuous range
2047	with zero pages, but zero them instead. */
2048	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
2049	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2050	{
2051	void *pvPage;
2052	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2053	AssertLogRelRCReturn(rc, rc);
2054	ASMMemZeroPage(pvPage);
2055	}
2056	else if (PGM_PAGE_IS_BALLOONED(pPage))
2057	{
2058	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2059	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2060	}
2061	else if (!PGM_PAGE_IS_ZERO(pPage))
2062	{
2063	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2064	PGMPAGETYPE_RAM);
2065	AssertLogRelRCReturn(rc, rc);
2066	}
2067	break;
2068
2069	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2070	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2071	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2072	pRam, true /fDoAccounting/);
2073	break;
2074
2075	case PGMPAGETYPE_MMIO2:
2076	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2077	case PGMPAGETYPE_ROM:
2078	case PGMPAGETYPE_MMIO:
2079	break;
2080	default:
2081	AssertFailed();
2082	}
2083	} /* for each page */
2084	}
2085	else
2086	{
2087	/* Zero the memory. */
2088	while (iPage-- > 0)
2089	{
2090	PPGMPAGE pPage = &pRam->aPages[iPage];
2091	switch (PGM_PAGE_GET_TYPE(pPage))
2092	{
2093	case PGMPAGETYPE_RAM:
2094	switch (PGM_PAGE_GET_STATE(pPage))
2095	{
2096	case PGM_PAGE_STATE_ZERO:
2097	break;
2098
2099	case PGM_PAGE_STATE_BALLOONED:
2100	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2101	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2102	break;
2103
2104	case PGM_PAGE_STATE_SHARED:
2105	case PGM_PAGE_STATE_WRITE_MONITORED:
2106	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2107	AssertLogRelRCReturn(rc, rc);
2108	RT_FALL_THRU();
2109
2110	case PGM_PAGE_STATE_ALLOCATED:
2111	if (pVM->pgm.s.fZeroRamPagesOnReset)
2112	{
2113	void *pvPage;
2114	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2115	AssertLogRelRCReturn(rc, rc);
2116	ASMMemZeroPage(pvPage);
2117	}
2118	break;
2119	}
2120	break;
2121
2122	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2123	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2124	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2125	pRam, true /fDoAccounting/);
2126	break;
2127
2128	case PGMPAGETYPE_MMIO2:
2129	case PGMPAGETYPE_ROM_SHADOW:
2130	case PGMPAGETYPE_ROM:
2131	case PGMPAGETYPE_MMIO:
2132	break;
2133	default:
2134	AssertFailed();
2135
2136	}
2137	} /* for each page */
2138	}
2139
2140	}
2141
2142	/*
2143	* Finish off any pages pending freeing.
2144	*/
2145	if (cPendingPages)
2146	{
2147	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2148	AssertLogRelRCReturn(rc, rc);
2149	}
2150	GMMR3FreePagesCleanup(pReq);
2151	return VINF_SUCCESS;
2152	}
2153
2154
2155	/**
2156	* Frees all RAM during VM termination
2157	*
2158	* ASSUMES that the caller owns the PGM lock.
2159	*
2160	* @returns VBox status code.
2161	* @param pVM The cross context VM structure.
2162	*/
2163	int pgmR3PhysRamTerm(PVM pVM)
2164	{
2165	PGM_LOCK_ASSERT_OWNER(pVM);
2166
2167	/* Reset the memory balloon. */
2168	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2169	AssertRC(rc);
2170
2171	#ifdef VBOX_WITH_PAGE_SHARING
2172	/*
2173	* Clear all registered shared modules.
2174	*/
2175	pgmR3PhysAssertSharedPageChecksums(pVM);
2176	rc = GMMR3ResetSharedModules(pVM);
2177	AssertRC(rc);
2178
2179	/*
2180	* Flush the handy pages updates to make sure no shared pages are hiding
2181	* in there. (Not unlikely if the VM shuts down, apparently.)
2182	*/
2183	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2184	#endif
2185
2186	/*
2187	* We batch up pages that should be freed instead of calling GMM for
2188	* each and every one of them.
2189	*/
2190	uint32_t cPendingPages = 0;
2191	PGMMFREEPAGESREQ pReq;
2192	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2193	AssertLogRelRCReturn(rc, rc);
2194
2195	/*
2196	* Walk the ram ranges.
2197	*/
2198	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2199	{
2200	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2201	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2202
2203	while (iPage-- > 0)
2204	{
2205	PPGMPAGE pPage = &pRam->aPages[iPage];
2206	switch (PGM_PAGE_GET_TYPE(pPage))
2207	{
2208	case PGMPAGETYPE_RAM:
2209	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2210	/** @todo change this to explicitly free private pages here. */
2211	if (PGM_PAGE_IS_SHARED(pPage))
2212	{
2213	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2214	PGMPAGETYPE_RAM);
2215	AssertLogRelRCReturn(rc, rc);
2216	}
2217	break;
2218
2219	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2220	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2221	case PGMPAGETYPE_MMIO2:
2222	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2223	case PGMPAGETYPE_ROM:
2224	case PGMPAGETYPE_MMIO:
2225	break;
2226	default:
2227	AssertFailed();
2228	}
2229	} /* for each page */
2230	}
2231
2232	/*
2233	* Finish off any pages pending freeing.
2234	*/
2235	if (cPendingPages)
2236	{
2237	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2238	AssertLogRelRCReturn(rc, rc);
2239	}
2240	GMMR3FreePagesCleanup(pReq);
2241	return VINF_SUCCESS;
2242	}
2243
2244
2245
2246	/*********************************************************************************************************************************
2247	* MMIO *
2248	*********************************************************************************************************************************/
2249
2250	/**
2251	* This is the interface IOM is using to register an MMIO region.
2252	*
2253	* It will check for conflicts and ensure that a RAM range structure
2254	* is present before calling the PGMR3HandlerPhysicalRegister API to
2255	* register the callbacks.
2256	*
2257	* @returns VBox status code.
2258	*
2259	* @param pVM The cross context VM structure.
2260	* @param GCPhys The start of the MMIO region.
2261	* @param cb The size of the MMIO region.
2262	* @param hType The physical access handler type registration.
2263	* @param pvUserR3 The user argument for R3.
2264	* @param pvUserR0 The user argument for R0.
2265	* @param pvUserRC The user argument for RC.
2266	* @param pszDesc The description of the MMIO region.
2267	*/
2268	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2269	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2270	{
2271	/*
2272	* Assert on some assumption.
2273	*/
2274	VM_ASSERT_EMT(pVM);
2275	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2276	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2277	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2278	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2279	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2280
2281	int rc = PGM_LOCK(pVM);
2282	AssertRCReturn(rc, rc);
2283
2284	/*
2285	* Make sure there's a RAM range structure for the region.
2286	*/
2287	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2288	bool fRamExists = false;
2289	PPGMRAMRANGE pRamPrev = NULL;
2290	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2291	while (pRam && GCPhysLast >= pRam->GCPhys)
2292	{
2293	if ( GCPhysLast >= pRam->GCPhys
2294	&& GCPhys <= pRam->GCPhysLast)
2295	{
2296	/* Simplification: all within the same range. */
2297	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2298	&& GCPhysLast <= pRam->GCPhysLast,
2299	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2300	GCPhys, GCPhysLast, pszDesc,
2301	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2302	PGM_UNLOCK(pVM),
2303	VERR_PGM_RAM_CONFLICT);
2304
2305	/* Check that it's all RAM or MMIO pages. */
2306	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2307	uint32_t cLeft = cb >> PAGE_SHIFT;
2308	while (cLeft-- > 0)
2309	{
2310	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2311	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2312	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2313	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2314	PGM_UNLOCK(pVM),
2315	VERR_PGM_RAM_CONFLICT);
2316	pPage++;
2317	}
2318
2319	/* Looks good. */
2320	fRamExists = true;
2321	break;
2322	}
2323
2324	/* next */
2325	pRamPrev = pRam;
2326	pRam = pRam->pNextR3;
2327	}
2328	PPGMRAMRANGE pNew;
2329	if (fRamExists)
2330	{
2331	pNew = NULL;
2332
2333	/*
2334	* Make all the pages in the range MMIO/ZERO pages, freeing any
2335	* RAM pages currently mapped here. This might not be 100% correct
2336	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2337	*/
2338	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, NULL);
2339	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
2340
2341	/* Force a PGM pool flush as guest ram references have been changed. */
2342	/** @todo not entirely SMP safe; assuming for now the guest takes
2343	* care of this internally (not touch mapped mmio while changing the
2344	* mapping). */
2345	PVMCPU pVCpu = VMMGetCpu(pVM);
2346	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2347	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2348	}
2349	else
2350	{
2351	/*
2352	* No RAM range, insert an ad hoc one.
2353	*
2354	* Note that we don't have to tell REM about this range because
2355	* PGMHandlerPhysicalRegisterEx will do that for us.
2356	*/
2357	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2358
2359	/* Alloc. */
2360	const uint32_t cPages = cb >> PAGE_SHIFT;
2361	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
2362	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2363	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), PGM_UNLOCK(pVM), rc);
2364
2365	#ifdef VBOX_WITH_NATIVE_NEM
2366	/* Notify NEM. */
2367	uint8_t u2State = 0; /* (must have valid state as there can't be anything to preserve) */
2368	if (VM_IS_NEM_ENABLED(pVM))
2369	{
2370	rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, cPages << PAGE_SHIFT, 0 /fFlags/, NULL, NULL,
2371	&u2State, &pNew->uNemRange);
2372	AssertLogRelRCReturnStmt(rc, MMHyperFree(pVM, pNew), rc);
2373	}
2374	#endif
2375
2376	/* Initialize the range. */
2377	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2378	pNew->GCPhys = GCPhys;
2379	pNew->GCPhysLast = GCPhysLast;
2380	pNew->cb = cb;
2381	pNew->pszDesc = pszDesc;
2382	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2383	pNew->pvR3 = NULL;
2384	pNew->paLSPages = NULL;
2385
2386	uint32_t iPage = cPages;
2387	while (iPage-- > 0)
2388	{
2389	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2390	#ifdef VBOX_WITH_NATIVE_NEM
2391	PGM_PAGE_SET_NEM_STATE(&pNew->aPages[iPage], u2State);
2392	#endif
2393	}
2394	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2395
2396	/* update the page count stats. */
2397	pVM->pgm.s.cPureMmioPages += cPages;
2398	pVM->pgm.s.cAllPages += cPages;
2399
2400	/* link it */
2401	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2402	}
2403
2404	/*
2405	* Register the access handler.
2406	*/
2407	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2408	if (RT_SUCCESS(rc))
2409	{
2410	#ifdef VBOX_WITH_NATIVE_NEM
2411	/* Late NEM notification. */
2412	if (VM_IS_NEM_ENABLED(pVM))
2413	{
2414	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
2415	rc = NEMR3NotifyPhysMmioExMapLate(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify,
2416	fRamExists ? (uint8_t *)pRam->pvR3 + (uintptr_t)(GCPhys - pRam->GCPhys) : NULL,
2417	NULL, !fRamExists ? &pRam->uNemRange : NULL);
2418	AssertLogRelRCReturn(rc, rc);
2419	}
2420	#endif
2421	}
2422	/** @todo the phys handler failure handling isn't complete, esp. wrt NEM. */
2423	else if (!fRamExists)
2424	{
2425	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2426	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2427
2428	/* remove the ad hoc range. */
2429	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2430	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2431	MMHyperFree(pVM, pRam);
2432	}
2433	pgmPhysInvalidatePageMapTLB(pVM);
2434
2435	PGM_UNLOCK(pVM);
2436	return rc;
2437	}
2438
2439
2440	/**
2441	* This is the interface IOM is using to register an MMIO region.
2442	*
2443	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2444	* any ad hoc PGMRAMRANGE left behind.
2445	*
2446	* @returns VBox status code.
2447	* @param pVM The cross context VM structure.
2448	* @param GCPhys The start of the MMIO region.
2449	* @param cb The size of the MMIO region.
2450	*/
2451	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2452	{
2453	VM_ASSERT_EMT(pVM);
2454
2455	int rc = PGM_LOCK(pVM);
2456	AssertRCReturn(rc, rc);
2457
2458	/*
2459	* First deregister the handler, then check if we should remove the ram range.
2460	*/
2461	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2462	if (RT_SUCCESS(rc))
2463	{
2464	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2465	PPGMRAMRANGE pRamPrev = NULL;
2466	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2467	while (pRam && GCPhysLast >= pRam->GCPhys)
2468	{
2469	/** @todo We're being a bit too careful here. rewrite. */
2470	if ( GCPhysLast == pRam->GCPhysLast
2471	&& GCPhys == pRam->GCPhys)
2472	{
2473	Assert(pRam->cb == cb);
2474
2475	/*
2476	* See if all the pages are dead MMIO pages.
2477	*/
2478	uint32_t const cPages = cb >> PAGE_SHIFT;
2479	bool fAllMMIO = true;
2480	uint32_t iPage = 0;
2481	uint32_t cLeft = cPages;
2482	while (cLeft-- > 0)
2483	{
2484	PPGMPAGE pPage = &pRam->aPages[iPage];
2485	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2486	/\|\| not-out-of-action later /)
2487	{
2488	fAllMMIO = false;
2489	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2490	break;
2491	}
2492	Assert( PGM_PAGE_IS_ZERO(pPage)
2493	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2494	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2495	pPage++;
2496	}
2497	if (fAllMMIO)
2498	{
2499	/*
2500	* Ad-hoc range, unlink and free it.
2501	*/
2502	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2503	GCPhys, GCPhysLast, pRam->pszDesc));
2504	/** @todo check the ad-hoc flags? */
2505
2506	#ifdef VBOX_WITH_NATIVE_NEM
2507	if (VM_IS_NEM_ENABLED(pVM)) /* Notify REM before we unlink the range. */
2508	{
2509	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhys, GCPhysLast - GCPhys + 1, 0 /fFlags/, NULL, NULL, NULL);
2510	AssertLogRelRCReturn(rc, rc);
2511	}
2512	#endif
2513
2514	pVM->pgm.s.cAllPages -= cPages;
2515	pVM->pgm.s.cPureMmioPages -= cPages;
2516
2517	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2518	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2519	MMHyperFree(pVM, pRam);
2520	break;
2521	}
2522	}
2523
2524	/*
2525	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2526	*/
2527	if ( GCPhysLast >= pRam->GCPhys
2528	&& GCPhys <= pRam->GCPhysLast)
2529	{
2530	Assert(GCPhys >= pRam->GCPhys);
2531	Assert(GCPhysLast <= pRam->GCPhysLast);
2532
2533	/*
2534	* Turn the pages back into RAM pages.
2535	*/
2536	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2537	uint32_t cLeft = cb >> PAGE_SHIFT;
2538	while (cLeft--)
2539	{
2540	PPGMPAGE pPage = &pRam->aPages[iPage];
2541	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2542	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2543	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2544	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2545	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2546	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2547	iPage++;
2548	}
2549
2550	#ifdef VBOX_WITH_NATIVE_NEM
2551	/* Notify REM (failure will probably leave things in a non-working state). */
2552	if (VM_IS_NEM_ENABLED(pVM))
2553	{
2554	uint8_t u2State = UINT8_MAX;
2555	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhys, GCPhysLast - GCPhys + 1, NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
2556	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL,
2557	NULL, &u2State);
2558	AssertLogRelRCReturn(rc, rc);
2559	if (u2State != UINT8_MAX)
2560	pgmPhysSetNemStateForPages(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT],
2561	cb >> PAGE_SHIFT, u2State);
2562	}
2563	#endif
2564	break;
2565	}
2566
2567	/* next */
2568	pRamPrev = pRam;
2569	pRam = pRam->pNextR3;
2570	}
2571	}
2572
2573	/* Force a PGM pool flush as guest ram references have been changed. */
2574	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2575	* this internally (not touch mapped mmio while changing the mapping). */
2576	PVMCPU pVCpu = VMMGetCpu(pVM);
2577	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2578	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2579
2580	pgmPhysInvalidatePageMapTLB(pVM);
2581	pgmPhysInvalidRamRangeTlbs(pVM);
2582	PGM_UNLOCK(pVM);
2583	return rc;
2584	}
2585
2586
2587
2588	/*********************************************************************************************************************************
2589	* MMIO2 *
2590	*********************************************************************************************************************************/
2591
2592	/**
2593	* Locate a MMIO2 range.
2594	*
2595	* @returns Pointer to the MMIO2 range.
2596	* @param pVM The cross context VM structure.
2597	* @param pDevIns The device instance owning the region.
2598	* @param iSubDev The sub-device number.
2599	* @param iRegion The region.
2600	* @param hMmio2 Handle to look up. If NIL, use the @a iSubDev and
2601	* @a iRegion.
2602	*/
2603	DECLINLINE(PPGMREGMMIO2RANGE) pgmR3PhysMmio2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev,
2604	uint32_t iRegion, PGMMMIO2HANDLE hMmio2)
2605	{
2606	if (hMmio2 != NIL_PGMMMIO2HANDLE)
2607	{
2608	if (hMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3) && hMmio2 != 0)
2609	{
2610	PPGMREGMMIO2RANGE pCur = pVM->pgm.s.apMmio2RangesR3[hMmio2 - 1];
2611	if (pCur && pCur->pDevInsR3 == pDevIns)
2612	{
2613	Assert(pCur->idMmio2 == hMmio2);
2614	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, NULL);
2615	return pCur;
2616	}
2617	Assert(!pCur);
2618	}
2619	for (PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2620	if (pCur->idMmio2 == hMmio2)
2621	{
2622	AssertBreak(pCur->pDevInsR3 == pDevIns);
2623	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, NULL);
2624	return pCur;
2625	}
2626	}
2627	else
2628	{
2629	/*
2630	* Search the list. There shouldn't be many entries.
2631	*/
2632	/** @todo Optimize this lookup! There may now be many entries and it'll
2633	* become really slow when doing MMR3HyperMapMMIO2 and similar. */
2634	for (PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2635	if ( pCur->pDevInsR3 == pDevIns
2636	&& pCur->iRegion == iRegion
2637	&& pCur->iSubDev == iSubDev)
2638	return pCur;
2639	}
2640	return NULL;
2641	}
2642
2643
2644	/**
2645	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking and PGMR3PhysMmio2Map.
2646	*/
2647	static int pgmR3PhysMmio2EnableDirtyPageTracing(PVM pVM, PPGMREGMMIO2RANGE pFirstMmio2)
2648	{
2649	int rc = VINF_SUCCESS;
2650	for (PPGMREGMMIO2RANGE pCurMmio2 = pFirstMmio2; pCurMmio2; pCurMmio2 = pCurMmio2->pNextR3)
2651	{
2652	Assert(!(pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_IS_TRACKING));
2653	int rc2 = pgmHandlerPhysicalExRegister(pVM, pCurMmio2->pPhysHandlerR3, pCurMmio2->RamRange.GCPhys,
2654	pCurMmio2->RamRange.GCPhysLast);
2655	AssertLogRelMsgRC(rc2, ("%#RGp-%#RGp %s failed -> %Rrc\n", pCurMmio2->RamRange.GCPhys, pCurMmio2->RamRange.GCPhysLast,
2656	pCurMmio2->RamRange.pszDesc, rc2));
2657	if (RT_SUCCESS(rc2))
2658	pCurMmio2->fFlags \|= PGMREGMMIO2RANGE_F_IS_TRACKING;
2659	else if (RT_SUCCESS(rc))
2660	rc = rc2;
2661	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2662	return rc;
2663	}
2664	AssertFailed();
2665	return rc;
2666	}
2667
2668
2669	/**
2670	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking and PGMR3PhysMmio2Unmap.
2671	*/
2672	static int pgmR3PhysMmio2DisableDirtyPageTracing(PVM pVM, PPGMREGMMIO2RANGE pFirstMmio2)
2673	{
2674	for (PPGMREGMMIO2RANGE pCurMmio2 = pFirstMmio2; pCurMmio2; pCurMmio2 = pCurMmio2->pNextR3)
2675	{
2676	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_IS_TRACKING)
2677	{
2678	int rc2 = pgmHandlerPhysicalExDeregister(pVM, pCurMmio2->pPhysHandlerR3);
2679	AssertLogRelMsgRC(rc2, ("%#RGp-%#RGp %s failed -> %Rrc\n", pCurMmio2->RamRange.GCPhys, pCurMmio2->RamRange.GCPhysLast,
2680	pCurMmio2->RamRange.pszDesc, rc2));
2681	pCurMmio2->fFlags &= ~PGMREGMMIO2RANGE_F_IS_TRACKING;
2682	}
2683	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2684	return VINF_SUCCESS;
2685	}
2686	AssertFailed();
2687	return VINF_SUCCESS;
2688
2689	}
2690
2691
2692	/**
2693	* Calculates the number of chunks
2694	*
2695	* @returns Number of registration chunk needed.
2696	* @param pVM The cross context VM structure.
2697	* @param cb The size of the MMIO/MMIO2 range.
2698	* @param pcPagesPerChunk Where to return the number of pages tracked by each
2699	* chunk. Optional.
2700	* @param pcbChunk Where to return the guest mapping size for a chunk.
2701	*/
2702	static uint16_t pgmR3PhysMmio2CalcChunkCount(PVM pVM, RTGCPHYS cb, uint32_t pcPagesPerChunk, uint32_t pcbChunk)
2703	{
2704	RT_NOREF_PV(pVM); /* without raw mode */
2705
2706	/*
2707	* This is the same calculation as PGMR3PhysRegisterRam does, except we'll be
2708	* needing a few bytes extra the PGMREGMMIO2RANGE structure.
2709	*
2710	* Note! In additions, we've got a 24 bit sub-page range for MMIO2 ranges, leaving
2711	* us with an absolute maximum of 16777215 pages per chunk (close to 64 GB).
2712	*
2713	* P.S. If we want to include a dirty bitmap, we'd have to drop down to 1040384 pages.
2714	*/
2715	uint32_t cbChunk = _16M;
2716	uint32_t cPagesPerChunk = 1047552; /* max ~1048059 */
2717	Assert(cPagesPerChunk / 64 * 64 == cPagesPerChunk); /* (NEM requirement) */
2718	Assert(cPagesPerChunk / 512 * 512 == cPagesPerChunk); /* (NEM large page requirement) */
2719	AssertCompile(sizeof(PGMREGMMIO2RANGE) + sizeof(PGMPAGE) * 1047552 < _16M - PAGE_SIZE * 2);
2720	AssertRelease(cPagesPerChunk <= PGM_MMIO2_MAX_PAGE_COUNT); /* See above note. */
2721	AssertRelease(RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
2722	if (pcbChunk)
2723	*pcbChunk = cbChunk;
2724	if (pcPagesPerChunk)
2725	*pcPagesPerChunk = cPagesPerChunk;
2726
2727	/* Calc the number of chunks we need. */
2728	RTGCPHYS const cPages = cb >> X86_PAGE_SHIFT;
2729	uint16_t cChunks = (uint16_t)((cPages + cPagesPerChunk - 1) / cPagesPerChunk);
2730	AssertRelease((RTGCPHYS)cChunks * cPagesPerChunk >= cPages);
2731	return cChunks;
2732	}
2733
2734
2735	/**
2736	* Worker for PGMR3PhysMMIO2Register that allocates and the PGMREGMMIO2RANGE
2737	* structures and does basic initialization.
2738	*
2739	* Caller must set type specfic members and initialize the PGMPAGE structures.
2740	*
2741	* This was previously also used by PGMR3PhysMmio2PreRegister, a function for
2742	* pre-registering MMIO that was later (6.1) replaced by a new handle based IOM
2743	* interface. The reference to caller and type above is purely historical.
2744	*
2745	* @returns VBox status code.
2746	* @param pVM The cross context VM structure.
2747	* @param pDevIns The device instance owning the region.
2748	* @param iSubDev The sub-device number (internal PCI config number).
2749	* @param iRegion The region number. If the MMIO2 memory is a PCI
2750	* I/O region this number has to be the number of that
2751	* region. Otherwise it can be any number safe
2752	* UINT8_MAX.
2753	* @param cb The size of the region. Must be page aligned.
2754	* @param fFlags PGMPHYS_MMIO2_FLAGS_XXX.
2755	* @param idMmio2 The MMIO2 ID for the first chunk.
2756	* @param pszDesc The description.
2757	* @param ppHeadRet Where to return the pointer to the first
2758	* registration chunk.
2759	*
2760	* @thread EMT
2761	*/
2762	static int pgmR3PhysMmio2Create(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags,
2763	uint8_t idMmio2, const char pszDesc, PPGMREGMMIO2RANGE ppHeadRet)
2764	{
2765	/*
2766	* Figure out how many chunks we need and of which size.
2767	*/
2768	uint32_t cPagesPerChunk;
2769	uint16_t cChunks = pgmR3PhysMmio2CalcChunkCount(pVM, cb, &cPagesPerChunk, NULL);
2770	AssertReturn(cChunks, VERR_PGM_PHYS_MMIO_EX_IPE);
2771
2772	/*
2773	* Allocate the chunks.
2774	*/
2775	PPGMREGMMIO2RANGE *ppNext = ppHeadRet;
2776	*ppNext = NULL;
2777
2778	int rc = VINF_SUCCESS;
2779	uint32_t cPagesLeft = cb >> X86_PAGE_SHIFT;
2780	for (uint16_t iChunk = 0; iChunk < cChunks && RT_SUCCESS(rc); iChunk++, idMmio2++)
2781	{
2782	/*
2783	* We currently do a single RAM range for the whole thing. This will
2784	* probably have to change once someone needs really large MMIO regions,
2785	* as we will be running into SUPR3PageAllocEx limitations and such.
2786	*/
2787	const uint32_t cPagesTrackedByChunk = RT_MIN(cPagesLeft, cPagesPerChunk);
2788	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPagesTrackedByChunk]);
2789	PPGMREGMMIO2RANGE pNew = NULL;
2790	if ( iChunk + 1 < cChunks
2791	\|\| cbRange >= _1M)
2792	{
2793	/*
2794	* Allocate memory for the registration structure.
2795	*/
2796	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2797	size_t const cbChunk = (1 + cChunkPages + 1) << PAGE_SHIFT;
2798	AssertLogRelBreakStmt(cbChunk == (uint32_t)cbChunk, rc = VERR_OUT_OF_RANGE);
2799	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
2800	AssertBreakStmt(paChunkPages, rc = VERR_NO_TMP_MEMORY);
2801	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
2802	void *pvChunk = NULL;
2803	rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
2804	AssertLogRelMsgRCBreakStmt(rc, ("rc=%Rrc, cChunkPages=%#zx\n", rc, cChunkPages), RTMemTmpFree(paChunkPages));
2805
2806	Assert(R0PtrChunk != NIL_RTR0PTR);
2807	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
2808
2809	pNew = (PPGMREGMMIO2RANGE)pvChunk;
2810	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_FLOATING;
2811	pNew->RamRange.pSelfR0 = R0PtrChunk + RT_UOFFSETOF(PGMREGMMIO2RANGE, RamRange);
2812
2813	RTMemTmpFree(paChunkPages);
2814	}
2815	/*
2816	* Not so big, do a one time hyper allocation.
2817	*/
2818	else
2819	{
2820	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2821	AssertLogRelMsgRCBreak(rc, ("cbRange=%zu\n", cbRange));
2822
2823	/*
2824	* Initialize allocation specific items.
2825	*/
2826	//pNew->RamRange.fFlags = 0;
2827	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2828	}
2829
2830	/*
2831	* Initialize the registration structure (caller does specific bits).
2832	*/
2833	pNew->pDevInsR3 = pDevIns;
2834	//pNew->pvR3 = NULL;
2835	//pNew->pNext = NULL;
2836	if (iChunk == 0)
2837	pNew->fFlags \|= PGMREGMMIO2RANGE_F_FIRST_CHUNK;
2838	if (iChunk + 1 == cChunks)
2839	pNew->fFlags \|= PGMREGMMIO2RANGE_F_LAST_CHUNK;
2840	if (fFlags & PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES)
2841	pNew->fFlags \|= PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES;
2842	pNew->iSubDev = iSubDev;
2843	pNew->iRegion = iRegion;
2844	pNew->idSavedState = UINT8_MAX;
2845	pNew->idMmio2 = idMmio2;
2846	//pNew->pPhysHandlerR3 = NULL;
2847	//pNew->paLSPages = NULL;
2848	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2849	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2850	pNew->RamRange.pszDesc = pszDesc;
2851	pNew->RamRange.cb = pNew->cbReal = (RTGCPHYS)cPagesTrackedByChunk << X86_PAGE_SHIFT;
2852	pNew->RamRange.fFlags \|= PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX;
2853	pNew->RamRange.uNemRange = UINT32_MAX;
2854	//pNew->RamRange.pvR3 = NULL;
2855	//pNew->RamRange.paLSPages = NULL;
2856
2857	*ppNext = pNew;
2858	ASMCompilerBarrier();
2859	cPagesLeft -= cPagesTrackedByChunk;
2860	ppNext = &pNew->pNextR3;
2861
2862	/*
2863	* Pre-allocate a handler if we're tracking dirty pages, unless NEM takes care of this.
2864	*/
2865	if ( (fFlags & PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES)
2866	#ifdef VBOX_WITH_PGM_NEM_MODE
2867	&& !NEMR3IsMmio2DirtyPageTrackingSupported(pVM)
2868	#endif
2869	)
2870
2871	{
2872	rc = pgmHandlerPhysicalExCreate(pVM, pVM->pgm.s.hMmio2DirtyPhysHandlerType,
2873	(RTR3PTR)(uintptr_t)idMmio2, idMmio2, idMmio2, pszDesc, &pNew->pPhysHandlerR3);
2874	AssertLogRelMsgRCBreak(rc, ("idMmio2=%zu\n", idMmio2));
2875	}
2876	}
2877	Assert(cPagesLeft == 0);
2878
2879	if (RT_SUCCESS(rc))
2880	{
2881	Assert((*ppHeadRet)->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
2882	return VINF_SUCCESS;
2883	}
2884
2885	/*
2886	* Free floating ranges.
2887	*/
2888	while (*ppHeadRet)
2889	{
2890	PPGMREGMMIO2RANGE pFree = *ppHeadRet;
2891	*ppHeadRet = pFree->pNextR3;
2892
2893	if (pFree->pPhysHandlerR3)
2894	{
2895	pgmHandlerPhysicalExDestroy(pVM, pFree->pPhysHandlerR3);
2896	pFree->pPhysHandlerR3 = NULL;
2897	}
2898
2899	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
2900	{
2901	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
2902	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2903	SUPR3PageFreeEx(pFree, cChunkPages);
2904	}
2905	}
2906
2907	return rc;
2908	}
2909
2910
2911	/**
2912	* Common worker PGMR3PhysMmio2PreRegister & PGMR3PhysMMIO2Register that links a
2913	* complete registration entry into the lists and lookup tables.
2914	*
2915	* @param pVM The cross context VM structure.
2916	* @param pNew The new MMIO / MMIO2 registration to link.
2917	*/
2918	static void pgmR3PhysMmio2Link(PVM pVM, PPGMREGMMIO2RANGE pNew)
2919	{
2920	Assert(pNew->idMmio2 != UINT8_MAX);
2921
2922	/*
2923	* Link it into the list (order doesn't matter, so insert it at the head).
2924	*
2925	* Note! The range we're linking may consist of multiple chunks, so we
2926	* have to find the last one.
2927	*/
2928	PPGMREGMMIO2RANGE pLast = pNew;
2929	for (pLast = pNew; ; pLast = pLast->pNextR3)
2930	{
2931	if (pLast->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2932	break;
2933	Assert(pLast->pNextR3);
2934	Assert(pLast->pNextR3->pDevInsR3 == pNew->pDevInsR3);
2935	Assert(pLast->pNextR3->iSubDev == pNew->iSubDev);
2936	Assert(pLast->pNextR3->iRegion == pNew->iRegion);
2937	Assert(pLast->pNextR3->idMmio2 == pLast->idMmio2 + 1);
2938	}
2939
2940	PGM_LOCK_VOID(pVM);
2941
2942	/* Link in the chain of ranges at the head of the list. */
2943	pLast->pNextR3 = pVM->pgm.s.pRegMmioRangesR3;
2944	pVM->pgm.s.pRegMmioRangesR3 = pNew;
2945
2946	/* Insert the MMIO2 range/page IDs. */
2947	uint8_t idMmio2 = pNew->idMmio2;
2948	for (;;)
2949	{
2950	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
2951	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
2952	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
2953	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = pNew->RamRange.pSelfR0 - RT_UOFFSETOF(PGMREGMMIO2RANGE, RamRange);
2954	if (pNew->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2955	break;
2956	pNew = pNew->pNextR3;
2957	idMmio2++;
2958	}
2959
2960	pgmPhysInvalidatePageMapTLB(pVM);
2961	PGM_UNLOCK(pVM);
2962	}
2963
2964
2965	/**
2966	* Allocate and register an MMIO2 region.
2967	*
2968	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2969	* associated with a device. It is also non-shared memory with a permanent
2970	* ring-3 mapping and page backing (presently).
2971	*
2972	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
2973	* the VM, in which case we'll drop the base memory pages. Presently we will
2974	* make no attempt to preserve anything that happens to be present in the base
2975	* memory that is replaced, this is of course incorrect but it's too much
2976	* effort.
2977	*
2978	* @returns VBox status code.
2979	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2980	* memory.
2981	* @retval VERR_ALREADY_EXISTS if the region already exists.
2982	*
2983	* @param pVM The cross context VM structure.
2984	* @param pDevIns The device instance owning the region.
2985	* @param iSubDev The sub-device number.
2986	* @param iRegion The region number. If the MMIO2 memory is a PCI
2987	* I/O region this number has to be the number of that
2988	* region. Otherwise it can be any number save
2989	* UINT8_MAX.
2990	* @param cb The size of the region. Must be page aligned.
2991	* @param fFlags Reserved for future use, must be zero.
2992	* @param pszDesc The description.
2993	* @param ppv Where to store the pointer to the ring-3 mapping of
2994	* the memory.
2995	* @param phRegion Where to return the MMIO2 region handle. Optional.
2996	* @thread EMT
2997	*/
2998	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2999	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion)
3000	{
3001	/*
3002	* Validate input.
3003	*/
3004	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
3005	*ppv = NULL;
3006	if (phRegion)
3007	{
3008	AssertPtrReturn(phRegion, VERR_INVALID_POINTER);
3009	*phRegion = NIL_PGMMMIO2HANDLE;
3010	}
3011	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3012	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3013	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3014	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3015	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3016	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3017	AssertReturn(pgmR3PhysMmio2Find(pVM, pDevIns, iSubDev, iRegion, NIL_PGMMMIO2HANDLE) == NULL, VERR_ALREADY_EXISTS);
3018	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3019	AssertReturn(cb, VERR_INVALID_PARAMETER);
3020	AssertReturn(!(fFlags & ~PGMPHYS_MMIO2_FLAGS_VALID_MASK), VERR_INVALID_FLAGS);
3021
3022	const uint32_t cPages = cb >> PAGE_SHIFT;
3023	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
3024	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3025	AssertLogRelReturn(cPages <= PGM_MMIO2_MAX_PAGE_COUNT, VERR_OUT_OF_RANGE);
3026
3027	/*
3028	* For the 2nd+ instance, mangle the description string so it's unique.
3029	*/
3030	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3031	{
3032	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3033	if (!pszDesc)
3034	return VERR_NO_MEMORY;
3035	}
3036
3037	/*
3038	* Allocate an MMIO2 range ID (not freed on failure).
3039	*
3040	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID, so
3041	* the IDs goes from 1 thru PGM_MMIO2_MAX_RANGES.
3042	*/
3043	unsigned cChunks = pgmR3PhysMmio2CalcChunkCount(pVM, cb, NULL, NULL);
3044
3045	PGM_LOCK_VOID(pVM);
3046	AssertCompile(PGM_MMIO2_MAX_RANGES < 255);
3047	uint8_t const idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
3048	unsigned const cNewMmio2Regions = pVM->pgm.s.cMmio2Regions + cChunks;
3049	if (cNewMmio2Regions > PGM_MMIO2_MAX_RANGES)
3050	{
3051	PGM_UNLOCK(pVM);
3052	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
3053	}
3054	pVM->pgm.s.cMmio2Regions = cNewMmio2Regions;
3055	PGM_UNLOCK(pVM);
3056
3057	/*
3058	* Try reserve and allocate the backing memory first as this is what is
3059	* most likely to fail.
3060	*/
3061	int rc = VINF_SUCCESS;
3062	#ifdef VBOX_WITH_PGM_NEM_MODE
3063	if (!pVM->pgm.s.fNemMode)
3064	#endif
3065	rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
3066	if (RT_SUCCESS(rc))
3067	{
3068	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
3069	if (RT_SUCCESS(rc))
3070	{
3071	void *pvPages;
3072	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3073	RTR0PTR pvPagesR0 = NIL_RTR0PTR;
3074	#endif
3075
3076	#ifdef VBOX_WITH_PGM_NEM_MODE
3077	if (!pVM->pgm.s.fNemMode)
3078	#endif
3079	{
3080	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3081	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, &pvPagesR0, paPages);
3082	#else
3083	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
3084	#endif
3085	}
3086	#ifdef VBOX_WITH_PGM_NEM_MODE
3087	else
3088	{
3089	rc = SUPR3PageAlloc(cPages, &pvPages);
3090	if (RT_SUCCESS(rc))
3091	for (uint32_t i = 0; i < cPages; i++)
3092	paPages[i].Phys = UINT64_C(0x0000fffffffff000);
3093	}
3094	#endif
3095	if (RT_SUCCESS(rc))
3096	{
3097	memset(pvPages, 0, cPages * PAGE_SIZE);
3098
3099	/*
3100	* Create the registered MMIO range record for it.
3101	*/
3102	PPGMREGMMIO2RANGE pNew;
3103	rc = pgmR3PhysMmio2Create(pVM, pDevIns, iSubDev, iRegion, cb, fFlags, idMmio2, pszDesc, &pNew);
3104	if (RT_SUCCESS(rc))
3105	{
3106	if (phRegion)
3107	phRegion = idMmio2; / The ID of the first chunk. */
3108
3109	uint32_t iSrcPage = 0;
3110	uint8_t pbCurPages = (uint8_t )pvPages;
3111	for (PPGMREGMMIO2RANGE pCur = pNew; pCur; pCur = pCur->pNextR3)
3112	{
3113	pCur->pvR3 = pbCurPages;
3114	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3115	pCur->pvR0 = pvPagesR0 + (iSrcPage << PAGE_SHIFT);
3116	#endif
3117	pCur->RamRange.pvR3 = pbCurPages;
3118
3119	uint32_t iDstPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3120	while (iDstPage-- > 0)
3121	{
3122	PGM_PAGE_INIT(&pNew->RamRange.aPages[iDstPage],
3123	paPages[iDstPage + iSrcPage].Phys,
3124	PGM_MMIO2_PAGEID_MAKE(idMmio2, iDstPage),
3125	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
3126	}
3127
3128	/* advance. */
3129	iSrcPage += pCur->RamRange.cb >> X86_PAGE_SHIFT;
3130	pbCurPages += pCur->RamRange.cb;
3131	}
3132
3133	RTMemTmpFree(paPages);
3134
3135	/*
3136	* Update the page count stats, link the registration and we're done.
3137	*/
3138	pVM->pgm.s.cAllPages += cPages;
3139	pVM->pgm.s.cPrivatePages += cPages;
3140
3141	pgmR3PhysMmio2Link(pVM, pNew);
3142
3143	*ppv = pvPages;
3144	return VINF_SUCCESS;
3145	}
3146
3147	SUPR3PageFreeEx(pvPages, cPages);
3148	}
3149	}
3150	RTMemTmpFree(paPages);
3151	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
3152	}
3153	if (pDevIns->iInstance > 0)
3154	MMR3HeapFree((void *)pszDesc);
3155	return rc;
3156	}
3157
3158
3159	/**
3160	* Deregisters and frees an MMIO2 region.
3161	*
3162	* Any physical access handlers registered for the region must be deregistered
3163	* before calling this function.
3164	*
3165	* @returns VBox status code.
3166	* @param pVM The cross context VM structure.
3167	* @param pDevIns The device instance owning the region.
3168	* @param hMmio2 The MMIO2 handle to deregister, or NIL if all
3169	* regions for the given device is to be deregistered.
3170	*/
3171	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3172	{
3173	/*
3174	* Validate input.
3175	*/
3176	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3177	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3178
3179	/*
3180	* The loop here scanning all registrations will make sure that multi-chunk ranges
3181	* get properly deregistered, though it's original purpose was the wildcard iRegion.
3182	*/
3183	PGM_LOCK_VOID(pVM);
3184	int rc = VINF_SUCCESS;
3185	unsigned cFound = 0;
3186	PPGMREGMMIO2RANGE pPrev = NULL;
3187	PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3;
3188	while (pCur)
3189	{
3190	uint32_t const fFlags = pCur->fFlags;
3191	if ( pCur->pDevInsR3 == pDevIns
3192	&& ( hMmio2 == NIL_PGMMMIO2HANDLE
3193	\|\| pCur->idMmio2 == hMmio2))
3194	{
3195	cFound++;
3196
3197	/*
3198	* Unmap it if it's mapped.
3199	*/
3200	if (fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3201	{
3202	int rc2 = PGMR3PhysMmio2Unmap(pVM, pCur->pDevInsR3, pCur->idMmio2, pCur->RamRange.GCPhys);
3203	AssertRC(rc2);
3204	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3205	rc = rc2;
3206	}
3207
3208	/*
3209	* Unlink it
3210	*/
3211	PPGMREGMMIO2RANGE pNext = pCur->pNextR3;
3212	if (pPrev)
3213	pPrev->pNextR3 = pNext;
3214	else
3215	pVM->pgm.s.pRegMmioRangesR3 = pNext;
3216	pCur->pNextR3 = NULL;
3217
3218	uint8_t idMmio2 = pCur->idMmio2;
3219	Assert(idMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3));
3220	if (idMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3))
3221	{
3222	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
3223	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
3224	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
3225	}
3226
3227	/*
3228	* Free the memory.
3229	*/
3230	uint32_t const cPages = pCur->cbReal >> PAGE_SHIFT;
3231	#ifdef VBOX_WITH_PGM_NEM_MODE
3232	if (!pVM->pgm.s.fNemMode)
3233	#endif
3234	{
3235	int rc2 = SUPR3PageFreeEx(pCur->pvR3, cPages);
3236	AssertRC(rc2);
3237	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3238	rc = rc2;
3239
3240	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
3241	AssertRC(rc2);
3242	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3243	rc = rc2;
3244	}
3245	#ifdef VBOX_WITH_PGM_NEM_MODE
3246	else
3247	{
3248	int rc2 = SUPR3PageFree(pCur->pvR3, cPages);
3249	AssertRC(rc2);
3250	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3251	rc = rc2;
3252	}
3253	#endif
3254
3255	if (pCur->pPhysHandlerR3)
3256	{
3257	pgmHandlerPhysicalExDestroy(pVM, pCur->pPhysHandlerR3);
3258	pCur->pPhysHandlerR3 = NULL;
3259	}
3260
3261	/* we're leaking hyper memory here if done at runtime. */
3262	#ifdef VBOX_STRICT
3263	VMSTATE const enmState = VMR3GetState(pVM);
3264	AssertMsg( enmState == VMSTATE_POWERING_OFF
3265	\|\| enmState == VMSTATE_POWERING_OFF_LS
3266	\|\| enmState == VMSTATE_OFF
3267	\|\| enmState == VMSTATE_OFF_LS
3268	\|\| enmState == VMSTATE_DESTROYING
3269	\|\| enmState == VMSTATE_TERMINATED
3270	\|\| enmState == VMSTATE_CREATING
3271	, ("%s\n", VMR3GetStateName(enmState)));
3272	#endif
3273
3274	if (pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3275	{
3276	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPages]);
3277	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3278	SUPR3PageFreeEx(pCur, cChunkPages);
3279	}
3280	/*else
3281	{
3282	rc = MMHyperFree(pVM, pCur); - does not work, see the alloc call.
3283	AssertRCReturn(rc, rc);
3284	} */
3285
3286
3287	/* update page count stats */
3288	pVM->pgm.s.cAllPages -= cPages;
3289	pVM->pgm.s.cPrivatePages -= cPages;
3290
3291	/* next */
3292	pCur = pNext;
3293	if (hMmio2 != NIL_PGMMMIO2HANDLE)
3294	{
3295	if (fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3296	break;
3297	hMmio2++;
3298	Assert(pCur->idMmio2 == hMmio2);
3299	Assert(pCur->pDevInsR3 == pDevIns);
3300	Assert(!(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK));
3301	}
3302	}
3303	else
3304	{
3305	pPrev = pCur;
3306	pCur = pCur->pNextR3;
3307	}
3308	}
3309	pgmPhysInvalidatePageMapTLB(pVM);
3310	PGM_UNLOCK(pVM);
3311	return !cFound && hMmio2 != NIL_PGMMMIO2HANDLE ? VERR_NOT_FOUND : rc;
3312	}
3313
3314
3315	/**
3316	* Maps a MMIO2 region.
3317	*
3318	* This is typically done when a guest / the bios / state loading changes the
3319	* PCI config. The replacing of base memory has the same restrictions as during
3320	* registration, of course.
3321	*
3322	* @returns VBox status code.
3323	*
3324	* @param pVM The cross context VM structure.
3325	* @param pDevIns The device instance owning the region.
3326	* @param hMmio2 The handle of the region to map.
3327	* @param GCPhys The guest-physical address to be remapped.
3328	*/
3329	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys)
3330	{
3331	/*
3332	* Validate input.
3333	*
3334	* Note! It's safe to walk the MMIO/MMIO2 list since registrations only
3335	* happens during VM construction.
3336	*/
3337	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3338	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3339	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3340	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3341	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3342	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3343
3344	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3345	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3346	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3347
3348	PPGMREGMMIO2RANGE pLastMmio = pFirstMmio;
3349	RTGCPHYS cbRange = 0;
3350	for (;;)
3351	{
3352	AssertReturn(!(pLastMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED), VERR_WRONG_ORDER);
3353	Assert(pLastMmio->RamRange.GCPhys == NIL_RTGCPHYS);
3354	Assert(pLastMmio->RamRange.GCPhysLast == NIL_RTGCPHYS);
3355	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3356	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3357	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3358	cbRange += pLastMmio->RamRange.cb;
3359	if (pLastMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3360	break;
3361	pLastMmio = pLastMmio->pNextR3;
3362	}
3363
3364	RTGCPHYS GCPhysLast = GCPhys + cbRange - 1;
3365	AssertLogRelReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3366
3367	/*
3368	* Find our location in the ram range list, checking for restriction
3369	* we don't bother implementing yet (partially overlapping, multiple
3370	* ram ranges).
3371	*/
3372	PGM_LOCK_VOID(pVM);
3373
3374	AssertReturnStmt(!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED), PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3375
3376	bool fRamExists = false;
3377	PPGMRAMRANGE pRamPrev = NULL;
3378	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3379	while (pRam && GCPhysLast >= pRam->GCPhys)
3380	{
3381	if ( GCPhys <= pRam->GCPhysLast
3382	&& GCPhysLast >= pRam->GCPhys)
3383	{
3384	/* Completely within? */
3385	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
3386	&& GCPhysLast <= pRam->GCPhysLast,
3387	("%RGp-%RGp (MMIOEx/%s) falls partly outside %RGp-%RGp (%s)\n",
3388	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc,
3389	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3390	PGM_UNLOCK(pVM),
3391	VERR_PGM_RAM_CONFLICT);
3392
3393	/* Check that all the pages are RAM pages. */
3394	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3395	uint32_t cPagesLeft = cbRange >> PAGE_SHIFT;
3396	while (cPagesLeft-- > 0)
3397	{
3398	AssertLogRelMsgReturnStmt(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3399	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
3400	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc),
3401	PGM_UNLOCK(pVM),
3402	VERR_PGM_RAM_CONFLICT);
3403	pPage++;
3404	}
3405
3406	/* There can only be one MMIO/MMIO2 chunk matching here! */
3407	AssertLogRelMsgReturnStmt(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK,
3408	("%RGp-%RGp (MMIOEx/%s, flags %#X) consists of multiple chunks whereas the RAM somehow doesn't!\n",
3409	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3410	PGM_UNLOCK(pVM),
3411	VERR_PGM_PHYS_MMIO_EX_IPE);
3412
3413	fRamExists = true;
3414	break;
3415	}
3416
3417	/* next */
3418	pRamPrev = pRam;
3419	pRam = pRam->pNextR3;
3420	}
3421	Log(("PGMR3PhysMmio2Map: %RGp-%RGp fRamExists=%RTbool %s\n", GCPhys, GCPhysLast, fRamExists, pFirstMmio->RamRange.pszDesc));
3422
3423
3424	/*
3425	* Make the changes.
3426	*/
3427	RTGCPHYS GCPhysCur = GCPhys;
3428	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3429	{
3430	pCurMmio->RamRange.GCPhys = GCPhysCur;
3431	pCurMmio->RamRange.GCPhysLast = GCPhysCur + pCurMmio->RamRange.cb - 1;
3432	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3433	{
3434	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3435	break;
3436	}
3437	GCPhysCur += pCurMmio->RamRange.cb;
3438	}
3439
3440	if (fRamExists)
3441	{
3442	/*
3443	* Make all the pages in the range MMIO/ZERO pages, freeing any
3444	* RAM pages currently mapped here. This might not be 100% correct
3445	* for PCI memory, but we're doing the same thing for MMIO2 pages.
3446	*
3447	* We replace these MMIO/ZERO pages with real pages in the MMIO2 case.
3448	*/
3449	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK); /* Only one chunk */
3450	Assert(pFirstMmio->pvR3 == pFirstMmio->RamRange.pvR3);
3451	Assert(pFirstMmio->RamRange.pvR3 != NULL);
3452
3453	#ifdef VBOX_WITH_PGM_NEM_MODE
3454	/* We cannot mix MMIO2 into a RAM range in simplified memory mode because pRam->pvR3 can't point
3455	both at the RAM and MMIO2, so we won't ever write & read from the actual MMIO2 memory if we try. */
3456	AssertLogRelMsgReturn(!pVM->pgm.s.fNemMode, ("%s at %RGp-%RGp\n", pFirstMmio->RamRange.pszDesc, GCPhys, GCPhysLast),
3457	VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
3458	#endif
3459
3460	int rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, pFirstMmio->RamRange.pvR3);
3461	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3462
3463	/* Replace the pages, freeing all present RAM pages. */
3464	PPGMPAGE pPageSrc = &pFirstMmio->RamRange.aPages[0];
3465	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3466	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3467	while (cPagesLeft-- > 0)
3468	{
3469	Assert(PGM_PAGE_IS_MMIO(pPageDst));
3470
3471	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
3472	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
3473	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
3474	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
3475	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
3476	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
3477	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
3478	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
3479	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
3480	/* NEM state is set by pgmR3PhysFreePageRange. */
3481
3482	pVM->pgm.s.cZeroPages--;
3483	GCPhys += PAGE_SIZE;
3484	pPageSrc++;
3485	pPageDst++;
3486	}
3487
3488	/* Flush physical page map TLB. */
3489	pgmPhysInvalidatePageMapTLB(pVM);
3490
3491	/* Force a PGM pool flush as guest ram references have been changed. */
3492	/** @todo not entirely SMP safe; assuming for now the guest takes care of
3493	* this internally (not touch mapped mmio while changing the mapping). */
3494	PVMCPU pVCpu = VMMGetCpu(pVM);
3495	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3496	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3497	}
3498	else
3499	{
3500	/*
3501	* No RAM range, insert the ones prepared during registration.
3502	*/
3503	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3504	{
3505	#ifdef VBOX_WITH_NATIVE_NEM
3506	/* Tell NEM and get the new NEM state for the pages. */
3507	uint8_t u2NemState = 0;
3508	if (VM_IS_NEM_ENABLED(pVM))
3509	{
3510	int rc = NEMR3NotifyPhysMmioExMapEarly(pVM, pCurMmio->RamRange.GCPhys,
3511	pCurMmio->RamRange.GCPhysLast - pCurMmio->RamRange.GCPhys + 1,
3512	NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2
3513	\| (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
3514	? NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES : 0),
3515	NULL /pvRam/, pCurMmio->RamRange.pvR3,
3516	&u2NemState, &pCurMmio->RamRange.uNemRange);
3517	AssertLogRelRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3518	}
3519	#endif
3520
3521	/* Clear the tracking data of pages we're going to reactivate. */
3522	PPGMPAGE pPageSrc = &pCurMmio->RamRange.aPages[0];
3523	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3524	while (cPagesLeft-- > 0)
3525	{
3526	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
3527	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
3528	#ifdef VBOX_WITH_NATIVE_NEM
3529	PGM_PAGE_SET_NEM_STATE(pPageSrc, u2NemState);
3530	#endif
3531	pPageSrc++;
3532	}
3533
3534	/* link in the ram range */
3535	pgmR3PhysLinkRamRange(pVM, &pCurMmio->RamRange, pRamPrev);
3536
3537	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3538	{
3539	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3540	break;
3541	}
3542	pRamPrev = &pCurMmio->RamRange;
3543	}
3544	}
3545
3546	/*
3547	* If the range have dirty page monitoring enabled, enable that.
3548	*
3549	* We ignore failures here for now because if we fail, the whole mapping
3550	* will have to be reversed and we'll end up with nothing at all on the
3551	* screen and a grumpy guest, whereas if we just go on, we'll only have
3552	* visual distortions to gripe about. There will be something in the
3553	* release log.
3554	*/
3555	if ( pFirstMmio->pPhysHandlerR3
3556	&& (pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3557	pgmR3PhysMmio2EnableDirtyPageTracing(pVM, pFirstMmio);
3558
3559	/*
3560	* We're good, set the flags and invalid the mapping TLB.
3561	*/
3562	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3563	{
3564	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_MAPPED;
3565	if (fRamExists)
3566	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_OVERLAPPING;
3567	else
3568	pCurMmio->fFlags &= ~PGMREGMMIO2RANGE_F_OVERLAPPING;
3569	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3570	break;
3571	}
3572	pgmPhysInvalidatePageMapTLB(pVM);
3573
3574	#ifdef VBOX_WITH_NATIVE_NEM
3575	/*
3576	* Late NEM notification.
3577	*/
3578	if (VM_IS_NEM_ENABLED(pVM))
3579	{
3580	int rc;
3581	uint32_t fNemFlags = NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2;
3582	if (pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES)
3583	fNemFlags \|= NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES;
3584	if (fRamExists)
3585	rc = NEMR3NotifyPhysMmioExMapLate(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemFlags \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
3586	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL, pFirstMmio->pvR3,
3587	NULL /puNemRange/);
3588	else
3589	{
3590	rc = VINF_SUCCESS;
3591	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3592	{
3593	rc = NEMR3NotifyPhysMmioExMapLate(pVM, pCurMmio->RamRange.GCPhys, pCurMmio->RamRange.cb, fNemFlags,
3594	NULL, pCurMmio->RamRange.pvR3, &pCurMmio->RamRange.uNemRange);
3595	if ((pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK) \|\| RT_FAILURE(rc))
3596	break;
3597	}
3598	}
3599	AssertLogRelRCReturnStmt(rc, PGMR3PhysMmio2Unmap(pVM, pDevIns, hMmio2, GCPhys); PGM_UNLOCK(pVM), rc);
3600	}
3601	#endif
3602
3603	PGM_UNLOCK(pVM);
3604
3605	return VINF_SUCCESS;
3606	}
3607
3608
3609	/**
3610	* Unmaps an MMIO2 region.
3611	*
3612	* This is typically done when a guest / the bios / state loading changes the
3613	* PCI config. The replacing of base memory has the same restrictions as during
3614	* registration, of course.
3615	*/
3616	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys)
3617	{
3618	/*
3619	* Validate input
3620	*/
3621	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3622	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3623	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3624	if (GCPhys != NIL_RTGCPHYS)
3625	{
3626	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3627	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3628	}
3629
3630	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3631	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3632	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3633
3634	int rc = PGM_LOCK(pVM);
3635	AssertRCReturn(rc, rc);
3636
3637	PPGMREGMMIO2RANGE pLastMmio = pFirstMmio;
3638	RTGCPHYS cbRange = 0;
3639	for (;;)
3640	{
3641	AssertReturnStmt(pLastMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED, PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3642	AssertReturnStmt(pLastMmio->RamRange.GCPhys == GCPhys + cbRange \|\| GCPhys == NIL_RTGCPHYS, PGM_UNLOCK(pVM), VERR_INVALID_PARAMETER);
3643	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3644	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3645	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3646	cbRange += pLastMmio->RamRange.cb;
3647	if (pLastMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3648	break;
3649	pLastMmio = pLastMmio->pNextR3;
3650	}
3651
3652	Log(("PGMR3PhysMmio2Unmap: %RGp-%RGp %s\n",
3653	pFirstMmio->RamRange.GCPhys, pLastMmio->RamRange.GCPhysLast, pFirstMmio->RamRange.pszDesc));
3654
3655	uint16_t const fOldFlags = pFirstMmio->fFlags;
3656	AssertReturnStmt(fOldFlags & PGMREGMMIO2RANGE_F_MAPPED, PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3657
3658	/*
3659	* If monitoring dirty pages, we must deregister the handlers first.
3660	*/
3661	if ( pFirstMmio->pPhysHandlerR3
3662	&& (fOldFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3663	pgmR3PhysMmio2DisableDirtyPageTracing(pVM, pFirstMmio);
3664
3665	/*
3666	* Unmap it.
3667	*/
3668	int rcRet = VINF_SUCCESS;
3669	#ifdef VBOX_WITH_NATIVE_NEM
3670	uint32_t const fNemFlags = NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2
3671	\| (fOldFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
3672	? NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES : 0);
3673	#endif
3674	if (fOldFlags & PGMREGMMIO2RANGE_F_OVERLAPPING)
3675	{
3676	/*
3677	* We've replaced RAM, replace with zero pages.
3678	*
3679	* Note! This is where we might differ a little from a real system, because
3680	* it's likely to just show the RAM pages as they were before the
3681	* MMIO/MMIO2 region was mapped here.
3682	*/
3683	/* Only one chunk allowed when overlapping! */
3684	Assert(fOldFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK);
3685
3686	/* Restore the RAM pages we've replaced. */
3687	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3688	while (pRam->GCPhys > pFirstMmio->RamRange.GCPhysLast)
3689	pRam = pRam->pNextR3;
3690
3691	PPGMPAGE pPageDst = &pRam->aPages[(pFirstMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3692	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3693	pVM->pgm.s.cZeroPages += cPagesLeft; /** @todo not correct for NEM mode */
3694
3695	#ifdef VBOX_WITH_NATIVE_NEM
3696	if (VM_IS_NEM_ENABLED(pVM)) /* Notify NEM. Note! we cannot be here in simple memory mode, see mapping function. */
3697	{
3698	uint8_t u2State = UINT8_MAX;
3699	rc = NEMR3NotifyPhysMmioExUnmap(pVM, pFirstMmio->RamRange.GCPhys, pFirstMmio->RamRange.cb,
3700	fNemFlags \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
3701	pRam->pvR3
3702	? (uint8_t *)pRam->pvR3 + pFirstMmio->RamRange.GCPhys - pRam->GCPhys : NULL,
3703	pFirstMmio->pvR3, &u2State);
3704	AssertRCStmt(rc, rcRet = rc);
3705	if (u2State != UINT8_MAX)
3706	pgmPhysSetNemStateForPages(pPageDst, cPagesLeft, u2State);
3707	}
3708	#endif
3709
3710	while (cPagesLeft-- > 0)
3711	{
3712	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3713	pPageDst++;
3714	}
3715
3716	/* Flush physical page map TLB. */
3717	pgmPhysInvalidatePageMapTLB(pVM);
3718
3719	/* Update range state. */
3720	pFirstMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3721	pFirstMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3722	pFirstMmio->fFlags &= ~(PGMREGMMIO2RANGE_F_OVERLAPPING \| PGMREGMMIO2RANGE_F_MAPPED);
3723	}
3724	else
3725	{
3726	/*
3727	* Unlink the chunks related to the MMIO/MMIO2 region.
3728	*/
3729	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3730	{
3731	#ifdef VBOX_WITH_NATIVE_NEM
3732	if (VM_IS_NEM_ENABLED(pVM)) /* Notify NEM. */
3733	{
3734	uint8_t u2State = UINT8_MAX;
3735	rc = NEMR3NotifyPhysMmioExUnmap(pVM, pCurMmio->RamRange.GCPhys, pCurMmio->RamRange.cb, fNemFlags,
3736	NULL, pCurMmio->pvR3, &u2State);
3737	AssertRCStmt(rc, rcRet = rc);
3738	if (u2State != UINT8_MAX)
3739	pgmPhysSetNemStateForPages(pCurMmio->RamRange.aPages, pCurMmio->RamRange.cb >> PAGE_SHIFT, u2State);
3740	}
3741	#endif
3742	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3743	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3744	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3745	pCurMmio->fFlags &= ~(PGMREGMMIO2RANGE_F_OVERLAPPING \| PGMREGMMIO2RANGE_F_MAPPED);
3746	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3747	break;
3748	}
3749	}
3750
3751	/* Force a PGM pool flush as guest ram references have been changed. */
3752	/** @todo not entirely SMP safe; assuming for now the guest takes care
3753	* of this internally (not touch mapped mmio while changing the
3754	* mapping). */
3755	PVMCPU pVCpu = VMMGetCpu(pVM);
3756	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3757	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3758
3759	pgmPhysInvalidatePageMapTLB(pVM);
3760	pgmPhysInvalidRamRangeTlbs(pVM);
3761
3762	PGM_UNLOCK(pVM);
3763	return rcRet;
3764	}
3765
3766
3767	/**
3768	* Reduces the mapping size of a MMIO2 region.
3769	*
3770	* This is mainly for dealing with old saved states after changing the default
3771	* size of a mapping region. See PGMDevHlpMMIOExReduce and
3772	* PDMPCIDEV::pfnRegionLoadChangeHookR3.
3773	*
3774	* The region must not currently be mapped when making this call. The VM state
3775	* must be state restore or VM construction.
3776	*
3777	* @returns VBox status code.
3778	* @param pVM The cross context VM structure.
3779	* @param pDevIns The device instance owning the region.
3780	* @param hMmio2 The handle of the region to reduce.
3781	* @param cbRegion The new mapping size.
3782	*/
3783	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion)
3784	{
3785	/*
3786	* Validate input
3787	*/
3788	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3789	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3790	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3791	AssertReturn(cbRegion >= X86_PAGE_SIZE, VERR_INVALID_PARAMETER);
3792	AssertReturn(!(cbRegion & X86_PAGE_OFFSET_MASK), VERR_UNSUPPORTED_ALIGNMENT);
3793	VMSTATE enmVmState = VMR3GetState(pVM);
3794	AssertLogRelMsgReturn( enmVmState == VMSTATE_CREATING
3795	\|\| enmVmState == VMSTATE_LOADING,
3796	("enmVmState=%d (%s)\n", enmVmState, VMR3GetStateName(enmVmState)),
3797	VERR_VM_INVALID_VM_STATE);
3798
3799	int rc = PGM_LOCK(pVM);
3800	AssertRCReturn(rc, rc);
3801
3802	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3803	if (pFirstMmio)
3804	{
3805	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3806	if (!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED))
3807	{
3808	/*
3809	* NOTE! Current implementation does not support multiple ranges.
3810	* Implement when there is a real world need and thus a testcase.
3811	*/
3812	AssertLogRelMsgStmt(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK,
3813	("%s: %#x\n", pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3814	rc = VERR_NOT_SUPPORTED);
3815	if (RT_SUCCESS(rc))
3816	{
3817	/*
3818	* Make the change.
3819	*/
3820	Log(("PGMR3PhysMmio2Reduce: %s changes from %RGp bytes (%RGp) to %RGp bytes.\n",
3821	pFirstMmio->RamRange.pszDesc, pFirstMmio->RamRange.cb, pFirstMmio->cbReal, cbRegion));
3822
3823	AssertLogRelMsgStmt(cbRegion <= pFirstMmio->cbReal,
3824	("%s: cbRegion=%#RGp cbReal=%#RGp\n", pFirstMmio->RamRange.pszDesc, cbRegion, pFirstMmio->cbReal),
3825	rc = VERR_OUT_OF_RANGE);
3826	if (RT_SUCCESS(rc))
3827	{
3828	pFirstMmio->RamRange.cb = cbRegion;
3829	}
3830	}
3831	}
3832	else
3833	rc = VERR_WRONG_ORDER;
3834	}
3835	else
3836	rc = VERR_NOT_FOUND;
3837
3838	PGM_UNLOCK(pVM);
3839	return rc;
3840	}
3841
3842
3843	/**
3844	* Validates @a hMmio2, making sure it belongs to @a pDevIns.
3845	*
3846	* @returns VBox status code.
3847	* @param pVM The cross context VM structure.
3848	* @param pDevIns The device which allegedly owns @a hMmio2.
3849	* @param hMmio2 The handle to validate.
3850	*/
3851	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3852	{
3853	/*
3854	* Validate input
3855	*/
3856	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3857	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
3858
3859	/*
3860	* Just do this the simple way. No need for locking as this is only taken at
3861	*/
3862	PGM_LOCK_VOID(pVM);
3863	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3864	PGM_UNLOCK(pVM);
3865	AssertReturn(pFirstMmio, VERR_INVALID_HANDLE);
3866	AssertReturn(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, VERR_INVALID_HANDLE);
3867	return VINF_SUCCESS;
3868	}
3869
3870
3871	/**
3872	* Gets the mapping address of an MMIO2 region.
3873	*
3874	* @returns Mapping address, NIL_RTGCPHYS if not mapped or invalid handle.
3875	*
3876	* @param pVM The cross context VM structure.
3877	* @param pDevIns The device owning the MMIO2 handle.
3878	* @param hMmio2 The region handle.
3879	*/
3880	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3881	{
3882	AssertPtrReturn(pDevIns, NIL_RTGCPHYS);
3883
3884	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3885	AssertReturn(pFirstRegMmio, NIL_RTGCPHYS);
3886
3887	if (pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3888	return pFirstRegMmio->RamRange.GCPhys;
3889	return NIL_RTGCPHYS;
3890	}
3891
3892
3893	/**
3894	* Worker for PGMR3PhysMmio2QueryAndResetDirtyBitmap.
3895	*
3896	* Called holding the PGM lock.
3897	*/
3898	static int pgmR3PhysMmio2QueryAndResetDirtyBitmapLocked(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
3899	void *pvBitmap, size_t cbBitmap)
3900	{
3901	/*
3902	* Continue validation.
3903	*/
3904	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3905	AssertReturn(pFirstRegMmio, VERR_INVALID_HANDLE);
3906	AssertReturn( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
3907	== (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK),
3908	VERR_INVALID_FUNCTION);
3909	AssertReturn(pDevIns == pFirstRegMmio->pDevInsR3, VERR_NOT_OWNER);
3910
3911	RTGCPHYS cbTotal = 0;
3912	uint16_t fTotalDirty = 0;
3913	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio;;)
3914	{
3915	cbTotal += pCur->RamRange.cb; /* Not using cbReal here, because NEM is not in on the creating, only the mapping. */
3916	fTotalDirty \|= pCur->fFlags;
3917	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3918	break;
3919	pCur = pCur->pNextR3;
3920	AssertPtrReturn(pCur, VERR_INTERNAL_ERROR_5);
3921	AssertReturn( (pCur->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
3922	== PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES,
3923	VERR_INTERNAL_ERROR_4);
3924	}
3925	size_t const cbTotalBitmap = RT_ALIGN_T(cbTotal, PAGE_SIZE * 64, RTGCPHYS) / PAGE_SIZE / 8;
3926
3927	if (cbBitmap)
3928	{
3929	AssertPtrReturn(pvBitmap, VERR_INVALID_POINTER);
3930	AssertReturn(RT_ALIGN_P(pvBitmap, sizeof(uint64_t)) == pvBitmap, VERR_INVALID_POINTER);
3931	AssertReturn(cbBitmap == cbTotalBitmap, VERR_INVALID_PARAMETER);
3932	}
3933
3934	/*
3935	* Do the work.
3936	*/
3937	int rc = VINF_SUCCESS;
3938	if (pvBitmap)
3939	{
3940	#ifdef VBOX_WITH_PGM_NEM_MODE
3941	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
3942	{
3943	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
3944	uint8_t pbBitmap = (uint8_t )pvBitmap;
3945	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3946	{
3947	size_t const cbBitmapChunk = pCur->RamRange.cb / PAGE_SIZE / 8;
3948	Assert((RTGCPHYS)cbBitmapChunk * PAGE_SIZE * 8 == pCur->RamRange.cb);
3949	int rc2 = NEMR3PhysMmio2QueryAndResetDirtyBitmap(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb,
3950	pCur->RamRange.uNemRange, pbBitmap, cbBitmapChunk);
3951	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3952	rc = rc2;
3953	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3954	break;
3955	pbBitmap += pCur->RamRange.cb / PAGE_SIZE / 8;
3956	}
3957	}
3958	else
3959	#endif
3960	if (fTotalDirty & PGMREGMMIO2RANGE_F_IS_DIRTY)
3961	{
3962	if ( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3963	== (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3964	{
3965	/*
3966	* Reset each chunk, gathering dirty bits.
3967	*/
3968	RT_BZERO(pvBitmap, cbBitmap); /* simpler for now. */
3969	uint32_t iPageNo = 0;
3970	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3971	{
3972	if (pCur->fFlags & PGMREGMMIO2RANGE_F_IS_DIRTY)
3973	{
3974	int rc2 = pgmHandlerPhysicalResetMmio2WithBitmap(pVM, pCur->RamRange.GCPhys, pvBitmap, iPageNo);
3975	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3976	rc = rc2;
3977	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
3978	}
3979	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3980	break;
3981	iPageNo += pCur->RamRange.cb >> PAGE_SHIFT;
3982	}
3983	}
3984	else
3985	{
3986	/*
3987	* If not mapped or tracking is disabled, we return the
3988	* PGMREGMMIO2RANGE_F_IS_DIRTY status for all pages. We cannot
3989	* get more accurate data than that after unmapping or disabling.
3990	*/
3991	RT_BZERO(pvBitmap, cbBitmap);
3992	uint32_t iPageNo = 0;
3993	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3994	{
3995	if (pCur->fFlags & PGMREGMMIO2RANGE_F_IS_DIRTY)
3996	{
3997	ASMBitSetRange(pvBitmap, iPageNo, iPageNo + (pCur->RamRange.cb >> PAGE_SHIFT));
3998	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
3999	}
4000	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4001	break;
4002	iPageNo += pCur->RamRange.cb >> PAGE_SHIFT;
4003	}
4004	}
4005	}
4006	/*
4007	* No dirty chunks.
4008	*/
4009	else
4010	RT_BZERO(pvBitmap, cbBitmap);
4011	}
4012	/*
4013	* No bitmap. Reset the region if tracking is currently enabled.
4014	*/
4015	else if ( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4016	== (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4017	{
4018	#ifdef VBOX_WITH_PGM_NEM_MODE
4019	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
4020	{
4021	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
4022	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
4023	{
4024	int rc2 = NEMR3PhysMmio2QueryAndResetDirtyBitmap(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb,
4025	pCur->RamRange.uNemRange, NULL, 0);
4026	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4027	rc = rc2;
4028	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4029	break;
4030	}
4031	}
4032	else
4033	#endif
4034	{
4035	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
4036	{
4037	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
4038	int rc2 = PGMHandlerPhysicalReset(pVM, pCur->RamRange.GCPhys);
4039	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4040	rc = rc2;
4041	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4042	break;
4043	}
4044	}
4045	}
4046
4047	return rc;
4048	}
4049
4050
4051	/**
4052	* Queries the dirty page bitmap and resets the monitoring.
4053	*
4054	* The PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag must be specified when
4055	* creating the range for this to work.
4056	*
4057	* @returns VBox status code.
4058	* @retval VERR_INVALID_FUNCTION if not created using
4059	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES.
4060	* @param pVM The cross context VM structure.
4061	* @param pDevIns The device owning the MMIO2 handle.
4062	* @param hMmio2 The region handle.
4063	* @param pvBitmap The output bitmap. Must be 8-byte aligned. Ignored
4064	* when @a cbBitmap is zero.
4065	* @param cbBitmap The size of the bitmap. Must be the size of the whole
4066	* MMIO2 range, rounded up to the nearest 8 bytes.
4067	* When zero only a reset is done.
4068	*/
4069	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
4070	void *pvBitmap, size_t cbBitmap)
4071	{
4072	/*
4073	* Do some basic validation before grapping the PGM lock and continuing.
4074	*/
4075	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
4076	AssertReturn(RT_ALIGN_Z(cbBitmap, sizeof(uint64_t)) == cbBitmap, VERR_INVALID_PARAMETER);
4077	int rc = PGM_LOCK(pVM);
4078	if (RT_SUCCESS(rc))
4079	{
4080	STAM_PROFILE_START(&pVM->pgm.s.StatMmio2QueryAndResetDirtyBitmap, a);
4081	rc = pgmR3PhysMmio2QueryAndResetDirtyBitmapLocked(pVM, pDevIns, hMmio2, pvBitmap, cbBitmap);
4082	STAM_PROFILE_STOP(&pVM->pgm.s.StatMmio2QueryAndResetDirtyBitmap, a);
4083	PGM_UNLOCK(pVM);
4084	}
4085	return rc;
4086	}
4087
4088	/**
4089	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking
4090	*
4091	* Called owning the PGM lock.
4092	*/
4093	static int pgmR3PhysMmio2ControlDirtyPageTrackingLocked(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled)
4094	{
4095	/*
4096	* Continue validation.
4097	*/
4098	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
4099	AssertReturn(pFirstRegMmio, VERR_INVALID_HANDLE);
4100	AssertReturn( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
4101	== (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK)
4102	, VERR_INVALID_FUNCTION);
4103	AssertReturn(pDevIns == pFirstRegMmio->pDevInsR3, VERR_NOT_OWNER);
4104
4105	#ifdef VBOX_WITH_PGM_NEM_MODE
4106	/*
4107	* This is a nop if NEM is responsible for doing the tracking, we simply
4108	* leave the tracking on all the time there.
4109	*/
4110	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
4111	{
4112	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
4113	return VINF_SUCCESS;
4114	}
4115	#endif
4116
4117	/*
4118	* Anyting needing doing?
4119	*/
4120	if (fEnabled != RT_BOOL(pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4121	{
4122	LogFlowFunc(("fEnabled=%RTbool %s\n", fEnabled, pFirstRegMmio->RamRange.pszDesc));
4123
4124	/*
4125	* Update the PGMREGMMIO2RANGE_F_TRACKING_ENABLED flag.
4126	*/
4127	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio;;)
4128	{
4129	if (fEnabled)
4130	pCur->fFlags \|= PGMREGMMIO2RANGE_F_TRACKING_ENABLED;
4131	else
4132	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_TRACKING_ENABLED;
4133	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4134	break;
4135	pCur = pCur->pNextR3;
4136	AssertPtrReturn(pCur, VERR_INTERNAL_ERROR_5);
4137	AssertReturn( (pCur->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
4138	== PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
4139	, VERR_INTERNAL_ERROR_4);
4140	}
4141
4142	/*
4143	* Enable/disable handlers if currently mapped.
4144	*
4145	* We ignore status codes here as we've already changed the flags and
4146	* returning a failure status now would be confusing. Besides, the two
4147	* functions will continue past failures. As argued in the mapping code,
4148	* it's in the release log.
4149	*/
4150	if (pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED)
4151	{
4152	if (fEnabled)
4153	pgmR3PhysMmio2EnableDirtyPageTracing(pVM, pFirstRegMmio);
4154	else
4155	pgmR3PhysMmio2DisableDirtyPageTracing(pVM, pFirstRegMmio);
4156	}
4157	}
4158	else
4159	LogFlowFunc(("fEnabled=%RTbool %s - no change\n", fEnabled, pFirstRegMmio->RamRange.pszDesc));
4160
4161	return VINF_SUCCESS;
4162	}
4163
4164
4165	/**
4166	* Controls the dirty page tracking for an MMIO2 range.
4167	*
4168	* @returns VBox status code.
4169	* @param pVM The cross context VM structure.
4170	* @param pDevIns The device owning the MMIO2 memory.
4171	* @param hMmio2 The handle of the region.
4172	* @param fEnabled The new tracking state.
4173	*/
4174	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled)
4175	{
4176	/*
4177	* Do some basic validation before grapping the PGM lock and continuing.
4178	*/
4179	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
4180	int rc = PGM_LOCK(pVM);
4181	if (RT_SUCCESS(rc))
4182	{
4183	rc = pgmR3PhysMmio2ControlDirtyPageTrackingLocked(pVM, pDevIns, hMmio2, fEnabled);
4184	PGM_UNLOCK(pVM);
4185	}
4186	return rc;
4187	}
4188
4189
4190	/**
4191	* Changes the region number of an MMIO2 region.
4192	*
4193	* This is only for dealing with save state issues, nothing else.
4194	*
4195	* @return VBox status code.
4196	*
4197	* @param pVM The cross context VM structure.
4198	* @param pDevIns The device owning the MMIO2 memory.
4199	* @param hMmio2 The handle of the region.
4200	* @param iNewRegion The new region index.
4201	*
4202	* @thread EMT(0)
4203	* @sa @bugref{9359}
4204	*/
4205	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion)
4206	{
4207	/*
4208	* Validate input.
4209	*/
4210	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4211	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_LOADING, VERR_VM_INVALID_VM_STATE);
4212	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4213	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
4214	AssertReturn(iNewRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4215
4216	AssertReturn(pVM->enmVMState == VMSTATE_LOADING, VERR_INVALID_STATE);
4217
4218	int rc = PGM_LOCK(pVM);
4219	AssertRCReturn(rc, rc);
4220
4221	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
4222	AssertReturnStmt(pFirstRegMmio, PGM_UNLOCK(pVM), VERR_NOT_FOUND);
4223	AssertReturnStmt(pgmR3PhysMmio2Find(pVM, pDevIns, pFirstRegMmio->iSubDev, iNewRegion, NIL_PGMMMIO2HANDLE) == NULL,
4224	PGM_UNLOCK(pVM), VERR_RESOURCE_IN_USE);
4225
4226	/*
4227	* Make the change.
4228	*/
4229	pFirstRegMmio->iRegion = (uint8_t)iNewRegion;
4230
4231	PGM_UNLOCK(pVM);
4232	return VINF_SUCCESS;
4233	}
4234
4235
4236
4237	/*********************************************************************************************************************************
4238	* ROM *
4239	*********************************************************************************************************************************/
4240
4241	/**
4242	* Worker for PGMR3PhysRomRegister.
4243	*
4244	* This is here to simplify lock management, i.e. the caller does all the
4245	* locking and we can simply return without needing to remember to unlock
4246	* anything first.
4247	*
4248	* @returns VBox status code.
4249	* @param pVM The cross context VM structure.
4250	* @param pDevIns The device instance owning the ROM.
4251	* @param GCPhys First physical address in the range.
4252	* Must be page aligned!
4253	* @param cb The size of the range (in bytes).
4254	* Must be page aligned!
4255	* @param pvBinary Pointer to the binary data backing the ROM image.
4256	* @param cbBinary The size of the binary data pvBinary points to.
4257	* This must be less or equal to @a cb.
4258	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4259	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4260	* @param pszDesc Pointer to description string. This must not be freed.
4261	*/
4262	static int pgmR3PhysRomRegisterLocked(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4263	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc)
4264	{
4265	/*
4266	* Validate input.
4267	*/
4268	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4269	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
4270	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
4271	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4272	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4273	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
4274	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
4275	AssertReturn(!(fFlags & ~PGMPHYS_ROM_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
4276	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
4277
4278	const uint32_t cPages = cb >> PAGE_SHIFT;
4279
4280	/*
4281	* Find the ROM location in the ROM list first.
4282	*/
4283	PPGMROMRANGE pRomPrev = NULL;
4284	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
4285	while (pRom && GCPhysLast >= pRom->GCPhys)
4286	{
4287	if ( GCPhys <= pRom->GCPhysLast
4288	&& GCPhysLast >= pRom->GCPhys)
4289	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
4290	GCPhys, GCPhysLast, pszDesc,
4291	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
4292	VERR_PGM_RAM_CONFLICT);
4293	/* next */
4294	pRomPrev = pRom;
4295	pRom = pRom->pNextR3;
4296	}
4297
4298	/*
4299	* Find the RAM location and check for conflicts.
4300	*
4301	* Conflict detection is a bit different than for RAM registration since a
4302	* ROM can be located within a RAM range. So, what we have to check for is
4303	* other memory types (other than RAM that is) and that we don't span more
4304	* than one RAM range (lazy).
4305	*/
4306	bool fRamExists = false;
4307	PPGMRAMRANGE pRamPrev = NULL;
4308	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4309	while (pRam && GCPhysLast >= pRam->GCPhys)
4310	{
4311	if ( GCPhys <= pRam->GCPhysLast
4312	&& GCPhysLast >= pRam->GCPhys)
4313	{
4314	/* completely within? */
4315	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
4316	&& GCPhysLast <= pRam->GCPhysLast,
4317	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
4318	GCPhys, GCPhysLast, pszDesc,
4319	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
4320	VERR_PGM_RAM_CONFLICT);
4321	fRamExists = true;
4322	break;
4323	}
4324
4325	/* next */
4326	pRamPrev = pRam;
4327	pRam = pRam->pNextR3;
4328	}
4329	if (fRamExists)
4330	{
4331	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4332	uint32_t cPagesLeft = cPages;
4333	while (cPagesLeft-- > 0)
4334	{
4335	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
4336	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
4337	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
4338	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
4339	Assert(PGM_PAGE_IS_ZERO(pPage) \|\| PGM_IS_IN_NEM_MODE(pVM));
4340	pPage++;
4341	}
4342	}
4343
4344	/*
4345	* Update the base memory reservation if necessary.
4346	*/
4347	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
4348	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4349	cExtraBaseCost += cPages;
4350	if (cExtraBaseCost)
4351	{
4352	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
4353	if (RT_FAILURE(rc))
4354	return rc;
4355	}
4356
4357	#ifdef VBOX_WITH_NATIVE_NEM
4358	/*
4359	* Early NEM notification before we've made any changes or anything.
4360	*/
4361	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_ROM_F_REPLACE : 0)
4362	\| (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED ? NEM_NOTIFY_PHYS_ROM_F_SHADOW : 0);
4363	uint8_t u2NemState = UINT8_MAX;
4364	if (VM_IS_NEM_ENABLED(pVM))
4365	{
4366	int rc = NEMR3NotifyPhysRomRegisterEarly(pVM, GCPhys, cPages << PAGE_SHIFT,
4367	fRamExists ? PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhys) : NULL,
4368	fNemNotify, &u2NemState);
4369	AssertLogRelRCReturn(rc, rc);
4370	}
4371	#endif
4372
4373	/*
4374	* Allocate memory for the virgin copy of the RAM. In simplified memory mode,
4375	* we allocate memory for any ad-hoc RAM range and for shadow pages.
4376	*/
4377	PGMMALLOCATEPAGESREQ pReq = NULL;
4378	#ifdef VBOX_WITH_PGM_NEM_MODE
4379	void *pvRam = NULL;
4380	void *pvAlt = NULL;
4381	if (pVM->pgm.s.fNemMode)
4382	{
4383	if (!fRamExists)
4384	{
4385	int rc = SUPR3PageAlloc(cPages, &pvRam);
4386	if (RT_FAILURE(rc))
4387	return rc;
4388	}
4389	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4390	{
4391	int rc = SUPR3PageAlloc(cPages, &pvAlt);
4392	if (RT_FAILURE(rc))
4393	{
4394	if (pvRam)
4395	SUPR3PageFree(pvRam, cPages);
4396	return rc;
4397	}
4398	}
4399	}
4400	else
4401	#endif
4402	{
4403	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
4404	AssertRCReturn(rc, rc);
4405
4406	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4407	{
4408	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
4409	pReq->aPages[iPage].fZeroed = false;
4410	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
4411	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
4412	}
4413
4414	rc = GMMR3AllocatePagesPerform(pVM, pReq);
4415	if (RT_FAILURE(rc))
4416	{
4417	GMMR3AllocatePagesCleanup(pReq);
4418	return rc;
4419	}
4420	}
4421
4422	/*
4423	* Allocate the new ROM range and RAM range (if necessary).
4424	*/
4425	PPGMROMRANGE pRomNew;
4426	int rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
4427	if (RT_SUCCESS(rc))
4428	{
4429	PPGMRAMRANGE pRamNew = NULL;
4430	if (!fRamExists)
4431	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
4432	if (RT_SUCCESS(rc))
4433	{
4434	/*
4435	* Initialize and insert the RAM range (if required).
4436	*/
4437	uint32_t const idxFirstRamPage = fRamExists ? (GCPhys - pRam->GCPhys) >> PAGE_SHIFT : 0;
4438	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
4439	if (!fRamExists)
4440	{
4441	/* New RAM range. */
4442	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
4443	pRamNew->GCPhys = GCPhys;
4444	pRamNew->GCPhysLast = GCPhysLast;
4445	pRamNew->cb = cb;
4446	pRamNew->pszDesc = pszDesc;
4447	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
4448	pRamNew->pvR3 = NULL;
4449	pRamNew->paLSPages = NULL;
4450
4451	PPGMPAGE pRamPage = &pRamNew->aPages[idxFirstRamPage];
4452	#ifdef VBOX_WITH_PGM_NEM_MODE
4453	if (pVM->pgm.s.fNemMode)
4454	{
4455	AssertPtr(pvRam); Assert(pReq == NULL);
4456	pRamNew->pvR3 = pvRam;
4457	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4458	{
4459	PGM_PAGE_INIT(pRamPage, UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
4460	PGMPAGETYPE_ROM, PGM_PAGE_STATE_ALLOCATED);
4461	pRomPage->Virgin = *pRamPage;
4462	}
4463	}
4464	else
4465	#endif
4466	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4467	{
4468	PGM_PAGE_INIT(pRamPage,
4469	pReq->aPages[iPage].HCPhysGCPhys,
4470	pReq->aPages[iPage].idPage,
4471	PGMPAGETYPE_ROM,
4472	PGM_PAGE_STATE_ALLOCATED);
4473
4474	pRomPage->Virgin = *pRamPage;
4475	}
4476
4477	pVM->pgm.s.cAllPages += cPages;
4478	pVM->pgm.s.cPrivatePages += cPages;
4479	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
4480	}
4481	else
4482	{
4483	/* Existing RAM range. */
4484	PPGMPAGE pRamPage = &pRam->aPages[idxFirstRamPage];
4485	#ifdef VBOX_WITH_PGM_NEM_MODE
4486	if (pVM->pgm.s.fNemMode)
4487	{
4488	Assert(pvRam == NULL); Assert(pReq == NULL);
4489	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4490	{
4491	Assert(PGM_PAGE_GET_HCPHYS(pRamPage) == UINT64_C(0x0000fffffffff000));
4492	Assert(PGM_PAGE_GET_PAGEID(pRamPage) == NIL_GMM_PAGEID);
4493	Assert(PGM_PAGE_GET_STATE(pRamPage) == PGM_PAGE_STATE_ALLOCATED);
4494	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_ROM);
4495	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4496	PGM_PAGE_SET_PDE_TYPE(pVM, pRamPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4497	PGM_PAGE_SET_PTE_INDEX(pVM, pRamPage, 0);
4498	PGM_PAGE_SET_TRACKING(pVM, pRamPage, 0);
4499
4500	pRomPage->Virgin = *pRamPage;
4501	}
4502	}
4503	else
4504	#endif
4505	{
4506	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4507	{
4508	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_ROM);
4509	PGM_PAGE_SET_HCPHYS(pVM, pRamPage, pReq->aPages[iPage].HCPhysGCPhys);
4510	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4511	PGM_PAGE_SET_PAGEID(pVM, pRamPage, pReq->aPages[iPage].idPage);
4512	PGM_PAGE_SET_PDE_TYPE(pVM, pRamPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4513	PGM_PAGE_SET_PTE_INDEX(pVM, pRamPage, 0);
4514	PGM_PAGE_SET_TRACKING(pVM, pRamPage, 0);
4515
4516	pRomPage->Virgin = *pRamPage;
4517	}
4518	pVM->pgm.s.cZeroPages -= cPages;
4519	pVM->pgm.s.cPrivatePages += cPages;
4520	}
4521	pRamNew = pRam;
4522	}
4523
4524	#ifdef VBOX_WITH_NATIVE_NEM
4525	/* Set the NEM state of the pages if needed. */
4526	if (u2NemState != UINT8_MAX)
4527	pgmPhysSetNemStateForPages(&pRamNew->aPages[idxFirstRamPage], cPages, u2NemState);
4528	#endif
4529
4530	/* Flush physical page map TLB. */
4531	pgmPhysInvalidatePageMapTLB(pVM);
4532
4533	/*
4534	* Register the ROM access handler.
4535	*/
4536	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4537	pRomNew, MMHyperCCToR0(pVM, pRomNew), NIL_RTRCPTR, pszDesc);
4538	if (RT_SUCCESS(rc))
4539	{
4540	/*
4541	* Copy the image over to the virgin pages.
4542	* This must be done after linking in the RAM range.
4543	*/
4544	size_t cbBinaryLeft = cbBinary;
4545	PPGMPAGE pRamPage = &pRamNew->aPages[idxFirstRamPage];
4546	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4547	{
4548	void *pvDstPage;
4549	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
4550	if (RT_FAILURE(rc))
4551	{
4552	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
4553	break;
4554	}
4555	if (cbBinaryLeft >= PAGE_SIZE)
4556	{
4557	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
4558	cbBinaryLeft -= PAGE_SIZE;
4559	}
4560	else
4561	{
4562	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
4563	if (cbBinaryLeft > 0)
4564	{
4565	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
4566	cbBinaryLeft = 0;
4567	}
4568	}
4569	}
4570	if (RT_SUCCESS(rc))
4571	{
4572	/*
4573	* Initialize the ROM range.
4574	* Note that the Virgin member of the pages has already been initialized above.
4575	*/
4576	pRomNew->GCPhys = GCPhys;
4577	pRomNew->GCPhysLast = GCPhysLast;
4578	pRomNew->cb = cb;
4579	pRomNew->fFlags = fFlags;
4580	pRomNew->idSavedState = UINT8_MAX;
4581	pRomNew->cbOriginal = cbBinary;
4582	pRomNew->pszDesc = pszDesc;
4583	#ifdef VBOX_WITH_PGM_NEM_MODE
4584	pRomNew->pbR3Alternate = (uint8_t *)pvAlt;
4585	#endif
4586	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
4587	? pvBinary : RTMemDup(pvBinary, cbBinary);
4588	if (pRomNew->pvOriginal)
4589	{
4590	for (unsigned iPage = 0; iPage < cPages; iPage++)
4591	{
4592	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
4593	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
4594	#ifdef VBOX_WITH_PGM_NEM_MODE
4595	if (pVM->pgm.s.fNemMode)
4596	PGM_PAGE_INIT(&pPage->Shadow, UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
4597	PGMPAGETYPE_ROM_SHADOW, PGM_PAGE_STATE_ALLOCATED);
4598	else
4599	#endif
4600	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
4601	}
4602
4603	/* update the page count stats for the shadow pages. */
4604	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4605	{
4606	#ifdef VBOX_WITH_PGM_NEM_MODE
4607	if (pVM->pgm.s.fNemMode)
4608	pVM->pgm.s.cPrivatePages += cPages;
4609	else
4610	#endif
4611	pVM->pgm.s.cZeroPages += cPages;
4612	pVM->pgm.s.cAllPages += cPages;
4613	}
4614
4615	/*
4616	* Insert the ROM range, tell REM and return successfully.
4617	*/
4618	pRomNew->pNextR3 = pRom;
4619	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4620
4621	if (pRomPrev)
4622	{
4623	pRomPrev->pNextR3 = pRomNew;
4624	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
4625	}
4626	else
4627	{
4628	pVM->pgm.s.pRomRangesR3 = pRomNew;
4629	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
4630	}
4631
4632	pgmPhysInvalidatePageMapTLB(pVM);
4633	#ifdef VBOX_WITH_PGM_NEM_MODE
4634	if (!pVM->pgm.s.fNemMode)
4635	#endif
4636	GMMR3AllocatePagesCleanup(pReq);
4637
4638	#ifdef VBOX_WITH_NATIVE_NEM
4639	/*
4640	* Notify NEM again.
4641	*/
4642	if (VM_IS_NEM_ENABLED(pVM))
4643	{
4644	u2NemState = UINT8_MAX;
4645	rc = NEMR3NotifyPhysRomRegisterLate(pVM, GCPhys, cb, PGM_RAMRANGE_CALC_PAGE_R3PTR(pRamNew, GCPhys),
4646	fNemNotify, &u2NemState);
4647	if (u2NemState != UINT8_MAX)
4648	pgmPhysSetNemStateForPages(&pRamNew->aPages[idxFirstRamPage], cPages, u2NemState);
4649	if (RT_SUCCESS(rc))
4650	return rc;
4651	}
4652	else
4653	#endif
4654	return rc;
4655
4656	/*
4657	* bail out
4658	*/
4659	#ifdef VBOX_WITH_NATIVE_NEM
4660	/* unlink */
4661	if (pRomPrev)
4662	{
4663	pRomPrev->pNextR3 = pRom;
4664	pRomPrev->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4665	}
4666	else
4667	{
4668	pVM->pgm.s.pRomRangesR3 = pRom;
4669	pVM->pgm.s.pRomRangesR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4670	}
4671
4672	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4673	{
4674	# ifdef VBOX_WITH_PGM_NEM_MODE
4675	if (pVM->pgm.s.fNemMode)
4676	pVM->pgm.s.cPrivatePages -= cPages;
4677	else
4678	# endif
4679	pVM->pgm.s.cZeroPages -= cPages;
4680	pVM->pgm.s.cAllPages -= cPages;
4681	}
4682	#endif
4683	}
4684	else
4685	rc = VERR_NO_MEMORY;
4686	}
4687
4688	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
4689	AssertRC(rc2);
4690	}
4691
4692	if (!fRamExists)
4693	{
4694	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
4695	MMHyperFree(pVM, pRamNew);
4696	}
4697	else
4698	{
4699	PPGMPAGE pRamPage = &pRam->aPages[idxFirstRamPage];
4700	#ifdef VBOX_WITH_PGM_NEM_MODE
4701	if (pVM->pgm.s.fNemMode)
4702	{
4703	Assert(pvRam == NULL); Assert(pReq == NULL);
4704	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4705	{
4706	Assert(PGM_PAGE_GET_HCPHYS(pRamPage) == UINT64_C(0x0000fffffffff000));
4707	Assert(PGM_PAGE_GET_PAGEID(pRamPage) == NIL_GMM_PAGEID);
4708	Assert(PGM_PAGE_GET_STATE(pRamPage) == PGM_PAGE_STATE_ALLOCATED);
4709	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_RAM);
4710	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4711	}
4712	}
4713	else
4714	#endif
4715	{
4716	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4717	PGM_PAGE_INIT_ZERO(pRamPage, pVM, PGMPAGETYPE_RAM);
4718	pVM->pgm.s.cZeroPages += cPages;
4719	pVM->pgm.s.cPrivatePages -= cPages;
4720	}
4721	}
4722	}
4723	MMHyperFree(pVM, pRomNew);
4724	}
4725
4726	/** @todo Purge the mapping cache or something... */
4727	#ifdef VBOX_WITH_PGM_NEM_MODE
4728	if (pVM->pgm.s.fNemMode)
4729	{
4730	Assert(!pReq);
4731	if (pvRam)
4732	SUPR3PageFree(pvRam, cPages);
4733	if (pvAlt)
4734	SUPR3PageFree(pvAlt, cPages);
4735	}
4736	else
4737	#endif
4738	{
4739	GMMR3FreeAllocatedPages(pVM, pReq);
4740	GMMR3AllocatePagesCleanup(pReq);
4741	}
4742	return rc;
4743	}
4744
4745
4746	/**
4747	* Registers a ROM image.
4748	*
4749	* Shadowed ROM images requires double the amount of backing memory, so,
4750	* don't use that unless you have to. Shadowing of ROM images is process
4751	* where we can select where the reads go and where the writes go. On real
4752	* hardware the chipset provides means to configure this. We provide
4753	* PGMR3PhysProtectROM() for this purpose.
4754	*
4755	* A read-only copy of the ROM image will always be kept around while we
4756	* will allocate RAM pages for the changes on demand (unless all memory
4757	* is configured to be preallocated).
4758	*
4759	* @returns VBox status code.
4760	* @param pVM The cross context VM structure.
4761	* @param pDevIns The device instance owning the ROM.
4762	* @param GCPhys First physical address in the range.
4763	* Must be page aligned!
4764	* @param cb The size of the range (in bytes).
4765	* Must be page aligned!
4766	* @param pvBinary Pointer to the binary data backing the ROM image.
4767	* @param cbBinary The size of the binary data pvBinary points to.
4768	* This must be less or equal to @a cb.
4769	* @param fFlags Mask of flags, PGMPHYS_ROM_FLAGS_XXX.
4770	* @param pszDesc Pointer to description string. This must not be freed.
4771	*
4772	* @remark There is no way to remove the rom, automatically on device cleanup or
4773	* manually from the device yet. This isn't difficult in any way, it's
4774	* just not something we expect to be necessary for a while.
4775	*/
4776	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4777	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc)
4778	{
4779	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
4780	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
4781	PGM_LOCK_VOID(pVM);
4782	int rc = pgmR3PhysRomRegisterLocked(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
4783	PGM_UNLOCK(pVM);
4784	return rc;
4785	}
4786
4787
4788	/**
4789	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
4790	* that the virgin part is untouched.
4791	*
4792	* This is done after the normal memory has been cleared.
4793	*
4794	* ASSUMES that the caller owns the PGM lock.
4795	*
4796	* @param pVM The cross context VM structure.
4797	*/
4798	int pgmR3PhysRomReset(PVM pVM)
4799	{
4800	PGM_LOCK_ASSERT_OWNER(pVM);
4801	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4802	{
4803	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
4804
4805	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4806	{
4807	/*
4808	* Reset the physical handler.
4809	*/
4810	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
4811	AssertRCReturn(rc, rc);
4812
4813	/*
4814	* What we do with the shadow pages depends on the memory
4815	* preallocation option. If not enabled, we'll just throw
4816	* out all the dirty pages and replace them by the zero page.
4817	*/
4818	#ifdef VBOX_WITH_PGM_NEM_MODE
4819	if (pVM->pgm.s.fNemMode)
4820	{
4821	/* Clear all the shadow pages (currently using alternate backing). */
4822	RT_BZERO(pRom->pbR3Alternate, pRom->cb);
4823	}
4824	else
4825	#endif
4826	if (!pVM->pgm.s.fRamPreAlloc)
4827	{
4828	/* Free the dirty pages. */
4829	uint32_t cPendingPages = 0;
4830	PGMMFREEPAGESREQ pReq;
4831	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4832	AssertRCReturn(rc, rc);
4833
4834	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4835	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
4836	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
4837	{
4838	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
4839	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
4840	pRom->GCPhys + (iPage << PAGE_SHIFT),
4841	(PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pRom->aPages[iPage].Shadow));
4842	AssertLogRelRCReturn(rc, rc);
4843	}
4844
4845	if (cPendingPages)
4846	{
4847	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
4848	AssertLogRelRCReturn(rc, rc);
4849	}
4850	GMMR3FreePagesCleanup(pReq);
4851	}
4852	else
4853	{
4854	/* clear all the shadow pages. */
4855	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4856	{
4857	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
4858	continue;
4859	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
4860	void *pvDstPage;
4861	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4862	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
4863	if (RT_FAILURE(rc))
4864	break;
4865	ASMMemZeroPage(pvDstPage);
4866	}
4867	AssertRCReturn(rc, rc);
4868	}
4869	}
4870
4871	/*
4872	* Restore the original ROM pages after a saved state load.
4873	* Also, in strict builds check that ROM pages remain unmodified.
4874	*/
4875	#ifndef VBOX_STRICT
4876	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4877	#endif
4878	{
4879	size_t cbSrcLeft = pRom->cbOriginal;
4880	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
4881	uint32_t cRestored = 0;
4882	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
4883	{
4884	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4885	PPGMPAGE const pPage = pgmPhysGetPage(pVM, GCPhys);
4886	void const *pvDstPage = NULL;
4887	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvDstPage);
4888	if (RT_FAILURE(rc))
4889	break;
4890
4891	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
4892	{
4893	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4894	{
4895	void *pvDstPageW = NULL;
4896	rc = pgmPhysPageMap(pVM, pPage, GCPhys, &pvDstPageW);
4897	AssertLogRelRCReturn(rc, rc);
4898	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
4899	cRestored++;
4900	}
4901	else
4902	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
4903	}
4904	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
4905	}
4906	if (cRestored > 0)
4907	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
4908	}
4909	}
4910
4911	/* Clear the ROM restore flag now as we only need to do this once after
4912	loading saved state. */
4913	pVM->pgm.s.fRestoreRomPagesOnReset = false;
4914
4915	return VINF_SUCCESS;
4916	}
4917
4918
4919	/**
4920	* Called by PGMR3Term to free resources.
4921	*
4922	* ASSUMES that the caller owns the PGM lock.
4923	*
4924	* @param pVM The cross context VM structure.
4925	*/
4926	void pgmR3PhysRomTerm(PVM pVM)
4927	{
4928	/*
4929	* Free the heap copy of the original bits.
4930	*/
4931	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4932	{
4933	if ( pRom->pvOriginal
4934	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
4935	{
4936	RTMemFree((void *)pRom->pvOriginal);
4937	pRom->pvOriginal = NULL;
4938	}
4939	}
4940	}
4941
4942
4943	/**
4944	* Change the shadowing of a range of ROM pages.
4945	*
4946	* This is intended for implementing chipset specific memory registers
4947	* and will not be very strict about the input. It will silently ignore
4948	* any pages that are not the part of a shadowed ROM.
4949	*
4950	* @returns VBox status code.
4951	* @retval VINF_PGM_SYNC_CR3
4952	*
4953	* @param pVM The cross context VM structure.
4954	* @param GCPhys Where to start. Page aligned.
4955	* @param cb How much to change. Page aligned.
4956	* @param enmProt The new ROM protection.
4957	*/
4958	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
4959	{
4960	/*
4961	* Check input
4962	*/
4963	if (!cb)
4964	return VINF_SUCCESS;
4965	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4966	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4967	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4968	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4969	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
4970
4971	/*
4972	* Process the request.
4973	*/
4974	PGM_LOCK_VOID(pVM);
4975	int rc = VINF_SUCCESS;
4976	bool fFlushTLB = false;
4977	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4978	{
4979	if ( GCPhys <= pRom->GCPhysLast
4980	&& GCPhysLast >= pRom->GCPhys
4981	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
4982	{
4983	/*
4984	* Iterate the relevant pages and make necessary the changes.
4985	*/
4986	#ifdef VBOX_WITH_NATIVE_NEM
4987	PPGMRAMRANGE const pRam = pgmPhysGetRange(pVM, GCPhys);
4988	AssertPtrReturn(pRam, VERR_INTERNAL_ERROR_3);
4989	#endif
4990	bool fChanges = false;
4991	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
4992	? pRom->cb >> PAGE_SHIFT
4993	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
4994	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
4995	iPage < cPages;
4996	iPage++)
4997	{
4998	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
4999	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
5000	{
5001	fChanges = true;
5002
5003	/* flush references to the page. */
5004	RTGCPHYS const GCPhysPage = pRom->GCPhys + (iPage << PAGE_SHIFT);
5005	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, GCPhysPage);
5006	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pRamPage, true /fFlushPTEs/, &fFlushTLB);
5007	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
5008	rc = rc2;
5009	#ifdef VBOX_WITH_NATIVE_NEM
5010	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pRamPage);
5011	#endif
5012
5013	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
5014	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
5015
5016	pOld = pRamPage;
5017	pRamPage = pNew;
5018	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
5019
5020	#ifdef VBOX_WITH_NATIVE_NEM
5021	# ifdef VBOX_WITH_PGM_NEM_MODE
5022	/* In simplified mode we have to switch the page data around too. */
5023	if (pVM->pgm.s.fNemMode)
5024	{
5025	uint8_t abPage[PAGE_SIZE];
5026	uint8_t * const pbRamPage = PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhysPage);
5027	memcpy(abPage, &pRom->pbR3Alternate[(size_t)iPage << PAGE_SHIFT], sizeof(abPage));
5028	memcpy(&pRom->pbR3Alternate[(size_t)iPage << PAGE_SHIFT], pbRamPage, sizeof(abPage));
5029	memcpy(pbRamPage, abPage, sizeof(abPage));
5030	}
5031	# endif
5032	/* Tell NEM about the backing and protection change. */
5033	if (VM_IS_NEM_ENABLED(pVM))
5034	{
5035	PGMPAGETYPE enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pNew);
5036	NEMHCNotifyPhysPageChanged(pVM, GCPhys, PGM_PAGE_GET_HCPHYS(pOld), PGM_PAGE_GET_HCPHYS(pNew),
5037	PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhysPage),
5038	pgmPhysPageCalcNemProtection(pRamPage, enmType), enmType, &u2State);
5039	PGM_PAGE_SET_NEM_STATE(pRamPage, u2State);
5040	}
5041	#endif
5042	}
5043	pRomPage->enmProt = enmProt;
5044	}
5045
5046	/*
5047	* Reset the access handler if we made changes, no need
5048	* to optimize this.
5049	*/
5050	if (fChanges)
5051	{
5052	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
5053	if (RT_FAILURE(rc2))
5054	{
5055	PGM_UNLOCK(pVM);
5056	AssertRC(rc);
5057	return rc2;
5058	}
5059	}
5060
5061	/* Advance - cb isn't updated. */
5062	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
5063	}
5064	}
5065	PGM_UNLOCK(pVM);
5066	if (fFlushTLB)
5067	PGM_INVL_ALL_VCPU_TLBS(pVM);
5068
5069	return rc;
5070	}
5071
5072
5073
5074	/*********************************************************************************************************************************
5075	* Ballooning *
5076	*********************************************************************************************************************************/
5077
5078	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
5079
5080	/**
5081	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
5082	*
5083	* This is only called on one of the EMTs while the other ones are waiting for
5084	* it to complete this function.
5085	*
5086	* @returns VINF_SUCCESS (VBox strict status code).
5087	* @param pVM The cross context VM structure.
5088	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5089	* @param pvUser User parameter
5090	*/
5091	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5092	{
5093	uintptr_t paUser = (uintptr_t )pvUser;
5094	bool fInflate = !!paUser[0];
5095	unsigned cPages = paUser[1];
5096	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
5097	uint32_t cPendingPages = 0;
5098	PGMMFREEPAGESREQ pReq;
5099	int rc;
5100
5101	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
5102	PGM_LOCK_VOID(pVM);
5103
5104	if (fInflate)
5105	{
5106	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
5107	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
5108
5109	/* Replace pages with ZERO pages. */
5110	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
5111	if (RT_FAILURE(rc))
5112	{
5113	PGM_UNLOCK(pVM);
5114	AssertLogRelRC(rc);
5115	return rc;
5116	}
5117
5118	/* Iterate the pages. */
5119	for (unsigned i = 0; i < cPages; i++)
5120	{
5121	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
5122	if ( pPage == NULL
5123	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
5124	{
5125	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
5126	break;
5127	}
5128
5129	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
5130
5131	/* Flush the shadow PT if this page was previously used as a guest page table. */
5132	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
5133
5134	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i], (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
5135	if (RT_FAILURE(rc))
5136	{
5137	PGM_UNLOCK(pVM);
5138	AssertLogRelRC(rc);
5139	return rc;
5140	}
5141	Assert(PGM_PAGE_IS_ZERO(pPage));
5142	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
5143	}
5144
5145	if (cPendingPages)
5146	{
5147	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
5148	if (RT_FAILURE(rc))
5149	{
5150	PGM_UNLOCK(pVM);
5151	AssertLogRelRC(rc);
5152	return rc;
5153	}
5154	}
5155	GMMR3FreePagesCleanup(pReq);
5156	}
5157	else
5158	{
5159	/* Iterate the pages. */
5160	for (unsigned i = 0; i < cPages; i++)
5161	{
5162	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
5163	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
5164
5165	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
5166
5167	Assert(PGM_PAGE_IS_BALLOONED(pPage));
5168
5169	/* Change back to zero page. (NEM does not need to be informed.) */
5170	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
5171	}
5172
5173	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
5174	}
5175
5176	/* Notify GMM about the balloon change. */
5177	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
5178	if (RT_SUCCESS(rc))
5179	{
5180	if (!fInflate)
5181	{
5182	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
5183	pVM->pgm.s.cBalloonedPages -= cPages;
5184	}
5185	else
5186	pVM->pgm.s.cBalloonedPages += cPages;
5187	}
5188
5189	PGM_UNLOCK(pVM);
5190
5191	/* Flush the recompiler's TLB as well. */
5192	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5193	CPUMSetChangedFlags(pVM->apCpusR3[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5194
5195	AssertLogRelRC(rc);
5196	return rc;
5197	}
5198
5199
5200	/**
5201	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
5202	*
5203	* @returns VBox status code.
5204	* @param pVM The cross context VM structure.
5205	* @param fInflate Inflate or deflate memory balloon
5206	* @param cPages Number of pages to free
5207	* @param paPhysPage Array of guest physical addresses
5208	*/
5209	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
5210	{
5211	uintptr_t paUser[3];
5212
5213	paUser[0] = fInflate;
5214	paUser[1] = cPages;
5215	paUser[2] = (uintptr_t)paPhysPage;
5216	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
5217	AssertRC(rc);
5218
5219	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
5220	RTMemFree(paPhysPage);
5221	}
5222
5223	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
5224
5225	/**
5226	* Inflate or deflate a memory balloon
5227	*
5228	* @returns VBox status code.
5229	* @param pVM The cross context VM structure.
5230	* @param fInflate Inflate or deflate memory balloon
5231	* @param cPages Number of pages to free
5232	* @param paPhysPage Array of guest physical addresses
5233	*/
5234	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
5235	{
5236	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
5237	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
5238	int rc;
5239
5240	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
5241	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
5242
5243	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
5244	* In the SMP case we post a request packet to postpone the job.
5245	*/
5246	if (pVM->cCpus > 1)
5247	{
5248	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
5249	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
5250	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
5251
5252	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
5253
5254	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
5255	AssertRC(rc);
5256	}
5257	else
5258	{
5259	uintptr_t paUser[3];
5260
5261	paUser[0] = fInflate;
5262	paUser[1] = cPages;
5263	paUser[2] = (uintptr_t)paPhysPage;
5264	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
5265	AssertRC(rc);
5266	}
5267	return rc;
5268
5269	#else
5270	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
5271	return VERR_NOT_IMPLEMENTED;
5272	#endif
5273	}
5274
5275
5276	/*********************************************************************************************************************************
5277	* Write Monitoring *
5278	*********************************************************************************************************************************/
5279
5280	/**
5281	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
5282	* physical RAM.
5283	*
5284	* This is only called on one of the EMTs while the other ones are waiting for
5285	* it to complete this function.
5286	*
5287	* @returns VINF_SUCCESS (VBox strict status code).
5288	* @param pVM The cross context VM structure.
5289	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5290	* @param pvUser User parameter, unused.
5291	*/
5292	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5293	{
5294	int rc = VINF_SUCCESS;
5295	NOREF(pvUser); NOREF(pVCpu);
5296
5297	PGM_LOCK_VOID(pVM);
5298	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5299	pgmPoolResetDirtyPages(pVM);
5300	#endif
5301
5302	/** @todo pointless to write protect the physical page pointed to by RSP. */
5303
5304	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
5305	pRam;
5306	pRam = pRam->CTX_SUFF(pNext))
5307	{
5308	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
5309	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5310	{
5311	PPGMPAGE pPage = &pRam->aPages[iPage];
5312	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
5313
5314	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
5315	\|\| enmPageType == PGMPAGETYPE_MMIO2)
5316	{
5317	/*
5318	* A RAM page.
5319	*/
5320	switch (PGM_PAGE_GET_STATE(pPage))
5321	{
5322	case PGM_PAGE_STATE_ALLOCATED:
5323	/** @todo Optimize this: Don't always re-enable write
5324	* monitoring if the page is known to be very busy. */
5325	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
5326	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
5327
5328	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
5329	break;
5330
5331	case PGM_PAGE_STATE_SHARED:
5332	AssertFailed();
5333	break;
5334
5335	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
5336	default:
5337	break;
5338	}
5339	}
5340	}
5341	}
5342	pgmR3PoolWriteProtectPages(pVM);
5343	PGM_INVL_ALL_VCPU_TLBS(pVM);
5344	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5345	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5346
5347	PGM_UNLOCK(pVM);
5348	return rc;
5349	}
5350
5351	/**
5352	* Protect all physical RAM to monitor writes
5353	*
5354	* @returns VBox status code.
5355	* @param pVM The cross context VM structure.
5356	*/
5357	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
5358	{
5359	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
5360
5361	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
5362	AssertRC(rc);
5363	return rc;
5364	}
5365
5366
5367	/*********************************************************************************************************************************
5368	* Stats. *
5369	*********************************************************************************************************************************/
5370
5371	/**
5372	* Query the amount of free memory inside VMMR0
5373	*
5374	* @returns VBox status code.
5375	* @param pUVM The user mode VM handle.
5376	* @param pcbAllocMem Where to return the amount of memory allocated
5377	* by VMs.
5378	* @param pcbFreeMem Where to return the amount of memory that is
5379	* allocated from the host but not currently used
5380	* by any VMs.
5381	* @param pcbBallonedMem Where to return the sum of memory that is
5382	* currently ballooned by the VMs.
5383	* @param pcbSharedMem Where to return the amount of memory that is
5384	* currently shared.
5385	*/
5386	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
5387	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
5388	{
5389	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
5390	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
5391
5392	uint64_t cAllocPages = 0;
5393	uint64_t cFreePages = 0;
5394	uint64_t cBalloonPages = 0;
5395	uint64_t cSharedPages = 0;
5396	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
5397	AssertRCReturn(rc, rc);
5398
5399	if (pcbAllocMem)
5400	pcbAllocMem = cAllocPages _4K;
5401
5402	if (pcbFreeMem)
5403	pcbFreeMem = cFreePages _4K;
5404
5405	if (pcbBallonedMem)
5406	pcbBallonedMem = cBalloonPages _4K;
5407
5408	if (pcbSharedMem)
5409	pcbSharedMem = cSharedPages _4K;
5410
5411	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
5412	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
5413	return VINF_SUCCESS;
5414	}
5415
5416
5417	/**
5418	* Query memory stats for the VM.
5419	*
5420	* @returns VBox status code.
5421	* @param pUVM The user mode VM handle.
5422	* @param pcbTotalMem Where to return total amount memory the VM may
5423	* possibly use.
5424	* @param pcbPrivateMem Where to return the amount of private memory
5425	* currently allocated.
5426	* @param pcbSharedMem Where to return the amount of actually shared
5427	* memory currently used by the VM.
5428	* @param pcbZeroMem Where to return the amount of memory backed by
5429	* zero pages.
5430	*
5431	* @remarks The total mem is normally larger than the sum of the three
5432	* components. There are two reasons for this, first the amount of
5433	* shared memory is what we're sure is shared instead of what could
5434	* possibly be shared with someone. Secondly, because the total may
5435	* include some pure MMIO pages that doesn't go into any of the three
5436	* sub-counts.
5437	*
5438	* @todo Why do we return reused shared pages instead of anything that could
5439	* potentially be shared? Doesn't this mean the first VM gets a much
5440	* lower number of shared pages?
5441	*/
5442	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
5443	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
5444	{
5445	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
5446	PVM pVM = pUVM->pVM;
5447	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
5448
5449	if (pcbTotalMem)
5450	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
5451
5452	if (pcbPrivateMem)
5453	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
5454
5455	if (pcbSharedMem)
5456	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
5457
5458	if (pcbZeroMem)
5459	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
5460
5461	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
5462	return VINF_SUCCESS;
5463	}
5464
5465
5466
5467	/*********************************************************************************************************************************
5468	* Chunk Mappings and Page Allocation *
5469	*********************************************************************************************************************************/
5470
5471	/**
5472	* Tree enumeration callback for dealing with age rollover.
5473	* It will perform a simple compression of the current age.
5474	*/
5475	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
5476	{
5477	/* Age compression - ASSUMES iNow == 4. */
5478	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
5479	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
5480	pChunk->iLastUsed = 3;
5481	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
5482	pChunk->iLastUsed = 2;
5483	else if (pChunk->iLastUsed)
5484	pChunk->iLastUsed = 1;
5485	else /* iLastUsed = 0 */
5486	pChunk->iLastUsed = 4;
5487
5488	NOREF(pvUser);
5489	return 0;
5490	}
5491
5492
5493	/**
5494	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
5495	*/
5496	typedef struct PGMR3PHYSCHUNKUNMAPCB
5497	{
5498	PVM pVM; /*< Pointer to the VM. /
5499	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
5500	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
5501
5502
5503	/**
5504	* Callback used to find the mapping that's been unused for
5505	* the longest time.
5506	*/
5507	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
5508	{
5509	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
5510	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
5511
5512	/*
5513	* Check for locks and compare when last used.
5514	*/
5515	if (pChunk->cRefs)
5516	return 0;
5517	if (pChunk->cPermRefs)
5518	return 0;
5519	if ( pArg->pChunk
5520	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
5521	return 0;
5522
5523	/*
5524	* Check that it's not in any of the TLBs.
5525	*/
5526	PVM pVM = pArg->pVM;
5527	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
5528	== pChunk->Core.Key)
5529	{
5530	pChunk = NULL;
5531	return 0;
5532	}
5533	#ifdef VBOX_STRICT
5534	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5535	{
5536	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
5537	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
5538	}
5539	#endif
5540
5541	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbR3.aEntries); i++)
5542	if (pVM->pgm.s.PhysTlbR3.aEntries[i].pMap == pChunk)
5543	return 0;
5544
5545	pArg->pChunk = pChunk;
5546	return 0;
5547	}
5548
5549
5550	/**
5551	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
5552	*
5553	* The candidate will not be part of any TLBs, so no need to flush
5554	* anything afterwards.
5555	*
5556	* @returns Chunk id.
5557	* @param pVM The cross context VM structure.
5558	*/
5559	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
5560	{
5561	PGM_LOCK_ASSERT_OWNER(pVM);
5562
5563	/*
5564	* Enumerate the age tree starting with the left most node.
5565	*/
5566	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5567	PGMR3PHYSCHUNKUNMAPCB Args;
5568	Args.pVM = pVM;
5569	Args.pChunk = NULL;
5570	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
5571	Assert(Args.pChunk);
5572	if (Args.pChunk)
5573	{
5574	Assert(Args.pChunk->cRefs == 0);
5575	Assert(Args.pChunk->cPermRefs == 0);
5576	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5577	return Args.pChunk->Core.Key;
5578	}
5579
5580	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5581	return INT32_MAX;
5582	}
5583
5584
5585	/**
5586	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
5587	*
5588	* This is only called on one of the EMTs while the other ones are waiting for
5589	* it to complete this function.
5590	*
5591	* @returns VINF_SUCCESS (VBox strict status code).
5592	* @param pVM The cross context VM structure.
5593	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5594	* @param pvUser User pointer. Unused
5595	*
5596	*/
5597	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5598	{
5599	int rc = VINF_SUCCESS;
5600	PGM_LOCK_VOID(pVM);
5601	NOREF(pVCpu); NOREF(pvUser);
5602
5603	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
5604	{
5605	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
5606	/** @todo also not really efficient to unmap a chunk that contains PD
5607	* or PT pages. */
5608	pgmR3PoolClearAllRendezvous(pVM, pVM->apCpusR3[0], NULL /* no need to flush the REM TLB as we already did that above */);
5609
5610	/*
5611	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
5612	*/
5613	GMMMAPUNMAPCHUNKREQ Req;
5614	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5615	Req.Hdr.cbReq = sizeof(Req);
5616	Req.pvR3 = NULL;
5617	Req.idChunkMap = NIL_GMM_CHUNKID;
5618	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
5619	if (Req.idChunkUnmap != INT32_MAX)
5620	{
5621	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkUnmap, a);
5622	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5623	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkUnmap, a);
5624	if (RT_SUCCESS(rc))
5625	{
5626	/*
5627	* Remove the unmapped one.
5628	*/
5629	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
5630	AssertRelease(pUnmappedChunk);
5631	AssertRelease(!pUnmappedChunk->cRefs);
5632	AssertRelease(!pUnmappedChunk->cPermRefs);
5633	pUnmappedChunk->pv = NULL;
5634	pUnmappedChunk->Core.Key = UINT32_MAX;
5635	MMR3HeapFree(pUnmappedChunk);
5636	pVM->pgm.s.ChunkR3Map.c--;
5637	pVM->pgm.s.cUnmappedChunks++;
5638
5639	/*
5640	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
5641	*/
5642	/** @todo We should not flush chunks which include cr3 mappings. */
5643	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5644	{
5645	PPGMCPU pPGM = &pVM->apCpusR3[idCpu]->pgm.s;
5646
5647	pPGM->pGst32BitPdR3 = NULL;
5648	pPGM->pGstPaePdptR3 = NULL;
5649	pPGM->pGstAmd64Pml4R3 = NULL;
5650	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
5651	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
5652	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
5653	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
5654	{
5655	pPGM->apGstPaePDsR3[i] = NULL;
5656	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
5657	}
5658
5659	/* Flush REM TLBs. */
5660	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5661	}
5662	}
5663	}
5664	}
5665	PGM_UNLOCK(pVM);
5666	return rc;
5667	}
5668
5669	/**
5670	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
5671	*
5672	* @returns VBox status code.
5673	* @param pVM The cross context VM structure.
5674	*/
5675	static DECLCALLBACK(void) pgmR3PhysUnmapChunk(PVM pVM)
5676	{
5677	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
5678	AssertRC(rc);
5679	}
5680
5681
5682	/**
5683	* Maps the given chunk into the ring-3 mapping cache.
5684	*
5685	* This will call ring-0.
5686	*
5687	* @returns VBox status code.
5688	* @param pVM The cross context VM structure.
5689	* @param idChunk The chunk in question.
5690	* @param ppChunk Where to store the chunk tracking structure.
5691	*
5692	* @remarks Called from within the PGM critical section.
5693	* @remarks Can be called from any thread!
5694	*/
5695	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
5696	{
5697	int rc;
5698
5699	PGM_LOCK_ASSERT_OWNER(pVM);
5700
5701	/*
5702	* Move the chunk time forward.
5703	*/
5704	pVM->pgm.s.ChunkR3Map.iNow++;
5705	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
5706	{
5707	pVM->pgm.s.ChunkR3Map.iNow = 4;
5708	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
5709	}
5710
5711	/*
5712	* Allocate a new tracking structure first.
5713	*/
5714	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
5715	AssertReturn(pChunk, VERR_NO_MEMORY);
5716	pChunk->Core.Key = idChunk;
5717	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
5718
5719	/*
5720	* Request the ring-0 part to map the chunk in question.
5721	*/
5722	GMMMAPUNMAPCHUNKREQ Req;
5723	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5724	Req.Hdr.cbReq = sizeof(Req);
5725	Req.pvR3 = NULL;
5726	Req.idChunkMap = idChunk;
5727	Req.idChunkUnmap = NIL_GMM_CHUNKID;
5728
5729	/* Must be callable from any thread, so can't use VMMR3CallR0. */
5730	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkMap, a);
5731	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5732	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkMap, a);
5733	if (RT_SUCCESS(rc))
5734	{
5735	pChunk->pv = Req.pvR3;
5736
5737	/*
5738	* If we're running out of virtual address space, then we should
5739	* unmap another chunk.
5740	*
5741	* Currently, an unmap operation requires that all other virtual CPUs
5742	* are idling and not by chance making use of the memory we're
5743	* unmapping. So, we create an async unmap operation here.
5744	*
5745	* Now, when creating or restoring a saved state this wont work very
5746	* well since we may want to restore all guest RAM + a little something.
5747	* So, we have to do the unmap synchronously. Fortunately for us
5748	* though, during these operations the other virtual CPUs are inactive
5749	* and it should be safe to do this.
5750	*/
5751	/** @todo Eventually we should lock all memory when used and do
5752	* map+unmap as one kernel call without any rendezvous or
5753	* other precautions. */
5754	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
5755	{
5756	switch (VMR3GetState(pVM))
5757	{
5758	case VMSTATE_LOADING:
5759	case VMSTATE_SAVING:
5760	{
5761	PVMCPU pVCpu = VMMGetCpu(pVM);
5762	if ( pVCpu
5763	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
5764	{
5765	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
5766	break;
5767	}
5768	}
5769	RT_FALL_THRU();
5770	default:
5771	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
5772	AssertRC(rc);
5773	break;
5774	}
5775	}
5776
5777	/*
5778	* Update the tree. We must do this after any unmapping to make sure
5779	* the chunk we're going to return isn't unmapped by accident.
5780	*/
5781	AssertPtr(Req.pvR3);
5782	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
5783	AssertRelease(fRc);
5784	pVM->pgm.s.ChunkR3Map.c++;
5785	pVM->pgm.s.cMappedChunks++;
5786	}
5787	else
5788	{
5789	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
5790	* should probably restrict ourselves on linux. */
5791	AssertRC(rc);
5792	MMR3HeapFree(pChunk);
5793	pChunk = NULL;
5794	}
5795
5796	*ppChunk = pChunk;
5797	return rc;
5798	}
5799
5800
5801	/**
5802	* Invalidates the TLB for the ring-3 mapping cache.
5803	*
5804	* @param pVM The cross context VM structure.
5805	*/
5806	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
5807	{
5808	PGM_LOCK_VOID(pVM);
5809	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5810	{
5811	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
5812	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
5813	}
5814	/* The page map TLB references chunks, so invalidate that one too. */
5815	pgmPhysInvalidatePageMapTLB(pVM);
5816	PGM_UNLOCK(pVM);
5817	}
5818
5819
5820	/**
5821	* Response to VM_FF_PGM_NEED_HANDY_PAGES and helper for pgmPhysEnsureHandyPage.
5822	*
5823	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
5824	* signal and clear the out of memory condition. When called, this API is used
5825	* to try clear the condition when the user wants to resume.
5826	*
5827	* @returns The following VBox status codes.
5828	* @retval VINF_SUCCESS on success. FFs cleared.
5829	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
5830	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
5831	*
5832	* @param pVM The cross context VM structure.
5833	*
5834	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
5835	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
5836	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
5837	* handler.
5838	*/
5839	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
5840	{
5841	PGM_LOCK_VOID(pVM);
5842
5843	/*
5844	* Allocate more pages, noting down the index of the first new page.
5845	*/
5846	uint32_t iClear = pVM->pgm.s.cHandyPages;
5847	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
5848	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
5849	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5850	/** @todo we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
5851	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
5852	&& pVM->pgm.s.cHandyPages > 0)
5853	{
5854	/* Still handy pages left, so don't panic. */
5855	rc = VINF_SUCCESS;
5856	}
5857
5858	if (RT_SUCCESS(rc))
5859	{
5860	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
5861	Assert(pVM->pgm.s.cHandyPages > 0);
5862	#ifdef VBOX_STRICT
5863	uint32_t i;
5864	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
5865	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
5866	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
5867	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
5868	break;
5869	if (i != pVM->pgm.s.cHandyPages)
5870	{
5871	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
5872	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
5873	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
5874	RTAssertMsg2Add("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%s\n", j,
5875	pVM->pgm.s.aHandyPages[j].idPage,
5876	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
5877	pVM->pgm.s.aHandyPages[j].idSharedPage,
5878	j == i ? " <---" : "");
5879	RTAssertPanic();
5880	}
5881	#endif
5882	}
5883	else
5884	{
5885	/*
5886	* We should never get here unless there is a genuine shortage of
5887	* memory (or some internal error). Flag the error so the VM can be
5888	* suspended ASAP and the user informed. If we're totally out of
5889	* handy pages we will return failure.
5890	*/
5891	/* Report the failure. */
5892	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc cHandyPages=%#x\n"
5893	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
5894	rc, pVM->pgm.s.cHandyPages,
5895	pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cSharedPages, pVM->pgm.s.cZeroPages));
5896
5897	if ( rc != VERR_NO_MEMORY
5898	&& rc != VERR_NO_PHYS_MEMORY
5899	&& rc != VERR_LOCK_FAILED)
5900	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5901	{
5902	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
5903	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
5904	pVM->pgm.s.aHandyPages[i].idSharedPage));
5905	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
5906	if (idPage != NIL_GMM_PAGEID)
5907	{
5908	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
5909	pRam;
5910	pRam = pRam->pNextR3)
5911	{
5912	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
5913	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5914	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
5915	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
5916	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
5917	}
5918	}
5919	}
5920
5921	if (rc == VERR_NO_MEMORY)
5922	{
5923	uint64_t cbHostRamAvail = 0;
5924	int rc2 = RTSystemQueryAvailableRam(&cbHostRamAvail);
5925	if (RT_SUCCESS(rc2))
5926	LogRel(("Host RAM: %RU64MB available\n", cbHostRamAvail / _1M));
5927	else
5928	LogRel(("Cannot determine the amount of available host memory\n"));
5929	}
5930
5931	/* Set the FFs and adjust rc. */
5932	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5933	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
5934	if ( rc == VERR_NO_MEMORY
5935	\|\| rc == VERR_NO_PHYS_MEMORY
5936	\|\| rc == VERR_LOCK_FAILED)
5937	rc = VINF_EM_NO_MEMORY;
5938	}
5939
5940	PGM_UNLOCK(pVM);
5941	return rc;
5942	}
5943
5944
5945	/*********************************************************************************************************************************
5946	* Other Stuff *
5947	*********************************************************************************************************************************/
5948
5949	/**
5950	* Sets the Address Gate 20 state.
5951	*
5952	* @param pVCpu The cross context virtual CPU structure.
5953	* @param fEnable True if the gate should be enabled.
5954	* False if the gate should be disabled.
5955	*/
5956	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
5957	{
5958	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
5959	if (pVCpu->pgm.s.fA20Enabled != fEnable)
5960	{
5961	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5962	PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
5963	if ( CPUMIsGuestInVmxRootMode(pCtx)
5964	&& !fEnable)
5965	{
5966	Log(("Cannot enter A20M mode while in VMX root mode\n"));
5967	return;
5968	}
5969	#endif
5970	pVCpu->pgm.s.fA20Enabled = fEnable;
5971	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
5972	if (VM_IS_NEM_ENABLED(pVCpu->CTX_SUFF(pVM)))
5973	NEMR3NotifySetA20(pVCpu, fEnable);
5974	#ifdef PGM_WITH_A20
5975	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5976	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
5977	HMFlushTlb(pVCpu);
5978	#endif
5979	IEMTlbInvalidateAllPhysical(pVCpu);
5980	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
5981	}
5982	}
5983

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 92424

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