PGMPhys.cpp@ 92676

Last change on this file since 92676 was 92626, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Adjust PGM APIs and translate nested-guest CR3 prior to mapping them when switching mode and other places.
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1	/* $Id: PGMPhys.cpp 92626 2021-11-29 12:32:58Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_PHYS
23	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
24	#include <VBox/vmm/pgm.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/iom.h>
27	#include <VBox/vmm/mm.h>
28	#include <VBox/vmm/nem.h>
29	#include <VBox/vmm/stam.h>
30	#include <VBox/vmm/pdmdev.h>
31	#include "PGMInternal.h"
32	#include <VBox/vmm/vmcc.h>
33
34	#include "PGMInline.h"
35
36	#include <VBox/sup.h>
37	#include <VBox/param.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#ifdef VBOX_STRICT
44	# include <iprt/crc.h>
45	#endif
46	#include <iprt/thread.h>
47	#include <iprt/string.h>
48	#include <iprt/system.h>
49
50
51	/*********************************************************************************************************************************
52	* Defined Constants And Macros *
53	*********************************************************************************************************************************/
54	/** The number of pages to free in one batch. */
55	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
56
57
58
59	/*********************************************************************************************************************************
60	* Reading and Writing Guest Pysical Memory *
61	*********************************************************************************************************************************/
62
63	/*
64	* PGMR3PhysReadU8-64
65	* PGMR3PhysWriteU8-64
66	*/
67	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
68	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
69	#define PGMPHYS_DATASIZE 1
70	#define PGMPHYS_DATATYPE uint8_t
71	#include "PGMPhysRWTmpl.h"
72
73	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
74	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
75	#define PGMPHYS_DATASIZE 2
76	#define PGMPHYS_DATATYPE uint16_t
77	#include "PGMPhysRWTmpl.h"
78
79	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
80	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
81	#define PGMPHYS_DATASIZE 4
82	#define PGMPHYS_DATATYPE uint32_t
83	#include "PGMPhysRWTmpl.h"
84
85	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
86	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
87	#define PGMPHYS_DATASIZE 8
88	#define PGMPHYS_DATATYPE uint64_t
89	#include "PGMPhysRWTmpl.h"
90
91
92	/**
93	* EMT worker for PGMR3PhysReadExternal.
94	*/
95	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead,
96	PGMACCESSORIGIN enmOrigin)
97	{
98	VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead, enmOrigin);
99	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
100	return VINF_SUCCESS;
101	}
102
103
104	/**
105	* Read from physical memory, external users.
106	*
107	* @returns VBox status code.
108	* @retval VINF_SUCCESS.
109	*
110	* @param pVM The cross context VM structure.
111	* @param GCPhys Physical address to read from.
112	* @param pvBuf Where to read into.
113	* @param cbRead How many bytes to read.
114	* @param enmOrigin Who is calling.
115	*
116	* @thread Any but EMTs.
117	*/
118	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
119	{
120	VM_ASSERT_OTHER_THREAD(pVM);
121
122	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
123	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
124
125	PGM_LOCK_VOID(pVM);
126
127	/*
128	* Copy loop on ram ranges.
129	*/
130	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
131	for (;;)
132	{
133	/* Inside range or not? */
134	if (pRam && GCPhys >= pRam->GCPhys)
135	{
136	/*
137	* Must work our way thru this page by page.
138	*/
139	RTGCPHYS off = GCPhys - pRam->GCPhys;
140	while (off < pRam->cb)
141	{
142	unsigned iPage = off >> PAGE_SHIFT;
143	PPGMPAGE pPage = &pRam->aPages[iPage];
144
145	/*
146	* If the page has an ALL access handler, we'll have to
147	* delegate the job to EMT.
148	*/
149	if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
150	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
151	{
152	PGM_UNLOCK(pVM);
153
154	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 5,
155	pVM, &GCPhys, pvBuf, cbRead, enmOrigin);
156	}
157	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
158
159	/*
160	* Simple stuff, go ahead.
161	*/
162	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
163	if (cb > cbRead)
164	cb = cbRead;
165	PGMPAGEMAPLOCK PgMpLck;
166	const void *pvSrc;
167	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
168	if (RT_SUCCESS(rc))
169	{
170	memcpy(pvBuf, pvSrc, cb);
171	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
172	}
173	else
174	{
175	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
176	pRam->GCPhys + off, pPage, rc));
177	memset(pvBuf, 0xff, cb);
178	}
179
180	/* next page */
181	if (cb >= cbRead)
182	{
183	PGM_UNLOCK(pVM);
184	return VINF_SUCCESS;
185	}
186	cbRead -= cb;
187	off += cb;
188	GCPhys += cb;
189	pvBuf = (char *)pvBuf + cb;
190	} /* walk pages in ram range. */
191	}
192	else
193	{
194	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
195
196	/*
197	* Unassigned address space.
198	*/
199	size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
200	if (cb >= cbRead)
201	{
202	memset(pvBuf, 0xff, cbRead);
203	break;
204	}
205	memset(pvBuf, 0xff, cb);
206
207	cbRead -= cb;
208	pvBuf = (char *)pvBuf + cb;
209	GCPhys += cb;
210	}
211
212	/* Advance range if necessary. */
213	while (pRam && GCPhys > pRam->GCPhysLast)
214	pRam = pRam->CTX_SUFF(pNext);
215	} /* Ram range walk */
216
217	PGM_UNLOCK(pVM);
218
219	return VINF_SUCCESS;
220	}
221
222
223	/**
224	* EMT worker for PGMR3PhysWriteExternal.
225	*/
226	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite,
227	PGMACCESSORIGIN enmOrigin)
228	{
229	/** @todo VERR_EM_NO_MEMORY */
230	VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite, enmOrigin);
231	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); NOREF(rcStrict);
232	return VINF_SUCCESS;
233	}
234
235
236	/**
237	* Write to physical memory, external users.
238	*
239	* @returns VBox status code.
240	* @retval VINF_SUCCESS.
241	* @retval VERR_EM_NO_MEMORY.
242	*
243	* @param pVM The cross context VM structure.
244	* @param GCPhys Physical address to write to.
245	* @param pvBuf What to write.
246	* @param cbWrite How many bytes to write.
247	* @param enmOrigin Who is calling.
248	*
249	* @thread Any but EMTs.
250	*/
251	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
252	{
253	VM_ASSERT_OTHER_THREAD(pVM);
254
255	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
256	("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x enmOrigin=%d\n",
257	GCPhys, cbWrite, enmOrigin));
258	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
259	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
260
261	PGM_LOCK_VOID(pVM);
262
263	/*
264	* Copy loop on ram ranges, stop when we hit something difficult.
265	*/
266	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
267	for (;;)
268	{
269	/* Inside range or not? */
270	if (pRam && GCPhys >= pRam->GCPhys)
271	{
272	/*
273	* Must work our way thru this page by page.
274	*/
275	RTGCPTR off = GCPhys - pRam->GCPhys;
276	while (off < pRam->cb)
277	{
278	RTGCPTR iPage = off >> PAGE_SHIFT;
279	PPGMPAGE pPage = &pRam->aPages[iPage];
280
281	/*
282	* Is the page problematic, we have to do the work on the EMT.
283	*
284	* Allocating writable pages and access handlers are
285	* problematic, write monitored pages are simple and can be
286	* dealt with here.
287	*/
288	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
289	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
290	\|\| PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
291	{
292	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
293	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
294	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
295	else
296	{
297	PGM_UNLOCK(pVM);
298
299	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 5,
300	pVM, &GCPhys, pvBuf, cbWrite, enmOrigin);
301	}
302	}
303	Assert(!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage));
304
305	/*
306	* Simple stuff, go ahead.
307	*/
308	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
309	if (cb > cbWrite)
310	cb = cbWrite;
311	PGMPAGEMAPLOCK PgMpLck;
312	void *pvDst;
313	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
314	if (RT_SUCCESS(rc))
315	{
316	memcpy(pvDst, pvBuf, cb);
317	pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
318	}
319	else
320	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
321	pRam->GCPhys + off, pPage, rc));
322
323	/* next page */
324	if (cb >= cbWrite)
325	{
326	PGM_UNLOCK(pVM);
327	return VINF_SUCCESS;
328	}
329
330	cbWrite -= cb;
331	off += cb;
332	GCPhys += cb;
333	pvBuf = (const char *)pvBuf + cb;
334	} /* walk pages in ram range */
335	}
336	else
337	{
338	/*
339	* Unassigned address space, skip it.
340	*/
341	if (!pRam)
342	break;
343	size_t cb = pRam->GCPhys - GCPhys;
344	if (cb >= cbWrite)
345	break;
346	cbWrite -= cb;
347	pvBuf = (const char *)pvBuf + cb;
348	GCPhys += cb;
349	}
350
351	/* Advance range if necessary. */
352	while (pRam && GCPhys > pRam->GCPhysLast)
353	pRam = pRam->CTX_SUFF(pNext);
354	} /* Ram range walk */
355
356	PGM_UNLOCK(pVM);
357	return VINF_SUCCESS;
358	}
359
360
361	/*********************************************************************************************************************************
362	* Mapping Guest Physical Memory *
363	*********************************************************************************************************************************/
364
365	/**
366	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
367	*
368	* @returns see PGMR3PhysGCPhys2CCPtrExternal
369	* @param pVM The cross context VM structure.
370	* @param pGCPhys Pointer to the guest physical address.
371	* @param ppv Where to store the mapping address.
372	* @param pLock Where to store the lock.
373	*/
374	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
375	{
376	/*
377	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
378	* an access handler after it succeeds.
379	*/
380	int rc = PGM_LOCK(pVM);
381	AssertRCReturn(rc, rc);
382
383	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
384	if (RT_SUCCESS(rc))
385	{
386	PPGMPAGEMAPTLBE pTlbe;
387	int rc2 = pgmPhysPageQueryTlbe(pVM, *pGCPhys, &pTlbe);
388	AssertFatalRC(rc2);
389	PPGMPAGE pPage = pTlbe->pPage;
390	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
391	{
392	PGMPhysReleasePageMappingLock(pVM, pLock);
393	rc = VERR_PGM_PHYS_PAGE_RESERVED;
394	}
395	else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
396	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
397	\|\| pgmPoolIsDirtyPage(pVM, *pGCPhys)
398	#endif
399	)
400	{
401	/* We must flush any corresponding pgm pool page here, otherwise we'll
402	* not be informed about writes and keep bogus gst->shw mappings around.
403	*/
404	pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
405	Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
406	/** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
407	* active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
408	}
409	}
410
411	PGM_UNLOCK(pVM);
412	return rc;
413	}
414
415
416	/**
417	* Requests the mapping of a guest page into ring-3, external threads.
418	*
419	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
420	* release it.
421	*
422	* This API will assume your intention is to write to the page, and will
423	* therefore replace shared and zero pages. If you do not intend to modify the
424	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
425	*
426	* @returns VBox status code.
427	* @retval VINF_SUCCESS on success.
428	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
429	* backing or if the page has any active access handlers. The caller
430	* must fall back on using PGMR3PhysWriteExternal.
431	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
432	*
433	* @param pVM The cross context VM structure.
434	* @param GCPhys The guest physical address of the page that should be mapped.
435	* @param ppv Where to store the address corresponding to GCPhys.
436	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
437	*
438	* @remark Avoid calling this API from within critical sections (other than the
439	* PGM one) because of the deadlock risk when we have to delegating the
440	* task to an EMT.
441	* @thread Any.
442	*/
443	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
444	{
445	AssertPtr(ppv);
446	AssertPtr(pLock);
447
448	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
449
450	int rc = PGM_LOCK(pVM);
451	AssertRCReturn(rc, rc);
452
453	/*
454	* Query the Physical TLB entry for the page (may fail).
455	*/
456	PPGMPAGEMAPTLBE pTlbe;
457	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
458	if (RT_SUCCESS(rc))
459	{
460	PPGMPAGE pPage = pTlbe->pPage;
461	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
462	rc = VERR_PGM_PHYS_PAGE_RESERVED;
463	else
464	{
465	/*
466	* If the page is shared, the zero page, or being write monitored
467	* it must be converted to an page that's writable if possible.
468	* We can only deal with write monitored pages here, the rest have
469	* to be on an EMT.
470	*/
471	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
472	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
473	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
474	\|\| pgmPoolIsDirtyPage(pVM, GCPhys)
475	#endif
476	)
477	{
478	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
479	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
480	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
481	&& !pgmPoolIsDirtyPage(pVM, GCPhys) /** @todo we're very likely doing this twice. */
482	#endif
483	)
484	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, GCPhys);
485	else
486	{
487	PGM_UNLOCK(pVM);
488
489	return VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
490	pVM, &GCPhys, ppv, pLock);
491	}
492	}
493
494	/*
495	* Now, just perform the locking and calculate the return address.
496	*/
497	PPGMPAGEMAP pMap = pTlbe->pMap;
498	if (pMap)
499	pMap->cRefs++;
500
501	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
502	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
503	{
504	if (cLocks == 0)
505	pVM->pgm.s.cWriteLockedPages++;
506	PGM_PAGE_INC_WRITE_LOCKS(pPage);
507	}
508	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
509	{
510	PGM_PAGE_INC_WRITE_LOCKS(pPage);
511	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
512	if (pMap)
513	pMap->cRefs++; /* Extra ref to prevent it from going away. */
514	}
515
516	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
517	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
518	pLock->pvMap = pMap;
519	}
520	}
521
522	PGM_UNLOCK(pVM);
523	return rc;
524	}
525
526
527	/**
528	* Requests the mapping of a guest page into ring-3, external threads.
529	*
530	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
531	* release it.
532	*
533	* @returns VBox status code.
534	* @retval VINF_SUCCESS on success.
535	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
536	* backing or if the page as an active ALL access handler. The caller
537	* must fall back on using PGMPhysRead.
538	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
539	*
540	* @param pVM The cross context VM structure.
541	* @param GCPhys The guest physical address of the page that should be mapped.
542	* @param ppv Where to store the address corresponding to GCPhys.
543	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
544	*
545	* @remark Avoid calling this API from within critical sections (other than
546	* the PGM one) because of the deadlock risk.
547	* @thread Any.
548	*/
549	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
550	{
551	int rc = PGM_LOCK(pVM);
552	AssertRCReturn(rc, rc);
553
554	/*
555	* Query the Physical TLB entry for the page (may fail).
556	*/
557	PPGMPAGEMAPTLBE pTlbe;
558	rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
559	if (RT_SUCCESS(rc))
560	{
561	PPGMPAGE pPage = pTlbe->pPage;
562	#if 1
563	/* MMIO pages doesn't have any readable backing. */
564	if (PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
565	rc = VERR_PGM_PHYS_PAGE_RESERVED;
566	#else
567	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
568	rc = VERR_PGM_PHYS_PAGE_RESERVED;
569	#endif
570	else
571	{
572	/*
573	* Now, just perform the locking and calculate the return address.
574	*/
575	PPGMPAGEMAP pMap = pTlbe->pMap;
576	if (pMap)
577	pMap->cRefs++;
578
579	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
580	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
581	{
582	if (cLocks == 0)
583	pVM->pgm.s.cReadLockedPages++;
584	PGM_PAGE_INC_READ_LOCKS(pPage);
585	}
586	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
587	{
588	PGM_PAGE_INC_READ_LOCKS(pPage);
589	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
590	if (pMap)
591	pMap->cRefs++; /* Extra ref to prevent it from going away. */
592	}
593
594	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
595	pLock->uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
596	pLock->pvMap = pMap;
597	}
598	}
599
600	PGM_UNLOCK(pVM);
601	return rc;
602	}
603
604
605	/**
606	* Requests the mapping of multiple guest page into ring-3, external threads.
607	*
608	* When you're done with the pages, call PGMPhysBulkReleasePageMappingLock()
609	* ASAP to release them.
610	*
611	* This API will assume your intention is to write to the pages, and will
612	* therefore replace shared and zero pages. If you do not intend to modify the
613	* pages, use the PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal() API.
614	*
615	* @returns VBox status code.
616	* @retval VINF_SUCCESS on success.
617	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
618	* backing or if any of the pages the page has any active access
619	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
620	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
621	* an invalid physical address.
622	*
623	* @param pVM The cross context VM structure.
624	* @param cPages Number of pages to lock.
625	* @param paGCPhysPages The guest physical address of the pages that
626	* should be mapped (@a cPages entries).
627	* @param papvPages Where to store the ring-3 mapping addresses
628	* corresponding to @a paGCPhysPages.
629	* @param paLocks Where to store the locking information that
630	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
631	* in length).
632	*
633	* @remark Avoid calling this API from within critical sections (other than the
634	* PGM one) because of the deadlock risk when we have to delegating the
635	* task to an EMT.
636	* @thread Any.
637	*/
638	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
639	void **papvPages, PPGMPAGEMAPLOCK paLocks)
640	{
641	Assert(cPages > 0);
642	AssertPtr(papvPages);
643	AssertPtr(paLocks);
644
645	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
646
647	int rc = PGM_LOCK(pVM);
648	AssertRCReturn(rc, rc);
649
650	/*
651	* Lock the pages one by one.
652	* The loop body is similar to PGMR3PhysGCPhys2CCPtrExternal.
653	*/
654	int32_t cNextYield = 128;
655	uint32_t iPage;
656	for (iPage = 0; iPage < cPages; iPage++)
657	{
658	if (--cNextYield > 0)
659	{ /* likely */ }
660	else
661	{
662	PGM_UNLOCK(pVM);
663	ASMNopPause();
664	PGM_LOCK_VOID(pVM);
665	cNextYield = 128;
666	}
667
668	/*
669	* Query the Physical TLB entry for the page (may fail).
670	*/
671	PPGMPAGEMAPTLBE pTlbe;
672	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
673	if (RT_SUCCESS(rc))
674	{ }
675	else
676	break;
677	PPGMPAGE pPage = pTlbe->pPage;
678
679	/*
680	* No MMIO or active access handlers.
681	*/
682	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
683	&& !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
684	{ }
685	else
686	{
687	rc = VERR_PGM_PHYS_PAGE_RESERVED;
688	break;
689	}
690
691	/*
692	* The page must be in the allocated state and not be a dirty pool page.
693	* We can handle converting a write monitored page to an allocated one, but
694	* anything more complicated must be delegated to an EMT.
695	*/
696	bool fDelegateToEmt = false;
697	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
698	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
699	fDelegateToEmt = pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]);
700	#else
701	fDelegateToEmt = false;
702	#endif
703	else if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
704	{
705	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
706	if (!pgmPoolIsDirtyPage(pVM, paGCPhysPages[iPage]))
707	pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage, paGCPhysPages[iPage]);
708	else
709	fDelegateToEmt = true;
710	#endif
711	}
712	else
713	fDelegateToEmt = true;
714	if (!fDelegateToEmt)
715	{ }
716	else
717	{
718	/* We could do this delegation in bulk, but considered too much work vs gain. */
719	PGM_UNLOCK(pVM);
720	rc = VMR3ReqPriorityCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
721	pVM, &paGCPhysPages[iPage], &papvPages[iPage], &paLocks[iPage]);
722	PGM_LOCK_VOID(pVM);
723	if (RT_FAILURE(rc))
724	break;
725	cNextYield = 128;
726	}
727
728	/*
729	* Now, just perform the locking and address calculation.
730	*/
731	PPGMPAGEMAP pMap = pTlbe->pMap;
732	if (pMap)
733	pMap->cRefs++;
734
735	unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
736	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
737	{
738	if (cLocks == 0)
739	pVM->pgm.s.cWriteLockedPages++;
740	PGM_PAGE_INC_WRITE_LOCKS(pPage);
741	}
742	else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
743	{
744	PGM_PAGE_INC_WRITE_LOCKS(pPage);
745	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", paGCPhysPages[iPage], pPage));
746	if (pMap)
747	pMap->cRefs++; /* Extra ref to prevent it from going away. */
748	}
749
750	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
751	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_WRITE;
752	paLocks[iPage].pvMap = pMap;
753	}
754
755	PGM_UNLOCK(pVM);
756
757	/*
758	* On failure we must unlock any pages we managed to get already.
759	*/
760	if (RT_FAILURE(rc) && iPage > 0)
761	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
762
763	return rc;
764	}
765
766
767	/**
768	* Requests the mapping of multiple guest page into ring-3, for reading only,
769	* external threads.
770	*
771	* When you're done with the pages, call PGMPhysReleasePageMappingLock() ASAP
772	* to release them.
773	*
774	* @returns VBox status code.
775	* @retval VINF_SUCCESS on success.
776	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
777	* backing or if any of the pages the page has an active ALL access
778	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
779	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
780	* an invalid physical address.
781	*
782	* @param pVM The cross context VM structure.
783	* @param cPages Number of pages to lock.
784	* @param paGCPhysPages The guest physical address of the pages that
785	* should be mapped (@a cPages entries).
786	* @param papvPages Where to store the ring-3 mapping addresses
787	* corresponding to @a paGCPhysPages.
788	* @param paLocks Where to store the lock information that
789	* pfnPhysReleasePageMappingLock needs (@a cPages
790	* in length).
791	*
792	* @remark Avoid calling this API from within critical sections (other than
793	* the PGM one) because of the deadlock risk.
794	* @thread Any.
795	*/
796	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
797	void const **papvPages, PPGMPAGEMAPLOCK paLocks)
798	{
799	Assert(cPages > 0);
800	AssertPtr(papvPages);
801	AssertPtr(paLocks);
802
803	Assert(VM_IS_EMT(pVM) \|\| !PGMIsLockOwner(pVM));
804
805	int rc = PGM_LOCK(pVM);
806	AssertRCReturn(rc, rc);
807
808	/*
809	* Lock the pages one by one.
810	* The loop body is similar to PGMR3PhysGCPhys2CCPtrReadOnlyExternal.
811	*/
812	int32_t cNextYield = 256;
813	uint32_t iPage;
814	for (iPage = 0; iPage < cPages; iPage++)
815	{
816	if (--cNextYield > 0)
817	{ /* likely */ }
818	else
819	{
820	PGM_UNLOCK(pVM);
821	ASMNopPause();
822	PGM_LOCK_VOID(pVM);
823	cNextYield = 256;
824	}
825
826	/*
827	* Query the Physical TLB entry for the page (may fail).
828	*/
829	PPGMPAGEMAPTLBE pTlbe;
830	rc = pgmPhysPageQueryTlbe(pVM, paGCPhysPages[iPage], &pTlbe);
831	if (RT_SUCCESS(rc))
832	{ }
833	else
834	break;
835	PPGMPAGE pPage = pTlbe->pPage;
836
837	/*
838	* No MMIO or active all access handlers, everything else can be accessed.
839	*/
840	if ( !PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)
841	&& !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
842	{ }
843	else
844	{
845	rc = VERR_PGM_PHYS_PAGE_RESERVED;
846	break;
847	}
848
849	/*
850	* Now, just perform the locking and address calculation.
851	*/
852	PPGMPAGEMAP pMap = pTlbe->pMap;
853	if (pMap)
854	pMap->cRefs++;
855
856	unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
857	if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
858	{
859	if (cLocks == 0)
860	pVM->pgm.s.cReadLockedPages++;
861	PGM_PAGE_INC_READ_LOCKS(pPage);
862	}
863	else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
864	{
865	PGM_PAGE_INC_READ_LOCKS(pPage);
866	AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", paGCPhysPages[iPage], pPage));
867	if (pMap)
868	pMap->cRefs++; /* Extra ref to prevent it from going away. */
869	}
870
871	papvPages[iPage] = (void *)((uintptr_t)pTlbe->pv \| (uintptr_t)(paGCPhysPages[iPage] & PAGE_OFFSET_MASK));
872	paLocks[iPage].uPageAndType = (uintptr_t)pPage \| PGMPAGEMAPLOCK_TYPE_READ;
873	paLocks[iPage].pvMap = pMap;
874	}
875
876	PGM_UNLOCK(pVM);
877
878	/*
879	* On failure we must unlock any pages we managed to get already.
880	*/
881	if (RT_FAILURE(rc) && iPage > 0)
882	PGMPhysBulkReleasePageMappingLocks(pVM, iPage, paLocks);
883
884	return rc;
885	}
886
887
888	/**
889	* Converts a GC physical address to a HC ring-3 pointer, with some
890	* additional checks.
891	*
892	* @returns VBox status code.
893	* @retval VINF_SUCCESS on success.
894	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
895	* access handler of some kind.
896	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
897	* accesses or is odd in any way.
898	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
899	*
900	* @param pVM The cross context VM structure.
901	* @param GCPhys The GC physical address to convert. Since this is only
902	* used for filling the REM TLB, the A20 mask must be
903	* applied before calling this API.
904	* @param fWritable Whether write access is required.
905	* @param ppv Where to store the pointer corresponding to GCPhys on
906	* success.
907	*/
908	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
909	{
910	PGM_LOCK_VOID(pVM);
911	PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
912
913	PPGMRAMRANGE pRam;
914	PPGMPAGE pPage;
915	int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
916	if (RT_SUCCESS(rc))
917	{
918	if (PGM_PAGE_IS_BALLOONED(pPage))
919	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
920	else if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
921	rc = VINF_SUCCESS;
922	else
923	{
924	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
925	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
926	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
927	{
928	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
929	* in -norawr0 mode. */
930	if (fWritable)
931	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
932	}
933	else
934	{
935	/* Temporarily disabled physical handler(s), since the recompiler
936	doesn't get notified when it's reset we'll have to pretend it's
937	operating normally. */
938	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
939	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
940	else
941	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
942	}
943	}
944	if (RT_SUCCESS(rc))
945	{
946	int rc2;
947
948	/* Make sure what we return is writable. */
949	if (fWritable)
950	switch (PGM_PAGE_GET_STATE(pPage))
951	{
952	case PGM_PAGE_STATE_ALLOCATED:
953	break;
954	case PGM_PAGE_STATE_BALLOONED:
955	AssertFailed();
956	break;
957	case PGM_PAGE_STATE_ZERO:
958	case PGM_PAGE_STATE_SHARED:
959	if (rc == VINF_PGM_PHYS_TLB_CATCH_WRITE)
960	break;
961	RT_FALL_THRU();
962	case PGM_PAGE_STATE_WRITE_MONITORED:
963	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
964	AssertLogRelRCReturn(rc2, rc2);
965	break;
966	}
967
968	/* Get a ring-3 mapping of the address. */
969	PPGMPAGER3MAPTLBE pTlbe;
970	rc2 = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
971	AssertLogRelRCReturn(rc2, rc2);
972	ppv = (void )((uintptr_t)pTlbe->pv \| (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
973	/** @todo mapping/locking hell; this isn't horribly efficient since
974	* pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
975
976	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
977	}
978	else
979	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
980
981	/* else: handler catching all access, no pointer returned. */
982	}
983	else
984	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
985
986	PGM_UNLOCK(pVM);
987	return rc;
988	}
989
990
991
992	/*********************************************************************************************************************************
993	* RAM Range Management *
994	*********************************************************************************************************************************/
995
996	#define MAKE_LEAF(a_pNode) \
997	do { \
998	(a_pNode)->pLeftR3 = NIL_RTR3PTR; \
999	(a_pNode)->pRightR3 = NIL_RTR3PTR; \
1000	(a_pNode)->pLeftR0 = NIL_RTR0PTR; \
1001	(a_pNode)->pRightR0 = NIL_RTR0PTR; \
1002	} while (0)
1003
1004	#define INSERT_LEFT(a_pParent, a_pNode) \
1005	do { \
1006	(a_pParent)->pLeftR3 = (a_pNode); \
1007	(a_pParent)->pLeftR0 = (a_pNode)->pSelfR0; \
1008	} while (0)
1009	#define INSERT_RIGHT(a_pParent, a_pNode) \
1010	do { \
1011	(a_pParent)->pRightR3 = (a_pNode); \
1012	(a_pParent)->pRightR0 = (a_pNode)->pSelfR0; \
1013	} while (0)
1014
1015
1016	/**
1017	* Recursive tree builder.
1018	*
1019	* @param ppRam Pointer to the iterator variable.
1020	* @param iDepth The current depth. Inserts a leaf node if 0.
1021	*/
1022	static PPGMRAMRANGE pgmR3PhysRebuildRamRangeSearchTreesRecursively(PPGMRAMRANGE *ppRam, int iDepth)
1023	{
1024	PPGMRAMRANGE pRam;
1025	if (iDepth <= 0)
1026	{
1027	/*
1028	* Leaf node.
1029	*/
1030	pRam = *ppRam;
1031	if (pRam)
1032	{
1033	*ppRam = pRam->pNextR3;
1034	MAKE_LEAF(pRam);
1035	}
1036	}
1037	else
1038	{
1039
1040	/*
1041	* Intermediate node.
1042	*/
1043	PPGMRAMRANGE pLeft = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
1044
1045	pRam = *ppRam;
1046	if (!pRam)
1047	return pLeft;
1048	*ppRam = pRam->pNextR3;
1049	MAKE_LEAF(pRam);
1050	INSERT_LEFT(pRam, pLeft);
1051
1052	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(ppRam, iDepth - 1);
1053	if (pRight)
1054	INSERT_RIGHT(pRam, pRight);
1055	}
1056	return pRam;
1057	}
1058
1059
1060	/**
1061	* Rebuilds the RAM range search trees.
1062	*
1063	* @param pVM The cross context VM structure.
1064	*/
1065	static void pgmR3PhysRebuildRamRangeSearchTrees(PVM pVM)
1066	{
1067
1068	/*
1069	* Create the reasonably balanced tree in a sequential fashion.
1070	* For simplicity (laziness) we use standard recursion here.
1071	*/
1072	int iDepth = 0;
1073	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1074	PPGMRAMRANGE pRoot = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, 0);
1075	while (pRam)
1076	{
1077	PPGMRAMRANGE pLeft = pRoot;
1078
1079	pRoot = pRam;
1080	pRam = pRam->pNextR3;
1081	MAKE_LEAF(pRoot);
1082	INSERT_LEFT(pRoot, pLeft);
1083
1084	PPGMRAMRANGE pRight = pgmR3PhysRebuildRamRangeSearchTreesRecursively(&pRam, iDepth);
1085	if (pRight)
1086	INSERT_RIGHT(pRoot, pRight);
1087	/** @todo else: rotate the tree. */
1088
1089	iDepth++;
1090	}
1091
1092	pVM->pgm.s.pRamRangeTreeR3 = pRoot;
1093	pVM->pgm.s.pRamRangeTreeR0 = pRoot ? pRoot->pSelfR0 : NIL_RTR0PTR;
1094
1095	#ifdef VBOX_STRICT
1096	/*
1097	* Verify that the above code works.
1098	*/
1099	unsigned cRanges = 0;
1100	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1101	cRanges++;
1102	Assert(cRanges > 0);
1103
1104	unsigned cMaxDepth = ASMBitLastSetU32(cRanges);
1105	if ((1U << cMaxDepth) < cRanges)
1106	cMaxDepth++;
1107
1108	for (pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1109	{
1110	unsigned cDepth = 0;
1111	PPGMRAMRANGE pRam2 = pVM->pgm.s.pRamRangeTreeR3;
1112	for (;;)
1113	{
1114	if (pRam == pRam2)
1115	break;
1116	Assert(pRam2);
1117	if (pRam->GCPhys < pRam2->GCPhys)
1118	pRam2 = pRam2->pLeftR3;
1119	else
1120	pRam2 = pRam2->pRightR3;
1121	}
1122	AssertMsg(cDepth <= cMaxDepth, ("cDepth=%d cMaxDepth=%d\n", cDepth, cMaxDepth));
1123	}
1124	#endif /* VBOX_STRICT */
1125	}
1126
1127	#undef MAKE_LEAF
1128	#undef INSERT_LEFT
1129	#undef INSERT_RIGHT
1130
1131	/**
1132	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
1133	*
1134	* Called when anything was relocated.
1135	*
1136	* @param pVM The cross context VM structure.
1137	*/
1138	void pgmR3PhysRelinkRamRanges(PVM pVM)
1139	{
1140	PPGMRAMRANGE pCur;
1141
1142	#ifdef VBOX_STRICT
1143	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1144	{
1145	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
1146	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
1147	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1148	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
1149	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
1150	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesXR3; pCur2; pCur2 = pCur2->pNextR3)
1151	Assert( pCur2 == pCur
1152	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
1153	}
1154	#endif
1155
1156	pCur = pVM->pgm.s.pRamRangesXR3;
1157	if (pCur)
1158	{
1159	pVM->pgm.s.pRamRangesXR0 = pCur->pSelfR0;
1160
1161	for (; pCur->pNextR3; pCur = pCur->pNextR3)
1162	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
1163
1164	Assert(pCur->pNextR0 == NIL_RTR0PTR);
1165	}
1166	else
1167	{
1168	Assert(pVM->pgm.s.pRamRangesXR0 == NIL_RTR0PTR);
1169	}
1170	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1171
1172	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1173	}
1174
1175
1176	/**
1177	* Links a new RAM range into the list.
1178	*
1179	* @param pVM The cross context VM structure.
1180	* @param pNew Pointer to the new list entry.
1181	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1182	*/
1183	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
1184	{
1185	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
1186	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
1187
1188	PGM_LOCK_VOID(pVM);
1189
1190	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesXR3;
1191	pNew->pNextR3 = pRam;
1192	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
1193
1194	if (pPrev)
1195	{
1196	pPrev->pNextR3 = pNew;
1197	pPrev->pNextR0 = pNew->pSelfR0;
1198	}
1199	else
1200	{
1201	pVM->pgm.s.pRamRangesXR3 = pNew;
1202	pVM->pgm.s.pRamRangesXR0 = pNew->pSelfR0;
1203	}
1204	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1205
1206	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1207	PGM_UNLOCK(pVM);
1208	}
1209
1210
1211	/**
1212	* Unlink an existing RAM range from the list.
1213	*
1214	* @param pVM The cross context VM structure.
1215	* @param pRam Pointer to the new list entry.
1216	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
1217	*/
1218	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
1219	{
1220	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesXR3 == pRam);
1221	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
1222
1223	PGM_LOCK_VOID(pVM);
1224
1225	PPGMRAMRANGE pNext = pRam->pNextR3;
1226	if (pPrev)
1227	{
1228	pPrev->pNextR3 = pNext;
1229	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1230	}
1231	else
1232	{
1233	Assert(pVM->pgm.s.pRamRangesXR3 == pRam);
1234	pVM->pgm.s.pRamRangesXR3 = pNext;
1235	pVM->pgm.s.pRamRangesXR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
1236	}
1237	ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
1238
1239	pgmR3PhysRebuildRamRangeSearchTrees(pVM);
1240	PGM_UNLOCK(pVM);
1241	}
1242
1243
1244	/**
1245	* Unlink an existing RAM range from the list.
1246	*
1247	* @param pVM The cross context VM structure.
1248	* @param pRam Pointer to the new list entry.
1249	*/
1250	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
1251	{
1252	PGM_LOCK_VOID(pVM);
1253
1254	/* find prev. */
1255	PPGMRAMRANGE pPrev = NULL;
1256	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3;
1257	while (pCur != pRam)
1258	{
1259	pPrev = pCur;
1260	pCur = pCur->pNextR3;
1261	}
1262	AssertFatal(pCur);
1263
1264	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
1265	PGM_UNLOCK(pVM);
1266	}
1267
1268
1269	/**
1270	* Gets the number of ram ranges.
1271	*
1272	* @returns Number of ram ranges. Returns UINT32_MAX if @a pVM is invalid.
1273	* @param pVM The cross context VM structure.
1274	*/
1275	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM)
1276	{
1277	VM_ASSERT_VALID_EXT_RETURN(pVM, UINT32_MAX);
1278
1279	PGM_LOCK_VOID(pVM);
1280	uint32_t cRamRanges = 0;
1281	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext))
1282	cRamRanges++;
1283	PGM_UNLOCK(pVM);
1284	return cRamRanges;
1285	}
1286
1287
1288	/**
1289	* Get information about a range.
1290	*
1291	* @returns VINF_SUCCESS or VERR_OUT_OF_RANGE.
1292	* @param pVM The cross context VM structure.
1293	* @param iRange The ordinal of the range.
1294	* @param pGCPhysStart Where to return the start of the range. Optional.
1295	* @param pGCPhysLast Where to return the address of the last byte in the
1296	* range. Optional.
1297	* @param ppszDesc Where to return the range description. Optional.
1298	* @param pfIsMmio Where to indicate that this is a pure MMIO range.
1299	* Optional.
1300	*/
1301	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1302	const char *ppszDesc, bool pfIsMmio)
1303	{
1304	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1305
1306	PGM_LOCK_VOID(pVM);
1307	uint32_t iCurRange = 0;
1308	for (PPGMRAMRANGE pCur = pVM->pgm.s.CTX_SUFF(pRamRangesX); pCur; pCur = pCur->CTX_SUFF(pNext), iCurRange++)
1309	if (iCurRange == iRange)
1310	{
1311	if (pGCPhysStart)
1312	*pGCPhysStart = pCur->GCPhys;
1313	if (pGCPhysLast)
1314	*pGCPhysLast = pCur->GCPhysLast;
1315	if (ppszDesc)
1316	*ppszDesc = pCur->pszDesc;
1317	if (pfIsMmio)
1318	*pfIsMmio = !!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO);
1319
1320	PGM_UNLOCK(pVM);
1321	return VINF_SUCCESS;
1322	}
1323	PGM_UNLOCK(pVM);
1324	return VERR_OUT_OF_RANGE;
1325	}
1326
1327
1328	/*********************************************************************************************************************************
1329	* RAM *
1330	*********************************************************************************************************************************/
1331
1332	/**
1333	* Frees the specified RAM page and replaces it with the ZERO page.
1334	*
1335	* This is used by ballooning, remapping MMIO2, RAM reset and state loading.
1336	*
1337	* @param pVM The cross context VM structure.
1338	* @param pReq Pointer to the request. This is NULL when doing a
1339	* bulk free in NEM memory mode.
1340	* @param pcPendingPages Where the number of pages waiting to be freed are
1341	* kept. This will normally be incremented. This is
1342	* NULL when doing a bulk free in NEM memory mode.
1343	* @param pPage Pointer to the page structure.
1344	* @param GCPhys The guest physical address of the page, if applicable.
1345	* @param enmNewType New page type for NEM notification, since several
1346	* callers will change the type upon successful return.
1347	*
1348	* @remarks The caller must own the PGM lock.
1349	*/
1350	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
1351	PGMPAGETYPE enmNewType)
1352	{
1353	/*
1354	* Assert sanity.
1355	*/
1356	PGM_LOCK_ASSERT_OWNER(pVM);
1357	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
1358	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
1359	{
1360	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
1361	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
1362	}
1363
1364	/** @todo What about ballooning of large pages??! */
1365	Assert( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
1366	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED);
1367
1368	if ( PGM_PAGE_IS_ZERO(pPage)
1369	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1370	return VINF_SUCCESS;
1371
1372	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
1373	Log3(("pgmPhysFreePage: idPage=%#x GCPhys=%RGp pPage=%R[pgmpage]\n", idPage, GCPhys, pPage));
1374	if (RT_UNLIKELY(!PGM_IS_IN_NEM_MODE(pVM)
1375	? idPage == NIL_GMM_PAGEID
1376	\|\| idPage > GMM_PAGEID_LAST
1377	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID
1378	: idPage != NIL_GMM_PAGEID))
1379	{
1380	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
1381	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
1382	}
1383	#ifdef VBOX_WITH_NATIVE_NEM
1384	const RTHCPHYS HCPhysPrev = PGM_PAGE_GET_HCPHYS(pPage);
1385	#endif
1386
1387	/* update page count stats. */
1388	if (PGM_PAGE_IS_SHARED(pPage))
1389	pVM->pgm.s.cSharedPages--;
1390	else
1391	pVM->pgm.s.cPrivatePages--;
1392	pVM->pgm.s.cZeroPages++;
1393
1394	/* Deal with write monitored pages. */
1395	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1396	{
1397	PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
1398	pVM->pgm.s.cWrittenToPages++;
1399	}
1400
1401	/*
1402	* pPage = ZERO page.
1403	*/
1404	PGM_PAGE_SET_HCPHYS(pVM, pPage, pVM->pgm.s.HCPhysZeroPg);
1405	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
1406	PGM_PAGE_SET_PAGEID(pVM, pPage, NIL_GMM_PAGEID);
1407	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_DONTCARE);
1408	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, 0);
1409	PGM_PAGE_SET_TRACKING(pVM, pPage, 0);
1410
1411	/* Flush physical page map TLB entry. */
1412	pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
1413
1414	#ifdef VBOX_WITH_PGM_NEM_MODE
1415	/*
1416	* Skip the rest if we're doing a bulk free in NEM memory mode.
1417	*/
1418	if (!pReq)
1419	return VINF_SUCCESS;
1420	AssertLogRelReturn(!pVM->pgm.s.fNemMode, VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
1421	#endif
1422
1423	#ifdef VBOX_WITH_NATIVE_NEM
1424	/* Notify NEM. */
1425	/** @todo Remove this one? */
1426	if (VM_IS_NEM_ENABLED(pVM))
1427	{
1428	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pPage);
1429	NEMHCNotifyPhysPageChanged(pVM, GCPhys, HCPhysPrev, pVM->pgm.s.HCPhysZeroPg, pVM->pgm.s.pvZeroPgR3,
1430	pgmPhysPageCalcNemProtection(pPage, enmNewType), enmNewType, &u2State);
1431	PGM_PAGE_SET_NEM_STATE(pPage, u2State);
1432	}
1433	#else
1434	RT_NOREF(enmNewType);
1435	#endif
1436
1437	/*
1438	* Make sure it's not in the handy page array.
1439	*/
1440	for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1441	{
1442	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
1443	{
1444	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_GMMPAGEDESC_PHYS;
1445	pVM->pgm.s.aHandyPages[i].fZeroed = false;
1446	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1447	break;
1448	}
1449	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
1450	{
1451	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1452	break;
1453	}
1454	}
1455
1456	/*
1457	* Push it onto the page array.
1458	*/
1459	uint32_t iPage = *pcPendingPages;
1460	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
1461	*pcPendingPages += 1;
1462
1463	pReq->aPages[iPage].idPage = idPage;
1464
1465	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
1466	return VINF_SUCCESS;
1467
1468	/*
1469	* Flush the pages.
1470	*/
1471	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
1472	if (RT_SUCCESS(rc))
1473	{
1474	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1475	*pcPendingPages = 0;
1476	}
1477	return rc;
1478	}
1479
1480
1481	/**
1482	* Frees a range of pages, replacing them with ZERO pages of the specified type.
1483	*
1484	* @returns VBox status code.
1485	* @param pVM The cross context VM structure.
1486	* @param pRam The RAM range in which the pages resides.
1487	* @param GCPhys The address of the first page.
1488	* @param GCPhysLast The address of the last page.
1489	* @param pvMmio2 Pointer to the ring-3 mapping of any MMIO2 memory that
1490	* will replace the pages we're freeing up.
1491	*/
1492	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, void *pvMmio2)
1493	{
1494	PGM_LOCK_ASSERT_OWNER(pVM);
1495
1496	#ifdef VBOX_WITH_PGM_NEM_MODE
1497	/*
1498	* In simplified memory mode we don't actually free the memory,
1499	* we just unmap it and let NEM do any unlocking of it.
1500	*/
1501	if (pVM->pgm.s.fNemMode)
1502	{
1503	Assert(VM_IS_NEM_ENABLED(pVM));
1504	uint32_t const fNemNotify = (pvMmio2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0) \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE;
1505	uint8_t u2State = 0; /* (We don't support UINT8_MAX here.) */
1506	int rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify,
1507	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL,
1508	pvMmio2, &u2State, NULL /puNemRange/);
1509	AssertLogRelRCReturn(rc, rc);
1510
1511	/* Iterate the pages. */
1512	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1513	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1514	while (cPagesLeft-- > 0)
1515	{
1516	rc = pgmPhysFreePage(pVM, NULL, NULL, pPageDst, GCPhys, PGMPAGETYPE_MMIO);
1517	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1518
1519	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO);
1520	PGM_PAGE_SET_NEM_STATE(pPageDst, u2State);
1521
1522	GCPhys += PAGE_SIZE;
1523	pPageDst++;
1524	}
1525	return rc;
1526	}
1527	#else /* !VBOX_WITH_PGM_NEM_MODE */
1528	RT_NOREF(pvMmio2);
1529	#endif /* !VBOX_WITH_PGM_NEM_MODE */
1530
1531	/*
1532	* Regular mode.
1533	*/
1534	/* Prepare. */
1535	uint32_t cPendingPages = 0;
1536	PGMMFREEPAGESREQ pReq;
1537	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1538	AssertLogRelRCReturn(rc, rc);
1539
1540	#ifdef VBOX_WITH_NATIVE_NEM
1541	/* Tell NEM up-front. */
1542	uint8_t u2State = UINT8_MAX;
1543	if (VM_IS_NEM_ENABLED(pVM))
1544	{
1545	uint32_t const fNemNotify = (pvMmio2 ? NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2 : 0) \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE;
1546	rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify, NULL, pvMmio2,
1547	&u2State, NULL /puNemRange/);
1548	AssertLogRelRCReturnStmt(rc, GMMR3FreePagesCleanup(pReq), rc);
1549	}
1550	#endif
1551
1552	/* Iterate the pages. */
1553	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1554	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
1555	while (cPagesLeft-- > 0)
1556	{
1557	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys, PGMPAGETYPE_MMIO);
1558	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1559
1560	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO);
1561	#ifdef VBOX_WITH_NATIVE_NEM
1562	if (u2State != UINT8_MAX)
1563	PGM_PAGE_SET_NEM_STATE(pPageDst, u2State);
1564	#endif
1565
1566	GCPhys += PAGE_SIZE;
1567	pPageDst++;
1568	}
1569
1570	/* Finish pending and cleanup. */
1571	if (cPendingPages)
1572	{
1573	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1574	AssertLogRelRCReturn(rc, rc);
1575	}
1576	GMMR3FreePagesCleanup(pReq);
1577
1578	return rc;
1579	}
1580
1581
1582	/**
1583	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
1584	*
1585	* In NEM mode, this will allocate the pages backing the RAM range and this may
1586	* fail. NEM registration may also fail. (In regular HM mode it won't fail.)
1587	*
1588	* @returns VBox status code.
1589	* @param pVM The cross context VM structure.
1590	* @param pNew The new RAM range.
1591	* @param GCPhys The address of the RAM range.
1592	* @param GCPhysLast The last address of the RAM range.
1593	* @param R0PtrNew Ditto for R0.
1594	* @param fFlags PGM_RAM_RANGE_FLAGS_FLOATING or zero.
1595	* @param pszDesc The description.
1596	* @param pPrev The previous RAM range (for linking).
1597	*/
1598	static int pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
1599	RTR0PTR R0PtrNew, uint32_t fFlags, const char *pszDesc, PPGMRAMRANGE pPrev)
1600	{
1601	/*
1602	* Initialize the range.
1603	*/
1604	pNew->pSelfR0 = R0PtrNew;
1605	pNew->GCPhys = GCPhys;
1606	pNew->GCPhysLast = GCPhysLast;
1607	pNew->cb = GCPhysLast - GCPhys + 1;
1608	pNew->pszDesc = pszDesc;
1609	pNew->fFlags = fFlags;
1610	pNew->uNemRange = UINT32_MAX;
1611	pNew->pvR3 = NULL;
1612	pNew->paLSPages = NULL;
1613
1614	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
1615	#ifdef VBOX_WITH_PGM_NEM_MODE
1616	if (!pVM->pgm.s.fNemMode)
1617	#endif
1618	{
1619	RTGCPHYS iPage = cPages;
1620	while (iPage-- > 0)
1621	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
1622
1623	/* Update the page count stats. */
1624	pVM->pgm.s.cZeroPages += cPages;
1625	pVM->pgm.s.cAllPages += cPages;
1626	}
1627	#ifdef VBOX_WITH_PGM_NEM_MODE
1628	else
1629	{
1630	int rc = SUPR3PageAlloc(cPages, pVM->pgm.s.fUseLargePages ? SUP_PAGE_ALLOC_F_LARGE_PAGES : 0, &pNew->pvR3);
1631	if (RT_FAILURE(rc))
1632	return rc;
1633
1634	RTGCPHYS iPage = cPages;
1635	while (iPage-- > 0)
1636	PGM_PAGE_INIT(&pNew->aPages[iPage], UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
1637	PGMPAGETYPE_RAM, PGM_PAGE_STATE_ALLOCATED);
1638
1639	/* Update the page count stats. */
1640	pVM->pgm.s.cPrivatePages += cPages;
1641	pVM->pgm.s.cAllPages += cPages;
1642	}
1643	#endif
1644
1645	/*
1646	* Link it.
1647	*/
1648	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
1649
1650	#ifdef VBOX_WITH_NATIVE_NEM
1651	/*
1652	* Notify NEM now that it has been linked.
1653	*/
1654	if (VM_IS_NEM_ENABLED(pVM))
1655	{
1656	uint8_t u2State = UINT8_MAX;
1657	int rc = NEMR3NotifyPhysRamRegister(pVM, GCPhys, pNew->cb, pNew->pvR3, &u2State, &pNew->uNemRange);
1658	if (RT_SUCCESS(rc))
1659	{
1660	if (u2State != UINT8_MAX)
1661	pgmPhysSetNemStateForPages(&pNew->aPages[0], cPages, u2State);
1662	}
1663	else
1664	pgmR3PhysUnlinkRamRange2(pVM, pNew, pPrev);
1665	return rc;
1666	}
1667	#endif
1668	return VINF_SUCCESS;
1669	}
1670
1671
1672	/**
1673	* PGMR3PhysRegisterRam worker that registers a high chunk.
1674	*
1675	* @returns VBox status code.
1676	* @param pVM The cross context VM structure.
1677	* @param GCPhys The address of the RAM.
1678	* @param cRamPages The number of RAM pages to register.
1679	* @param iChunk The chunk number.
1680	* @param pszDesc The RAM range description.
1681	* @param ppPrev Previous RAM range pointer. In/Out.
1682	*/
1683	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages, uint32_t iChunk,
1684	const char pszDesc, PPGMRAMRANGE ppPrev)
1685	{
1686	const char *pszDescChunk = iChunk == 0
1687	? pszDesc
1688	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
1689	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
1690
1691	/*
1692	* Allocate memory for the new chunk.
1693	*/
1694	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
1695	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
1696	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
1697	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
1698	void *pvChunk = NULL;
1699	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
1700	if (RT_SUCCESS(rc))
1701	{
1702	Assert(R0PtrChunk != NIL_RTR0PTR);
1703	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
1704
1705	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
1706
1707	/*
1708	* Ok, init and link the range.
1709	*/
1710	rc = pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
1711	R0PtrChunk, PGM_RAM_RANGE_FLAGS_FLOATING, pszDescChunk, *ppPrev);
1712	if (RT_SUCCESS(rc))
1713	*ppPrev = pNew;
1714
1715	if (RT_FAILURE(rc))
1716	SUPR3PageFreeEx(pvChunk, cChunkPages);
1717	}
1718
1719	RTMemTmpFree(paChunkPages);
1720	return rc;
1721	}
1722
1723
1724	/**
1725	* Sets up a range RAM.
1726	*
1727	* This will check for conflicting registrations, make a resource
1728	* reservation for the memory (with GMM), and setup the per-page
1729	* tracking structures (PGMPAGE).
1730	*
1731	* @returns VBox status code.
1732	* @param pVM The cross context VM structure.
1733	* @param GCPhys The physical address of the RAM.
1734	* @param cb The size of the RAM.
1735	* @param pszDesc The description - not copied, so, don't free or change it.
1736	*/
1737	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
1738	{
1739	/*
1740	* Validate input.
1741	*/
1742	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
1743	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1744	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1745	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
1746	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1747	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
1748	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1749	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1750
1751	PGM_LOCK_VOID(pVM);
1752
1753	/*
1754	* Find range location and check for conflicts.
1755	*/
1756	PPGMRAMRANGE pPrev = NULL;
1757	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
1758	while (pRam && GCPhysLast >= pRam->GCPhys)
1759	{
1760	AssertLogRelMsgReturnStmt( GCPhysLast < pRam->GCPhys
1761	\|\| GCPhys > pRam->GCPhysLast,
1762	("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1763	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1764	PGM_UNLOCK(pVM), VERR_PGM_RAM_CONFLICT);
1765
1766	/* next */
1767	pPrev = pRam;
1768	pRam = pRam->pNextR3;
1769	}
1770
1771	/*
1772	* Register it with GMM (the API bitches).
1773	*/
1774	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
1775	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
1776	if (RT_FAILURE(rc))
1777	{
1778	PGM_UNLOCK(pVM);
1779	return rc;
1780	}
1781
1782	if ( GCPhys >= _4G
1783	&& cPages > 256)
1784	{
1785	/*
1786	* The PGMRAMRANGE structures for the high memory can get very big.
1787	* There used to be some limitations on SUPR3PageAllocEx allocation
1788	* sizes, so traditionally we limited this to 16MB chunks. These days
1789	* we do ~64 MB chunks each covering 16GB of guest RAM, making sure
1790	* each range is a multiple of 1GB to enable eager hosts to use 1GB
1791	* pages in NEM mode.
1792	*
1793	* See also pgmR3PhysMmio2CalcChunkCount.
1794	*/
1795	uint32_t const cPagesPerChunk = _4M;
1796	Assert(RT_ALIGN_32(cPagesPerChunk, X86_PD_PAE_SHIFT - X86_PAGE_SHIFT)); /* NEM large page requirement: 1GB pages. */
1797
1798	RTGCPHYS cPagesLeft = cPages;
1799	RTGCPHYS GCPhysChunk = GCPhys;
1800	uint32_t iChunk = 0;
1801	while (cPagesLeft > 0)
1802	{
1803	uint32_t cPagesInChunk = cPagesLeft;
1804	if (cPagesInChunk > cPagesPerChunk)
1805	cPagesInChunk = cPagesPerChunk;
1806
1807	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, iChunk, pszDesc, &pPrev);
1808	AssertRCReturn(rc, rc);
1809
1810	/* advance */
1811	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1812	cPagesLeft -= cPagesInChunk;
1813	iChunk++;
1814	}
1815	}
1816	else
1817	{
1818	/*
1819	* Allocate, initialize and link the new RAM range.
1820	*/
1821	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
1822	PPGMRAMRANGE pNew;
1823	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1824	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc cbRamRange=%zu\n", rc, cbRamRange), rc);
1825
1826	rc = pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, MMHyperCCToR0(pVM, pNew), 0 /fFlags/, pszDesc, pPrev);
1827	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc cbRamRange=%zu\n", rc, cbRamRange), rc);
1828	}
1829	pgmPhysInvalidatePageMapTLB(pVM);
1830
1831	PGM_UNLOCK(pVM);
1832	return rc;
1833	}
1834
1835
1836	/**
1837	* Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1838	*
1839	* We do this late in the init process so that all the ROM and MMIO ranges have
1840	* been registered already and we don't go wasting memory on them.
1841	*
1842	* @returns VBox status code.
1843	*
1844	* @param pVM The cross context VM structure.
1845	*/
1846	int pgmR3PhysRamPreAllocate(PVM pVM)
1847	{
1848	Assert(pVM->pgm.s.fRamPreAlloc);
1849	Log(("pgmR3PhysRamPreAllocate: enter\n"));
1850	#ifdef VBOX_WITH_PGM_NEM_MODE
1851	AssertLogRelReturn(!pVM->pgm.s.fNemMode, VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
1852	#endif
1853
1854	/*
1855	* Walk the RAM ranges and allocate all RAM pages, halt at
1856	* the first allocation error.
1857	*/
1858	uint64_t cPages = 0;
1859	uint64_t NanoTS = RTTimeNanoTS();
1860	PGM_LOCK_VOID(pVM);
1861	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1862	{
1863	PPGMPAGE pPage = &pRam->aPages[0];
1864	RTGCPHYS GCPhys = pRam->GCPhys;
1865	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1866	while (cLeft-- > 0)
1867	{
1868	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1869	{
1870	switch (PGM_PAGE_GET_STATE(pPage))
1871	{
1872	case PGM_PAGE_STATE_ZERO:
1873	{
1874	int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1875	if (RT_FAILURE(rc))
1876	{
1877	LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1878	PGM_UNLOCK(pVM);
1879	return rc;
1880	}
1881	cPages++;
1882	break;
1883	}
1884
1885	case PGM_PAGE_STATE_BALLOONED:
1886	case PGM_PAGE_STATE_ALLOCATED:
1887	case PGM_PAGE_STATE_WRITE_MONITORED:
1888	case PGM_PAGE_STATE_SHARED:
1889	/* nothing to do here. */
1890	break;
1891	}
1892	}
1893
1894	/* next */
1895	pPage++;
1896	GCPhys += PAGE_SIZE;
1897	}
1898	}
1899	PGM_UNLOCK(pVM);
1900	NanoTS = RTTimeNanoTS() - NanoTS;
1901
1902	LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1903	Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1904	return VINF_SUCCESS;
1905	}
1906
1907
1908	/**
1909	* Checks shared page checksums.
1910	*
1911	* @param pVM The cross context VM structure.
1912	*/
1913	void pgmR3PhysAssertSharedPageChecksums(PVM pVM)
1914	{
1915	#ifdef VBOX_STRICT
1916	PGM_LOCK_VOID(pVM);
1917
1918	if (pVM->pgm.s.cSharedPages > 0)
1919	{
1920	/*
1921	* Walk the ram ranges.
1922	*/
1923	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
1924	{
1925	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1926	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1927
1928	while (iPage-- > 0)
1929	{
1930	PPGMPAGE pPage = &pRam->aPages[iPage];
1931	if (PGM_PAGE_IS_SHARED(pPage))
1932	{
1933	uint32_t u32Checksum = pPage->s.u2Unused0/* \| ((uint32_t)pPage->s.u2Unused1 << 8)*/;
1934	if (!u32Checksum)
1935	{
1936	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1937	void const *pvPage;
1938	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhysPage, &pvPage);
1939	if (RT_SUCCESS(rc))
1940	{
1941	uint32_t u32Checksum2 = RTCrc32(pvPage, PAGE_SIZE);
1942	# if 0
1943	AssertMsg((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum, ("GCPhysPage=%RGp\n", GCPhysPage));
1944	# else
1945	if ((u32Checksum2 & /UINT32_C(0x00000303)/ 0x3) == u32Checksum)
1946	LogFlow(("shpg %#x @ %RGp %#x [OK]\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1947	else
1948	AssertMsgFailed(("shpg %#x @ %RGp %#x\n", PGM_PAGE_GET_PAGEID(pPage), GCPhysPage, u32Checksum2));
1949	# endif
1950	}
1951	else
1952	AssertRC(rc);
1953	}
1954	}
1955
1956	} /* for each page */
1957
1958	} /* for each ram range */
1959	}
1960
1961	PGM_UNLOCK(pVM);
1962	#endif /* VBOX_STRICT */
1963	NOREF(pVM);
1964	}
1965
1966
1967	/**
1968	* Resets the physical memory state.
1969	*
1970	* ASSUMES that the caller owns the PGM lock.
1971	*
1972	* @returns VBox status code.
1973	* @param pVM The cross context VM structure.
1974	*/
1975	int pgmR3PhysRamReset(PVM pVM)
1976	{
1977	PGM_LOCK_ASSERT_OWNER(pVM);
1978
1979	/* Reset the memory balloon. */
1980	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
1981	AssertRC(rc);
1982
1983	#ifdef VBOX_WITH_PAGE_SHARING
1984	/* Clear all registered shared modules. */
1985	pgmR3PhysAssertSharedPageChecksums(pVM);
1986	rc = GMMR3ResetSharedModules(pVM);
1987	AssertRC(rc);
1988	#endif
1989	/* Reset counters. */
1990	pVM->pgm.s.cReusedSharedPages = 0;
1991	pVM->pgm.s.cBalloonedPages = 0;
1992
1993	return VINF_SUCCESS;
1994	}
1995
1996
1997	/**
1998	* Resets (zeros) the RAM after all devices and components have been reset.
1999	*
2000	* ASSUMES that the caller owns the PGM lock.
2001	*
2002	* @returns VBox status code.
2003	* @param pVM The cross context VM structure.
2004	*/
2005	int pgmR3PhysRamZeroAll(PVM pVM)
2006	{
2007	PGM_LOCK_ASSERT_OWNER(pVM);
2008
2009	/*
2010	* We batch up pages that should be freed instead of calling GMM for
2011	* each and every one of them.
2012	*/
2013	uint32_t cPendingPages = 0;
2014	PGMMFREEPAGESREQ pReq;
2015	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2016	AssertLogRelRCReturn(rc, rc);
2017
2018	/*
2019	* Walk the ram ranges.
2020	*/
2021	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2022	{
2023	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2024	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2025
2026	if ( !pVM->pgm.s.fRamPreAlloc
2027	#ifdef VBOX_WITH_PGM_NEM_MODE
2028	&& !pVM->pgm.s.fNemMode
2029	#endif
2030	&& pVM->pgm.s.fZeroRamPagesOnReset)
2031	{
2032	/* Replace all RAM pages by ZERO pages. */
2033	while (iPage-- > 0)
2034	{
2035	PPGMPAGE pPage = &pRam->aPages[iPage];
2036	switch (PGM_PAGE_GET_TYPE(pPage))
2037	{
2038	case PGMPAGETYPE_RAM:
2039	/* Do not replace pages part of a 2 MB continuous range
2040	with zero pages, but zero them instead. */
2041	if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE
2042	\|\| PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2043	{
2044	void *pvPage;
2045	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2046	AssertLogRelRCReturn(rc, rc);
2047	ASMMemZeroPage(pvPage);
2048	}
2049	else if (PGM_PAGE_IS_BALLOONED(pPage))
2050	{
2051	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2052	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2053	}
2054	else if (!PGM_PAGE_IS_ZERO(pPage))
2055	{
2056	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2057	PGMPAGETYPE_RAM);
2058	AssertLogRelRCReturn(rc, rc);
2059	}
2060	break;
2061
2062	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2063	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2064	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2065	pRam, true /fDoAccounting/);
2066	break;
2067
2068	case PGMPAGETYPE_MMIO2:
2069	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2070	case PGMPAGETYPE_ROM:
2071	case PGMPAGETYPE_MMIO:
2072	break;
2073	default:
2074	AssertFailed();
2075	}
2076	} /* for each page */
2077	}
2078	else
2079	{
2080	/* Zero the memory. */
2081	while (iPage-- > 0)
2082	{
2083	PPGMPAGE pPage = &pRam->aPages[iPage];
2084	switch (PGM_PAGE_GET_TYPE(pPage))
2085	{
2086	case PGMPAGETYPE_RAM:
2087	switch (PGM_PAGE_GET_STATE(pPage))
2088	{
2089	case PGM_PAGE_STATE_ZERO:
2090	break;
2091
2092	case PGM_PAGE_STATE_BALLOONED:
2093	/* Turn into a zero page; the balloon status is lost when the VM reboots. */
2094	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2095	break;
2096
2097	case PGM_PAGE_STATE_SHARED:
2098	case PGM_PAGE_STATE_WRITE_MONITORED:
2099	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
2100	AssertLogRelRCReturn(rc, rc);
2101	RT_FALL_THRU();
2102
2103	case PGM_PAGE_STATE_ALLOCATED:
2104	if (pVM->pgm.s.fZeroRamPagesOnReset)
2105	{
2106	void *pvPage;
2107	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
2108	AssertLogRelRCReturn(rc, rc);
2109	ASMMemZeroPage(pvPage);
2110	}
2111	break;
2112	}
2113	break;
2114
2115	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2116	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO: /** @todo perhaps leave the special page alone? I don't think VT-x copes with this code. */
2117	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2118	pRam, true /fDoAccounting/);
2119	break;
2120
2121	case PGMPAGETYPE_MMIO2:
2122	case PGMPAGETYPE_ROM_SHADOW:
2123	case PGMPAGETYPE_ROM:
2124	case PGMPAGETYPE_MMIO:
2125	break;
2126	default:
2127	AssertFailed();
2128
2129	}
2130	} /* for each page */
2131	}
2132
2133	}
2134
2135	/*
2136	* Finish off any pages pending freeing.
2137	*/
2138	if (cPendingPages)
2139	{
2140	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2141	AssertLogRelRCReturn(rc, rc);
2142	}
2143	GMMR3FreePagesCleanup(pReq);
2144	return VINF_SUCCESS;
2145	}
2146
2147
2148	/**
2149	* Frees all RAM during VM termination
2150	*
2151	* ASSUMES that the caller owns the PGM lock.
2152	*
2153	* @returns VBox status code.
2154	* @param pVM The cross context VM structure.
2155	*/
2156	int pgmR3PhysRamTerm(PVM pVM)
2157	{
2158	PGM_LOCK_ASSERT_OWNER(pVM);
2159
2160	/* Reset the memory balloon. */
2161	int rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_RESET, 0);
2162	AssertRC(rc);
2163
2164	#ifdef VBOX_WITH_PAGE_SHARING
2165	/*
2166	* Clear all registered shared modules.
2167	*/
2168	pgmR3PhysAssertSharedPageChecksums(pVM);
2169	rc = GMMR3ResetSharedModules(pVM);
2170	AssertRC(rc);
2171
2172	/*
2173	* Flush the handy pages updates to make sure no shared pages are hiding
2174	* in there. (Not unlikely if the VM shuts down, apparently.)
2175	*/
2176	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_FLUSH_HANDY_PAGES, 0, NULL);
2177	#endif
2178
2179	/*
2180	* We batch up pages that should be freed instead of calling GMM for
2181	* each and every one of them.
2182	*/
2183	uint32_t cPendingPages = 0;
2184	PGMMFREEPAGESREQ pReq;
2185	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2186	AssertLogRelRCReturn(rc, rc);
2187
2188	/*
2189	* Walk the ram ranges.
2190	*/
2191	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3; pRam; pRam = pRam->pNextR3)
2192	{
2193	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
2194	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
2195
2196	while (iPage-- > 0)
2197	{
2198	PPGMPAGE pPage = &pRam->aPages[iPage];
2199	switch (PGM_PAGE_GET_TYPE(pPage))
2200	{
2201	case PGMPAGETYPE_RAM:
2202	/* Free all shared pages. Private pages are automatically freed during GMM VM cleanup. */
2203	/** @todo change this to explicitly free private pages here. */
2204	if (PGM_PAGE_IS_SHARED(pPage))
2205	{
2206	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT),
2207	PGMPAGETYPE_RAM);
2208	AssertLogRelRCReturn(rc, rc);
2209	}
2210	break;
2211
2212	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
2213	case PGMPAGETYPE_SPECIAL_ALIAS_MMIO:
2214	case PGMPAGETYPE_MMIO2:
2215	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
2216	case PGMPAGETYPE_ROM:
2217	case PGMPAGETYPE_MMIO:
2218	break;
2219	default:
2220	AssertFailed();
2221	}
2222	} /* for each page */
2223	}
2224
2225	/*
2226	* Finish off any pages pending freeing.
2227	*/
2228	if (cPendingPages)
2229	{
2230	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2231	AssertLogRelRCReturn(rc, rc);
2232	}
2233	GMMR3FreePagesCleanup(pReq);
2234	return VINF_SUCCESS;
2235	}
2236
2237
2238
2239	/*********************************************************************************************************************************
2240	* MMIO *
2241	*********************************************************************************************************************************/
2242
2243	/**
2244	* This is the interface IOM is using to register an MMIO region.
2245	*
2246	* It will check for conflicts and ensure that a RAM range structure
2247	* is present before calling the PGMR3HandlerPhysicalRegister API to
2248	* register the callbacks.
2249	*
2250	* @returns VBox status code.
2251	*
2252	* @param pVM The cross context VM structure.
2253	* @param GCPhys The start of the MMIO region.
2254	* @param cb The size of the MMIO region.
2255	* @param hType The physical access handler type registration.
2256	* @param pvUserR3 The user argument for R3.
2257	* @param pvUserR0 The user argument for R0.
2258	* @param pvUserRC The user argument for RC.
2259	* @param pszDesc The description of the MMIO region.
2260	*/
2261	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
2262	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc)
2263	{
2264	/*
2265	* Assert on some assumption.
2266	*/
2267	VM_ASSERT_EMT(pVM);
2268	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2269	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2270	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2271	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
2272	Assert(((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(pVM, hType))->enmKind == PGMPHYSHANDLERKIND_MMIO);
2273
2274	int rc = PGM_LOCK(pVM);
2275	AssertRCReturn(rc, rc);
2276
2277	/*
2278	* Make sure there's a RAM range structure for the region.
2279	*/
2280	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2281	bool fRamExists = false;
2282	PPGMRAMRANGE pRamPrev = NULL;
2283	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2284	while (pRam && GCPhysLast >= pRam->GCPhys)
2285	{
2286	if ( GCPhysLast >= pRam->GCPhys
2287	&& GCPhys <= pRam->GCPhysLast)
2288	{
2289	/* Simplification: all within the same range. */
2290	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
2291	&& GCPhysLast <= pRam->GCPhysLast,
2292	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
2293	GCPhys, GCPhysLast, pszDesc,
2294	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2295	PGM_UNLOCK(pVM),
2296	VERR_PGM_RAM_CONFLICT);
2297
2298	/* Check that it's all RAM or MMIO pages. */
2299	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2300	uint32_t cLeft = cb >> PAGE_SHIFT;
2301	while (cLeft-- > 0)
2302	{
2303	AssertLogRelMsgReturnStmt( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2304	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
2305	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
2306	GCPhys, GCPhysLast, pszDesc, pRam->GCPhys, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
2307	PGM_UNLOCK(pVM),
2308	VERR_PGM_RAM_CONFLICT);
2309	pPage++;
2310	}
2311
2312	/* Looks good. */
2313	fRamExists = true;
2314	break;
2315	}
2316
2317	/* next */
2318	pRamPrev = pRam;
2319	pRam = pRam->pNextR3;
2320	}
2321	PPGMRAMRANGE pNew;
2322	if (fRamExists)
2323	{
2324	pNew = NULL;
2325
2326	/*
2327	* Make all the pages in the range MMIO/ZERO pages, freeing any
2328	* RAM pages currently mapped here. This might not be 100% correct
2329	* for PCI memory, but we're doing the same thing for MMIO2 pages.
2330	*/
2331	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, NULL);
2332	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
2333
2334	/* Force a PGM pool flush as guest ram references have been changed. */
2335	/** @todo not entirely SMP safe; assuming for now the guest takes
2336	* care of this internally (not touch mapped mmio while changing the
2337	* mapping). */
2338	PVMCPU pVCpu = VMMGetCpu(pVM);
2339	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2340	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2341	}
2342	else
2343	{
2344	/*
2345	* No RAM range, insert an ad hoc one.
2346	*
2347	* Note that we don't have to tell REM about this range because
2348	* PGMHandlerPhysicalRegisterEx will do that for us.
2349	*/
2350	Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
2351
2352	/* Alloc. */
2353	const uint32_t cPages = cb >> PAGE_SHIFT;
2354	const size_t cbRamRange = RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]);
2355	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
2356	AssertLogRelMsgRCReturnStmt(rc, ("cbRamRange=%zu\n", cbRamRange), PGM_UNLOCK(pVM), rc);
2357
2358	#ifdef VBOX_WITH_NATIVE_NEM
2359	/* Notify NEM. */
2360	uint8_t u2State = 0; /* (must have valid state as there can't be anything to preserve) */
2361	if (VM_IS_NEM_ENABLED(pVM))
2362	{
2363	rc = NEMR3NotifyPhysMmioExMapEarly(pVM, GCPhys, cPages << PAGE_SHIFT, 0 /fFlags/, NULL, NULL,
2364	&u2State, &pNew->uNemRange);
2365	AssertLogRelRCReturnStmt(rc, MMHyperFree(pVM, pNew), rc);
2366	}
2367	#endif
2368
2369	/* Initialize the range. */
2370	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
2371	pNew->GCPhys = GCPhys;
2372	pNew->GCPhysLast = GCPhysLast;
2373	pNew->cb = cb;
2374	pNew->pszDesc = pszDesc;
2375	pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
2376	pNew->pvR3 = NULL;
2377	pNew->paLSPages = NULL;
2378
2379	uint32_t iPage = cPages;
2380	while (iPage-- > 0)
2381	{
2382	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
2383	#ifdef VBOX_WITH_NATIVE_NEM
2384	PGM_PAGE_SET_NEM_STATE(&pNew->aPages[iPage], u2State);
2385	#endif
2386	}
2387	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
2388
2389	/* update the page count stats. */
2390	pVM->pgm.s.cPureMmioPages += cPages;
2391	pVM->pgm.s.cAllPages += cPages;
2392
2393	/* link it */
2394	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
2395	}
2396
2397	/*
2398	* Register the access handler.
2399	*/
2400	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, hType, pvUserR3, pvUserR0, pvUserRC, pszDesc);
2401	if (RT_SUCCESS(rc))
2402	{
2403	#ifdef VBOX_WITH_NATIVE_NEM
2404	/* Late NEM notification. */
2405	if (VM_IS_NEM_ENABLED(pVM))
2406	{
2407	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE : 0);
2408	rc = NEMR3NotifyPhysMmioExMapLate(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemNotify,
2409	fRamExists ? (uint8_t *)pRam->pvR3 + (uintptr_t)(GCPhys - pRam->GCPhys) : NULL,
2410	NULL, !fRamExists ? &pRam->uNemRange : NULL);
2411	AssertLogRelRCReturn(rc, rc);
2412	}
2413	#endif
2414	}
2415	/** @todo the phys handler failure handling isn't complete, esp. wrt NEM. */
2416	else if (!fRamExists)
2417	{
2418	pVM->pgm.s.cPureMmioPages -= cb >> PAGE_SHIFT;
2419	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
2420
2421	/* remove the ad hoc range. */
2422	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
2423	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
2424	MMHyperFree(pVM, pRam);
2425	}
2426	pgmPhysInvalidatePageMapTLB(pVM);
2427
2428	PGM_UNLOCK(pVM);
2429	return rc;
2430	}
2431
2432
2433	/**
2434	* This is the interface IOM is using to register an MMIO region.
2435	*
2436	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
2437	* any ad hoc PGMRAMRANGE left behind.
2438	*
2439	* @returns VBox status code.
2440	* @param pVM The cross context VM structure.
2441	* @param GCPhys The start of the MMIO region.
2442	* @param cb The size of the MMIO region.
2443	*/
2444	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
2445	{
2446	VM_ASSERT_EMT(pVM);
2447
2448	int rc = PGM_LOCK(pVM);
2449	AssertRCReturn(rc, rc);
2450
2451	/*
2452	* First deregister the handler, then check if we should remove the ram range.
2453	*/
2454	rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2455	if (RT_SUCCESS(rc))
2456	{
2457	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2458	PPGMRAMRANGE pRamPrev = NULL;
2459	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
2460	while (pRam && GCPhysLast >= pRam->GCPhys)
2461	{
2462	/** @todo We're being a bit too careful here. rewrite. */
2463	if ( GCPhysLast == pRam->GCPhysLast
2464	&& GCPhys == pRam->GCPhys)
2465	{
2466	Assert(pRam->cb == cb);
2467
2468	/*
2469	* See if all the pages are dead MMIO pages.
2470	*/
2471	uint32_t const cPages = cb >> PAGE_SHIFT;
2472	bool fAllMMIO = true;
2473	uint32_t iPage = 0;
2474	uint32_t cLeft = cPages;
2475	while (cLeft-- > 0)
2476	{
2477	PPGMPAGE pPage = &pRam->aPages[iPage];
2478	if ( !PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)
2479	/\|\| not-out-of-action later /)
2480	{
2481	fAllMMIO = false;
2482	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2483	break;
2484	}
2485	Assert( PGM_PAGE_IS_ZERO(pPage)
2486	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2487	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO);
2488	pPage++;
2489	}
2490	if (fAllMMIO)
2491	{
2492	/*
2493	* Ad-hoc range, unlink and free it.
2494	*/
2495	Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
2496	GCPhys, GCPhysLast, pRam->pszDesc));
2497	/** @todo check the ad-hoc flags? */
2498
2499	#ifdef VBOX_WITH_NATIVE_NEM
2500	if (VM_IS_NEM_ENABLED(pVM)) /* Notify REM before we unlink the range. */
2501	{
2502	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhys, GCPhysLast - GCPhys + 1, 0 /fFlags/,
2503	NULL, NULL, NULL, &pRam->uNemRange);
2504	AssertLogRelRCReturn(rc, rc);
2505	}
2506	#endif
2507
2508	pVM->pgm.s.cAllPages -= cPages;
2509	pVM->pgm.s.cPureMmioPages -= cPages;
2510
2511	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
2512	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
2513	MMHyperFree(pVM, pRam);
2514	break;
2515	}
2516	}
2517
2518	/*
2519	* Range match? It will all be within one range (see PGMAllHandler.cpp).
2520	*/
2521	if ( GCPhysLast >= pRam->GCPhys
2522	&& GCPhys <= pRam->GCPhysLast)
2523	{
2524	Assert(GCPhys >= pRam->GCPhys);
2525	Assert(GCPhysLast <= pRam->GCPhysLast);
2526
2527	/*
2528	* Turn the pages back into RAM pages.
2529	*/
2530	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2531	uint32_t cLeft = cb >> PAGE_SHIFT;
2532	while (cLeft--)
2533	{
2534	PPGMPAGE pPage = &pRam->aPages[iPage];
2535	AssertMsg( (PGM_PAGE_IS_MMIO(pPage) && PGM_PAGE_IS_ZERO(pPage))
2536	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO
2537	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
2538	("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
2539	if (PGM_PAGE_IS_MMIO_OR_ALIAS(pPage))
2540	PGM_PAGE_SET_TYPE(pVM, pPage, PGMPAGETYPE_RAM);
2541	iPage++;
2542	}
2543
2544	#ifdef VBOX_WITH_NATIVE_NEM
2545	/* Notify REM (failure will probably leave things in a non-working state). */
2546	if (VM_IS_NEM_ENABLED(pVM))
2547	{
2548	uint8_t u2State = UINT8_MAX;
2549	rc = NEMR3NotifyPhysMmioExUnmap(pVM, GCPhys, GCPhysLast - GCPhys + 1, NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
2550	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL,
2551	NULL, &u2State, &pRam->uNemRange);
2552	AssertLogRelRCReturn(rc, rc);
2553	if (u2State != UINT8_MAX)
2554	pgmPhysSetNemStateForPages(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT],
2555	cb >> PAGE_SHIFT, u2State);
2556	}
2557	#endif
2558	break;
2559	}
2560
2561	/* next */
2562	pRamPrev = pRam;
2563	pRam = pRam->pNextR3;
2564	}
2565	}
2566
2567	/* Force a PGM pool flush as guest ram references have been changed. */
2568	/** @todo Not entirely SMP safe; assuming for now the guest takes care of
2569	* this internally (not touch mapped mmio while changing the mapping). */
2570	PVMCPU pVCpu = VMMGetCpu(pVM);
2571	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2572	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2573
2574	pgmPhysInvalidatePageMapTLB(pVM);
2575	pgmPhysInvalidRamRangeTlbs(pVM);
2576	PGM_UNLOCK(pVM);
2577	return rc;
2578	}
2579
2580
2581
2582	/*********************************************************************************************************************************
2583	* MMIO2 *
2584	*********************************************************************************************************************************/
2585
2586	/**
2587	* Locate a MMIO2 range.
2588	*
2589	* @returns Pointer to the MMIO2 range.
2590	* @param pVM The cross context VM structure.
2591	* @param pDevIns The device instance owning the region.
2592	* @param iSubDev The sub-device number.
2593	* @param iRegion The region.
2594	* @param hMmio2 Handle to look up. If NIL, use the @a iSubDev and
2595	* @a iRegion.
2596	*/
2597	DECLINLINE(PPGMREGMMIO2RANGE) pgmR3PhysMmio2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev,
2598	uint32_t iRegion, PGMMMIO2HANDLE hMmio2)
2599	{
2600	if (hMmio2 != NIL_PGMMMIO2HANDLE)
2601	{
2602	if (hMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3) && hMmio2 != 0)
2603	{
2604	PPGMREGMMIO2RANGE pCur = pVM->pgm.s.apMmio2RangesR3[hMmio2 - 1];
2605	if (pCur && pCur->pDevInsR3 == pDevIns)
2606	{
2607	Assert(pCur->idMmio2 == hMmio2);
2608	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, NULL);
2609	return pCur;
2610	}
2611	Assert(!pCur);
2612	}
2613	for (PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2614	if (pCur->idMmio2 == hMmio2)
2615	{
2616	AssertBreak(pCur->pDevInsR3 == pDevIns);
2617	AssertReturn(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, NULL);
2618	return pCur;
2619	}
2620	}
2621	else
2622	{
2623	/*
2624	* Search the list. There shouldn't be many entries.
2625	*/
2626	/** @todo Optimize this lookup! There may now be many entries and it'll
2627	* become really slow when doing MMR3HyperMapMMIO2 and similar. */
2628	for (PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3; pCur; pCur = pCur->pNextR3)
2629	if ( pCur->pDevInsR3 == pDevIns
2630	&& pCur->iRegion == iRegion
2631	&& pCur->iSubDev == iSubDev)
2632	return pCur;
2633	}
2634	return NULL;
2635	}
2636
2637
2638	/**
2639	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking and PGMR3PhysMmio2Map.
2640	*/
2641	static int pgmR3PhysMmio2EnableDirtyPageTracing(PVM pVM, PPGMREGMMIO2RANGE pFirstMmio2)
2642	{
2643	int rc = VINF_SUCCESS;
2644	for (PPGMREGMMIO2RANGE pCurMmio2 = pFirstMmio2; pCurMmio2; pCurMmio2 = pCurMmio2->pNextR3)
2645	{
2646	Assert(!(pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_IS_TRACKING));
2647	int rc2 = pgmHandlerPhysicalExRegister(pVM, pCurMmio2->pPhysHandlerR3, pCurMmio2->RamRange.GCPhys,
2648	pCurMmio2->RamRange.GCPhysLast);
2649	AssertLogRelMsgRC(rc2, ("%#RGp-%#RGp %s failed -> %Rrc\n", pCurMmio2->RamRange.GCPhys, pCurMmio2->RamRange.GCPhysLast,
2650	pCurMmio2->RamRange.pszDesc, rc2));
2651	if (RT_SUCCESS(rc2))
2652	pCurMmio2->fFlags \|= PGMREGMMIO2RANGE_F_IS_TRACKING;
2653	else if (RT_SUCCESS(rc))
2654	rc = rc2;
2655	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2656	return rc;
2657	}
2658	AssertFailed();
2659	return rc;
2660	}
2661
2662
2663	/**
2664	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking and PGMR3PhysMmio2Unmap.
2665	*/
2666	static int pgmR3PhysMmio2DisableDirtyPageTracing(PVM pVM, PPGMREGMMIO2RANGE pFirstMmio2)
2667	{
2668	for (PPGMREGMMIO2RANGE pCurMmio2 = pFirstMmio2; pCurMmio2; pCurMmio2 = pCurMmio2->pNextR3)
2669	{
2670	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_IS_TRACKING)
2671	{
2672	int rc2 = pgmHandlerPhysicalExDeregister(pVM, pCurMmio2->pPhysHandlerR3);
2673	AssertLogRelMsgRC(rc2, ("%#RGp-%#RGp %s failed -> %Rrc\n", pCurMmio2->RamRange.GCPhys, pCurMmio2->RamRange.GCPhysLast,
2674	pCurMmio2->RamRange.pszDesc, rc2));
2675	pCurMmio2->fFlags &= ~PGMREGMMIO2RANGE_F_IS_TRACKING;
2676	}
2677	if (pCurMmio2->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2678	return VINF_SUCCESS;
2679	}
2680	AssertFailed();
2681	return VINF_SUCCESS;
2682
2683	}
2684
2685
2686	/**
2687	* Calculates the number of chunks
2688	*
2689	* @returns Number of registration chunk needed.
2690	* @param pVM The cross context VM structure.
2691	* @param cb The size of the MMIO/MMIO2 range.
2692	* @param pcPagesPerChunk Where to return the number of pages tracked by each
2693	* chunk. Optional.
2694	* @param pcbChunk Where to return the guest mapping size for a chunk.
2695	*/
2696	static uint16_t pgmR3PhysMmio2CalcChunkCount(PVM pVM, RTGCPHYS cb, uint32_t pcPagesPerChunk, uint32_t pcbChunk)
2697	{
2698	RT_NOREF_PV(pVM); /* without raw mode */
2699
2700	/*
2701	* This is the same calculation as PGMR3PhysRegisterRam does, except we'll be
2702	* needing a few bytes extra the PGMREGMMIO2RANGE structure.
2703	*
2704	* Note! In additions, we've got a 24 bit sub-page range for MMIO2 ranges, leaving
2705	* us with an absolute maximum of 16777215 pages per chunk (close to 64 GB).
2706	*/
2707	uint32_t const cPagesPerChunk = _4M;
2708	Assert(RT_ALIGN_32(cPagesPerChunk, X86_PD_PAE_SHIFT - X86_PAGE_SHIFT)); /* NEM large page requirement: 1GB pages. */
2709	uint32_t const cbChunk = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPagesPerChunk]);
2710	AssertRelease(cPagesPerChunk < _16M);
2711
2712	if (pcbChunk)
2713	*pcbChunk = cbChunk;
2714	if (pcPagesPerChunk)
2715	*pcPagesPerChunk = cPagesPerChunk;
2716
2717	/* Calc the number of chunks we need. */
2718	RTGCPHYS const cPages = cb >> X86_PAGE_SHIFT;
2719	uint16_t cChunks = (uint16_t)((cPages + cPagesPerChunk - 1) / cPagesPerChunk);
2720	AssertRelease((RTGCPHYS)cChunks * cPagesPerChunk >= cPages);
2721	return cChunks;
2722	}
2723
2724
2725	/**
2726	* Worker for PGMR3PhysMMIO2Register that allocates and the PGMREGMMIO2RANGE
2727	* structures and does basic initialization.
2728	*
2729	* Caller must set type specfic members and initialize the PGMPAGE structures.
2730	*
2731	* This was previously also used by PGMR3PhysMmio2PreRegister, a function for
2732	* pre-registering MMIO that was later (6.1) replaced by a new handle based IOM
2733	* interface. The reference to caller and type above is purely historical.
2734	*
2735	* @returns VBox status code.
2736	* @param pVM The cross context VM structure.
2737	* @param pDevIns The device instance owning the region.
2738	* @param iSubDev The sub-device number (internal PCI config number).
2739	* @param iRegion The region number. If the MMIO2 memory is a PCI
2740	* I/O region this number has to be the number of that
2741	* region. Otherwise it can be any number safe
2742	* UINT8_MAX.
2743	* @param cb The size of the region. Must be page aligned.
2744	* @param fFlags PGMPHYS_MMIO2_FLAGS_XXX.
2745	* @param idMmio2 The MMIO2 ID for the first chunk.
2746	* @param pszDesc The description.
2747	* @param ppHeadRet Where to return the pointer to the first
2748	* registration chunk.
2749	*
2750	* @thread EMT
2751	*/
2752	static int pgmR3PhysMmio2Create(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags,
2753	uint8_t idMmio2, const char pszDesc, PPGMREGMMIO2RANGE ppHeadRet)
2754	{
2755	/*
2756	* Figure out how many chunks we need and of which size.
2757	*/
2758	uint32_t cPagesPerChunk;
2759	uint16_t cChunks = pgmR3PhysMmio2CalcChunkCount(pVM, cb, &cPagesPerChunk, NULL);
2760	AssertReturn(cChunks, VERR_PGM_PHYS_MMIO_EX_IPE);
2761
2762	/*
2763	* Allocate the chunks.
2764	*/
2765	PPGMREGMMIO2RANGE *ppNext = ppHeadRet;
2766	*ppNext = NULL;
2767
2768	int rc = VINF_SUCCESS;
2769	uint32_t cPagesLeft = cb >> X86_PAGE_SHIFT;
2770	for (uint16_t iChunk = 0; iChunk < cChunks && RT_SUCCESS(rc); iChunk++, idMmio2++)
2771	{
2772	/*
2773	* We currently do a single RAM range for the whole thing. This will
2774	* probably have to change once someone needs really large MMIO regions,
2775	* as we will be running into SUPR3PageAllocEx limitations and such.
2776	*/
2777	const uint32_t cPagesTrackedByChunk = RT_MIN(cPagesLeft, cPagesPerChunk);
2778	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPagesTrackedByChunk]);
2779	PPGMREGMMIO2RANGE pNew = NULL;
2780	if ( iChunk + 1 < cChunks
2781	\|\| cbRange >= _1M)
2782	{
2783	/*
2784	* Allocate memory for the registration structure.
2785	*/
2786	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2787	size_t const cbChunk = (1 + cChunkPages + 1) << PAGE_SHIFT;
2788	AssertLogRelBreakStmt(cbChunk == (uint32_t)cbChunk, rc = VERR_OUT_OF_RANGE);
2789	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
2790	AssertBreakStmt(paChunkPages, rc = VERR_NO_TMP_MEMORY);
2791	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
2792	void *pvChunk = NULL;
2793	rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk, &R0PtrChunk, paChunkPages);
2794	AssertLogRelMsgRCBreakStmt(rc, ("rc=%Rrc, cChunkPages=%#zx\n", rc, cChunkPages), RTMemTmpFree(paChunkPages));
2795
2796	Assert(R0PtrChunk != NIL_RTR0PTR);
2797	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
2798
2799	pNew = (PPGMREGMMIO2RANGE)pvChunk;
2800	pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_FLOATING;
2801	pNew->RamRange.pSelfR0 = R0PtrChunk + RT_UOFFSETOF(PGMREGMMIO2RANGE, RamRange);
2802
2803	RTMemTmpFree(paChunkPages);
2804	}
2805	/*
2806	* Not so big, do a one time hyper allocation.
2807	*/
2808	else
2809	{
2810	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
2811	AssertLogRelMsgRCBreak(rc, ("cbRange=%zu\n", cbRange));
2812
2813	/*
2814	* Initialize allocation specific items.
2815	*/
2816	//pNew->RamRange.fFlags = 0;
2817	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
2818	}
2819
2820	/*
2821	* Initialize the registration structure (caller does specific bits).
2822	*/
2823	pNew->pDevInsR3 = pDevIns;
2824	//pNew->pvR3 = NULL;
2825	//pNew->pNext = NULL;
2826	if (iChunk == 0)
2827	pNew->fFlags \|= PGMREGMMIO2RANGE_F_FIRST_CHUNK;
2828	if (iChunk + 1 == cChunks)
2829	pNew->fFlags \|= PGMREGMMIO2RANGE_F_LAST_CHUNK;
2830	if (fFlags & PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES)
2831	pNew->fFlags \|= PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES;
2832	pNew->iSubDev = iSubDev;
2833	pNew->iRegion = iRegion;
2834	pNew->idSavedState = UINT8_MAX;
2835	pNew->idMmio2 = idMmio2;
2836	//pNew->pPhysHandlerR3 = NULL;
2837	//pNew->paLSPages = NULL;
2838	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
2839	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
2840	pNew->RamRange.pszDesc = pszDesc;
2841	pNew->RamRange.cb = pNew->cbReal = (RTGCPHYS)cPagesTrackedByChunk << X86_PAGE_SHIFT;
2842	pNew->RamRange.fFlags \|= PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX;
2843	pNew->RamRange.uNemRange = UINT32_MAX;
2844	//pNew->RamRange.pvR3 = NULL;
2845	//pNew->RamRange.paLSPages = NULL;
2846
2847	*ppNext = pNew;
2848	ASMCompilerBarrier();
2849	cPagesLeft -= cPagesTrackedByChunk;
2850	ppNext = &pNew->pNextR3;
2851
2852	/*
2853	* Pre-allocate a handler if we're tracking dirty pages, unless NEM takes care of this.
2854	*/
2855	if ( (fFlags & PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES)
2856	#ifdef VBOX_WITH_PGM_NEM_MODE
2857	&& (!VM_IS_NEM_ENABLED(pVM) \|\| !NEMR3IsMmio2DirtyPageTrackingSupported(pVM))
2858	#endif
2859	)
2860
2861	{
2862	rc = pgmHandlerPhysicalExCreate(pVM, pVM->pgm.s.hMmio2DirtyPhysHandlerType,
2863	(RTR3PTR)(uintptr_t)idMmio2, idMmio2, idMmio2, pszDesc, &pNew->pPhysHandlerR3);
2864	AssertLogRelMsgRCBreak(rc, ("idMmio2=%zu\n", idMmio2));
2865	}
2866	}
2867	Assert(cPagesLeft == 0);
2868
2869	if (RT_SUCCESS(rc))
2870	{
2871	Assert((*ppHeadRet)->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
2872	return VINF_SUCCESS;
2873	}
2874
2875	/*
2876	* Free floating ranges.
2877	*/
2878	while (*ppHeadRet)
2879	{
2880	PPGMREGMMIO2RANGE pFree = *ppHeadRet;
2881	*ppHeadRet = pFree->pNextR3;
2882
2883	if (pFree->pPhysHandlerR3)
2884	{
2885	pgmHandlerPhysicalExDestroy(pVM, pFree->pPhysHandlerR3);
2886	pFree->pPhysHandlerR3 = NULL;
2887	}
2888
2889	if (pFree->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
2890	{
2891	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[pFree->RamRange.cb >> X86_PAGE_SHIFT]);
2892	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
2893	SUPR3PageFreeEx(pFree, cChunkPages);
2894	}
2895	}
2896
2897	return rc;
2898	}
2899
2900
2901	/**
2902	* Common worker PGMR3PhysMmio2PreRegister & PGMR3PhysMMIO2Register that links a
2903	* complete registration entry into the lists and lookup tables.
2904	*
2905	* @param pVM The cross context VM structure.
2906	* @param pNew The new MMIO / MMIO2 registration to link.
2907	*/
2908	static void pgmR3PhysMmio2Link(PVM pVM, PPGMREGMMIO2RANGE pNew)
2909	{
2910	Assert(pNew->idMmio2 != UINT8_MAX);
2911
2912	/*
2913	* Link it into the list (order doesn't matter, so insert it at the head).
2914	*
2915	* Note! The range we're linking may consist of multiple chunks, so we
2916	* have to find the last one.
2917	*/
2918	PPGMREGMMIO2RANGE pLast = pNew;
2919	for (pLast = pNew; ; pLast = pLast->pNextR3)
2920	{
2921	if (pLast->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2922	break;
2923	Assert(pLast->pNextR3);
2924	Assert(pLast->pNextR3->pDevInsR3 == pNew->pDevInsR3);
2925	Assert(pLast->pNextR3->iSubDev == pNew->iSubDev);
2926	Assert(pLast->pNextR3->iRegion == pNew->iRegion);
2927	Assert(pLast->pNextR3->idMmio2 == pLast->idMmio2 + 1);
2928	}
2929
2930	PGM_LOCK_VOID(pVM);
2931
2932	/* Link in the chain of ranges at the head of the list. */
2933	pLast->pNextR3 = pVM->pgm.s.pRegMmioRangesR3;
2934	pVM->pgm.s.pRegMmioRangesR3 = pNew;
2935
2936	/* Insert the MMIO2 range/page IDs. */
2937	uint8_t idMmio2 = pNew->idMmio2;
2938	for (;;)
2939	{
2940	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == NULL);
2941	Assert(pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] == NIL_RTR0PTR);
2942	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = pNew;
2943	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = pNew->RamRange.pSelfR0 - RT_UOFFSETOF(PGMREGMMIO2RANGE, RamRange);
2944	if (pNew->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
2945	break;
2946	pNew = pNew->pNextR3;
2947	idMmio2++;
2948	}
2949
2950	pgmPhysInvalidatePageMapTLB(pVM);
2951	PGM_UNLOCK(pVM);
2952	}
2953
2954
2955	/**
2956	* Allocate and register an MMIO2 region.
2957	*
2958	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2959	* associated with a device. It is also non-shared memory with a permanent
2960	* ring-3 mapping and page backing (presently).
2961	*
2962	* A MMIO2 range may overlap with base memory if a lot of RAM is configured for
2963	* the VM, in which case we'll drop the base memory pages. Presently we will
2964	* make no attempt to preserve anything that happens to be present in the base
2965	* memory that is replaced, this is of course incorrect but it's too much
2966	* effort.
2967	*
2968	* @returns VBox status code.
2969	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the
2970	* memory.
2971	* @retval VERR_ALREADY_EXISTS if the region already exists.
2972	*
2973	* @param pVM The cross context VM structure.
2974	* @param pDevIns The device instance owning the region.
2975	* @param iSubDev The sub-device number.
2976	* @param iRegion The region number. If the MMIO2 memory is a PCI
2977	* I/O region this number has to be the number of that
2978	* region. Otherwise it can be any number save
2979	* UINT8_MAX.
2980	* @param cb The size of the region. Must be page aligned.
2981	* @param fFlags Reserved for future use, must be zero.
2982	* @param pszDesc The description.
2983	* @param ppv Where to store the pointer to the ring-3 mapping of
2984	* the memory.
2985	* @param phRegion Where to return the MMIO2 region handle. Optional.
2986	* @thread EMT
2987	*/
2988	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
2989	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion)
2990	{
2991	/*
2992	* Validate input.
2993	*/
2994	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
2995	*ppv = NULL;
2996	if (phRegion)
2997	{
2998	AssertPtrReturn(phRegion, VERR_INVALID_POINTER);
2999	*phRegion = NIL_PGMMMIO2HANDLE;
3000	}
3001	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3002	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3003	AssertReturn(iSubDev <= UINT8_MAX, VERR_INVALID_PARAMETER);
3004	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
3005	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
3006	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
3007	AssertReturn(pgmR3PhysMmio2Find(pVM, pDevIns, iSubDev, iRegion, NIL_PGMMMIO2HANDLE) == NULL, VERR_ALREADY_EXISTS);
3008	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3009	AssertReturn(cb, VERR_INVALID_PARAMETER);
3010	AssertReturn(!(fFlags & ~PGMPHYS_MMIO2_FLAGS_VALID_MASK), VERR_INVALID_FLAGS);
3011
3012	const uint32_t cPages = cb >> PAGE_SHIFT;
3013	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
3014	AssertLogRelReturn(cPages <= (MM_MMIO_64_MAX >> X86_PAGE_SHIFT), VERR_OUT_OF_RANGE);
3015	AssertLogRelReturn(cPages <= PGM_MMIO2_MAX_PAGE_COUNT, VERR_OUT_OF_RANGE);
3016
3017	/*
3018	* For the 2nd+ instance, mangle the description string so it's unique.
3019	*/
3020	if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
3021	{
3022	pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
3023	if (!pszDesc)
3024	return VERR_NO_MEMORY;
3025	}
3026
3027	/*
3028	* Allocate an MMIO2 range ID (not freed on failure).
3029	*
3030	* The zero ID is not used as it could be confused with NIL_GMM_PAGEID, so
3031	* the IDs goes from 1 thru PGM_MMIO2_MAX_RANGES.
3032	*/
3033	unsigned cChunks = pgmR3PhysMmio2CalcChunkCount(pVM, cb, NULL, NULL);
3034
3035	PGM_LOCK_VOID(pVM);
3036	AssertCompile(PGM_MMIO2_MAX_RANGES < 255);
3037	uint8_t const idMmio2 = pVM->pgm.s.cMmio2Regions + 1;
3038	unsigned const cNewMmio2Regions = pVM->pgm.s.cMmio2Regions + cChunks;
3039	if (cNewMmio2Regions > PGM_MMIO2_MAX_RANGES)
3040	{
3041	PGM_UNLOCK(pVM);
3042	AssertLogRelFailedReturn(VERR_PGM_TOO_MANY_MMIO2_RANGES);
3043	}
3044	pVM->pgm.s.cMmio2Regions = cNewMmio2Regions;
3045	PGM_UNLOCK(pVM);
3046
3047	/*
3048	* Try reserve and allocate the backing memory first as this is what is
3049	* most likely to fail.
3050	*/
3051	int rc = VINF_SUCCESS;
3052	#ifdef VBOX_WITH_PGM_NEM_MODE
3053	if (!pVM->pgm.s.fNemMode)
3054	#endif
3055	rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
3056	if (RT_SUCCESS(rc))
3057	{
3058	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
3059	if (RT_SUCCESS(rc))
3060	{
3061	void *pvPages;
3062	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3063	RTR0PTR pvPagesR0 = NIL_RTR0PTR;
3064	#endif
3065
3066	#ifdef VBOX_WITH_PGM_NEM_MODE
3067	if (!pVM->pgm.s.fNemMode)
3068	#endif
3069	{
3070	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3071	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, &pvPagesR0, paPages);
3072	#else
3073	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
3074	#endif
3075	}
3076	#ifdef VBOX_WITH_PGM_NEM_MODE
3077	else
3078	{
3079	rc = SUPR3PageAlloc(cPages, pVM->pgm.s.fUseLargePages ? SUP_PAGE_ALLOC_F_LARGE_PAGES : 0, &pvPages);
3080	if (RT_SUCCESS(rc))
3081	for (uint32_t i = 0; i < cPages; i++)
3082	paPages[i].Phys = UINT64_C(0x0000fffffffff000);
3083	}
3084	#endif
3085	if (RT_SUCCESS(rc))
3086	{
3087	memset(pvPages, 0, cPages * PAGE_SIZE);
3088
3089	/*
3090	* Create the registered MMIO range record for it.
3091	*/
3092	PPGMREGMMIO2RANGE pNew;
3093	rc = pgmR3PhysMmio2Create(pVM, pDevIns, iSubDev, iRegion, cb, fFlags, idMmio2, pszDesc, &pNew);
3094	if (RT_SUCCESS(rc))
3095	{
3096	if (phRegion)
3097	phRegion = idMmio2; / The ID of the first chunk. */
3098
3099	uint32_t iSrcPage = 0;
3100	uint8_t pbCurPages = (uint8_t )pvPages;
3101	for (PPGMREGMMIO2RANGE pCur = pNew; pCur; pCur = pCur->pNextR3)
3102	{
3103	pCur->pvR3 = pbCurPages;
3104	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3105	pCur->pvR0 = pvPagesR0 + (iSrcPage << PAGE_SHIFT);
3106	#endif
3107	pCur->RamRange.pvR3 = pbCurPages;
3108
3109	uint32_t iDstPage = pCur->RamRange.cb >> X86_PAGE_SHIFT;
3110	while (iDstPage-- > 0)
3111	{
3112	PGM_PAGE_INIT(&pNew->RamRange.aPages[iDstPage],
3113	paPages[iDstPage + iSrcPage].Phys,
3114	PGM_MMIO2_PAGEID_MAKE(idMmio2, iDstPage),
3115	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
3116	}
3117
3118	/* advance. */
3119	iSrcPage += pCur->RamRange.cb >> X86_PAGE_SHIFT;
3120	pbCurPages += pCur->RamRange.cb;
3121	}
3122
3123	RTMemTmpFree(paPages);
3124
3125	/*
3126	* Update the page count stats, link the registration and we're done.
3127	*/
3128	pVM->pgm.s.cAllPages += cPages;
3129	pVM->pgm.s.cPrivatePages += cPages;
3130
3131	pgmR3PhysMmio2Link(pVM, pNew);
3132
3133	*ppv = pvPages;
3134	return VINF_SUCCESS;
3135	}
3136
3137	SUPR3PageFreeEx(pvPages, cPages);
3138	}
3139	}
3140	RTMemTmpFree(paPages);
3141	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
3142	}
3143	if (pDevIns->iInstance > 0)
3144	MMR3HeapFree((void *)pszDesc);
3145	return rc;
3146	}
3147
3148
3149	/**
3150	* Deregisters and frees an MMIO2 region.
3151	*
3152	* Any physical access handlers registered for the region must be deregistered
3153	* before calling this function.
3154	*
3155	* @returns VBox status code.
3156	* @param pVM The cross context VM structure.
3157	* @param pDevIns The device instance owning the region.
3158	* @param hMmio2 The MMIO2 handle to deregister, or NIL if all
3159	* regions for the given device is to be deregistered.
3160	*/
3161	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3162	{
3163	/*
3164	* Validate input.
3165	*/
3166	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3167	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3168
3169	/*
3170	* The loop here scanning all registrations will make sure that multi-chunk ranges
3171	* get properly deregistered, though it's original purpose was the wildcard iRegion.
3172	*/
3173	PGM_LOCK_VOID(pVM);
3174	int rc = VINF_SUCCESS;
3175	unsigned cFound = 0;
3176	PPGMREGMMIO2RANGE pPrev = NULL;
3177	PPGMREGMMIO2RANGE pCur = pVM->pgm.s.pRegMmioRangesR3;
3178	while (pCur)
3179	{
3180	uint32_t const fFlags = pCur->fFlags;
3181	if ( pCur->pDevInsR3 == pDevIns
3182	&& ( hMmio2 == NIL_PGMMMIO2HANDLE
3183	\|\| pCur->idMmio2 == hMmio2))
3184	{
3185	cFound++;
3186
3187	/*
3188	* Unmap it if it's mapped.
3189	*/
3190	if (fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3191	{
3192	int rc2 = PGMR3PhysMmio2Unmap(pVM, pCur->pDevInsR3, pCur->idMmio2, pCur->RamRange.GCPhys);
3193	AssertRC(rc2);
3194	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3195	rc = rc2;
3196	}
3197
3198	/*
3199	* Unlink it
3200	*/
3201	PPGMREGMMIO2RANGE pNext = pCur->pNextR3;
3202	if (pPrev)
3203	pPrev->pNextR3 = pNext;
3204	else
3205	pVM->pgm.s.pRegMmioRangesR3 = pNext;
3206	pCur->pNextR3 = NULL;
3207
3208	uint8_t idMmio2 = pCur->idMmio2;
3209	Assert(idMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3));
3210	if (idMmio2 <= RT_ELEMENTS(pVM->pgm.s.apMmio2RangesR3))
3211	{
3212	Assert(pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] == pCur);
3213	pVM->pgm.s.apMmio2RangesR3[idMmio2 - 1] = NULL;
3214	pVM->pgm.s.apMmio2RangesR0[idMmio2 - 1] = NIL_RTR0PTR;
3215	}
3216
3217	/*
3218	* Free the memory.
3219	*/
3220	uint32_t const cPages = pCur->cbReal >> PAGE_SHIFT;
3221	#ifdef VBOX_WITH_PGM_NEM_MODE
3222	if (!pVM->pgm.s.fNemMode)
3223	#endif
3224	{
3225	int rc2 = SUPR3PageFreeEx(pCur->pvR3, cPages);
3226	AssertRC(rc2);
3227	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3228	rc = rc2;
3229
3230	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
3231	AssertRC(rc2);
3232	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3233	rc = rc2;
3234	}
3235	#ifdef VBOX_WITH_PGM_NEM_MODE
3236	else
3237	{
3238	int rc2 = SUPR3PageFree(pCur->pvR3, cPages);
3239	AssertRC(rc2);
3240	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3241	rc = rc2;
3242	}
3243	#endif
3244
3245	if (pCur->pPhysHandlerR3)
3246	{
3247	pgmHandlerPhysicalExDestroy(pVM, pCur->pPhysHandlerR3);
3248	pCur->pPhysHandlerR3 = NULL;
3249	}
3250
3251	/* we're leaking hyper memory here if done at runtime. */
3252	#ifdef VBOX_STRICT
3253	VMSTATE const enmState = VMR3GetState(pVM);
3254	AssertMsg( enmState == VMSTATE_POWERING_OFF
3255	\|\| enmState == VMSTATE_POWERING_OFF_LS
3256	\|\| enmState == VMSTATE_OFF
3257	\|\| enmState == VMSTATE_OFF_LS
3258	\|\| enmState == VMSTATE_DESTROYING
3259	\|\| enmState == VMSTATE_TERMINATED
3260	\|\| enmState == VMSTATE_CREATING
3261	, ("%s\n", VMR3GetStateName(enmState)));
3262	#endif
3263
3264	if (pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING)
3265	{
3266	const size_t cbRange = RT_UOFFSETOF_DYN(PGMREGMMIO2RANGE, RamRange.aPages[cPages]);
3267	size_t const cChunkPages = RT_ALIGN_Z(cbRange, PAGE_SIZE) >> PAGE_SHIFT;
3268	SUPR3PageFreeEx(pCur, cChunkPages);
3269	}
3270	/*else
3271	{
3272	rc = MMHyperFree(pVM, pCur); - does not work, see the alloc call.
3273	AssertRCReturn(rc, rc);
3274	} */
3275
3276
3277	/* update page count stats */
3278	pVM->pgm.s.cAllPages -= cPages;
3279	pVM->pgm.s.cPrivatePages -= cPages;
3280
3281	/* next */
3282	pCur = pNext;
3283	if (hMmio2 != NIL_PGMMMIO2HANDLE)
3284	{
3285	if (fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3286	break;
3287	hMmio2++;
3288	Assert(pCur->idMmio2 == hMmio2);
3289	Assert(pCur->pDevInsR3 == pDevIns);
3290	Assert(!(pCur->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK));
3291	}
3292	}
3293	else
3294	{
3295	pPrev = pCur;
3296	pCur = pCur->pNextR3;
3297	}
3298	}
3299	pgmPhysInvalidatePageMapTLB(pVM);
3300	PGM_UNLOCK(pVM);
3301	return !cFound && hMmio2 != NIL_PGMMMIO2HANDLE ? VERR_NOT_FOUND : rc;
3302	}
3303
3304
3305	/**
3306	* Maps a MMIO2 region.
3307	*
3308	* This is typically done when a guest / the bios / state loading changes the
3309	* PCI config. The replacing of base memory has the same restrictions as during
3310	* registration, of course.
3311	*
3312	* @returns VBox status code.
3313	*
3314	* @param pVM The cross context VM structure.
3315	* @param pDevIns The device instance owning the region.
3316	* @param hMmio2 The handle of the region to map.
3317	* @param GCPhys The guest-physical address to be remapped.
3318	*/
3319	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys)
3320	{
3321	/*
3322	* Validate input.
3323	*
3324	* Note! It's safe to walk the MMIO/MMIO2 list since registrations only
3325	* happens during VM construction.
3326	*/
3327	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3328	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3329	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
3330	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3331	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3332	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3333
3334	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3335	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3336	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3337
3338	PPGMREGMMIO2RANGE pLastMmio = pFirstMmio;
3339	RTGCPHYS cbRange = 0;
3340	for (;;)
3341	{
3342	AssertReturn(!(pLastMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED), VERR_WRONG_ORDER);
3343	Assert(pLastMmio->RamRange.GCPhys == NIL_RTGCPHYS);
3344	Assert(pLastMmio->RamRange.GCPhysLast == NIL_RTGCPHYS);
3345	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3346	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3347	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3348	cbRange += pLastMmio->RamRange.cb;
3349	if (pLastMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3350	break;
3351	pLastMmio = pLastMmio->pNextR3;
3352	}
3353
3354	RTGCPHYS GCPhysLast = GCPhys + cbRange - 1;
3355	AssertLogRelReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3356
3357	/*
3358	* Find our location in the ram range list, checking for restriction
3359	* we don't bother implementing yet (partially overlapping, multiple
3360	* ram ranges).
3361	*/
3362	PGM_LOCK_VOID(pVM);
3363
3364	AssertReturnStmt(!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED), PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3365
3366	bool fRamExists = false;
3367	PPGMRAMRANGE pRamPrev = NULL;
3368	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3369	while (pRam && GCPhysLast >= pRam->GCPhys)
3370	{
3371	if ( GCPhys <= pRam->GCPhysLast
3372	&& GCPhysLast >= pRam->GCPhys)
3373	{
3374	/* Completely within? */
3375	AssertLogRelMsgReturnStmt( GCPhys >= pRam->GCPhys
3376	&& GCPhysLast <= pRam->GCPhysLast,
3377	("%RGp-%RGp (MMIOEx/%s) falls partly outside %RGp-%RGp (%s)\n",
3378	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc,
3379	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
3380	PGM_UNLOCK(pVM),
3381	VERR_PGM_RAM_CONFLICT);
3382
3383	/* Check that all the pages are RAM pages. */
3384	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3385	uint32_t cPagesLeft = cbRange >> PAGE_SHIFT;
3386	while (cPagesLeft-- > 0)
3387	{
3388	AssertLogRelMsgReturnStmt(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
3389	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
3390	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc),
3391	PGM_UNLOCK(pVM),
3392	VERR_PGM_RAM_CONFLICT);
3393	pPage++;
3394	}
3395
3396	/* There can only be one MMIO/MMIO2 chunk matching here! */
3397	AssertLogRelMsgReturnStmt(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK,
3398	("%RGp-%RGp (MMIOEx/%s, flags %#X) consists of multiple chunks whereas the RAM somehow doesn't!\n",
3399	GCPhys, GCPhysLast, pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3400	PGM_UNLOCK(pVM),
3401	VERR_PGM_PHYS_MMIO_EX_IPE);
3402
3403	fRamExists = true;
3404	break;
3405	}
3406
3407	/* next */
3408	pRamPrev = pRam;
3409	pRam = pRam->pNextR3;
3410	}
3411	Log(("PGMR3PhysMmio2Map: %RGp-%RGp fRamExists=%RTbool %s\n", GCPhys, GCPhysLast, fRamExists, pFirstMmio->RamRange.pszDesc));
3412
3413
3414	/*
3415	* Make the changes.
3416	*/
3417	RTGCPHYS GCPhysCur = GCPhys;
3418	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3419	{
3420	pCurMmio->RamRange.GCPhys = GCPhysCur;
3421	pCurMmio->RamRange.GCPhysLast = GCPhysCur + pCurMmio->RamRange.cb - 1;
3422	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3423	{
3424	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3425	break;
3426	}
3427	GCPhysCur += pCurMmio->RamRange.cb;
3428	}
3429
3430	if (fRamExists)
3431	{
3432	/*
3433	* Make all the pages in the range MMIO/ZERO pages, freeing any
3434	* RAM pages currently mapped here. This might not be 100% correct
3435	* for PCI memory, but we're doing the same thing for MMIO2 pages.
3436	*
3437	* We replace these MMIO/ZERO pages with real pages in the MMIO2 case.
3438	*/
3439	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK); /* Only one chunk */
3440	Assert(pFirstMmio->pvR3 == pFirstMmio->RamRange.pvR3);
3441	Assert(pFirstMmio->RamRange.pvR3 != NULL);
3442
3443	#ifdef VBOX_WITH_PGM_NEM_MODE
3444	/* We cannot mix MMIO2 into a RAM range in simplified memory mode because pRam->pvR3 can't point
3445	both at the RAM and MMIO2, so we won't ever write & read from the actual MMIO2 memory if we try. */
3446	AssertLogRelMsgReturn(!pVM->pgm.s.fNemMode, ("%s at %RGp-%RGp\n", pFirstMmio->RamRange.pszDesc, GCPhys, GCPhysLast),
3447	VERR_PGM_NOT_SUPPORTED_FOR_NEM_MODE);
3448	#endif
3449
3450	int rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, pFirstMmio->RamRange.pvR3);
3451	AssertRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3452
3453	/* Replace the pages, freeing all present RAM pages. */
3454	PPGMPAGE pPageSrc = &pFirstMmio->RamRange.aPages[0];
3455	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3456	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3457	while (cPagesLeft-- > 0)
3458	{
3459	Assert(PGM_PAGE_IS_MMIO(pPageDst));
3460
3461	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
3462	uint32_t const idPage = PGM_PAGE_GET_PAGEID(pPageSrc);
3463	PGM_PAGE_SET_PAGEID(pVM, pPageDst, idPage);
3464	PGM_PAGE_SET_HCPHYS(pVM, pPageDst, HCPhys);
3465	PGM_PAGE_SET_TYPE(pVM, pPageDst, PGMPAGETYPE_MMIO2);
3466	PGM_PAGE_SET_STATE(pVM, pPageDst, PGM_PAGE_STATE_ALLOCATED);
3467	PGM_PAGE_SET_PDE_TYPE(pVM, pPageDst, PGM_PAGE_PDE_TYPE_DONTCARE);
3468	PGM_PAGE_SET_PTE_INDEX(pVM, pPageDst, 0);
3469	PGM_PAGE_SET_TRACKING(pVM, pPageDst, 0);
3470	/* NEM state is set by pgmR3PhysFreePageRange. */
3471
3472	pVM->pgm.s.cZeroPages--;
3473	GCPhys += PAGE_SIZE;
3474	pPageSrc++;
3475	pPageDst++;
3476	}
3477
3478	/* Flush physical page map TLB. */
3479	pgmPhysInvalidatePageMapTLB(pVM);
3480
3481	/* Force a PGM pool flush as guest ram references have been changed. */
3482	/** @todo not entirely SMP safe; assuming for now the guest takes care of
3483	* this internally (not touch mapped mmio while changing the mapping). */
3484	PVMCPU pVCpu = VMMGetCpu(pVM);
3485	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3486	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3487	}
3488	else
3489	{
3490	/*
3491	* No RAM range, insert the ones prepared during registration.
3492	*/
3493	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3494	{
3495	#ifdef VBOX_WITH_NATIVE_NEM
3496	/* Tell NEM and get the new NEM state for the pages. */
3497	uint8_t u2NemState = 0;
3498	if (VM_IS_NEM_ENABLED(pVM))
3499	{
3500	int rc = NEMR3NotifyPhysMmioExMapEarly(pVM, pCurMmio->RamRange.GCPhys,
3501	pCurMmio->RamRange.GCPhysLast - pCurMmio->RamRange.GCPhys + 1,
3502	NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2
3503	\| (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
3504	? NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES : 0),
3505	NULL /pvRam/, pCurMmio->RamRange.pvR3,
3506	&u2NemState, &pCurMmio->RamRange.uNemRange);
3507	AssertLogRelRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
3508	}
3509	#endif
3510
3511	/* Clear the tracking data of pages we're going to reactivate. */
3512	PPGMPAGE pPageSrc = &pCurMmio->RamRange.aPages[0];
3513	uint32_t cPagesLeft = pCurMmio->RamRange.cb >> PAGE_SHIFT;
3514	while (cPagesLeft-- > 0)
3515	{
3516	PGM_PAGE_SET_TRACKING(pVM, pPageSrc, 0);
3517	PGM_PAGE_SET_PTE_INDEX(pVM, pPageSrc, 0);
3518	#ifdef VBOX_WITH_NATIVE_NEM
3519	PGM_PAGE_SET_NEM_STATE(pPageSrc, u2NemState);
3520	#endif
3521	pPageSrc++;
3522	}
3523
3524	/* link in the ram range */
3525	pgmR3PhysLinkRamRange(pVM, &pCurMmio->RamRange, pRamPrev);
3526
3527	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3528	{
3529	Assert(pCurMmio->RamRange.GCPhysLast == GCPhysLast);
3530	break;
3531	}
3532	pRamPrev = &pCurMmio->RamRange;
3533	}
3534	}
3535
3536	/*
3537	* If the range have dirty page monitoring enabled, enable that.
3538	*
3539	* We ignore failures here for now because if we fail, the whole mapping
3540	* will have to be reversed and we'll end up with nothing at all on the
3541	* screen and a grumpy guest, whereas if we just go on, we'll only have
3542	* visual distortions to gripe about. There will be something in the
3543	* release log.
3544	*/
3545	if ( pFirstMmio->pPhysHandlerR3
3546	&& (pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3547	pgmR3PhysMmio2EnableDirtyPageTracing(pVM, pFirstMmio);
3548
3549	/*
3550	* We're good, set the flags and invalid the mapping TLB.
3551	*/
3552	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3553	{
3554	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_MAPPED;
3555	if (fRamExists)
3556	pCurMmio->fFlags \|= PGMREGMMIO2RANGE_F_OVERLAPPING;
3557	else
3558	pCurMmio->fFlags &= ~PGMREGMMIO2RANGE_F_OVERLAPPING;
3559	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3560	break;
3561	}
3562	pgmPhysInvalidatePageMapTLB(pVM);
3563
3564	#ifdef VBOX_WITH_NATIVE_NEM
3565	/*
3566	* Late NEM notification.
3567	*/
3568	if (VM_IS_NEM_ENABLED(pVM))
3569	{
3570	int rc;
3571	uint32_t fNemFlags = NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2;
3572	if (pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES)
3573	fNemFlags \|= NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES;
3574	if (fRamExists)
3575	rc = NEMR3NotifyPhysMmioExMapLate(pVM, GCPhys, GCPhysLast - GCPhys + 1, fNemFlags \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
3576	pRam->pvR3 ? (uint8_t *)pRam->pvR3 + GCPhys - pRam->GCPhys : NULL, pFirstMmio->pvR3,
3577	NULL /puNemRange/);
3578	else
3579	{
3580	rc = VINF_SUCCESS;
3581	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3582	{
3583	rc = NEMR3NotifyPhysMmioExMapLate(pVM, pCurMmio->RamRange.GCPhys, pCurMmio->RamRange.cb, fNemFlags,
3584	NULL, pCurMmio->RamRange.pvR3, &pCurMmio->RamRange.uNemRange);
3585	if ((pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK) \|\| RT_FAILURE(rc))
3586	break;
3587	}
3588	}
3589	AssertLogRelRCReturnStmt(rc, PGMR3PhysMmio2Unmap(pVM, pDevIns, hMmio2, GCPhys); PGM_UNLOCK(pVM), rc);
3590	}
3591	#endif
3592
3593	PGM_UNLOCK(pVM);
3594
3595	return VINF_SUCCESS;
3596	}
3597
3598
3599	/**
3600	* Unmaps an MMIO2 region.
3601	*
3602	* This is typically done when a guest / the bios / state loading changes the
3603	* PCI config. The replacing of base memory has the same restrictions as during
3604	* registration, of course.
3605	*/
3606	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys)
3607	{
3608	/*
3609	* Validate input
3610	*/
3611	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3612	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3613	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3614	if (GCPhys != NIL_RTGCPHYS)
3615	{
3616	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
3617	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
3618	}
3619
3620	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3621	AssertReturn(pFirstMmio, VERR_NOT_FOUND);
3622	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3623
3624	int rc = PGM_LOCK(pVM);
3625	AssertRCReturn(rc, rc);
3626
3627	PPGMREGMMIO2RANGE pLastMmio = pFirstMmio;
3628	RTGCPHYS cbRange = 0;
3629	for (;;)
3630	{
3631	AssertReturnStmt(pLastMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED, PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3632	AssertReturnStmt(pLastMmio->RamRange.GCPhys == GCPhys + cbRange \|\| GCPhys == NIL_RTGCPHYS, PGM_UNLOCK(pVM), VERR_INVALID_PARAMETER);
3633	Assert(pLastMmio->pDevInsR3 == pFirstMmio->pDevInsR3);
3634	Assert(pLastMmio->iSubDev == pFirstMmio->iSubDev);
3635	Assert(pLastMmio->iRegion == pFirstMmio->iRegion);
3636	cbRange += pLastMmio->RamRange.cb;
3637	if (pLastMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3638	break;
3639	pLastMmio = pLastMmio->pNextR3;
3640	}
3641
3642	Log(("PGMR3PhysMmio2Unmap: %RGp-%RGp %s\n",
3643	pFirstMmio->RamRange.GCPhys, pLastMmio->RamRange.GCPhysLast, pFirstMmio->RamRange.pszDesc));
3644
3645	uint16_t const fOldFlags = pFirstMmio->fFlags;
3646	AssertReturnStmt(fOldFlags & PGMREGMMIO2RANGE_F_MAPPED, PGM_UNLOCK(pVM), VERR_WRONG_ORDER);
3647
3648	/*
3649	* If monitoring dirty pages, we must deregister the handlers first.
3650	*/
3651	if ( pFirstMmio->pPhysHandlerR3
3652	&& (fOldFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3653	pgmR3PhysMmio2DisableDirtyPageTracing(pVM, pFirstMmio);
3654
3655	/*
3656	* Unmap it.
3657	*/
3658	int rcRet = VINF_SUCCESS;
3659	#ifdef VBOX_WITH_NATIVE_NEM
3660	uint32_t const fNemFlags = NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2
3661	\| (fOldFlags & PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
3662	? NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES : 0);
3663	#endif
3664	if (fOldFlags & PGMREGMMIO2RANGE_F_OVERLAPPING)
3665	{
3666	/*
3667	* We've replaced RAM, replace with zero pages.
3668	*
3669	* Note! This is where we might differ a little from a real system, because
3670	* it's likely to just show the RAM pages as they were before the
3671	* MMIO/MMIO2 region was mapped here.
3672	*/
3673	/* Only one chunk allowed when overlapping! */
3674	Assert(fOldFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK);
3675
3676	/* Restore the RAM pages we've replaced. */
3677	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3678	while (pRam->GCPhys > pFirstMmio->RamRange.GCPhysLast)
3679	pRam = pRam->pNextR3;
3680
3681	PPGMPAGE pPageDst = &pRam->aPages[(pFirstMmio->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3682	uint32_t cPagesLeft = pFirstMmio->RamRange.cb >> PAGE_SHIFT;
3683	pVM->pgm.s.cZeroPages += cPagesLeft; /** @todo not correct for NEM mode */
3684
3685	#ifdef VBOX_WITH_NATIVE_NEM
3686	if (VM_IS_NEM_ENABLED(pVM)) /* Notify NEM. Note! we cannot be here in simple memory mode, see mapping function. */
3687	{
3688	uint8_t u2State = UINT8_MAX;
3689	rc = NEMR3NotifyPhysMmioExUnmap(pVM, pFirstMmio->RamRange.GCPhys, pFirstMmio->RamRange.cb,
3690	fNemFlags \| NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE,
3691	pRam->pvR3
3692	? (uint8_t *)pRam->pvR3 + pFirstMmio->RamRange.GCPhys - pRam->GCPhys : NULL,
3693	pFirstMmio->pvR3, &u2State, &pRam->uNemRange);
3694	AssertRCStmt(rc, rcRet = rc);
3695	if (u2State != UINT8_MAX)
3696	pgmPhysSetNemStateForPages(pPageDst, cPagesLeft, u2State);
3697	}
3698	#endif
3699
3700	while (cPagesLeft-- > 0)
3701	{
3702	PGM_PAGE_INIT_ZERO(pPageDst, pVM, PGMPAGETYPE_RAM);
3703	pPageDst++;
3704	}
3705
3706	/* Flush physical page map TLB. */
3707	pgmPhysInvalidatePageMapTLB(pVM);
3708
3709	/* Update range state. */
3710	pFirstMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3711	pFirstMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3712	pFirstMmio->fFlags &= ~(PGMREGMMIO2RANGE_F_OVERLAPPING \| PGMREGMMIO2RANGE_F_MAPPED);
3713	}
3714	else
3715	{
3716	/*
3717	* Unlink the chunks related to the MMIO/MMIO2 region.
3718	*/
3719	for (PPGMREGMMIO2RANGE pCurMmio = pFirstMmio; ; pCurMmio = pCurMmio->pNextR3)
3720	{
3721	#ifdef VBOX_WITH_NATIVE_NEM
3722	if (VM_IS_NEM_ENABLED(pVM)) /* Notify NEM. */
3723	{
3724	uint8_t u2State = UINT8_MAX;
3725	rc = NEMR3NotifyPhysMmioExUnmap(pVM, pCurMmio->RamRange.GCPhys, pCurMmio->RamRange.cb, fNemFlags,
3726	NULL, pCurMmio->pvR3, &u2State, &pCurMmio->RamRange.uNemRange);
3727	AssertRCStmt(rc, rcRet = rc);
3728	if (u2State != UINT8_MAX)
3729	pgmPhysSetNemStateForPages(pCurMmio->RamRange.aPages, pCurMmio->RamRange.cb >> PAGE_SHIFT, u2State);
3730	}
3731	#endif
3732	pgmR3PhysUnlinkRamRange(pVM, &pCurMmio->RamRange);
3733	pCurMmio->RamRange.GCPhys = NIL_RTGCPHYS;
3734	pCurMmio->RamRange.GCPhysLast = NIL_RTGCPHYS;
3735	pCurMmio->fFlags &= ~(PGMREGMMIO2RANGE_F_OVERLAPPING \| PGMREGMMIO2RANGE_F_MAPPED);
3736	if (pCurMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3737	break;
3738	}
3739	}
3740
3741	/* Force a PGM pool flush as guest ram references have been changed. */
3742	/** @todo not entirely SMP safe; assuming for now the guest takes care
3743	* of this internally (not touch mapped mmio while changing the
3744	* mapping). */
3745	PVMCPU pVCpu = VMMGetCpu(pVM);
3746	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3747	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3748
3749	pgmPhysInvalidatePageMapTLB(pVM);
3750	pgmPhysInvalidRamRangeTlbs(pVM);
3751
3752	PGM_UNLOCK(pVM);
3753	return rcRet;
3754	}
3755
3756
3757	/**
3758	* Reduces the mapping size of a MMIO2 region.
3759	*
3760	* This is mainly for dealing with old saved states after changing the default
3761	* size of a mapping region. See PGMDevHlpMMIOExReduce and
3762	* PDMPCIDEV::pfnRegionLoadChangeHookR3.
3763	*
3764	* The region must not currently be mapped when making this call. The VM state
3765	* must be state restore or VM construction.
3766	*
3767	* @returns VBox status code.
3768	* @param pVM The cross context VM structure.
3769	* @param pDevIns The device instance owning the region.
3770	* @param hMmio2 The handle of the region to reduce.
3771	* @param cbRegion The new mapping size.
3772	*/
3773	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion)
3774	{
3775	/*
3776	* Validate input
3777	*/
3778	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3779	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
3780	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
3781	AssertReturn(cbRegion >= X86_PAGE_SIZE, VERR_INVALID_PARAMETER);
3782	AssertReturn(!(cbRegion & X86_PAGE_OFFSET_MASK), VERR_UNSUPPORTED_ALIGNMENT);
3783	VMSTATE enmVmState = VMR3GetState(pVM);
3784	AssertLogRelMsgReturn( enmVmState == VMSTATE_CREATING
3785	\|\| enmVmState == VMSTATE_LOADING,
3786	("enmVmState=%d (%s)\n", enmVmState, VMR3GetStateName(enmVmState)),
3787	VERR_VM_INVALID_VM_STATE);
3788
3789	int rc = PGM_LOCK(pVM);
3790	AssertRCReturn(rc, rc);
3791
3792	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3793	if (pFirstMmio)
3794	{
3795	Assert(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK);
3796	if (!(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED))
3797	{
3798	/*
3799	* NOTE! Current implementation does not support multiple ranges.
3800	* Implement when there is a real world need and thus a testcase.
3801	*/
3802	AssertLogRelMsgStmt(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK,
3803	("%s: %#x\n", pFirstMmio->RamRange.pszDesc, pFirstMmio->fFlags),
3804	rc = VERR_NOT_SUPPORTED);
3805	if (RT_SUCCESS(rc))
3806	{
3807	/*
3808	* Make the change.
3809	*/
3810	Log(("PGMR3PhysMmio2Reduce: %s changes from %RGp bytes (%RGp) to %RGp bytes.\n",
3811	pFirstMmio->RamRange.pszDesc, pFirstMmio->RamRange.cb, pFirstMmio->cbReal, cbRegion));
3812
3813	AssertLogRelMsgStmt(cbRegion <= pFirstMmio->cbReal,
3814	("%s: cbRegion=%#RGp cbReal=%#RGp\n", pFirstMmio->RamRange.pszDesc, cbRegion, pFirstMmio->cbReal),
3815	rc = VERR_OUT_OF_RANGE);
3816	if (RT_SUCCESS(rc))
3817	{
3818	pFirstMmio->RamRange.cb = cbRegion;
3819	}
3820	}
3821	}
3822	else
3823	rc = VERR_WRONG_ORDER;
3824	}
3825	else
3826	rc = VERR_NOT_FOUND;
3827
3828	PGM_UNLOCK(pVM);
3829	return rc;
3830	}
3831
3832
3833	/**
3834	* Validates @a hMmio2, making sure it belongs to @a pDevIns.
3835	*
3836	* @returns VBox status code.
3837	* @param pVM The cross context VM structure.
3838	* @param pDevIns The device which allegedly owns @a hMmio2.
3839	* @param hMmio2 The handle to validate.
3840	*/
3841	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3842	{
3843	/*
3844	* Validate input
3845	*/
3846	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
3847	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
3848
3849	/*
3850	* Just do this the simple way. No need for locking as this is only taken at
3851	*/
3852	PGM_LOCK_VOID(pVM);
3853	PPGMREGMMIO2RANGE pFirstMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3854	PGM_UNLOCK(pVM);
3855	AssertReturn(pFirstMmio, VERR_INVALID_HANDLE);
3856	AssertReturn(pFirstMmio->fFlags & PGMREGMMIO2RANGE_F_FIRST_CHUNK, VERR_INVALID_HANDLE);
3857	return VINF_SUCCESS;
3858	}
3859
3860
3861	/**
3862	* Gets the mapping address of an MMIO2 region.
3863	*
3864	* @returns Mapping address, NIL_RTGCPHYS if not mapped or invalid handle.
3865	*
3866	* @param pVM The cross context VM structure.
3867	* @param pDevIns The device owning the MMIO2 handle.
3868	* @param hMmio2 The region handle.
3869	*/
3870	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2)
3871	{
3872	AssertPtrReturn(pDevIns, NIL_RTGCPHYS);
3873
3874	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3875	AssertReturn(pFirstRegMmio, NIL_RTGCPHYS);
3876
3877	if (pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED)
3878	return pFirstRegMmio->RamRange.GCPhys;
3879	return NIL_RTGCPHYS;
3880	}
3881
3882
3883	/**
3884	* Worker for PGMR3PhysMmio2QueryAndResetDirtyBitmap.
3885	*
3886	* Called holding the PGM lock.
3887	*/
3888	static int pgmR3PhysMmio2QueryAndResetDirtyBitmapLocked(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
3889	void *pvBitmap, size_t cbBitmap)
3890	{
3891	/*
3892	* Continue validation.
3893	*/
3894	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
3895	AssertReturn(pFirstRegMmio, VERR_INVALID_HANDLE);
3896	AssertReturn( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
3897	== (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK),
3898	VERR_INVALID_FUNCTION);
3899	AssertReturn(pDevIns == pFirstRegMmio->pDevInsR3, VERR_NOT_OWNER);
3900
3901	RTGCPHYS cbTotal = 0;
3902	uint16_t fTotalDirty = 0;
3903	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio;;)
3904	{
3905	cbTotal += pCur->RamRange.cb; /* Not using cbReal here, because NEM is not in on the creating, only the mapping. */
3906	fTotalDirty \|= pCur->fFlags;
3907	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3908	break;
3909	pCur = pCur->pNextR3;
3910	AssertPtrReturn(pCur, VERR_INTERNAL_ERROR_5);
3911	AssertReturn( (pCur->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
3912	== PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES,
3913	VERR_INTERNAL_ERROR_4);
3914	}
3915	size_t const cbTotalBitmap = RT_ALIGN_T(cbTotal, PAGE_SIZE * 64, RTGCPHYS) / PAGE_SIZE / 8;
3916
3917	if (cbBitmap)
3918	{
3919	AssertPtrReturn(pvBitmap, VERR_INVALID_POINTER);
3920	AssertReturn(RT_ALIGN_P(pvBitmap, sizeof(uint64_t)) == pvBitmap, VERR_INVALID_POINTER);
3921	AssertReturn(cbBitmap == cbTotalBitmap, VERR_INVALID_PARAMETER);
3922	}
3923
3924	/*
3925	* Do the work.
3926	*/
3927	int rc = VINF_SUCCESS;
3928	if (pvBitmap)
3929	{
3930	#ifdef VBOX_WITH_PGM_NEM_MODE
3931	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
3932	{
3933	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
3934	uint8_t pbBitmap = (uint8_t )pvBitmap;
3935	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3936	{
3937	size_t const cbBitmapChunk = pCur->RamRange.cb / PAGE_SIZE / 8;
3938	Assert((RTGCPHYS)cbBitmapChunk * PAGE_SIZE * 8 == pCur->RamRange.cb);
3939	int rc2 = NEMR3PhysMmio2QueryAndResetDirtyBitmap(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb,
3940	pCur->RamRange.uNemRange, pbBitmap, cbBitmapChunk);
3941	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3942	rc = rc2;
3943	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3944	break;
3945	pbBitmap += pCur->RamRange.cb / PAGE_SIZE / 8;
3946	}
3947	}
3948	else
3949	#endif
3950	if (fTotalDirty & PGMREGMMIO2RANGE_F_IS_DIRTY)
3951	{
3952	if ( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3953	== (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
3954	{
3955	/*
3956	* Reset each chunk, gathering dirty bits.
3957	*/
3958	RT_BZERO(pvBitmap, cbBitmap); /* simpler for now. */
3959	uint32_t iPageNo = 0;
3960	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3961	{
3962	if (pCur->fFlags & PGMREGMMIO2RANGE_F_IS_DIRTY)
3963	{
3964	int rc2 = pgmHandlerPhysicalResetMmio2WithBitmap(pVM, pCur->RamRange.GCPhys, pvBitmap, iPageNo);
3965	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3966	rc = rc2;
3967	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
3968	}
3969	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3970	break;
3971	iPageNo += pCur->RamRange.cb >> PAGE_SHIFT;
3972	}
3973	}
3974	else
3975	{
3976	/*
3977	* If not mapped or tracking is disabled, we return the
3978	* PGMREGMMIO2RANGE_F_IS_DIRTY status for all pages. We cannot
3979	* get more accurate data than that after unmapping or disabling.
3980	*/
3981	RT_BZERO(pvBitmap, cbBitmap);
3982	uint32_t iPageNo = 0;
3983	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
3984	{
3985	if (pCur->fFlags & PGMREGMMIO2RANGE_F_IS_DIRTY)
3986	{
3987	ASMBitSetRange(pvBitmap, iPageNo, iPageNo + (pCur->RamRange.cb >> PAGE_SHIFT));
3988	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
3989	}
3990	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
3991	break;
3992	iPageNo += pCur->RamRange.cb >> PAGE_SHIFT;
3993	}
3994	}
3995	}
3996	/*
3997	* No dirty chunks.
3998	*/
3999	else
4000	RT_BZERO(pvBitmap, cbBitmap);
4001	}
4002	/*
4003	* No bitmap. Reset the region if tracking is currently enabled.
4004	*/
4005	else if ( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4006	== (PGMREGMMIO2RANGE_F_MAPPED \| PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4007	{
4008	#ifdef VBOX_WITH_PGM_NEM_MODE
4009	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
4010	{
4011	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
4012	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
4013	{
4014	int rc2 = NEMR3PhysMmio2QueryAndResetDirtyBitmap(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb,
4015	pCur->RamRange.uNemRange, NULL, 0);
4016	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4017	rc = rc2;
4018	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4019	break;
4020	}
4021	}
4022	else
4023	#endif
4024	{
4025	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio; pCur; pCur = pCur->pNextR3)
4026	{
4027	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_IS_DIRTY;
4028	int rc2 = PGMHandlerPhysicalReset(pVM, pCur->RamRange.GCPhys);
4029	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4030	rc = rc2;
4031	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4032	break;
4033	}
4034	}
4035	}
4036
4037	return rc;
4038	}
4039
4040
4041	/**
4042	* Queries the dirty page bitmap and resets the monitoring.
4043	*
4044	* The PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag must be specified when
4045	* creating the range for this to work.
4046	*
4047	* @returns VBox status code.
4048	* @retval VERR_INVALID_FUNCTION if not created using
4049	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES.
4050	* @param pVM The cross context VM structure.
4051	* @param pDevIns The device owning the MMIO2 handle.
4052	* @param hMmio2 The region handle.
4053	* @param pvBitmap The output bitmap. Must be 8-byte aligned. Ignored
4054	* when @a cbBitmap is zero.
4055	* @param cbBitmap The size of the bitmap. Must be the size of the whole
4056	* MMIO2 range, rounded up to the nearest 8 bytes.
4057	* When zero only a reset is done.
4058	*/
4059	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
4060	void *pvBitmap, size_t cbBitmap)
4061	{
4062	/*
4063	* Do some basic validation before grapping the PGM lock and continuing.
4064	*/
4065	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
4066	AssertReturn(RT_ALIGN_Z(cbBitmap, sizeof(uint64_t)) == cbBitmap, VERR_INVALID_PARAMETER);
4067	int rc = PGM_LOCK(pVM);
4068	if (RT_SUCCESS(rc))
4069	{
4070	STAM_PROFILE_START(&pVM->pgm.s.StatMmio2QueryAndResetDirtyBitmap, a);
4071	rc = pgmR3PhysMmio2QueryAndResetDirtyBitmapLocked(pVM, pDevIns, hMmio2, pvBitmap, cbBitmap);
4072	STAM_PROFILE_STOP(&pVM->pgm.s.StatMmio2QueryAndResetDirtyBitmap, a);
4073	PGM_UNLOCK(pVM);
4074	}
4075	return rc;
4076	}
4077
4078	/**
4079	* Worker for PGMR3PhysMmio2ControlDirtyPageTracking
4080	*
4081	* Called owning the PGM lock.
4082	*/
4083	static int pgmR3PhysMmio2ControlDirtyPageTrackingLocked(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled)
4084	{
4085	/*
4086	* Continue validation.
4087	*/
4088	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
4089	AssertReturn(pFirstRegMmio, VERR_INVALID_HANDLE);
4090	AssertReturn( (pFirstRegMmio->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
4091	== (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK)
4092	, VERR_INVALID_FUNCTION);
4093	AssertReturn(pDevIns == pFirstRegMmio->pDevInsR3, VERR_NOT_OWNER);
4094
4095	#ifdef VBOX_WITH_PGM_NEM_MODE
4096	/*
4097	* This is a nop if NEM is responsible for doing the tracking, we simply
4098	* leave the tracking on all the time there.
4099	*/
4100	if (pFirstRegMmio->pPhysHandlerR3 == NULL)
4101	{
4102	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_INTERNAL_ERROR_4);
4103	return VINF_SUCCESS;
4104	}
4105	#endif
4106
4107	/*
4108	* Anyting needing doing?
4109	*/
4110	if (fEnabled != RT_BOOL(pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_TRACKING_ENABLED))
4111	{
4112	LogFlowFunc(("fEnabled=%RTbool %s\n", fEnabled, pFirstRegMmio->RamRange.pszDesc));
4113
4114	/*
4115	* Update the PGMREGMMIO2RANGE_F_TRACKING_ENABLED flag.
4116	*/
4117	for (PPGMREGMMIO2RANGE pCur = pFirstRegMmio;;)
4118	{
4119	if (fEnabled)
4120	pCur->fFlags \|= PGMREGMMIO2RANGE_F_TRACKING_ENABLED;
4121	else
4122	pCur->fFlags &= ~PGMREGMMIO2RANGE_F_TRACKING_ENABLED;
4123	if (pCur->fFlags & PGMREGMMIO2RANGE_F_LAST_CHUNK)
4124	break;
4125	pCur = pCur->pNextR3;
4126	AssertPtrReturn(pCur, VERR_INTERNAL_ERROR_5);
4127	AssertReturn( (pCur->fFlags & (PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES \| PGMREGMMIO2RANGE_F_FIRST_CHUNK))
4128	== PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES
4129	, VERR_INTERNAL_ERROR_4);
4130	}
4131
4132	/*
4133	* Enable/disable handlers if currently mapped.
4134	*
4135	* We ignore status codes here as we've already changed the flags and
4136	* returning a failure status now would be confusing. Besides, the two
4137	* functions will continue past failures. As argued in the mapping code,
4138	* it's in the release log.
4139	*/
4140	if (pFirstRegMmio->fFlags & PGMREGMMIO2RANGE_F_MAPPED)
4141	{
4142	if (fEnabled)
4143	pgmR3PhysMmio2EnableDirtyPageTracing(pVM, pFirstRegMmio);
4144	else
4145	pgmR3PhysMmio2DisableDirtyPageTracing(pVM, pFirstRegMmio);
4146	}
4147	}
4148	else
4149	LogFlowFunc(("fEnabled=%RTbool %s - no change\n", fEnabled, pFirstRegMmio->RamRange.pszDesc));
4150
4151	return VINF_SUCCESS;
4152	}
4153
4154
4155	/**
4156	* Controls the dirty page tracking for an MMIO2 range.
4157	*
4158	* @returns VBox status code.
4159	* @param pVM The cross context VM structure.
4160	* @param pDevIns The device owning the MMIO2 memory.
4161	* @param hMmio2 The handle of the region.
4162	* @param fEnabled The new tracking state.
4163	*/
4164	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled)
4165	{
4166	/*
4167	* Do some basic validation before grapping the PGM lock and continuing.
4168	*/
4169	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
4170	int rc = PGM_LOCK(pVM);
4171	if (RT_SUCCESS(rc))
4172	{
4173	rc = pgmR3PhysMmio2ControlDirtyPageTrackingLocked(pVM, pDevIns, hMmio2, fEnabled);
4174	PGM_UNLOCK(pVM);
4175	}
4176	return rc;
4177	}
4178
4179
4180	/**
4181	* Changes the region number of an MMIO2 region.
4182	*
4183	* This is only for dealing with save state issues, nothing else.
4184	*
4185	* @return VBox status code.
4186	*
4187	* @param pVM The cross context VM structure.
4188	* @param pDevIns The device owning the MMIO2 memory.
4189	* @param hMmio2 The handle of the region.
4190	* @param iNewRegion The new region index.
4191	*
4192	* @thread EMT(0)
4193	* @sa @bugref{9359}
4194	*/
4195	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion)
4196	{
4197	/*
4198	* Validate input.
4199	*/
4200	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
4201	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_LOADING, VERR_VM_INVALID_VM_STATE);
4202	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4203	AssertReturn(hMmio2 != NIL_PGMMMIO2HANDLE, VERR_INVALID_HANDLE);
4204	AssertReturn(iNewRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
4205
4206	AssertReturn(pVM->enmVMState == VMSTATE_LOADING, VERR_INVALID_STATE);
4207
4208	int rc = PGM_LOCK(pVM);
4209	AssertRCReturn(rc, rc);
4210
4211	PPGMREGMMIO2RANGE pFirstRegMmio = pgmR3PhysMmio2Find(pVM, pDevIns, UINT32_MAX, UINT32_MAX, hMmio2);
4212	AssertReturnStmt(pFirstRegMmio, PGM_UNLOCK(pVM), VERR_NOT_FOUND);
4213	AssertReturnStmt(pgmR3PhysMmio2Find(pVM, pDevIns, pFirstRegMmio->iSubDev, iNewRegion, NIL_PGMMMIO2HANDLE) == NULL,
4214	PGM_UNLOCK(pVM), VERR_RESOURCE_IN_USE);
4215
4216	/*
4217	* Make the change.
4218	*/
4219	pFirstRegMmio->iRegion = (uint8_t)iNewRegion;
4220
4221	PGM_UNLOCK(pVM);
4222	return VINF_SUCCESS;
4223	}
4224
4225
4226
4227	/*********************************************************************************************************************************
4228	* ROM *
4229	*********************************************************************************************************************************/
4230
4231	/**
4232	* Worker for PGMR3PhysRomRegister.
4233	*
4234	* This is here to simplify lock management, i.e. the caller does all the
4235	* locking and we can simply return without needing to remember to unlock
4236	* anything first.
4237	*
4238	* @returns VBox status code.
4239	* @param pVM The cross context VM structure.
4240	* @param pDevIns The device instance owning the ROM.
4241	* @param GCPhys First physical address in the range.
4242	* Must be page aligned!
4243	* @param cb The size of the range (in bytes).
4244	* Must be page aligned!
4245	* @param pvBinary Pointer to the binary data backing the ROM image.
4246	* @param cbBinary The size of the binary data pvBinary points to.
4247	* This must be less or equal to @a cb.
4248	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
4249	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
4250	* @param pszDesc Pointer to description string. This must not be freed.
4251	*/
4252	static int pgmR3PhysRomRegisterLocked(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4253	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc)
4254	{
4255	/*
4256	* Validate input.
4257	*/
4258	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
4259	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
4260	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
4261	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4262	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4263	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
4264	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
4265	AssertReturn(!(fFlags & ~PGMPHYS_ROM_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
4266	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
4267
4268	const uint32_t cPages = cb >> PAGE_SHIFT;
4269
4270	/*
4271	* Find the ROM location in the ROM list first.
4272	*/
4273	PPGMROMRANGE pRomPrev = NULL;
4274	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
4275	while (pRom && GCPhysLast >= pRom->GCPhys)
4276	{
4277	if ( GCPhys <= pRom->GCPhysLast
4278	&& GCPhysLast >= pRom->GCPhys)
4279	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
4280	GCPhys, GCPhysLast, pszDesc,
4281	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
4282	VERR_PGM_RAM_CONFLICT);
4283	/* next */
4284	pRomPrev = pRom;
4285	pRom = pRom->pNextR3;
4286	}
4287
4288	/*
4289	* Find the RAM location and check for conflicts.
4290	*
4291	* Conflict detection is a bit different than for RAM registration since a
4292	* ROM can be located within a RAM range. So, what we have to check for is
4293	* other memory types (other than RAM that is) and that we don't span more
4294	* than one RAM range (lazy).
4295	*/
4296	bool fRamExists = false;
4297	PPGMRAMRANGE pRamPrev = NULL;
4298	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
4299	while (pRam && GCPhysLast >= pRam->GCPhys)
4300	{
4301	if ( GCPhys <= pRam->GCPhysLast
4302	&& GCPhysLast >= pRam->GCPhys)
4303	{
4304	/* completely within? */
4305	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
4306	&& GCPhysLast <= pRam->GCPhysLast,
4307	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
4308	GCPhys, GCPhysLast, pszDesc,
4309	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
4310	VERR_PGM_RAM_CONFLICT);
4311	fRamExists = true;
4312	break;
4313	}
4314
4315	/* next */
4316	pRamPrev = pRam;
4317	pRam = pRam->pNextR3;
4318	}
4319	if (fRamExists)
4320	{
4321	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
4322	uint32_t cPagesLeft = cPages;
4323	while (cPagesLeft-- > 0)
4324	{
4325	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
4326	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
4327	pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
4328	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
4329	Assert(PGM_PAGE_IS_ZERO(pPage) \|\| PGM_IS_IN_NEM_MODE(pVM));
4330	pPage++;
4331	}
4332	}
4333
4334	/*
4335	* Update the base memory reservation if necessary.
4336	*/
4337	uint32_t cExtraBaseCost = fRamExists ? 0 : cPages;
4338	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4339	cExtraBaseCost += cPages;
4340	if (cExtraBaseCost)
4341	{
4342	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
4343	if (RT_FAILURE(rc))
4344	return rc;
4345	}
4346
4347	#ifdef VBOX_WITH_NATIVE_NEM
4348	/*
4349	* Early NEM notification before we've made any changes or anything.
4350	*/
4351	uint32_t const fNemNotify = (fRamExists ? NEM_NOTIFY_PHYS_ROM_F_REPLACE : 0)
4352	\| (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED ? NEM_NOTIFY_PHYS_ROM_F_SHADOW : 0);
4353	uint8_t u2NemState = UINT8_MAX;
4354	uint32_t uNemRange = 0;
4355	if (VM_IS_NEM_ENABLED(pVM))
4356	{
4357	int rc = NEMR3NotifyPhysRomRegisterEarly(pVM, GCPhys, cPages << PAGE_SHIFT,
4358	fRamExists ? PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhys) : NULL,
4359	fNemNotify, &u2NemState, fRamExists ? &pRam->uNemRange : &uNemRange);
4360	AssertLogRelRCReturn(rc, rc);
4361	}
4362	#endif
4363
4364	/*
4365	* Allocate memory for the virgin copy of the RAM. In simplified memory mode,
4366	* we allocate memory for any ad-hoc RAM range and for shadow pages.
4367	*/
4368	PGMMALLOCATEPAGESREQ pReq = NULL;
4369	#ifdef VBOX_WITH_PGM_NEM_MODE
4370	void *pvRam = NULL;
4371	void *pvAlt = NULL;
4372	if (pVM->pgm.s.fNemMode)
4373	{
4374	if (!fRamExists)
4375	{
4376	int rc = SUPR3PageAlloc(cPages, 0, &pvRam);
4377	if (RT_FAILURE(rc))
4378	return rc;
4379	}
4380	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4381	{
4382	int rc = SUPR3PageAlloc(cPages, 0, &pvAlt);
4383	if (RT_FAILURE(rc))
4384	{
4385	if (pvRam)
4386	SUPR3PageFree(pvRam, cPages);
4387	return rc;
4388	}
4389	}
4390	}
4391	else
4392	#endif
4393	{
4394	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
4395	AssertRCReturn(rc, rc);
4396
4397	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4398	{
4399	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
4400	pReq->aPages[iPage].fZeroed = false;
4401	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
4402	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
4403	}
4404
4405	rc = GMMR3AllocatePagesPerform(pVM, pReq);
4406	if (RT_FAILURE(rc))
4407	{
4408	GMMR3AllocatePagesCleanup(pReq);
4409	return rc;
4410	}
4411	}
4412
4413	/*
4414	* Allocate the new ROM range and RAM range (if necessary).
4415	*/
4416	PPGMROMRANGE pRomNew;
4417	int rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
4418	if (RT_SUCCESS(rc))
4419	{
4420	PPGMRAMRANGE pRamNew = NULL;
4421	if (!fRamExists)
4422	rc = MMHyperAlloc(pVM, RT_UOFFSETOF_DYN(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
4423	if (RT_SUCCESS(rc))
4424	{
4425	/*
4426	* Initialize and insert the RAM range (if required).
4427	*/
4428	uint32_t const idxFirstRamPage = fRamExists ? (GCPhys - pRam->GCPhys) >> PAGE_SHIFT : 0;
4429	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
4430	if (!fRamExists)
4431	{
4432	/* New RAM range. */
4433	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
4434	pRamNew->GCPhys = GCPhys;
4435	pRamNew->GCPhysLast = GCPhysLast;
4436	pRamNew->cb = cb;
4437	pRamNew->pszDesc = pszDesc;
4438	pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
4439	pRamNew->pvR3 = NULL;
4440	pRamNew->paLSPages = NULL;
4441	#ifdef VBOX_WITH_NATIVE_NEM
4442	pRamNew->uNemRange = uNemRange;
4443	#endif
4444
4445	PPGMPAGE pRamPage = &pRamNew->aPages[idxFirstRamPage];
4446	#ifdef VBOX_WITH_PGM_NEM_MODE
4447	if (pVM->pgm.s.fNemMode)
4448	{
4449	AssertPtr(pvRam); Assert(pReq == NULL);
4450	pRamNew->pvR3 = pvRam;
4451	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4452	{
4453	PGM_PAGE_INIT(pRamPage, UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
4454	PGMPAGETYPE_ROM, PGM_PAGE_STATE_ALLOCATED);
4455	pRomPage->Virgin = *pRamPage;
4456	}
4457	}
4458	else
4459	#endif
4460	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4461	{
4462	PGM_PAGE_INIT(pRamPage,
4463	pReq->aPages[iPage].HCPhysGCPhys,
4464	pReq->aPages[iPage].idPage,
4465	PGMPAGETYPE_ROM,
4466	PGM_PAGE_STATE_ALLOCATED);
4467
4468	pRomPage->Virgin = *pRamPage;
4469	}
4470
4471	pVM->pgm.s.cAllPages += cPages;
4472	pVM->pgm.s.cPrivatePages += cPages;
4473	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
4474	}
4475	else
4476	{
4477	/* Existing RAM range. */
4478	PPGMPAGE pRamPage = &pRam->aPages[idxFirstRamPage];
4479	#ifdef VBOX_WITH_PGM_NEM_MODE
4480	if (pVM->pgm.s.fNemMode)
4481	{
4482	Assert(pvRam == NULL); Assert(pReq == NULL);
4483	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4484	{
4485	Assert(PGM_PAGE_GET_HCPHYS(pRamPage) == UINT64_C(0x0000fffffffff000));
4486	Assert(PGM_PAGE_GET_PAGEID(pRamPage) == NIL_GMM_PAGEID);
4487	Assert(PGM_PAGE_GET_STATE(pRamPage) == PGM_PAGE_STATE_ALLOCATED);
4488	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_ROM);
4489	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4490	PGM_PAGE_SET_PDE_TYPE(pVM, pRamPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4491	PGM_PAGE_SET_PTE_INDEX(pVM, pRamPage, 0);
4492	PGM_PAGE_SET_TRACKING(pVM, pRamPage, 0);
4493
4494	pRomPage->Virgin = *pRamPage;
4495	}
4496	}
4497	else
4498	#endif
4499	{
4500	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4501	{
4502	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_ROM);
4503	PGM_PAGE_SET_HCPHYS(pVM, pRamPage, pReq->aPages[iPage].HCPhysGCPhys);
4504	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4505	PGM_PAGE_SET_PAGEID(pVM, pRamPage, pReq->aPages[iPage].idPage);
4506	PGM_PAGE_SET_PDE_TYPE(pVM, pRamPage, PGM_PAGE_PDE_TYPE_DONTCARE);
4507	PGM_PAGE_SET_PTE_INDEX(pVM, pRamPage, 0);
4508	PGM_PAGE_SET_TRACKING(pVM, pRamPage, 0);
4509
4510	pRomPage->Virgin = *pRamPage;
4511	}
4512	pVM->pgm.s.cZeroPages -= cPages;
4513	pVM->pgm.s.cPrivatePages += cPages;
4514	}
4515	pRamNew = pRam;
4516	}
4517
4518	#ifdef VBOX_WITH_NATIVE_NEM
4519	/* Set the NEM state of the pages if needed. */
4520	if (u2NemState != UINT8_MAX)
4521	pgmPhysSetNemStateForPages(&pRamNew->aPages[idxFirstRamPage], cPages, u2NemState);
4522	#endif
4523
4524	/* Flush physical page map TLB. */
4525	pgmPhysInvalidatePageMapTLB(pVM);
4526
4527	/*
4528	* Register the ROM access handler.
4529	*/
4530	rc = PGMHandlerPhysicalRegister(pVM, GCPhys, GCPhysLast, pVM->pgm.s.hRomPhysHandlerType,
4531	pRomNew, MMHyperCCToR0(pVM, pRomNew), NIL_RTRCPTR, pszDesc);
4532	if (RT_SUCCESS(rc))
4533	{
4534	/*
4535	* Copy the image over to the virgin pages.
4536	* This must be done after linking in the RAM range.
4537	*/
4538	size_t cbBinaryLeft = cbBinary;
4539	PPGMPAGE pRamPage = &pRamNew->aPages[idxFirstRamPage];
4540	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4541	{
4542	void *pvDstPage;
4543	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
4544	if (RT_FAILURE(rc))
4545	{
4546	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
4547	break;
4548	}
4549	if (cbBinaryLeft >= PAGE_SIZE)
4550	{
4551	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), PAGE_SIZE);
4552	cbBinaryLeft -= PAGE_SIZE;
4553	}
4554	else
4555	{
4556	ASMMemZeroPage(pvDstPage); /* (shouldn't be necessary, but can't hurt either) */
4557	if (cbBinaryLeft > 0)
4558	{
4559	memcpy(pvDstPage, (uint8_t const *)pvBinary + ((size_t)iPage << PAGE_SHIFT), cbBinaryLeft);
4560	cbBinaryLeft = 0;
4561	}
4562	}
4563	}
4564	if (RT_SUCCESS(rc))
4565	{
4566	/*
4567	* Initialize the ROM range.
4568	* Note that the Virgin member of the pages has already been initialized above.
4569	*/
4570	pRomNew->GCPhys = GCPhys;
4571	pRomNew->GCPhysLast = GCPhysLast;
4572	pRomNew->cb = cb;
4573	pRomNew->fFlags = fFlags;
4574	pRomNew->idSavedState = UINT8_MAX;
4575	pRomNew->cbOriginal = cbBinary;
4576	pRomNew->pszDesc = pszDesc;
4577	#ifdef VBOX_WITH_PGM_NEM_MODE
4578	pRomNew->pbR3Alternate = (uint8_t *)pvAlt;
4579	#endif
4580	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY
4581	? pvBinary : RTMemDup(pvBinary, cbBinary);
4582	if (pRomNew->pvOriginal)
4583	{
4584	for (unsigned iPage = 0; iPage < cPages; iPage++)
4585	{
4586	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
4587	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
4588	#ifdef VBOX_WITH_PGM_NEM_MODE
4589	if (pVM->pgm.s.fNemMode)
4590	PGM_PAGE_INIT(&pPage->Shadow, UINT64_C(0x0000fffffffff000), NIL_GMM_PAGEID,
4591	PGMPAGETYPE_ROM_SHADOW, PGM_PAGE_STATE_ALLOCATED);
4592	else
4593	#endif
4594	PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
4595	}
4596
4597	/* update the page count stats for the shadow pages. */
4598	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4599	{
4600	#ifdef VBOX_WITH_PGM_NEM_MODE
4601	if (pVM->pgm.s.fNemMode)
4602	pVM->pgm.s.cPrivatePages += cPages;
4603	else
4604	#endif
4605	pVM->pgm.s.cZeroPages += cPages;
4606	pVM->pgm.s.cAllPages += cPages;
4607	}
4608
4609	/*
4610	* Insert the ROM range, tell REM and return successfully.
4611	*/
4612	pRomNew->pNextR3 = pRom;
4613	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4614
4615	if (pRomPrev)
4616	{
4617	pRomPrev->pNextR3 = pRomNew;
4618	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
4619	}
4620	else
4621	{
4622	pVM->pgm.s.pRomRangesR3 = pRomNew;
4623	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
4624	}
4625
4626	pgmPhysInvalidatePageMapTLB(pVM);
4627	#ifdef VBOX_WITH_PGM_NEM_MODE
4628	if (!pVM->pgm.s.fNemMode)
4629	#endif
4630	GMMR3AllocatePagesCleanup(pReq);
4631
4632	#ifdef VBOX_WITH_NATIVE_NEM
4633	/*
4634	* Notify NEM again.
4635	*/
4636	if (VM_IS_NEM_ENABLED(pVM))
4637	{
4638	u2NemState = UINT8_MAX;
4639	rc = NEMR3NotifyPhysRomRegisterLate(pVM, GCPhys, cb, PGM_RAMRANGE_CALC_PAGE_R3PTR(pRamNew, GCPhys),
4640	fNemNotify, &u2NemState,
4641	fRamExists ? &pRam->uNemRange : &pRamNew->uNemRange);
4642	if (u2NemState != UINT8_MAX)
4643	pgmPhysSetNemStateForPages(&pRamNew->aPages[idxFirstRamPage], cPages, u2NemState);
4644	if (RT_SUCCESS(rc))
4645	return rc;
4646	}
4647	else
4648	#endif
4649	return rc;
4650
4651	/*
4652	* bail out
4653	*/
4654	#ifdef VBOX_WITH_NATIVE_NEM
4655	/* unlink */
4656	if (pRomPrev)
4657	{
4658	pRomPrev->pNextR3 = pRom;
4659	pRomPrev->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4660	}
4661	else
4662	{
4663	pVM->pgm.s.pRomRangesR3 = pRom;
4664	pVM->pgm.s.pRomRangesR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
4665	}
4666
4667	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4668	{
4669	# ifdef VBOX_WITH_PGM_NEM_MODE
4670	if (pVM->pgm.s.fNemMode)
4671	pVM->pgm.s.cPrivatePages -= cPages;
4672	else
4673	# endif
4674	pVM->pgm.s.cZeroPages -= cPages;
4675	pVM->pgm.s.cAllPages -= cPages;
4676	}
4677	#endif
4678	}
4679	else
4680	rc = VERR_NO_MEMORY;
4681	}
4682
4683	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
4684	AssertRC(rc2);
4685	}
4686
4687	if (!fRamExists)
4688	{
4689	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
4690	MMHyperFree(pVM, pRamNew);
4691	}
4692	else
4693	{
4694	PPGMPAGE pRamPage = &pRam->aPages[idxFirstRamPage];
4695	#ifdef VBOX_WITH_PGM_NEM_MODE
4696	if (pVM->pgm.s.fNemMode)
4697	{
4698	Assert(pvRam == NULL); Assert(pReq == NULL);
4699	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++, pRomPage++)
4700	{
4701	Assert(PGM_PAGE_GET_HCPHYS(pRamPage) == UINT64_C(0x0000fffffffff000));
4702	Assert(PGM_PAGE_GET_PAGEID(pRamPage) == NIL_GMM_PAGEID);
4703	Assert(PGM_PAGE_GET_STATE(pRamPage) == PGM_PAGE_STATE_ALLOCATED);
4704	PGM_PAGE_SET_TYPE(pVM, pRamPage, PGMPAGETYPE_RAM);
4705	PGM_PAGE_SET_STATE(pVM, pRamPage, PGM_PAGE_STATE_ALLOCATED);
4706	}
4707	}
4708	else
4709	#endif
4710	{
4711	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
4712	PGM_PAGE_INIT_ZERO(pRamPage, pVM, PGMPAGETYPE_RAM);
4713	pVM->pgm.s.cZeroPages += cPages;
4714	pVM->pgm.s.cPrivatePages -= cPages;
4715	}
4716	}
4717	}
4718	MMHyperFree(pVM, pRomNew);
4719	}
4720
4721	/** @todo Purge the mapping cache or something... */
4722	#ifdef VBOX_WITH_PGM_NEM_MODE
4723	if (pVM->pgm.s.fNemMode)
4724	{
4725	Assert(!pReq);
4726	if (pvRam)
4727	SUPR3PageFree(pvRam, cPages);
4728	if (pvAlt)
4729	SUPR3PageFree(pvAlt, cPages);
4730	}
4731	else
4732	#endif
4733	{
4734	GMMR3FreeAllocatedPages(pVM, pReq);
4735	GMMR3AllocatePagesCleanup(pReq);
4736	}
4737	return rc;
4738	}
4739
4740
4741	/**
4742	* Registers a ROM image.
4743	*
4744	* Shadowed ROM images requires double the amount of backing memory, so,
4745	* don't use that unless you have to. Shadowing of ROM images is process
4746	* where we can select where the reads go and where the writes go. On real
4747	* hardware the chipset provides means to configure this. We provide
4748	* PGMR3PhysProtectROM() for this purpose.
4749	*
4750	* A read-only copy of the ROM image will always be kept around while we
4751	* will allocate RAM pages for the changes on demand (unless all memory
4752	* is configured to be preallocated).
4753	*
4754	* @returns VBox status code.
4755	* @param pVM The cross context VM structure.
4756	* @param pDevIns The device instance owning the ROM.
4757	* @param GCPhys First physical address in the range.
4758	* Must be page aligned!
4759	* @param cb The size of the range (in bytes).
4760	* Must be page aligned!
4761	* @param pvBinary Pointer to the binary data backing the ROM image.
4762	* @param cbBinary The size of the binary data pvBinary points to.
4763	* This must be less or equal to @a cb.
4764	* @param fFlags Mask of flags, PGMPHYS_ROM_FLAGS_XXX.
4765	* @param pszDesc Pointer to description string. This must not be freed.
4766	*
4767	* @remark There is no way to remove the rom, automatically on device cleanup or
4768	* manually from the device yet. This isn't difficult in any way, it's
4769	* just not something we expect to be necessary for a while.
4770	*/
4771	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
4772	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc)
4773	{
4774	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p cbBinary=%#x fFlags=%#x pszDesc=%s\n",
4775	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, cbBinary, fFlags, pszDesc));
4776	PGM_LOCK_VOID(pVM);
4777	int rc = pgmR3PhysRomRegisterLocked(pVM, pDevIns, GCPhys, cb, pvBinary, cbBinary, fFlags, pszDesc);
4778	PGM_UNLOCK(pVM);
4779	return rc;
4780	}
4781
4782
4783	/**
4784	* Called by PGMR3MemSetup to reset the shadow, switch to the virgin, and verify
4785	* that the virgin part is untouched.
4786	*
4787	* This is done after the normal memory has been cleared.
4788	*
4789	* ASSUMES that the caller owns the PGM lock.
4790	*
4791	* @param pVM The cross context VM structure.
4792	*/
4793	int pgmR3PhysRomReset(PVM pVM)
4794	{
4795	PGM_LOCK_ASSERT_OWNER(pVM);
4796	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4797	{
4798	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
4799
4800	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
4801	{
4802	/*
4803	* Reset the physical handler.
4804	*/
4805	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
4806	AssertRCReturn(rc, rc);
4807
4808	/*
4809	* What we do with the shadow pages depends on the memory
4810	* preallocation option. If not enabled, we'll just throw
4811	* out all the dirty pages and replace them by the zero page.
4812	*/
4813	#ifdef VBOX_WITH_PGM_NEM_MODE
4814	if (pVM->pgm.s.fNemMode)
4815	{
4816	/* Clear all the shadow pages (currently using alternate backing). */
4817	RT_BZERO(pRom->pbR3Alternate, pRom->cb);
4818	}
4819	else
4820	#endif
4821	if (!pVM->pgm.s.fRamPreAlloc)
4822	{
4823	/* Free the dirty pages. */
4824	uint32_t cPendingPages = 0;
4825	PGMMFREEPAGESREQ pReq;
4826	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4827	AssertRCReturn(rc, rc);
4828
4829	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4830	if ( !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow)
4831	&& !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow))
4832	{
4833	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
4834	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow,
4835	pRom->GCPhys + (iPage << PAGE_SHIFT),
4836	(PGMPAGETYPE)PGM_PAGE_GET_TYPE(&pRom->aPages[iPage].Shadow));
4837	AssertLogRelRCReturn(rc, rc);
4838	}
4839
4840	if (cPendingPages)
4841	{
4842	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
4843	AssertLogRelRCReturn(rc, rc);
4844	}
4845	GMMR3FreePagesCleanup(pReq);
4846	}
4847	else
4848	{
4849	/* clear all the shadow pages. */
4850	for (uint32_t iPage = 0; iPage < cPages; iPage++)
4851	{
4852	if (PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow))
4853	continue;
4854	Assert(!PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow));
4855	void *pvDstPage;
4856	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4857	rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
4858	if (RT_FAILURE(rc))
4859	break;
4860	ASMMemZeroPage(pvDstPage);
4861	}
4862	AssertRCReturn(rc, rc);
4863	}
4864	}
4865
4866	/*
4867	* Restore the original ROM pages after a saved state load.
4868	* Also, in strict builds check that ROM pages remain unmodified.
4869	*/
4870	#ifndef VBOX_STRICT
4871	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4872	#endif
4873	{
4874	size_t cbSrcLeft = pRom->cbOriginal;
4875	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
4876	uint32_t cRestored = 0;
4877	for (uint32_t iPage = 0; iPage < cPages && cbSrcLeft > 0; iPage++, pbSrcPage += PAGE_SIZE)
4878	{
4879	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
4880	PPGMPAGE const pPage = pgmPhysGetPage(pVM, GCPhys);
4881	void const *pvDstPage = NULL;
4882	int rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvDstPage);
4883	if (RT_FAILURE(rc))
4884	break;
4885
4886	if (memcmp(pvDstPage, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE)))
4887	{
4888	if (pVM->pgm.s.fRestoreRomPagesOnReset)
4889	{
4890	void *pvDstPageW = NULL;
4891	rc = pgmPhysPageMap(pVM, pPage, GCPhys, &pvDstPageW);
4892	AssertLogRelRCReturn(rc, rc);
4893	memcpy(pvDstPageW, pbSrcPage, RT_MIN(cbSrcLeft, PAGE_SIZE));
4894	cRestored++;
4895	}
4896	else
4897	LogRel(("pgmR3PhysRomReset: %RGp: ROM page changed (%s)\n", GCPhys, pRom->pszDesc));
4898	}
4899	cbSrcLeft -= RT_MIN(cbSrcLeft, PAGE_SIZE);
4900	}
4901	if (cRestored > 0)
4902	LogRel(("PGM: ROM \"%s\": Reloaded %u of %u pages.\n", pRom->pszDesc, cRestored, cPages));
4903	}
4904	}
4905
4906	/* Clear the ROM restore flag now as we only need to do this once after
4907	loading saved state. */
4908	pVM->pgm.s.fRestoreRomPagesOnReset = false;
4909
4910	return VINF_SUCCESS;
4911	}
4912
4913
4914	/**
4915	* Called by PGMR3Term to free resources.
4916	*
4917	* ASSUMES that the caller owns the PGM lock.
4918	*
4919	* @param pVM The cross context VM structure.
4920	*/
4921	void pgmR3PhysRomTerm(PVM pVM)
4922	{
4923	/*
4924	* Free the heap copy of the original bits.
4925	*/
4926	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4927	{
4928	if ( pRom->pvOriginal
4929	&& !(pRom->fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY))
4930	{
4931	RTMemFree((void *)pRom->pvOriginal);
4932	pRom->pvOriginal = NULL;
4933	}
4934	}
4935	}
4936
4937
4938	/**
4939	* Change the shadowing of a range of ROM pages.
4940	*
4941	* This is intended for implementing chipset specific memory registers
4942	* and will not be very strict about the input. It will silently ignore
4943	* any pages that are not the part of a shadowed ROM.
4944	*
4945	* @returns VBox status code.
4946	* @retval VINF_PGM_SYNC_CR3
4947	*
4948	* @param pVM The cross context VM structure.
4949	* @param GCPhys Where to start. Page aligned.
4950	* @param cb How much to change. Page aligned.
4951	* @param enmProt The new ROM protection.
4952	*/
4953	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
4954	{
4955	/*
4956	* Check input
4957	*/
4958	if (!cb)
4959	return VINF_SUCCESS;
4960	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4961	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
4962	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
4963	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
4964	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
4965
4966	/*
4967	* Process the request.
4968	*/
4969	PGM_LOCK_VOID(pVM);
4970	int rc = VINF_SUCCESS;
4971	bool fFlushTLB = false;
4972	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
4973	{
4974	if ( GCPhys <= pRom->GCPhysLast
4975	&& GCPhysLast >= pRom->GCPhys
4976	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
4977	{
4978	/*
4979	* Iterate the relevant pages and make necessary the changes.
4980	*/
4981	#ifdef VBOX_WITH_NATIVE_NEM
4982	PPGMRAMRANGE const pRam = pgmPhysGetRange(pVM, GCPhys);
4983	AssertPtrReturn(pRam, VERR_INTERNAL_ERROR_3);
4984	#endif
4985	bool fChanges = false;
4986	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
4987	? pRom->cb >> PAGE_SHIFT
4988	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
4989	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
4990	iPage < cPages;
4991	iPage++)
4992	{
4993	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
4994	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
4995	{
4996	fChanges = true;
4997
4998	/* flush references to the page. */
4999	RTGCPHYS const GCPhysPage = pRom->GCPhys + (iPage << PAGE_SHIFT);
5000	PPGMPAGE pRamPage = pgmPhysGetPage(pVM, GCPhysPage);
5001	int rc2 = pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pRamPage, true /fFlushPTEs/, &fFlushTLB);
5002	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
5003	rc = rc2;
5004	#ifdef VBOX_WITH_NATIVE_NEM
5005	uint8_t u2State = PGM_PAGE_GET_NEM_STATE(pRamPage);
5006	#endif
5007
5008	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
5009	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
5010
5011	pOld = pRamPage;
5012	pRamPage = pNew;
5013	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
5014
5015	#ifdef VBOX_WITH_NATIVE_NEM
5016	# ifdef VBOX_WITH_PGM_NEM_MODE
5017	/* In simplified mode we have to switch the page data around too. */
5018	if (pVM->pgm.s.fNemMode)
5019	{
5020	uint8_t abPage[PAGE_SIZE];
5021	uint8_t * const pbRamPage = PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhysPage);
5022	memcpy(abPage, &pRom->pbR3Alternate[(size_t)iPage << PAGE_SHIFT], sizeof(abPage));
5023	memcpy(&pRom->pbR3Alternate[(size_t)iPage << PAGE_SHIFT], pbRamPage, sizeof(abPage));
5024	memcpy(pbRamPage, abPage, sizeof(abPage));
5025	}
5026	# endif
5027	/* Tell NEM about the backing and protection change. */
5028	if (VM_IS_NEM_ENABLED(pVM))
5029	{
5030	PGMPAGETYPE enmType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pNew);
5031	NEMHCNotifyPhysPageChanged(pVM, GCPhys, PGM_PAGE_GET_HCPHYS(pOld), PGM_PAGE_GET_HCPHYS(pNew),
5032	PGM_RAMRANGE_CALC_PAGE_R3PTR(pRam, GCPhysPage),
5033	pgmPhysPageCalcNemProtection(pRamPage, enmType), enmType, &u2State);
5034	PGM_PAGE_SET_NEM_STATE(pRamPage, u2State);
5035	}
5036	#endif
5037	}
5038	pRomPage->enmProt = enmProt;
5039	}
5040
5041	/*
5042	* Reset the access handler if we made changes, no need
5043	* to optimize this.
5044	*/
5045	if (fChanges)
5046	{
5047	int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
5048	if (RT_FAILURE(rc2))
5049	{
5050	PGM_UNLOCK(pVM);
5051	AssertRC(rc);
5052	return rc2;
5053	}
5054	}
5055
5056	/* Advance - cb isn't updated. */
5057	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
5058	}
5059	}
5060	PGM_UNLOCK(pVM);
5061	if (fFlushTLB)
5062	PGM_INVL_ALL_VCPU_TLBS(pVM);
5063
5064	return rc;
5065	}
5066
5067
5068
5069	/*********************************************************************************************************************************
5070	* Ballooning *
5071	*********************************************************************************************************************************/
5072
5073	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
5074
5075	/**
5076	* Rendezvous callback used by PGMR3ChangeMemBalloon that changes the memory balloon size
5077	*
5078	* This is only called on one of the EMTs while the other ones are waiting for
5079	* it to complete this function.
5080	*
5081	* @returns VINF_SUCCESS (VBox strict status code).
5082	* @param pVM The cross context VM structure.
5083	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5084	* @param pvUser User parameter
5085	*/
5086	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5087	{
5088	uintptr_t paUser = (uintptr_t )pvUser;
5089	bool fInflate = !!paUser[0];
5090	unsigned cPages = paUser[1];
5091	RTGCPHYS paPhysPage = (RTGCPHYS )paUser[2];
5092	uint32_t cPendingPages = 0;
5093	PGMMFREEPAGESREQ pReq;
5094	int rc;
5095
5096	Log(("pgmR3PhysChangeMemBalloonRendezvous: %s %x pages\n", (fInflate) ? "inflate" : "deflate", cPages));
5097	PGM_LOCK_VOID(pVM);
5098
5099	if (fInflate)
5100	{
5101	/* Flush the PGM pool cache as we might have stale references to pages that we just freed. */
5102	pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
5103
5104	/* Replace pages with ZERO pages. */
5105	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
5106	if (RT_FAILURE(rc))
5107	{
5108	PGM_UNLOCK(pVM);
5109	AssertLogRelRC(rc);
5110	return rc;
5111	}
5112
5113	/* Iterate the pages. */
5114	for (unsigned i = 0; i < cPages; i++)
5115	{
5116	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
5117	if ( pPage == NULL
5118	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM)
5119	{
5120	Log(("pgmR3PhysChangeMemBalloonRendezvous: invalid physical page %RGp pPage->u3Type=%d\n", paPhysPage[i], pPage ? PGM_PAGE_GET_TYPE(pPage) : 0));
5121	break;
5122	}
5123
5124	LogFlow(("balloon page: %RGp\n", paPhysPage[i]));
5125
5126	/* Flush the shadow PT if this page was previously used as a guest page table. */
5127	pgmPoolFlushPageByGCPhys(pVM, paPhysPage[i]);
5128
5129	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, paPhysPage[i], (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage));
5130	if (RT_FAILURE(rc))
5131	{
5132	PGM_UNLOCK(pVM);
5133	AssertLogRelRC(rc);
5134	return rc;
5135	}
5136	Assert(PGM_PAGE_IS_ZERO(pPage));
5137	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
5138	}
5139
5140	if (cPendingPages)
5141	{
5142	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
5143	if (RT_FAILURE(rc))
5144	{
5145	PGM_UNLOCK(pVM);
5146	AssertLogRelRC(rc);
5147	return rc;
5148	}
5149	}
5150	GMMR3FreePagesCleanup(pReq);
5151	}
5152	else
5153	{
5154	/* Iterate the pages. */
5155	for (unsigned i = 0; i < cPages; i++)
5156	{
5157	PPGMPAGE pPage = pgmPhysGetPage(pVM, paPhysPage[i]);
5158	AssertBreak(pPage && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
5159
5160	LogFlow(("Free ballooned page: %RGp\n", paPhysPage[i]));
5161
5162	Assert(PGM_PAGE_IS_BALLOONED(pPage));
5163
5164	/* Change back to zero page. (NEM does not need to be informed.) */
5165	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
5166	}
5167
5168	/* Note that we currently do not map any ballooned pages in our shadow page tables, so no need to flush the pgm pool. */
5169	}
5170
5171	/* Notify GMM about the balloon change. */
5172	rc = GMMR3BalloonedPages(pVM, (fInflate) ? GMMBALLOONACTION_INFLATE : GMMBALLOONACTION_DEFLATE, cPages);
5173	if (RT_SUCCESS(rc))
5174	{
5175	if (!fInflate)
5176	{
5177	Assert(pVM->pgm.s.cBalloonedPages >= cPages);
5178	pVM->pgm.s.cBalloonedPages -= cPages;
5179	}
5180	else
5181	pVM->pgm.s.cBalloonedPages += cPages;
5182	}
5183
5184	PGM_UNLOCK(pVM);
5185
5186	/* Flush the recompiler's TLB as well. */
5187	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5188	CPUMSetChangedFlags(pVM->apCpusR3[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5189
5190	AssertLogRelRC(rc);
5191	return rc;
5192	}
5193
5194
5195	/**
5196	* Frees a range of ram pages, replacing them with ZERO pages; helper for PGMR3PhysFreeRamPages
5197	*
5198	* @returns VBox status code.
5199	* @param pVM The cross context VM structure.
5200	* @param fInflate Inflate or deflate memory balloon
5201	* @param cPages Number of pages to free
5202	* @param paPhysPage Array of guest physical addresses
5203	*/
5204	static DECLCALLBACK(void) pgmR3PhysChangeMemBalloonHelper(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
5205	{
5206	uintptr_t paUser[3];
5207
5208	paUser[0] = fInflate;
5209	paUser[1] = cPages;
5210	paUser[2] = (uintptr_t)paPhysPage;
5211	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
5212	AssertRC(rc);
5213
5214	/* Made a copy in PGMR3PhysFreeRamPages; free it here. */
5215	RTMemFree(paPhysPage);
5216	}
5217
5218	#endif /* 64-bit host && (Windows \|\| Solaris \|\| Linux \|\| FreeBSD) */
5219
5220	/**
5221	* Inflate or deflate a memory balloon
5222	*
5223	* @returns VBox status code.
5224	* @param pVM The cross context VM structure.
5225	* @param fInflate Inflate or deflate memory balloon
5226	* @param cPages Number of pages to free
5227	* @param paPhysPage Array of guest physical addresses
5228	*/
5229	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
5230	{
5231	/* This must match GMMR0Init; currently we only support memory ballooning on all 64-bit hosts except Mac OS X */
5232	#if HC_ARCH_BITS == 64 && (defined(RT_OS_WINDOWS) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_LINUX) \|\| defined(RT_OS_FREEBSD))
5233	int rc;
5234
5235	/* Older additions (ancient non-functioning balloon code) pass wrong physical addresses. */
5236	AssertReturn(!(paPhysPage[0] & 0xfff), VERR_INVALID_PARAMETER);
5237
5238	/* We own the IOM lock here and could cause a deadlock by waiting for another VCPU that is blocking on the IOM lock.
5239	* In the SMP case we post a request packet to postpone the job.
5240	*/
5241	if (pVM->cCpus > 1)
5242	{
5243	unsigned cbPhysPage = cPages * sizeof(paPhysPage[0]);
5244	RTGCPHYS paPhysPageCopy = (RTGCPHYS )RTMemAlloc(cbPhysPage);
5245	AssertReturn(paPhysPageCopy, VERR_NO_MEMORY);
5246
5247	memcpy(paPhysPageCopy, paPhysPage, cbPhysPage);
5248
5249	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysChangeMemBalloonHelper, 4, pVM, fInflate, cPages, paPhysPageCopy);
5250	AssertRC(rc);
5251	}
5252	else
5253	{
5254	uintptr_t paUser[3];
5255
5256	paUser[0] = fInflate;
5257	paUser[1] = cPages;
5258	paUser[2] = (uintptr_t)paPhysPage;
5259	rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysChangeMemBalloonRendezvous, (void *)paUser);
5260	AssertRC(rc);
5261	}
5262	return rc;
5263
5264	#else
5265	NOREF(pVM); NOREF(fInflate); NOREF(cPages); NOREF(paPhysPage);
5266	return VERR_NOT_IMPLEMENTED;
5267	#endif
5268	}
5269
5270
5271	/*********************************************************************************************************************************
5272	* Write Monitoring *
5273	*********************************************************************************************************************************/
5274
5275	/**
5276	* Rendezvous callback used by PGMR3WriteProtectRAM that write protects all
5277	* physical RAM.
5278	*
5279	* This is only called on one of the EMTs while the other ones are waiting for
5280	* it to complete this function.
5281	*
5282	* @returns VINF_SUCCESS (VBox strict status code).
5283	* @param pVM The cross context VM structure.
5284	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5285	* @param pvUser User parameter, unused.
5286	*/
5287	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5288	{
5289	int rc = VINF_SUCCESS;
5290	NOREF(pvUser); NOREF(pVCpu);
5291
5292	PGM_LOCK_VOID(pVM);
5293	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5294	pgmPoolResetDirtyPages(pVM);
5295	#endif
5296
5297	/** @todo pointless to write protect the physical page pointed to by RSP. */
5298
5299	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
5300	pRam;
5301	pRam = pRam->CTX_SUFF(pNext))
5302	{
5303	uint32_t cPages = pRam->cb >> PAGE_SHIFT;
5304	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5305	{
5306	PPGMPAGE pPage = &pRam->aPages[iPage];
5307	PGMPAGETYPE enmPageType = (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage);
5308
5309	if ( RT_LIKELY(enmPageType == PGMPAGETYPE_RAM)
5310	\|\| enmPageType == PGMPAGETYPE_MMIO2)
5311	{
5312	/*
5313	* A RAM page.
5314	*/
5315	switch (PGM_PAGE_GET_STATE(pPage))
5316	{
5317	case PGM_PAGE_STATE_ALLOCATED:
5318	/** @todo Optimize this: Don't always re-enable write
5319	* monitoring if the page is known to be very busy. */
5320	if (PGM_PAGE_IS_WRITTEN_TO(pPage))
5321	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
5322
5323	pgmPhysPageWriteMonitor(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
5324	break;
5325
5326	case PGM_PAGE_STATE_SHARED:
5327	AssertFailed();
5328	break;
5329
5330	case PGM_PAGE_STATE_WRITE_MONITORED: /* nothing to change. */
5331	default:
5332	break;
5333	}
5334	}
5335	}
5336	}
5337	pgmR3PoolWriteProtectPages(pVM);
5338	PGM_INVL_ALL_VCPU_TLBS(pVM);
5339	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5340	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5341
5342	PGM_UNLOCK(pVM);
5343	return rc;
5344	}
5345
5346	/**
5347	* Protect all physical RAM to monitor writes
5348	*
5349	* @returns VBox status code.
5350	* @param pVM The cross context VM structure.
5351	*/
5352	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM)
5353	{
5354	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
5355
5356	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysWriteProtectRAMRendezvous, NULL);
5357	AssertRC(rc);
5358	return rc;
5359	}
5360
5361
5362	/*********************************************************************************************************************************
5363	* Stats. *
5364	*********************************************************************************************************************************/
5365
5366	/**
5367	* Query the amount of free memory inside VMMR0
5368	*
5369	* @returns VBox status code.
5370	* @param pUVM The user mode VM handle.
5371	* @param pcbAllocMem Where to return the amount of memory allocated
5372	* by VMs.
5373	* @param pcbFreeMem Where to return the amount of memory that is
5374	* allocated from the host but not currently used
5375	* by any VMs.
5376	* @param pcbBallonedMem Where to return the sum of memory that is
5377	* currently ballooned by the VMs.
5378	* @param pcbSharedMem Where to return the amount of memory that is
5379	* currently shared.
5380	*/
5381	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem,
5382	uint64_t pcbBallonedMem, uint64_t pcbSharedMem)
5383	{
5384	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
5385	VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
5386
5387	uint64_t cAllocPages = 0;
5388	uint64_t cFreePages = 0;
5389	uint64_t cBalloonPages = 0;
5390	uint64_t cSharedPages = 0;
5391	int rc = GMMR3QueryHypervisorMemoryStats(pUVM->pVM, &cAllocPages, &cFreePages, &cBalloonPages, &cSharedPages);
5392	AssertRCReturn(rc, rc);
5393
5394	if (pcbAllocMem)
5395	pcbAllocMem = cAllocPages _4K;
5396
5397	if (pcbFreeMem)
5398	pcbFreeMem = cFreePages _4K;
5399
5400	if (pcbBallonedMem)
5401	pcbBallonedMem = cBalloonPages _4K;
5402
5403	if (pcbSharedMem)
5404	pcbSharedMem = cSharedPages _4K;
5405
5406	Log(("PGMR3QueryVMMMemoryStats: all=%llx free=%llx ballooned=%llx shared=%llx\n",
5407	cAllocPages, cFreePages, cBalloonPages, cSharedPages));
5408	return VINF_SUCCESS;
5409	}
5410
5411
5412	/**
5413	* Query memory stats for the VM.
5414	*
5415	* @returns VBox status code.
5416	* @param pUVM The user mode VM handle.
5417	* @param pcbTotalMem Where to return total amount memory the VM may
5418	* possibly use.
5419	* @param pcbPrivateMem Where to return the amount of private memory
5420	* currently allocated.
5421	* @param pcbSharedMem Where to return the amount of actually shared
5422	* memory currently used by the VM.
5423	* @param pcbZeroMem Where to return the amount of memory backed by
5424	* zero pages.
5425	*
5426	* @remarks The total mem is normally larger than the sum of the three
5427	* components. There are two reasons for this, first the amount of
5428	* shared memory is what we're sure is shared instead of what could
5429	* possibly be shared with someone. Secondly, because the total may
5430	* include some pure MMIO pages that doesn't go into any of the three
5431	* sub-counts.
5432	*
5433	* @todo Why do we return reused shared pages instead of anything that could
5434	* potentially be shared? Doesn't this mean the first VM gets a much
5435	* lower number of shared pages?
5436	*/
5437	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem,
5438	uint64_t pcbSharedMem, uint64_t pcbZeroMem)
5439	{
5440	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
5441	PVM pVM = pUVM->pVM;
5442	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
5443
5444	if (pcbTotalMem)
5445	pcbTotalMem = (uint64_t)pVM->pgm.s.cAllPages PAGE_SIZE;
5446
5447	if (pcbPrivateMem)
5448	pcbPrivateMem = (uint64_t)pVM->pgm.s.cPrivatePages PAGE_SIZE;
5449
5450	if (pcbSharedMem)
5451	pcbSharedMem = (uint64_t)pVM->pgm.s.cReusedSharedPages PAGE_SIZE;
5452
5453	if (pcbZeroMem)
5454	pcbZeroMem = (uint64_t)pVM->pgm.s.cZeroPages PAGE_SIZE;
5455
5456	Log(("PGMR3QueryMemoryStats: all=%x private=%x reused=%x zero=%x\n", pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cReusedSharedPages, pVM->pgm.s.cZeroPages));
5457	return VINF_SUCCESS;
5458	}
5459
5460
5461
5462	/*********************************************************************************************************************************
5463	* Chunk Mappings and Page Allocation *
5464	*********************************************************************************************************************************/
5465
5466	/**
5467	* Tree enumeration callback for dealing with age rollover.
5468	* It will perform a simple compression of the current age.
5469	*/
5470	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
5471	{
5472	/* Age compression - ASSUMES iNow == 4. */
5473	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
5474	if (pChunk->iLastUsed >= UINT32_C(0xffffff00))
5475	pChunk->iLastUsed = 3;
5476	else if (pChunk->iLastUsed >= UINT32_C(0xfffff000))
5477	pChunk->iLastUsed = 2;
5478	else if (pChunk->iLastUsed)
5479	pChunk->iLastUsed = 1;
5480	else /* iLastUsed = 0 */
5481	pChunk->iLastUsed = 4;
5482
5483	NOREF(pvUser);
5484	return 0;
5485	}
5486
5487
5488	/**
5489	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
5490	*/
5491	typedef struct PGMR3PHYSCHUNKUNMAPCB
5492	{
5493	PVM pVM; /*< Pointer to the VM. /
5494	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
5495	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
5496
5497
5498	/**
5499	* Callback used to find the mapping that's been unused for
5500	* the longest time.
5501	*/
5502	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLU32NODECORE pNode, void *pvUser)
5503	{
5504	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
5505	PPGMR3PHYSCHUNKUNMAPCB pArg = (PPGMR3PHYSCHUNKUNMAPCB)pvUser;
5506
5507	/*
5508	* Check for locks and compare when last used.
5509	*/
5510	if (pChunk->cRefs)
5511	return 0;
5512	if (pChunk->cPermRefs)
5513	return 0;
5514	if ( pArg->pChunk
5515	&& pChunk->iLastUsed >= pArg->pChunk->iLastUsed)
5516	return 0;
5517
5518	/*
5519	* Check that it's not in any of the TLBs.
5520	*/
5521	PVM pVM = pArg->pVM;
5522	if ( pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(pChunk->Core.Key)].idChunk
5523	== pChunk->Core.Key)
5524	{
5525	pChunk = NULL;
5526	return 0;
5527	}
5528	#ifdef VBOX_STRICT
5529	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5530	{
5531	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk != pChunk);
5532	Assert(pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk != pChunk->Core.Key);
5533	}
5534	#endif
5535
5536	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbR3.aEntries); i++)
5537	if (pVM->pgm.s.PhysTlbR3.aEntries[i].pMap == pChunk)
5538	return 0;
5539
5540	pArg->pChunk = pChunk;
5541	return 0;
5542	}
5543
5544
5545	/**
5546	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
5547	*
5548	* The candidate will not be part of any TLBs, so no need to flush
5549	* anything afterwards.
5550	*
5551	* @returns Chunk id.
5552	* @param pVM The cross context VM structure.
5553	*/
5554	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
5555	{
5556	PGM_LOCK_ASSERT_OWNER(pVM);
5557
5558	/*
5559	* Enumerate the age tree starting with the left most node.
5560	*/
5561	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5562	PGMR3PHYSCHUNKUNMAPCB Args;
5563	Args.pVM = pVM;
5564	Args.pChunk = NULL;
5565	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, &Args);
5566	Assert(Args.pChunk);
5567	if (Args.pChunk)
5568	{
5569	Assert(Args.pChunk->cRefs == 0);
5570	Assert(Args.pChunk->cPermRefs == 0);
5571	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5572	return Args.pChunk->Core.Key;
5573	}
5574
5575	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkFindCandidate, a);
5576	return INT32_MAX;
5577	}
5578
5579
5580	/**
5581	* Rendezvous callback used by pgmR3PhysUnmapChunk that unmaps a chunk
5582	*
5583	* This is only called on one of the EMTs while the other ones are waiting for
5584	* it to complete this function.
5585	*
5586	* @returns VINF_SUCCESS (VBox strict status code).
5587	* @param pVM The cross context VM structure.
5588	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
5589	* @param pvUser User pointer. Unused
5590	*
5591	*/
5592	static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser)
5593	{
5594	int rc = VINF_SUCCESS;
5595	PGM_LOCK_VOID(pVM);
5596	NOREF(pVCpu); NOREF(pvUser);
5597
5598	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
5599	{
5600	/* Flush the pgm pool cache; call the internal rendezvous handler as we're already in a rendezvous handler here. */
5601	/** @todo also not really efficient to unmap a chunk that contains PD
5602	* or PT pages. */
5603	pgmR3PoolClearAllRendezvous(pVM, pVM->apCpusR3[0], NULL /* no need to flush the REM TLB as we already did that above */);
5604
5605	/*
5606	* Request the ring-0 part to unmap a chunk to make space in the mapping cache.
5607	*/
5608	GMMMAPUNMAPCHUNKREQ Req;
5609	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5610	Req.Hdr.cbReq = sizeof(Req);
5611	Req.pvR3 = NULL;
5612	Req.idChunkMap = NIL_GMM_CHUNKID;
5613	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
5614	if (Req.idChunkUnmap != INT32_MAX)
5615	{
5616	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkUnmap, a);
5617	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5618	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkUnmap, a);
5619	if (RT_SUCCESS(rc))
5620	{
5621	/*
5622	* Remove the unmapped one.
5623	*/
5624	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
5625	AssertRelease(pUnmappedChunk);
5626	AssertRelease(!pUnmappedChunk->cRefs);
5627	AssertRelease(!pUnmappedChunk->cPermRefs);
5628	pUnmappedChunk->pv = NULL;
5629	pUnmappedChunk->Core.Key = UINT32_MAX;
5630	MMR3HeapFree(pUnmappedChunk);
5631	pVM->pgm.s.ChunkR3Map.c--;
5632	pVM->pgm.s.cUnmappedChunks++;
5633
5634	/*
5635	* Flush dangling PGM pointers (R3 & R0 ptrs to GC physical addresses).
5636	*/
5637	/** @todo We should not flush chunks which include cr3 mappings. */
5638	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5639	{
5640	PPGMCPU pPGM = &pVM->apCpusR3[idCpu]->pgm.s;
5641
5642	pPGM->pGst32BitPdR3 = NULL;
5643	pPGM->pGstPaePdptR3 = NULL;
5644	pPGM->pGstAmd64Pml4R3 = NULL;
5645	pPGM->pGstEptPml4R3 = NULL;
5646	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
5647	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
5648	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
5649	pPGM->pGstEptPml4R0 = NIL_RTR0PTR;
5650	for (unsigned i = 0; i < RT_ELEMENTS(pPGM->apGstPaePDsR3); i++)
5651	{
5652	pPGM->apGstPaePDsR3[i] = NULL;
5653	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
5654	}
5655
5656	/* Flush REM TLBs. */
5657	CPUMSetChangedFlags(pVM->apCpusR3[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
5658	}
5659	}
5660	}
5661	}
5662	PGM_UNLOCK(pVM);
5663	return rc;
5664	}
5665
5666	/**
5667	* Unmap a chunk to free up virtual address space (request packet handler for pgmR3PhysChunkMap)
5668	*
5669	* @returns VBox status code.
5670	* @param pVM The cross context VM structure.
5671	*/
5672	static DECLCALLBACK(void) pgmR3PhysUnmapChunk(PVM pVM)
5673	{
5674	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PhysUnmapChunkRendezvous, NULL);
5675	AssertRC(rc);
5676	}
5677
5678
5679	/**
5680	* Maps the given chunk into the ring-3 mapping cache.
5681	*
5682	* This will call ring-0.
5683	*
5684	* @returns VBox status code.
5685	* @param pVM The cross context VM structure.
5686	* @param idChunk The chunk in question.
5687	* @param ppChunk Where to store the chunk tracking structure.
5688	*
5689	* @remarks Called from within the PGM critical section.
5690	* @remarks Can be called from any thread!
5691	*/
5692	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
5693	{
5694	int rc;
5695
5696	PGM_LOCK_ASSERT_OWNER(pVM);
5697
5698	/*
5699	* Move the chunk time forward.
5700	*/
5701	pVM->pgm.s.ChunkR3Map.iNow++;
5702	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
5703	{
5704	pVM->pgm.s.ChunkR3Map.iNow = 4;
5705	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
5706	}
5707
5708	/*
5709	* Allocate a new tracking structure first.
5710	*/
5711	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAllocZ(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
5712	AssertReturn(pChunk, VERR_NO_MEMORY);
5713	pChunk->Core.Key = idChunk;
5714	pChunk->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
5715
5716	/*
5717	* Request the ring-0 part to map the chunk in question.
5718	*/
5719	GMMMAPUNMAPCHUNKREQ Req;
5720	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
5721	Req.Hdr.cbReq = sizeof(Req);
5722	Req.pvR3 = NULL;
5723	Req.idChunkMap = idChunk;
5724	Req.idChunkUnmap = NIL_GMM_CHUNKID;
5725
5726	/* Must be callable from any thread, so can't use VMMR3CallR0. */
5727	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatChunkMap, a);
5728	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), NIL_VMCPUID, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
5729	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatChunkMap, a);
5730	if (RT_SUCCESS(rc))
5731	{
5732	pChunk->pv = Req.pvR3;
5733
5734	/*
5735	* If we're running out of virtual address space, then we should
5736	* unmap another chunk.
5737	*
5738	* Currently, an unmap operation requires that all other virtual CPUs
5739	* are idling and not by chance making use of the memory we're
5740	* unmapping. So, we create an async unmap operation here.
5741	*
5742	* Now, when creating or restoring a saved state this wont work very
5743	* well since we may want to restore all guest RAM + a little something.
5744	* So, we have to do the unmap synchronously. Fortunately for us
5745	* though, during these operations the other virtual CPUs are inactive
5746	* and it should be safe to do this.
5747	*/
5748	/** @todo Eventually we should lock all memory when used and do
5749	* map+unmap as one kernel call without any rendezvous or
5750	* other precautions. */
5751	if (pVM->pgm.s.ChunkR3Map.c + 1 >= pVM->pgm.s.ChunkR3Map.cMax)
5752	{
5753	switch (VMR3GetState(pVM))
5754	{
5755	case VMSTATE_LOADING:
5756	case VMSTATE_SAVING:
5757	{
5758	PVMCPU pVCpu = VMMGetCpu(pVM);
5759	if ( pVCpu
5760	&& pVM->pgm.s.cDeprecatedPageLocks == 0)
5761	{
5762	pgmR3PhysUnmapChunkRendezvous(pVM, pVCpu, NULL);
5763	break;
5764	}
5765	}
5766	RT_FALL_THRU();
5767	default:
5768	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pgmR3PhysUnmapChunk, 1, pVM);
5769	AssertRC(rc);
5770	break;
5771	}
5772	}
5773
5774	/*
5775	* Update the tree. We must do this after any unmapping to make sure
5776	* the chunk we're going to return isn't unmapped by accident.
5777	*/
5778	AssertPtr(Req.pvR3);
5779	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
5780	AssertRelease(fRc);
5781	pVM->pgm.s.ChunkR3Map.c++;
5782	pVM->pgm.s.cMappedChunks++;
5783	}
5784	else
5785	{
5786	/** @todo this may fail because of /proc/sys/vm/max_map_count, so we
5787	* should probably restrict ourselves on linux. */
5788	AssertRC(rc);
5789	MMR3HeapFree(pChunk);
5790	pChunk = NULL;
5791	}
5792
5793	*ppChunk = pChunk;
5794	return rc;
5795	}
5796
5797
5798	/**
5799	* Invalidates the TLB for the ring-3 mapping cache.
5800	*
5801	* @param pVM The cross context VM structure.
5802	*/
5803	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
5804	{
5805	PGM_LOCK_VOID(pVM);
5806	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
5807	{
5808	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
5809	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
5810	}
5811	/* The page map TLB references chunks, so invalidate that one too. */
5812	pgmPhysInvalidatePageMapTLB(pVM);
5813	PGM_UNLOCK(pVM);
5814	}
5815
5816
5817	/**
5818	* Response to VM_FF_PGM_NEED_HANDY_PAGES and helper for pgmPhysEnsureHandyPage.
5819	*
5820	* This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
5821	* signal and clear the out of memory condition. When called, this API is used
5822	* to try clear the condition when the user wants to resume.
5823	*
5824	* @returns The following VBox status codes.
5825	* @retval VINF_SUCCESS on success. FFs cleared.
5826	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
5827	* this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
5828	*
5829	* @param pVM The cross context VM structure.
5830	*
5831	* @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
5832	* in EM.cpp and shouldn't be propagated outside TRPM, HM, EM and
5833	* pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
5834	* handler.
5835	*/
5836	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
5837	{
5838	PGM_LOCK_VOID(pVM);
5839
5840	/*
5841	* Allocate more pages, noting down the index of the first new page.
5842	*/
5843	uint32_t iClear = pVM->pgm.s.cHandyPages;
5844	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_PGM_HANDY_PAGE_IPE);
5845	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
5846	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
5847	/** @todo we should split this up into an allocate and flush operation. sometimes you want to flush and not allocate more (which will trigger the vm account limit error) */
5848	if ( rc == VERR_GMM_HIT_VM_ACCOUNT_LIMIT
5849	&& pVM->pgm.s.cHandyPages > 0)
5850	{
5851	/* Still handy pages left, so don't panic. */
5852	rc = VINF_SUCCESS;
5853	}
5854
5855	if (RT_SUCCESS(rc))
5856	{
5857	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
5858	Assert(pVM->pgm.s.cHandyPages > 0);
5859	#ifdef VBOX_STRICT
5860	uint32_t i;
5861	for (i = iClear; i < pVM->pgm.s.cHandyPages; i++)
5862	if ( pVM->pgm.s.aHandyPages[i].idPage == NIL_GMM_PAGEID
5863	\|\| pVM->pgm.s.aHandyPages[i].idSharedPage != NIL_GMM_PAGEID
5864	\|\| (pVM->pgm.s.aHandyPages[i].HCPhysGCPhys & PAGE_OFFSET_MASK))
5865	break;
5866	if (i != pVM->pgm.s.cHandyPages)
5867	{
5868	RTAssertMsg1Weak(NULL, __LINE__, __FILE__, __FUNCTION__);
5869	RTAssertMsg2Weak("i=%d iClear=%d cHandyPages=%d\n", i, iClear, pVM->pgm.s.cHandyPages);
5870	for (uint32_t j = iClear; j < pVM->pgm.s.cHandyPages; j++)
5871	RTAssertMsg2Add("%03d: idPage=%d HCPhysGCPhys=%RHp idSharedPage=%d%s\n", j,
5872	pVM->pgm.s.aHandyPages[j].idPage,
5873	pVM->pgm.s.aHandyPages[j].HCPhysGCPhys,
5874	pVM->pgm.s.aHandyPages[j].idSharedPage,
5875	j == i ? " <---" : "");
5876	RTAssertPanic();
5877	}
5878	#endif
5879	}
5880	else
5881	{
5882	/*
5883	* We should never get here unless there is a genuine shortage of
5884	* memory (or some internal error). Flag the error so the VM can be
5885	* suspended ASAP and the user informed. If we're totally out of
5886	* handy pages we will return failure.
5887	*/
5888	/* Report the failure. */
5889	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc cHandyPages=%#x\n"
5890	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
5891	rc, pVM->pgm.s.cHandyPages,
5892	pVM->pgm.s.cAllPages, pVM->pgm.s.cPrivatePages, pVM->pgm.s.cSharedPages, pVM->pgm.s.cZeroPages));
5893
5894	if ( rc != VERR_NO_MEMORY
5895	&& rc != VERR_NO_PHYS_MEMORY
5896	&& rc != VERR_LOCK_FAILED)
5897	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
5898	{
5899	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
5900	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
5901	pVM->pgm.s.aHandyPages[i].idSharedPage));
5902	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
5903	if (idPage != NIL_GMM_PAGEID)
5904	{
5905	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
5906	pRam;
5907	pRam = pRam->pNextR3)
5908	{
5909	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
5910	for (uint32_t iPage = 0; iPage < cPages; iPage++)
5911	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
5912	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
5913	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
5914	}
5915	}
5916	}
5917
5918	if (rc == VERR_NO_MEMORY)
5919	{
5920	uint64_t cbHostRamAvail = 0;
5921	int rc2 = RTSystemQueryAvailableRam(&cbHostRamAvail);
5922	if (RT_SUCCESS(rc2))
5923	LogRel(("Host RAM: %RU64MB available\n", cbHostRamAvail / _1M));
5924	else
5925	LogRel(("Cannot determine the amount of available host memory\n"));
5926	}
5927
5928	/* Set the FFs and adjust rc. */
5929	VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
5930	VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
5931	if ( rc == VERR_NO_MEMORY
5932	\|\| rc == VERR_NO_PHYS_MEMORY
5933	\|\| rc == VERR_LOCK_FAILED)
5934	rc = VINF_EM_NO_MEMORY;
5935	}
5936
5937	PGM_UNLOCK(pVM);
5938	return rc;
5939	}
5940
5941
5942	/*********************************************************************************************************************************
5943	* Other Stuff *
5944	*********************************************************************************************************************************/
5945
5946	/**
5947	* Sets the Address Gate 20 state.
5948	*
5949	* @param pVCpu The cross context virtual CPU structure.
5950	* @param fEnable True if the gate should be enabled.
5951	* False if the gate should be disabled.
5952	*/
5953	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
5954	{
5955	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
5956	if (pVCpu->pgm.s.fA20Enabled != fEnable)
5957	{
5958	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5959	PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
5960	if ( CPUMIsGuestInVmxRootMode(pCtx)
5961	&& !fEnable)
5962	{
5963	Log(("Cannot enter A20M mode while in VMX root mode\n"));
5964	return;
5965	}
5966	#endif
5967	pVCpu->pgm.s.fA20Enabled = fEnable;
5968	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);
5969	if (VM_IS_NEM_ENABLED(pVCpu->CTX_SUFF(pVM)))
5970	NEMR3NotifySetA20(pVCpu, fEnable);
5971	#ifdef PGM_WITH_A20
5972	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5973	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
5974	HMFlushTlb(pVCpu);
5975	#endif
5976	IEMTlbInvalidateAllPhysical(pVCpu);
5977	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cA20Changes);
5978	}
5979	}
5980

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp@ 92676

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