PGMPool.cpp@ 74168

Last change on this file since 74168 was 73246, checked in by vboxsync, 6 years ago
PGM: Working on eliminating PGMMODEDATA and the corresponding PGMCPU section so we can do mode switching in ring-0. This second part deals with shadow paging pointers and expands PGM_TYPE_NESTED & PGMMODE_NESTED into 32BIT, PAE and AMD64 variants to better map to reality at the expense of a little bit of more code. bugref:9044
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File size: 56.0 KB

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1	/* $Id: PGMPool.cpp 73246 2018-07-19 15:51:20Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_pgm_pool PGM Shadow Page Pool
19	*
20	* Motivations:
21	* -# Relationship between shadow page tables and physical guest pages. This
22	* should allow us to skip most of the global flushes now following access
23	* handler changes. The main expense is flushing shadow pages.
24	* -# Limit the pool size if necessary (default is kind of limitless).
25	* -# Allocate shadow pages from RC. We use to only do this in SyncCR3.
26	* -# Required for 64-bit guests.
27	* -# Combining the PD cache and page pool in order to simplify caching.
28	*
29	*
30	* @section sec_pgm_pool_outline Design Outline
31	*
32	* The shadow page pool tracks pages used for shadowing paging structures (i.e.
33	* page tables, page directory, page directory pointer table and page map
34	* level-4). Each page in the pool has an unique identifier. This identifier is
35	* used to link a guest physical page to a shadow PT. The identifier is a
36	* non-zero value and has a relativly low max value - say 14 bits. This makes it
37	* possible to fit it into the upper bits of the of the aHCPhys entries in the
38	* ram range.
39	*
40	* By restricting host physical memory to the first 48 bits (which is the
41	* announced physical memory range of the K8L chip (scheduled for 2008)), we
42	* can safely use the upper 16 bits for shadow page ID and reference counting.
43	*
44	* Update: The 48 bit assumption will be lifted with the new physical memory
45	* management (PGMPAGE), so we won't have any trouble when someone stuffs 2TB
46	* into a box in some years.
47	*
48	* Now, it's possible for a page to be aliased, i.e. mapped by more than one PT
49	* or PD. This is solved by creating a list of physical cross reference extents
50	* when ever this happens. Each node in the list (extent) is can contain 3 page
51	* pool indexes. The list it self is chained using indexes into the paPhysExt
52	* array.
53	*
54	*
55	* @section sec_pgm_pool_life Life Cycle of a Shadow Page
56	*
57	* -# The SyncPT function requests a page from the pool.
58	* The request includes the kind of page it is (PT/PD, PAE/legacy), the
59	* address of the page it's shadowing, and more.
60	* -# The pool responds to the request by allocating a new page.
61	* When the cache is enabled, it will first check if it's in the cache.
62	* Should the pool be exhausted, one of two things can be done:
63	* -# Flush the whole pool and current CR3.
64	* -# Use the cache to find a page which can be flushed (~age).
65	* -# The SyncPT function will sync one or more pages and insert it into the
66	* shadow PD.
67	* -# The SyncPage function may sync more pages on a later \#PFs.
68	* -# The page is freed / flushed in SyncCR3 (perhaps) and some other cases.
69	* When caching is enabled, the page isn't flush but remains in the cache.
70	*
71	*
72	* @section sec_pgm_pool_monitoring Monitoring
73	*
74	* We always monitor PAGE_SIZE chunks of memory. When we've got multiple shadow
75	* pages for the same PAGE_SIZE of guest memory (PAE and mixed PD/PT) the pages
76	* sharing the monitor get linked using the iMonitoredNext/Prev. The head page
77	* is the pvUser to the access handlers.
78	*
79	*
80	* @section sec_pgm_pool_impl Implementation
81	*
82	* The pool will take pages from the MM page pool. The tracking data
83	* (attributes, bitmaps and so on) are allocated from the hypervisor heap. The
84	* pool content can be accessed both by using the page id and the physical
85	* address (HC). The former is managed by means of an array, the latter by an
86	* offset based AVL tree.
87	*
88	* Flushing of a pool page means that we iterate the content (we know what kind
89	* it is) and updates the link information in the ram range.
90	*
91	* ...
92	*/
93
94
95	/*********************************************************************************************************************************
96	* Header Files *
97	*********************************************************************************************************************************/
98	#define LOG_GROUP LOG_GROUP_PGM_POOL
99	#include <VBox/vmm/pgm.h>
100	#include <VBox/vmm/mm.h>
101	#include "PGMInternal.h"
102	#include <VBox/vmm/vm.h>
103	#include <VBox/vmm/uvm.h>
104	#include "PGMInline.h"
105
106	#include <VBox/log.h>
107	#include <VBox/err.h>
108	#include <iprt/asm.h>
109	#include <iprt/string.h>
110	#include <VBox/dbg.h>
111
112
113	/*********************************************************************************************************************************
114	* Internal Functions *
115	*********************************************************************************************************************************/
116	#ifdef VBOX_WITH_DEBUGGER
117	static FNDBGCCMD pgmR3PoolCmdCheck;
118	#endif
119
120	#ifdef VBOX_WITH_DEBUGGER
121	/** Command descriptors. */
122	static const DBGCCMD g_aCmds[] =
123	{
124	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
125	{ "pgmpoolcheck", 0, 0, NULL, 0, 0, pgmR3PoolCmdCheck, "", "Check the pgm pool pages." },
126	};
127	#endif
128
129	/**
130	* Initializes the pool
131	*
132	* @returns VBox status code.
133	* @param pVM The cross context VM structure.
134	*/
135	int pgmR3PoolInit(PVM pVM)
136	{
137	int rc;
138
139	AssertCompile(NIL_PGMPOOL_IDX == 0);
140	/* pPage->cLocked is an unsigned byte. */
141	AssertCompile(VMM_MAX_CPU_COUNT <= 255);
142
143	/*
144	* Query Pool config.
145	*/
146	PCFGMNODE pCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM/Pool");
147
148	/* Default pgm pool size is 1024 pages (4MB). */
149	uint16_t cMaxPages = 1024;
150
151	/* Adjust it up relative to the RAM size, using the nested paging formula. */
152	uint64_t cbRam;
153	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0); AssertRCReturn(rc, rc);
154	uint64_t u64MaxPages = (cbRam >> 9)
155	+ (cbRam >> 18)
156	+ (cbRam >> 27)
157	+ 32 * PAGE_SIZE;
158	u64MaxPages >>= PAGE_SHIFT;
159	if (u64MaxPages > PGMPOOL_IDX_LAST)
160	cMaxPages = PGMPOOL_IDX_LAST;
161	else
162	cMaxPages = (uint16_t)u64MaxPages;
163
164	/** @cfgm{/PGM/Pool/MaxPages, uint16_t, \#pages, 16, 0x3fff, F(ram-size)}
165	* The max size of the shadow page pool in pages. The pool will grow dynamically
166	* up to this limit.
167	*/
168	rc = CFGMR3QueryU16Def(pCfg, "MaxPages", &cMaxPages, cMaxPages);
169	AssertLogRelRCReturn(rc, rc);
170	AssertLogRelMsgReturn(cMaxPages <= PGMPOOL_IDX_LAST && cMaxPages >= RT_ALIGN(PGMPOOL_IDX_FIRST, 16),
171	("cMaxPages=%u (%#x)\n", cMaxPages, cMaxPages), VERR_INVALID_PARAMETER);
172	cMaxPages = RT_ALIGN(cMaxPages, 16);
173	if (cMaxPages > PGMPOOL_IDX_LAST)
174	cMaxPages = PGMPOOL_IDX_LAST;
175	LogRel(("PGM: PGMPool: cMaxPages=%u (u64MaxPages=%llu)\n", cMaxPages, u64MaxPages));
176
177	/** @todo
178	* We need to be much more careful with our allocation strategy here.
179	* For nested paging we don't need pool user info nor extents at all, but
180	* we can't check for nested paging here (too early during init to get a
181	* confirmation it can be used). The default for large memory configs is a
182	* bit large for shadow paging, so I've restricted the extent maximum to 8k
183	* (8k * 16 = 128k of hyper heap).
184	*
185	* Also when large page support is enabled, we typically don't need so much,
186	* although that depends on the availability of 2 MB chunks on the host.
187	*/
188
189	/** @cfgm{/PGM/Pool/MaxUsers, uint16_t, \#users, MaxUsers, 32K, MaxPages*2}
190	* The max number of shadow page user tracking records. Each shadow page has
191	* zero of other shadow pages (or CR3s) that references it, or uses it if you
192	* like. The structures describing these relationships are allocated from a
193	* fixed sized pool. This configuration variable defines the pool size.
194	*/
195	uint16_t cMaxUsers;
196	rc = CFGMR3QueryU16Def(pCfg, "MaxUsers", &cMaxUsers, cMaxPages * 2);
197	AssertLogRelRCReturn(rc, rc);
198	AssertLogRelMsgReturn(cMaxUsers >= cMaxPages && cMaxPages <= _32K,
199	("cMaxUsers=%u (%#x)\n", cMaxUsers, cMaxUsers), VERR_INVALID_PARAMETER);
200
201	/** @cfgm{/PGM/Pool/MaxPhysExts, uint16_t, \#extents, 16, MaxPages * 2, MIN(MaxPages*2\,8192)}
202	* The max number of extents for tracking aliased guest pages.
203	*/
204	uint16_t cMaxPhysExts;
205	rc = CFGMR3QueryU16Def(pCfg, "MaxPhysExts", &cMaxPhysExts,
206	RT_MIN(cMaxPages * 2, 8192 /* 8Ki max as this eat too much hyper heap */));
207	AssertLogRelRCReturn(rc, rc);
208	AssertLogRelMsgReturn(cMaxPhysExts >= 16 && cMaxPhysExts <= PGMPOOL_IDX_LAST,
209	("cMaxPhysExts=%u (%#x)\n", cMaxPhysExts, cMaxPhysExts), VERR_INVALID_PARAMETER);
210
211	/** @cfgm{/PGM/Pool/ChacheEnabled, bool, true}
212	* Enables or disabling caching of shadow pages. Caching means that we will try
213	* reuse shadow pages instead of recreating them everything SyncCR3, SyncPT or
214	* SyncPage requests one. When reusing a shadow page, we can save time
215	* reconstructing it and it's children.
216	*/
217	bool fCacheEnabled;
218	rc = CFGMR3QueryBoolDef(pCfg, "CacheEnabled", &fCacheEnabled, true);
219	AssertLogRelRCReturn(rc, rc);
220
221	LogRel(("PGM: pgmR3PoolInit: cMaxPages=%#RX16 cMaxUsers=%#RX16 cMaxPhysExts=%#RX16 fCacheEnable=%RTbool\n",
222	cMaxPages, cMaxUsers, cMaxPhysExts, fCacheEnabled));
223
224	/*
225	* Allocate the data structures.
226	*/
227	uint32_t cb = RT_UOFFSETOF_DYN(PGMPOOL, aPages[cMaxPages]);
228	cb += cMaxUsers * sizeof(PGMPOOLUSER);
229	cb += cMaxPhysExts * sizeof(PGMPOOLPHYSEXT);
230	PPGMPOOL pPool;
231	rc = MMR3HyperAllocOnceNoRel(pVM, cb, 0, MM_TAG_PGM_POOL, (void **)&pPool);
232	if (RT_FAILURE(rc))
233	return rc;
234	pVM->pgm.s.pPoolR3 = pPool;
235	pVM->pgm.s.pPoolR0 = MMHyperR3ToR0(pVM, pPool);
236	pVM->pgm.s.pPoolRC = MMHyperR3ToRC(pVM, pPool);
237
238	/*
239	* Initialize it.
240	*/
241	pPool->pVMR3 = pVM;
242	pPool->pVMR0 = pVM->pVMR0;
243	pPool->pVMRC = pVM->pVMRC;
244	pPool->cMaxPages = cMaxPages;
245	pPool->cCurPages = PGMPOOL_IDX_FIRST;
246	pPool->iUserFreeHead = 0;
247	pPool->cMaxUsers = cMaxUsers;
248	PPGMPOOLUSER paUsers = (PPGMPOOLUSER)&pPool->aPages[pPool->cMaxPages];
249	pPool->paUsersR3 = paUsers;
250	pPool->paUsersR0 = MMHyperR3ToR0(pVM, paUsers);
251	pPool->paUsersRC = MMHyperR3ToRC(pVM, paUsers);
252	for (unsigned i = 0; i < cMaxUsers; i++)
253	{
254	paUsers[i].iNext = i + 1;
255	paUsers[i].iUser = NIL_PGMPOOL_IDX;
256	paUsers[i].iUserTable = 0xfffffffe;
257	}
258	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
259	pPool->iPhysExtFreeHead = 0;
260	pPool->cMaxPhysExts = cMaxPhysExts;
261	PPGMPOOLPHYSEXT paPhysExts = (PPGMPOOLPHYSEXT)&paUsers[cMaxUsers];
262	pPool->paPhysExtsR3 = paPhysExts;
263	pPool->paPhysExtsR0 = MMHyperR3ToR0(pVM, paPhysExts);
264	pPool->paPhysExtsRC = MMHyperR3ToRC(pVM, paPhysExts);
265	for (unsigned i = 0; i < cMaxPhysExts; i++)
266	{
267	paPhysExts[i].iNext = i + 1;
268	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
269	paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
270	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
271	paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
272	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
273	paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
274	}
275	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
276	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
277	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
278	pPool->iAgeHead = NIL_PGMPOOL_IDX;
279	pPool->iAgeTail = NIL_PGMPOOL_IDX;
280	pPool->fCacheEnabled = fCacheEnabled;
281
282	pPool->hAccessHandlerType = NIL_PGMPHYSHANDLERTYPE;
283	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_WRITE,
284	pgmPoolAccessHandler,
285	NULL, "pgmPoolAccessHandler", "pgmRZPoolAccessPfHandler",
286	NULL, "pgmPoolAccessHandler", "pgmRZPoolAccessPfHandler",
287	"Guest Paging Access Handler",
288	&pPool->hAccessHandlerType);
289	AssertLogRelRCReturn(rc, rc);
290
291	pPool->HCPhysTree = 0;
292
293	/*
294	* The NIL entry.
295	*/
296	Assert(NIL_PGMPOOL_IDX == 0);
297	pPool->aPages[NIL_PGMPOOL_IDX].enmKind = PGMPOOLKIND_INVALID;
298	pPool->aPages[NIL_PGMPOOL_IDX].idx = NIL_PGMPOOL_IDX;
299	pPool->aPages[NIL_PGMPOOL_IDX].Core.Key = NIL_RTHCPHYS;
300	pPool->aPages[NIL_PGMPOOL_IDX].GCPhys = NIL_RTGCPHYS;
301	pPool->aPages[NIL_PGMPOOL_IDX].iNext = NIL_PGMPOOL_IDX;
302	/* pPool->aPages[NIL_PGMPOOL_IDX].cLocked = INT32_MAX; - test this out... */
303	pPool->aPages[NIL_PGMPOOL_IDX].pvPageR3 = 0;
304	pPool->aPages[NIL_PGMPOOL_IDX].iUserHead = NIL_PGMPOOL_USER_INDEX;
305	pPool->aPages[NIL_PGMPOOL_IDX].iModifiedNext = NIL_PGMPOOL_IDX;
306	pPool->aPages[NIL_PGMPOOL_IDX].iModifiedPrev = NIL_PGMPOOL_IDX;
307	pPool->aPages[NIL_PGMPOOL_IDX].iMonitoredNext = NIL_PGMPOOL_IDX;
308	pPool->aPages[NIL_PGMPOOL_IDX].iMonitoredPrev = NIL_PGMPOOL_IDX;
309	pPool->aPages[NIL_PGMPOOL_IDX].iAgeNext = NIL_PGMPOOL_IDX;
310	pPool->aPages[NIL_PGMPOOL_IDX].iAgePrev = NIL_PGMPOOL_IDX;
311
312	Assert(pPool->aPages[NIL_PGMPOOL_IDX].idx == NIL_PGMPOOL_IDX);
313	Assert(pPool->aPages[NIL_PGMPOOL_IDX].GCPhys == NIL_RTGCPHYS);
314	Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fSeenNonGlobal);
315	Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fMonitored);
316	Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fCached);
317	Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fZeroed);
318	Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fReusedFlushPending);
319
320	#ifdef VBOX_WITH_STATISTICS
321	/*
322	* Register statistics.
323	*/
324	STAM_REG(pVM, &pPool->cCurPages, STAMTYPE_U16, "/PGM/Pool/cCurPages", STAMUNIT_PAGES, "Current pool size.");
325	STAM_REG(pVM, &pPool->cMaxPages, STAMTYPE_U16, "/PGM/Pool/cMaxPages", STAMUNIT_PAGES, "Max pool size.");
326	STAM_REG(pVM, &pPool->cUsedPages, STAMTYPE_U16, "/PGM/Pool/cUsedPages", STAMUNIT_PAGES, "The number of pages currently in use.");
327	STAM_REG(pVM, &pPool->cUsedPagesHigh, STAMTYPE_U16_RESET, "/PGM/Pool/cUsedPagesHigh", STAMUNIT_PAGES, "The high watermark for cUsedPages.");
328	STAM_REG(pVM, &pPool->StatAlloc, STAMTYPE_PROFILE_ADV, "/PGM/Pool/Alloc", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmPoolAlloc.");
329	STAM_REG(pVM, &pPool->StatClearAll, STAMTYPE_PROFILE, "/PGM/Pool/ClearAll", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmR3PoolClearAll.");
330	STAM_REG(pVM, &pPool->StatR3Reset, STAMTYPE_PROFILE, "/PGM/Pool/R3Reset", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmR3PoolReset.");
331	STAM_REG(pVM, &pPool->StatFlushPage, STAMTYPE_PROFILE, "/PGM/Pool/FlushPage", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmPoolFlushPage.");
332	STAM_REG(pVM, &pPool->StatFree, STAMTYPE_PROFILE, "/PGM/Pool/Free", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmPoolFree.");
333	STAM_REG(pVM, &pPool->StatForceFlushPage, STAMTYPE_COUNTER, "/PGM/Pool/FlushForce", STAMUNIT_OCCURENCES, "Counting explicit flushes by PGMPoolFlushPage().");
334	STAM_REG(pVM, &pPool->StatForceFlushDirtyPage, STAMTYPE_COUNTER, "/PGM/Pool/FlushForceDirty", STAMUNIT_OCCURENCES, "Counting explicit flushes of dirty pages by PGMPoolFlushPage().");
335	STAM_REG(pVM, &pPool->StatForceFlushReused, STAMTYPE_COUNTER, "/PGM/Pool/FlushReused", STAMUNIT_OCCURENCES, "Counting flushes for reused pages.");
336	STAM_REG(pVM, &pPool->StatZeroPage, STAMTYPE_PROFILE, "/PGM/Pool/ZeroPage", STAMUNIT_TICKS_PER_CALL, "Profiling time spent zeroing pages. Overlaps with Alloc.");
337	STAM_REG(pVM, &pPool->cMaxUsers, STAMTYPE_U16, "/PGM/Pool/Track/cMaxUsers", STAMUNIT_COUNT, "Max user tracking records.");
338	STAM_REG(pVM, &pPool->cPresent, STAMTYPE_U32, "/PGM/Pool/Track/cPresent", STAMUNIT_COUNT, "Number of present page table entries.");
339	STAM_REG(pVM, &pPool->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Pool/Track/Deref", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmPoolTrackDeref.");
340	STAM_REG(pVM, &pPool->StatTrackFlushGCPhysPT, STAMTYPE_PROFILE, "/PGM/Pool/Track/FlushGCPhysPT", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmPoolTrackFlushGCPhysPT.");
341	STAM_REG(pVM, &pPool->StatTrackFlushGCPhysPTs, STAMTYPE_PROFILE, "/PGM/Pool/Track/FlushGCPhysPTs", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmPoolTrackFlushGCPhysPTs.");
342	STAM_REG(pVM, &pPool->StatTrackFlushGCPhysPTsSlow, STAMTYPE_PROFILE, "/PGM/Pool/Track/FlushGCPhysPTsSlow", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmPoolTrackFlushGCPhysPTsSlow.");
343	STAM_REG(pVM, &pPool->StatTrackFlushEntry, STAMTYPE_COUNTER, "/PGM/Pool/Track/Entry/Flush", STAMUNIT_COUNT, "Nr of flushed entries.");
344	STAM_REG(pVM, &pPool->StatTrackFlushEntryKeep, STAMTYPE_COUNTER, "/PGM/Pool/Track/Entry/Update", STAMUNIT_COUNT, "Nr of updated entries.");
345	STAM_REG(pVM, &pPool->StatTrackFreeUpOneUser, STAMTYPE_COUNTER, "/PGM/Pool/Track/FreeUpOneUser", STAMUNIT_TICKS_PER_CALL, "The number of times we were out of user tracking records.");
346	STAM_REG(pVM, &pPool->StatTrackDerefGCPhys, STAMTYPE_PROFILE, "/PGM/Pool/Track/DrefGCPhys", STAMUNIT_TICKS_PER_CALL, "Profiling deref activity related tracking GC physical pages.");
347	STAM_REG(pVM, &pPool->StatTrackLinearRamSearches, STAMTYPE_COUNTER, "/PGM/Pool/Track/LinearRamSearches", STAMUNIT_OCCURENCES, "The number of times we had to do linear ram searches.");
348	STAM_REG(pVM, &pPool->StamTrackPhysExtAllocFailures,STAMTYPE_COUNTER, "/PGM/Pool/Track/PhysExtAllocFailures", STAMUNIT_OCCURENCES, "The number of failing pgmPoolTrackPhysExtAlloc calls.");
349
350	STAM_REG(pVM, &pPool->StatMonitorPfRZ, STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/#PF", STAMUNIT_TICKS_PER_CALL, "Profiling the RC/R0 #PF access handler.");
351	STAM_REG(pVM, &pPool->StatMonitorPfRZEmulateInstr, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/#PF/EmulateInstr", STAMUNIT_OCCURENCES, "Times we've failed interpreting the instruction.");
352	STAM_REG(pVM, &pPool->StatMonitorPfRZFlushPage, STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/#PF/FlushPage", STAMUNIT_TICKS_PER_CALL, "Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler.");
353	STAM_REG(pVM, &pPool->StatMonitorPfRZFlushReinit, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/#PF/FlushReinit", STAMUNIT_OCCURENCES, "Times we've detected a page table reinit.");
354	STAM_REG(pVM, &pPool->StatMonitorPfRZFlushModOverflow,STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/#PF/FlushOverflow", STAMUNIT_OCCURENCES, "Counting flushes for pages that are modified too often.");
355	STAM_REG(pVM, &pPool->StatMonitorPfRZFork, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/#PF/Fork", STAMUNIT_OCCURENCES, "Times we've detected fork().");
356	STAM_REG(pVM, &pPool->StatMonitorPfRZHandled, STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/#PF/Handled", STAMUNIT_TICKS_PER_CALL, "Profiling the RC/R0 #PF access we've handled (except REP STOSD).");
357	STAM_REG(pVM, &pPool->StatMonitorPfRZIntrFailPatch1, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/#PF/IntrFailPatch1", STAMUNIT_OCCURENCES, "Times we've failed interpreting a patch code instruction.");
358	STAM_REG(pVM, &pPool->StatMonitorPfRZIntrFailPatch2, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/#PF/IntrFailPatch2", STAMUNIT_OCCURENCES, "Times we've failed interpreting a patch code instruction during flushing.");
359	STAM_REG(pVM, &pPool->StatMonitorPfRZRepPrefix, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/#PF/RepPrefix", STAMUNIT_OCCURENCES, "The number of times we've seen rep prefixes we can't handle.");
360	STAM_REG(pVM, &pPool->StatMonitorPfRZRepStosd, STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/#PF/RepStosd", STAMUNIT_TICKS_PER_CALL, "Profiling the REP STOSD cases we've handled.");
361
362	STAM_REG(pVM, &pPool->StatMonitorRZ, STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM", STAMUNIT_TICKS_PER_CALL, "Profiling the regular access handler.");
363	STAM_REG(pVM, &pPool->StatMonitorRZFlushPage, STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/FlushPage", STAMUNIT_TICKS_PER_CALL, "Profiling the pgmPoolFlushPage calls made from the regular access handler.");
364	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[0], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size01", STAMUNIT_OCCURENCES, "Number of 1 byte accesses.");
365	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[1], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size02", STAMUNIT_OCCURENCES, "Number of 2 byte accesses.");
366	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[2], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size03", STAMUNIT_OCCURENCES, "Number of 3 byte accesses.");
367	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[3], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size04", STAMUNIT_OCCURENCES, "Number of 4 byte accesses.");
368	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[4], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size05", STAMUNIT_OCCURENCES, "Number of 5 byte accesses.");
369	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[5], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size06", STAMUNIT_OCCURENCES, "Number of 6 byte accesses.");
370	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[6], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size07", STAMUNIT_OCCURENCES, "Number of 7 byte accesses.");
371	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[7], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size08", STAMUNIT_OCCURENCES, "Number of 8 byte accesses.");
372	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[8], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size09", STAMUNIT_OCCURENCES, "Number of 9 byte accesses.");
373	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[9], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size0a", STAMUNIT_OCCURENCES, "Number of 10 byte accesses.");
374	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[10], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size0b", STAMUNIT_OCCURENCES, "Number of 11 byte accesses.");
375	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[11], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size0c", STAMUNIT_OCCURENCES, "Number of 12 byte accesses.");
376	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[12], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size0d", STAMUNIT_OCCURENCES, "Number of 13 byte accesses.");
377	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[13], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size0e", STAMUNIT_OCCURENCES, "Number of 14 byte accesses.");
378	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[14], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size0f", STAMUNIT_OCCURENCES, "Number of 15 byte accesses.");
379	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[15], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size10", STAMUNIT_OCCURENCES, "Number of 16 byte accesses.");
380	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[16], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size11-2f", STAMUNIT_OCCURENCES, "Number of 17-31 byte accesses.");
381	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[17], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size20-3f", STAMUNIT_OCCURENCES, "Number of 32-63 byte accesses.");
382	STAM_REG(pVM, &pPool->aStatMonitorRZSizes[18], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Size40+", STAMUNIT_OCCURENCES, "Number of 64+ byte accesses.");
383	STAM_REG(pVM, &pPool->aStatMonitorRZMisaligned[0], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Misaligned1", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 1.");
384	STAM_REG(pVM, &pPool->aStatMonitorRZMisaligned[1], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Misaligned2", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 2.");
385	STAM_REG(pVM, &pPool->aStatMonitorRZMisaligned[2], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Misaligned3", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 3.");
386	STAM_REG(pVM, &pPool->aStatMonitorRZMisaligned[3], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Misaligned4", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 4.");
387	STAM_REG(pVM, &pPool->aStatMonitorRZMisaligned[4], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Misaligned5", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 5.");
388	STAM_REG(pVM, &pPool->aStatMonitorRZMisaligned[5], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Misaligned6", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 6.");
389	STAM_REG(pVM, &pPool->aStatMonitorRZMisaligned[6], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/RZ/IEM/Misaligned7", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 7.");
390
391	STAM_REG(pVM, &pPool->StatMonitorRZFaultPT, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/Fault/PT", STAMUNIT_OCCURENCES, "Nr of handled PT faults.");
392	STAM_REG(pVM, &pPool->StatMonitorRZFaultPD, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/Fault/PD", STAMUNIT_OCCURENCES, "Nr of handled PD faults.");
393	STAM_REG(pVM, &pPool->StatMonitorRZFaultPDPT, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/Fault/PDPT", STAMUNIT_OCCURENCES, "Nr of handled PDPT faults.");
394	STAM_REG(pVM, &pPool->StatMonitorRZFaultPML4, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/RZ/Fault/PML4", STAMUNIT_OCCURENCES, "Nr of handled PML4 faults.");
395
396	STAM_REG(pVM, &pPool->StatMonitorR3, STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3", STAMUNIT_TICKS_PER_CALL, "Profiling the R3 access handler.");
397	STAM_REG(pVM, &pPool->StatMonitorR3FlushPage, STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/FlushPage", STAMUNIT_TICKS_PER_CALL, "Profiling the pgmPoolFlushPage calls made from the R3 access handler.");
398	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[0], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size01", STAMUNIT_OCCURENCES, "Number of 1 byte accesses (R3).");
399	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[1], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size02", STAMUNIT_OCCURENCES, "Number of 2 byte accesses (R3).");
400	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[2], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size03", STAMUNIT_OCCURENCES, "Number of 3 byte accesses (R3).");
401	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[3], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size04", STAMUNIT_OCCURENCES, "Number of 4 byte accesses (R3).");
402	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[4], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size05", STAMUNIT_OCCURENCES, "Number of 5 byte accesses (R3).");
403	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[5], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size06", STAMUNIT_OCCURENCES, "Number of 6 byte accesses (R3).");
404	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[6], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size07", STAMUNIT_OCCURENCES, "Number of 7 byte accesses (R3).");
405	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[7], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size08", STAMUNIT_OCCURENCES, "Number of 8 byte accesses (R3).");
406	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[8], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size09", STAMUNIT_OCCURENCES, "Number of 9 byte accesses (R3).");
407	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[9], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size0a", STAMUNIT_OCCURENCES, "Number of 10 byte accesses (R3).");
408	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[10], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size0b", STAMUNIT_OCCURENCES, "Number of 11 byte accesses (R3).");
409	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[11], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size0c", STAMUNIT_OCCURENCES, "Number of 12 byte accesses (R3).");
410	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[12], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size0d", STAMUNIT_OCCURENCES, "Number of 13 byte accesses (R3).");
411	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[13], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size0e", STAMUNIT_OCCURENCES, "Number of 14 byte accesses (R3).");
412	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[14], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size0f", STAMUNIT_OCCURENCES, "Number of 15 byte accesses (R3).");
413	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[15], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size10", STAMUNIT_OCCURENCES, "Number of 16 byte accesses (R3).");
414	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[16], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size11-2f", STAMUNIT_OCCURENCES, "Number of 17-31 byte accesses.");
415	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[17], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size20-3f", STAMUNIT_OCCURENCES, "Number of 32-63 byte accesses.");
416	STAM_REG(pVM, &pPool->aStatMonitorR3Sizes[18], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Size40+", STAMUNIT_OCCURENCES, "Number of 64+ byte accesses.");
417	STAM_REG(pVM, &pPool->aStatMonitorR3Misaligned[0], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Misaligned1", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 1 in R3.");
418	STAM_REG(pVM, &pPool->aStatMonitorR3Misaligned[1], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Misaligned2", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 2 in R3.");
419	STAM_REG(pVM, &pPool->aStatMonitorR3Misaligned[2], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Misaligned3", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 3 in R3.");
420	STAM_REG(pVM, &pPool->aStatMonitorR3Misaligned[3], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Misaligned4", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 4 in R3.");
421	STAM_REG(pVM, &pPool->aStatMonitorR3Misaligned[4], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Misaligned5", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 5 in R3.");
422	STAM_REG(pVM, &pPool->aStatMonitorR3Misaligned[5], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Misaligned6", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 6 in R3.");
423	STAM_REG(pVM, &pPool->aStatMonitorR3Misaligned[6], STAMTYPE_PROFILE, "/PGM/Pool/Monitor/R3/Misaligned7", STAMUNIT_OCCURENCES, "Number of misaligned access with offset 7 in R3.");
424
425	STAM_REG(pVM, &pPool->StatMonitorR3FaultPT, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/R3/Fault/PT", STAMUNIT_OCCURENCES, "Nr of handled PT faults.");
426	STAM_REG(pVM, &pPool->StatMonitorR3FaultPD, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/R3/Fault/PD", STAMUNIT_OCCURENCES, "Nr of handled PD faults.");
427	STAM_REG(pVM, &pPool->StatMonitorR3FaultPDPT, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/R3/Fault/PDPT", STAMUNIT_OCCURENCES, "Nr of handled PDPT faults.");
428	STAM_REG(pVM, &pPool->StatMonitorR3FaultPML4, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/R3/Fault/PML4", STAMUNIT_OCCURENCES, "Nr of handled PML4 faults.");
429
430	STAM_REG(pVM, &pPool->cModifiedPages, STAMTYPE_U16, "/PGM/Pool/Monitor/cModifiedPages", STAMUNIT_PAGES, "The current cModifiedPages value.");
431	STAM_REG(pVM, &pPool->cModifiedPagesHigh, STAMTYPE_U16_RESET, "/PGM/Pool/Monitor/cModifiedPagesHigh", STAMUNIT_PAGES, "The high watermark for cModifiedPages.");
432	STAM_REG(pVM, &pPool->StatResetDirtyPages, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/Dirty/Resets", STAMUNIT_OCCURENCES, "Times we've called pgmPoolResetDirtyPages (and there were dirty page).");
433	STAM_REG(pVM, &pPool->StatDirtyPage, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/Dirty/Pages", STAMUNIT_OCCURENCES, "Times we've called pgmPoolAddDirtyPage.");
434	STAM_REG(pVM, &pPool->StatDirtyPageDupFlush, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/Dirty/FlushDup", STAMUNIT_OCCURENCES, "Times we've had to flush duplicates for dirty page management.");
435	STAM_REG(pVM, &pPool->StatDirtyPageOverFlowFlush, STAMTYPE_COUNTER, "/PGM/Pool/Monitor/Dirty/FlushOverflow",STAMUNIT_OCCURENCES, "Times we've had to flush because of overflow.");
436	STAM_REG(pVM, &pPool->StatCacheHits, STAMTYPE_COUNTER, "/PGM/Pool/Cache/Hits", STAMUNIT_OCCURENCES, "The number of pgmPoolAlloc calls satisfied by the cache.");
437	STAM_REG(pVM, &pPool->StatCacheMisses, STAMTYPE_COUNTER, "/PGM/Pool/Cache/Misses", STAMUNIT_OCCURENCES, "The number of pgmPoolAlloc calls not statisfied by the cache.");
438	STAM_REG(pVM, &pPool->StatCacheKindMismatches, STAMTYPE_COUNTER, "/PGM/Pool/Cache/KindMismatches", STAMUNIT_OCCURENCES, "The number of shadow page kind mismatches. (Better be low, preferably 0!)");
439	STAM_REG(pVM, &pPool->StatCacheFreeUpOne, STAMTYPE_COUNTER, "/PGM/Pool/Cache/FreeUpOne", STAMUNIT_OCCURENCES, "The number of times the cache was asked to free up a page.");
440	STAM_REG(pVM, &pPool->StatCacheCacheable, STAMTYPE_COUNTER, "/PGM/Pool/Cache/Cacheable", STAMUNIT_OCCURENCES, "The number of cacheable allocations.");
441	STAM_REG(pVM, &pPool->StatCacheUncacheable, STAMTYPE_COUNTER, "/PGM/Pool/Cache/Uncacheable", STAMUNIT_OCCURENCES, "The number of uncacheable allocations.");
442	#endif /* VBOX_WITH_STATISTICS */
443
444	#ifdef VBOX_WITH_DEBUGGER
445	/*
446	* Debugger commands.
447	*/
448	static bool s_fRegisteredCmds = false;
449	if (!s_fRegisteredCmds)
450	{
451	rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
452	if (RT_SUCCESS(rc))
453	s_fRegisteredCmds = true;
454	}
455	#endif
456
457	return VINF_SUCCESS;
458	}
459
460
461	/**
462	* Relocate the page pool data.
463	*
464	* @param pVM The cross context VM structure.
465	*/
466	void pgmR3PoolRelocate(PVM pVM)
467	{
468	pVM->pgm.s.pPoolRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pPoolR3);
469	pVM->pgm.s.pPoolR3->pVMRC = pVM->pVMRC;
470	pVM->pgm.s.pPoolR3->paUsersRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pPoolR3->paUsersR3);
471	pVM->pgm.s.pPoolR3->paPhysExtsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pPoolR3->paPhysExtsR3);
472	}
473
474
475	/**
476	* Grows the shadow page pool.
477	*
478	* I.e. adds more pages to it, assuming that hasn't reached cMaxPages yet.
479	*
480	* @returns VBox status code.
481	* @param pVM The cross context VM structure.
482	*/
483	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM)
484	{
485	PPGMPOOL pPool = pVM->pgm.s.pPoolR3;
486	AssertReturn(pPool->cCurPages < pPool->cMaxPages, VERR_PGM_POOL_MAXED_OUT_ALREADY);
487
488	/* With 32-bit guests and no EPT, the CR3 limits the root pages to low
489	(below 4 GB) memory. */
490	/** @todo change the pool to handle ROOT page allocations specially when
491	* required. */
492	bool fCanUseHighMemory = HMIsNestedPagingActive(pVM)
493	&& HMIsVmxActive(pVM);
494
495	pgmLock(pVM);
496
497	/*
498	* How much to grow it by?
499	*/
500	uint32_t cPages = pPool->cMaxPages - pPool->cCurPages;
501	cPages = RT_MIN(PGMPOOL_CFG_MAX_GROW, cPages);
502	LogFlow(("PGMR3PoolGrow: Growing the pool by %d (%#x) pages. fCanUseHighMemory=%RTbool\n", cPages, cPages, fCanUseHighMemory));
503
504	for (unsigned i = pPool->cCurPages; cPages-- > 0; i++)
505	{
506	PPGMPOOLPAGE pPage = &pPool->aPages[i];
507
508	if (fCanUseHighMemory)
509	pPage->pvPageR3 = MMR3PageAlloc(pVM);
510	else
511	pPage->pvPageR3 = MMR3PageAllocLow(pVM);
512	if (!pPage->pvPageR3)
513	{
514	Log(("We're out of memory!! i=%d fCanUseHighMemory=%RTbool\n", i, fCanUseHighMemory));
515	pgmUnlock(pVM);
516	return i ? VINF_SUCCESS : VERR_NO_PAGE_MEMORY;
517	}
518	pPage->Core.Key = MMPage2Phys(pVM, pPage->pvPageR3);
519	AssertFatal(pPage->Core.Key < _4G \|\| fCanUseHighMemory);
520	pPage->GCPhys = NIL_RTGCPHYS;
521	pPage->enmKind = PGMPOOLKIND_FREE;
522	pPage->idx = pPage - &pPool->aPages[0];
523	LogFlow(("PGMR3PoolGrow: insert page #%#x - %RHp\n", pPage->idx, pPage->Core.Key));
524	pPage->iNext = pPool->iFreeHead;
525	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
526	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
527	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
528	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
529	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
530	pPage->iAgeNext = NIL_PGMPOOL_IDX;
531	pPage->iAgePrev = NIL_PGMPOOL_IDX;
532	/* commit it */
533	bool fRc = RTAvloHCPhysInsert(&pPool->HCPhysTree, &pPage->Core); Assert(fRc); NOREF(fRc);
534	pPool->iFreeHead = i;
535	pPool->cCurPages = i + 1;
536	}
537
538	pgmUnlock(pVM);
539	Assert(pPool->cCurPages <= pPool->cMaxPages);
540	return VINF_SUCCESS;
541	}
542
543
544	/**
545	* Rendezvous callback used by pgmR3PoolClearAll that clears all shadow pages
546	* and all modification counters.
547	*
548	* This is only called on one of the EMTs while the other ones are waiting for
549	* it to complete this function.
550	*
551	* @returns VINF_SUCCESS (VBox strict status code).
552	* @param pVM The cross context VM structure.
553	* @param pVCpu The cross context virtual CPU structure of the calling EMT. Unused.
554	* @param fpvFlushRemTlb When not NULL, we'll flush the REM TLB as well.
555	* (This is the pvUser, so it has to be void *.)
556	*
557	*/
558	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTlb)
559	{
560	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
561	STAM_PROFILE_START(&pPool->StatClearAll, c);
562	NOREF(pVCpu);
563
564	pgmLock(pVM);
565	Log(("pgmR3PoolClearAllRendezvous: cUsedPages=%d fpvFlushRemTlb=%RTbool\n", pPool->cUsedPages, !!fpvFlushRemTlb));
566
567	/*
568	* Iterate all the pages until we've encountered all that are in use.
569	* This is a simple but not quite optimal solution.
570	*/
571	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
572	unsigned cLeft = pPool->cUsedPages;
573	uint32_t iPage = pPool->cCurPages;
574	while (--iPage >= PGMPOOL_IDX_FIRST)
575	{
576	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
577	if (pPage->GCPhys != NIL_RTGCPHYS)
578	{
579	switch (pPage->enmKind)
580	{
581	/*
582	* We only care about shadow page tables that reference physical memory
583	*/
584	#ifdef PGM_WITH_LARGE_PAGES
585	case PGMPOOLKIND_EPT_PD_FOR_PHYS: /* Large pages reference 2 MB of physical memory, so we must clear them. */
586	if (pPage->cPresent)
587	{
588	PX86PDPAE pShwPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pPool->CTX_SUFF(pVM), pVCpu, pPage);
589	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
590	{
591	if ( pShwPD->a[i].n.u1Present
592	&& pShwPD->a[i].b.u1Size)
593	{
594	Assert(!(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING));
595	pShwPD->a[i].u = 0;
596	Assert(pPage->cPresent);
597	pPage->cPresent--;
598	}
599	}
600	if (pPage->cPresent == 0)
601	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
602	}
603	goto default_case;
604
605	case PGMPOOLKIND_PAE_PD_PHYS: /* Large pages reference 2 MB of physical memory, so we must clear them. */
606	if (pPage->cPresent)
607	{
608	PEPTPD pShwPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pPool->CTX_SUFF(pVM), pVCpu, pPage);
609	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
610	{
611	Assert((pShwPD->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
612	if ( pShwPD->a[i].n.u1Present
613	&& pShwPD->a[i].b.u1Size)
614	{
615	Assert(!(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING));
616	pShwPD->a[i].u = 0;
617	Assert(pPage->cPresent);
618	pPage->cPresent--;
619	}
620	}
621	if (pPage->cPresent == 0)
622	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
623	}
624	goto default_case;
625	#endif /* PGM_WITH_LARGE_PAGES */
626
627	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
628	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
629	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
630	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
631	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
632	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
633	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
634	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
635	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
636	{
637	if (pPage->cPresent)
638	{
639	void *pvShw = PGMPOOL_PAGE_2_PTR_V2(pPool->CTX_SUFF(pVM), pVCpu, pPage);
640	STAM_PROFILE_START(&pPool->StatZeroPage, z);
641	#if 0
642	/* Useful check for leaking references; very expensive though. */
643	switch (pPage->enmKind)
644	{
645	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
646	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
647	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
648	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
649	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
650	{
651	bool fFoundFirst = false;
652	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)pvShw;
653	for (unsigned ptIndex = 0; ptIndex < RT_ELEMENTS(pPT->a); ptIndex++)
654	{
655	if (pPT->a[ptIndex].u)
656	{
657	if (!fFoundFirst)
658	{
659	AssertFatalMsg(pPage->iFirstPresent <= ptIndex, ("ptIndex = %d first present = %d\n", ptIndex, pPage->iFirstPresent));
660	if (pPage->iFirstPresent != ptIndex)
661	Log(("ptIndex = %d first present = %d\n", ptIndex, pPage->iFirstPresent));
662	fFoundFirst = true;
663	}
664	if (PGMSHWPTEPAE_IS_P(pPT->a[ptIndex]))
665	{
666	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pPT->a[ptIndex]), NIL_RTGCPHYS);
667	if (pPage->iFirstPresent == ptIndex)
668	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
669	}
670	}
671	}
672	AssertFatalMsg(pPage->cPresent == 0, ("cPresent = %d pPage = %RGv\n", pPage->cPresent, pPage->GCPhys));
673	break;
674	}
675	default:
676	break;
677	}
678	#endif
679	ASMMemZeroPage(pvShw);
680	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
681	pPage->cPresent = 0;
682	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
683	}
684	}
685	RT_FALL_THRU();
686	#ifdef PGM_WITH_LARGE_PAGES
687	default_case:
688	#endif
689	default:
690	Assert(!pPage->cModifications \|\| ++cModifiedPages);
691	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
692	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
693	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
694	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
695	pPage->cModifications = 0;
696	break;
697
698	}
699	if (!--cLeft)
700	break;
701	}
702	}
703
704	#ifndef DEBUG_michael
705	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
706	#endif
707	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
708	pPool->cModifiedPages = 0;
709
710	/*
711	* Clear all the GCPhys links and rebuild the phys ext free list.
712	*/
713	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRangesX);
714	pRam;
715	pRam = pRam->CTX_SUFF(pNext))
716	{
717	iPage = pRam->cb >> PAGE_SHIFT;
718	while (iPage-- > 0)
719	PGM_PAGE_SET_TRACKING(pVM, &pRam->aPages[iPage], 0);
720	}
721
722	pPool->iPhysExtFreeHead = 0;
723	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
724	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
725	for (unsigned i = 0; i < cMaxPhysExts; i++)
726	{
727	paPhysExts[i].iNext = i + 1;
728	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
729	paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
730	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
731	paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
732	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
733	paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
734	}
735	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
736
737
738	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
739	/* Reset all dirty pages to reactivate the page monitoring. */
740	/* Note: we must do this after clearing all page references and shadow page tables as there might be stale references to
741	* recently removed MMIO ranges around that might otherwise end up asserting in pgmPoolTracDerefGCPhysHint
742	*/
743	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
744	{
745	PPGMPOOLPAGE pPage;
746	unsigned idxPage;
747
748	if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
749	continue;
750
751	idxPage = pPool->aDirtyPages[i].uIdx;
752	AssertRelease(idxPage != NIL_PGMPOOL_IDX);
753	pPage = &pPool->aPages[idxPage];
754	Assert(pPage->idx == idxPage);
755	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
756
757	AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, i));
758
759	Log(("Reactivate dirty page %RGp\n", pPage->GCPhys));
760
761	/* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
762	int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK);
763	AssertRCSuccess(rc);
764	pPage->fDirty = false;
765
766	pPool->aDirtyPages[i].uIdx = NIL_PGMPOOL_IDX;
767	}
768
769	/* Clear all dirty pages. */
770	pPool->idxFreeDirtyPage = 0;
771	pPool->cDirtyPages = 0;
772	#endif
773
774	/* Clear the PGM_SYNC_CLEAR_PGM_POOL flag on all VCPUs to prevent redundant flushes. */
775	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
776	pVM->aCpus[idCpu].pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
777
778	/* Flush job finished. */
779	VM_FF_CLEAR(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
780	pPool->cPresent = 0;
781	pgmUnlock(pVM);
782
783	PGM_INVL_ALL_VCPU_TLBS(pVM);
784
785	if (fpvFlushRemTlb)
786	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
787	CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
788
789	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
790	return VINF_SUCCESS;
791	}
792
793
794	/**
795	* Clears the shadow page pool.
796	*
797	* @param pVM The cross context VM structure.
798	* @param fFlushRemTlb When set, the REM TLB is scheduled for flushing as
799	* well.
800	*/
801	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb)
802	{
803	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmR3PoolClearAllRendezvous, &fFlushRemTlb);
804	AssertRC(rc);
805	}
806
807
808	/**
809	* Protect all pgm pool page table entries to monitor writes
810	*
811	* @param pVM The cross context VM structure.
812	*
813	* @remarks ASSUMES the caller will flush all TLBs!!
814	*/
815	void pgmR3PoolWriteProtectPages(PVM pVM)
816	{
817	PGM_LOCK_ASSERT_OWNER(pVM);
818	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
819	unsigned cLeft = pPool->cUsedPages;
820	unsigned iPage = pPool->cCurPages;
821	while (--iPage >= PGMPOOL_IDX_FIRST)
822	{
823	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
824	if ( pPage->GCPhys != NIL_RTGCPHYS
825	&& pPage->cPresent)
826	{
827	union
828	{
829	void *pv;
830	PX86PT pPT;
831	PPGMSHWPTPAE pPTPae;
832	PEPTPT pPTEpt;
833	} uShw;
834	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
835
836	switch (pPage->enmKind)
837	{
838	/*
839	* We only care about shadow page tables.
840	*/
841	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
842	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
843	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
844	for (unsigned iShw = 0; iShw < RT_ELEMENTS(uShw.pPT->a); iShw++)
845	{
846	if (uShw.pPT->a[iShw].n.u1Present)
847	uShw.pPT->a[iShw].n.u1Write = 0;
848	}
849	break;
850
851	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
852	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
853	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
854	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
855	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
856	for (unsigned iShw = 0; iShw < RT_ELEMENTS(uShw.pPTPae->a); iShw++)
857	{
858	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
859	PGMSHWPTEPAE_SET_RO(uShw.pPTPae->a[iShw]);
860	}
861	break;
862
863	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
864	for (unsigned iShw = 0; iShw < RT_ELEMENTS(uShw.pPTEpt->a); iShw++)
865	{
866	if (uShw.pPTEpt->a[iShw].n.u1Present)
867	uShw.pPTEpt->a[iShw].n.u1Write = 0;
868	}
869	break;
870
871	default:
872	break;
873	}
874	if (!--cLeft)
875	break;
876	}
877	}
878	}
879
880	#ifdef VBOX_WITH_DEBUGGER
881	/**
882	* @callback_method_impl{FNDBGCCMD, The '.pgmpoolcheck' command.}
883	*/
884	static DECLCALLBACK(int) pgmR3PoolCmdCheck(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
885	{
886	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
887	PVM pVM = pUVM->pVM;
888	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
889	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, -1, cArgs == 0);
890	uint32_t cErrors = 0;
891	NOREF(paArgs);
892
893	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
894	for (unsigned i = 0; i < pPool->cCurPages; i++)
895	{
896	PPGMPOOLPAGE pPage = &pPool->aPages[i];
897	bool fFirstMsg = true;
898
899	/** @todo cover other paging modes too. */
900	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
901	{
902	PPGMSHWPTPAE pShwPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
903	{
904	PX86PTPAE pGstPT;
905	PGMPAGEMAPLOCK LockPage;
906	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, pPage->GCPhys, (const void **)&pGstPT, &LockPage); AssertReleaseRC(rc);
907
908	/* Check if any PTEs are out of sync. */
909	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
910	{
911	if (PGMSHWPTEPAE_IS_P(pShwPT->a[j]))
912	{
913	RTHCPHYS HCPhys = NIL_RTHCPHYS;
914	rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[j].u & X86_PTE_PAE_PG_MASK, &HCPhys);
915	if ( rc != VINF_SUCCESS
916	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[j]) != HCPhys)
917	{
918	if (fFirstMsg)
919	{
920	DBGCCmdHlpPrintf(pCmdHlp, "Check pool page %RGp\n", pPage->GCPhys);
921	fFirstMsg = false;
922	}
923	DBGCCmdHlpPrintf(pCmdHlp, "Mismatch HCPhys: rc=%Rrc idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, j, pGstPT->a[j].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), HCPhys);
924	cErrors++;
925	}
926	else if ( PGMSHWPTEPAE_IS_RW(pShwPT->a[j])
927	&& !pGstPT->a[j].n.u1Write)
928	{
929	if (fFirstMsg)
930	{
931	DBGCCmdHlpPrintf(pCmdHlp, "Check pool page %RGp\n", pPage->GCPhys);
932	fFirstMsg = false;
933	}
934	DBGCCmdHlpPrintf(pCmdHlp, "Mismatch r/w gst/shw: idx=%d guest %RX64 shw=%RX64 vs %RHp\n", j, pGstPT->a[j].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), HCPhys);
935	cErrors++;
936	}
937	}
938	}
939	PGMPhysReleasePageMappingLock(pVM, &LockPage);
940	}
941
942	/* Make sure this page table can't be written to from any shadow mapping. */
943	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
944	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pPage->GCPhys, &HCPhysPT);
945	AssertMsgRC(rc, ("PGMPhysGCPhys2HCPhys failed with rc=%d for %RGp\n", rc, pPage->GCPhys));
946	if (rc == VINF_SUCCESS)
947	{
948	for (unsigned j = 0; j < pPool->cCurPages; j++)
949	{
950	PPGMPOOLPAGE pTempPage = &pPool->aPages[j];
951
952	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
953	{
954	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pTempPage);
955
956	for (unsigned k = 0; k < RT_ELEMENTS(pShwPT->a); k++)
957	{
958	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[k])
959	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
960	&& !pPage->fDirty
961	# endif
962	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[k]) == HCPhysPT)
963	{
964	if (fFirstMsg)
965	{
966	DBGCCmdHlpPrintf(pCmdHlp, "Check pool page %RGp\n", pPage->GCPhys);
967	fFirstMsg = false;
968	}
969	DBGCCmdHlpPrintf(pCmdHlp, "Mismatch: r/w: GCPhys=%RGp idx=%d shw %RX64 %RX64\n", pTempPage->GCPhys, k, PGMSHWPTEPAE_GET_LOG(pShwPT->a[k]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[k]));
970	cErrors++;
971	}
972	}
973	}
974	}
975	}
976	}
977	}
978	if (cErrors > 0)
979	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Found %#x errors", cErrors);
980	return VINF_SUCCESS;
981	}
982	#endif /* VBOX_WITH_DEBUGGER */

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMPool.cpp@ 74168

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