PGMShw.h@ 60682

Last change on this file since 60682 was 58126, checked in by vboxsync, 9 years ago
VMM: Fixed almost all the Doxygen warnings.
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1	/* $Id: PGMShw.h 58126 2015-10-08 20:59:48Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager / Monitor, Shadow Paging Template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Defined Constants And Macros *
20	*******************************************************************************/
21	#undef SHWPT
22	#undef PSHWPT
23	#undef SHWPTE
24	#undef PSHWPTE
25	#undef SHWPD
26	#undef PSHWPD
27	#undef SHWPDE
28	#undef PSHWPDE
29	#undef SHW_PDE_PG_MASK
30	#undef SHW_PD_SHIFT
31	#undef SHW_PD_MASK
32	#undef SHW_PTE_PG_MASK
33	#undef SHW_PT_SHIFT
34	#undef SHW_PT_MASK
35	#undef SHW_TOTAL_PD_ENTRIES
36	#undef SHW_PDPT_SHIFT
37	#undef SHW_PDPT_MASK
38	#undef SHW_PDPE_PG_MASK
39
40	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
41	# define SHWPT X86PT
42	# define PSHWPT PX86PT
43	# define SHWPTE X86PTE
44	# define PSHWPTE PX86PTE
45	# define SHWPD X86PD
46	# define PSHWPD PX86PD
47	# define SHWPDE X86PDE
48	# define PSHWPDE PX86PDE
49	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
50	# define SHW_PD_SHIFT X86_PD_SHIFT
51	# define SHW_PD_MASK X86_PD_MASK
52	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
53	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
54	# define SHW_PT_SHIFT X86_PT_SHIFT
55	# define SHW_PT_MASK X86_PT_MASK
56
57	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
58	# define SHWPT EPTPT
59	# define PSHWPT PEPTPT
60	# define SHWPTE EPTPTE
61	# define PSHWPTE PEPTPTE
62	# define SHWPD EPTPD
63	# define PSHWPD PEPTPD
64	# define SHWPDE EPTPDE
65	# define PSHWPDE PEPTPDE
66	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
67	# define SHW_PD_SHIFT EPT_PD_SHIFT
68	# define SHW_PD_MASK EPT_PD_MASK
69	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
70	# define SHW_PT_SHIFT EPT_PT_SHIFT
71	# define SHW_PT_MASK EPT_PT_MASK
72	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
73	# define SHW_PDPT_MASK EPT_PDPT_MASK
74	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
75	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
76
77	#else
78	# define SHWPT PGMSHWPTPAE
79	# define PSHWPT PPGMSHWPTPAE
80	# define SHWPTE PGMSHWPTEPAE
81	# define PSHWPTE PPGMSHWPTEPAE
82	# define SHWPD X86PDPAE
83	# define PSHWPD PX86PDPAE
84	# define SHWPDE X86PDEPAE
85	# define PSHWPDE PX86PDEPAE
86	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
87	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
88	# define SHW_PD_MASK X86_PD_PAE_MASK
89	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
90	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
91	# define SHW_PT_MASK X86_PT_PAE_MASK
92
93	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
94	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
95	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
96	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
97	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
98
99	# else /* 32 bits PAE mode */
100	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
101	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
102	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
103	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
104	# endif
105	#endif
106
107
108	/*******************************************************************************
109	* Internal Functions *
110	*******************************************************************************/
111	RT_C_DECLS_BEGIN
112	/* r3 */
113	PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0);
114	PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
115	PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
116	PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
117
118	/* all */
119	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
120	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
121	RT_C_DECLS_END
122
123
124	/**
125	* Initializes the guest bit of the paging mode data.
126	*
127	* @returns VBox status code.
128	* @param pVM The cross context VM structure.
129	* @param pModeData The pointer table to initialize (our members only).
130	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
131	* This is used early in the init process to avoid trouble with PDM
132	* not being initialized yet.
133	*/
134	PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0)
135	{
136	Assert(pModeData->uShwType == PGM_SHW_TYPE \|\| pModeData->uShwType == PGM_TYPE_NESTED);
137
138	/* Ring-3 */
139	pModeData->pfnR3ShwRelocate = PGM_SHW_NAME(Relocate);
140	pModeData->pfnR3ShwExit = PGM_SHW_NAME(Exit);
141	pModeData->pfnR3ShwGetPage = PGM_SHW_NAME(GetPage);
142	pModeData->pfnR3ShwModifyPage = PGM_SHW_NAME(ModifyPage);
143
144	if (fResolveGCAndR0)
145	{
146	int rc;
147
148	if (!HMIsEnabled(pVM))
149	{
150	#if PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT /* No AMD64 for traditional virtualization, only VT-x and AMD-V. */
151	/* GC */
152	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(GetPage), &pModeData->pfnRCShwGetPage);
153	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(GetPage), rc), rc);
154	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(ModifyPage), &pModeData->pfnRCShwModifyPage);
155	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(ModifyPage), rc), rc);
156	#endif /* Not AMD64 shadow paging. */
157	}
158
159	/* Ring-0 */
160	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(GetPage), &pModeData->pfnR0ShwGetPage);
161	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(GetPage), rc), rc);
162	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(ModifyPage), &pModeData->pfnR0ShwModifyPage);
163	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(ModifyPage), rc), rc);
164	}
165	return VINF_SUCCESS;
166	}
167
168	/**
169	* Enters the shadow mode.
170	*
171	* @returns VBox status code.
172	* @param pVCpu The cross context virtual CPU structure.
173	* @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
174	*/
175	PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
176	{
177	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
178
179	# if PGM_SHW_TYPE == PGM_TYPE_NESTED && HC_ARCH_BITS == 32
180	/* Must distinguish between 32 and 64 bits guest paging modes as we'll use
181	a different shadow paging root/mode in both cases. */
182	RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
183	# else
184	RTGCPHYS GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
185	# endif
186	PPGMPOOLPAGE pNewShwPageCR3;
187	PVM pVM = pVCpu->pVMR3;
188
189	Assert(HMIsNestedPagingActive(pVM) == pVM->pgm.s.fNestedPaging);
190	Assert(pVM->pgm.s.fNestedPaging);
191	Assert(!pVCpu->pgm.s.pShwPageCR3R3);
192
193	pgmLock(pVM);
194
195	int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
196	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
197	&pNewShwPageCR3);
198	AssertFatalRC(rc);
199
200	pVCpu->pgm.s.pShwPageCR3R3 = pNewShwPageCR3;
201
202	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.pShwPageCR3R3);
203	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.pShwPageCR3R3);
204
205	pgmUnlock(pVM);
206
207	Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
208	#else
209	NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
210	#endif
211	return VINF_SUCCESS;
212	}
213
214
215	/**
216	* Relocate any GC pointers related to shadow mode paging.
217	*
218	* @returns VBox status code.
219	* @param pVCpu The cross context virtual CPU structure.
220	* @param offDelta The relocation offset.
221	*/
222	PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
223	{
224	pVCpu->pgm.s.pShwPageCR3RC += offDelta;
225	return VINF_SUCCESS;
226	}
227
228
229	/**
230	* Exits the shadow mode.
231	*
232	* @returns VBox status code.
233	* @param pVCpu The cross context virtual CPU structure.
234	*/
235	PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu)
236	{
237	PVM pVM = pVCpu->pVMR3;
238
239	if ( ( pVCpu->pgm.s.enmShadowMode == PGMMODE_NESTED
240	\|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT)
241	&& pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
242	{
243	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
244
245	pgmLock(pVM);
246
247	/* Do not unlock this page as we have two of them floating around in the 32-bit host & 64-bit guest case.
248	* We currently assert when you try to free one of them; don't bother to really allow this.
249	*
250	* Note that this is two nested paging root pages max. This isn't a leak. They are reused.
251	*/
252	/* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
253
254	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
255	pVCpu->pgm.s.pShwPageCR3R3 = 0;
256	pVCpu->pgm.s.pShwPageCR3R0 = 0;
257	pVCpu->pgm.s.pShwPageCR3RC = 0;
258
259	pgmUnlock(pVM);
260
261	Log(("Leave nested shadow paging mode\n"));
262	}
263	return VINF_SUCCESS;
264	}
265

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMShw.h@ 60682

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