PGMShw.h@ 44397

Last change on this file since 44397 was 43387, checked in by vboxsync, 12 years ago
VMM: HM cleanup.
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1	/* $Id: PGMShw.h 43387 2012-09-21 09:40:25Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager / Monitor, Shadow Paging Template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Defined Constants And Macros *
20	*******************************************************************************/
21	#undef SHWPT
22	#undef PSHWPT
23	#undef SHWPTE
24	#undef PSHWPTE
25	#undef SHWPD
26	#undef PSHWPD
27	#undef SHWPDE
28	#undef PSHWPDE
29	#undef SHW_PDE_PG_MASK
30	#undef SHW_PD_SHIFT
31	#undef SHW_PD_MASK
32	#undef SHW_PTE_PG_MASK
33	#undef SHW_PT_SHIFT
34	#undef SHW_PT_MASK
35	#undef SHW_TOTAL_PD_ENTRIES
36	#undef SHW_PDPT_SHIFT
37	#undef SHW_PDPT_MASK
38	#undef SHW_PDPE_PG_MASK
39	#undef SHW_POOL_ROOT_IDX
40
41	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
42	# define SHWPT X86PT
43	# define PSHWPT PX86PT
44	# define SHWPTE X86PTE
45	# define PSHWPTE PX86PTE
46	# define SHWPD X86PD
47	# define PSHWPD PX86PD
48	# define SHWPDE X86PDE
49	# define PSHWPDE PX86PDE
50	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
51	# define SHW_PD_SHIFT X86_PD_SHIFT
52	# define SHW_PD_MASK X86_PD_MASK
53	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
54	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
55	# define SHW_PT_SHIFT X86_PT_SHIFT
56	# define SHW_PT_MASK X86_PT_MASK
57	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
58
59	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
60	# define SHWPT EPTPT
61	# define PSHWPT PEPTPT
62	# define SHWPTE EPTPTE
63	# define PSHWPTE PEPTPTE
64	# define SHWPD EPTPD
65	# define PSHWPD PEPTPD
66	# define SHWPDE EPTPDE
67	# define PSHWPDE PEPTPDE
68	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
69	# define SHW_PD_SHIFT EPT_PD_SHIFT
70	# define SHW_PD_MASK EPT_PD_MASK
71	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
72	# define SHW_PT_SHIFT EPT_PT_SHIFT
73	# define SHW_PT_MASK EPT_PT_MASK
74	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
75	# define SHW_PDPT_MASK EPT_PDPT_MASK
76	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
77	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
78	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
79
80	#else
81	# define SHWPT PGMSHWPTPAE
82	# define PSHWPT PPGMSHWPTPAE
83	# define SHWPTE PGMSHWPTEPAE
84	# define PSHWPTE PPGMSHWPTEPAE
85	# define SHWPD X86PDPAE
86	# define PSHWPD PX86PDPAE
87	# define SHWPDE X86PDEPAE
88	# define PSHWPDE PX86PDEPAE
89	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
90	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
91	# define SHW_PD_MASK X86_PD_PAE_MASK
92	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
93	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
94	# define SHW_PT_MASK X86_PT_PAE_MASK
95
96	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
97	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
98	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
99	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
100	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
101	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_AMD64_CR3
102
103	# else /* 32 bits PAE mode */
104	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
105	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
106	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
107	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
108	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PDPT
109	# endif
110	#endif
111
112
113	/*******************************************************************************
114	* Internal Functions *
115	*******************************************************************************/
116	RT_C_DECLS_BEGIN
117	/* r3 */
118	PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0);
119	PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
120	PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
121	PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
122
123	/* all */
124	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
125	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
126	RT_C_DECLS_END
127
128
129	/**
130	* Initializes the guest bit of the paging mode data.
131	*
132	* @returns VBox status code.
133	* @param pVM Pointer to the VM.
134	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
135	* This is used early in the init process to avoid trouble with PDM
136	* not being initialized yet.
137	*/
138	PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0)
139	{
140	Assert(pModeData->uShwType == PGM_SHW_TYPE \|\| pModeData->uShwType == PGM_TYPE_NESTED);
141
142	/* Ring-3 */
143	pModeData->pfnR3ShwRelocate = PGM_SHW_NAME(Relocate);
144	pModeData->pfnR3ShwExit = PGM_SHW_NAME(Exit);
145	pModeData->pfnR3ShwGetPage = PGM_SHW_NAME(GetPage);
146	pModeData->pfnR3ShwModifyPage = PGM_SHW_NAME(ModifyPage);
147
148	if (fResolveGCAndR0)
149	{
150	int rc;
151
152	#if PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT /* No AMD64 for traditional virtualization, only VT-x and AMD-V. */
153	/* GC */
154	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(GetPage), &pModeData->pfnRCShwGetPage);
155	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(GetPage), rc), rc);
156	rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(ModifyPage), &pModeData->pfnRCShwModifyPage);
157	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(ModifyPage), rc), rc);
158	#endif /* Not AMD64 shadow paging. */
159
160	/* Ring-0 */
161	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(GetPage), &pModeData->pfnR0ShwGetPage);
162	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(GetPage), rc), rc);
163	rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(ModifyPage), &pModeData->pfnR0ShwModifyPage);
164	AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(ModifyPage), rc), rc);
165	}
166	return VINF_SUCCESS;
167	}
168
169	/**
170	* Enters the shadow mode.
171	*
172	* @returns VBox status code.
173	* @param pVCpu Pointer to the VMCPU.
174	* @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
175	*/
176	PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
177	{
178	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
179
180	# if PGM_SHW_TYPE == PGM_TYPE_NESTED && HC_ARCH_BITS == 32
181	/* Must distinguish between 32 and 64 bits guest paging modes as we'll use
182	a different shadow paging root/mode in both cases. */
183	RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
184	# else
185	RTGCPHYS GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
186	# endif
187	PPGMPOOLPAGE pNewShwPageCR3;
188	PVM pVM = pVCpu->pVMR3;
189
190	Assert(HMIsNestedPagingActive(pVM) == pVM->pgm.s.fNestedPaging);
191	Assert(pVM->pgm.s.fNestedPaging);
192	Assert(!pVCpu->pgm.s.pShwPageCR3R3);
193
194	pgmLock(pVM);
195
196	int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
197	PGMPOOL_IDX_NESTED_ROOT, GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/,
198	&pNewShwPageCR3);
199	AssertFatalRC(rc);
200
201	pVCpu->pgm.s.iShwUser = PGMPOOL_IDX_NESTED_ROOT;
202	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
203	pVCpu->pgm.s.pShwPageCR3R3 = pNewShwPageCR3;
204
205	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.pShwPageCR3R3);
206	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.pShwPageCR3R3);
207
208	pgmUnlock(pVM);
209
210	Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
211	#else
212	NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
213	#endif
214	return VINF_SUCCESS;
215	}
216
217
218	/**
219	* Relocate any GC pointers related to shadow mode paging.
220	*
221	* @returns VBox status code.
222	* @param pVCpu Pointer to the VMCPU.
223	* @param offDelta The relocation offset.
224	*/
225	PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
226	{
227	pVCpu->pgm.s.pShwPageCR3RC += offDelta;
228	return VINF_SUCCESS;
229	}
230
231
232	/**
233	* Exits the shadow mode.
234	*
235	* @returns VBox status code.
236	* @param pVCpu Pointer to the VMCPU.
237	*/
238	PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu)
239	{
240	PVM pVM = pVCpu->pVMR3;
241
242	if ( ( pVCpu->pgm.s.enmShadowMode == PGMMODE_NESTED
243	\|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT)
244	&& pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
245	{
246	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
247
248	Assert(pVCpu->pgm.s.iShwUser == PGMPOOL_IDX_NESTED_ROOT);
249
250	pgmLock(pVM);
251
252	/* Do not unlock this page as we have two of them floating around in the 32-bit host & 64-bit guest case.
253	* We currently assert when you try to free one of them; don't bother to really allow this.
254	*
255	* Note that this is two nested paging root pages max. This isn't a leak. They are reused.
256	*/
257	/* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
258
259	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
260	pVCpu->pgm.s.pShwPageCR3R3 = 0;
261	pVCpu->pgm.s.pShwPageCR3R0 = 0;
262	pVCpu->pgm.s.pShwPageCR3RC = 0;
263	pVCpu->pgm.s.iShwUser = 0;
264	pVCpu->pgm.s.iShwUserTable = 0;
265
266	pgmUnlock(pVM);
267
268	Log(("Leave nested shadow paging mode\n"));
269	}
270	return VINF_SUCCESS;
271	}
272

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMShw.h@ 44397

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