VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PGMShw.h@ 70520

Last change on this file since 70520 was 69474, checked in by vboxsync, 7 years ago

*: scm updates - header files should have 'svn:keywords=Id Revision' too (doesn't mean they have to use them).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 10.0 KB
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1/* $Id: PGMShw.h 69474 2017-10-28 13:12:06Z vboxsync $ */
2/** @file
3 * VBox - Page Manager / Monitor, Shadow Paging Template.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Defined Constants And Macros *
20*******************************************************************************/
21#undef SHWPT
22#undef PSHWPT
23#undef SHWPTE
24#undef PSHWPTE
25#undef SHWPD
26#undef PSHWPD
27#undef SHWPDE
28#undef PSHWPDE
29#undef SHW_PDE_PG_MASK
30#undef SHW_PD_SHIFT
31#undef SHW_PD_MASK
32#undef SHW_PTE_PG_MASK
33#undef SHW_PT_SHIFT
34#undef SHW_PT_MASK
35#undef SHW_TOTAL_PD_ENTRIES
36#undef SHW_PDPT_SHIFT
37#undef SHW_PDPT_MASK
38#undef SHW_PDPE_PG_MASK
39
40#if PGM_SHW_TYPE == PGM_TYPE_32BIT
41# define SHWPT X86PT
42# define PSHWPT PX86PT
43# define SHWPTE X86PTE
44# define PSHWPTE PX86PTE
45# define SHWPD X86PD
46# define PSHWPD PX86PD
47# define SHWPDE X86PDE
48# define PSHWPDE PX86PDE
49# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
50# define SHW_PD_SHIFT X86_PD_SHIFT
51# define SHW_PD_MASK X86_PD_MASK
52# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
53# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
54# define SHW_PT_SHIFT X86_PT_SHIFT
55# define SHW_PT_MASK X86_PT_MASK
56
57#elif PGM_SHW_TYPE == PGM_TYPE_EPT
58# define SHWPT EPTPT
59# define PSHWPT PEPTPT
60# define SHWPTE EPTPTE
61# define PSHWPTE PEPTPTE
62# define SHWPD EPTPD
63# define PSHWPD PEPTPD
64# define SHWPDE EPTPDE
65# define PSHWPDE PEPTPDE
66# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
67# define SHW_PD_SHIFT EPT_PD_SHIFT
68# define SHW_PD_MASK EPT_PD_MASK
69# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
70# define SHW_PT_SHIFT EPT_PT_SHIFT
71# define SHW_PT_MASK EPT_PT_MASK
72# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
73# define SHW_PDPT_MASK EPT_PDPT_MASK
74# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
75# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
76
77#else
78# define SHWPT PGMSHWPTPAE
79# define PSHWPT PPGMSHWPTPAE
80# define SHWPTE PGMSHWPTEPAE
81# define PSHWPTE PPGMSHWPTEPAE
82# define SHWPD X86PDPAE
83# define PSHWPD PX86PDPAE
84# define SHWPDE X86PDEPAE
85# define PSHWPDE PX86PDEPAE
86# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
87# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
88# define SHW_PD_MASK X86_PD_PAE_MASK
89# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
90# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
91# define SHW_PT_MASK X86_PT_PAE_MASK
92
93# if PGM_SHW_TYPE == PGM_TYPE_AMD64
94# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
95# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
96# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
97# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
98
99# else /* 32 bits PAE mode */
100# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
101# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
102# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
103# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
104# endif
105#endif
106
107
108/*******************************************************************************
109* Internal Functions *
110*******************************************************************************/
111RT_C_DECLS_BEGIN
112/* r3 */
113PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0);
114PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
115PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
116PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
117
118/* all */
119PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
120PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
121RT_C_DECLS_END
122
123
124/**
125 * Initializes the guest bit of the paging mode data.
126 *
127 * @returns VBox status code.
128 * @param pVM The cross context VM structure.
129 * @param pModeData The pointer table to initialize (our members only).
130 * @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
131 * This is used early in the init process to avoid trouble with PDM
132 * not being initialized yet.
133 */
134PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0)
135{
136#if PGM_SHW_TYPE != PGM_TYPE_NESTED
137 Assert(pModeData->uShwType == PGM_SHW_TYPE || pModeData->uShwType == PGM_TYPE_NESTED);
138#else
139 Assert(pModeData->uShwType == PGM_SHW_TYPE);
140#endif
141
142 /* Ring-3 */
143 pModeData->pfnR3ShwRelocate = PGM_SHW_NAME(Relocate);
144 pModeData->pfnR3ShwExit = PGM_SHW_NAME(Exit);
145 pModeData->pfnR3ShwGetPage = PGM_SHW_NAME(GetPage);
146 pModeData->pfnR3ShwModifyPage = PGM_SHW_NAME(ModifyPage);
147
148 if (fResolveGCAndR0)
149 {
150 int rc;
151
152 if (!HMIsEnabled(pVM))
153 {
154#if PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT /* No AMD64 for traditional virtualization, only VT-x and AMD-V. */
155 /* GC */
156 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(GetPage), &pModeData->pfnRCShwGetPage);
157 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(GetPage), rc), rc);
158 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(ModifyPage), &pModeData->pfnRCShwModifyPage);
159 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(ModifyPage), rc), rc);
160#endif /* Not AMD64 shadow paging. */
161 }
162
163 /* Ring-0 */
164 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(GetPage), &pModeData->pfnR0ShwGetPage);
165 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(GetPage), rc), rc);
166 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(ModifyPage), &pModeData->pfnR0ShwModifyPage);
167 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(ModifyPage), rc), rc);
168 }
169 return VINF_SUCCESS;
170}
171
172/**
173 * Enters the shadow mode.
174 *
175 * @returns VBox status code.
176 * @param pVCpu The cross context virtual CPU structure.
177 * @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
178 */
179PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
180{
181#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
182
183# if PGM_SHW_TYPE == PGM_TYPE_NESTED && HC_ARCH_BITS == 32
184 /* Must distinguish between 32 and 64 bits guest paging modes as we'll use
185 a different shadow paging root/mode in both cases. */
186 RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
187# else
188 RTGCPHYS GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
189# endif
190 PPGMPOOLPAGE pNewShwPageCR3;
191 PVM pVM = pVCpu->pVMR3;
192
193 Assert(HMIsNestedPagingActive(pVM) == pVM->pgm.s.fNestedPaging);
194 Assert(pVM->pgm.s.fNestedPaging);
195 Assert(!pVCpu->pgm.s.pShwPageCR3R3);
196
197 pgmLock(pVM);
198
199 int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
200 NIL_PGMPOOL_IDX, UINT32_MAX, true /*fLockPage*/,
201 &pNewShwPageCR3);
202 AssertFatalRC(rc);
203
204 pVCpu->pgm.s.pShwPageCR3R3 = pNewShwPageCR3;
205
206 pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.pShwPageCR3R3);
207 pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.pShwPageCR3R3);
208
209 pgmUnlock(pVM);
210
211 Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
212#else
213 NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
214#endif
215 return VINF_SUCCESS;
216}
217
218
219/**
220 * Relocate any GC pointers related to shadow mode paging.
221 *
222 * @returns VBox status code.
223 * @param pVCpu The cross context virtual CPU structure.
224 * @param offDelta The relocation offset.
225 */
226PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
227{
228 pVCpu->pgm.s.pShwPageCR3RC += offDelta;
229 return VINF_SUCCESS;
230}
231
232
233/**
234 * Exits the shadow mode.
235 *
236 * @returns VBox status code.
237 * @param pVCpu The cross context virtual CPU structure.
238 */
239PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu)
240{
241 PVM pVM = pVCpu->pVMR3;
242
243 if ( ( pVCpu->pgm.s.enmShadowMode == PGMMODE_NESTED
244 || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT)
245 && pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
246 {
247 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
248
249 pgmLock(pVM);
250
251 /* Do *not* unlock this page as we have two of them floating around in the 32-bit host & 64-bit guest case.
252 * We currently assert when you try to free one of them; don't bother to really allow this.
253 *
254 * Note that this is two nested paging root pages max. This isn't a leak. They are reused.
255 */
256 /* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
257
258 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
259 pVCpu->pgm.s.pShwPageCR3R3 = 0;
260 pVCpu->pgm.s.pShwPageCR3R0 = 0;
261 pVCpu->pgm.s.pShwPageCR3RC = 0;
262
263 pgmUnlock(pVM);
264
265 Log(("Leave nested shadow paging mode\n"));
266 }
267 return VINF_SUCCESS;
268}
269
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