1 | /* $Id: PGMShw.h 70948 2018-02-10 15:38:12Z vboxsync $ */
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2 | /** @file
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3 | * VBox - Page Manager / Monitor, Shadow Paging Template.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2017 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | /*******************************************************************************
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19 | * Defined Constants And Macros *
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20 | *******************************************************************************/
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21 | #undef SHWPT
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22 | #undef PSHWPT
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23 | #undef SHWPTE
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24 | #undef PSHWPTE
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25 | #undef SHWPD
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26 | #undef PSHWPD
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27 | #undef SHWPDE
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28 | #undef PSHWPDE
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29 | #undef SHW_PDE_PG_MASK
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30 | #undef SHW_PD_SHIFT
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31 | #undef SHW_PD_MASK
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32 | #undef SHW_PTE_PG_MASK
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33 | #undef SHW_PT_SHIFT
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34 | #undef SHW_PT_MASK
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35 | #undef SHW_TOTAL_PD_ENTRIES
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36 | #undef SHW_PDPT_SHIFT
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37 | #undef SHW_PDPT_MASK
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38 | #undef SHW_PDPE_PG_MASK
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39 |
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40 | #if PGM_SHW_TYPE == PGM_TYPE_32BIT
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41 | # define SHWPT X86PT
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42 | # define PSHWPT PX86PT
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43 | # define SHWPTE X86PTE
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44 | # define PSHWPTE PX86PTE
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45 | # define SHWPD X86PD
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46 | # define PSHWPD PX86PD
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47 | # define SHWPDE X86PDE
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48 | # define PSHWPDE PX86PDE
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49 | # define SHW_PDE_PG_MASK X86_PDE_PG_MASK
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50 | # define SHW_PD_SHIFT X86_PD_SHIFT
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51 | # define SHW_PD_MASK X86_PD_MASK
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52 | # define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
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53 | # define SHW_PTE_PG_MASK X86_PTE_PG_MASK
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54 | # define SHW_PT_SHIFT X86_PT_SHIFT
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55 | # define SHW_PT_MASK X86_PT_MASK
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56 |
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57 | #elif PGM_SHW_TYPE == PGM_TYPE_EPT
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58 | # define SHWPT EPTPT
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59 | # define PSHWPT PEPTPT
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60 | # define SHWPTE EPTPTE
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61 | # define PSHWPTE PEPTPTE
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62 | # define SHWPD EPTPD
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63 | # define PSHWPD PEPTPD
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64 | # define SHWPDE EPTPDE
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65 | # define PSHWPDE PEPTPDE
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66 | # define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
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67 | # define SHW_PD_SHIFT EPT_PD_SHIFT
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68 | # define SHW_PD_MASK EPT_PD_MASK
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69 | # define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
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70 | # define SHW_PT_SHIFT EPT_PT_SHIFT
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71 | # define SHW_PT_MASK EPT_PT_MASK
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72 | # define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
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73 | # define SHW_PDPT_MASK EPT_PDPT_MASK
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74 | # define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
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75 | # define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
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76 |
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77 | #else
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78 | # define SHWPT PGMSHWPTPAE
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79 | # define PSHWPT PPGMSHWPTPAE
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80 | # define SHWPTE PGMSHWPTEPAE
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81 | # define PSHWPTE PPGMSHWPTEPAE
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82 | # define SHWPD X86PDPAE
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83 | # define PSHWPD PX86PDPAE
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84 | # define SHWPDE X86PDEPAE
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85 | # define PSHWPDE PX86PDEPAE
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86 | # define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
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87 | # define SHW_PD_SHIFT X86_PD_PAE_SHIFT
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88 | # define SHW_PD_MASK X86_PD_PAE_MASK
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89 | # define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
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90 | # define SHW_PT_SHIFT X86_PT_PAE_SHIFT
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91 | # define SHW_PT_MASK X86_PT_PAE_MASK
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92 |
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93 | # if PGM_SHW_TYPE == PGM_TYPE_AMD64
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94 | # define SHW_PDPT_SHIFT X86_PDPT_SHIFT
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95 | # define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
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96 | # define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
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97 | # define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
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98 |
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99 | # else /* 32 bits PAE mode */
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100 | # define SHW_PDPT_SHIFT X86_PDPT_SHIFT
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101 | # define SHW_PDPT_MASK X86_PDPT_MASK_PAE
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102 | # define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
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103 | # define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
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104 | # endif
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105 | #endif
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106 |
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107 |
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108 | /*******************************************************************************
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109 | * Internal Functions *
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110 | *******************************************************************************/
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111 | RT_C_DECLS_BEGIN
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112 | /* r3 */
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113 | PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0);
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114 | PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
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115 | PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
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116 | PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
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117 |
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118 | /* all */
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119 | PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
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120 | PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
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121 | RT_C_DECLS_END
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122 |
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123 |
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124 | /**
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125 | * Initializes the guest bit of the paging mode data.
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126 | *
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127 | * @returns VBox status code.
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128 | * @param pVM The cross context VM structure.
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129 | * @param pModeData The pointer table to initialize (our members only).
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130 | * @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
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131 | * This is used early in the init process to avoid trouble with PDM
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132 | * not being initialized yet.
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133 | */
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134 | PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0)
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135 | {
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136 | #if PGM_SHW_TYPE != PGM_TYPE_NESTED
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137 | Assert(pModeData->uShwType == PGM_SHW_TYPE || pModeData->uShwType == PGM_TYPE_NESTED);
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138 | #else
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139 | Assert(pModeData->uShwType == PGM_SHW_TYPE);
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140 | #endif
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141 |
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142 | /* Ring-3 */
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143 | pModeData->pfnR3ShwRelocate = PGM_SHW_NAME(Relocate);
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144 | pModeData->pfnR3ShwExit = PGM_SHW_NAME(Exit);
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145 | pModeData->pfnR3ShwGetPage = PGM_SHW_NAME(GetPage);
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146 | pModeData->pfnR3ShwModifyPage = PGM_SHW_NAME(ModifyPage);
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147 |
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148 | if (fResolveGCAndR0)
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149 | {
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150 | int rc;
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151 |
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152 | if (VM_IS_RAW_MODE_ENABLED(pVM))
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153 | {
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154 | #if PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT /* No AMD64 for traditional virtualization, only VT-x and AMD-V. */
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155 | /* GC */
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156 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(GetPage), &pModeData->pfnRCShwGetPage);
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157 | AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(GetPage), rc), rc);
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158 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(ModifyPage), &pModeData->pfnRCShwModifyPage);
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159 | AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(ModifyPage), rc), rc);
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160 | #endif /* Not AMD64 shadow paging. */
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161 | }
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162 |
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163 | /* Ring-0 */
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164 | rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(GetPage), &pModeData->pfnR0ShwGetPage);
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165 | AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(GetPage), rc), rc);
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166 | rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(ModifyPage), &pModeData->pfnR0ShwModifyPage);
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167 | AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(ModifyPage), rc), rc);
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168 | }
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169 | return VINF_SUCCESS;
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170 | }
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171 |
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172 | /**
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173 | * Enters the shadow mode.
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174 | *
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175 | * @returns VBox status code.
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176 | * @param pVCpu The cross context virtual CPU structure.
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177 | * @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
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178 | */
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179 | PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
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180 | {
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181 | #if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
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182 |
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183 | # if PGM_SHW_TYPE == PGM_TYPE_NESTED && HC_ARCH_BITS == 32
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184 | /* Must distinguish between 32 and 64 bits guest paging modes as we'll use
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185 | a different shadow paging root/mode in both cases. */
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186 | RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
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187 | # else
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188 | RTGCPHYS GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
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189 | # endif
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190 | PPGMPOOLPAGE pNewShwPageCR3;
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191 | PVM pVM = pVCpu->pVMR3;
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192 |
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193 | Assert(HMIsNestedPagingActive(pVM) == pVM->pgm.s.fNestedPaging);
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194 | Assert(pVM->pgm.s.fNestedPaging);
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195 | Assert(!pVCpu->pgm.s.pShwPageCR3R3);
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196 |
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197 | pgmLock(pVM);
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198 |
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199 | int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
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200 | NIL_PGMPOOL_IDX, UINT32_MAX, true /*fLockPage*/,
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201 | &pNewShwPageCR3);
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202 | AssertFatalRC(rc);
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203 |
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204 | pVCpu->pgm.s.pShwPageCR3R3 = pNewShwPageCR3;
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205 |
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206 | pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.pShwPageCR3R3);
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207 | pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.pShwPageCR3R3);
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208 |
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209 | pgmUnlock(pVM);
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210 |
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211 | Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
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212 | #else
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213 | NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
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214 | #endif
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215 | return VINF_SUCCESS;
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216 | }
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217 |
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218 |
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219 | /**
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220 | * Relocate any GC pointers related to shadow mode paging.
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221 | *
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222 | * @returns VBox status code.
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223 | * @param pVCpu The cross context virtual CPU structure.
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224 | * @param offDelta The relocation offset.
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225 | */
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226 | PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
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227 | {
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228 | pVCpu->pgm.s.pShwPageCR3RC += offDelta;
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229 | return VINF_SUCCESS;
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230 | }
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231 |
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232 |
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233 | /**
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234 | * Exits the shadow mode.
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235 | *
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236 | * @returns VBox status code.
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237 | * @param pVCpu The cross context virtual CPU structure.
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238 | */
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239 | PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu)
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240 | {
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241 | PVM pVM = pVCpu->pVMR3;
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242 |
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243 | if ( ( pVCpu->pgm.s.enmShadowMode == PGMMODE_NESTED
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244 | || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT)
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245 | && pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
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246 | {
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247 | PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
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248 |
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249 | pgmLock(pVM);
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250 |
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251 | /* Do *not* unlock this page as we have two of them floating around in the 32-bit host & 64-bit guest case.
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252 | * We currently assert when you try to free one of them; don't bother to really allow this.
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253 | *
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254 | * Note that this is two nested paging root pages max. This isn't a leak. They are reused.
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255 | */
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256 | /* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
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257 |
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258 | pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
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259 | pVCpu->pgm.s.pShwPageCR3R3 = 0;
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260 | pVCpu->pgm.s.pShwPageCR3R0 = 0;
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261 | pVCpu->pgm.s.pShwPageCR3RC = 0;
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262 |
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263 | pgmUnlock(pVM);
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264 |
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265 | Log(("Leave nested shadow paging mode\n"));
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266 | }
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267 | return VINF_SUCCESS;
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268 | }
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269 |
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