SELM.cpp@ 42372

Last change on this file since 42372 was 42372, checked in by vboxsync, 12 years ago
SELM: Moving the code around and replacing two AssertRelease+VERR_NOT_SUPPORTED/IMPLEMENTED with proper status codes. Should be an real changes in this commit, just making the SELMR3UpdateFromCPUM code more managable.
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File size: 100.3 KB

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1	/* $Id: SELM.cpp 42372 2012-07-24 21:50:16Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/mm.h>
66	#include <VBox/vmm/ssm.h>
67	#include <VBox/vmm/pgm.h>
68	#include <VBox/vmm/trpm.h>
69	#include <VBox/vmm/dbgf.h>
70	#include "SELMInternal.h"
71	#include <VBox/vmm/vm.h>
72	#include <VBox/err.h>
73	#include <VBox/param.h>
74
75	#include <iprt/assert.h>
76	#include <VBox/log.h>
77	#include <iprt/asm.h>
78	#include <iprt/string.h>
79	#include <iprt/thread.h>
80	#include <iprt/string.h>
81
82
83	/**
84	* Enable or disable tracking of Shadow GDT/LDT/TSS.
85	* @{
86	*/
87	#define SELM_TRACK_SHADOW_GDT_CHANGES
88	#define SELM_TRACK_SHADOW_LDT_CHANGES
89	#define SELM_TRACK_SHADOW_TSS_CHANGES
90	/** @} */
91
92
93	/** SELM saved state version. */
94	#define SELM_SAVED_STATE_VERSION 5
95
96
97	/*******************************************************************************
98	* Internal Functions *
99	*******************************************************************************/
100	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
101	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
102	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
103	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
104	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
105	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
106	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112
113
114
115	/**
116	* Initializes the SELM.
117	*
118	* @returns VBox status code.
119	* @param pVM Pointer to the VM.
120	*/
121	VMMR3DECL(int) SELMR3Init(PVM pVM)
122	{
123	LogFlow(("SELMR3Init\n"));
124
125	/*
126	* Assert alignment and sizes.
127	* (The TSS block requires contiguous back.)
128	*/
129	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
130	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
131	#if 0 /* doesn't work */
132	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
133	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
134	#endif
135	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
136	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
137	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
138
139	/*
140	* Init the structure.
141	*/
142	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
143	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
144	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
145	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
146	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
147	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
148
149	/*
150	* Allocate GDT table.
151	*/
152	int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
153	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
154	AssertRCReturn(rc, rc);
155
156	/*
157	* Allocate LDT area.
158	*/
159	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
160	AssertRCReturn(rc, rc);
161
162	/*
163	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
164	*/
165	pVM->selm.s.cbEffGuestGdtLimit = 0;
166	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
167	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
168	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
169
170	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
171	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
172	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
173	pVM->selm.s.GCSelTss = RTSEL_MAX;
174
175	pVM->selm.s.fDisableMonitoring = false;
176	pVM->selm.s.fSyncTSSRing0Stack = false;
177
178	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
179	* for I/O operations. */
180	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
181	/* bit set to 1 means no redirection */
182	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
183
184	/*
185	* Register the saved state data unit.
186	*/
187	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
188	NULL, NULL, NULL,
189	NULL, selmR3Save, NULL,
190	NULL, selmR3Load, selmR3LoadDone);
191	if (RT_FAILURE(rc))
192	return rc;
193
194	/*
195	* Statistics.
196	*/
197	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
198	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
199	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
200	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
201	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
202	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
203	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
204	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
205	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
206
207	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
208	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
209
210	/*
211	* Default action when entering raw mode for the first time
212	*/
213	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
214	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
215	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
216	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
217
218	/*
219	* Register info handlers.
220	*/
221	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
222	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
223	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
224	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
225	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
226	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
227
228	return rc;
229	}
230
231
232	/**
233	* Finalizes HMA page attributes.
234	*
235	* @returns VBox status code.
236	* @param pVM Pointer to the VM.
237	*/
238	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
239	{
240	/** @cfgm{/DoubleFault,bool,false}
241	* Enables catching of double faults in the raw-mode context VMM code. This can
242	* be used when the triple faults or hangs occur and one suspect an unhandled
243	* double fault. This is not enabled by default because it means making the
244	* hyper selectors writeable for all supervisor code, including the guest's.
245	* The double fault is a task switch and thus requires write access to the GDT
246	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
247	* 8 TSS for the back link.
248	*/
249	bool f;
250	#if defined(DEBUG_bird)
251	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
252	#else
253	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
254	#endif
255	AssertLogRelRCReturn(rc, rc);
256	if (f)
257	{
258	PX86DESC paGdt = pVM->selm.s.paGdtR3;
259	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
260	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
261	AssertRC(rc);
262	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
263	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
264	AssertRC(rc);
265	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
266	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
267	AssertRC(rc);
268	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
269	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
270	AssertRC(rc);
271	}
272	return VINF_SUCCESS;
273	}
274
275
276	/**
277	* Setup the hypervisor GDT selectors in our shadow table
278	*
279	* @param pVM Pointer to the VM.
280	*/
281	static void selmR3SetupHyperGDTSelectors(PVM pVM)
282	{
283	PX86DESC paGdt = pVM->selm.s.paGdtR3;
284
285	/*
286	* Set up global code and data descriptors for use in the guest context.
287	* Both are wide open (base 0, limit 4GB)
288	*/
289	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
290	pDesc->Gen.u16LimitLow = 0xffff;
291	pDesc->Gen.u4LimitHigh = 0xf;
292	pDesc->Gen.u16BaseLow = 0;
293	pDesc->Gen.u8BaseHigh1 = 0;
294	pDesc->Gen.u8BaseHigh2 = 0;
295	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
296	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
297	pDesc->Gen.u2Dpl = 0; /* supervisor */
298	pDesc->Gen.u1Present = 1;
299	pDesc->Gen.u1Available = 0;
300	pDesc->Gen.u1Long = 0;
301	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
302	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
303
304	/* data */
305	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
306	pDesc->Gen.u16LimitLow = 0xffff;
307	pDesc->Gen.u4LimitHigh = 0xf;
308	pDesc->Gen.u16BaseLow = 0;
309	pDesc->Gen.u8BaseHigh1 = 0;
310	pDesc->Gen.u8BaseHigh2 = 0;
311	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
312	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
313	pDesc->Gen.u2Dpl = 0; /* supervisor */
314	pDesc->Gen.u1Present = 1;
315	pDesc->Gen.u1Available = 0;
316	pDesc->Gen.u1Long = 0;
317	pDesc->Gen.u1DefBig = 1; /* big */
318	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
319
320	/* 64-bit mode code (& data?) */
321	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
322	pDesc->Gen.u16LimitLow = 0xffff;
323	pDesc->Gen.u4LimitHigh = 0xf;
324	pDesc->Gen.u16BaseLow = 0;
325	pDesc->Gen.u8BaseHigh1 = 0;
326	pDesc->Gen.u8BaseHigh2 = 0;
327	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
328	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
329	pDesc->Gen.u2Dpl = 0; /* supervisor */
330	pDesc->Gen.u1Present = 1;
331	pDesc->Gen.u1Available = 0;
332	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
333	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
334	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
335
336	/*
337	* TSS descriptor
338	*/
339	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
340	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
341	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
342	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
343	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
344	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
345	pDesc->Gen.u4LimitHigh = 0;
346	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
347	pDesc->Gen.u1DescType = 0; /* system */
348	pDesc->Gen.u2Dpl = 0; /* supervisor */
349	pDesc->Gen.u1Present = 1;
350	pDesc->Gen.u1Available = 0;
351	pDesc->Gen.u1Long = 0;
352	pDesc->Gen.u1DefBig = 0;
353	pDesc->Gen.u1Granularity = 0; /* byte limit */
354
355	/*
356	* TSS descriptor for trap 08
357	*/
358	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
359	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
360	pDesc->Gen.u4LimitHigh = 0;
361	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
362	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
363	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
364	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
365	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
366	pDesc->Gen.u1DescType = 0; /* system */
367	pDesc->Gen.u2Dpl = 0; /* supervisor */
368	pDesc->Gen.u1Present = 1;
369	pDesc->Gen.u1Available = 0;
370	pDesc->Gen.u1Long = 0;
371	pDesc->Gen.u1DefBig = 0;
372	pDesc->Gen.u1Granularity = 0; /* byte limit */
373	}
374
375	/**
376	* Applies relocations to data and code managed by this
377	* component. This function will be called at init and
378	* whenever the VMM need to relocate it self inside the GC.
379	*
380	* @param pVM The VM.
381	*/
382	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
383	{
384	PX86DESC paGdt = pVM->selm.s.paGdtR3;
385	LogFlow(("SELMR3Relocate\n"));
386
387	for (VMCPUID i = 0; i < pVM->cCpus; i++)
388	{
389	PVMCPU pVCpu = &pVM->aCpus[i];
390
391	/*
392	* Update GDTR and selector.
393	*/
394	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
395
396	/** @todo selector relocations should be a separate operation? */
397	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
398	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
399	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
400	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
401	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
402	}
403
404	selmR3SetupHyperGDTSelectors(pVM);
405
406	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
407	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
408	/*
409	* Update the TSSes.
410	*/
411	/* Only applies to raw mode which supports only 1 VCPU */
412	PVMCPU pVCpu = &pVM->aCpus[0];
413
414	/* Current TSS */
415	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
416	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
417	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
418	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
419	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
420	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
421	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
422
423	/* trap 08 */
424	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
425	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
426	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
427	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
428	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
429	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
430	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
431	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
432	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
433	pVM->selm.s.TssTrap08.fs = 0;
434	pVM->selm.s.TssTrap08.gs = 0;
435	pVM->selm.s.TssTrap08.selLdt = 0;
436	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
437	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
438	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
439	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
440	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
441	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
442	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
443	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
444	/* TRPM will be updating the eip */
445
446	if ( !pVM->selm.s.fDisableMonitoring
447	&& !VMMIsHwVirtExtForced(pVM))
448	{
449	/*
450	* Update shadow GDT/LDT/TSS write access handlers.
451	*/
452	int rc;
453	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
454	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
455	{
456	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
457	AssertRC(rc);
458	}
459	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
460	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
461	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
462	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
463	AssertRC(rc);
464	#endif
465	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
466	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
467	{
468	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
469	AssertRC(rc);
470	}
471	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
472	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
473	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
474	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
475	AssertRC(rc);
476	#endif
477
478	/*
479	* Update the GC LDT region handler and address.
480	*/
481	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
482	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
483	{
484	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
485	AssertRC(rc);
486	}
487	#endif
488	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
489	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
490	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
491	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
492	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
493	AssertRC(rc);
494	#endif
495	}
496	}
497
498
499	/**
500	* Terminates the SELM.
501	*
502	* Termination means cleaning up and freeing all resources,
503	* the VM it self is at this point powered off or suspended.
504	*
505	* @returns VBox status code.
506	* @param pVM Pointer to the VM.
507	*/
508	VMMR3DECL(int) SELMR3Term(PVM pVM)
509	{
510	NOREF(pVM);
511	return 0;
512	}
513
514
515	/**
516	* The VM is being reset.
517	*
518	* For the SELM component this means that any GDT/LDT/TSS monitors
519	* needs to be removed.
520	*
521	* @param pVM Pointer to the VM.
522	*/
523	VMMR3DECL(void) SELMR3Reset(PVM pVM)
524	{
525	LogFlow(("SELMR3Reset:\n"));
526	VM_ASSERT_EMT(pVM);
527
528	/*
529	* Uninstall guest GDT/LDT/TSS write access handlers.
530	*/
531	int rc;
532	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
533	{
534	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
535	AssertRC(rc);
536	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
537	pVM->selm.s.GuestGdtr.cbGdt = 0;
538	}
539	pVM->selm.s.fGDTRangeRegistered = false;
540	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
541	{
542	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
543	AssertRC(rc);
544	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
545	}
546	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
547	{
548	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
549	AssertRC(rc);
550	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
551	pVM->selm.s.GCSelTss = RTSEL_MAX;
552	}
553
554	/*
555	* Re-initialize other members.
556	*/
557	pVM->selm.s.cbLdtLimit = 0;
558	pVM->selm.s.offLdtHyper = 0;
559	pVM->selm.s.cbMonitoredGuestTss = 0;
560
561	pVM->selm.s.fSyncTSSRing0Stack = false;
562
563	/*
564	* Default action when entering raw mode for the first time
565	*/
566	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
567	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
568	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
569	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
570	}
571
572	/**
573	* Disable GDT/LDT/TSS monitoring and syncing
574	*
575	* @param pVM Pointer to the VM.
576	*/
577	VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
578	{
579	/*
580	* Uninstall guest GDT/LDT/TSS write access handlers.
581	*/
582	int rc;
583	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
584	{
585	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
586	AssertRC(rc);
587	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
588	pVM->selm.s.GuestGdtr.cbGdt = 0;
589	}
590	pVM->selm.s.fGDTRangeRegistered = false;
591	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
592	{
593	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
594	AssertRC(rc);
595	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
596	}
597	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
598	{
599	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
600	AssertRC(rc);
601	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
602	pVM->selm.s.GCSelTss = RTSEL_MAX;
603	}
604
605	/*
606	* Unregister shadow GDT/LDT/TSS write access handlers.
607	*/
608	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
609	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
610	{
611	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
612	AssertRC(rc);
613	pVM->selm.s.paGdtRC = NIL_RTRCPTR;
614	}
615	#endif
616	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
617	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
618	{
619	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
620	AssertRC(rc);
621	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
622	}
623	#endif
624	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
625	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
626	{
627	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
628	AssertRC(rc);
629	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
630	}
631	#endif
632
633	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
634	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
635	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
636	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
637
638	pVM->selm.s.fDisableMonitoring = true;
639	}
640
641
642	/**
643	* Execute state save operation.
644	*
645	* @returns VBox status code.
646	* @param pVM Pointer to the VM.
647	* @param pSSM SSM operation handle.
648	*/
649	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
650	{
651	LogFlow(("selmR3Save:\n"));
652
653	/*
654	* Save the basic bits - fortunately all the other things can be resynced on load.
655	*/
656	PSELM pSelm = &pVM->selm.s;
657
658	SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
659	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
660	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
661	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
662	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
663	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
664	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
665	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
666	}
667
668
669	/**
670	* Execute state load operation.
671	*
672	* @returns VBox status code.
673	* @param pVM Pointer to the VM.
674	* @param pSSM SSM operation handle.
675	* @param uVersion Data layout version.
676	* @param uPass The data pass.
677	*/
678	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
679	{
680	LogFlow(("selmR3Load:\n"));
681	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
682
683	/*
684	* Validate version.
685	*/
686	if (uVersion != SELM_SAVED_STATE_VERSION)
687	{
688	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
689	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
690	}
691
692	/*
693	* Do a reset.
694	*/
695	SELMR3Reset(pVM);
696
697	/* Get the monitoring flag. */
698	SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
699
700	/* Get the TSS state flag. */
701	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
702
703	/*
704	* Get the selectors.
705	*/
706	RTSEL SelCS;
707	SSMR3GetSel(pSSM, &SelCS);
708	RTSEL SelDS;
709	SSMR3GetSel(pSSM, &SelDS);
710	RTSEL SelCS64;
711	SSMR3GetSel(pSSM, &SelCS64);
712	RTSEL SelDS64;
713	SSMR3GetSel(pSSM, &SelDS64);
714	RTSEL SelTSS;
715	SSMR3GetSel(pSSM, &SelTSS);
716	RTSEL SelTSSTrap08;
717	SSMR3GetSel(pSSM, &SelTSSTrap08);
718
719	/* Copy the selectors; they will be checked during relocation. */
720	PSELM pSelm = &pVM->selm.s;
721	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
722	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
723	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
724	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
725	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
726
727	return VINF_SUCCESS;
728	}
729
730
731	/**
732	* Sync the GDT, LDT and TSS after loading the state.
733	*
734	* Just to play save, we set the FFs to force syncing before
735	* executing GC code.
736	*
737	* @returns VBox status code.
738	* @param pVM Pointer to the VM.
739	* @param pSSM SSM operation handle.
740	*/
741	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
742	{
743	PVMCPU pVCpu = VMMGetCpu(pVM);
744
745	LogFlow(("selmR3LoadDone:\n"));
746
747	/*
748	* Don't do anything if it's a load failure.
749	*/
750	int rc = SSMR3HandleGetStatus(pSSM);
751	if (RT_FAILURE(rc))
752	return VINF_SUCCESS;
753
754	/*
755	* Do the syncing if we're in protected mode.
756	*/
757	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
758	{
759	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
760	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
761	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
762	SELMR3UpdateFromCPUM(pVM, pVCpu);
763	}
764
765	/*
766	* Flag everything for resync on next raw mode entry.
767	*/
768	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
769	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
770	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
771
772	return VINF_SUCCESS;
773	}
774
775
776	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
777	{
778	/*
779	* Always assume the best...
780	*/
781	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
782
783	/* If the GDT was changed, then make sure the LDT is checked too */
784	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
785	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
786	/* Same goes for the TSS selector */
787	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
788
789	/*
790	* Get the GDTR and check if there is anything to do (there usually is).
791	*/
792	VBOXGDTR GDTR;
793	CPUMGetGuestGDTR(pVCpu, &GDTR);
794	if (GDTR.cbGdt < sizeof(X86DESC))
795	{
796	Log(("No GDT entries...\n"));
797	return VINF_SUCCESS;
798	}
799
800	/*
801	* Read the Guest GDT.
802	* ASSUMES that the entire GDT is in memory.
803	*/
804	RTUINT cbEffLimit = GDTR.cbGdt;
805	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
806	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
807	if (RT_FAILURE(rc))
808	{
809	/*
810	* Read it page by page.
811	*
812	* Keep track of the last valid page and delay memsets and
813	* adjust cbEffLimit to reflect the effective size. The latter
814	* is something we do in the belief that the guest will probably
815	* never actually commit the last page, thus allowing us to keep
816	* our selectors in the high end of the GDT.
817	*/
818	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
819	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
820	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
821	uint8_t *pu8DstInvalid = pu8Dst;
822
823	while (cbLeft)
824	{
825	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
826	cb = RT_MIN(cb, cbLeft);
827	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
828	if (RT_SUCCESS(rc))
829	{
830	if (pu8DstInvalid != pu8Dst)
831	memset(pu8DstInvalid, 0, pu8Dst - pu8DstInvalid);
832	GCPtrSrc += cb;
833	pu8Dst += cb;
834	pu8DstInvalid = pu8Dst;
835	}
836	else if ( rc == VERR_PAGE_NOT_PRESENT
837	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
838	{
839	GCPtrSrc += cb;
840	pu8Dst += cb;
841	}
842	else
843	{
844	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
845	return VERR_SELM_GDT_READ_ERROR;
846	}
847	cbLeft -= cb;
848	}
849
850	/* any invalid pages at the end? */
851	if (pu8DstInvalid != pu8Dst)
852	{
853	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
854	/* If any GDTEs was invalidated, zero them. */
855	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
856	memset(pu8DstInvalid + cbEffLimit + 1, 0, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
857	}
858
859	/* keep track of the effective limit. */
860	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
861	{
862	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
863	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
864	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
865	}
866	}
867
868	/*
869	* Check if the Guest GDT intrudes on our GDT entries.
870	*/
871	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
872	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
873	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
874	{
875	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
876	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
877	int iGDT = 0;
878
879	Log(("Internal SELM GDT conflict: use non-present entries\n"));
880	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
881	while (pGDTECur > pGDTEStart)
882	{
883	/* We can reuse non-present entries */
884	if (!pGDTECur->Gen.u1Present)
885	{
886	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
887	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
888	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
889	iGDT++;
890	if (iGDT >= SELM_HYPER_SEL_MAX)
891	break;
892	}
893
894	pGDTECur--;
895	}
896	if (iGDT != SELM_HYPER_SEL_MAX)
897	{
898	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
899	return VERR_SELM_GDT_TOO_FULL;
900	}
901	}
902	else
903	{
904	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
905	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
906	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
907	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
908	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
909	}
910
911	/*
912	* Work thru the copied GDT entries adjusting them for correct virtualization.
913	*/
914	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
915	while (pGDTE < pGDTEEnd)
916	{
917	if (pGDTE->Gen.u1Present)
918	{
919	/*
920	* Code and data selectors are generally 1:1, with the
921	* 'little' adjustment we do for DPL 0 selectors.
922	*/
923	if (pGDTE->Gen.u1DescType)
924	{
925	/*
926	* Hack for A-bit against Trap E on read-only GDT.
927	*/
928	/** @todo Fix this by loading ds and cs before turning off WP. */
929	pGDTE->Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
930
931	/*
932	* All DPL 0 code and data segments are squeezed into DPL 1.
933	*
934	* We're skipping conforming segments here because those
935	* cannot give us any trouble.
936	*/
937	if ( pGDTE->Gen.u2Dpl == 0
938	&& (pGDTE->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
939	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
940	pGDTE->Gen.u2Dpl = 1;
941	}
942	else
943	{
944	/*
945	* System type selectors are marked not present.
946	* Recompiler or special handling is required for these.
947	*/
948	/** @todo what about interrupt gates and rawr0? */
949	pGDTE->Gen.u1Present = 0;
950	}
951	}
952
953	/* Next GDT entry. */
954	pGDTE++;
955	}
956
957	/*
958	* Check if our hypervisor selectors were changed.
959	*/
960	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
961	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
962	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
963	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
964	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
965	{
966	/* Reinitialize our hypervisor GDTs */
967	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
968	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
969	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
970	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
971	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
972
973	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
974
975	/*
976	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
977	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
978	*/
979	VMR3Relocate(pVM, 0);
980	}
981	else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
982	/* We overwrote all entries above, so we have to save them again. */
983	selmR3SetupHyperGDTSelectors(pVM);
984
985	/*
986	* Adjust the cached GDT limit.
987	* Any GDT entries which have been removed must be cleared.
988	*/
989	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
990	{
991	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
992	memset(pGDTE, 0, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
993	}
994
995	/*
996	* Check if Guest's GDTR is changed.
997	*/
998	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
999	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1000	{
1001	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1002
1003	/*
1004	* [Re]Register write virtual handler for guest's GDT.
1005	*/
1006	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1007	{
1008	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1009	AssertRC(rc);
1010	}
1011
1012	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1013	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1014	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1015	"Guest GDT write access handler");
1016	if (RT_FAILURE(rc))
1017	return rc;
1018
1019	/* Update saved Guest GDTR. */
1020	pVM->selm.s.GuestGdtr = GDTR;
1021	pVM->selm.s.fGDTRangeRegistered = true;
1022	}
1023
1024	return VINF_SUCCESS;
1025	}
1026
1027
1028	/**
1029	* Updates (syncs) the shadow LDT.
1030	*
1031	* @returns VBox status code.
1032	* @param pVM The VM handle.
1033	* @param pVCpu The current virtual CPU.
1034	*/
1035	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1036	{
1037	int rc = VINF_SUCCESS;
1038
1039	/*
1040	* Always assume the best...
1041	*/
1042	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1043
1044	/*
1045	* LDT handling is done similarly to the GDT handling with a shadow
1046	* array. However, since the LDT is expected to be swappable (at least
1047	* some ancient OSes makes it swappable) it must be floating and
1048	* synced on a per-page basis.
1049	*
1050	* Eventually we will change this to be fully on demand. Meaning that
1051	* we will only sync pages containing LDT selectors actually used and
1052	* let the #PF handler lazily sync pages as they are used.
1053	* (This applies to GDT too, when we start making OS/2 fast.)
1054	*/
1055
1056	/*
1057	* First, determine the current LDT selector.
1058	*/
1059	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1060	if ((SelLdt & X86_SEL_MASK) == 0)
1061	{
1062	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1063	CPUMSetHyperLDTR(pVCpu, 0);
1064	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1065	{
1066	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1067	AssertRC(rc);
1068	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1069	}
1070	return VINF_SUCCESS;
1071	}
1072
1073	/*
1074	* Get the LDT selector.
1075	*/
1076	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1077	RTGCPTR GCPtrLdt = X86DESC_BASE(*pDesc);
1078	unsigned cbLdt = X86DESC_LIMIT(*pDesc);
1079	if (pDesc->Gen.u1Granularity)
1080	cbLdt = (cbLdt << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
1081
1082	/*
1083	* Validate it.
1084	*/
1085	if ( !cbLdt
1086	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1087	\|\| pDesc->Gen.u1DescType
1088	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1089	{
1090	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1091
1092	/* cbLdt > 0:
1093	* This is quite impossible, so we do as most people do when faced with
1094	* the impossible, we simply ignore it.
1095	*/
1096	CPUMSetHyperLDTR(pVCpu, 0);
1097	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1098	{
1099	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1100	AssertRC(rc);
1101	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1102	}
1103	return VINF_SUCCESS;
1104	}
1105	/** @todo check what intel does about odd limits. */
1106	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1107
1108	/*
1109	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1110	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1111	*/
1112	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1113	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1114
1115
1116	/** @todo Handle only present LDT segments. */
1117	// if (pDesc->Gen.u1Present)
1118	{
1119	/*
1120	* Check if Guest's LDT address/limit is changed.
1121	*/
1122	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1123	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1124	{
1125	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1126	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1127
1128	/*
1129	* [Re]Register write virtual handler for guest's GDT.
1130	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1131	*/
1132	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1133	{
1134	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1135	AssertRC(rc);
1136	}
1137	#ifdef DEBUG
1138	if (pDesc->Gen.u1Present)
1139	Log(("LDT selector marked not present!!\n"));
1140	#endif
1141	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1142	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1143	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1144	{
1145	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1146	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1147	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1148	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1149	}
1150	else if (RT_SUCCESS(rc))
1151	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1152	else
1153	{
1154	CPUMSetHyperLDTR(pVCpu, 0);
1155	return rc;
1156	}
1157
1158	pVM->selm.s.cbLdtLimit = cbLdt;
1159	}
1160	}
1161
1162	/*
1163	* Calc Shadow LDT base.
1164	*/
1165	unsigned off;
1166	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1167	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1168	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1169
1170	/*
1171	* Enable the LDT selector in the shadow GDT.
1172	*/
1173	pDesc->Gen.u1Present = 1;
1174	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1175	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1176	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1177	pDesc->Gen.u1Available = 0;
1178	pDesc->Gen.u1Long = 0;
1179	if (cbLdt > 0xffff)
1180	{
1181	cbLdt = 0xffff;
1182	pDesc->Gen.u4LimitHigh = 0;
1183	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1184	}
1185
1186	/*
1187	* Set Hyper LDTR and notify TRPM.
1188	*/
1189	CPUMSetHyperLDTR(pVCpu, SelLdt);
1190
1191	/*
1192	* Loop synchronising the LDT page by page.
1193	*/
1194	/** @todo investigate how intel handle various operations on half present cross page entries. */
1195	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1196	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1197
1198	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1199	unsigned cbLeft = cbLdt + 1;
1200	PX86DESC pLDTE = pShadowLDT;
1201	while (cbLeft)
1202	{
1203	/*
1204	* Read a chunk.
1205	*/
1206	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1207	if (cbChunk > cbLeft)
1208	cbChunk = cbLeft;
1209	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1210	if (RT_SUCCESS(rc))
1211	{
1212	/*
1213	* Mark page
1214	*/
1215	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1216	AssertRC(rc);
1217
1218	/*
1219	* Loop thru the available LDT entries.
1220	* Figure out where to start and end and the potential cross pageness of
1221	* things adds a little complexity. pLDTE is updated there and not in the
1222	* 'next' part of the loop. The pLDTEEnd is inclusive.
1223	*/
1224	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1225	if (pLDTE + 1 < pShadowLDT)
1226	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1227	while (pLDTE <= pLDTEEnd)
1228	{
1229	if (pLDTE->Gen.u1Present)
1230	{
1231	/*
1232	* Code and data selectors are generally 1:1, with the
1233	* 'little' adjustment we do for DPL 0 selectors.
1234	*/
1235	if (pLDTE->Gen.u1DescType)
1236	{
1237	/*
1238	* Hack for A-bit against Trap E on read-only GDT.
1239	*/
1240	/** @todo Fix this by loading ds and cs before turning off WP. */
1241	if (!(pLDTE->Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1242	pLDTE->Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
1243
1244	/*
1245	* All DPL 0 code and data segments are squeezed into DPL 1.
1246	*
1247	* We're skipping conforming segments here because those
1248	* cannot give us any trouble.
1249	*/
1250	if ( pLDTE->Gen.u2Dpl == 0
1251	&& (pLDTE->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
1252	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
1253	pLDTE->Gen.u2Dpl = 1;
1254	}
1255	else
1256	{
1257	/*
1258	* System type selectors are marked not present.
1259	* Recompiler or special handling is required for these.
1260	*/
1261	/** @todo what about interrupt gates and rawr0? */
1262	pLDTE->Gen.u1Present = 0;
1263	}
1264	}
1265
1266	/* Next LDT entry. */
1267	pLDTE++;
1268	}
1269	}
1270	else
1271	{
1272	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1273	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1274	AssertRC(rc);
1275	}
1276
1277	/*
1278	* Advance to the next page.
1279	*/
1280	cbLeft -= cbChunk;
1281	GCPtrShadowLDT += cbChunk;
1282	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1283	GCPtrLdt += cbChunk;
1284	}
1285
1286	return VINF_SUCCESS;
1287	}
1288
1289
1290	/**
1291	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1292	*
1293	* @returns VBox status code.
1294	* @param pVM Pointer to the VM.
1295	* @param pVCpu Pointer to the VMCPU.
1296	*/
1297	VMMR3DECL(int) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1298	{
1299	if (pVM->selm.s.fDisableMonitoring)
1300	{
1301	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
1302	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1303	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1304	return VINF_SUCCESS;
1305	}
1306
1307	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1308
1309	/*
1310	* GDT sync
1311	*/
1312	int rc;
1313	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1314	{
1315	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1316	if (RT_FAILURE(rc))
1317	return rc; /* We're toast, so forget the profiling. */
1318	AssertRCSuccess(rc);
1319	}
1320
1321	/*
1322	* TSS sync
1323	*/
1324	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1325	{
1326	rc = SELMR3SyncTSS(pVM, pVCpu);
1327	if (RT_FAILURE(rc))
1328	return rc;
1329	AssertRCSuccess(rc);
1330	}
1331
1332	/*
1333	* LDT sync
1334	*/
1335	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1336	{
1337	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1338	if (RT_FAILURE(rc))
1339	return rc;
1340	AssertRCSuccess(rc);
1341	}
1342
1343	#if 0
1344	/*
1345	* Check for stale selectors and load hidden register bits where they
1346	* are missing.
1347	*/
1348	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1349	#endif
1350	rc = VINF_SUCCESS;
1351
1352	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1353	return rc;
1354	}
1355
1356
1357	/**
1358	* \#PF Handler callback for virtual access handler ranges.
1359	*
1360	* Important to realize that a physical page in a range can have aliases, and
1361	* for ALL and WRITE handlers these will also trigger.
1362	*
1363	* @returns VINF_SUCCESS if the handler have carried out the operation.
1364	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1365	* @param pVM Pointer to the VM.
1366	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1367	* @param pvPtr The HC mapping of that address.
1368	* @param pvBuf What the guest is reading/writing.
1369	* @param cbBuf How much it's reading/writing.
1370	* @param enmAccessType The access type.
1371	* @param pvUser User argument.
1372	*/
1373	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1374	PGMACCESSTYPE enmAccessType, void *pvUser)
1375	{
1376	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1377	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1378	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1379
1380	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1381	return VINF_PGM_HANDLER_DO_DEFAULT;
1382	}
1383
1384
1385	/**
1386	* \#PF Handler callback for virtual access handler ranges.
1387	*
1388	* Important to realize that a physical page in a range can have aliases, and
1389	* for ALL and WRITE handlers these will also trigger.
1390	*
1391	* @returns VINF_SUCCESS if the handler have carried out the operation.
1392	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1393	* @param pVM Pointer to the VM.
1394	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1395	* @param pvPtr The HC mapping of that address.
1396	* @param pvBuf What the guest is reading/writing.
1397	* @param cbBuf How much it's reading/writing.
1398	* @param enmAccessType The access type.
1399	* @param pvUser User argument.
1400	*/
1401	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1402	PGMACCESSTYPE enmAccessType, void *pvUser)
1403	{
1404	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1405	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1406	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1407
1408	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1409	return VINF_PGM_HANDLER_DO_DEFAULT;
1410	}
1411
1412
1413	/**
1414	* \#PF Handler callback for virtual access handler ranges.
1415	*
1416	* Important to realize that a physical page in a range can have aliases, and
1417	* for ALL and WRITE handlers these will also trigger.
1418	*
1419	* @returns VINF_SUCCESS if the handler have carried out the operation.
1420	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1421	* @param pVM Pointer to the VM.
1422	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1423	* @param pvPtr The HC mapping of that address.
1424	* @param pvBuf What the guest is reading/writing.
1425	* @param cbBuf How much it's reading/writing.
1426	* @param enmAccessType The access type.
1427	* @param pvUser User argument.
1428	*/
1429	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1430	PGMACCESSTYPE enmAccessType, void *pvUser)
1431	{
1432	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1433	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1434	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1435
1436	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1437	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1438	* should probably also deregister the virtual handler if TR.base/size
1439	* changes while we're in REM. */
1440
1441	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1442	return VINF_PGM_HANDLER_DO_DEFAULT;
1443	}
1444
1445
1446	/**
1447	* Synchronize the shadowed fields in the TSS.
1448	*
1449	* At present we're shadowing the ring-0 stack selector & pointer, and the
1450	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1451	* REM and this function is called both if REM made any changes to the TSS or
1452	* loaded TR.
1453	*
1454	* @returns VBox status code.
1455	* @param pVM Pointer to the VM.
1456	* @param pVCpu Pointer to the VMCPU.
1457	*/
1458	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1459	{
1460	int rc;
1461
1462	if (pVM->selm.s.fDisableMonitoring)
1463	{
1464	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1465	return VINF_SUCCESS;
1466	}
1467
1468	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1469	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1470
1471	/*
1472	* Get TR and extract and store the basic info.
1473	*
1474	* Note! The TSS limit is not checked by the LTR code, so we
1475	* have to be a bit careful with it. We make sure cbTss
1476	* won't be zero if TR is valid and if it's NULL we'll
1477	* make sure cbTss is 0.
1478	*/
1479	CPUMSELREGHID trHid;
1480	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1481	RTGCPTR GCPtrTss = trHid.u64Base;
1482	uint32_t cbTss = trHid.u32Limit;
1483	Assert( (SelTss & X86_SEL_MASK)
1484	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1485	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1486	if (SelTss & X86_SEL_MASK)
1487	{
1488	Assert(!(SelTss & X86_SEL_LDT));
1489	Assert(trHid.Attr.n.u1DescType == 0);
1490	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1491	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1492	if (!++cbTss)
1493	cbTss = UINT32_MAX;
1494	}
1495	else
1496	{
1497	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1498	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1499	cbTss = 0; /* the reset case. */
1500	}
1501	pVM->selm.s.cbGuestTss = cbTss;
1502	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1503	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1504
1505	/*
1506	* Figure out the size of what need to monitor.
1507	*/
1508	/* We're not interested in any 16-bit TSSes. */
1509	uint32_t cbMonitoredTss = cbTss;
1510	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1511	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1512	cbMonitoredTss = 0;
1513
1514	pVM->selm.s.offGuestIoBitmap = 0;
1515	bool fNoRing1Stack = true;
1516	if (cbMonitoredTss)
1517	{
1518	/*
1519	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1520	* If VME is enabled we also want to keep an eye on the interrupt
1521	* redirection bitmap.
1522	*/
1523	VBOXTSS Tss;
1524	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1525	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1526	if ( !(cr4 & X86_CR4_VME)
1527	\|\| ( RT_SUCCESS(rc)
1528	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1529	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1530	)
1531	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1532	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1533	else if (RT_SUCCESS(rc))
1534	{
1535	/*
1536	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1537	* this can be quite a large chunk. We use to skip it earlier and just hope it
1538	* was kind of static...
1539	*
1540	* Update the virtual interrupt redirection bitmap while we're here.
1541	* (It is located in the 32 bytes before TR:offIoBitmap.)
1542	*/
1543	cbMonitoredTss = Tss.offIoBitmap;
1544	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1545
1546	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1547	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1548	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1549	AssertRC(rc);
1550	/** @todo memset the bitmap on failure? */
1551	Log2(("Redirection bitmap:\n"));
1552	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1553	}
1554	else
1555	{
1556	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1557	pVM->selm.s.offGuestIoBitmap = 0;
1558	/** @todo memset the bitmap? */
1559	}
1560
1561	/*
1562	* Update the ring 0 stack selector and base address.
1563	*/
1564	if (RT_SUCCESS(rc))
1565	{
1566	#ifdef LOG_ENABLED
1567	if (LogIsEnabled())
1568	{
1569	uint32_t ssr0, espr0;
1570	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1571	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1572	{
1573	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1574	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1575	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1576	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1577	AssertMsg(ssr0 != Tss.ss0,
1578	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1579	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1580	}
1581	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1582	}
1583	#endif /* LOG_ENABLED */
1584	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1585
1586	/* Update our TSS structure for the guest's ring 1 stack */
1587	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1588	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1589	}
1590	}
1591
1592	/*
1593	* Flush the ring-1 stack and the direct syscall dispatching if we
1594	* cannot obtain SS0:ESP0.
1595	*/
1596	if (fNoRing1Stack)
1597	{
1598	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1599	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1600
1601	/** @todo handle these dependencies better! */
1602	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1603	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1604	}
1605
1606	/*
1607	* Check for monitor changes and apply them.
1608	*/
1609	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1610	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1611	{
1612	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1613	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1614
1615	/* Release the old range first. */
1616	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1617	{
1618	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1619	AssertRC(rc);
1620	}
1621
1622	/* Register the write handler if TS != 0. */
1623	if (cbMonitoredTss != 0)
1624	{
1625	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1626	0, selmR3GuestTSSWriteHandler,
1627	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1628	if (RT_FAILURE(rc))
1629	{
1630	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1631	return rc;
1632	}
1633
1634	/* Update saved Guest TSS info. */
1635	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1636	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1637	pVM->selm.s.GCSelTss = SelTss;
1638	}
1639	else
1640	{
1641	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1642	pVM->selm.s.cbMonitoredGuestTss = 0;
1643	pVM->selm.s.GCSelTss = 0;
1644	}
1645	}
1646
1647	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1648
1649	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1650	return VINF_SUCCESS;
1651	}
1652
1653
1654	/**
1655	* Compares the Guest GDT and LDT with the shadow tables.
1656	* This is a VBOX_STRICT only function.
1657	*
1658	* @returns VBox status code.
1659	* @param pVM Pointer to the VM.
1660	*/
1661	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1662	{
1663	#ifdef VBOX_STRICT
1664	PVMCPU pVCpu = VMMGetCpu(pVM);
1665
1666	/*
1667	* Get GDTR and check for conflict.
1668	*/
1669	VBOXGDTR GDTR;
1670	CPUMGetGuestGDTR(pVCpu, &GDTR);
1671	if (GDTR.cbGdt == 0)
1672	return VINF_SUCCESS;
1673
1674	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1675	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1676
1677	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1678	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1679
1680	/*
1681	* Loop thru the GDT checking each entry.
1682	*/
1683	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1684	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1685	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1686	while (pGDTE < pGDTEEnd)
1687	{
1688	X86DESC GDTEGuest;
1689	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1690	if (RT_SUCCESS(rc))
1691	{
1692	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1693	{
1694	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1695	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1696	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1697	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1698	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1699	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1700	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1701	{
1702	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1703	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1704	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1705	}
1706	}
1707	}
1708
1709	/* Advance to the next descriptor. */
1710	GCPtrGDTEGuest += sizeof(X86DESC);
1711	pGDTE++;
1712	}
1713
1714
1715	/*
1716	* LDT?
1717	*/
1718	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1719	if ((SelLdt & X86_SEL_MASK) == 0)
1720	return VINF_SUCCESS;
1721	if (SelLdt > GDTR.cbGdt)
1722	{
1723	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1724	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1725	}
1726	X86DESC LDTDesc;
1727	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1728	if (RT_FAILURE(rc))
1729	{
1730	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1731	return rc;
1732	}
1733	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(LDTDesc);
1734	unsigned cbLdt = X86DESC_LIMIT(LDTDesc);
1735	if (LDTDesc.Gen.u1Granularity)
1736	cbLdt = (cbLdt << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
1737
1738	/*
1739	* Validate it.
1740	*/
1741	if (!cbLdt)
1742	return VINF_SUCCESS;
1743	/** @todo check what intel does about odd limits. */
1744	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1745	if ( LDTDesc.Gen.u1DescType
1746	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1747	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1748	{
1749	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1750	return VERR_SELM_INVALID_LDT;
1751	}
1752
1753	/*
1754	* Loop thru the LDT checking each entry.
1755	*/
1756	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1757	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1758	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1759	while (pLDTE < pLDTEEnd)
1760	{
1761	X86DESC LDTEGuest;
1762	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1763	if (RT_SUCCESS(rc))
1764	{
1765	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1766	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1767	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1768	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1769	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1770	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1771	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1772	{
1773	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1774	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1775	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1776	}
1777	}
1778
1779	/* Advance to the next descriptor. */
1780	GCPtrLDTEGuest += sizeof(X86DESC);
1781	pLDTE++;
1782	}
1783
1784	#else /* !VBOX_STRICT */
1785	NOREF(pVM);
1786	#endif /* !VBOX_STRICT */
1787
1788	return VINF_SUCCESS;
1789	}
1790
1791
1792	/**
1793	* Validates the RawR0 TSS values against the one in the Guest TSS.
1794	*
1795	* @returns true if it matches.
1796	* @returns false and assertions on mismatch..
1797	* @param pVM Pointer to the VM.
1798	*/
1799	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1800	{
1801	#ifdef VBOX_STRICT
1802	PVMCPU pVCpu = VMMGetCpu(pVM);
1803
1804	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1805	return true;
1806
1807	/*
1808	* Get TR and extract the basic info.
1809	*/
1810	CPUMSELREGHID trHid;
1811	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1812	RTGCPTR GCPtrTss = trHid.u64Base;
1813	uint32_t cbTss = trHid.u32Limit;
1814	Assert( (SelTss & X86_SEL_MASK)
1815	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1816	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1817	if (SelTss & X86_SEL_MASK)
1818	{
1819	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1820	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1821	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1822	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1823	false);
1824	if (!++cbTss)
1825	cbTss = UINT32_MAX;
1826	}
1827	else
1828	{
1829	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1830	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1831	false);
1832	cbTss = 0; /* the reset case. */
1833	}
1834	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1835	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1836	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1837	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1838	false);
1839	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1840	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1841	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1842	false);
1843	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1844	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1845	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1846	false);
1847
1848
1849	/*
1850	* Figure out the size of what need to monitor.
1851	*/
1852	/* We're not interested in any 16-bit TSSes. */
1853	uint32_t cbMonitoredTss = cbTss;
1854	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1855	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1856	cbMonitoredTss = 0;
1857	if (cbMonitoredTss)
1858	{
1859	VBOXTSS Tss;
1860	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1861	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1862	AssertReturn( rc == VINF_SUCCESS
1863	/* Happens early in XP boot during page table switching. */
1864	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
1865	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1866	false);
1867	if ( !(cr4 & X86_CR4_VME)
1868	\|\| ( RT_SUCCESS(rc)
1869	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1870	&& Tss.offIoBitmap > cbTss)
1871	)
1872	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1873	else if (RT_SUCCESS(rc))
1874	{
1875	cbMonitoredTss = Tss.offIoBitmap;
1876	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1877	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1878	false);
1879
1880	/* check the bitmap */
1881	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1882	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1883	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1884	AssertRCReturn(rc, false);
1885	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1886	("offIoBitmap=%#x cbTss=%#x\n"
1887	" Guest: %.32Rhxs\n"
1888	"Shadow: %.32Rhxs\n",
1889	Tss.offIoBitmap, cbTss,
1890	&Tss.IntRedirBitmap[0],
1891	&pVM->selm.s.Tss.IntRedirBitmap[0]),
1892	false);
1893	}
1894	else
1895	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1896
1897	/*
1898	* Check SS0 and ESP0.
1899	*/
1900	if ( !pVM->selm.s.fSyncTSSRing0Stack
1901	&& RT_SUCCESS(rc))
1902	{
1903	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1904	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1905	{
1906	RTGCPHYS GCPhys;
1907	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1908	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1909	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1910	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1911	return false;
1912	}
1913	}
1914	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1915	}
1916	else
1917	{
1918	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1919	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1920	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1921	}
1922
1923
1924
1925	return true;
1926
1927	#else /* !VBOX_STRICT */
1928	NOREF(pVM);
1929	return true;
1930	#endif /* !VBOX_STRICT */
1931	}
1932
1933
1934	/**
1935	* Returns flat address and limit of LDT by LDT selector from guest GDTR.
1936	*
1937	* Fully validate selector.
1938	*
1939	* @returns VBox status.
1940	* @param pVM Pointer to the VM.
1941	* @param SelLdt LDT selector.
1942	* @param ppvLdt Where to store the flat address of LDT.
1943	* @param pcbLimit Where to store LDT limit.
1944	*/
1945	VMMDECL(int) SELMGetLDTFromSel(PVM pVM, RTSEL SelLdt, PRTGCPTR ppvLdt, unsigned *pcbLimit)
1946	{
1947	PVMCPU pVCpu = VMMGetCpu(pVM);
1948
1949	/* Get guest GDTR. */
1950	VBOXGDTR GDTR;
1951	CPUMGetGuestGDTR(pVCpu, &GDTR);
1952
1953	/* Check selector TI and GDT limit. */
1954	if ( (SelLdt & X86_SEL_LDT)
1955	\|\| SelLdt > GDTR.cbGdt)
1956	return VERR_INVALID_SELECTOR;
1957
1958	/* Read descriptor from GC. */
1959	X86DESC Desc;
1960	int rc = PGMPhysSimpleReadGCPtr(pVCpu, (void *)&Desc, (RTGCPTR)(GDTR.pGdt + (SelLdt & X86_SEL_MASK)), sizeof(Desc));
1961	if (RT_FAILURE(rc))
1962	{
1963	/* fatal */
1964	Log(("Can't read LDT descriptor for selector=%04X\n", SelLdt));
1965	return VERR_SELECTOR_NOT_PRESENT;
1966	}
1967
1968	/* Check if LDT descriptor is not present. */
1969	if (Desc.Gen.u1Present == 0)
1970	return VERR_SELECTOR_NOT_PRESENT;
1971
1972	/* Check LDT descriptor type. */
1973	if ( Desc.Gen.u1DescType == 1
1974	\|\| Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1975	return VERR_INVALID_SELECTOR;
1976
1977	/* LDT descriptor is ok. */
1978	if (ppvLdt)
1979	{
1980	*ppvLdt = (RTGCPTR)X86DESC_BASE(Desc);
1981	*pcbLimit = X86DESC_LIMIT(Desc);
1982	}
1983	return VINF_SUCCESS;
1984	}
1985
1986
1987	/**
1988	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
1989	*
1990	* See SELMR3GetSelectorInfo for details.
1991	*
1992	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
1993	*
1994	* @param pVCpu Pointer to the VMCPU.
1995	* @param Sel The selector to get info about.
1996	* @param pSelInfo Where to store the information.
1997	*/
1998	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
1999	{
2000	/*
2001	* Read it from the guest descriptor table.
2002	*/
2003	X86DESC64 Desc;
2004	VBOXGDTR Gdtr;
2005	RTGCPTR GCPtrDesc;
2006	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2007	if (!(Sel & X86_SEL_LDT))
2008	{
2009	/* GDT */
2010	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2011	return VERR_INVALID_SELECTOR;
2012	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2013	}
2014	else
2015	{
2016	/*
2017	* LDT - must locate the LDT first.
2018	*/
2019	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2020	if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? / /* @todo r=bird: No, I don't think so */
2021	\|\| (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2022	return VERR_INVALID_SELECTOR;
2023	GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2024	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2025	if (RT_FAILURE(rc))
2026	return rc;
2027
2028	/* validate the LDT descriptor. */
2029	if (Desc.Gen.u1Present == 0)
2030	return VERR_SELECTOR_NOT_PRESENT;
2031	if ( Desc.Gen.u1DescType == 1
2032	\|\| Desc.Gen.u4Type != AMD64_SEL_TYPE_SYS_LDT)
2033	return VERR_INVALID_SELECTOR;
2034
2035	uint32_t cbLimit = X86DESC_LIMIT(Desc);
2036	if (Desc.Gen.u1Granularity)
2037	cbLimit = (cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
2038	if ((uint32_t)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2039	return VERR_INVALID_SELECTOR;
2040
2041	/* calc the descriptor location. */
2042	GCPtrDesc = X86DESC64_BASE(Desc);
2043	GCPtrDesc += (Sel & X86_SEL_MASK);
2044	}
2045
2046	/* read the descriptor. */
2047	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2048	if (RT_FAILURE(rc))
2049	{
2050	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2051	if (RT_FAILURE(rc))
2052	return rc;
2053	Desc.au64[1] = 0;
2054	}
2055
2056	/*
2057	* Extract the base and limit
2058	* (We ignore the present bit here, which is probably a bit silly...)
2059	*/
2060	pSelInfo->Sel = Sel;
2061	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2062	pSelInfo->u.Raw64 = Desc;
2063	if (Desc.Gen.u1DescType)
2064	{
2065	/*
2066	* 64-bit code selectors are wide open, it's not possible to detect
2067	* 64-bit data or stack selectors without also dragging in assumptions
2068	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2069	* the selinfo user needs to deal with this in the context the info is
2070	* used unfortunately.
2071	*/
2072	if ( Desc.Gen.u1Long
2073	&& !Desc.Gen.u1DefBig
2074	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2075	{
2076	/* Note! We ignore the segment limit hacks that was added by AMD. */
2077	pSelInfo->GCPtrBase = 0;
2078	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2079	}
2080	else
2081	{
2082	pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2083	if (Desc.Gen.u1Granularity)
2084	pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
2085	pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2086	}
2087	pSelInfo->SelGate = 0;
2088	}
2089	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2090	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2091	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2092	{
2093	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2094	in the AMD manual here as a simplification. */
2095	pSelInfo->GCPtrBase = X86DESC64_BASE(Desc);
2096	pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2097	if (Desc.Gen.u1Granularity)
2098	pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
2099	pSelInfo->SelGate = 0;
2100	}
2101	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2102	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2103	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2104	{
2105	pSelInfo->cbLimit = X86DESC64_BASE(Desc);
2106	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2107	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2108	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2109	pSelInfo->SelGate = Desc.Gate.u16Sel;
2110	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2111	}
2112	else
2113	{
2114	pSelInfo->cbLimit = 0;
2115	pSelInfo->GCPtrBase = 0;
2116	pSelInfo->SelGate = 0;
2117	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2118	}
2119	if (!Desc.Gen.u1Present)
2120	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2121
2122	return VINF_SUCCESS;
2123	}
2124
2125
2126	/**
2127	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2128	* interprets a legacy descriptor table entry and fills in the selector info
2129	* structure from it.
2130	*
2131	* @param pSelInfo Where to store the selector info. Only the fFlags and
2132	* Sel members have been initialized.
2133	* @param pDesc The legacy descriptor to parse.
2134	*/
2135	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2136	{
2137	pSelInfo->u.Raw64.au64[1] = 0;
2138	pSelInfo->u.Raw = *pDesc;
2139	if ( pDesc->Gen.u1DescType
2140	\|\| !(pDesc->Gen.u4Type & 4))
2141	{
2142	pSelInfo->cbLimit = X86DESC_LIMIT(*pDesc);
2143	if (pDesc->Gen.u1Granularity)
2144	pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
2145	pSelInfo->GCPtrBase = X86DESC_BASE(*pDesc);
2146	pSelInfo->SelGate = 0;
2147	}
2148	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2149	{
2150	pSelInfo->cbLimit = 0;
2151	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2152	pSelInfo->GCPtrBase = 0;
2153	else
2154	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2155	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2156	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2157	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2158	}
2159	else
2160	{
2161	pSelInfo->cbLimit = 0;
2162	pSelInfo->GCPtrBase = 0;
2163	pSelInfo->SelGate = 0;
2164	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2165	}
2166	if (!pDesc->Gen.u1Present)
2167	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2168	}
2169
2170
2171	/**
2172	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2173	*
2174	* See SELMR3GetSelectorInfo for details.
2175	*
2176	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2177	*
2178	* @param pVM Pointer to the VM.
2179	* @param pVCpu Pointer to the VMCPU.
2180	* @param Sel The selector to get info about.
2181	* @param pSelInfo Where to store the information.
2182	*/
2183	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2184	{
2185	/*
2186	* Read the descriptor entry
2187	*/
2188	pSelInfo->fFlags = 0;
2189	X86DESC Desc;
2190	if ( !(Sel & X86_SEL_LDT)
2191	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2192	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2193	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2194	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2195	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK))
2196	)
2197	{
2198	/*
2199	* Hypervisor descriptor.
2200	*/
2201	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2202	if (CPUMIsGuestInProtectedMode(pVCpu))
2203	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2204	else
2205	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2206
2207	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2208	}
2209	else if (CPUMIsGuestInProtectedMode(pVCpu))
2210	{
2211	/*
2212	* Read it from the guest descriptor table.
2213	*/
2214	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2215
2216	VBOXGDTR Gdtr;
2217	RTGCPTR GCPtrDesc;
2218	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2219	if (!(Sel & X86_SEL_LDT))
2220	{
2221	/* GDT */
2222	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2223	return VERR_INVALID_SELECTOR;
2224	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2225	}
2226	else
2227	{
2228	/*
2229	* LDT - must locate the LDT first...
2230	*/
2231	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2232	if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? / /* @todo r=bird: No, I don't think so */
2233	\|\| (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2234	return VERR_INVALID_SELECTOR;
2235	GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2236	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2237	if (RT_FAILURE(rc))
2238	return rc;
2239
2240	/* validate the LDT descriptor. */
2241	if (Desc.Gen.u1Present == 0)
2242	return VERR_SELECTOR_NOT_PRESENT;
2243	if ( Desc.Gen.u1DescType == 1
2244	\|\| Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2245	return VERR_INVALID_SELECTOR;
2246
2247	unsigned cbLimit = X86DESC_LIMIT(Desc);
2248	if (Desc.Gen.u1Granularity)
2249	cbLimit = (cbLimit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
2250	if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2251	return VERR_INVALID_SELECTOR;
2252
2253	/* calc the descriptor location. */
2254	GCPtrDesc = X86DESC_BASE(Desc);
2255	GCPtrDesc += (Sel & X86_SEL_MASK);
2256	}
2257
2258	/* read the descriptor. */
2259	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2260	if (RT_FAILURE(rc))
2261	return rc;
2262	}
2263	else
2264	{
2265	/*
2266	* We're in real mode.
2267	*/
2268	pSelInfo->Sel = Sel;
2269	pSelInfo->GCPtrBase = Sel << 4;
2270	pSelInfo->cbLimit = 0xffff;
2271	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2272	pSelInfo->u.Raw64.au64[0] = 0;
2273	pSelInfo->u.Raw64.au64[1] = 0;
2274	pSelInfo->SelGate = 0;
2275	return VINF_SUCCESS;
2276	}
2277
2278	/*
2279	* Extract the base and limit or sel:offset for gates.
2280	*/
2281	pSelInfo->Sel = Sel;
2282	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2283
2284	return VINF_SUCCESS;
2285	}
2286
2287
2288	/**
2289	* Gets information about a selector.
2290	*
2291	* Intended for the debugger mostly and will prefer the guest descriptor tables
2292	* over the shadow ones.
2293	*
2294	* @retval VINF_SUCCESS on success.
2295	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2296	* descriptor table.
2297	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2298	* is not returned if the selector itself isn't present, you have to
2299	* check that for yourself (see DBGFSELINFO::fFlags).
2300	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2301	* pagetable or page backing the selector table wasn't present.
2302	* @returns Other VBox status code on other errors.
2303	*
2304	* @param pVM Pointer to the VM.
2305	* @param pVCpu Pointer to the VMCPU.
2306	* @param Sel The selector to get info about.
2307	* @param pSelInfo Where to store the information.
2308	*/
2309	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2310	{
2311	AssertPtr(pSelInfo);
2312	if (CPUMIsGuestInLongMode(pVCpu))
2313	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2314	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2315	}
2316
2317
2318	/**
2319	* Gets information about a selector from the shadow tables.
2320	*
2321	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2322	* requires that the caller ensures that the shadow tables are up to date.
2323	*
2324	* @retval VINF_SUCCESS on success.
2325	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2326	* descriptor table.
2327	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2328	* is not returned if the selector itself isn't present, you have to
2329	* check that for yourself (see DBGFSELINFO::fFlags).
2330	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2331	* pagetable or page backing the selector table wasn't present.
2332	* @returns Other VBox status code on other errors.
2333	*
2334	* @param pVM Pointer to the VM.
2335	* @param Sel The selector to get info about.
2336	* @param pSelInfo Where to store the information.
2337	*
2338	* @remarks Don't use this when in hardware assisted virtualization mode.
2339	*/
2340	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2341	{
2342	Assert(pSelInfo);
2343
2344	/*
2345	* Read the descriptor entry
2346	*/
2347	X86DESC Desc;
2348	if (!(Sel & X86_SEL_LDT))
2349	{
2350	/*
2351	* Global descriptor.
2352	*/
2353	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2354	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2355	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2356	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2357	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2358	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK)
2359	? DBGFSELINFO_FLAGS_HYPER
2360	: 0;
2361	/** @todo check that the GDT offset is valid. */
2362	}
2363	else
2364	{
2365	/*
2366	* Local Descriptor.
2367	*/
2368	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2369	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2370	/** @todo check if the LDT page is actually available. */
2371	/** @todo check that the LDT offset is valid. */
2372	pSelInfo->fFlags = 0;
2373	}
2374	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2375	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2376	else
2377	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2378
2379	/*
2380	* Extract the base and limit or sel:offset for gates.
2381	*/
2382	pSelInfo->Sel = Sel;
2383	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2384
2385	return VINF_SUCCESS;
2386	}
2387
2388
2389	/**
2390	* Formats a descriptor.
2391	*
2392	* @param Desc Descriptor to format.
2393	* @param Sel Selector number.
2394	* @param pszOutput Output buffer.
2395	* @param cchOutput Size of output buffer.
2396	*/
2397	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2398	{
2399	/*
2400	* Make variable description string.
2401	*/
2402	static struct
2403	{
2404	unsigned cch;
2405	const char *psz;
2406	} const aTypes[32] =
2407	{
2408	#define STRENTRY(str) { sizeof(str) - 1, str }
2409	/* system */
2410	STRENTRY("Reserved0 "), /* 0x00 */
2411	STRENTRY("TSS16Avail "), /* 0x01 */
2412	STRENTRY("LDT "), /* 0x02 */
2413	STRENTRY("TSS16Busy "), /* 0x03 */
2414	STRENTRY("Call16 "), /* 0x04 */
2415	STRENTRY("Task "), /* 0x05 */
2416	STRENTRY("Int16 "), /* 0x06 */
2417	STRENTRY("Trap16 "), /* 0x07 */
2418	STRENTRY("Reserved8 "), /* 0x08 */
2419	STRENTRY("TSS32Avail "), /* 0x09 */
2420	STRENTRY("ReservedA "), /* 0x0a */
2421	STRENTRY("TSS32Busy "), /* 0x0b */
2422	STRENTRY("Call32 "), /* 0x0c */
2423	STRENTRY("ReservedD "), /* 0x0d */
2424	STRENTRY("Int32 "), /* 0x0e */
2425	STRENTRY("Trap32 "), /* 0x0f */
2426	/* non system */
2427	STRENTRY("DataRO "), /* 0x10 */
2428	STRENTRY("DataRO Accessed "), /* 0x11 */
2429	STRENTRY("DataRW "), /* 0x12 */
2430	STRENTRY("DataRW Accessed "), /* 0x13 */
2431	STRENTRY("DataDownRO "), /* 0x14 */
2432	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2433	STRENTRY("DataDownRW "), /* 0x16 */
2434	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2435	STRENTRY("CodeEO "), /* 0x18 */
2436	STRENTRY("CodeEO Accessed "), /* 0x19 */
2437	STRENTRY("CodeER "), /* 0x1a */
2438	STRENTRY("CodeER Accessed "), /* 0x1b */
2439	STRENTRY("CodeConfEO "), /* 0x1c */
2440	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2441	STRENTRY("CodeConfER "), /* 0x1e */
2442	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2443	#undef SYSENTRY
2444	};
2445	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2446	char szMsg[128];
2447	char *psz = &szMsg[0];
2448	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2449	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2450	psz += aTypes[i].cch;
2451
2452	if (Desc.Gen.u1Present)
2453	ADD_STR(psz, "Present ");
2454	else
2455	ADD_STR(psz, "Not-Present ");
2456	if (Desc.Gen.u1Granularity)
2457	ADD_STR(psz, "Page ");
2458	if (Desc.Gen.u1DefBig)
2459	ADD_STR(psz, "32-bit ");
2460	else
2461	ADD_STR(psz, "16-bit ");
2462	#undef ADD_STR
2463	*psz = '\0';
2464
2465	/*
2466	* Limit and Base and format the output.
2467	*/
2468	uint32_t u32Limit = X86DESC_LIMIT(Desc);
2469	if (Desc.Gen.u1Granularity)
2470	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
2471	uint32_t u32Base = X86DESC_BASE(Desc);
2472
2473	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2474	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2475	}
2476
2477
2478	/**
2479	* Dumps a descriptor.
2480	*
2481	* @param Desc Descriptor to dump.
2482	* @param Sel Selector number.
2483	* @param pszMsg Message to prepend the log entry with.
2484	*/
2485	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2486	{
2487	char szOutput[128];
2488	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2489	Log(("%s: %s\n", pszMsg, szOutput));
2490	NOREF(szOutput[0]);
2491	}
2492
2493
2494	/**
2495	* Display the shadow gdt.
2496	*
2497	* @param pVM Pointer to the VM.
2498	* @param pHlp The info helpers.
2499	* @param pszArgs Arguments, ignored.
2500	*/
2501	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2502	{
2503	NOREF(pszArgs);
2504	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2505	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2506	{
2507	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2508	{
2509	char szOutput[128];
2510	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2511	const char *psz = "";
2512	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2513	psz = " HyperCS";
2514	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2515	psz = " HyperDS";
2516	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2517	psz = " HyperCS64";
2518	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2519	psz = " HyperTSS";
2520	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2521	psz = " HyperTSSTrap08";
2522	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2523	}
2524	}
2525	}
2526
2527
2528	/**
2529	* Display the guest gdt.
2530	*
2531	* @param pVM Pointer to the VM.
2532	* @param pHlp The info helpers.
2533	* @param pszArgs Arguments, ignored.
2534	*/
2535	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2536	{
2537	/** @todo SMP support! */
2538	PVMCPU pVCpu = &pVM->aCpus[0];
2539
2540	VBOXGDTR GDTR;
2541	CPUMGetGuestGDTR(pVCpu, &GDTR);
2542	RTGCPTR GCPtrGDT = GDTR.pGdt;
2543	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2544
2545	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2546	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2547	{
2548	X86DESC GDTE;
2549	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2550	if (RT_SUCCESS(rc))
2551	{
2552	if (GDTE.Gen.u1Present)
2553	{
2554	char szOutput[128];
2555	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2556	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2557	}
2558	}
2559	else if (rc == VERR_PAGE_NOT_PRESENT)
2560	{
2561	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2562	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2563	}
2564	else
2565	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2566	}
2567	NOREF(pszArgs);
2568	}
2569
2570
2571	/**
2572	* Display the shadow ldt.
2573	*
2574	* @param pVM Pointer to the VM.
2575	* @param pHlp The info helpers.
2576	* @param pszArgs Arguments, ignored.
2577	*/
2578	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2579	{
2580	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2581	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2582	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2583	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2584	{
2585	if (paLDT[iLDT].Gen.u1Present)
2586	{
2587	char szOutput[128];
2588	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2589	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2590	}
2591	}
2592	NOREF(pszArgs);
2593	}
2594
2595
2596	/**
2597	* Display the guest ldt.
2598	*
2599	* @param pVM Pointer to the VM.
2600	* @param pHlp The info helpers.
2601	* @param pszArgs Arguments, ignored.
2602	*/
2603	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2604	{
2605	/** @todo SMP support! */
2606	PVMCPU pVCpu = &pVM->aCpus[0];
2607
2608	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2609	if (!(SelLdt & X86_SEL_MASK))
2610	{
2611	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2612	return;
2613	}
2614
2615	RTGCPTR GCPtrLdt;
2616	unsigned cbLdt;
2617	int rc = SELMGetLDTFromSel(pVM, SelLdt, &GCPtrLdt, &cbLdt);
2618	if (RT_FAILURE(rc))
2619	{
2620	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): rc=%Rrc\n", SelLdt, rc);
2621	return;
2622	}
2623
2624	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RGv limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2625	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2626	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2627	{
2628	X86DESC LdtE;
2629	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2630	if (RT_SUCCESS(rc))
2631	{
2632	if (LdtE.Gen.u1Present)
2633	{
2634	char szOutput[128];
2635	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2636	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2637	}
2638	}
2639	else if (rc == VERR_PAGE_NOT_PRESENT)
2640	{
2641	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2642	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2643	}
2644	else
2645	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2646	}
2647	NOREF(pszArgs);
2648	}
2649
2650
2651	/**
2652	* Dumps the hypervisor GDT
2653	*
2654	* @param pVM Pointer to the VM.
2655	*/
2656	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2657	{
2658	DBGFR3Info(pVM, "gdt", NULL, NULL);
2659	}
2660
2661
2662	/**
2663	* Dumps the hypervisor LDT
2664	*
2665	* @param pVM Pointer to the VM.
2666	*/
2667	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2668	{
2669	DBGFR3Info(pVM, "ldt", NULL, NULL);
2670	}
2671
2672
2673	/**
2674	* Dumps the guest GDT
2675	*
2676	* @param pVM Pointer to the VM.
2677	*/
2678	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2679	{
2680	DBGFR3Info(pVM, "gdtguest", NULL, NULL);
2681	}
2682
2683
2684	/**
2685	* Dumps the guest LDT
2686	*
2687	* @param pVM Pointer to the VM.
2688	*/
2689	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2690	{
2691	DBGFR3Info(pVM, "ldtguest", NULL, NULL);
2692	}
2693

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 42372

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