VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 45026

Last change on this file since 45026 was 44528, checked in by vboxsync, 12 years ago

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1/* $Id: SELM.cpp 44528 2013-02-04 14:27:54Z vboxsync $ */
2/** @file
3 * SELM - The Selector Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_selm SELM - The Selector Manager
19 *
20 * SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21 * of a few hyper selector for the raw-mode context. In the hardware assisted
22 * virtualization mode its only task is to decode entries in the guest GDT or
23 * LDT once in a while.
24 *
25 * @see grp_selm
26 *
27 *
28 * @section seg_selm_shadowing Shadowing
29 *
30 * SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31 * work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32 * The idea is to do it in a more on-demand fashion when we get time. There
33 * also a whole bunch of issues with the current synchronization of all three
34 * tables, see notes and todos in the code.
35 *
36 * When the guest makes changes to the GDT we will try update the shadow copy
37 * without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38 *
39 * When the guest make LDT changes we'll trigger a full resync of the LDT
40 * (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41 *
42 * The TSS shadowing is limited to the fields we need to care about, namely SS0
43 * and ESP0. The Patch Manager makes use of these. We monitor updates to the
44 * guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45 * rather than go the SELMR3SyncTSS() route.
46 *
47 * When in raw-mode SELM also injects a few extra GDT selectors which are used
48 * by the raw-mode (hyper) context. These start their life at the high end of
49 * the table and will be relocated when the guest tries to make use of them...
50 * Well, that was that idea at least, only the code isn't quite there yet which
51 * is why we have trouble with guests which actually have a full sized GDT.
52 *
53 * So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54 * lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55 *
56 */
57
58/*******************************************************************************
59* Header Files *
60*******************************************************************************/
61#define LOG_GROUP LOG_GROUP_SELM
62#include <VBox/vmm/selm.h>
63#include <VBox/vmm/cpum.h>
64#include <VBox/vmm/stam.h>
65#include <VBox/vmm/mm.h>
66#include <VBox/vmm/ssm.h>
67#include <VBox/vmm/pgm.h>
68#include <VBox/vmm/trpm.h>
69#include <VBox/vmm/dbgf.h>
70#include "SELMInternal.h"
71#include <VBox/vmm/vm.h>
72#include <VBox/err.h>
73#include <VBox/param.h>
74
75#include <iprt/assert.h>
76#include <VBox/log.h>
77#include <iprt/asm.h>
78#include <iprt/string.h>
79#include <iprt/thread.h>
80#include <iprt/string.h>
81
82
83/**
84 * Enable or disable tracking of Shadow GDT/LDT/TSS.
85 * @{
86 */
87#define SELM_TRACK_SHADOW_GDT_CHANGES
88#define SELM_TRACK_SHADOW_LDT_CHANGES
89#define SELM_TRACK_SHADOW_TSS_CHANGES
90/** @} */
91
92
93/** SELM saved state version. */
94#define SELM_SAVED_STATE_VERSION 5
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
101static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
102static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
103static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
104static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
105static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
106static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112
113
114/*******************************************************************************
115* Global Variables *
116*******************************************************************************/
117#ifdef LOG_ENABLED
118/** Segment register names. */
119static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
120#endif
121
122
123/**
124 * Initializes the SELM.
125 *
126 * @returns VBox status code.
127 * @param pVM Pointer to the VM.
128 */
129VMMR3DECL(int) SELMR3Init(PVM pVM)
130{
131 LogFlow(("SELMR3Init\n"));
132
133 /*
134 * Assert alignment and sizes.
135 * (The TSS block requires contiguous back.)
136 */
137 AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
138 AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
139#if 0 /* doesn't work */
140 AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
141 AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
142#endif
143 AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
144 AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
145 AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
146
147 /*
148 * Init the structure.
149 */
150 pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
151 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
152 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
153 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
154 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
155 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
156
157 /*
158 * Allocate GDT table.
159 */
160 int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
161 PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
162 AssertRCReturn(rc, rc);
163
164 /*
165 * Allocate LDT area.
166 */
167 rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
168 AssertRCReturn(rc, rc);
169
170 /*
171 * Init Guest's and Shadow GDT, LDT, TSS changes control variables.
172 */
173 pVM->selm.s.cbEffGuestGdtLimit = 0;
174 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
175 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
176 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
177
178 pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
179 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
180 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
181 pVM->selm.s.GCSelTss = RTSEL_MAX;
182
183 pVM->selm.s.fDisableMonitoring = false;
184 pVM->selm.s.fSyncTSSRing0Stack = false;
185
186 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
187 * for I/O operations. */
188 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
189 /* bit set to 1 means no redirection */
190 memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
191
192 /*
193 * Register the saved state data unit.
194 */
195 rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
196 NULL, NULL, NULL,
197 NULL, selmR3Save, NULL,
198 NULL, selmR3Load, selmR3LoadDone);
199 if (RT_FAILURE(rc))
200 return rc;
201
202 /*
203 * Statistics.
204 */
205 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
206 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
207 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
208 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
209 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
210 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
211 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
212 STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
213 STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
214
215 STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
216 STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
217
218 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
219 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
220 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
221 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
222 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
223 STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
224
225 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
226 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
227 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
228 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
229 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
230 STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
231
232 STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
233
234 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
235 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
236 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
237 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
238 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
239 STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
240
241 STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
242 STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
243 STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
244 STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
245
246 /*
247 * Default action when entering raw mode for the first time
248 */
249 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
250 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
251 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
252 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
253
254 /*
255 * Register info handlers.
256 */
257 DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
258 DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
259 DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
260 DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
261 //DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
262 //DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
263
264 return rc;
265}
266
267
268/**
269 * Finalizes HMA page attributes.
270 *
271 * @returns VBox status code.
272 * @param pVM Pointer to the VM.
273 */
274VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
275{
276 /** @cfgm{/DoubleFault,bool,false}
277 * Enables catching of double faults in the raw-mode context VMM code. This can
278 * be used when the triple faults or hangs occur and one suspect an unhandled
279 * double fault. This is not enabled by default because it means making the
280 * hyper selectors writeable for all supervisor code, including the guest's.
281 * The double fault is a task switch and thus requires write access to the GDT
282 * of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
283 * 8 TSS for the back link.
284 */
285 bool f;
286#if defined(DEBUG_bird)
287 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
288#else
289 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
290#endif
291 AssertLogRelRCReturn(rc, rc);
292 if (f)
293 {
294 PX86DESC paGdt = pVM->selm.s.paGdtR3;
295 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
296 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
297 AssertRC(rc);
298 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
299 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
300 AssertRC(rc);
301 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
302 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
303 AssertRC(rc);
304 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
305 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
306 AssertRC(rc);
307 }
308 return VINF_SUCCESS;
309}
310
311
312/**
313 * Setup the hypervisor GDT selectors in our shadow table
314 *
315 * @param pVM Pointer to the VM.
316 */
317static void selmR3SetupHyperGDTSelectors(PVM pVM)
318{
319 PX86DESC paGdt = pVM->selm.s.paGdtR3;
320
321 /*
322 * Set up global code and data descriptors for use in the guest context.
323 * Both are wide open (base 0, limit 4GB)
324 */
325 PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
326 pDesc->Gen.u16LimitLow = 0xffff;
327 pDesc->Gen.u4LimitHigh = 0xf;
328 pDesc->Gen.u16BaseLow = 0;
329 pDesc->Gen.u8BaseHigh1 = 0;
330 pDesc->Gen.u8BaseHigh2 = 0;
331 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
332 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
333 pDesc->Gen.u2Dpl = 0; /* supervisor */
334 pDesc->Gen.u1Present = 1;
335 pDesc->Gen.u1Available = 0;
336 pDesc->Gen.u1Long = 0;
337 pDesc->Gen.u1DefBig = 1; /* def 32 bit */
338 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
339
340 /* data */
341 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
342 pDesc->Gen.u16LimitLow = 0xffff;
343 pDesc->Gen.u4LimitHigh = 0xf;
344 pDesc->Gen.u16BaseLow = 0;
345 pDesc->Gen.u8BaseHigh1 = 0;
346 pDesc->Gen.u8BaseHigh2 = 0;
347 pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
348 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
349 pDesc->Gen.u2Dpl = 0; /* supervisor */
350 pDesc->Gen.u1Present = 1;
351 pDesc->Gen.u1Available = 0;
352 pDesc->Gen.u1Long = 0;
353 pDesc->Gen.u1DefBig = 1; /* big */
354 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
355
356 /* 64-bit mode code (& data?) */
357 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
358 pDesc->Gen.u16LimitLow = 0xffff;
359 pDesc->Gen.u4LimitHigh = 0xf;
360 pDesc->Gen.u16BaseLow = 0;
361 pDesc->Gen.u8BaseHigh1 = 0;
362 pDesc->Gen.u8BaseHigh2 = 0;
363 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
364 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
365 pDesc->Gen.u2Dpl = 0; /* supervisor */
366 pDesc->Gen.u1Present = 1;
367 pDesc->Gen.u1Available = 0;
368 pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
369 pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
370 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
371
372 /*
373 * TSS descriptor
374 */
375 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
376 RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
377 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
378 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
379 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
380 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
381 pDesc->Gen.u4LimitHigh = 0;
382 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
383 pDesc->Gen.u1DescType = 0; /* system */
384 pDesc->Gen.u2Dpl = 0; /* supervisor */
385 pDesc->Gen.u1Present = 1;
386 pDesc->Gen.u1Available = 0;
387 pDesc->Gen.u1Long = 0;
388 pDesc->Gen.u1DefBig = 0;
389 pDesc->Gen.u1Granularity = 0; /* byte limit */
390
391 /*
392 * TSS descriptor for trap 08
393 */
394 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
395 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
396 pDesc->Gen.u4LimitHigh = 0;
397 RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
398 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
399 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
400 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
401 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
402 pDesc->Gen.u1DescType = 0; /* system */
403 pDesc->Gen.u2Dpl = 0; /* supervisor */
404 pDesc->Gen.u1Present = 1;
405 pDesc->Gen.u1Available = 0;
406 pDesc->Gen.u1Long = 0;
407 pDesc->Gen.u1DefBig = 0;
408 pDesc->Gen.u1Granularity = 0; /* byte limit */
409}
410
411/**
412 * Applies relocations to data and code managed by this
413 * component. This function will be called at init and
414 * whenever the VMM need to relocate it self inside the GC.
415 *
416 * @param pVM The VM.
417 */
418VMMR3DECL(void) SELMR3Relocate(PVM pVM)
419{
420 PX86DESC paGdt = pVM->selm.s.paGdtR3;
421 LogFlow(("SELMR3Relocate\n"));
422
423 for (VMCPUID i = 0; i < pVM->cCpus; i++)
424 {
425 PVMCPU pVCpu = &pVM->aCpus[i];
426
427 /*
428 * Update GDTR and selector.
429 */
430 CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
431
432 /** @todo selector relocations should be a separate operation? */
433 CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
434 CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
435 CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
436 CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
437 CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
438 }
439
440 selmR3SetupHyperGDTSelectors(pVM);
441
442/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
443/** @todo PGM knows the proper CR3 values these days, not CPUM. */
444 /*
445 * Update the TSSes.
446 */
447 /* Only applies to raw mode which supports only 1 VCPU */
448 PVMCPU pVCpu = &pVM->aCpus[0];
449
450 /* Current TSS */
451 pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
452 pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
453 pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
454 pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
455 pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
456 pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
457 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
458
459 /* trap 08 */
460 pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
461 pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
462 pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
463 pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
464 pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
465 pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
466 pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
467 pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
468 pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
469 pVM->selm.s.TssTrap08.fs = 0;
470 pVM->selm.s.TssTrap08.gs = 0;
471 pVM->selm.s.TssTrap08.selLdt = 0;
472 pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
473 pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
474 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
475 pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
476 pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
477 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
478 pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
479 pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
480 /* TRPM will be updating the eip */
481
482 if ( !pVM->selm.s.fDisableMonitoring
483 && !VMMIsHwVirtExtForced(pVM))
484 {
485 /*
486 * Update shadow GDT/LDT/TSS write access handlers.
487 */
488 int rc;
489#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
490 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
491 {
492 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
493 AssertRC(rc);
494 }
495 pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
496 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
497 pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
498 0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
499 AssertRC(rc);
500#endif
501#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
502 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
503 {
504 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
505 AssertRC(rc);
506 }
507 pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
508 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
509 pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
510 0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
511 AssertRC(rc);
512#endif
513
514 /*
515 * Update the GC LDT region handler and address.
516 */
517#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
518 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
519 {
520 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
521 AssertRC(rc);
522 }
523#endif
524 pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
525#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
526 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
527 pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
528 0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
529 AssertRC(rc);
530#endif
531 }
532}
533
534
535/**
536 * Terminates the SELM.
537 *
538 * Termination means cleaning up and freeing all resources,
539 * the VM it self is at this point powered off or suspended.
540 *
541 * @returns VBox status code.
542 * @param pVM Pointer to the VM.
543 */
544VMMR3DECL(int) SELMR3Term(PVM pVM)
545{
546 NOREF(pVM);
547 return 0;
548}
549
550
551/**
552 * The VM is being reset.
553 *
554 * For the SELM component this means that any GDT/LDT/TSS monitors
555 * needs to be removed.
556 *
557 * @param pVM Pointer to the VM.
558 */
559VMMR3DECL(void) SELMR3Reset(PVM pVM)
560{
561 LogFlow(("SELMR3Reset:\n"));
562 VM_ASSERT_EMT(pVM);
563
564 /*
565 * Uninstall guest GDT/LDT/TSS write access handlers.
566 */
567 int rc;
568 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
569 {
570 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
571 AssertRC(rc);
572 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
573 pVM->selm.s.GuestGdtr.cbGdt = 0;
574 }
575 pVM->selm.s.fGDTRangeRegistered = false;
576 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
577 {
578 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
579 AssertRC(rc);
580 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
581 }
582 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
583 {
584 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
585 AssertRC(rc);
586 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
587 pVM->selm.s.GCSelTss = RTSEL_MAX;
588 }
589
590 /*
591 * Re-initialize other members.
592 */
593 pVM->selm.s.cbLdtLimit = 0;
594 pVM->selm.s.offLdtHyper = 0;
595 pVM->selm.s.cbMonitoredGuestTss = 0;
596
597 pVM->selm.s.fSyncTSSRing0Stack = false;
598
599 /*
600 * Default action when entering raw mode for the first time
601 */
602 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
603 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
604 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
605 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
606}
607
608/**
609 * Disable GDT/LDT/TSS monitoring and syncing
610 *
611 * @param pVM Pointer to the VM.
612 */
613VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
614{
615 /*
616 * Uninstall guest GDT/LDT/TSS write access handlers.
617 */
618 int rc;
619 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
620 {
621 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
622 AssertRC(rc);
623 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
624 pVM->selm.s.GuestGdtr.cbGdt = 0;
625 }
626 pVM->selm.s.fGDTRangeRegistered = false;
627 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
628 {
629 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
630 AssertRC(rc);
631 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
632 }
633 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
634 {
635 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
636 AssertRC(rc);
637 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
638 pVM->selm.s.GCSelTss = RTSEL_MAX;
639 }
640
641 /*
642 * Unregister shadow GDT/LDT/TSS write access handlers.
643 */
644#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
645 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
646 {
647 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
648 AssertRC(rc);
649 pVM->selm.s.paGdtRC = NIL_RTRCPTR;
650 }
651#endif
652#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
653 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
654 {
655 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
656 AssertRC(rc);
657 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
658 }
659#endif
660#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
661 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
662 {
663 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
664 AssertRC(rc);
665 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
666 }
667#endif
668
669 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
670 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
671 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
672 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
673
674 pVM->selm.s.fDisableMonitoring = true;
675}
676
677
678/**
679 * Execute state save operation.
680 *
681 * @returns VBox status code.
682 * @param pVM Pointer to the VM.
683 * @param pSSM SSM operation handle.
684 */
685static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
686{
687 LogFlow(("selmR3Save:\n"));
688
689 /*
690 * Save the basic bits - fortunately all the other things can be resynced on load.
691 */
692 PSELM pSelm = &pVM->selm.s;
693
694 SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
695 SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
696 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
697 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
698 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
699 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
700 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
701 return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
702}
703
704
705/**
706 * Execute state load operation.
707 *
708 * @returns VBox status code.
709 * @param pVM Pointer to the VM.
710 * @param pSSM SSM operation handle.
711 * @param uVersion Data layout version.
712 * @param uPass The data pass.
713 */
714static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
715{
716 LogFlow(("selmR3Load:\n"));
717 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
718
719 /*
720 * Validate version.
721 */
722 if (uVersion != SELM_SAVED_STATE_VERSION)
723 {
724 AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
725 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
726 }
727
728 /*
729 * Do a reset.
730 */
731 SELMR3Reset(pVM);
732
733 /* Get the monitoring flag. */
734 SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
735
736 /* Get the TSS state flag. */
737 SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
738
739 /*
740 * Get the selectors.
741 */
742 RTSEL SelCS;
743 SSMR3GetSel(pSSM, &SelCS);
744 RTSEL SelDS;
745 SSMR3GetSel(pSSM, &SelDS);
746 RTSEL SelCS64;
747 SSMR3GetSel(pSSM, &SelCS64);
748 RTSEL SelDS64;
749 SSMR3GetSel(pSSM, &SelDS64);
750 RTSEL SelTSS;
751 SSMR3GetSel(pSSM, &SelTSS);
752 RTSEL SelTSSTrap08;
753 SSMR3GetSel(pSSM, &SelTSSTrap08);
754
755 /* Copy the selectors; they will be checked during relocation. */
756 PSELM pSelm = &pVM->selm.s;
757 pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
758 pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
759 pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
760 pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
761 pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
762
763 return VINF_SUCCESS;
764}
765
766
767/**
768 * Sync the GDT, LDT and TSS after loading the state.
769 *
770 * Just to play save, we set the FFs to force syncing before
771 * executing GC code.
772 *
773 * @returns VBox status code.
774 * @param pVM Pointer to the VM.
775 * @param pSSM SSM operation handle.
776 */
777static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
778{
779 PVMCPU pVCpu = VMMGetCpu(pVM);
780
781 LogFlow(("selmR3LoadDone:\n"));
782
783 /*
784 * Don't do anything if it's a load failure.
785 */
786 int rc = SSMR3HandleGetStatus(pSSM);
787 if (RT_FAILURE(rc))
788 return VINF_SUCCESS;
789
790 /*
791 * Do the syncing if we're in protected mode.
792 */
793 if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
794 {
795 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
796 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
797 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
798 SELMR3UpdateFromCPUM(pVM, pVCpu);
799 }
800
801 /*
802 * Flag everything for resync on next raw mode entry.
803 */
804 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
805 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
806 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
807
808 return VINF_SUCCESS;
809}
810
811#ifdef VBOX_WITH_RAW_MODE
812
813/**
814 * Updates (syncs) the shadow GDT.
815 *
816 * @returns VBox status code.
817 * @param pVM The VM handle.
818 * @param pVCpu The current virtual CPU.
819 */
820static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
821{
822 /*
823 * Always assume the best...
824 */
825 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
826
827 /* If the GDT was changed, then make sure the LDT is checked too */
828 /** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
829 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
830 /* Same goes for the TSS selector */
831 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
832
833 /*
834 * Get the GDTR and check if there is anything to do (there usually is).
835 */
836 VBOXGDTR GDTR;
837 CPUMGetGuestGDTR(pVCpu, &GDTR);
838 if (GDTR.cbGdt < sizeof(X86DESC))
839 {
840 Log(("No GDT entries...\n"));
841 return VINF_SUCCESS;
842 }
843
844 /*
845 * Read the Guest GDT.
846 * ASSUMES that the entire GDT is in memory.
847 */
848 RTUINT cbEffLimit = GDTR.cbGdt;
849 PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
850 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
851 if (RT_FAILURE(rc))
852 {
853 /*
854 * Read it page by page.
855 *
856 * Keep track of the last valid page and delay memsets and
857 * adjust cbEffLimit to reflect the effective size. The latter
858 * is something we do in the belief that the guest will probably
859 * never actually commit the last page, thus allowing us to keep
860 * our selectors in the high end of the GDT.
861 */
862 RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
863 RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
864 uint8_t *pu8Dst = (uint8_t *)&pVM->selm.s.paGdtR3[1];
865 uint8_t *pu8DstInvalid = pu8Dst;
866
867 while (cbLeft)
868 {
869 RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
870 cb = RT_MIN(cb, cbLeft);
871 rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
872 if (RT_SUCCESS(rc))
873 {
874 if (pu8DstInvalid != pu8Dst)
875 RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
876 GCPtrSrc += cb;
877 pu8Dst += cb;
878 pu8DstInvalid = pu8Dst;
879 }
880 else if ( rc == VERR_PAGE_NOT_PRESENT
881 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
882 {
883 GCPtrSrc += cb;
884 pu8Dst += cb;
885 }
886 else
887 {
888 AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
889 return VERR_SELM_GDT_READ_ERROR;
890 }
891 cbLeft -= cb;
892 }
893
894 /* any invalid pages at the end? */
895 if (pu8DstInvalid != pu8Dst)
896 {
897 cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
898 /* If any GDTEs was invalidated, zero them. */
899 if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
900 RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
901 }
902
903 /* keep track of the effective limit. */
904 if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
905 {
906 Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
907 pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
908 pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
909 }
910 }
911
912 /*
913 * Check if the Guest GDT intrudes on our GDT entries.
914 */
915 /** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
916 RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
917 if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
918 {
919 PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
920 PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
921 int iGDT = 0;
922
923 Log(("Internal SELM GDT conflict: use non-present entries\n"));
924 STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
925 while (pGDTECur > pGDTEStart)
926 {
927 /* We can reuse non-present entries */
928 if (!pGDTECur->Gen.u1Present)
929 {
930 aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
931 aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
932 Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
933 iGDT++;
934 if (iGDT >= SELM_HYPER_SEL_MAX)
935 break;
936 }
937
938 pGDTECur--;
939 }
940 if (iGDT != SELM_HYPER_SEL_MAX)
941 {
942 AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
943 return VERR_SELM_GDT_TOO_FULL;
944 }
945 }
946 else
947 {
948 aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
949 aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
950 aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
951 aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
952 aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
953 }
954
955 /*
956 * Work thru the copied GDT entries adjusting them for correct virtualization.
957 */
958 PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
959 while (pGDTE < pGDTEEnd)
960 {
961 if (pGDTE->Gen.u1Present)
962 selmGuestToShadowDesc(pGDTE);
963
964 /* Next GDT entry. */
965 pGDTE++;
966 }
967
968 /*
969 * Check if our hypervisor selectors were changed.
970 */
971 if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
972 || aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
973 || aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
974 || aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
975 || aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
976 {
977 /* Reinitialize our hypervisor GDTs */
978 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
979 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
980 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
981 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
982 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
983
984 STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
985
986 /*
987 * Do the relocation callbacks to let everyone update their hyper selector dependencies.
988 * (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
989 */
990 VMR3Relocate(pVM, 0);
991 }
992 else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
993 /* We overwrote all entries above, so we have to save them again. */
994 selmR3SetupHyperGDTSelectors(pVM);
995
996 /*
997 * Adjust the cached GDT limit.
998 * Any GDT entries which have been removed must be cleared.
999 */
1000 if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1001 {
1002 if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1003 RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1004 }
1005
1006 /*
1007 * Check if Guest's GDTR is changed.
1008 */
1009 if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1010 || GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1011 {
1012 Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1013
1014 /*
1015 * [Re]Register write virtual handler for guest's GDT.
1016 */
1017 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1018 {
1019 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1020 AssertRC(rc);
1021 }
1022
1023 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1024 GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1025 0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1026 "Guest GDT write access handler");
1027 if (RT_FAILURE(rc))
1028 return rc;
1029
1030 /* Update saved Guest GDTR. */
1031 pVM->selm.s.GuestGdtr = GDTR;
1032 pVM->selm.s.fGDTRangeRegistered = true;
1033 }
1034
1035 return VINF_SUCCESS;
1036}
1037
1038
1039/**
1040 * Updates (syncs) the shadow LDT.
1041 *
1042 * @returns VBox status code.
1043 * @param pVM The VM handle.
1044 * @param pVCpu The current virtual CPU.
1045 */
1046static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1047{
1048 int rc = VINF_SUCCESS;
1049
1050 /*
1051 * Always assume the best...
1052 */
1053 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1054
1055 /*
1056 * LDT handling is done similarly to the GDT handling with a shadow
1057 * array. However, since the LDT is expected to be swappable (at least
1058 * some ancient OSes makes it swappable) it must be floating and
1059 * synced on a per-page basis.
1060 *
1061 * Eventually we will change this to be fully on demand. Meaning that
1062 * we will only sync pages containing LDT selectors actually used and
1063 * let the #PF handler lazily sync pages as they are used.
1064 * (This applies to GDT too, when we start making OS/2 fast.)
1065 */
1066
1067 /*
1068 * First, determine the current LDT selector.
1069 */
1070 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1071 if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1072 {
1073 /* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1074 CPUMSetHyperLDTR(pVCpu, 0);
1075 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1076 {
1077 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1078 AssertRC(rc);
1079 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1080 }
1081 pVM->selm.s.cbLdtLimit = 0;
1082 return VINF_SUCCESS;
1083 }
1084
1085 /*
1086 * Get the LDT selector.
1087 */
1088/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1089 PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1090 RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1091 uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1092
1093 /*
1094 * Validate it.
1095 */
1096 if ( !cbLdt
1097 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1098 || pDesc->Gen.u1DescType
1099 || pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1100 {
1101 AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1102
1103 /* cbLdt > 0:
1104 * This is quite impossible, so we do as most people do when faced with
1105 * the impossible, we simply ignore it.
1106 */
1107 CPUMSetHyperLDTR(pVCpu, 0);
1108 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1109 {
1110 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1111 AssertRC(rc);
1112 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1113 }
1114 return VINF_SUCCESS;
1115 }
1116 /** @todo check what intel does about odd limits. */
1117 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1118
1119 /*
1120 * Use the cached guest ldt address if the descriptor has already been modified (see below)
1121 * (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1122 */
1123 if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1124 GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1125
1126
1127 /** @todo Handle only present LDT segments. */
1128// if (pDesc->Gen.u1Present)
1129 {
1130 /*
1131 * Check if Guest's LDT address/limit is changed.
1132 */
1133 if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1134 || cbLdt != pVM->selm.s.cbLdtLimit)
1135 {
1136 Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1137 pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1138
1139 /*
1140 * [Re]Register write virtual handler for guest's GDT.
1141 * In the event of LDT overlapping something, don't install it just assume it's being updated.
1142 */
1143 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1144 {
1145 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1146 AssertRC(rc);
1147 }
1148#ifdef DEBUG
1149 if (pDesc->Gen.u1Present)
1150 Log(("LDT selector marked not present!!\n"));
1151#endif
1152 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1153 0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1154 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1155 {
1156 /** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1157 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1158 Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1159 GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1160 }
1161 else if (RT_SUCCESS(rc))
1162 pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1163 else
1164 {
1165 CPUMSetHyperLDTR(pVCpu, 0);
1166 return rc;
1167 }
1168
1169 pVM->selm.s.cbLdtLimit = cbLdt;
1170 }
1171 }
1172
1173 /*
1174 * Calc Shadow LDT base.
1175 */
1176 unsigned off;
1177 pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1178 RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1179 PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1180
1181 /*
1182 * Enable the LDT selector in the shadow GDT.
1183 */
1184 pDesc->Gen.u1Present = 1;
1185 pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1186 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1187 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1188 pDesc->Gen.u1Available = 0;
1189 pDesc->Gen.u1Long = 0;
1190 if (cbLdt > 0xffff)
1191 {
1192 cbLdt = 0xffff;
1193 pDesc->Gen.u4LimitHigh = 0;
1194 pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1195 }
1196
1197 /*
1198 * Set Hyper LDTR and notify TRPM.
1199 */
1200 CPUMSetHyperLDTR(pVCpu, SelLdt);
1201
1202 /*
1203 * Loop synchronising the LDT page by page.
1204 */
1205 /** @todo investigate how intel handle various operations on half present cross page entries. */
1206 off = GCPtrLdt & (sizeof(X86DESC) - 1);
1207 AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1208
1209 /* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1210 unsigned cbLeft = cbLdt + 1;
1211 PX86DESC pLDTE = pShadowLDT;
1212 while (cbLeft)
1213 {
1214 /*
1215 * Read a chunk.
1216 */
1217 unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1218 if (cbChunk > cbLeft)
1219 cbChunk = cbLeft;
1220 rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1221 if (RT_SUCCESS(rc))
1222 {
1223 /*
1224 * Mark page
1225 */
1226 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D);
1227 AssertRC(rc);
1228
1229 /*
1230 * Loop thru the available LDT entries.
1231 * Figure out where to start and end and the potential cross pageness of
1232 * things adds a little complexity. pLDTE is updated there and not in the
1233 * 'next' part of the loop. The pLDTEEnd is inclusive.
1234 */
1235 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1236 if (pLDTE + 1 < pShadowLDT)
1237 pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1238 while (pLDTE <= pLDTEEnd)
1239 {
1240 if (pLDTE->Gen.u1Present)
1241 selmGuestToShadowDesc(pLDTE);
1242
1243 /* Next LDT entry. */
1244 pLDTE++;
1245 }
1246 }
1247 else
1248 {
1249 RT_BZERO(pShadowLDT, cbChunk);
1250 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1251 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1252 AssertRC(rc);
1253 }
1254
1255 /*
1256 * Advance to the next page.
1257 */
1258 cbLeft -= cbChunk;
1259 GCPtrShadowLDT += cbChunk;
1260 pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1261 GCPtrLdt += cbChunk;
1262 }
1263
1264 return VINF_SUCCESS;
1265}
1266
1267
1268/**
1269 * Checks and updates segment selector registers.
1270 *
1271 * @returns VBox strict status code.
1272 * @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1273 *
1274 * @param pVM The VM handle.
1275 * @param pVCpu The current virtual CPU.
1276 */
1277static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1278{
1279 Assert(CPUMIsGuestInProtectedMode(pVCpu));
1280
1281 /*
1282 * No stale selectors in V8086 mode.
1283 */
1284 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1285 if (pCtx->eflags.Bits.u1VM)
1286 return VINF_SUCCESS;
1287
1288 /*
1289 * Check for stale selectors and load hidden register bits where they
1290 * are missing.
1291 */
1292 uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1293 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1294 PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1295 for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1296 {
1297 RTSEL const Sel = paSReg[iSReg].Sel;
1298 if (Sel & X86_SEL_MASK_OFF_RPL)
1299 {
1300 /* Get the shadow descriptor entry corresponding to this. */
1301 static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1302 PCX86DESC pDesc;
1303 if (!(Sel & X86_SEL_LDT))
1304 {
1305 if ((Sel | (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1306 pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1307 else
1308 pDesc = &s_NotPresentDesc;
1309 }
1310 else
1311 {
1312 if ((Sel | (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1313 pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1314 else
1315 pDesc = &s_NotPresentDesc;
1316 }
1317
1318 /* Check the segment register. */
1319 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1320 {
1321 if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1322 {
1323 /* Did it go stale? */
1324 if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1325 {
1326 Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1327 STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1328 paSReg[iSReg].fFlags |= CPUMSELREG_FLAGS_STALE;
1329 rcStrict = VINF_EM_RESCHEDULE_REM;
1330 }
1331 }
1332 else
1333 {
1334 /* Did it stop being stale? I.e. did the guest change it things
1335 back to the way they were? */
1336 if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1337 {
1338 STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1339 paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1340 }
1341 else
1342 {
1343 Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1344 STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1345 rcStrict = VINF_EM_RESCHEDULE_REM;
1346 }
1347 }
1348 }
1349 /* Load the hidden registers if it's a valid descriptor for the
1350 current segment register. */
1351 else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1352 {
1353 selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1354 STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1355 }
1356 /* It's stale. */
1357 else
1358 {
1359 Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1360 STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1361 paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1362 rcStrict = VINF_EM_RESCHEDULE_REM;
1363 }
1364 }
1365 /* else: 0 selector, ignore. */
1366 }
1367
1368 return rcStrict;
1369}
1370
1371#endif /*VBOX_WITH_RAW_MODE*/
1372
1373
1374/**
1375 * Updates the Guest GDT & LDT virtualization based on current CPU state.
1376 *
1377 * @returns VBox status code.
1378 * @param pVM Pointer to the VM.
1379 * @param pVCpu Pointer to the VMCPU.
1380 */
1381VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1382{
1383#ifdef VBOX_WITH_RAW_MODE
1384 if (pVM->selm.s.fDisableMonitoring)
1385#endif
1386 {
1387 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
1388 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1389 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1390 return VINF_SUCCESS;
1391 }
1392
1393#ifdef VBOX_WITH_RAW_MODE
1394 STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1395
1396 /*
1397 * GDT sync
1398 */
1399 int rc;
1400 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1401 {
1402 rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1403 if (RT_FAILURE(rc))
1404 return rc; /* We're toast, so forget the profiling. */
1405 AssertRCSuccess(rc);
1406 }
1407
1408 /*
1409 * TSS sync
1410 */
1411 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1412 {
1413 rc = SELMR3SyncTSS(pVM, pVCpu);
1414 if (RT_FAILURE(rc))
1415 return rc;
1416 AssertRCSuccess(rc);
1417 }
1418
1419 /*
1420 * LDT sync
1421 */
1422 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1423 {
1424 rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1425 if (RT_FAILURE(rc))
1426 return rc;
1427 AssertRCSuccess(rc);
1428 }
1429
1430 /*
1431 * Check selector registers.
1432 */
1433 VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1434
1435 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1436 return rcStrict;
1437#endif
1438}
1439
1440
1441/**
1442 * \#PF Handler callback for virtual access handler ranges.
1443 *
1444 * Important to realize that a physical page in a range can have aliases, and
1445 * for ALL and WRITE handlers these will also trigger.
1446 *
1447 * @returns VINF_SUCCESS if the handler have carried out the operation.
1448 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1449 * @param pVM Pointer to the VM.
1450 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1451 * @param pvPtr The HC mapping of that address.
1452 * @param pvBuf What the guest is reading/writing.
1453 * @param cbBuf How much it's reading/writing.
1454 * @param enmAccessType The access type.
1455 * @param pvUser User argument.
1456 */
1457static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf,
1458 PGMACCESSTYPE enmAccessType, void *pvUser)
1459{
1460 Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1461 Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1462 NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1463
1464 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1465 return VINF_PGM_HANDLER_DO_DEFAULT;
1466}
1467
1468
1469/**
1470 * \#PF Handler callback for virtual access handler ranges.
1471 *
1472 * Important to realize that a physical page in a range can have aliases, and
1473 * for ALL and WRITE handlers these will also trigger.
1474 *
1475 * @returns VINF_SUCCESS if the handler have carried out the operation.
1476 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1477 * @param pVM Pointer to the VM.
1478 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1479 * @param pvPtr The HC mapping of that address.
1480 * @param pvBuf What the guest is reading/writing.
1481 * @param cbBuf How much it's reading/writing.
1482 * @param enmAccessType The access type.
1483 * @param pvUser User argument.
1484 */
1485static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf,
1486 PGMACCESSTYPE enmAccessType, void *pvUser)
1487{
1488 Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1489 Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1490 NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1491
1492 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1493 return VINF_PGM_HANDLER_DO_DEFAULT;
1494}
1495
1496
1497/**
1498 * \#PF Handler callback for virtual access handler ranges.
1499 *
1500 * Important to realize that a physical page in a range can have aliases, and
1501 * for ALL and WRITE handlers these will also trigger.
1502 *
1503 * @returns VINF_SUCCESS if the handler have carried out the operation.
1504 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1505 * @param pVM Pointer to the VM.
1506 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1507 * @param pvPtr The HC mapping of that address.
1508 * @param pvBuf What the guest is reading/writing.
1509 * @param cbBuf How much it's reading/writing.
1510 * @param enmAccessType The access type.
1511 * @param pvUser User argument.
1512 */
1513static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf,
1514 PGMACCESSTYPE enmAccessType, void *pvUser)
1515{
1516 Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1517 Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1518 NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1519
1520 /** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1521 * reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1522 * should probably also deregister the virtual handler if TR.base/size
1523 * changes while we're in REM. */
1524
1525 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1526 return VINF_PGM_HANDLER_DO_DEFAULT;
1527}
1528
1529
1530/**
1531 * Synchronize the shadowed fields in the TSS.
1532 *
1533 * At present we're shadowing the ring-0 stack selector & pointer, and the
1534 * interrupt redirection bitmap (if present). We take the lazy approach wrt to
1535 * REM and this function is called both if REM made any changes to the TSS or
1536 * loaded TR.
1537 *
1538 * @returns VBox status code.
1539 * @param pVM Pointer to the VM.
1540 * @param pVCpu Pointer to the VMCPU.
1541 */
1542VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1543{
1544 int rc;
1545
1546#ifdef VBOX_WITH_RAW_MODE
1547 if (pVM->selm.s.fDisableMonitoring)
1548#endif
1549 {
1550 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1551 return VINF_SUCCESS;
1552 }
1553
1554#ifdef VBOX_WITH_RAW_MODE
1555 STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1556 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1557
1558 /*
1559 * Get TR and extract and store the basic info.
1560 *
1561 * Note! The TSS limit is not checked by the LTR code, so we
1562 * have to be a bit careful with it. We make sure cbTss
1563 * won't be zero if TR is valid and if it's NULL we'll
1564 * make sure cbTss is 0.
1565 */
1566/** @todo use the hidden bits, not shadow GDT. */
1567 CPUMSELREGHID trHid;
1568 RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1569 RTGCPTR GCPtrTss = trHid.u64Base;
1570 uint32_t cbTss = trHid.u32Limit;
1571 Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1572 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1573 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1574 if (SelTss & X86_SEL_MASK_OFF_RPL)
1575 {
1576 Assert(!(SelTss & X86_SEL_LDT));
1577 Assert(trHid.Attr.n.u1DescType == 0);
1578 Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1579 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1580 if (!++cbTss)
1581 cbTss = UINT32_MAX;
1582 }
1583 else
1584 {
1585 Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1586 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1587 cbTss = 0; /* the reset case. */
1588 }
1589 pVM->selm.s.cbGuestTss = cbTss;
1590 pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1591 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1592
1593 /*
1594 * Figure out the size of what need to monitor.
1595 */
1596 /* We're not interested in any 16-bit TSSes. */
1597 uint32_t cbMonitoredTss = cbTss;
1598 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1599 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1600 cbMonitoredTss = 0;
1601
1602 pVM->selm.s.offGuestIoBitmap = 0;
1603 bool fNoRing1Stack = true;
1604 if (cbMonitoredTss)
1605 {
1606 /*
1607 * 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1608 * If VME is enabled we also want to keep an eye on the interrupt
1609 * redirection bitmap.
1610 */
1611 VBOXTSS Tss;
1612 uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1613 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1614 if ( !(cr4 & X86_CR4_VME)
1615 || ( RT_SUCCESS(rc)
1616 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1617 && Tss.offIoBitmap > cbTss) /* beyond the end */ /** @todo not sure how the partial case is handled; probably not allowed. */
1618 )
1619 /* No interrupt redirection bitmap, just ESP0 and SS0. */
1620 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1621 else if (RT_SUCCESS(rc))
1622 {
1623 /*
1624 * Everything up to and including the interrupt redirection bitmap. Unfortunately
1625 * this can be quite a large chunk. We use to skip it earlier and just hope it
1626 * was kind of static...
1627 *
1628 * Update the virtual interrupt redirection bitmap while we're here.
1629 * (It is located in the 32 bytes before TR:offIoBitmap.)
1630 */
1631 cbMonitoredTss = Tss.offIoBitmap;
1632 pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1633
1634 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1635 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1636 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1637 AssertRC(rc);
1638 /** @todo memset the bitmap on failure? */
1639 Log2(("Redirection bitmap:\n"));
1640 Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1641 }
1642 else
1643 {
1644 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1645 pVM->selm.s.offGuestIoBitmap = 0;
1646 /** @todo memset the bitmap? */
1647 }
1648
1649 /*
1650 * Update the ring 0 stack selector and base address.
1651 */
1652 if (RT_SUCCESS(rc))
1653 {
1654#ifdef LOG_ENABLED
1655 if (LogIsEnabled())
1656 {
1657 uint32_t ssr0, espr0;
1658 SELMGetRing1Stack(pVM, &ssr0, &espr0);
1659 if ((ssr0 & ~1) != Tss.ss0 || espr0 != Tss.esp0)
1660 {
1661 RTGCPHYS GCPhys = NIL_RTGCPHYS;
1662 rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1663 Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1664 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1665 AssertMsg(ssr0 != Tss.ss0,
1666 ("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1667 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1668 }
1669 Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1670 }
1671#endif /* LOG_ENABLED */
1672 AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1673
1674 /* Update our TSS structure for the guest's ring 1 stack */
1675 selmSetRing1Stack(pVM, Tss.ss0 | 1, Tss.esp0);
1676 pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1677 }
1678 }
1679
1680 /*
1681 * Flush the ring-1 stack and the direct syscall dispatching if we
1682 * cannot obtain SS0:ESP0.
1683 */
1684 if (fNoRing1Stack)
1685 {
1686 selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1687 pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1688
1689 /** @todo handle these dependencies better! */
1690 TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1691 TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1692 }
1693
1694 /*
1695 * Check for monitor changes and apply them.
1696 */
1697 if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1698 || cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1699 {
1700 Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1701 GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1702
1703 /* Release the old range first. */
1704 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1705 {
1706 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1707 AssertRC(rc);
1708 }
1709
1710 /* Register the write handler if TS != 0. */
1711 if (cbMonitoredTss != 0)
1712 {
1713 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1714 0, selmR3GuestTSSWriteHandler,
1715 "selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1716 if (RT_FAILURE(rc))
1717 {
1718 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1719 return rc;
1720 }
1721
1722 /* Update saved Guest TSS info. */
1723 pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1724 pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1725 pVM->selm.s.GCSelTss = SelTss;
1726 }
1727 else
1728 {
1729 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1730 pVM->selm.s.cbMonitoredGuestTss = 0;
1731 pVM->selm.s.GCSelTss = 0;
1732 }
1733 }
1734
1735 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1736
1737 STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1738 return VINF_SUCCESS;
1739#endif /*VBOX_WITH_RAW_MODE*/
1740}
1741
1742#ifdef VBOX_WITH_RAW_MODE
1743
1744/**
1745 * Compares the Guest GDT and LDT with the shadow tables.
1746 * This is a VBOX_STRICT only function.
1747 *
1748 * @returns VBox status code.
1749 * @param pVM Pointer to the VM.
1750 */
1751VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1752{
1753#ifdef VBOX_STRICT
1754 PVMCPU pVCpu = VMMGetCpu(pVM);
1755
1756 /*
1757 * Get GDTR and check for conflict.
1758 */
1759 VBOXGDTR GDTR;
1760 CPUMGetGuestGDTR(pVCpu, &GDTR);
1761 if (GDTR.cbGdt == 0)
1762 return VINF_SUCCESS;
1763
1764 if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1765 Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1766
1767 if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1768 Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1769
1770 /*
1771 * Loop thru the GDT checking each entry.
1772 */
1773 RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1774 PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1775 PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1776 while (pGDTE < pGDTEEnd)
1777 {
1778 X86DESC GDTEGuest;
1779 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1780 if (RT_SUCCESS(rc))
1781 {
1782 if (pGDTE->Gen.u1DescType || pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1783 {
1784 if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1785 || pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1786 || pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1787 || pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1788 || pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1789 || pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1790 || pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1791 {
1792 unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1793 SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1794 SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1795 }
1796 }
1797 }
1798
1799 /* Advance to the next descriptor. */
1800 GCPtrGDTEGuest += sizeof(X86DESC);
1801 pGDTE++;
1802 }
1803
1804
1805 /*
1806 * LDT?
1807 */
1808 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1809 if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1810 return VINF_SUCCESS;
1811 Assert(!(SelLdt & X86_SEL_LDT));
1812 if (SelLdt > GDTR.cbGdt)
1813 {
1814 Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1815 return VERR_SELM_LDT_OUT_OF_BOUNDS;
1816 }
1817 X86DESC LDTDesc;
1818 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1819 if (RT_FAILURE(rc))
1820 {
1821 Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1822 return rc;
1823 }
1824 RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1825 uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1826
1827 /*
1828 * Validate it.
1829 */
1830 if (!cbLdt)
1831 return VINF_SUCCESS;
1832 /** @todo check what intel does about odd limits. */
1833 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1834 if ( LDTDesc.Gen.u1DescType
1835 || LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1836 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1837 {
1838 Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1839 return VERR_SELM_INVALID_LDT;
1840 }
1841
1842 /*
1843 * Loop thru the LDT checking each entry.
1844 */
1845 unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1846 PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1847 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1848 while (pLDTE < pLDTEEnd)
1849 {
1850 X86DESC LDTEGuest;
1851 rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1852 if (RT_SUCCESS(rc))
1853 {
1854 if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1855 || pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1856 || pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1857 || pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1858 || pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1859 || pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1860 || pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1861 {
1862 unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1863 SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1864 SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1865 }
1866 }
1867
1868 /* Advance to the next descriptor. */
1869 GCPtrLDTEGuest += sizeof(X86DESC);
1870 pLDTE++;
1871 }
1872
1873#else /* !VBOX_STRICT */
1874 NOREF(pVM);
1875#endif /* !VBOX_STRICT */
1876
1877 return VINF_SUCCESS;
1878}
1879
1880
1881/**
1882 * Validates the RawR0 TSS values against the one in the Guest TSS.
1883 *
1884 * @returns true if it matches.
1885 * @returns false and assertions on mismatch..
1886 * @param pVM Pointer to the VM.
1887 */
1888VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1889{
1890#ifdef VBOX_STRICT
1891 PVMCPU pVCpu = VMMGetCpu(pVM);
1892
1893 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1894 return true;
1895
1896 /*
1897 * Get TR and extract the basic info.
1898 */
1899 CPUMSELREGHID trHid;
1900 RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1901 RTGCPTR GCPtrTss = trHid.u64Base;
1902 uint32_t cbTss = trHid.u32Limit;
1903 Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1904 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1905 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1906 if (SelTss & X86_SEL_MASK_OFF_RPL)
1907 {
1908 AssertReturn(!(SelTss & X86_SEL_LDT), false);
1909 AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1910 AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1911 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1912 false);
1913 if (!++cbTss)
1914 cbTss = UINT32_MAX;
1915 }
1916 else
1917 {
1918 AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1919 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1920 false);
1921 cbTss = 0; /* the reset case. */
1922 }
1923 AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1924 AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1925 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1926 ("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1927 false);
1928 AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1929 || (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1930 ("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1931 false);
1932 AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1933 || (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1934 ("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1935 false);
1936
1937
1938 /*
1939 * Figure out the size of what need to monitor.
1940 */
1941 /* We're not interested in any 16-bit TSSes. */
1942 uint32_t cbMonitoredTss = cbTss;
1943 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1944 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1945 cbMonitoredTss = 0;
1946 if (cbMonitoredTss)
1947 {
1948 VBOXTSS Tss;
1949 uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1950 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1951 AssertReturn( rc == VINF_SUCCESS
1952 /* Happens early in XP boot during page table switching. */
1953 || ( (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
1954 && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1955 false);
1956 if ( !(cr4 & X86_CR4_VME)
1957 || ( RT_SUCCESS(rc)
1958 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1959 && Tss.offIoBitmap > cbTss)
1960 )
1961 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1962 else if (RT_SUCCESS(rc))
1963 {
1964 cbMonitoredTss = Tss.offIoBitmap;
1965 AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1966 ("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1967 false);
1968
1969 /* check the bitmap */
1970 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1971 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1972 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1973 AssertRCReturn(rc, false);
1974 AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1975 ("offIoBitmap=%#x cbTss=%#x\n"
1976 " Guest: %.32Rhxs\n"
1977 "Shadow: %.32Rhxs\n",
1978 Tss.offIoBitmap, cbTss,
1979 &Tss.IntRedirBitmap[0],
1980 &pVM->selm.s.Tss.IntRedirBitmap[0]),
1981 false);
1982 }
1983 else
1984 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1985
1986 /*
1987 * Check SS0 and ESP0.
1988 */
1989 if ( !pVM->selm.s.fSyncTSSRing0Stack
1990 && RT_SUCCESS(rc))
1991 {
1992 if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1993 || Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1994 {
1995 RTGCPHYS GCPhys;
1996 rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1997 AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1998 (pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1999 Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
2000 return false;
2001 }
2002 }
2003 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2004 }
2005 else
2006 {
2007 AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
2008 AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
2009 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2010 }
2011
2012
2013
2014 return true;
2015
2016#else /* !VBOX_STRICT */
2017 NOREF(pVM);
2018 return true;
2019#endif /* !VBOX_STRICT */
2020}
2021
2022#endif /* VBOX_WITH_RAW_MODE */
2023
2024/**
2025 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2026 *
2027 * See SELMR3GetSelectorInfo for details.
2028 *
2029 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
2030 *
2031 * @param pVCpu Pointer to the VMCPU.
2032 * @param Sel The selector to get info about.
2033 * @param pSelInfo Where to store the information.
2034 */
2035static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2036{
2037 /*
2038 * Read it from the guest descriptor table.
2039 */
2040/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2041 X86DESC64 Desc;
2042 RTGCPTR GCPtrDesc;
2043 if (!(Sel & X86_SEL_LDT))
2044 {
2045 /* GDT */
2046 VBOXGDTR Gdtr;
2047 CPUMGetGuestGDTR(pVCpu, &Gdtr);
2048 if ((Sel | X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2049 return VERR_INVALID_SELECTOR;
2050 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2051 }
2052 else
2053 {
2054 /* LDT */
2055 uint64_t GCPtrBase;
2056 uint32_t cbLimit;
2057 CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2058 if ((Sel | X86_SEL_RPL_LDT) > cbLimit)
2059 return VERR_INVALID_SELECTOR;
2060
2061 /* calc the descriptor location. */
2062 GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2063 }
2064
2065 /* read the descriptor. */
2066 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2067 if (RT_FAILURE(rc))
2068 {
2069 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2070 if (RT_FAILURE(rc))
2071 return rc;
2072 Desc.au64[1] = 0;
2073 }
2074
2075 /*
2076 * Extract the base and limit
2077 * (We ignore the present bit here, which is probably a bit silly...)
2078 */
2079 pSelInfo->Sel = Sel;
2080 pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2081 pSelInfo->u.Raw64 = Desc;
2082 if (Desc.Gen.u1DescType)
2083 {
2084 /*
2085 * 64-bit code selectors are wide open, it's not possible to detect
2086 * 64-bit data or stack selectors without also dragging in assumptions
2087 * about current CS (i.e. that's we're executing in 64-bit mode). So,
2088 * the selinfo user needs to deal with this in the context the info is
2089 * used unfortunately.
2090 */
2091 if ( Desc.Gen.u1Long
2092 && !Desc.Gen.u1DefBig
2093 && (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2094 {
2095 /* Note! We ignore the segment limit hacks that was added by AMD. */
2096 pSelInfo->GCPtrBase = 0;
2097 pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2098 }
2099 else
2100 {
2101 pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2102 pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2103 }
2104 pSelInfo->SelGate = 0;
2105 }
2106 else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2107 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2108 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2109 {
2110 /* Note. LDT descriptors are weird in long mode, we ignore the footnote
2111 in the AMD manual here as a simplification. */
2112 pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2113 pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2114 pSelInfo->SelGate = 0;
2115 }
2116 else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2117 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2118 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2119 {
2120 pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2121 pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2122 | ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2123 | ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2124 pSelInfo->SelGate = Desc.Gate.u16Sel;
2125 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_GATE;
2126 }
2127 else
2128 {
2129 pSelInfo->cbLimit = 0;
2130 pSelInfo->GCPtrBase = 0;
2131 pSelInfo->SelGate = 0;
2132 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_INVALID;
2133 }
2134 if (!Desc.Gen.u1Present)
2135 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_NOT_PRESENT;
2136
2137 return VINF_SUCCESS;
2138}
2139
2140
2141/**
2142 * Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2143 * interprets a legacy descriptor table entry and fills in the selector info
2144 * structure from it.
2145 *
2146 * @param pSelInfo Where to store the selector info. Only the fFlags and
2147 * Sel members have been initialized.
2148 * @param pDesc The legacy descriptor to parse.
2149 */
2150DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2151{
2152 pSelInfo->u.Raw64.au64[1] = 0;
2153 pSelInfo->u.Raw = *pDesc;
2154 if ( pDesc->Gen.u1DescType
2155 || !(pDesc->Gen.u4Type & 4))
2156 {
2157 pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2158 pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2159 pSelInfo->SelGate = 0;
2160 }
2161 else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2162 {
2163 pSelInfo->cbLimit = 0;
2164 if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2165 pSelInfo->GCPtrBase = 0;
2166 else
2167 pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2168 | (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2169 pSelInfo->SelGate = pDesc->Gate.u16Sel;
2170 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_GATE;
2171 }
2172 else
2173 {
2174 pSelInfo->cbLimit = 0;
2175 pSelInfo->GCPtrBase = 0;
2176 pSelInfo->SelGate = 0;
2177 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_INVALID;
2178 }
2179 if (!pDesc->Gen.u1Present)
2180 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_NOT_PRESENT;
2181}
2182
2183
2184/**
2185 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2186 *
2187 * See SELMR3GetSelectorInfo for details.
2188 *
2189 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
2190 *
2191 * @param pVM Pointer to the VM.
2192 * @param pVCpu Pointer to the VMCPU.
2193 * @param Sel The selector to get info about.
2194 * @param pSelInfo Where to store the information.
2195 */
2196static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2197{
2198 /*
2199 * Read the descriptor entry
2200 */
2201 pSelInfo->fFlags = 0;
2202 X86DESC Desc;
2203 if ( !(Sel & X86_SEL_LDT)
2204 && ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2205 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2206 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2207 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2208 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2209 )
2210 {
2211 /*
2212 * Hypervisor descriptor.
2213 */
2214 pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2215 if (CPUMIsGuestInProtectedMode(pVCpu))
2216 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_PROT_MODE;
2217 else
2218 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_REAL_MODE;
2219
2220 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2221 }
2222 else if (CPUMIsGuestInProtectedMode(pVCpu))
2223 {
2224 /*
2225 * Read it from the guest descriptor table.
2226 */
2227 pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2228
2229 RTGCPTR GCPtrDesc;
2230 if (!(Sel & X86_SEL_LDT))
2231 {
2232 /* GDT */
2233 VBOXGDTR Gdtr;
2234 CPUMGetGuestGDTR(pVCpu, &Gdtr);
2235 if ((Sel | X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2236 return VERR_INVALID_SELECTOR;
2237 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2238 }
2239 else
2240 {
2241 /* LDT */
2242 uint64_t GCPtrBase;
2243 uint32_t cbLimit;
2244 CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2245 if ((Sel | X86_SEL_RPL_LDT) > cbLimit)
2246 return VERR_INVALID_SELECTOR;
2247
2248 /* calc the descriptor location. */
2249 GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2250 }
2251
2252 /* read the descriptor. */
2253 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2254 if (RT_FAILURE(rc))
2255 return rc;
2256 }
2257 else
2258 {
2259 /*
2260 * We're in real mode.
2261 */
2262 pSelInfo->Sel = Sel;
2263 pSelInfo->GCPtrBase = Sel << 4;
2264 pSelInfo->cbLimit = 0xffff;
2265 pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2266 pSelInfo->u.Raw64.au64[0] = 0;
2267 pSelInfo->u.Raw64.au64[1] = 0;
2268 pSelInfo->SelGate = 0;
2269 return VINF_SUCCESS;
2270 }
2271
2272 /*
2273 * Extract the base and limit or sel:offset for gates.
2274 */
2275 pSelInfo->Sel = Sel;
2276 selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2277
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/**
2283 * Gets information about a selector.
2284 *
2285 * Intended for the debugger mostly and will prefer the guest descriptor tables
2286 * over the shadow ones.
2287 *
2288 * @retval VINF_SUCCESS on success.
2289 * @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2290 * descriptor table.
2291 * @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2292 * is not returned if the selector itself isn't present, you have to
2293 * check that for yourself (see DBGFSELINFO::fFlags).
2294 * @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2295 * pagetable or page backing the selector table wasn't present.
2296 * @returns Other VBox status code on other errors.
2297 *
2298 * @param pVM Pointer to the VM.
2299 * @param pVCpu Pointer to the VMCPU.
2300 * @param Sel The selector to get info about.
2301 * @param pSelInfo Where to store the information.
2302 */
2303VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2304{
2305 AssertPtr(pSelInfo);
2306 if (CPUMIsGuestInLongMode(pVCpu))
2307 return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2308 return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2309}
2310
2311
2312/**
2313 * Gets information about a selector from the shadow tables.
2314 *
2315 * This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2316 * requires that the caller ensures that the shadow tables are up to date.
2317 *
2318 * @retval VINF_SUCCESS on success.
2319 * @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2320 * descriptor table.
2321 * @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2322 * is not returned if the selector itself isn't present, you have to
2323 * check that for yourself (see DBGFSELINFO::fFlags).
2324 * @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2325 * pagetable or page backing the selector table wasn't present.
2326 * @returns Other VBox status code on other errors.
2327 *
2328 * @param pVM Pointer to the VM.
2329 * @param Sel The selector to get info about.
2330 * @param pSelInfo Where to store the information.
2331 *
2332 * @remarks Don't use this when in hardware assisted virtualization mode.
2333 */
2334VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2335{
2336 Assert(pSelInfo);
2337
2338 /*
2339 * Read the descriptor entry
2340 */
2341 X86DESC Desc;
2342 if (!(Sel & X86_SEL_LDT))
2343 {
2344 /*
2345 * Global descriptor.
2346 */
2347 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2348 pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2349 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2350 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2351 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2352 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2353 ? DBGFSELINFO_FLAGS_HYPER
2354 : 0;
2355 /** @todo check that the GDT offset is valid. */
2356 }
2357 else
2358 {
2359 /*
2360 * Local Descriptor.
2361 */
2362 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2363 Desc = paLDT[Sel >> X86_SEL_SHIFT];
2364 /** @todo check if the LDT page is actually available. */
2365 /** @todo check that the LDT offset is valid. */
2366 pSelInfo->fFlags = 0;
2367 }
2368 if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2369 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_PROT_MODE;
2370 else
2371 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_REAL_MODE;
2372
2373 /*
2374 * Extract the base and limit or sel:offset for gates.
2375 */
2376 pSelInfo->Sel = Sel;
2377 selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2378
2379 return VINF_SUCCESS;
2380}
2381
2382
2383/**
2384 * Formats a descriptor.
2385 *
2386 * @param Desc Descriptor to format.
2387 * @param Sel Selector number.
2388 * @param pszOutput Output buffer.
2389 * @param cchOutput Size of output buffer.
2390 */
2391static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2392{
2393 /*
2394 * Make variable description string.
2395 */
2396 static struct
2397 {
2398 unsigned cch;
2399 const char *psz;
2400 } const aTypes[32] =
2401 {
2402#define STRENTRY(str) { sizeof(str) - 1, str }
2403 /* system */
2404 STRENTRY("Reserved0 "), /* 0x00 */
2405 STRENTRY("TSS16Avail "), /* 0x01 */
2406 STRENTRY("LDT "), /* 0x02 */
2407 STRENTRY("TSS16Busy "), /* 0x03 */
2408 STRENTRY("Call16 "), /* 0x04 */
2409 STRENTRY("Task "), /* 0x05 */
2410 STRENTRY("Int16 "), /* 0x06 */
2411 STRENTRY("Trap16 "), /* 0x07 */
2412 STRENTRY("Reserved8 "), /* 0x08 */
2413 STRENTRY("TSS32Avail "), /* 0x09 */
2414 STRENTRY("ReservedA "), /* 0x0a */
2415 STRENTRY("TSS32Busy "), /* 0x0b */
2416 STRENTRY("Call32 "), /* 0x0c */
2417 STRENTRY("ReservedD "), /* 0x0d */
2418 STRENTRY("Int32 "), /* 0x0e */
2419 STRENTRY("Trap32 "), /* 0x0f */
2420 /* non system */
2421 STRENTRY("DataRO "), /* 0x10 */
2422 STRENTRY("DataRO Accessed "), /* 0x11 */
2423 STRENTRY("DataRW "), /* 0x12 */
2424 STRENTRY("DataRW Accessed "), /* 0x13 */
2425 STRENTRY("DataDownRO "), /* 0x14 */
2426 STRENTRY("DataDownRO Accessed "), /* 0x15 */
2427 STRENTRY("DataDownRW "), /* 0x16 */
2428 STRENTRY("DataDownRW Accessed "), /* 0x17 */
2429 STRENTRY("CodeEO "), /* 0x18 */
2430 STRENTRY("CodeEO Accessed "), /* 0x19 */
2431 STRENTRY("CodeER "), /* 0x1a */
2432 STRENTRY("CodeER Accessed "), /* 0x1b */
2433 STRENTRY("CodeConfEO "), /* 0x1c */
2434 STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2435 STRENTRY("CodeConfER "), /* 0x1e */
2436 STRENTRY("CodeConfER Accessed ") /* 0x1f */
2437#undef SYSENTRY
2438 };
2439#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2440 char szMsg[128];
2441 char *psz = &szMsg[0];
2442 unsigned i = Desc.Gen.u1DescType << 4 | Desc.Gen.u4Type;
2443 memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2444 psz += aTypes[i].cch;
2445
2446 if (Desc.Gen.u1Present)
2447 ADD_STR(psz, "Present ");
2448 else
2449 ADD_STR(psz, "Not-Present ");
2450 if (Desc.Gen.u1Granularity)
2451 ADD_STR(psz, "Page ");
2452 if (Desc.Gen.u1DefBig)
2453 ADD_STR(psz, "32-bit ");
2454 else
2455 ADD_STR(psz, "16-bit ");
2456#undef ADD_STR
2457 *psz = '\0';
2458
2459 /*
2460 * Limit and Base and format the output.
2461 */
2462 uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2463 uint32_t u32Base = X86DESC_BASE(&Desc);
2464
2465 RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2466 Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2467}
2468
2469
2470/**
2471 * Dumps a descriptor.
2472 *
2473 * @param Desc Descriptor to dump.
2474 * @param Sel Selector number.
2475 * @param pszMsg Message to prepend the log entry with.
2476 */
2477VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2478{
2479 char szOutput[128];
2480 selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2481 Log(("%s: %s\n", pszMsg, szOutput));
2482 NOREF(szOutput[0]);
2483}
2484
2485
2486/**
2487 * Display the shadow gdt.
2488 *
2489 * @param pVM Pointer to the VM.
2490 * @param pHlp The info helpers.
2491 * @param pszArgs Arguments, ignored.
2492 */
2493static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2494{
2495 NOREF(pszArgs);
2496 pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2497 for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2498 {
2499 if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2500 {
2501 char szOutput[128];
2502 selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2503 const char *psz = "";
2504 if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2505 psz = " HyperCS";
2506 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2507 psz = " HyperDS";
2508 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2509 psz = " HyperCS64";
2510 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2511 psz = " HyperTSS";
2512 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2513 psz = " HyperTSSTrap08";
2514 pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2515 }
2516 }
2517}
2518
2519
2520/**
2521 * Display the guest gdt.
2522 *
2523 * @param pVM Pointer to the VM.
2524 * @param pHlp The info helpers.
2525 * @param pszArgs Arguments, ignored.
2526 */
2527static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2528{
2529 /** @todo SMP support! */
2530 PVMCPU pVCpu = &pVM->aCpus[0];
2531
2532 VBOXGDTR GDTR;
2533 CPUMGetGuestGDTR(pVCpu, &GDTR);
2534 RTGCPTR GCPtrGDT = GDTR.pGdt;
2535 unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2536
2537 pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2538 for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2539 {
2540 X86DESC GDTE;
2541 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2542 if (RT_SUCCESS(rc))
2543 {
2544 if (GDTE.Gen.u1Present)
2545 {
2546 char szOutput[128];
2547 selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2548 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2549 }
2550 }
2551 else if (rc == VERR_PAGE_NOT_PRESENT)
2552 {
2553 if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2554 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2555 }
2556 else
2557 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2558 }
2559 NOREF(pszArgs);
2560}
2561
2562
2563/**
2564 * Display the shadow ldt.
2565 *
2566 * @param pVM Pointer to the VM.
2567 * @param pHlp The info helpers.
2568 * @param pszArgs Arguments, ignored.
2569 */
2570static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2571{
2572 unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2573 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2574 pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2575 for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2576 {
2577 if (paLDT[iLDT].Gen.u1Present)
2578 {
2579 char szOutput[128];
2580 selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2581 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2582 }
2583 }
2584 NOREF(pszArgs);
2585}
2586
2587
2588/**
2589 * Display the guest ldt.
2590 *
2591 * @param pVM Pointer to the VM.
2592 * @param pHlp The info helpers.
2593 * @param pszArgs Arguments, ignored.
2594 */
2595static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2596{
2597 /** @todo SMP support! */
2598 PVMCPU pVCpu = &pVM->aCpus[0];
2599
2600 uint64_t GCPtrLdt;
2601 uint32_t cbLdt;
2602 RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2603 if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2604 {
2605 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2606 return;
2607 }
2608
2609 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2610 unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2611 for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2612 {
2613 X86DESC LdtE;
2614 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2615 if (RT_SUCCESS(rc))
2616 {
2617 if (LdtE.Gen.u1Present)
2618 {
2619 char szOutput[128];
2620 selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2621 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2622 }
2623 }
2624 else if (rc == VERR_PAGE_NOT_PRESENT)
2625 {
2626 if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2627 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, GCPtrLdt);
2628 }
2629 else
2630 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, rc, GCPtrLdt);
2631 }
2632 NOREF(pszArgs);
2633}
2634
2635
2636/**
2637 * Dumps the hypervisor GDT
2638 *
2639 * @param pVM Pointer to the VM.
2640 */
2641VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2642{
2643 DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2644}
2645
2646
2647/**
2648 * Dumps the hypervisor LDT
2649 *
2650 * @param pVM Pointer to the VM.
2651 */
2652VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2653{
2654 DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2655}
2656
2657
2658/**
2659 * Dumps the guest GDT
2660 *
2661 * @param pVM Pointer to the VM.
2662 */
2663VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2664{
2665 DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2666}
2667
2668
2669/**
2670 * Dumps the guest LDT
2671 *
2672 * @param pVM Pointer to the VM.
2673 */
2674VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2675{
2676 DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2677}
2678
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