SELM.cpp@ 45357

Last change on this file since 45357 was 45276, checked in by vboxsync, 12 years ago

Ring-1 compression patches, courtesy of trivirt AG:

main: diff to remove the hwvirt requirement for QNX
rem: diff for dealing with raw ring 0/1 selectors and general changes to allowed guest execution states
vmm: changes for using the guest's TSS selector index as our hypervisor TSS selector (makes str safe) (VBOX_WITH_SAFE_STR )
vmm: changes for dealing with guest ring 1 code (VBOX_WITH_RAW_RING1)
vmm: change to emulate smsw in RC/R0 (QNX uses this old style instruction a lot so going to qemu for emulation is very expensive)
vmm: change (hack) to kick out patm virtual handlers in case they conflict with guest GDT/TSS write monitors; we should allow multiple handlers per page, but that change would be rather invasive

Property svn:eol-style set to native
Property svn:keywords set to Id Revision

File size: 107.9 KB

Line
1	/* $Id: SELM.cpp 45276 2013-04-02 08:17:11Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/mm.h>
66	#include <VBox/vmm/ssm.h>
67	#include <VBox/vmm/pgm.h>
68	#include <VBox/vmm/trpm.h>
69	#include <VBox/vmm/dbgf.h>
70	#include "SELMInternal.h"
71	#include <VBox/vmm/vm.h>
72	#include <VBox/err.h>
73	#include <VBox/param.h>
74
75	#include <iprt/assert.h>
76	#include <VBox/log.h>
77	#include <iprt/asm.h>
78	#include <iprt/string.h>
79	#include <iprt/thread.h>
80	#include <iprt/string.h>
81
82
83
84	/** SELM saved state version. */
85	#define SELM_SAVED_STATE_VERSION 5
86
87
88	/*******************************************************************************
89	* Internal Functions *
90	*******************************************************************************/
91	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
92	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
93	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
95	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
96	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
97	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
98	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103
104
105	/*******************************************************************************
106	* Global Variables *
107	*******************************************************************************/
108	#ifdef LOG_ENABLED
109	/** Segment register names. */
110	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
111	#endif
112
113
114	/**
115	* Initializes the SELM.
116	*
117	* @returns VBox status code.
118	* @param pVM Pointer to the VM.
119	*/
120	VMMR3DECL(int) SELMR3Init(PVM pVM)
121	{
122	LogFlow(("SELMR3Init\n"));
123
124	/*
125	* Assert alignment and sizes.
126	* (The TSS block requires contiguous back.)
127	*/
128	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
129	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
130	#if 0 /* doesn't work */
131	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
132	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
133	#endif
134	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
135	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
136	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
137
138	/*
139	* Init the structure.
140	*/
141	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
142	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
143	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
144	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
145	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
146	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
147
148	/*
149	* Allocate GDT table.
150	*/
151	int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
152	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
153	AssertRCReturn(rc, rc);
154
155	/*
156	* Allocate LDT area.
157	*/
158	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
159	AssertRCReturn(rc, rc);
160
161	/*
162	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
163	*/
164	pVM->selm.s.cbEffGuestGdtLimit = 0;
165	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
166	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
167	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
168
169	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
170	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
171	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
172	pVM->selm.s.GCSelTss = RTSEL_MAX;
173
174	pVM->selm.s.fDisableMonitoring = false;
175	pVM->selm.s.fSyncTSSRing0Stack = false;
176
177	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
178	* for I/O operations. */
179	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
180	/* bit set to 1 means no redirection */
181	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
182
183	/*
184	* Register the saved state data unit.
185	*/
186	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
187	NULL, NULL, NULL,
188	NULL, selmR3Save, NULL,
189	NULL, selmR3Load, selmR3LoadDone);
190	if (RT_FAILURE(rc))
191	return rc;
192
193	/*
194	* Statistics.
195	*/
196	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
197	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
198	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
199	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
200	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
201	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
202	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
203	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
204	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
205
206	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
207	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
208
209	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
210	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
211	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
212	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
213	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
214	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
215
216	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
217	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
218	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
219	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
220	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
221	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
222
223	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
224
225	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
226	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
227	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
228	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
229	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
230	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
231
232	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
233	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
234	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
235	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
236
237	/*
238	* Default action when entering raw mode for the first time
239	*/
240	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
241	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
242	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
243	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
244
245	/*
246	* Register info handlers.
247	*/
248	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
249	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
250	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
251	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
252	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
253	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
254
255	return rc;
256	}
257
258
259	/**
260	* Finalizes HMA page attributes.
261	*
262	* @returns VBox status code.
263	* @param pVM Pointer to the VM.
264	*/
265	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
266	{
267	/** @cfgm{/DoubleFault,bool,false}
268	* Enables catching of double faults in the raw-mode context VMM code. This can
269	* be used when the triple faults or hangs occur and one suspect an unhandled
270	* double fault. This is not enabled by default because it means making the
271	* hyper selectors writeable for all supervisor code, including the guest's.
272	* The double fault is a task switch and thus requires write access to the GDT
273	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
274	* 8 TSS for the back link.
275	*/
276	bool f;
277	#if defined(DEBUG_bird)
278	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
279	#else
280	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
281	#endif
282	AssertLogRelRCReturn(rc, rc);
283	if (f)
284	{
285	PX86DESC paGdt = pVM->selm.s.paGdtR3;
286	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
287	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
288	AssertRC(rc);
289	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
290	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
291	AssertRC(rc);
292	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
293	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
294	AssertRC(rc);
295	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
296	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
297	AssertRC(rc);
298	}
299	return VINF_SUCCESS;
300	}
301
302
303	/**
304	* Setup the hypervisor GDT selectors in our shadow table
305	*
306	* @param pVM Pointer to the VM.
307	*/
308	static void selmR3SetupHyperGDTSelectors(PVM pVM)
309	{
310	PX86DESC paGdt = pVM->selm.s.paGdtR3;
311
312	/*
313	* Set up global code and data descriptors for use in the guest context.
314	* Both are wide open (base 0, limit 4GB)
315	*/
316	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
317	pDesc->Gen.u16LimitLow = 0xffff;
318	pDesc->Gen.u4LimitHigh = 0xf;
319	pDesc->Gen.u16BaseLow = 0;
320	pDesc->Gen.u8BaseHigh1 = 0;
321	pDesc->Gen.u8BaseHigh2 = 0;
322	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
323	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
324	pDesc->Gen.u2Dpl = 0; /* supervisor */
325	pDesc->Gen.u1Present = 1;
326	pDesc->Gen.u1Available = 0;
327	pDesc->Gen.u1Long = 0;
328	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
329	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
330
331	/* data */
332	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
333	pDesc->Gen.u16LimitLow = 0xffff;
334	pDesc->Gen.u4LimitHigh = 0xf;
335	pDesc->Gen.u16BaseLow = 0;
336	pDesc->Gen.u8BaseHigh1 = 0;
337	pDesc->Gen.u8BaseHigh2 = 0;
338	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
339	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
340	pDesc->Gen.u2Dpl = 0; /* supervisor */
341	pDesc->Gen.u1Present = 1;
342	pDesc->Gen.u1Available = 0;
343	pDesc->Gen.u1Long = 0;
344	pDesc->Gen.u1DefBig = 1; /* big */
345	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
346
347	/* 64-bit mode code (& data?) */
348	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
349	pDesc->Gen.u16LimitLow = 0xffff;
350	pDesc->Gen.u4LimitHigh = 0xf;
351	pDesc->Gen.u16BaseLow = 0;
352	pDesc->Gen.u8BaseHigh1 = 0;
353	pDesc->Gen.u8BaseHigh2 = 0;
354	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
355	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
356	pDesc->Gen.u2Dpl = 0; /* supervisor */
357	pDesc->Gen.u1Present = 1;
358	pDesc->Gen.u1Available = 0;
359	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
360	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
361	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
362
363	/*
364	* TSS descriptor
365	*/
366	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
367	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
368	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
369	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
370	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
371	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
372	pDesc->Gen.u4LimitHigh = 0;
373	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
374	pDesc->Gen.u1DescType = 0; /* system */
375	pDesc->Gen.u2Dpl = 0; /* supervisor */
376	pDesc->Gen.u1Present = 1;
377	pDesc->Gen.u1Available = 0;
378	pDesc->Gen.u1Long = 0;
379	pDesc->Gen.u1DefBig = 0;
380	pDesc->Gen.u1Granularity = 0; /* byte limit */
381
382	/*
383	* TSS descriptor for trap 08
384	*/
385	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
386	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
387	pDesc->Gen.u4LimitHigh = 0;
388	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
389	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
390	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
391	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
392	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
393	pDesc->Gen.u1DescType = 0; /* system */
394	pDesc->Gen.u2Dpl = 0; /* supervisor */
395	pDesc->Gen.u1Present = 1;
396	pDesc->Gen.u1Available = 0;
397	pDesc->Gen.u1Long = 0;
398	pDesc->Gen.u1DefBig = 0;
399	pDesc->Gen.u1Granularity = 0; /* byte limit */
400	}
401
402	/**
403	* Applies relocations to data and code managed by this
404	* component. This function will be called at init and
405	* whenever the VMM need to relocate it self inside the GC.
406	*
407	* @param pVM The VM.
408	*/
409	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
410	{
411	PX86DESC paGdt = pVM->selm.s.paGdtR3;
412	LogFlow(("SELMR3Relocate\n"));
413
414	for (VMCPUID i = 0; i < pVM->cCpus; i++)
415	{
416	PVMCPU pVCpu = &pVM->aCpus[i];
417
418	/*
419	* Update GDTR and selector.
420	*/
421	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
422
423	/** @todo selector relocations should be a separate operation? */
424	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
425	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
426	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
427	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
428	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
429	}
430
431	selmR3SetupHyperGDTSelectors(pVM);
432
433	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
434	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
435	/*
436	* Update the TSSes.
437	*/
438	/* Only applies to raw mode which supports only 1 VCPU */
439	PVMCPU pVCpu = &pVM->aCpus[0];
440
441	/* Current TSS */
442	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
443	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
444	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
445	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
446	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
447	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
448	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
449
450	/* trap 08 */
451	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
452	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
453	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
454	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
455	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
456	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
457	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
458	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
459	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
460	pVM->selm.s.TssTrap08.fs = 0;
461	pVM->selm.s.TssTrap08.gs = 0;
462	pVM->selm.s.TssTrap08.selLdt = 0;
463	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
464	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
465	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
466	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
467	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
468	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
469	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
470	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
471	/* TRPM will be updating the eip */
472
473	if ( !pVM->selm.s.fDisableMonitoring
474	&& !VMMIsHwVirtExtForced(pVM))
475	{
476	/*
477	* Update shadow GDT/LDT/TSS write access handlers.
478	*/
479	int rc;
480	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
481	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
482	{
483	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
484	AssertRC(rc);
485	}
486	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
487	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
488	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
489	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
490	AssertRC(rc);
491	#endif
492	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
493	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
494	{
495	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
496	AssertRC(rc);
497	}
498	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
499	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
500	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
501	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
502	AssertRC(rc);
503	#endif
504
505	/*
506	* Update the GC LDT region handler and address.
507	*/
508	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
509	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
510	{
511	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
512	AssertRC(rc);
513	}
514	#endif
515	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
516	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
517	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
518	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
519	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
520	AssertRC(rc);
521	#endif
522	}
523	}
524
525
526	/**
527	* Terminates the SELM.
528	*
529	* Termination means cleaning up and freeing all resources,
530	* the VM it self is at this point powered off or suspended.
531	*
532	* @returns VBox status code.
533	* @param pVM Pointer to the VM.
534	*/
535	VMMR3DECL(int) SELMR3Term(PVM pVM)
536	{
537	NOREF(pVM);
538	return 0;
539	}
540
541
542	/**
543	* The VM is being reset.
544	*
545	* For the SELM component this means that any GDT/LDT/TSS monitors
546	* needs to be removed.
547	*
548	* @param pVM Pointer to the VM.
549	*/
550	VMMR3DECL(void) SELMR3Reset(PVM pVM)
551	{
552	LogFlow(("SELMR3Reset:\n"));
553	VM_ASSERT_EMT(pVM);
554
555	/*
556	* Uninstall guest GDT/LDT/TSS write access handlers.
557	*/
558	int rc = VINF_SUCCESS;
559	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
560	{
561	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
562	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
563	AssertRC(rc);
564	#endif
565	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
566	pVM->selm.s.GuestGdtr.cbGdt = 0;
567	}
568	pVM->selm.s.fGDTRangeRegistered = false;
569	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
570	{
571	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
572	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
573	AssertRC(rc);
574	#endif
575	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
576	}
577	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
578	{
579	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
580	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
581	AssertRC(rc);
582	#endif
583	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
584	pVM->selm.s.GCSelTss = RTSEL_MAX;
585	}
586
587	/*
588	* Re-initialize other members.
589	*/
590	pVM->selm.s.cbLdtLimit = 0;
591	pVM->selm.s.offLdtHyper = 0;
592	pVM->selm.s.cbMonitoredGuestTss = 0;
593
594	pVM->selm.s.fSyncTSSRing0Stack = false;
595
596	/*
597	* Default action when entering raw mode for the first time
598	*/
599	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
600	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
601	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
602	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
603	}
604
605	/**
606	* Disable GDT/LDT/TSS monitoring and syncing
607	*
608	* @param pVM Pointer to the VM.
609	*/
610	VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
611	{
612	/*
613	* Uninstall guest GDT/LDT/TSS write access handlers.
614	*/
615	int rc;
616	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
617	{
618	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
619	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
620	AssertRC(rc);
621	#endif
622	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
623	pVM->selm.s.GuestGdtr.cbGdt = 0;
624	}
625	pVM->selm.s.fGDTRangeRegistered = false;
626	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
627	{
628	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
629	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
630	AssertRC(rc);
631	#endif
632	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
633	}
634	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
635	{
636	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
637	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
638	AssertRC(rc);
639	#endif
640	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
641	pVM->selm.s.GCSelTss = RTSEL_MAX;
642	}
643
644	/*
645	* Unregister shadow GDT/LDT/TSS write access handlers.
646	*/
647	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
648	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
649	{
650	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
651	AssertRC(rc);
652	pVM->selm.s.paGdtRC = NIL_RTRCPTR;
653	}
654	#endif
655	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
656	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
657	{
658	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
659	AssertRC(rc);
660	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
661	}
662	#endif
663	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
664	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
665	{
666	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
667	AssertRC(rc);
668	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
669	}
670	#endif
671
672	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
673	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
674	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
675	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
676
677	pVM->selm.s.fDisableMonitoring = true;
678	}
679
680
681	/**
682	* Execute state save operation.
683	*
684	* @returns VBox status code.
685	* @param pVM Pointer to the VM.
686	* @param pSSM SSM operation handle.
687	*/
688	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
689	{
690	LogFlow(("selmR3Save:\n"));
691
692	/*
693	* Save the basic bits - fortunately all the other things can be resynced on load.
694	*/
695	PSELM pSelm = &pVM->selm.s;
696
697	SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
698	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
699	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
700	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
701	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
702	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
703	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
704	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
705	}
706
707
708	/**
709	* Execute state load operation.
710	*
711	* @returns VBox status code.
712	* @param pVM Pointer to the VM.
713	* @param pSSM SSM operation handle.
714	* @param uVersion Data layout version.
715	* @param uPass The data pass.
716	*/
717	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
718	{
719	LogFlow(("selmR3Load:\n"));
720	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
721
722	/*
723	* Validate version.
724	*/
725	if (uVersion != SELM_SAVED_STATE_VERSION)
726	{
727	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
728	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
729	}
730
731	/*
732	* Do a reset.
733	*/
734	SELMR3Reset(pVM);
735
736	/* Get the monitoring flag. */
737	SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
738
739	/* Get the TSS state flag. */
740	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
741
742	/*
743	* Get the selectors.
744	*/
745	RTSEL SelCS;
746	SSMR3GetSel(pSSM, &SelCS);
747	RTSEL SelDS;
748	SSMR3GetSel(pSSM, &SelDS);
749	RTSEL SelCS64;
750	SSMR3GetSel(pSSM, &SelCS64);
751	RTSEL SelDS64;
752	SSMR3GetSel(pSSM, &SelDS64);
753	RTSEL SelTSS;
754	SSMR3GetSel(pSSM, &SelTSS);
755	RTSEL SelTSSTrap08;
756	SSMR3GetSel(pSSM, &SelTSSTrap08);
757
758	/* Copy the selectors; they will be checked during relocation. */
759	PSELM pSelm = &pVM->selm.s;
760	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
761	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
762	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
763	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
764	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
765
766	return VINF_SUCCESS;
767	}
768
769
770	/**
771	* Sync the GDT, LDT and TSS after loading the state.
772	*
773	* Just to play save, we set the FFs to force syncing before
774	* executing GC code.
775	*
776	* @returns VBox status code.
777	* @param pVM Pointer to the VM.
778	* @param pSSM SSM operation handle.
779	*/
780	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
781	{
782	PVMCPU pVCpu = VMMGetCpu(pVM);
783
784	LogFlow(("selmR3LoadDone:\n"));
785
786	/*
787	* Don't do anything if it's a load failure.
788	*/
789	int rc = SSMR3HandleGetStatus(pSSM);
790	if (RT_FAILURE(rc))
791	return VINF_SUCCESS;
792
793	/*
794	* Do the syncing if we're in protected mode.
795	*/
796	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
797	{
798	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
799	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
800	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
801	SELMR3UpdateFromCPUM(pVM, pVCpu);
802	}
803
804	/*
805	* Flag everything for resync on next raw mode entry.
806	*/
807	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
808	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
809	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
810
811	return VINF_SUCCESS;
812	}
813
814	#ifdef VBOX_WITH_RAW_MODE
815
816	/**
817	* Updates (syncs) the shadow GDT.
818	*
819	* @returns VBox status code.
820	* @param pVM The VM handle.
821	* @param pVCpu The current virtual CPU.
822	*/
823	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
824	{
825	/*
826	* Always assume the best...
827	*/
828	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
829
830	/* If the GDT was changed, then make sure the LDT is checked too */
831	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
832	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
833	/* Same goes for the TSS selector */
834	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
835
836	/*
837	* Get the GDTR and check if there is anything to do (there usually is).
838	*/
839	VBOXGDTR GDTR;
840	CPUMGetGuestGDTR(pVCpu, &GDTR);
841	if (GDTR.cbGdt < sizeof(X86DESC))
842	{
843	Log(("No GDT entries...\n"));
844	return VINF_SUCCESS;
845	}
846
847	/*
848	* Read the Guest GDT.
849	* ASSUMES that the entire GDT is in memory.
850	*/
851	RTUINT cbEffLimit = GDTR.cbGdt;
852	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
853	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
854	if (RT_FAILURE(rc))
855	{
856	/*
857	* Read it page by page.
858	*
859	* Keep track of the last valid page and delay memsets and
860	* adjust cbEffLimit to reflect the effective size. The latter
861	* is something we do in the belief that the guest will probably
862	* never actually commit the last page, thus allowing us to keep
863	* our selectors in the high end of the GDT.
864	*/
865	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
866	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
867	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
868	uint8_t *pu8DstInvalid = pu8Dst;
869
870	while (cbLeft)
871	{
872	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
873	cb = RT_MIN(cb, cbLeft);
874	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
875	if (RT_SUCCESS(rc))
876	{
877	if (pu8DstInvalid != pu8Dst)
878	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
879	GCPtrSrc += cb;
880	pu8Dst += cb;
881	pu8DstInvalid = pu8Dst;
882	}
883	else if ( rc == VERR_PAGE_NOT_PRESENT
884	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
885	{
886	GCPtrSrc += cb;
887	pu8Dst += cb;
888	}
889	else
890	{
891	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
892	return VERR_SELM_GDT_READ_ERROR;
893	}
894	cbLeft -= cb;
895	}
896
897	/* any invalid pages at the end? */
898	if (pu8DstInvalid != pu8Dst)
899	{
900	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
901	/* If any GDTEs was invalidated, zero them. */
902	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
903	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
904	}
905
906	/* keep track of the effective limit. */
907	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
908	{
909	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
910	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
911	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
912	}
913	}
914
915	/*
916	* Check if the Guest GDT intrudes on our GDT entries.
917	*/
918	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
919	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
920	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
921	{
922	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
923	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
924	int iGDT = 0;
925
926	Log(("Internal SELM GDT conflict: use non-present entries\n"));
927	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
928	while (pGDTECur > pGDTEStart)
929	{
930	/* We can reuse non-present entries */
931	if (!pGDTECur->Gen.u1Present)
932	{
933	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
934	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
935	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
936	iGDT++;
937	if (iGDT >= SELM_HYPER_SEL_MAX)
938	break;
939	}
940
941	pGDTECur--;
942	}
943	if (iGDT != SELM_HYPER_SEL_MAX)
944	{
945	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
946	return VERR_SELM_GDT_TOO_FULL;
947	}
948	}
949	else
950	{
951	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
952	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
953	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
954	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
955	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
956	}
957
958	#ifdef VBOX_WITH_SAFE_STR
959	/** Use the guest's TR selector to plug the str virtualization hole. */
960	if (CPUMGetGuestTR(pVCpu, NULL) != 0)
961	{
962	Log(("SELM: Use guest TSS selector %x\n", CPUMGetGuestTR(pVCpu, NULL)));
963	aHyperSel[SELM_HYPER_SEL_TSS] = CPUMGetGuestTR(pVCpu, NULL);
964	}
965	#endif
966
967	/*
968	* Work thru the copied GDT entries adjusting them for correct virtualization.
969	*/
970	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
971	while (pGDTE < pGDTEEnd)
972	{
973	if (pGDTE->Gen.u1Present)
974	selmGuestToShadowDesc(pVM, pGDTE);
975
976	/* Next GDT entry. */
977	pGDTE++;
978	}
979
980	/*
981	* Check if our hypervisor selectors were changed.
982	*/
983	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
984	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
985	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
986	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
987	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
988	{
989	/* Reinitialize our hypervisor GDTs */
990	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
991	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
992	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
993	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
994	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
995
996	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
997
998	/*
999	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
1000	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1001	*/
1002	VMR3Relocate(pVM, 0);
1003	}
1004	else
1005	#ifdef VBOX_WITH_SAFE_STR
1006	if ( cbEffLimit >= SELM_HYPER_DEFAULT_BASE
1007	\|\| CPUMGetGuestTR(pVCpu, NULL) != 0) /* Our shadow TR entry was overwritten when we synced the guest's GDT. */
1008	#else
1009	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1010	#endif
1011	/* We overwrote all entries above, so we have to save them again. */
1012	selmR3SetupHyperGDTSelectors(pVM);
1013
1014	/*
1015	* Adjust the cached GDT limit.
1016	* Any GDT entries which have been removed must be cleared.
1017	*/
1018	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1019	{
1020	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1021	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1022	}
1023
1024	/*
1025	* Check if Guest's GDTR is changed.
1026	*/
1027	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1028	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1029	{
1030	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1031	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1032	/*
1033	* [Re]Register write virtual handler for guest's GDT.
1034	*/
1035	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1036	{
1037	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1038	AssertRC(rc);
1039	}
1040
1041	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1042	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1043	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1044	"Guest GDT write access handler");
1045	# ifdef VBOX_WITH_RAW_RING1
1046	/* Some guest OSes (QNX) share code and the GDT on the same page; PGMR3HandlerVirtualRegister doesn't support more than one handler, so we kick out the
1047	* PATM handler as this one is more important.
1048	* @todo fix this properly in PGMR3HandlerVirtualRegister
1049	*/
1050	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1051	{
1052	LogRel(("selmR3UpdateShadowGdt: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority GDT page monitor\n", GDTR.pGdt));
1053	rc = PGMHandlerVirtualDeregister(pVM, GDTR.pGdt & PAGE_BASE_GC_MASK);
1054	AssertRC(rc);
1055
1056	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1057	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1058	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1059	"Guest GDT write access handler");
1060	}
1061	# endif
1062	if (RT_FAILURE(rc))
1063	return rc;
1064	#endif
1065	/* Update saved Guest GDTR. */
1066	pVM->selm.s.GuestGdtr = GDTR;
1067	pVM->selm.s.fGDTRangeRegistered = true;
1068	}
1069
1070	return VINF_SUCCESS;
1071	}
1072
1073
1074	/**
1075	* Updates (syncs) the shadow LDT.
1076	*
1077	* @returns VBox status code.
1078	* @param pVM The VM handle.
1079	* @param pVCpu The current virtual CPU.
1080	*/
1081	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1082	{
1083	int rc = VINF_SUCCESS;
1084
1085	/*
1086	* Always assume the best...
1087	*/
1088	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1089
1090	/*
1091	* LDT handling is done similarly to the GDT handling with a shadow
1092	* array. However, since the LDT is expected to be swappable (at least
1093	* some ancient OSes makes it swappable) it must be floating and
1094	* synced on a per-page basis.
1095	*
1096	* Eventually we will change this to be fully on demand. Meaning that
1097	* we will only sync pages containing LDT selectors actually used and
1098	* let the #PF handler lazily sync pages as they are used.
1099	* (This applies to GDT too, when we start making OS/2 fast.)
1100	*/
1101
1102	/*
1103	* First, determine the current LDT selector.
1104	*/
1105	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1106	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1107	{
1108	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1109	CPUMSetHyperLDTR(pVCpu, 0);
1110	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1111	{
1112	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1113	AssertRC(rc);
1114	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1115	}
1116	pVM->selm.s.cbLdtLimit = 0;
1117	return VINF_SUCCESS;
1118	}
1119
1120	/*
1121	* Get the LDT selector.
1122	*/
1123	/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1124	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1125	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1126	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1127
1128	/*
1129	* Validate it.
1130	*/
1131	if ( !cbLdt
1132	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1133	\|\| pDesc->Gen.u1DescType
1134	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1135	{
1136	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1137
1138	/* cbLdt > 0:
1139	* This is quite impossible, so we do as most people do when faced with
1140	* the impossible, we simply ignore it.
1141	*/
1142	CPUMSetHyperLDTR(pVCpu, 0);
1143	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1144	{
1145	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1146	AssertRC(rc);
1147	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1148	}
1149	return VINF_SUCCESS;
1150	}
1151	/** @todo check what intel does about odd limits. */
1152	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1153
1154	/*
1155	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1156	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1157	*/
1158	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1159	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1160
1161
1162	/** @todo Handle only present LDT segments. */
1163	// if (pDesc->Gen.u1Present)
1164	{
1165	/*
1166	* Check if Guest's LDT address/limit is changed.
1167	*/
1168	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1169	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1170	{
1171	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1172	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1173
1174	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1175	/*
1176	* [Re]Register write virtual handler for guest's GDT.
1177	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1178	*/
1179	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1180	{
1181	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1182	AssertRC(rc);
1183	}
1184	# ifdef DEBUG
1185	if (pDesc->Gen.u1Present)
1186	Log(("LDT selector marked not present!!\n"));
1187	# endif
1188	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1189	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1190	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1191	{
1192	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1193	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1194	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1195	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1196	}
1197	else if (RT_SUCCESS(rc))
1198	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1199	else
1200	{
1201	CPUMSetHyperLDTR(pVCpu, 0);
1202	return rc;
1203	}
1204	#else
1205	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1206	#endif
1207	pVM->selm.s.cbLdtLimit = cbLdt;
1208	}
1209	}
1210
1211	/*
1212	* Calc Shadow LDT base.
1213	*/
1214	unsigned off;
1215	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1216	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1217	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1218
1219	/*
1220	* Enable the LDT selector in the shadow GDT.
1221	*/
1222	pDesc->Gen.u1Present = 1;
1223	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1224	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1225	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1226	pDesc->Gen.u1Available = 0;
1227	pDesc->Gen.u1Long = 0;
1228	if (cbLdt > 0xffff)
1229	{
1230	cbLdt = 0xffff;
1231	pDesc->Gen.u4LimitHigh = 0;
1232	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1233	}
1234
1235	/*
1236	* Set Hyper LDTR and notify TRPM.
1237	*/
1238	CPUMSetHyperLDTR(pVCpu, SelLdt);
1239
1240	/*
1241	* Loop synchronising the LDT page by page.
1242	*/
1243	/** @todo investigate how intel handle various operations on half present cross page entries. */
1244	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1245	//// AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1246
1247	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1248	unsigned cbLeft = cbLdt + 1;
1249	PX86DESC pLDTE = pShadowLDT;
1250	while (cbLeft)
1251	{
1252	/*
1253	* Read a chunk.
1254	*/
1255	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1256	if (cbChunk > cbLeft)
1257	cbChunk = cbLeft;
1258	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1259	if (RT_SUCCESS(rc))
1260	{
1261	/*
1262	* Mark page
1263	*/
1264	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1265	AssertRC(rc);
1266
1267	/*
1268	* Loop thru the available LDT entries.
1269	* Figure out where to start and end and the potential cross pageness of
1270	* things adds a little complexity. pLDTE is updated there and not in the
1271	* 'next' part of the loop. The pLDTEEnd is inclusive.
1272	*/
1273	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1274	if (pLDTE + 1 < pShadowLDT)
1275	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1276	while (pLDTE <= pLDTEEnd)
1277	{
1278	if (pLDTE->Gen.u1Present)
1279	selmGuestToShadowDesc(pVM, pLDTE);
1280
1281	/* Next LDT entry. */
1282	pLDTE++;
1283	}
1284	}
1285	else
1286	{
1287	RT_BZERO(pShadowLDT, cbChunk);
1288	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1289	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1290	AssertRC(rc);
1291	}
1292
1293	/*
1294	* Advance to the next page.
1295	*/
1296	cbLeft -= cbChunk;
1297	GCPtrShadowLDT += cbChunk;
1298	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1299	GCPtrLdt += cbChunk;
1300	}
1301
1302	return VINF_SUCCESS;
1303	}
1304
1305
1306	/**
1307	* Checks and updates segment selector registers.
1308	*
1309	* @returns VBox strict status code.
1310	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1311	*
1312	* @param pVM The VM handle.
1313	* @param pVCpu The current virtual CPU.
1314	*/
1315	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1316	{
1317	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1318
1319	/*
1320	* No stale selectors in V8086 mode.
1321	*/
1322	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1323	if (pCtx->eflags.Bits.u1VM)
1324	return VINF_SUCCESS;
1325
1326	/*
1327	* Check for stale selectors and load hidden register bits where they
1328	* are missing.
1329	*/
1330	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1331	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1332	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1333	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1334	{
1335	RTSEL const Sel = paSReg[iSReg].Sel;
1336	if (Sel & X86_SEL_MASK_OFF_RPL)
1337	{
1338	/* Get the shadow descriptor entry corresponding to this. */
1339	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1340	PCX86DESC pDesc;
1341	if (!(Sel & X86_SEL_LDT))
1342	{
1343	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1344	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1345	else
1346	pDesc = &s_NotPresentDesc;
1347	}
1348	else
1349	{
1350	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1351	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1352	else
1353	pDesc = &s_NotPresentDesc;
1354	}
1355
1356	/* Check the segment register. */
1357	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1358	{
1359	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1360	{
1361	/* Did it go stale? */
1362	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1363	{
1364	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1365	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1366	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1367	rcStrict = VINF_EM_RESCHEDULE_REM;
1368	}
1369	}
1370	else
1371	{
1372	/* Did it stop being stale? I.e. did the guest change it things
1373	back to the way they were? */
1374	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1375	{
1376	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1377	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1378	}
1379	else
1380	{
1381	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1382	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1383	rcStrict = VINF_EM_RESCHEDULE_REM;
1384	}
1385	}
1386	}
1387	/* Load the hidden registers if it's a valid descriptor for the
1388	current segment register. */
1389	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1390	{
1391	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1392	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1393	}
1394	/* It's stale. */
1395	else
1396	{
1397	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1398	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1399	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1400	rcStrict = VINF_EM_RESCHEDULE_REM;
1401	}
1402	}
1403	/* else: 0 selector, ignore. */
1404	}
1405
1406	return rcStrict;
1407	}
1408
1409	#endif /VBOX_WITH_RAW_MODE/
1410
1411
1412	/**
1413	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1414	*
1415	* @returns VBox status code.
1416	* @param pVM Pointer to the VM.
1417	* @param pVCpu Pointer to the VMCPU.
1418	*/
1419	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1420	{
1421	#ifdef VBOX_WITH_RAW_MODE
1422	if (pVM->selm.s.fDisableMonitoring)
1423	#endif
1424	{
1425	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
1426	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1427	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1428	return VINF_SUCCESS;
1429	}
1430
1431	#ifdef VBOX_WITH_RAW_MODE
1432	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1433
1434	/*
1435	* GDT sync
1436	*/
1437	int rc;
1438	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1439	{
1440	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1441	if (RT_FAILURE(rc))
1442	return rc; /* We're toast, so forget the profiling. */
1443	AssertRCSuccess(rc);
1444	}
1445
1446	/*
1447	* TSS sync
1448	*/
1449	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1450	{
1451	rc = SELMR3SyncTSS(pVM, pVCpu);
1452	if (RT_FAILURE(rc))
1453	return rc;
1454	AssertRCSuccess(rc);
1455	}
1456
1457	/*
1458	* LDT sync
1459	*/
1460	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1461	{
1462	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1463	if (RT_FAILURE(rc))
1464	return rc;
1465	AssertRCSuccess(rc);
1466	}
1467
1468	/*
1469	* Check selector registers.
1470	*/
1471	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1472
1473	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1474	return rcStrict;
1475	#endif
1476	}
1477
1478	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1479	/**
1480	* \#PF Handler callback for virtual access handler ranges.
1481	*
1482	* Important to realize that a physical page in a range can have aliases, and
1483	* for ALL and WRITE handlers these will also trigger.
1484	*
1485	* @returns VINF_SUCCESS if the handler have carried out the operation.
1486	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1487	* @param pVM Pointer to the VM.
1488	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1489	* @param pvPtr The HC mapping of that address.
1490	* @param pvBuf What the guest is reading/writing.
1491	* @param cbBuf How much it's reading/writing.
1492	* @param enmAccessType The access type.
1493	* @param pvUser User argument.
1494	*/
1495	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1496	PGMACCESSTYPE enmAccessType, void *pvUser)
1497	{
1498	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1499	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1500	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1501
1502	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1503	return VINF_PGM_HANDLER_DO_DEFAULT;
1504	}
1505	#endif
1506
1507	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1508	/**
1509	* \#PF Handler callback for virtual access handler ranges.
1510	*
1511	* Important to realize that a physical page in a range can have aliases, and
1512	* for ALL and WRITE handlers these will also trigger.
1513	*
1514	* @returns VINF_SUCCESS if the handler have carried out the operation.
1515	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1516	* @param pVM Pointer to the VM.
1517	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1518	* @param pvPtr The HC mapping of that address.
1519	* @param pvBuf What the guest is reading/writing.
1520	* @param cbBuf How much it's reading/writing.
1521	* @param enmAccessType The access type.
1522	* @param pvUser User argument.
1523	*/
1524	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1525	PGMACCESSTYPE enmAccessType, void *pvUser)
1526	{
1527	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1528	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1529	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1530
1531	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1532	return VINF_PGM_HANDLER_DO_DEFAULT;
1533	}
1534	#endif
1535
1536
1537	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1538	/**
1539	* \#PF Handler callback for virtual access handler ranges.
1540	*
1541	* Important to realize that a physical page in a range can have aliases, and
1542	* for ALL and WRITE handlers these will also trigger.
1543	*
1544	* @returns VINF_SUCCESS if the handler have carried out the operation.
1545	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1546	* @param pVM Pointer to the VM.
1547	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1548	* @param pvPtr The HC mapping of that address.
1549	* @param pvBuf What the guest is reading/writing.
1550	* @param cbBuf How much it's reading/writing.
1551	* @param enmAccessType The access type.
1552	* @param pvUser User argument.
1553	*/
1554	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1555	PGMACCESSTYPE enmAccessType, void *pvUser)
1556	{
1557	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1558	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1559	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1560
1561	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1562	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1563	* should probably also deregister the virtual handler if TR.base/size
1564	* changes while we're in REM. */
1565
1566	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1567	return VINF_PGM_HANDLER_DO_DEFAULT;
1568	}
1569	#endif
1570
1571	/**
1572	* Synchronize the shadowed fields in the TSS.
1573	*
1574	* At present we're shadowing the ring-0 stack selector & pointer, and the
1575	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1576	* REM and this function is called both if REM made any changes to the TSS or
1577	* loaded TR.
1578	*
1579	* @returns VBox status code.
1580	* @param pVM Pointer to the VM.
1581	* @param pVCpu Pointer to the VMCPU.
1582	*/
1583	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1584	{
1585	int rc;
1586
1587	#ifdef VBOX_WITH_RAW_MODE
1588	if (pVM->selm.s.fDisableMonitoring)
1589	#endif
1590	{
1591	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1592	return VINF_SUCCESS;
1593	}
1594
1595	#ifdef VBOX_WITH_RAW_MODE
1596	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1597	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1598
1599	/*
1600	* Get TR and extract and store the basic info.
1601	*
1602	* Note! The TSS limit is not checked by the LTR code, so we
1603	* have to be a bit careful with it. We make sure cbTss
1604	* won't be zero if TR is valid and if it's NULL we'll
1605	* make sure cbTss is 0.
1606	*/
1607	/** @todo use the hidden bits, not shadow GDT. */
1608	CPUMSELREGHID trHid;
1609	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1610	RTGCPTR GCPtrTss = trHid.u64Base;
1611	uint32_t cbTss = trHid.u32Limit;
1612	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1613	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1614	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1615	if (SelTss & X86_SEL_MASK_OFF_RPL)
1616	{
1617	Assert(!(SelTss & X86_SEL_LDT));
1618	Assert(trHid.Attr.n.u1DescType == 0);
1619	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1620	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1621	if (!++cbTss)
1622	cbTss = UINT32_MAX;
1623	}
1624	else
1625	{
1626	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1627	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1628	cbTss = 0; /* the reset case. */
1629	}
1630	pVM->selm.s.cbGuestTss = cbTss;
1631	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1632	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1633
1634	/*
1635	* Figure out the size of what need to monitor.
1636	*/
1637	/* We're not interested in any 16-bit TSSes. */
1638	uint32_t cbMonitoredTss = cbTss;
1639	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1640	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1641	cbMonitoredTss = 0;
1642
1643	pVM->selm.s.offGuestIoBitmap = 0;
1644	bool fNoRing1Stack = true;
1645	if (cbMonitoredTss)
1646	{
1647	/*
1648	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1649	* If VME is enabled we also want to keep an eye on the interrupt
1650	* redirection bitmap.
1651	*/
1652	VBOXTSS Tss;
1653	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1654	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1655	if ( !(cr4 & X86_CR4_VME)
1656	\|\| ( RT_SUCCESS(rc)
1657	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1658	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1659	)
1660	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1661	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1662	else if (RT_SUCCESS(rc))
1663	{
1664	/*
1665	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1666	* this can be quite a large chunk. We use to skip it earlier and just hope it
1667	* was kind of static...
1668	*
1669	* Update the virtual interrupt redirection bitmap while we're here.
1670	* (It is located in the 32 bytes before TR:offIoBitmap.)
1671	*/
1672	cbMonitoredTss = Tss.offIoBitmap;
1673	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1674
1675	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1676	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1677	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1678	AssertRC(rc);
1679	/** @todo memset the bitmap on failure? */
1680	Log2(("Redirection bitmap:\n"));
1681	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1682	}
1683	else
1684	{
1685	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1686	pVM->selm.s.offGuestIoBitmap = 0;
1687	/** @todo memset the bitmap? */
1688	}
1689
1690	/*
1691	* Update the ring 0 stack selector and base address.
1692	*/
1693	if (RT_SUCCESS(rc))
1694	{
1695	#ifdef LOG_ENABLED
1696	if (LogIsEnabled())
1697	{
1698	uint32_t ssr0, espr0;
1699	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1700	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1701	{
1702	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1703	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1704	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1705	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1706	AssertMsg(ssr0 != Tss.ss0,
1707	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1708	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1709	}
1710	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1711	}
1712	#endif /* LOG_ENABLED */
1713	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1714
1715	/* Update our TSS structure for the guest's ring 1 stack */
1716	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1717	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1718
1719	#ifdef VBOX_WITH_RAW_RING1
1720	/* Update our TSS structure for the guest's ring 2 stack */
1721	selmSetRing2Stack(pVM, (Tss.ss1 & ~1) \| 2, Tss.esp1);
1722
1723	if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) \| 1))
1724	\|\| pVM->selm.s.Tss.esp2 != Tss.esp1)
1725	{
1726	Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) \| 1, pVM->selm.s.Tss.esp2));
1727	}
1728	#endif
1729	}
1730	}
1731
1732	/*
1733	* Flush the ring-1 stack and the direct syscall dispatching if we
1734	* cannot obtain SS0:ESP0.
1735	*/
1736	if (fNoRing1Stack)
1737	{
1738	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1739	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1740
1741	/** @todo handle these dependencies better! */
1742	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1743	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1744	}
1745
1746	/*
1747	* Check for monitor changes and apply them.
1748	*/
1749	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1750	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1751	{
1752	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1753	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1754
1755	/* Release the old range first. */
1756	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1757	{
1758	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1759	AssertRC(rc);
1760	}
1761
1762	/* Register the write handler if TS != 0. */
1763	if (cbMonitoredTss != 0)
1764	{
1765	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1766	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1767	0, selmR3GuestTSSWriteHandler,
1768	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1769	if (RT_FAILURE(rc))
1770	{
1771	# ifdef VBOX_WITH_RAW_RING1
1772	/* Some guest OSes (QNX) share code and the TSS on the same page; PGMR3HandlerVirtualRegister doesn't support more than one handler, so we kick out the
1773	* PATM handler as this one is more important.
1774	* @todo fix this properly in PGMR3HandlerVirtualRegister
1775	*/
1776	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1777	{
1778	LogRel(("SELMR3SyncTSS: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority TSS page monitor\n", GCPtrTss));
1779	rc = PGMHandlerVirtualDeregister(pVM, GCPtrTss & PAGE_BASE_GC_MASK);
1780	AssertRC(rc);
1781
1782	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1783	0, selmR3GuestTSSWriteHandler,
1784	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1785	if (RT_FAILURE(rc))
1786	{
1787	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1788	return rc;
1789	}
1790	}
1791	# else
1792	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1793	return rc;
1794	# endif
1795	}
1796	#endif
1797	/* Update saved Guest TSS info. */
1798	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1799	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1800	pVM->selm.s.GCSelTss = SelTss;
1801	}
1802	else
1803	{
1804	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1805	pVM->selm.s.cbMonitoredGuestTss = 0;
1806	pVM->selm.s.GCSelTss = 0;
1807	}
1808	}
1809
1810	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1811
1812	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1813	return VINF_SUCCESS;
1814	#endif /VBOX_WITH_RAW_MODE/
1815	}
1816
1817	#ifdef VBOX_WITH_RAW_MODE
1818
1819	/**
1820	* Compares the Guest GDT and LDT with the shadow tables.
1821	* This is a VBOX_STRICT only function.
1822	*
1823	* @returns VBox status code.
1824	* @param pVM Pointer to the VM.
1825	*/
1826	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1827	{
1828	#ifdef VBOX_STRICT
1829	PVMCPU pVCpu = VMMGetCpu(pVM);
1830
1831	/*
1832	* Get GDTR and check for conflict.
1833	*/
1834	VBOXGDTR GDTR;
1835	CPUMGetGuestGDTR(pVCpu, &GDTR);
1836	if (GDTR.cbGdt == 0)
1837	return VINF_SUCCESS;
1838
1839	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1840	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1841
1842	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1843	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1844
1845	/*
1846	* Loop thru the GDT checking each entry.
1847	*/
1848	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1849	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1850	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1851	while (pGDTE < pGDTEEnd)
1852	{
1853	X86DESC GDTEGuest;
1854	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1855	if (RT_SUCCESS(rc))
1856	{
1857	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1858	{
1859	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1860	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1861	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1862	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1863	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1864	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1865	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1866	{
1867	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1868	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1869	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1870	}
1871	}
1872	}
1873
1874	/* Advance to the next descriptor. */
1875	GCPtrGDTEGuest += sizeof(X86DESC);
1876	pGDTE++;
1877	}
1878
1879
1880	/*
1881	* LDT?
1882	*/
1883	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1884	if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1885	return VINF_SUCCESS;
1886	Assert(!(SelLdt & X86_SEL_LDT));
1887	if (SelLdt > GDTR.cbGdt)
1888	{
1889	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1890	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1891	}
1892	X86DESC LDTDesc;
1893	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1894	if (RT_FAILURE(rc))
1895	{
1896	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1897	return rc;
1898	}
1899	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1900	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1901
1902	/*
1903	* Validate it.
1904	*/
1905	if (!cbLdt)
1906	return VINF_SUCCESS;
1907	/** @todo check what intel does about odd limits. */
1908	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1909	if ( LDTDesc.Gen.u1DescType
1910	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1911	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1912	{
1913	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1914	return VERR_SELM_INVALID_LDT;
1915	}
1916
1917	/*
1918	* Loop thru the LDT checking each entry.
1919	*/
1920	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1921	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1922	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1923	while (pLDTE < pLDTEEnd)
1924	{
1925	X86DESC LDTEGuest;
1926	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1927	if (RT_SUCCESS(rc))
1928	{
1929	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1930	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1931	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1932	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1933	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1934	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1935	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1936	{
1937	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1938	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1939	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1940	}
1941	}
1942
1943	/* Advance to the next descriptor. */
1944	GCPtrLDTEGuest += sizeof(X86DESC);
1945	pLDTE++;
1946	}
1947
1948	#else /* !VBOX_STRICT */
1949	NOREF(pVM);
1950	#endif /* !VBOX_STRICT */
1951
1952	return VINF_SUCCESS;
1953	}
1954
1955
1956	/**
1957	* Validates the RawR0 TSS values against the one in the Guest TSS.
1958	*
1959	* @returns true if it matches.
1960	* @returns false and assertions on mismatch..
1961	* @param pVM Pointer to the VM.
1962	*/
1963	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1964	{
1965	#if defined(VBOX_STRICT) && defined(SELM_TRACK_GUEST_TSS_CHANGES)
1966	PVMCPU pVCpu = VMMGetCpu(pVM);
1967
1968	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1969	return true;
1970
1971	/*
1972	* Get TR and extract the basic info.
1973	*/
1974	CPUMSELREGHID trHid;
1975	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1976	RTGCPTR GCPtrTss = trHid.u64Base;
1977	uint32_t cbTss = trHid.u32Limit;
1978	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1979	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1980	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1981	if (SelTss & X86_SEL_MASK_OFF_RPL)
1982	{
1983	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1984	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1985	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1986	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1987	false);
1988	if (!++cbTss)
1989	cbTss = UINT32_MAX;
1990	}
1991	else
1992	{
1993	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1994	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1995	false);
1996	cbTss = 0; /* the reset case. */
1997	}
1998	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1999	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2000	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
2001	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
2002	false);
2003	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
2004	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
2005	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
2006	false);
2007	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
2008	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
2009	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
2010	false);
2011
2012
2013	/*
2014	* Figure out the size of what need to monitor.
2015	*/
2016	/* We're not interested in any 16-bit TSSes. */
2017	uint32_t cbMonitoredTss = cbTss;
2018	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
2019	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2020	cbMonitoredTss = 0;
2021	if (cbMonitoredTss)
2022	{
2023	VBOXTSS Tss;
2024	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
2025	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
2026	AssertReturn( rc == VINF_SUCCESS
2027	/* Happens early in XP boot during page table switching. */
2028	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
2029	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
2030	false);
2031	if ( !(cr4 & X86_CR4_VME)
2032	\|\| ( RT_SUCCESS(rc)
2033	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
2034	&& Tss.offIoBitmap > cbTss)
2035	)
2036	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
2037	else if (RT_SUCCESS(rc))
2038	{
2039	cbMonitoredTss = Tss.offIoBitmap;
2040	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
2041	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
2042	false);
2043
2044	/* check the bitmap */
2045	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
2046	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
2047	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
2048	AssertRCReturn(rc, false);
2049	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
2050	("offIoBitmap=%#x cbTss=%#x\n"
2051	" Guest: %.32Rhxs\n"
2052	"Shadow: %.32Rhxs\n",
2053	Tss.offIoBitmap, cbTss,
2054	&Tss.IntRedirBitmap[0],
2055	&pVM->selm.s.Tss.IntRedirBitmap[0]),
2056	false);
2057	}
2058	else
2059	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
2060
2061	/*
2062	* Check SS0 and ESP0.
2063	*/
2064	if ( !pVM->selm.s.fSyncTSSRing0Stack
2065	&& RT_SUCCESS(rc))
2066	{
2067	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
2068	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
2069	{
2070	RTGCPHYS GCPhys;
2071	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
2072	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
2073	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
2074	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
2075	return false;
2076	}
2077	}
2078	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2079	}
2080	else
2081	{
2082	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
2083	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
2084	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2085	}
2086
2087
2088
2089	return true;
2090
2091	#else /* !VBOX_STRICT */
2092	NOREF(pVM);
2093	return true;
2094	#endif /* !VBOX_STRICT */
2095	}
2096
2097	# ifdef VBOX_WITH_SAFE_STR
2098	/**
2099	* Validates the RawR0 TR shadow GDT entry
2100	*
2101	* @returns true if it matches.
2102	* @returns false and assertions on mismatch..
2103	* @param pVM Pointer to the VM.
2104	*/
2105	VMMR3DECL(bool) SELMR3CheckShadowTR(PVM pVM)
2106	{
2107	# ifdef VBOX_STRICT
2108	PX86DESC paGdt = pVM->selm.s.paGdtR3;
2109
2110	/*
2111	* TSS descriptor
2112	*/
2113	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
2114	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
2115
2116	if ( pDesc->Gen.u16BaseLow != RT_LOWORD(RCPtrTSS)
2117	\|\| pDesc->Gen.u8BaseHigh1 != RT_BYTE3(RCPtrTSS)
2118	\|\| pDesc->Gen.u8BaseHigh2 != RT_BYTE4(RCPtrTSS)
2119	\|\| pDesc->Gen.u16LimitLow != sizeof(VBOXTSS) - 1
2120	\|\| pDesc->Gen.u4LimitHigh != 0
2121	\|\| (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL && pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2122	\|\| pDesc->Gen.u1DescType != 0 /* system */
2123	\|\| pDesc->Gen.u2Dpl != 0 /* supervisor */
2124	\|\| pDesc->Gen.u1Present != 1
2125	\|\| pDesc->Gen.u1Available != 0
2126	\|\| pDesc->Gen.u1Long != 0
2127	\|\| pDesc->Gen.u1DefBig != 0
2128	\|\| pDesc->Gen.u1Granularity != 0 /* byte limit */
2129	)
2130	{
2131	AssertFailed();
2132	return false;
2133	}
2134	# endif
2135	return true;
2136	}
2137	# endif
2138
2139	#endif /* VBOX_WITH_RAW_MODE */
2140
2141	/**
2142	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2143	*
2144	* See SELMR3GetSelectorInfo for details.
2145	*
2146	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2147	*
2148	* @param pVCpu Pointer to the VMCPU.
2149	* @param Sel The selector to get info about.
2150	* @param pSelInfo Where to store the information.
2151	*/
2152	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2153	{
2154	/*
2155	* Read it from the guest descriptor table.
2156	*/
2157	/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2158	X86DESC64 Desc;
2159	RTGCPTR GCPtrDesc;
2160	if (!(Sel & X86_SEL_LDT))
2161	{
2162	/* GDT */
2163	VBOXGDTR Gdtr;
2164	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2165	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2166	return VERR_INVALID_SELECTOR;
2167	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2168	}
2169	else
2170	{
2171	/* LDT */
2172	uint64_t GCPtrBase;
2173	uint32_t cbLimit;
2174	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2175	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2176	return VERR_INVALID_SELECTOR;
2177
2178	/* calc the descriptor location. */
2179	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2180	}
2181
2182	/* read the descriptor. */
2183	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2184	if (RT_FAILURE(rc))
2185	{
2186	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2187	if (RT_FAILURE(rc))
2188	return rc;
2189	Desc.au64[1] = 0;
2190	}
2191
2192	/*
2193	* Extract the base and limit
2194	* (We ignore the present bit here, which is probably a bit silly...)
2195	*/
2196	pSelInfo->Sel = Sel;
2197	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2198	pSelInfo->u.Raw64 = Desc;
2199	if (Desc.Gen.u1DescType)
2200	{
2201	/*
2202	* 64-bit code selectors are wide open, it's not possible to detect
2203	* 64-bit data or stack selectors without also dragging in assumptions
2204	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2205	* the selinfo user needs to deal with this in the context the info is
2206	* used unfortunately.
2207	*/
2208	if ( Desc.Gen.u1Long
2209	&& !Desc.Gen.u1DefBig
2210	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2211	{
2212	/* Note! We ignore the segment limit hacks that was added by AMD. */
2213	pSelInfo->GCPtrBase = 0;
2214	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2215	}
2216	else
2217	{
2218	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2219	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2220	}
2221	pSelInfo->SelGate = 0;
2222	}
2223	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2224	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2225	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2226	{
2227	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2228	in the AMD manual here as a simplification. */
2229	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2230	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2231	pSelInfo->SelGate = 0;
2232	}
2233	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2234	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2235	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2236	{
2237	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2238	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2239	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2240	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2241	pSelInfo->SelGate = Desc.Gate.u16Sel;
2242	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2243	}
2244	else
2245	{
2246	pSelInfo->cbLimit = 0;
2247	pSelInfo->GCPtrBase = 0;
2248	pSelInfo->SelGate = 0;
2249	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2250	}
2251	if (!Desc.Gen.u1Present)
2252	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2253
2254	return VINF_SUCCESS;
2255	}
2256
2257
2258	/**
2259	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2260	* interprets a legacy descriptor table entry and fills in the selector info
2261	* structure from it.
2262	*
2263	* @param pSelInfo Where to store the selector info. Only the fFlags and
2264	* Sel members have been initialized.
2265	* @param pDesc The legacy descriptor to parse.
2266	*/
2267	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2268	{
2269	pSelInfo->u.Raw64.au64[1] = 0;
2270	pSelInfo->u.Raw = *pDesc;
2271	if ( pDesc->Gen.u1DescType
2272	\|\| !(pDesc->Gen.u4Type & 4))
2273	{
2274	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2275	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2276	pSelInfo->SelGate = 0;
2277	}
2278	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2279	{
2280	pSelInfo->cbLimit = 0;
2281	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2282	pSelInfo->GCPtrBase = 0;
2283	else
2284	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2285	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2286	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2287	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2288	}
2289	else
2290	{
2291	pSelInfo->cbLimit = 0;
2292	pSelInfo->GCPtrBase = 0;
2293	pSelInfo->SelGate = 0;
2294	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2295	}
2296	if (!pDesc->Gen.u1Present)
2297	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2298	}
2299
2300
2301	/**
2302	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2303	*
2304	* See SELMR3GetSelectorInfo for details.
2305	*
2306	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2307	*
2308	* @param pVM Pointer to the VM.
2309	* @param pVCpu Pointer to the VMCPU.
2310	* @param Sel The selector to get info about.
2311	* @param pSelInfo Where to store the information.
2312	*/
2313	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2314	{
2315	/*
2316	* Read the descriptor entry
2317	*/
2318	pSelInfo->fFlags = 0;
2319	X86DESC Desc;
2320	if ( !(Sel & X86_SEL_LDT)
2321	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2322	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2323	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2324	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2325	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2326	)
2327	{
2328	/*
2329	* Hypervisor descriptor.
2330	*/
2331	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2332	if (CPUMIsGuestInProtectedMode(pVCpu))
2333	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2334	else
2335	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2336
2337	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2338	}
2339	else if (CPUMIsGuestInProtectedMode(pVCpu))
2340	{
2341	/*
2342	* Read it from the guest descriptor table.
2343	*/
2344	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2345
2346	RTGCPTR GCPtrDesc;
2347	if (!(Sel & X86_SEL_LDT))
2348	{
2349	/* GDT */
2350	VBOXGDTR Gdtr;
2351	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2352	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2353	return VERR_INVALID_SELECTOR;
2354	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2355	}
2356	else
2357	{
2358	/* LDT */
2359	uint64_t GCPtrBase;
2360	uint32_t cbLimit;
2361	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2362	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2363	return VERR_INVALID_SELECTOR;
2364
2365	/* calc the descriptor location. */
2366	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2367	}
2368
2369	/* read the descriptor. */
2370	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2371	if (RT_FAILURE(rc))
2372	return rc;
2373	}
2374	else
2375	{
2376	/*
2377	* We're in real mode.
2378	*/
2379	pSelInfo->Sel = Sel;
2380	pSelInfo->GCPtrBase = Sel << 4;
2381	pSelInfo->cbLimit = 0xffff;
2382	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2383	pSelInfo->u.Raw64.au64[0] = 0;
2384	pSelInfo->u.Raw64.au64[1] = 0;
2385	pSelInfo->SelGate = 0;
2386	return VINF_SUCCESS;
2387	}
2388
2389	/*
2390	* Extract the base and limit or sel:offset for gates.
2391	*/
2392	pSelInfo->Sel = Sel;
2393	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2394
2395	return VINF_SUCCESS;
2396	}
2397
2398
2399	/**
2400	* Gets information about a selector.
2401	*
2402	* Intended for the debugger mostly and will prefer the guest descriptor tables
2403	* over the shadow ones.
2404	*
2405	* @retval VINF_SUCCESS on success.
2406	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2407	* descriptor table.
2408	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2409	* is not returned if the selector itself isn't present, you have to
2410	* check that for yourself (see DBGFSELINFO::fFlags).
2411	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2412	* pagetable or page backing the selector table wasn't present.
2413	* @returns Other VBox status code on other errors.
2414	*
2415	* @param pVM Pointer to the VM.
2416	* @param pVCpu Pointer to the VMCPU.
2417	* @param Sel The selector to get info about.
2418	* @param pSelInfo Where to store the information.
2419	*/
2420	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2421	{
2422	AssertPtr(pSelInfo);
2423	if (CPUMIsGuestInLongMode(pVCpu))
2424	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2425	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2426	}
2427
2428
2429	/**
2430	* Gets information about a selector from the shadow tables.
2431	*
2432	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2433	* requires that the caller ensures that the shadow tables are up to date.
2434	*
2435	* @retval VINF_SUCCESS on success.
2436	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2437	* descriptor table.
2438	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2439	* is not returned if the selector itself isn't present, you have to
2440	* check that for yourself (see DBGFSELINFO::fFlags).
2441	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2442	* pagetable or page backing the selector table wasn't present.
2443	* @returns Other VBox status code on other errors.
2444	*
2445	* @param pVM Pointer to the VM.
2446	* @param Sel The selector to get info about.
2447	* @param pSelInfo Where to store the information.
2448	*
2449	* @remarks Don't use this when in hardware assisted virtualization mode.
2450	*/
2451	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2452	{
2453	Assert(pSelInfo);
2454
2455	/*
2456	* Read the descriptor entry
2457	*/
2458	X86DESC Desc;
2459	if (!(Sel & X86_SEL_LDT))
2460	{
2461	/*
2462	* Global descriptor.
2463	*/
2464	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2465	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2466	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2467	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2468	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2469	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2470	? DBGFSELINFO_FLAGS_HYPER
2471	: 0;
2472	/** @todo check that the GDT offset is valid. */
2473	}
2474	else
2475	{
2476	/*
2477	* Local Descriptor.
2478	*/
2479	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2480	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2481	/** @todo check if the LDT page is actually available. */
2482	/** @todo check that the LDT offset is valid. */
2483	pSelInfo->fFlags = 0;
2484	}
2485	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2486	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2487	else
2488	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2489
2490	/*
2491	* Extract the base and limit or sel:offset for gates.
2492	*/
2493	pSelInfo->Sel = Sel;
2494	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2495
2496	return VINF_SUCCESS;
2497	}
2498
2499
2500	/**
2501	* Formats a descriptor.
2502	*
2503	* @param Desc Descriptor to format.
2504	* @param Sel Selector number.
2505	* @param pszOutput Output buffer.
2506	* @param cchOutput Size of output buffer.
2507	*/
2508	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2509	{
2510	/*
2511	* Make variable description string.
2512	*/
2513	static struct
2514	{
2515	unsigned cch;
2516	const char *psz;
2517	} const aTypes[32] =
2518	{
2519	#define STRENTRY(str) { sizeof(str) - 1, str }
2520	/* system */
2521	STRENTRY("Reserved0 "), /* 0x00 */
2522	STRENTRY("TSS16Avail "), /* 0x01 */
2523	STRENTRY("LDT "), /* 0x02 */
2524	STRENTRY("TSS16Busy "), /* 0x03 */
2525	STRENTRY("Call16 "), /* 0x04 */
2526	STRENTRY("Task "), /* 0x05 */
2527	STRENTRY("Int16 "), /* 0x06 */
2528	STRENTRY("Trap16 "), /* 0x07 */
2529	STRENTRY("Reserved8 "), /* 0x08 */
2530	STRENTRY("TSS32Avail "), /* 0x09 */
2531	STRENTRY("ReservedA "), /* 0x0a */
2532	STRENTRY("TSS32Busy "), /* 0x0b */
2533	STRENTRY("Call32 "), /* 0x0c */
2534	STRENTRY("ReservedD "), /* 0x0d */
2535	STRENTRY("Int32 "), /* 0x0e */
2536	STRENTRY("Trap32 "), /* 0x0f */
2537	/* non system */
2538	STRENTRY("DataRO "), /* 0x10 */
2539	STRENTRY("DataRO Accessed "), /* 0x11 */
2540	STRENTRY("DataRW "), /* 0x12 */
2541	STRENTRY("DataRW Accessed "), /* 0x13 */
2542	STRENTRY("DataDownRO "), /* 0x14 */
2543	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2544	STRENTRY("DataDownRW "), /* 0x16 */
2545	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2546	STRENTRY("CodeEO "), /* 0x18 */
2547	STRENTRY("CodeEO Accessed "), /* 0x19 */
2548	STRENTRY("CodeER "), /* 0x1a */
2549	STRENTRY("CodeER Accessed "), /* 0x1b */
2550	STRENTRY("CodeConfEO "), /* 0x1c */
2551	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2552	STRENTRY("CodeConfER "), /* 0x1e */
2553	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2554	#undef SYSENTRY
2555	};
2556	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2557	char szMsg[128];
2558	char *psz = &szMsg[0];
2559	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2560	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2561	psz += aTypes[i].cch;
2562
2563	if (Desc.Gen.u1Present)
2564	ADD_STR(psz, "Present ");
2565	else
2566	ADD_STR(psz, "Not-Present ");
2567	if (Desc.Gen.u1Granularity)
2568	ADD_STR(psz, "Page ");
2569	if (Desc.Gen.u1DefBig)
2570	ADD_STR(psz, "32-bit ");
2571	else
2572	ADD_STR(psz, "16-bit ");
2573	#undef ADD_STR
2574	*psz = '\0';
2575
2576	/*
2577	* Limit and Base and format the output.
2578	*/
2579	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2580	uint32_t u32Base = X86DESC_BASE(&Desc);
2581
2582	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2583	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2584	}
2585
2586
2587	/**
2588	* Dumps a descriptor.
2589	*
2590	* @param Desc Descriptor to dump.
2591	* @param Sel Selector number.
2592	* @param pszMsg Message to prepend the log entry with.
2593	*/
2594	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2595	{
2596	char szOutput[128];
2597	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2598	Log(("%s: %s\n", pszMsg, szOutput));
2599	NOREF(szOutput[0]);
2600	}
2601
2602
2603	/**
2604	* Display the shadow gdt.
2605	*
2606	* @param pVM Pointer to the VM.
2607	* @param pHlp The info helpers.
2608	* @param pszArgs Arguments, ignored.
2609	*/
2610	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2611	{
2612	NOREF(pszArgs);
2613	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2614	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2615	{
2616	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2617	{
2618	char szOutput[128];
2619	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2620	const char *psz = "";
2621	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2622	psz = " HyperCS";
2623	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2624	psz = " HyperDS";
2625	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2626	psz = " HyperCS64";
2627	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2628	psz = " HyperTSS";
2629	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2630	psz = " HyperTSSTrap08";
2631	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2632	}
2633	}
2634	}
2635
2636
2637	/**
2638	* Display the guest gdt.
2639	*
2640	* @param pVM Pointer to the VM.
2641	* @param pHlp The info helpers.
2642	* @param pszArgs Arguments, ignored.
2643	*/
2644	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2645	{
2646	/** @todo SMP support! */
2647	PVMCPU pVCpu = &pVM->aCpus[0];
2648
2649	VBOXGDTR GDTR;
2650	CPUMGetGuestGDTR(pVCpu, &GDTR);
2651	RTGCPTR GCPtrGDT = GDTR.pGdt;
2652	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2653
2654	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2655	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2656	{
2657	X86DESC GDTE;
2658	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2659	if (RT_SUCCESS(rc))
2660	{
2661	if (GDTE.Gen.u1Present)
2662	{
2663	char szOutput[128];
2664	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2665	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2666	}
2667	}
2668	else if (rc == VERR_PAGE_NOT_PRESENT)
2669	{
2670	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2671	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2672	}
2673	else
2674	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2675	}
2676	NOREF(pszArgs);
2677	}
2678
2679
2680	/**
2681	* Display the shadow ldt.
2682	*
2683	* @param pVM Pointer to the VM.
2684	* @param pHlp The info helpers.
2685	* @param pszArgs Arguments, ignored.
2686	*/
2687	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2688	{
2689	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2690	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2691	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2692	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2693	{
2694	if (paLDT[iLDT].Gen.u1Present)
2695	{
2696	char szOutput[128];
2697	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2698	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2699	}
2700	}
2701	NOREF(pszArgs);
2702	}
2703
2704
2705	/**
2706	* Display the guest ldt.
2707	*
2708	* @param pVM Pointer to the VM.
2709	* @param pHlp The info helpers.
2710	* @param pszArgs Arguments, ignored.
2711	*/
2712	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2713	{
2714	/** @todo SMP support! */
2715	PVMCPU pVCpu = &pVM->aCpus[0];
2716
2717	uint64_t GCPtrLdt;
2718	uint32_t cbLdt;
2719	RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2720	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2721	{
2722	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2723	return;
2724	}
2725
2726	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2727	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2728	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2729	{
2730	X86DESC LdtE;
2731	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2732	if (RT_SUCCESS(rc))
2733	{
2734	if (LdtE.Gen.u1Present)
2735	{
2736	char szOutput[128];
2737	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2738	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2739	}
2740	}
2741	else if (rc == VERR_PAGE_NOT_PRESENT)
2742	{
2743	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2744	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2745	}
2746	else
2747	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2748	}
2749	NOREF(pszArgs);
2750	}
2751
2752
2753	/**
2754	* Dumps the hypervisor GDT
2755	*
2756	* @param pVM Pointer to the VM.
2757	*/
2758	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2759	{
2760	DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2761	}
2762
2763
2764	/**
2765	* Dumps the hypervisor LDT
2766	*
2767	* @param pVM Pointer to the VM.
2768	*/
2769	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2770	{
2771	DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2772	}
2773
2774
2775	/**
2776	* Dumps the guest GDT
2777	*
2778	* @param pVM Pointer to the VM.
2779	*/
2780	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2781	{
2782	DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2783	}
2784
2785
2786	/**
2787	* Dumps the guest LDT
2788	*
2789	* @param pVM Pointer to the VM.
2790	*/
2791	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2792	{
2793	DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2794	}
2795

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 45357

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