SELM.cpp@ 45665

Last change on this file since 45665 was 45618, checked in by vboxsync, 12 years ago
Do HMR3Init first in vmR3InitRing3 so the other components can skip raw-mode bits during init.
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File size: 108.3 KB

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1	/* $Id: SELM.cpp 45618 2013-04-18 18:41:07Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/em.h>
66	#include <VBox/vmm/hm.h>
67	#include <VBox/vmm/mm.h>
68	#include <VBox/vmm/ssm.h>
69	#include <VBox/vmm/pgm.h>
70	#include <VBox/vmm/trpm.h>
71	#include <VBox/vmm/dbgf.h>
72	#include "SELMInternal.h"
73	#include <VBox/vmm/vm.h>
74	#include <VBox/err.h>
75	#include <VBox/param.h>
76
77	#include <iprt/assert.h>
78	#include <VBox/log.h>
79	#include <iprt/asm.h>
80	#include <iprt/string.h>
81	#include <iprt/thread.h>
82	#include <iprt/string.h>
83
84	#include "SELMInline.h"
85
86
87	/** SELM saved state version. */
88	#define SELM_SAVED_STATE_VERSION 5
89
90
91	/*******************************************************************************
92	* Internal Functions *
93	*******************************************************************************/
94	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
95	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
96	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
97	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
98	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
99	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
100	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106
107
108	/*******************************************************************************
109	* Global Variables *
110	*******************************************************************************/
111	#ifdef LOG_ENABLED
112	/** Segment register names. */
113	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
114	#endif
115
116
117	/**
118	* Initializes the SELM.
119	*
120	* @returns VBox status code.
121	* @param pVM Pointer to the VM.
122	*/
123	VMMR3DECL(int) SELMR3Init(PVM pVM)
124	{
125	LogFlow(("SELMR3Init\n"));
126
127	/*
128	* Assert alignment and sizes.
129	* (The TSS block requires contiguous back.)
130	*/
131	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
132	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
133	#if 0 /* doesn't work */
134	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
135	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
136	#endif
137	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
138	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
139	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
140
141	/*
142	* Init the structure.
143	*/
144	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
145	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
146	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
147	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
148	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
149	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
150
151	/*
152	* Allocate GDT table.
153	*/
154	int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
155	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
156	AssertRCReturn(rc, rc);
157
158	/*
159	* Allocate LDT area.
160	*/
161	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
162	AssertRCReturn(rc, rc);
163
164	/*
165	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
166	*/
167	pVM->selm.s.cbEffGuestGdtLimit = 0;
168	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
169	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
170	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
171
172	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
173	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
174	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
175	pVM->selm.s.GCSelTss = RTSEL_MAX;
176
177	pVM->selm.s.fDisableMonitoring = false;
178	pVM->selm.s.fSyncTSSRing0Stack = false;
179
180	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
181	* for I/O operations. */
182	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
183	/* bit set to 1 means no redirection */
184	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
185
186	/*
187	* Register the saved state data unit.
188	*/
189	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
190	NULL, NULL, NULL,
191	NULL, selmR3Save, NULL,
192	NULL, selmR3Load, selmR3LoadDone);
193	if (RT_FAILURE(rc))
194	return rc;
195
196	/*
197	* Statistics.
198	*/
199	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
200	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
201	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
202	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
203	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
204	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
205	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
206	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
207	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
208
209	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
210	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
211
212	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
213	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
214	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
215	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
216	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
217	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
218
219	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
220	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
221	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
222	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
223	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
224	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
225
226	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
227
228	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
229	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
230	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
231	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
232	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
233	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
234
235	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
236	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
237	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
238	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
239
240	#ifdef VBOX_WITH_RAW_MODE
241	/*
242	* Default action when entering raw mode for the first time
243	*/
244	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
245	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
246	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
247	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
248	#endif
249
250	/*
251	* Register info handlers.
252	*/
253	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
254	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
255	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
256	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
257	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
258	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
259
260	return rc;
261	}
262
263
264	/**
265	* Finalizes HMA page attributes.
266	*
267	* @returns VBox status code.
268	* @param pVM Pointer to the VM.
269	*/
270	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
271	{
272	#ifdef VBOX_WITH_RAW_MODE
273	/** @cfgm{/DoubleFault,bool,false}
274	* Enables catching of double faults in the raw-mode context VMM code. This can
275	* be used when the triple faults or hangs occur and one suspect an unhandled
276	* double fault. This is not enabled by default because it means making the
277	* hyper selectors writeable for all supervisor code, including the guest's.
278	* The double fault is a task switch and thus requires write access to the GDT
279	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
280	* 8 TSS for the back link.
281	*/
282	bool f;
283	#if defined(DEBUG_bird)
284	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
285	#else
286	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
287	#endif
288	AssertLogRelRCReturn(rc, rc);
289	if (f)
290	{
291	PX86DESC paGdt = pVM->selm.s.paGdtR3;
292	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
293	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
294	AssertRC(rc);
295	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
296	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
297	AssertRC(rc);
298	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
299	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
300	AssertRC(rc);
301	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
302	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
303	AssertRC(rc);
304	}
305	#endif /* VBOX_WITH_RAW_MODE */
306	return VINF_SUCCESS;
307	}
308
309
310	/**
311	* Setup the hypervisor GDT selectors in our shadow table
312	*
313	* @param pVM Pointer to the VM.
314	*/
315	static void selmR3SetupHyperGDTSelectors(PVM pVM)
316	{
317	PX86DESC paGdt = pVM->selm.s.paGdtR3;
318
319	/*
320	* Set up global code and data descriptors for use in the guest context.
321	* Both are wide open (base 0, limit 4GB)
322	*/
323	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
324	pDesc->Gen.u16LimitLow = 0xffff;
325	pDesc->Gen.u4LimitHigh = 0xf;
326	pDesc->Gen.u16BaseLow = 0;
327	pDesc->Gen.u8BaseHigh1 = 0;
328	pDesc->Gen.u8BaseHigh2 = 0;
329	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
330	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
331	pDesc->Gen.u2Dpl = 0; /* supervisor */
332	pDesc->Gen.u1Present = 1;
333	pDesc->Gen.u1Available = 0;
334	pDesc->Gen.u1Long = 0;
335	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
336	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
337
338	/* data */
339	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
340	pDesc->Gen.u16LimitLow = 0xffff;
341	pDesc->Gen.u4LimitHigh = 0xf;
342	pDesc->Gen.u16BaseLow = 0;
343	pDesc->Gen.u8BaseHigh1 = 0;
344	pDesc->Gen.u8BaseHigh2 = 0;
345	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
346	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
347	pDesc->Gen.u2Dpl = 0; /* supervisor */
348	pDesc->Gen.u1Present = 1;
349	pDesc->Gen.u1Available = 0;
350	pDesc->Gen.u1Long = 0;
351	pDesc->Gen.u1DefBig = 1; /* big */
352	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
353
354	/* 64-bit mode code (& data?) */
355	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
356	pDesc->Gen.u16LimitLow = 0xffff;
357	pDesc->Gen.u4LimitHigh = 0xf;
358	pDesc->Gen.u16BaseLow = 0;
359	pDesc->Gen.u8BaseHigh1 = 0;
360	pDesc->Gen.u8BaseHigh2 = 0;
361	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
362	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
363	pDesc->Gen.u2Dpl = 0; /* supervisor */
364	pDesc->Gen.u1Present = 1;
365	pDesc->Gen.u1Available = 0;
366	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
367	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
368	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
369
370	/*
371	* TSS descriptor
372	*/
373	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
374	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
375	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
376	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
377	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
378	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
379	pDesc->Gen.u4LimitHigh = 0;
380	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
381	pDesc->Gen.u1DescType = 0; /* system */
382	pDesc->Gen.u2Dpl = 0; /* supervisor */
383	pDesc->Gen.u1Present = 1;
384	pDesc->Gen.u1Available = 0;
385	pDesc->Gen.u1Long = 0;
386	pDesc->Gen.u1DefBig = 0;
387	pDesc->Gen.u1Granularity = 0; /* byte limit */
388
389	/*
390	* TSS descriptor for trap 08
391	*/
392	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
393	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
394	pDesc->Gen.u4LimitHigh = 0;
395	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
396	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
397	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
398	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
399	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
400	pDesc->Gen.u1DescType = 0; /* system */
401	pDesc->Gen.u2Dpl = 0; /* supervisor */
402	pDesc->Gen.u1Present = 1;
403	pDesc->Gen.u1Available = 0;
404	pDesc->Gen.u1Long = 0;
405	pDesc->Gen.u1DefBig = 0;
406	pDesc->Gen.u1Granularity = 0; /* byte limit */
407	}
408
409	/**
410	* Applies relocations to data and code managed by this
411	* component. This function will be called at init and
412	* whenever the VMM need to relocate it self inside the GC.
413	*
414	* @param pVM The VM.
415	*/
416	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
417	{
418	PX86DESC paGdt = pVM->selm.s.paGdtR3;
419	LogFlow(("SELMR3Relocate\n"));
420
421	for (VMCPUID i = 0; i < pVM->cCpus; i++)
422	{
423	PVMCPU pVCpu = &pVM->aCpus[i];
424
425	/*
426	* Update GDTR and selector.
427	*/
428	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
429
430	/** @todo selector relocations should be a separate operation? */
431	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
432	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
433	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
434	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
435	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
436	}
437
438	selmR3SetupHyperGDTSelectors(pVM);
439
440	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
441	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
442	/*
443	* Update the TSSes.
444	*/
445	/* Only applies to raw mode which supports only 1 VCPU */
446	PVMCPU pVCpu = &pVM->aCpus[0];
447
448	/* Current TSS */
449	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
450	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
451	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
452	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
453	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
454	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
455	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
456
457	/* trap 08 */
458	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
459	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
460	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
461	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
462	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
463	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
464	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
465	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
466	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
467	pVM->selm.s.TssTrap08.fs = 0;
468	pVM->selm.s.TssTrap08.gs = 0;
469	pVM->selm.s.TssTrap08.selLdt = 0;
470	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
471	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
472	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
473	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
474	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
475	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
476	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
477	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
478	/* TRPM will be updating the eip */
479
480	if ( !pVM->selm.s.fDisableMonitoring
481	&& !HMIsEnabled(pVM))
482	{
483	/*
484	* Update shadow GDT/LDT/TSS write access handlers.
485	*/
486	int rc; NOREF(rc);
487	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
488	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
489	{
490	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
491	AssertRC(rc);
492	}
493	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
494	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
495	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
496	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
497	AssertRC(rc);
498	#endif
499	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
500	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
501	{
502	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
503	AssertRC(rc);
504	}
505	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
506	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
507	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
508	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
509	AssertRC(rc);
510	#endif
511
512	/*
513	* Update the GC LDT region handler and address.
514	*/
515	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
516	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
517	{
518	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
519	AssertRC(rc);
520	}
521	#endif
522	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
523	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
524	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
525	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
526	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
527	AssertRC(rc);
528	#endif
529	}
530	}
531
532
533	/**
534	* Terminates the SELM.
535	*
536	* Termination means cleaning up and freeing all resources,
537	* the VM it self is at this point powered off or suspended.
538	*
539	* @returns VBox status code.
540	* @param pVM Pointer to the VM.
541	*/
542	VMMR3DECL(int) SELMR3Term(PVM pVM)
543	{
544	NOREF(pVM);
545	return 0;
546	}
547
548
549	/**
550	* The VM is being reset.
551	*
552	* For the SELM component this means that any GDT/LDT/TSS monitors
553	* needs to be removed.
554	*
555	* @param pVM Pointer to the VM.
556	*/
557	VMMR3DECL(void) SELMR3Reset(PVM pVM)
558	{
559	LogFlow(("SELMR3Reset:\n"));
560	VM_ASSERT_EMT(pVM);
561
562	/*
563	* Uninstall guest GDT/LDT/TSS write access handlers.
564	*/
565	int rc = VINF_SUCCESS;
566	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
567	{
568	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
569	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
570	AssertRC(rc);
571	#endif
572	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
573	pVM->selm.s.GuestGdtr.cbGdt = 0;
574	}
575	pVM->selm.s.fGDTRangeRegistered = false;
576	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
577	{
578	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
579	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
580	AssertRC(rc);
581	#endif
582	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
583	}
584	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
585	{
586	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
587	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
588	AssertRC(rc);
589	#endif
590	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
591	pVM->selm.s.GCSelTss = RTSEL_MAX;
592	}
593
594	/*
595	* Re-initialize other members.
596	*/
597	pVM->selm.s.cbLdtLimit = 0;
598	pVM->selm.s.offLdtHyper = 0;
599	pVM->selm.s.cbMonitoredGuestTss = 0;
600
601	pVM->selm.s.fSyncTSSRing0Stack = false;
602
603	#ifdef VBOX_WITH_RAW_MODE
604	/*
605	* Default action when entering raw mode for the first time
606	*/
607	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
608	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
609	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
610	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
611	#endif
612	}
613
614
615	#ifdef VBOX_WITH_RAW_MODE
616	/**
617	* Disable GDT/LDT/TSS monitoring and syncing
618	*
619	* @param pVM Pointer to the VM.
620	*/
621	VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
622	{
623	/*
624	* Uninstall guest GDT/LDT/TSS write access handlers.
625	*/
626	int rc;
627	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
628	{
629	# ifdef SELM_TRACK_GUEST_GDT_CHANGES
630	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
631	AssertRC(rc);
632	# endif
633	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
634	pVM->selm.s.GuestGdtr.cbGdt = 0;
635	}
636	pVM->selm.s.fGDTRangeRegistered = false;
637	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
638	{
639	# ifdef SELM_TRACK_GUEST_LDT_CHANGES
640	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
641	AssertRC(rc);
642	# endif
643	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
644	}
645	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
646	{
647	# ifdef SELM_TRACK_GUEST_TSS_CHANGES
648	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
649	AssertRC(rc);
650	# endif
651	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
652	pVM->selm.s.GCSelTss = RTSEL_MAX;
653	}
654
655	/*
656	* Unregister shadow GDT/LDT/TSS write access handlers.
657	*/
658	# ifdef SELM_TRACK_SHADOW_GDT_CHANGES
659	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
660	{
661	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
662	AssertRC(rc);
663	pVM->selm.s.paGdtRC = NIL_RTRCPTR;
664	}
665	# endif
666	# ifdef SELM_TRACK_SHADOW_TSS_CHANGES
667	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
668	{
669	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
670	AssertRC(rc);
671	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
672	}
673	# endif
674	# ifdef SELM_TRACK_SHADOW_LDT_CHANGES
675	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
676	{
677	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
678	AssertRC(rc);
679	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
680	}
681	# endif
682
683	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
684	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
685	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
686	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
687
688	pVM->selm.s.fDisableMonitoring = true;
689	}
690	#endif /* VBOX_WITH_RAW_MODE */
691
692
693	/**
694	* Execute state save operation.
695	*
696	* @returns VBox status code.
697	* @param pVM Pointer to the VM.
698	* @param pSSM SSM operation handle.
699	*/
700	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
701	{
702	LogFlow(("selmR3Save:\n"));
703
704	/*
705	* Save the basic bits - fortunately all the other things can be resynced on load.
706	*/
707	PSELM pSelm = &pVM->selm.s;
708
709	SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
710	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
711	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
712	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
713	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
714	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
715	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
716	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
717	}
718
719
720	/**
721	* Execute state load operation.
722	*
723	* @returns VBox status code.
724	* @param pVM Pointer to the VM.
725	* @param pSSM SSM operation handle.
726	* @param uVersion Data layout version.
727	* @param uPass The data pass.
728	*/
729	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
730	{
731	LogFlow(("selmR3Load:\n"));
732	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
733
734	/*
735	* Validate version.
736	*/
737	if (uVersion != SELM_SAVED_STATE_VERSION)
738	{
739	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
740	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
741	}
742
743	/*
744	* Do a reset.
745	*/
746	SELMR3Reset(pVM);
747
748	/* Get the monitoring flag. */
749	SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
750
751	/* Get the TSS state flag. */
752	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
753
754	/*
755	* Get the selectors.
756	*/
757	RTSEL SelCS;
758	SSMR3GetSel(pSSM, &SelCS);
759	RTSEL SelDS;
760	SSMR3GetSel(pSSM, &SelDS);
761	RTSEL SelCS64;
762	SSMR3GetSel(pSSM, &SelCS64);
763	RTSEL SelDS64;
764	SSMR3GetSel(pSSM, &SelDS64);
765	RTSEL SelTSS;
766	SSMR3GetSel(pSSM, &SelTSS);
767	RTSEL SelTSSTrap08;
768	SSMR3GetSel(pSSM, &SelTSSTrap08);
769
770	/* Copy the selectors; they will be checked during relocation. */
771	PSELM pSelm = &pVM->selm.s;
772	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
773	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
774	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
775	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
776	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
777
778	return VINF_SUCCESS;
779	}
780
781
782	/**
783	* Sync the GDT, LDT and TSS after loading the state.
784	*
785	* Just to play save, we set the FFs to force syncing before
786	* executing GC code.
787	*
788	* @returns VBox status code.
789	* @param pVM Pointer to the VM.
790	* @param pSSM SSM operation handle.
791	*/
792	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
793	{
794	#ifdef VBOX_WITH_RAW_MODE
795	PVMCPU pVCpu = VMMGetCpu(pVM);
796
797	LogFlow(("selmR3LoadDone:\n"));
798
799	/*
800	* Don't do anything if it's a load failure.
801	*/
802	int rc = SSMR3HandleGetStatus(pSSM);
803	if (RT_FAILURE(rc))
804	return VINF_SUCCESS;
805
806	/*
807	* Do the syncing if we're in protected mode.
808	*/
809	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
810	{
811	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
812	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
813	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
814	SELMR3UpdateFromCPUM(pVM, pVCpu);
815	}
816
817	/*
818	* Flag everything for resync on next raw mode entry.
819	*/
820	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
821	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
822	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
823
824	#endif /VBOX_WITH_RAW_MODE/
825	return VINF_SUCCESS;
826	}
827
828	#ifdef VBOX_WITH_RAW_MODE
829
830	/**
831	* Updates (syncs) the shadow GDT.
832	*
833	* @returns VBox status code.
834	* @param pVM The VM handle.
835	* @param pVCpu The current virtual CPU.
836	*/
837	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
838	{
839	/*
840	* Always assume the best...
841	*/
842	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
843
844	/* If the GDT was changed, then make sure the LDT is checked too */
845	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
846	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
847	/* Same goes for the TSS selector */
848	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
849
850	/*
851	* Get the GDTR and check if there is anything to do (there usually is).
852	*/
853	VBOXGDTR GDTR;
854	CPUMGetGuestGDTR(pVCpu, &GDTR);
855	if (GDTR.cbGdt < sizeof(X86DESC))
856	{
857	Log(("No GDT entries...\n"));
858	return VINF_SUCCESS;
859	}
860
861	/*
862	* Read the Guest GDT.
863	* ASSUMES that the entire GDT is in memory.
864	*/
865	RTUINT cbEffLimit = GDTR.cbGdt;
866	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
867	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
868	if (RT_FAILURE(rc))
869	{
870	/*
871	* Read it page by page.
872	*
873	* Keep track of the last valid page and delay memsets and
874	* adjust cbEffLimit to reflect the effective size. The latter
875	* is something we do in the belief that the guest will probably
876	* never actually commit the last page, thus allowing us to keep
877	* our selectors in the high end of the GDT.
878	*/
879	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
880	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
881	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
882	uint8_t *pu8DstInvalid = pu8Dst;
883
884	while (cbLeft)
885	{
886	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
887	cb = RT_MIN(cb, cbLeft);
888	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
889	if (RT_SUCCESS(rc))
890	{
891	if (pu8DstInvalid != pu8Dst)
892	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
893	GCPtrSrc += cb;
894	pu8Dst += cb;
895	pu8DstInvalid = pu8Dst;
896	}
897	else if ( rc == VERR_PAGE_NOT_PRESENT
898	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
899	{
900	GCPtrSrc += cb;
901	pu8Dst += cb;
902	}
903	else
904	{
905	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
906	return VERR_SELM_GDT_READ_ERROR;
907	}
908	cbLeft -= cb;
909	}
910
911	/* any invalid pages at the end? */
912	if (pu8DstInvalid != pu8Dst)
913	{
914	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
915	/* If any GDTEs was invalidated, zero them. */
916	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
917	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
918	}
919
920	/* keep track of the effective limit. */
921	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
922	{
923	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
924	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
925	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
926	}
927	}
928
929	/*
930	* Check if the Guest GDT intrudes on our GDT entries.
931	*/
932	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
933	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
934	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
935	{
936	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
937	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
938	int iGDT = 0;
939
940	Log(("Internal SELM GDT conflict: use non-present entries\n"));
941	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
942	while (pGDTECur > pGDTEStart)
943	{
944	/* We can reuse non-present entries */
945	if (!pGDTECur->Gen.u1Present)
946	{
947	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
948	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
949	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
950	iGDT++;
951	if (iGDT >= SELM_HYPER_SEL_MAX)
952	break;
953	}
954
955	pGDTECur--;
956	}
957	if (iGDT != SELM_HYPER_SEL_MAX)
958	{
959	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
960	return VERR_SELM_GDT_TOO_FULL;
961	}
962	}
963	else
964	{
965	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
966	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
967	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
968	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
969	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
970	}
971
972	#ifdef VBOX_WITH_SAFE_STR
973	/* Use the guest's TR selector to plug the str virtualization hole. */
974	if (CPUMGetGuestTR(pVCpu, NULL) != 0)
975	{
976	Log(("SELM: Use guest TSS selector %x\n", CPUMGetGuestTR(pVCpu, NULL)));
977	aHyperSel[SELM_HYPER_SEL_TSS] = CPUMGetGuestTR(pVCpu, NULL);
978	}
979	#endif
980
981	/*
982	* Work thru the copied GDT entries adjusting them for correct virtualization.
983	*/
984	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
985	while (pGDTE < pGDTEEnd)
986	{
987	if (pGDTE->Gen.u1Present)
988	selmGuestToShadowDesc(pVM, pGDTE);
989
990	/* Next GDT entry. */
991	pGDTE++;
992	}
993
994	/*
995	* Check if our hypervisor selectors were changed.
996	*/
997	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
998	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
999	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
1000	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
1001	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
1002	{
1003	/* Reinitialize our hypervisor GDTs */
1004	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1005	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1006	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1007	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1008	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1009
1010	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1011
1012	/*
1013	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
1014	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1015	*/
1016	VMR3Relocate(pVM, 0);
1017	}
1018	else
1019	#ifdef VBOX_WITH_SAFE_STR
1020	if ( cbEffLimit >= SELM_HYPER_DEFAULT_BASE
1021	\|\| CPUMGetGuestTR(pVCpu, NULL) != 0) /* Our shadow TR entry was overwritten when we synced the guest's GDT. */
1022	#else
1023	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1024	#endif
1025	/* We overwrote all entries above, so we have to save them again. */
1026	selmR3SetupHyperGDTSelectors(pVM);
1027
1028	/*
1029	* Adjust the cached GDT limit.
1030	* Any GDT entries which have been removed must be cleared.
1031	*/
1032	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1033	{
1034	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1035	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1036	}
1037
1038	/*
1039	* Check if Guest's GDTR is changed.
1040	*/
1041	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1042	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1043	{
1044	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1045
1046	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1047	/*
1048	* [Re]Register write virtual handler for guest's GDT.
1049	*/
1050	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1051	{
1052	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1053	AssertRC(rc);
1054	}
1055
1056	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1057	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1058	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1059	"Guest GDT write access handler");
1060	# ifdef VBOX_WITH_RAW_RING1
1061	/** @todo !HACK ALERT!
1062	* Some guest OSes (QNX) share code and the GDT on the same page;
1063	* PGMR3HandlerVirtualRegister doesn't support more than one handler,
1064	* so we kick out the PATM handler as this one is more important.
1065	* Fix this properly in PGMR3HandlerVirtualRegister?
1066	*/
1067	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1068	{
1069	LogRel(("selmR3UpdateShadowGdt: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority GDT page monitor\n", GDTR.pGdt));
1070	rc = PGMHandlerVirtualDeregister(pVM, GDTR.pGdt & PAGE_BASE_GC_MASK);
1071	AssertRC(rc);
1072
1073	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1074	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1075	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1076	"Guest GDT write access handler");
1077	}
1078	# endif
1079	if (RT_FAILURE(rc))
1080	return rc;
1081	#endif /* SELM_TRACK_GUEST_GDT_CHANGES */
1082
1083	/* Update saved Guest GDTR. */
1084	pVM->selm.s.GuestGdtr = GDTR;
1085	pVM->selm.s.fGDTRangeRegistered = true;
1086	}
1087
1088	return VINF_SUCCESS;
1089	}
1090
1091
1092	/**
1093	* Updates (syncs) the shadow LDT.
1094	*
1095	* @returns VBox status code.
1096	* @param pVM The VM handle.
1097	* @param pVCpu The current virtual CPU.
1098	*/
1099	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1100	{
1101	int rc = VINF_SUCCESS;
1102
1103	/*
1104	* Always assume the best...
1105	*/
1106	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1107
1108	/*
1109	* LDT handling is done similarly to the GDT handling with a shadow
1110	* array. However, since the LDT is expected to be swappable (at least
1111	* some ancient OSes makes it swappable) it must be floating and
1112	* synced on a per-page basis.
1113	*
1114	* Eventually we will change this to be fully on demand. Meaning that
1115	* we will only sync pages containing LDT selectors actually used and
1116	* let the #PF handler lazily sync pages as they are used.
1117	* (This applies to GDT too, when we start making OS/2 fast.)
1118	*/
1119
1120	/*
1121	* First, determine the current LDT selector.
1122	*/
1123	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1124	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1125	{
1126	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1127	CPUMSetHyperLDTR(pVCpu, 0);
1128	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1129	{
1130	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1131	AssertRC(rc);
1132	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1133	}
1134	pVM->selm.s.cbLdtLimit = 0;
1135	return VINF_SUCCESS;
1136	}
1137
1138	/*
1139	* Get the LDT selector.
1140	*/
1141	/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1142	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1143	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1144	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1145
1146	/*
1147	* Validate it.
1148	*/
1149	if ( !cbLdt
1150	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1151	\|\| pDesc->Gen.u1DescType
1152	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1153	{
1154	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1155
1156	/* cbLdt > 0:
1157	* This is quite impossible, so we do as most people do when faced with
1158	* the impossible, we simply ignore it.
1159	*/
1160	CPUMSetHyperLDTR(pVCpu, 0);
1161	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1162	{
1163	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1164	AssertRC(rc);
1165	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1166	}
1167	return VINF_SUCCESS;
1168	}
1169	/** @todo check what intel does about odd limits. */
1170	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1171
1172	/*
1173	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1174	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1175	*/
1176	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1177	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1178
1179
1180	/** @todo Handle only present LDT segments. */
1181	// if (pDesc->Gen.u1Present)
1182	{
1183	/*
1184	* Check if Guest's LDT address/limit is changed.
1185	*/
1186	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1187	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1188	{
1189	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1190	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1191
1192	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1193	/*
1194	* [Re]Register write virtual handler for guest's GDT.
1195	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1196	*/
1197	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1198	{
1199	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1200	AssertRC(rc);
1201	}
1202	# ifdef DEBUG
1203	if (pDesc->Gen.u1Present)
1204	Log(("LDT selector marked not present!!\n"));
1205	# endif
1206	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1207	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1208	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1209	{
1210	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1211	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1212	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1213	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1214	}
1215	else if (RT_SUCCESS(rc))
1216	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1217	else
1218	{
1219	CPUMSetHyperLDTR(pVCpu, 0);
1220	return rc;
1221	}
1222	#else
1223	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1224	#endif
1225	pVM->selm.s.cbLdtLimit = cbLdt;
1226	}
1227	}
1228
1229	/*
1230	* Calc Shadow LDT base.
1231	*/
1232	unsigned off;
1233	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1234	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1235	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1236
1237	/*
1238	* Enable the LDT selector in the shadow GDT.
1239	*/
1240	pDesc->Gen.u1Present = 1;
1241	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1242	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1243	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1244	pDesc->Gen.u1Available = 0;
1245	pDesc->Gen.u1Long = 0;
1246	if (cbLdt > 0xffff)
1247	{
1248	cbLdt = 0xffff;
1249	pDesc->Gen.u4LimitHigh = 0;
1250	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1251	}
1252
1253	/*
1254	* Set Hyper LDTR and notify TRPM.
1255	*/
1256	CPUMSetHyperLDTR(pVCpu, SelLdt);
1257
1258	/*
1259	* Loop synchronising the LDT page by page.
1260	*/
1261	/** @todo investigate how intel handle various operations on half present cross page entries. */
1262	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1263	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1264
1265	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1266	unsigned cbLeft = cbLdt + 1;
1267	PX86DESC pLDTE = pShadowLDT;
1268	while (cbLeft)
1269	{
1270	/*
1271	* Read a chunk.
1272	*/
1273	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1274	if (cbChunk > cbLeft)
1275	cbChunk = cbLeft;
1276	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1277	if (RT_SUCCESS(rc))
1278	{
1279	/*
1280	* Mark page
1281	*/
1282	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1283	AssertRC(rc);
1284
1285	/*
1286	* Loop thru the available LDT entries.
1287	* Figure out where to start and end and the potential cross pageness of
1288	* things adds a little complexity. pLDTE is updated there and not in the
1289	* 'next' part of the loop. The pLDTEEnd is inclusive.
1290	*/
1291	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1292	if (pLDTE + 1 < pShadowLDT)
1293	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1294	while (pLDTE <= pLDTEEnd)
1295	{
1296	if (pLDTE->Gen.u1Present)
1297	selmGuestToShadowDesc(pVM, pLDTE);
1298
1299	/* Next LDT entry. */
1300	pLDTE++;
1301	}
1302	}
1303	else
1304	{
1305	RT_BZERO(pShadowLDT, cbChunk);
1306	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1307	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1308	AssertRC(rc);
1309	}
1310
1311	/*
1312	* Advance to the next page.
1313	*/
1314	cbLeft -= cbChunk;
1315	GCPtrShadowLDT += cbChunk;
1316	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1317	GCPtrLdt += cbChunk;
1318	}
1319
1320	return VINF_SUCCESS;
1321	}
1322
1323
1324	/**
1325	* Checks and updates segment selector registers.
1326	*
1327	* @returns VBox strict status code.
1328	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1329	*
1330	* @param pVM The VM handle.
1331	* @param pVCpu The current virtual CPU.
1332	*/
1333	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1334	{
1335	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1336
1337	/*
1338	* No stale selectors in V8086 mode.
1339	*/
1340	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1341	if (pCtx->eflags.Bits.u1VM)
1342	return VINF_SUCCESS;
1343
1344	/*
1345	* Check for stale selectors and load hidden register bits where they
1346	* are missing.
1347	*/
1348	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1349	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1350	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1351	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1352	{
1353	RTSEL const Sel = paSReg[iSReg].Sel;
1354	if (Sel & X86_SEL_MASK_OFF_RPL)
1355	{
1356	/* Get the shadow descriptor entry corresponding to this. */
1357	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1358	PCX86DESC pDesc;
1359	if (!(Sel & X86_SEL_LDT))
1360	{
1361	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1362	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1363	else
1364	pDesc = &s_NotPresentDesc;
1365	}
1366	else
1367	{
1368	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1369	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1370	else
1371	pDesc = &s_NotPresentDesc;
1372	}
1373
1374	/* Check the segment register. */
1375	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1376	{
1377	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1378	{
1379	/* Did it go stale? */
1380	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1381	{
1382	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1383	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1384	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1385	rcStrict = VINF_EM_RESCHEDULE_REM;
1386	}
1387	}
1388	else
1389	{
1390	/* Did it stop being stale? I.e. did the guest change it things
1391	back to the way they were? */
1392	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1393	{
1394	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1395	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1396	}
1397	else
1398	{
1399	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1400	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1401	rcStrict = VINF_EM_RESCHEDULE_REM;
1402	}
1403	}
1404	}
1405	/* Load the hidden registers if it's a valid descriptor for the
1406	current segment register. */
1407	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1408	{
1409	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1410	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1411	}
1412	/* It's stale. */
1413	else
1414	{
1415	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1416	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1417	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1418	rcStrict = VINF_EM_RESCHEDULE_REM;
1419	}
1420	}
1421	/* else: 0 selector, ignore. */
1422	}
1423
1424	return rcStrict;
1425	}
1426
1427
1428	/**
1429	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1430	*
1431	* @returns VBox status code.
1432	* @param pVM Pointer to the VM.
1433	* @param pVCpu Pointer to the VMCPU.
1434	*/
1435	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1436	{
1437	if (pVM->selm.s.fDisableMonitoring)
1438	{
1439	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
1440	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1441	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1442	return VINF_SUCCESS;
1443	}
1444
1445	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1446
1447	/*
1448	* GDT sync
1449	*/
1450	int rc;
1451	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1452	{
1453	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1454	if (RT_FAILURE(rc))
1455	return rc; /* We're toast, so forget the profiling. */
1456	AssertRCSuccess(rc);
1457	}
1458
1459	/*
1460	* TSS sync
1461	*/
1462	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1463	{
1464	rc = SELMR3SyncTSS(pVM, pVCpu);
1465	if (RT_FAILURE(rc))
1466	return rc;
1467	AssertRCSuccess(rc);
1468	}
1469
1470	/*
1471	* LDT sync
1472	*/
1473	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1474	{
1475	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1476	if (RT_FAILURE(rc))
1477	return rc;
1478	AssertRCSuccess(rc);
1479	}
1480
1481	/*
1482	* Check selector registers.
1483	*/
1484	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1485
1486	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1487	return rcStrict;
1488	}
1489
1490	#endif /VBOX_WITH_RAW_MODE/
1491
1492	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1493	/**
1494	* \#PF Handler callback for virtual access handler ranges.
1495	*
1496	* Important to realize that a physical page in a range can have aliases, and
1497	* for ALL and WRITE handlers these will also trigger.
1498	*
1499	* @returns VINF_SUCCESS if the handler have carried out the operation.
1500	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1501	* @param pVM Pointer to the VM.
1502	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1503	* @param pvPtr The HC mapping of that address.
1504	* @param pvBuf What the guest is reading/writing.
1505	* @param cbBuf How much it's reading/writing.
1506	* @param enmAccessType The access type.
1507	* @param pvUser User argument.
1508	*/
1509	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1510	PGMACCESSTYPE enmAccessType, void *pvUser)
1511	{
1512	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1513	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1514	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1515
1516	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1517	return VINF_PGM_HANDLER_DO_DEFAULT;
1518	}
1519	#endif
1520
1521	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1522	/**
1523	* \#PF Handler callback for virtual access handler ranges.
1524	*
1525	* Important to realize that a physical page in a range can have aliases, and
1526	* for ALL and WRITE handlers these will also trigger.
1527	*
1528	* @returns VINF_SUCCESS if the handler have carried out the operation.
1529	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1530	* @param pVM Pointer to the VM.
1531	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1532	* @param pvPtr The HC mapping of that address.
1533	* @param pvBuf What the guest is reading/writing.
1534	* @param cbBuf How much it's reading/writing.
1535	* @param enmAccessType The access type.
1536	* @param pvUser User argument.
1537	*/
1538	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1539	PGMACCESSTYPE enmAccessType, void *pvUser)
1540	{
1541	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1542	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1543	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1544
1545	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1546	return VINF_PGM_HANDLER_DO_DEFAULT;
1547	}
1548	#endif
1549
1550
1551	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1552	/**
1553	* \#PF Handler callback for virtual access handler ranges.
1554	*
1555	* Important to realize that a physical page in a range can have aliases, and
1556	* for ALL and WRITE handlers these will also trigger.
1557	*
1558	* @returns VINF_SUCCESS if the handler have carried out the operation.
1559	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1560	* @param pVM Pointer to the VM.
1561	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1562	* @param pvPtr The HC mapping of that address.
1563	* @param pvBuf What the guest is reading/writing.
1564	* @param cbBuf How much it's reading/writing.
1565	* @param enmAccessType The access type.
1566	* @param pvUser User argument.
1567	*/
1568	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1569	PGMACCESSTYPE enmAccessType, void *pvUser)
1570	{
1571	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1572	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1573	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1574
1575	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1576	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1577	* should probably also deregister the virtual handler if TR.base/size
1578	* changes while we're in REM. */
1579
1580	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1581	return VINF_PGM_HANDLER_DO_DEFAULT;
1582	}
1583	#endif
1584
1585	#ifdef VBOX_WITH_RAW_MODE
1586
1587	/**
1588	* Synchronize the shadowed fields in the TSS.
1589	*
1590	* At present we're shadowing the ring-0 stack selector & pointer, and the
1591	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1592	* REM and this function is called both if REM made any changes to the TSS or
1593	* loaded TR.
1594	*
1595	* @returns VBox status code.
1596	* @param pVM Pointer to the VM.
1597	* @param pVCpu Pointer to the VMCPU.
1598	*/
1599	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1600	{
1601	int rc;
1602
1603	if (pVM->selm.s.fDisableMonitoring)
1604	{
1605	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1606	return VINF_SUCCESS;
1607	}
1608
1609	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1610	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1611
1612	/*
1613	* Get TR and extract and store the basic info.
1614	*
1615	* Note! The TSS limit is not checked by the LTR code, so we
1616	* have to be a bit careful with it. We make sure cbTss
1617	* won't be zero if TR is valid and if it's NULL we'll
1618	* make sure cbTss is 0.
1619	*/
1620	/** @todo use the hidden bits, not shadow GDT. */
1621	CPUMSELREGHID trHid;
1622	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1623	RTGCPTR GCPtrTss = trHid.u64Base;
1624	uint32_t cbTss = trHid.u32Limit;
1625	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1626	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1627	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1628	if (SelTss & X86_SEL_MASK_OFF_RPL)
1629	{
1630	Assert(!(SelTss & X86_SEL_LDT));
1631	Assert(trHid.Attr.n.u1DescType == 0);
1632	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1633	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1634	if (!++cbTss)
1635	cbTss = UINT32_MAX;
1636	}
1637	else
1638	{
1639	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1640	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1641	cbTss = 0; /* the reset case. */
1642	}
1643	pVM->selm.s.cbGuestTss = cbTss;
1644	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1645	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1646
1647	/*
1648	* Figure out the size of what need to monitor.
1649	*/
1650	/* We're not interested in any 16-bit TSSes. */
1651	uint32_t cbMonitoredTss = cbTss;
1652	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1653	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1654	cbMonitoredTss = 0;
1655
1656	pVM->selm.s.offGuestIoBitmap = 0;
1657	bool fNoRing1Stack = true;
1658	if (cbMonitoredTss)
1659	{
1660	/*
1661	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1662	* If VME is enabled we also want to keep an eye on the interrupt
1663	* redirection bitmap.
1664	*/
1665	VBOXTSS Tss;
1666	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1667	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1668	if ( !(cr4 & X86_CR4_VME)
1669	\|\| ( RT_SUCCESS(rc)
1670	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1671	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1672	)
1673	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1674	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1675	else if (RT_SUCCESS(rc))
1676	{
1677	/*
1678	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1679	* this can be quite a large chunk. We use to skip it earlier and just hope it
1680	* was kind of static...
1681	*
1682	* Update the virtual interrupt redirection bitmap while we're here.
1683	* (It is located in the 32 bytes before TR:offIoBitmap.)
1684	*/
1685	cbMonitoredTss = Tss.offIoBitmap;
1686	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1687
1688	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1689	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1690	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1691	AssertRC(rc);
1692	/** @todo memset the bitmap on failure? */
1693	Log2(("Redirection bitmap:\n"));
1694	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1695	}
1696	else
1697	{
1698	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1699	pVM->selm.s.offGuestIoBitmap = 0;
1700	/** @todo memset the bitmap? */
1701	}
1702
1703	/*
1704	* Update the ring 0 stack selector and base address.
1705	*/
1706	if (RT_SUCCESS(rc))
1707	{
1708	# ifdef LOG_ENABLED
1709	if (LogIsEnabled())
1710	{
1711	uint32_t ssr0, espr0;
1712	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1713	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1714	{
1715	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1716	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1717	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1718	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1719	AssertMsg(ssr0 != Tss.ss0,
1720	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1721	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1722	}
1723	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1724	}
1725	# endif /* LOG_ENABLED */
1726	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1727
1728	/* Update our TSS structure for the guest's ring 1 stack */
1729	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1730	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1731
1732	# ifdef VBOX_WITH_RAW_RING1
1733	/* Update our TSS structure for the guest's ring 2 stack */
1734	if (EMIsRawRing1Enabled(pVM))
1735	{
1736	if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) \| 1))
1737	\|\| pVM->selm.s.Tss.esp2 != Tss.esp1)
1738	Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) \| 1, pVM->selm.s.Tss.esp2));
1739	selmSetRing2Stack(pVM, (Tss.ss1 & ~1) \| 2, Tss.esp1);
1740	}
1741	# endif
1742	}
1743	}
1744
1745	/*
1746	* Flush the ring-1 stack and the direct syscall dispatching if we
1747	* cannot obtain SS0:ESP0.
1748	*/
1749	if (fNoRing1Stack)
1750	{
1751	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1752	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1753
1754	/** @todo handle these dependencies better! */
1755	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1756	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1757	}
1758
1759	/*
1760	* Check for monitor changes and apply them.
1761	*/
1762	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1763	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1764	{
1765	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1766	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1767
1768	/* Release the old range first. */
1769	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1770	{
1771	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1772	AssertRC(rc);
1773	}
1774
1775	/* Register the write handler if TS != 0. */
1776	if (cbMonitoredTss != 0)
1777	{
1778	# ifdef SELM_TRACK_GUEST_TSS_CHANGES
1779	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1780	0, selmR3GuestTSSWriteHandler,
1781	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1782	if (RT_FAILURE(rc))
1783	{
1784	# ifdef VBOX_WITH_RAW_RING1
1785	/** @todo !HACK ALERT!
1786	* Some guest OSes (QNX) share code and the TSS on the same page;
1787	* PGMR3HandlerVirtualRegister doesn't support more than one
1788	* handler, so we kick out the PATM handler as this one is more
1789	* important. Fix this properly in PGMR3HandlerVirtualRegister?
1790	*/
1791	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1792	{
1793	LogRel(("SELMR3SyncTSS: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority TSS page monitor\n", GCPtrTss));
1794	rc = PGMHandlerVirtualDeregister(pVM, GCPtrTss & PAGE_BASE_GC_MASK);
1795	AssertRC(rc);
1796
1797	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1798	0, selmR3GuestTSSWriteHandler,
1799	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1800	if (RT_FAILURE(rc))
1801	{
1802	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1803	return rc;
1804	}
1805	}
1806	# else
1807	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1808	return rc;
1809	# endif
1810	}
1811	# endif /* SELM_TRACK_GUEST_TSS_CHANGES */
1812
1813	/* Update saved Guest TSS info. */
1814	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1815	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1816	pVM->selm.s.GCSelTss = SelTss;
1817	}
1818	else
1819	{
1820	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1821	pVM->selm.s.cbMonitoredGuestTss = 0;
1822	pVM->selm.s.GCSelTss = 0;
1823	}
1824	}
1825
1826	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1827
1828	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1829	return VINF_SUCCESS;
1830	}
1831
1832
1833	/**
1834	* Compares the Guest GDT and LDT with the shadow tables.
1835	* This is a VBOX_STRICT only function.
1836	*
1837	* @returns VBox status code.
1838	* @param pVM Pointer to the VM.
1839	*/
1840	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1841	{
1842	#ifdef VBOX_STRICT
1843	PVMCPU pVCpu = VMMGetCpu(pVM);
1844
1845	/*
1846	* Get GDTR and check for conflict.
1847	*/
1848	VBOXGDTR GDTR;
1849	CPUMGetGuestGDTR(pVCpu, &GDTR);
1850	if (GDTR.cbGdt == 0)
1851	return VINF_SUCCESS;
1852
1853	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1854	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1855
1856	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1857	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1858
1859	/*
1860	* Loop thru the GDT checking each entry.
1861	*/
1862	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1863	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1864	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1865	while (pGDTE < pGDTEEnd)
1866	{
1867	X86DESC GDTEGuest;
1868	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1869	if (RT_SUCCESS(rc))
1870	{
1871	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1872	{
1873	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1874	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1875	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1876	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1877	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1878	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1879	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1880	{
1881	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1882	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1883	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1884	}
1885	}
1886	}
1887
1888	/* Advance to the next descriptor. */
1889	GCPtrGDTEGuest += sizeof(X86DESC);
1890	pGDTE++;
1891	}
1892
1893
1894	/*
1895	* LDT?
1896	*/
1897	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1898	if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1899	return VINF_SUCCESS;
1900	Assert(!(SelLdt & X86_SEL_LDT));
1901	if (SelLdt > GDTR.cbGdt)
1902	{
1903	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1904	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1905	}
1906	X86DESC LDTDesc;
1907	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1908	if (RT_FAILURE(rc))
1909	{
1910	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1911	return rc;
1912	}
1913	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1914	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1915
1916	/*
1917	* Validate it.
1918	*/
1919	if (!cbLdt)
1920	return VINF_SUCCESS;
1921	/** @todo check what intel does about odd limits. */
1922	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1923	if ( LDTDesc.Gen.u1DescType
1924	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1925	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1926	{
1927	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1928	return VERR_SELM_INVALID_LDT;
1929	}
1930
1931	/*
1932	* Loop thru the LDT checking each entry.
1933	*/
1934	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1935	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1936	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1937	while (pLDTE < pLDTEEnd)
1938	{
1939	X86DESC LDTEGuest;
1940	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1941	if (RT_SUCCESS(rc))
1942	{
1943	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1944	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1945	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1946	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1947	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1948	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1949	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1950	{
1951	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1952	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1953	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1954	}
1955	}
1956
1957	/* Advance to the next descriptor. */
1958	GCPtrLDTEGuest += sizeof(X86DESC);
1959	pLDTE++;
1960	}
1961
1962	#else /* !VBOX_STRICT */
1963	NOREF(pVM);
1964	#endif /* !VBOX_STRICT */
1965
1966	return VINF_SUCCESS;
1967	}
1968
1969
1970	/**
1971	* Validates the RawR0 TSS values against the one in the Guest TSS.
1972	*
1973	* @returns true if it matches.
1974	* @returns false and assertions on mismatch..
1975	* @param pVM Pointer to the VM.
1976	*/
1977	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1978	{
1979	#if defined(VBOX_STRICT) && defined(SELM_TRACK_GUEST_TSS_CHANGES)
1980	PVMCPU pVCpu = VMMGetCpu(pVM);
1981
1982	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1983	return true;
1984
1985	/*
1986	* Get TR and extract the basic info.
1987	*/
1988	CPUMSELREGHID trHid;
1989	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1990	RTGCPTR GCPtrTss = trHid.u64Base;
1991	uint32_t cbTss = trHid.u32Limit;
1992	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1993	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1994	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1995	if (SelTss & X86_SEL_MASK_OFF_RPL)
1996	{
1997	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1998	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1999	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
2000	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
2001	false);
2002	if (!++cbTss)
2003	cbTss = UINT32_MAX;
2004	}
2005	else
2006	{
2007	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
2008	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
2009	false);
2010	cbTss = 0; /* the reset case. */
2011	}
2012	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
2013	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2014	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
2015	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
2016	false);
2017	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
2018	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
2019	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
2020	false);
2021	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
2022	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
2023	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
2024	false);
2025
2026
2027	/*
2028	* Figure out the size of what need to monitor.
2029	*/
2030	/* We're not interested in any 16-bit TSSes. */
2031	uint32_t cbMonitoredTss = cbTss;
2032	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
2033	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2034	cbMonitoredTss = 0;
2035	if (cbMonitoredTss)
2036	{
2037	VBOXTSS Tss;
2038	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
2039	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
2040	AssertReturn( rc == VINF_SUCCESS
2041	/* Happens early in XP boot during page table switching. */
2042	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
2043	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
2044	false);
2045	if ( !(cr4 & X86_CR4_VME)
2046	\|\| ( RT_SUCCESS(rc)
2047	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
2048	&& Tss.offIoBitmap > cbTss)
2049	)
2050	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
2051	else if (RT_SUCCESS(rc))
2052	{
2053	cbMonitoredTss = Tss.offIoBitmap;
2054	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
2055	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
2056	false);
2057
2058	/* check the bitmap */
2059	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
2060	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
2061	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
2062	AssertRCReturn(rc, false);
2063	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
2064	("offIoBitmap=%#x cbTss=%#x\n"
2065	" Guest: %.32Rhxs\n"
2066	"Shadow: %.32Rhxs\n",
2067	Tss.offIoBitmap, cbTss,
2068	&Tss.IntRedirBitmap[0],
2069	&pVM->selm.s.Tss.IntRedirBitmap[0]),
2070	false);
2071	}
2072	else
2073	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
2074
2075	/*
2076	* Check SS0 and ESP0.
2077	*/
2078	if ( !pVM->selm.s.fSyncTSSRing0Stack
2079	&& RT_SUCCESS(rc))
2080	{
2081	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
2082	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
2083	{
2084	RTGCPHYS GCPhys;
2085	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
2086	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
2087	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
2088	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
2089	return false;
2090	}
2091	}
2092	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2093	}
2094	else
2095	{
2096	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
2097	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
2098	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2099	}
2100
2101
2102
2103	return true;
2104
2105	#else /* !VBOX_STRICT */
2106	NOREF(pVM);
2107	return true;
2108	#endif /* !VBOX_STRICT */
2109	}
2110
2111
2112	# ifdef VBOX_WITH_SAFE_STR
2113	/**
2114	* Validates the RawR0 TR shadow GDT entry.
2115	*
2116	* @returns true if it matches.
2117	* @returns false and assertions on mismatch..
2118	* @param pVM Pointer to the VM.
2119	*/
2120	VMMR3DECL(bool) SELMR3CheckShadowTR(PVM pVM)
2121	{
2122	# ifdef VBOX_STRICT
2123	PX86DESC paGdt = pVM->selm.s.paGdtR3;
2124
2125	/*
2126	* TSS descriptor
2127	*/
2128	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
2129	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
2130
2131	if ( pDesc->Gen.u16BaseLow != RT_LOWORD(RCPtrTSS)
2132	\|\| pDesc->Gen.u8BaseHigh1 != RT_BYTE3(RCPtrTSS)
2133	\|\| pDesc->Gen.u8BaseHigh2 != RT_BYTE4(RCPtrTSS)
2134	\|\| pDesc->Gen.u16LimitLow != sizeof(VBOXTSS) - 1
2135	\|\| pDesc->Gen.u4LimitHigh != 0
2136	\|\| (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL && pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2137	\|\| pDesc->Gen.u1DescType != 0 /* system */
2138	\|\| pDesc->Gen.u2Dpl != 0 /* supervisor */
2139	\|\| pDesc->Gen.u1Present != 1
2140	\|\| pDesc->Gen.u1Available != 0
2141	\|\| pDesc->Gen.u1Long != 0
2142	\|\| pDesc->Gen.u1DefBig != 0
2143	\|\| pDesc->Gen.u1Granularity != 0 /* byte limit */
2144	)
2145	{
2146	AssertFailed();
2147	return false;
2148	}
2149	# endif
2150	return true;
2151	}
2152	# endif /* VBOX_WITH_SAFE_STR */
2153
2154	#endif /* VBOX_WITH_RAW_MODE */
2155
2156	/**
2157	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2158	*
2159	* See SELMR3GetSelectorInfo for details.
2160	*
2161	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2162	*
2163	* @param pVCpu Pointer to the VMCPU.
2164	* @param Sel The selector to get info about.
2165	* @param pSelInfo Where to store the information.
2166	*/
2167	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2168	{
2169	/*
2170	* Read it from the guest descriptor table.
2171	*/
2172	/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2173	X86DESC64 Desc;
2174	RTGCPTR GCPtrDesc;
2175	if (!(Sel & X86_SEL_LDT))
2176	{
2177	/* GDT */
2178	VBOXGDTR Gdtr;
2179	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2180	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2181	return VERR_INVALID_SELECTOR;
2182	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2183	}
2184	else
2185	{
2186	/* LDT */
2187	uint64_t GCPtrBase;
2188	uint32_t cbLimit;
2189	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2190	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2191	return VERR_INVALID_SELECTOR;
2192
2193	/* calc the descriptor location. */
2194	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2195	}
2196
2197	/* read the descriptor. */
2198	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2199	if (RT_FAILURE(rc))
2200	{
2201	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2202	if (RT_FAILURE(rc))
2203	return rc;
2204	Desc.au64[1] = 0;
2205	}
2206
2207	/*
2208	* Extract the base and limit
2209	* (We ignore the present bit here, which is probably a bit silly...)
2210	*/
2211	pSelInfo->Sel = Sel;
2212	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2213	pSelInfo->u.Raw64 = Desc;
2214	if (Desc.Gen.u1DescType)
2215	{
2216	/*
2217	* 64-bit code selectors are wide open, it's not possible to detect
2218	* 64-bit data or stack selectors without also dragging in assumptions
2219	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2220	* the selinfo user needs to deal with this in the context the info is
2221	* used unfortunately.
2222	*/
2223	if ( Desc.Gen.u1Long
2224	&& !Desc.Gen.u1DefBig
2225	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2226	{
2227	/* Note! We ignore the segment limit hacks that was added by AMD. */
2228	pSelInfo->GCPtrBase = 0;
2229	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2230	}
2231	else
2232	{
2233	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2234	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2235	}
2236	pSelInfo->SelGate = 0;
2237	}
2238	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2239	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2240	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2241	{
2242	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2243	in the AMD manual here as a simplification. */
2244	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2245	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2246	pSelInfo->SelGate = 0;
2247	}
2248	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2249	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2250	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2251	{
2252	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2253	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2254	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2255	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2256	pSelInfo->SelGate = Desc.Gate.u16Sel;
2257	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2258	}
2259	else
2260	{
2261	pSelInfo->cbLimit = 0;
2262	pSelInfo->GCPtrBase = 0;
2263	pSelInfo->SelGate = 0;
2264	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2265	}
2266	if (!Desc.Gen.u1Present)
2267	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2268
2269	return VINF_SUCCESS;
2270	}
2271
2272
2273	/**
2274	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2275	* interprets a legacy descriptor table entry and fills in the selector info
2276	* structure from it.
2277	*
2278	* @param pSelInfo Where to store the selector info. Only the fFlags and
2279	* Sel members have been initialized.
2280	* @param pDesc The legacy descriptor to parse.
2281	*/
2282	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2283	{
2284	pSelInfo->u.Raw64.au64[1] = 0;
2285	pSelInfo->u.Raw = *pDesc;
2286	if ( pDesc->Gen.u1DescType
2287	\|\| !(pDesc->Gen.u4Type & 4))
2288	{
2289	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2290	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2291	pSelInfo->SelGate = 0;
2292	}
2293	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2294	{
2295	pSelInfo->cbLimit = 0;
2296	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2297	pSelInfo->GCPtrBase = 0;
2298	else
2299	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2300	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2301	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2302	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2303	}
2304	else
2305	{
2306	pSelInfo->cbLimit = 0;
2307	pSelInfo->GCPtrBase = 0;
2308	pSelInfo->SelGate = 0;
2309	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2310	}
2311	if (!pDesc->Gen.u1Present)
2312	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2313	}
2314
2315
2316	/**
2317	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2318	*
2319	* See SELMR3GetSelectorInfo for details.
2320	*
2321	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2322	*
2323	* @param pVM Pointer to the VM.
2324	* @param pVCpu Pointer to the VMCPU.
2325	* @param Sel The selector to get info about.
2326	* @param pSelInfo Where to store the information.
2327	*/
2328	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2329	{
2330	/*
2331	* Read the descriptor entry
2332	*/
2333	pSelInfo->fFlags = 0;
2334	X86DESC Desc;
2335	if ( !(Sel & X86_SEL_LDT)
2336	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2337	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2338	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2339	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2340	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2341	)
2342	{
2343	/*
2344	* Hypervisor descriptor.
2345	*/
2346	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2347	if (CPUMIsGuestInProtectedMode(pVCpu))
2348	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2349	else
2350	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2351
2352	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2353	}
2354	else if (CPUMIsGuestInProtectedMode(pVCpu))
2355	{
2356	/*
2357	* Read it from the guest descriptor table.
2358	*/
2359	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2360
2361	RTGCPTR GCPtrDesc;
2362	if (!(Sel & X86_SEL_LDT))
2363	{
2364	/* GDT */
2365	VBOXGDTR Gdtr;
2366	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2367	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2368	return VERR_INVALID_SELECTOR;
2369	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2370	}
2371	else
2372	{
2373	/* LDT */
2374	uint64_t GCPtrBase;
2375	uint32_t cbLimit;
2376	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2377	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2378	return VERR_INVALID_SELECTOR;
2379
2380	/* calc the descriptor location. */
2381	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2382	}
2383
2384	/* read the descriptor. */
2385	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2386	if (RT_FAILURE(rc))
2387	return rc;
2388	}
2389	else
2390	{
2391	/*
2392	* We're in real mode.
2393	*/
2394	pSelInfo->Sel = Sel;
2395	pSelInfo->GCPtrBase = Sel << 4;
2396	pSelInfo->cbLimit = 0xffff;
2397	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2398	pSelInfo->u.Raw64.au64[0] = 0;
2399	pSelInfo->u.Raw64.au64[1] = 0;
2400	pSelInfo->SelGate = 0;
2401	return VINF_SUCCESS;
2402	}
2403
2404	/*
2405	* Extract the base and limit or sel:offset for gates.
2406	*/
2407	pSelInfo->Sel = Sel;
2408	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2409
2410	return VINF_SUCCESS;
2411	}
2412
2413
2414	/**
2415	* Gets information about a selector.
2416	*
2417	* Intended for the debugger mostly and will prefer the guest descriptor tables
2418	* over the shadow ones.
2419	*
2420	* @retval VINF_SUCCESS on success.
2421	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2422	* descriptor table.
2423	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2424	* is not returned if the selector itself isn't present, you have to
2425	* check that for yourself (see DBGFSELINFO::fFlags).
2426	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2427	* pagetable or page backing the selector table wasn't present.
2428	* @returns Other VBox status code on other errors.
2429	*
2430	* @param pVM Pointer to the VM.
2431	* @param pVCpu Pointer to the VMCPU.
2432	* @param Sel The selector to get info about.
2433	* @param pSelInfo Where to store the information.
2434	*/
2435	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2436	{
2437	AssertPtr(pSelInfo);
2438	if (CPUMIsGuestInLongMode(pVCpu))
2439	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2440	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2441	}
2442
2443
2444	/**
2445	* Gets information about a selector from the shadow tables.
2446	*
2447	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2448	* requires that the caller ensures that the shadow tables are up to date.
2449	*
2450	* @retval VINF_SUCCESS on success.
2451	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2452	* descriptor table.
2453	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2454	* is not returned if the selector itself isn't present, you have to
2455	* check that for yourself (see DBGFSELINFO::fFlags).
2456	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2457	* pagetable or page backing the selector table wasn't present.
2458	* @returns Other VBox status code on other errors.
2459	*
2460	* @param pVM Pointer to the VM.
2461	* @param Sel The selector to get info about.
2462	* @param pSelInfo Where to store the information.
2463	*
2464	* @remarks Don't use this when in hardware assisted virtualization mode.
2465	*/
2466	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2467	{
2468	Assert(pSelInfo);
2469
2470	/*
2471	* Read the descriptor entry
2472	*/
2473	X86DESC Desc;
2474	if (!(Sel & X86_SEL_LDT))
2475	{
2476	/*
2477	* Global descriptor.
2478	*/
2479	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2480	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2481	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2482	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2483	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2484	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2485	? DBGFSELINFO_FLAGS_HYPER
2486	: 0;
2487	/** @todo check that the GDT offset is valid. */
2488	}
2489	else
2490	{
2491	/*
2492	* Local Descriptor.
2493	*/
2494	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2495	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2496	/** @todo check if the LDT page is actually available. */
2497	/** @todo check that the LDT offset is valid. */
2498	pSelInfo->fFlags = 0;
2499	}
2500	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2501	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2502	else
2503	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2504
2505	/*
2506	* Extract the base and limit or sel:offset for gates.
2507	*/
2508	pSelInfo->Sel = Sel;
2509	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2510
2511	return VINF_SUCCESS;
2512	}
2513
2514
2515	/**
2516	* Formats a descriptor.
2517	*
2518	* @param Desc Descriptor to format.
2519	* @param Sel Selector number.
2520	* @param pszOutput Output buffer.
2521	* @param cchOutput Size of output buffer.
2522	*/
2523	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2524	{
2525	/*
2526	* Make variable description string.
2527	*/
2528	static struct
2529	{
2530	unsigned cch;
2531	const char *psz;
2532	} const aTypes[32] =
2533	{
2534	#define STRENTRY(str) { sizeof(str) - 1, str }
2535	/* system */
2536	STRENTRY("Reserved0 "), /* 0x00 */
2537	STRENTRY("TSS16Avail "), /* 0x01 */
2538	STRENTRY("LDT "), /* 0x02 */
2539	STRENTRY("TSS16Busy "), /* 0x03 */
2540	STRENTRY("Call16 "), /* 0x04 */
2541	STRENTRY("Task "), /* 0x05 */
2542	STRENTRY("Int16 "), /* 0x06 */
2543	STRENTRY("Trap16 "), /* 0x07 */
2544	STRENTRY("Reserved8 "), /* 0x08 */
2545	STRENTRY("TSS32Avail "), /* 0x09 */
2546	STRENTRY("ReservedA "), /* 0x0a */
2547	STRENTRY("TSS32Busy "), /* 0x0b */
2548	STRENTRY("Call32 "), /* 0x0c */
2549	STRENTRY("ReservedD "), /* 0x0d */
2550	STRENTRY("Int32 "), /* 0x0e */
2551	STRENTRY("Trap32 "), /* 0x0f */
2552	/* non system */
2553	STRENTRY("DataRO "), /* 0x10 */
2554	STRENTRY("DataRO Accessed "), /* 0x11 */
2555	STRENTRY("DataRW "), /* 0x12 */
2556	STRENTRY("DataRW Accessed "), /* 0x13 */
2557	STRENTRY("DataDownRO "), /* 0x14 */
2558	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2559	STRENTRY("DataDownRW "), /* 0x16 */
2560	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2561	STRENTRY("CodeEO "), /* 0x18 */
2562	STRENTRY("CodeEO Accessed "), /* 0x19 */
2563	STRENTRY("CodeER "), /* 0x1a */
2564	STRENTRY("CodeER Accessed "), /* 0x1b */
2565	STRENTRY("CodeConfEO "), /* 0x1c */
2566	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2567	STRENTRY("CodeConfER "), /* 0x1e */
2568	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2569	#undef SYSENTRY
2570	};
2571	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2572	char szMsg[128];
2573	char *psz = &szMsg[0];
2574	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2575	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2576	psz += aTypes[i].cch;
2577
2578	if (Desc.Gen.u1Present)
2579	ADD_STR(psz, "Present ");
2580	else
2581	ADD_STR(psz, "Not-Present ");
2582	if (Desc.Gen.u1Granularity)
2583	ADD_STR(psz, "Page ");
2584	if (Desc.Gen.u1DefBig)
2585	ADD_STR(psz, "32-bit ");
2586	else
2587	ADD_STR(psz, "16-bit ");
2588	#undef ADD_STR
2589	*psz = '\0';
2590
2591	/*
2592	* Limit and Base and format the output.
2593	*/
2594	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2595	uint32_t u32Base = X86DESC_BASE(&Desc);
2596
2597	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2598	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2599	}
2600
2601
2602	/**
2603	* Dumps a descriptor.
2604	*
2605	* @param Desc Descriptor to dump.
2606	* @param Sel Selector number.
2607	* @param pszMsg Message to prepend the log entry with.
2608	*/
2609	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2610	{
2611	char szOutput[128];
2612	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2613	Log(("%s: %s\n", pszMsg, szOutput));
2614	NOREF(szOutput[0]);
2615	}
2616
2617
2618	/**
2619	* Display the shadow gdt.
2620	*
2621	* @param pVM Pointer to the VM.
2622	* @param pHlp The info helpers.
2623	* @param pszArgs Arguments, ignored.
2624	*/
2625	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2626	{
2627	NOREF(pszArgs);
2628	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2629	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2630	{
2631	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2632	{
2633	char szOutput[128];
2634	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2635	const char *psz = "";
2636	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2637	psz = " HyperCS";
2638	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2639	psz = " HyperDS";
2640	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2641	psz = " HyperCS64";
2642	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2643	psz = " HyperTSS";
2644	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2645	psz = " HyperTSSTrap08";
2646	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2647	}
2648	}
2649	}
2650
2651
2652	/**
2653	* Display the guest gdt.
2654	*
2655	* @param pVM Pointer to the VM.
2656	* @param pHlp The info helpers.
2657	* @param pszArgs Arguments, ignored.
2658	*/
2659	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2660	{
2661	/** @todo SMP support! */
2662	PVMCPU pVCpu = &pVM->aCpus[0];
2663
2664	VBOXGDTR GDTR;
2665	CPUMGetGuestGDTR(pVCpu, &GDTR);
2666	RTGCPTR GCPtrGDT = GDTR.pGdt;
2667	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2668
2669	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2670	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2671	{
2672	X86DESC GDTE;
2673	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2674	if (RT_SUCCESS(rc))
2675	{
2676	if (GDTE.Gen.u1Present)
2677	{
2678	char szOutput[128];
2679	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2680	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2681	}
2682	}
2683	else if (rc == VERR_PAGE_NOT_PRESENT)
2684	{
2685	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2686	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2687	}
2688	else
2689	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2690	}
2691	NOREF(pszArgs);
2692	}
2693
2694
2695	/**
2696	* Display the shadow ldt.
2697	*
2698	* @param pVM Pointer to the VM.
2699	* @param pHlp The info helpers.
2700	* @param pszArgs Arguments, ignored.
2701	*/
2702	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2703	{
2704	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2705	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2706	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2707	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2708	{
2709	if (paLDT[iLDT].Gen.u1Present)
2710	{
2711	char szOutput[128];
2712	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2713	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2714	}
2715	}
2716	NOREF(pszArgs);
2717	}
2718
2719
2720	/**
2721	* Display the guest ldt.
2722	*
2723	* @param pVM Pointer to the VM.
2724	* @param pHlp The info helpers.
2725	* @param pszArgs Arguments, ignored.
2726	*/
2727	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2728	{
2729	/** @todo SMP support! */
2730	PVMCPU pVCpu = &pVM->aCpus[0];
2731
2732	uint64_t GCPtrLdt;
2733	uint32_t cbLdt;
2734	RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2735	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2736	{
2737	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2738	return;
2739	}
2740
2741	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2742	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2743	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2744	{
2745	X86DESC LdtE;
2746	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2747	if (RT_SUCCESS(rc))
2748	{
2749	if (LdtE.Gen.u1Present)
2750	{
2751	char szOutput[128];
2752	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2753	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2754	}
2755	}
2756	else if (rc == VERR_PAGE_NOT_PRESENT)
2757	{
2758	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2759	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2760	}
2761	else
2762	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2763	}
2764	NOREF(pszArgs);
2765	}
2766
2767
2768	/**
2769	* Dumps the hypervisor GDT
2770	*
2771	* @param pVM Pointer to the VM.
2772	*/
2773	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2774	{
2775	DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2776	}
2777
2778
2779	/**
2780	* Dumps the hypervisor LDT
2781	*
2782	* @param pVM Pointer to the VM.
2783	*/
2784	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2785	{
2786	DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2787	}
2788
2789
2790	/**
2791	* Dumps the guest GDT
2792	*
2793	* @param pVM Pointer to the VM.
2794	*/
2795	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2796	{
2797	DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2798	}
2799
2800
2801	/**
2802	* Dumps the guest LDT
2803	*
2804	* @param pVM Pointer to the VM.
2805	*/
2806	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2807	{
2808	DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2809	}
2810

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 45665

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