SELM.cpp@ 45728

Last change on this file since 45728 was 45709, checked in by vboxsync, 12 years ago
SELM.cpp: Must cast pointers to uintptr_t before doing greater/less-than checks.
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1	/* $Id: SELM.cpp 45709 2013-04-24 15:14:09Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/em.h>
66	#include <VBox/vmm/hm.h>
67	#include <VBox/vmm/mm.h>
68	#include <VBox/vmm/ssm.h>
69	#include <VBox/vmm/pgm.h>
70	#include <VBox/vmm/trpm.h>
71	#include <VBox/vmm/dbgf.h>
72	#include "SELMInternal.h"
73	#include <VBox/vmm/vm.h>
74	#include <VBox/err.h>
75	#include <VBox/param.h>
76
77	#include <iprt/assert.h>
78	#include <VBox/log.h>
79	#include <iprt/asm.h>
80	#include <iprt/string.h>
81	#include <iprt/thread.h>
82	#include <iprt/string.h>
83
84	#include "SELMInline.h"
85
86
87	/** SELM saved state version. */
88	#define SELM_SAVED_STATE_VERSION 5
89
90
91	/*******************************************************************************
92	* Internal Functions *
93	*******************************************************************************/
94	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
95	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
96	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
97	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
98	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
99	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
100	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106
107
108	/*******************************************************************************
109	* Global Variables *
110	*******************************************************************************/
111	#ifdef LOG_ENABLED
112	/** Segment register names. */
113	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
114	#endif
115
116
117	/**
118	* Initializes the SELM.
119	*
120	* @returns VBox status code.
121	* @param pVM Pointer to the VM.
122	*/
123	VMMR3DECL(int) SELMR3Init(PVM pVM)
124	{
125	int rc;
126	LogFlow(("SELMR3Init\n"));
127
128	/*
129	* Assert alignment and sizes.
130	* (The TSS block requires contiguous back.)
131	*/
132	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
133	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
134	#if 0 /* doesn't work */
135	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
136	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
137	#endif
138	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
139	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
140	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
141
142	/*
143	* Init the structure.
144	*/
145	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
146	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
147	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
148	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
149	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
150	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
151
152	if (HMIsRawModeCtxNeeded(pVM))
153	{
154	/*
155	* Allocate GDT table.
156	*/
157	rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
158	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
159	AssertRCReturn(rc, rc);
160
161	/*
162	* Allocate LDT area.
163	*/
164	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
165	AssertRCReturn(rc, rc);
166	}
167
168	/*
169	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
170	*/
171	pVM->selm.s.cbEffGuestGdtLimit = 0;
172	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
173	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
174	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
175
176	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
177	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
178	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
179	pVM->selm.s.GCSelTss = RTSEL_MAX;
180
181	pVM->selm.s.fSyncTSSRing0Stack = false;
182
183	/* The I/O bitmap starts right after the virtual interrupt redirection
184	bitmap. Outside the TSS on purpose; the CPU will not check it for
185	I/O operations. */
186	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
187	/* bit set to 1 means no redirection */
188	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
189
190	/*
191	* Register the saved state data unit.
192	*/
193	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
194	NULL, NULL, NULL,
195	NULL, selmR3Save, NULL,
196	NULL, selmR3Load, selmR3LoadDone);
197	if (RT_FAILURE(rc))
198	return rc;
199
200	/*
201	* Statistics.
202	*/
203	if (!HMIsEnabled(pVM))
204	{
205	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
206	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
207	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
208	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
209	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
210	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
211	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
212	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
213	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
214
215	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
216	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
217
218	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
219	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
220	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
221	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
222	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
223	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
224
225	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
226	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
227	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
228	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
229	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
230	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
231
232	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
233
234	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
235	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
236	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
237	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
238	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
239	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
240	}
241
242	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
243	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
244	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
245	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
246
247	#ifdef VBOX_WITH_RAW_MODE
248	/*
249	* Default action when entering raw mode for the first time
250	*/
251	if (!HMIsEnabled(pVM))
252	{
253	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
254	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
255	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
256	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
257	}
258	#endif
259
260	/*
261	* Register info handlers.
262	*/
263	if (HMIsRawModeCtxNeeded(pVM))
264	{
265	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
266	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
267	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
268	}
269	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
270	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
271	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
272
273	return rc;
274	}
275
276
277	/**
278	* Finalizes HMA page attributes.
279	*
280	* @returns VBox status code.
281	* @param pVM Pointer to the VM.
282	*/
283	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
284	{
285	#ifdef VBOX_WITH_RAW_MODE
286	/** @cfgm{/DoubleFault,bool,false}
287	* Enables catching of double faults in the raw-mode context VMM code. This can
288	* be used when the triple faults or hangs occur and one suspect an unhandled
289	* double fault. This is not enabled by default because it means making the
290	* hyper selectors writeable for all supervisor code, including the guest's.
291	* The double fault is a task switch and thus requires write access to the GDT
292	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
293	* 8 TSS for the back link.
294	*/
295	bool f;
296	# if defined(DEBUG_bird)
297	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
298	# else
299	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
300	# endif
301	AssertLogRelRCReturn(rc, rc);
302	if (f && HMIsRawModeCtxNeeded(pVM))
303	{
304	PX86DESC paGdt = pVM->selm.s.paGdtR3;
305	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
306	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
307	AssertRC(rc);
308	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
309	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
310	AssertRC(rc);
311	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
312	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
313	AssertRC(rc);
314	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
315	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
316	AssertRC(rc);
317	}
318	#endif /* VBOX_WITH_RAW_MODE */
319	return VINF_SUCCESS;
320	}
321
322
323	/**
324	* Setup the hypervisor GDT selectors in our shadow table
325	*
326	* @param pVM Pointer to the VM.
327	*/
328	static void selmR3SetupHyperGDTSelectors(PVM pVM)
329	{
330	PX86DESC paGdt = pVM->selm.s.paGdtR3;
331
332	/*
333	* Set up global code and data descriptors for use in the guest context.
334	* Both are wide open (base 0, limit 4GB)
335	*/
336	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
337	pDesc->Gen.u16LimitLow = 0xffff;
338	pDesc->Gen.u4LimitHigh = 0xf;
339	pDesc->Gen.u16BaseLow = 0;
340	pDesc->Gen.u8BaseHigh1 = 0;
341	pDesc->Gen.u8BaseHigh2 = 0;
342	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
343	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
344	pDesc->Gen.u2Dpl = 0; /* supervisor */
345	pDesc->Gen.u1Present = 1;
346	pDesc->Gen.u1Available = 0;
347	pDesc->Gen.u1Long = 0;
348	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
349	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
350
351	/* data */
352	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
353	pDesc->Gen.u16LimitLow = 0xffff;
354	pDesc->Gen.u4LimitHigh = 0xf;
355	pDesc->Gen.u16BaseLow = 0;
356	pDesc->Gen.u8BaseHigh1 = 0;
357	pDesc->Gen.u8BaseHigh2 = 0;
358	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
359	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
360	pDesc->Gen.u2Dpl = 0; /* supervisor */
361	pDesc->Gen.u1Present = 1;
362	pDesc->Gen.u1Available = 0;
363	pDesc->Gen.u1Long = 0;
364	pDesc->Gen.u1DefBig = 1; /* big */
365	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
366
367	/* 64-bit mode code (& data?) */
368	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
369	pDesc->Gen.u16LimitLow = 0xffff;
370	pDesc->Gen.u4LimitHigh = 0xf;
371	pDesc->Gen.u16BaseLow = 0;
372	pDesc->Gen.u8BaseHigh1 = 0;
373	pDesc->Gen.u8BaseHigh2 = 0;
374	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
375	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
376	pDesc->Gen.u2Dpl = 0; /* supervisor */
377	pDesc->Gen.u1Present = 1;
378	pDesc->Gen.u1Available = 0;
379	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
380	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
381	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
382
383	/*
384	* TSS descriptor
385	*/
386	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
387	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
388	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
389	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
390	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
391	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
392	pDesc->Gen.u4LimitHigh = 0;
393	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
394	pDesc->Gen.u1DescType = 0; /* system */
395	pDesc->Gen.u2Dpl = 0; /* supervisor */
396	pDesc->Gen.u1Present = 1;
397	pDesc->Gen.u1Available = 0;
398	pDesc->Gen.u1Long = 0;
399	pDesc->Gen.u1DefBig = 0;
400	pDesc->Gen.u1Granularity = 0; /* byte limit */
401
402	/*
403	* TSS descriptor for trap 08
404	*/
405	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
406	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
407	pDesc->Gen.u4LimitHigh = 0;
408	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
409	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
410	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
411	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
412	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
413	pDesc->Gen.u1DescType = 0; /* system */
414	pDesc->Gen.u2Dpl = 0; /* supervisor */
415	pDesc->Gen.u1Present = 1;
416	pDesc->Gen.u1Available = 0;
417	pDesc->Gen.u1Long = 0;
418	pDesc->Gen.u1DefBig = 0;
419	pDesc->Gen.u1Granularity = 0; /* byte limit */
420	}
421
422	/**
423	* Applies relocations to data and code managed by this
424	* component. This function will be called at init and
425	* whenever the VMM need to relocate it self inside the GC.
426	*
427	* @param pVM The VM.
428	*/
429	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
430	{
431	PX86DESC paGdt = pVM->selm.s.paGdtR3;
432	LogFlow(("SELMR3Relocate\n"));
433
434	if (HMIsRawModeCtxNeeded(pVM))
435	{
436	for (VMCPUID i = 0; i < pVM->cCpus; i++)
437	{
438	PVMCPU pVCpu = &pVM->aCpus[i];
439
440	/*
441	* Update GDTR and selector.
442	*/
443	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
444
445	/** @todo selector relocations should be a separate operation? */
446	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
447	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
448	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
449	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
450	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
451	}
452
453	selmR3SetupHyperGDTSelectors(pVM);
454
455	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
456	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
457	/*
458	* Update the TSSes.
459	*/
460	/* Only applies to raw mode which supports only 1 VCPU */
461	PVMCPU pVCpu = &pVM->aCpus[0];
462
463	/* Current TSS */
464	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
465	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
466	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
467	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
468	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
469	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
470	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
471
472	/* trap 08 */
473	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
474	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
475	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
476	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
477	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
478	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
479	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
480	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
481	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
482	pVM->selm.s.TssTrap08.fs = 0;
483	pVM->selm.s.TssTrap08.gs = 0;
484	pVM->selm.s.TssTrap08.selLdt = 0;
485	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
486	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
487	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
488	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
489	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
490	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
491	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
492	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
493	/* TRPM will be updating the eip */
494	}
495
496	if (!HMIsEnabled(pVM))
497	{
498	/*
499	* Update shadow GDT/LDT/TSS write access handlers.
500	*/
501	int rc; NOREF(rc);
502	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
503	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
504	{
505	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
506	AssertRC(rc);
507	}
508	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
509	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
510	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
511	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
512	AssertRC(rc);
513	#endif
514	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
515	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
516	{
517	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
518	AssertRC(rc);
519	}
520	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
521	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
522	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
523	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
524	AssertRC(rc);
525	#endif
526
527	/*
528	* Update the GC LDT region handler and address.
529	*/
530	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
531	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
532	{
533	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
534	AssertRC(rc);
535	}
536	#endif
537	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
538	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
539	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
540	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
541	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
542	AssertRC(rc);
543	#endif
544	}
545	}
546
547
548	/**
549	* Terminates the SELM.
550	*
551	* Termination means cleaning up and freeing all resources,
552	* the VM it self is at this point powered off or suspended.
553	*
554	* @returns VBox status code.
555	* @param pVM Pointer to the VM.
556	*/
557	VMMR3DECL(int) SELMR3Term(PVM pVM)
558	{
559	NOREF(pVM);
560	return VINF_SUCCESS;
561	}
562
563
564	/**
565	* The VM is being reset.
566	*
567	* For the SELM component this means that any GDT/LDT/TSS monitors
568	* needs to be removed.
569	*
570	* @param pVM Pointer to the VM.
571	*/
572	VMMR3DECL(void) SELMR3Reset(PVM pVM)
573	{
574	LogFlow(("SELMR3Reset:\n"));
575	VM_ASSERT_EMT(pVM);
576
577	/*
578	* Uninstall guest GDT/LDT/TSS write access handlers.
579	*/
580	int rc = VINF_SUCCESS;
581	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
582	{
583	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
584	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
585	AssertRC(rc);
586	#endif
587	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
588	pVM->selm.s.GuestGdtr.cbGdt = 0;
589	}
590	pVM->selm.s.fGDTRangeRegistered = false;
591	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
592	{
593	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
594	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
595	AssertRC(rc);
596	#endif
597	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
598	}
599	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
600	{
601	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
602	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
603	AssertRC(rc);
604	#endif
605	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
606	pVM->selm.s.GCSelTss = RTSEL_MAX;
607	}
608
609	/*
610	* Re-initialize other members.
611	*/
612	pVM->selm.s.cbLdtLimit = 0;
613	pVM->selm.s.offLdtHyper = 0;
614	pVM->selm.s.cbMonitoredGuestTss = 0;
615
616	pVM->selm.s.fSyncTSSRing0Stack = false;
617
618	#ifdef VBOX_WITH_RAW_MODE
619	if (!HMIsEnabled(pVM))
620	{
621	/*
622	* Default action when entering raw mode for the first time
623	*/
624	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
625	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
626	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
627	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
628	}
629	#endif
630	}
631
632
633	/**
634	* Execute state save operation.
635	*
636	* @returns VBox status code.
637	* @param pVM Pointer to the VM.
638	* @param pSSM SSM operation handle.
639	*/
640	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
641	{
642	LogFlow(("selmR3Save:\n"));
643
644	/*
645	* Save the basic bits - fortunately all the other things can be resynced on load.
646	*/
647	PSELM pSelm = &pVM->selm.s;
648
649	SSMR3PutBool(pSSM, HMIsEnabled(pVM));
650	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
651	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
652	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
653	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
654	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
655	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
656	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
657	}
658
659
660	/**
661	* Execute state load operation.
662	*
663	* @returns VBox status code.
664	* @param pVM Pointer to the VM.
665	* @param pSSM SSM operation handle.
666	* @param uVersion Data layout version.
667	* @param uPass The data pass.
668	*/
669	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
670	{
671	LogFlow(("selmR3Load:\n"));
672	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
673
674	/*
675	* Validate version.
676	*/
677	if (uVersion != SELM_SAVED_STATE_VERSION)
678	{
679	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
680	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
681	}
682
683	/*
684	* Do a reset.
685	*/
686	SELMR3Reset(pVM);
687
688	/* Get the monitoring flag. */
689	bool fIgnored;
690	SSMR3GetBool(pSSM, &fIgnored);
691
692	/* Get the TSS state flag. */
693	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
694
695	/*
696	* Get the selectors.
697	*/
698	RTSEL SelCS;
699	SSMR3GetSel(pSSM, &SelCS);
700	RTSEL SelDS;
701	SSMR3GetSel(pSSM, &SelDS);
702	RTSEL SelCS64;
703	SSMR3GetSel(pSSM, &SelCS64);
704	RTSEL SelDS64;
705	SSMR3GetSel(pSSM, &SelDS64);
706	RTSEL SelTSS;
707	SSMR3GetSel(pSSM, &SelTSS);
708	RTSEL SelTSSTrap08;
709	SSMR3GetSel(pSSM, &SelTSSTrap08);
710
711	/* Copy the selectors; they will be checked during relocation. */
712	PSELM pSelm = &pVM->selm.s;
713	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
714	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
715	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
716	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
717	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
718
719	return VINF_SUCCESS;
720	}
721
722
723	/**
724	* Sync the GDT, LDT and TSS after loading the state.
725	*
726	* Just to play save, we set the FFs to force syncing before
727	* executing GC code.
728	*
729	* @returns VBox status code.
730	* @param pVM Pointer to the VM.
731	* @param pSSM SSM operation handle.
732	*/
733	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
734	{
735	#ifdef VBOX_WITH_RAW_MODE
736	if (!HMIsEnabled(pVM))
737	{
738	PVMCPU pVCpu = VMMGetCpu(pVM);
739
740	LogFlow(("selmR3LoadDone:\n"));
741
742	/*
743	* Don't do anything if it's a load failure.
744	*/
745	int rc = SSMR3HandleGetStatus(pSSM);
746	if (RT_FAILURE(rc))
747	return VINF_SUCCESS;
748
749	/*
750	* Do the syncing if we're in protected mode and using raw-mode.
751	*/
752	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
753	{
754	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
755	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
756	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
757	SELMR3UpdateFromCPUM(pVM, pVCpu);
758	}
759
760	/*
761	* Flag everything for resync on next raw mode entry.
762	*/
763	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
764	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
765	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
766	}
767	#endif /VBOX_WITH_RAW_MODE/
768	return VINF_SUCCESS;
769	}
770
771	#ifdef VBOX_WITH_RAW_MODE
772
773	/**
774	* Updates (syncs) the shadow GDT.
775	*
776	* @returns VBox status code.
777	* @param pVM The VM handle.
778	* @param pVCpu The current virtual CPU.
779	*/
780	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
781	{
782	Assert(!HMIsEnabled(pVM));
783
784	/*
785	* Always assume the best...
786	*/
787	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
788
789	/* If the GDT was changed, then make sure the LDT is checked too */
790	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
791	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
792	/* Same goes for the TSS selector */
793	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
794
795	/*
796	* Get the GDTR and check if there is anything to do (there usually is).
797	*/
798	VBOXGDTR GDTR;
799	CPUMGetGuestGDTR(pVCpu, &GDTR);
800	if (GDTR.cbGdt < sizeof(X86DESC))
801	{
802	Log(("No GDT entries...\n"));
803	return VINF_SUCCESS;
804	}
805
806	/*
807	* Read the Guest GDT.
808	* ASSUMES that the entire GDT is in memory.
809	*/
810	RTUINT cbEffLimit = GDTR.cbGdt;
811	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
812	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
813	if (RT_FAILURE(rc))
814	{
815	/*
816	* Read it page by page.
817	*
818	* Keep track of the last valid page and delay memsets and
819	* adjust cbEffLimit to reflect the effective size. The latter
820	* is something we do in the belief that the guest will probably
821	* never actually commit the last page, thus allowing us to keep
822	* our selectors in the high end of the GDT.
823	*/
824	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
825	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
826	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
827	uint8_t *pu8DstInvalid = pu8Dst;
828
829	while (cbLeft)
830	{
831	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
832	cb = RT_MIN(cb, cbLeft);
833	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
834	if (RT_SUCCESS(rc))
835	{
836	if (pu8DstInvalid != pu8Dst)
837	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
838	GCPtrSrc += cb;
839	pu8Dst += cb;
840	pu8DstInvalid = pu8Dst;
841	}
842	else if ( rc == VERR_PAGE_NOT_PRESENT
843	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
844	{
845	GCPtrSrc += cb;
846	pu8Dst += cb;
847	}
848	else
849	{
850	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
851	return VERR_SELM_GDT_READ_ERROR;
852	}
853	cbLeft -= cb;
854	}
855
856	/* any invalid pages at the end? */
857	if (pu8DstInvalid != pu8Dst)
858	{
859	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
860	/* If any GDTEs was invalidated, zero them. */
861	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
862	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
863	}
864
865	/* keep track of the effective limit. */
866	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
867	{
868	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
869	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
870	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
871	}
872	}
873
874	/*
875	* Check if the Guest GDT intrudes on our GDT entries.
876	*/
877	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
878	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
879	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
880	{
881	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
882	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
883	int iGDT = 0;
884
885	Log(("Internal SELM GDT conflict: use non-present entries\n"));
886	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
887	while ((uintptr_t)pGDTECur > (uintptr_t)pGDTEStart)
888	{
889	/* We can reuse non-present entries */
890	if (!pGDTECur->Gen.u1Present)
891	{
892	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
893	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
894	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
895	iGDT++;
896	if (iGDT >= SELM_HYPER_SEL_MAX)
897	break;
898	}
899
900	pGDTECur--;
901	}
902	if (iGDT != SELM_HYPER_SEL_MAX)
903	{
904	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
905	return VERR_SELM_GDT_TOO_FULL;
906	}
907	}
908	else
909	{
910	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
911	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
912	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
913	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
914	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
915	}
916
917	# ifdef VBOX_WITH_SAFE_STR
918	/* Use the guest's TR selector to plug the str virtualization hole. */
919	if (CPUMGetGuestTR(pVCpu, NULL) != 0)
920	{
921	Log(("SELM: Use guest TSS selector %x\n", CPUMGetGuestTR(pVCpu, NULL)));
922	aHyperSel[SELM_HYPER_SEL_TSS] = CPUMGetGuestTR(pVCpu, NULL);
923	}
924	# endif
925
926	/*
927	* Work thru the copied GDT entries adjusting them for correct virtualization.
928	*/
929	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
930	while (pGDTE < pGDTEEnd)
931	{
932	if (pGDTE->Gen.u1Present)
933	selmGuestToShadowDesc(pVM, pGDTE);
934
935	/* Next GDT entry. */
936	pGDTE++;
937	}
938
939	/*
940	* Check if our hypervisor selectors were changed.
941	*/
942	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
943	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
944	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
945	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
946	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
947	{
948	/* Reinitialize our hypervisor GDTs */
949	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
950	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
951	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
952	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
953	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
954
955	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
956
957	/*
958	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
959	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
960	*/
961	VMR3Relocate(pVM, 0);
962	}
963	# ifdef VBOX_WITH_SAFE_STR
964	else if ( cbEffLimit >= SELM_HYPER_DEFAULT_BASE
965	\|\| CPUMGetGuestTR(pVCpu, NULL) != 0) /* Our shadow TR entry was overwritten when we synced the guest's GDT. */
966	# else
967	else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
968	# endif
969	/* We overwrote all entries above, so we have to save them again. */
970	selmR3SetupHyperGDTSelectors(pVM);
971
972	/*
973	* Adjust the cached GDT limit.
974	* Any GDT entries which have been removed must be cleared.
975	*/
976	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
977	{
978	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
979	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
980	}
981
982	/*
983	* Check if Guest's GDTR is changed.
984	*/
985	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
986	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
987	{
988	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
989
990	# ifdef SELM_TRACK_GUEST_GDT_CHANGES
991	/*
992	* [Re]Register write virtual handler for guest's GDT.
993	*/
994	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
995	{
996	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
997	AssertRC(rc);
998	}
999
1000	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1001	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1002	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1003	"Guest GDT write access handler");
1004	# ifdef VBOX_WITH_RAW_RING1
1005	/** @todo !HACK ALERT!
1006	* Some guest OSes (QNX) share code and the GDT on the same page;
1007	* PGMR3HandlerVirtualRegister doesn't support more than one handler,
1008	* so we kick out the PATM handler as this one is more important.
1009	* Fix this properly in PGMR3HandlerVirtualRegister?
1010	*/
1011	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1012	{
1013	LogRel(("selmR3UpdateShadowGdt: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority GDT page monitor\n", GDTR.pGdt));
1014	rc = PGMHandlerVirtualDeregister(pVM, GDTR.pGdt & PAGE_BASE_GC_MASK);
1015	AssertRC(rc);
1016
1017	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1018	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1019	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1020	"Guest GDT write access handler");
1021	}
1022	# endif
1023	if (RT_FAILURE(rc))
1024	return rc;
1025	# endif /* SELM_TRACK_GUEST_GDT_CHANGES */
1026
1027	/* Update saved Guest GDTR. */
1028	pVM->selm.s.GuestGdtr = GDTR;
1029	pVM->selm.s.fGDTRangeRegistered = true;
1030	}
1031
1032	return VINF_SUCCESS;
1033	}
1034
1035
1036	/**
1037	* Updates (syncs) the shadow LDT.
1038	*
1039	* @returns VBox status code.
1040	* @param pVM The VM handle.
1041	* @param pVCpu The current virtual CPU.
1042	*/
1043	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1044	{
1045	int rc = VINF_SUCCESS;
1046	Assert(!HMIsEnabled(pVM));
1047
1048	/*
1049	* Always assume the best...
1050	*/
1051	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1052
1053	/*
1054	* LDT handling is done similarly to the GDT handling with a shadow
1055	* array. However, since the LDT is expected to be swappable (at least
1056	* some ancient OSes makes it swappable) it must be floating and
1057	* synced on a per-page basis.
1058	*
1059	* Eventually we will change this to be fully on demand. Meaning that
1060	* we will only sync pages containing LDT selectors actually used and
1061	* let the #PF handler lazily sync pages as they are used.
1062	* (This applies to GDT too, when we start making OS/2 fast.)
1063	*/
1064
1065	/*
1066	* First, determine the current LDT selector.
1067	*/
1068	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1069	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1070	{
1071	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1072	CPUMSetHyperLDTR(pVCpu, 0);
1073	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1074	{
1075	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1076	AssertRC(rc);
1077	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1078	}
1079	pVM->selm.s.cbLdtLimit = 0;
1080	return VINF_SUCCESS;
1081	}
1082
1083	/*
1084	* Get the LDT selector.
1085	*/
1086	/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1087	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1088	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1089	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1090
1091	/*
1092	* Validate it.
1093	*/
1094	if ( !cbLdt
1095	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1096	\|\| pDesc->Gen.u1DescType
1097	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1098	{
1099	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1100
1101	/* cbLdt > 0:
1102	* This is quite impossible, so we do as most people do when faced with
1103	* the impossible, we simply ignore it.
1104	*/
1105	CPUMSetHyperLDTR(pVCpu, 0);
1106	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1107	{
1108	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1109	AssertRC(rc);
1110	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1111	}
1112	return VINF_SUCCESS;
1113	}
1114	/** @todo check what intel does about odd limits. */
1115	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1116
1117	/*
1118	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1119	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1120	*/
1121	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1122	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1123
1124
1125	/** @todo Handle only present LDT segments. */
1126	// if (pDesc->Gen.u1Present)
1127	{
1128	/*
1129	* Check if Guest's LDT address/limit is changed.
1130	*/
1131	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1132	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1133	{
1134	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1135	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1136
1137	# ifdef SELM_TRACK_GUEST_LDT_CHANGES
1138	/*
1139	* [Re]Register write virtual handler for guest's GDT.
1140	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1141	*/
1142	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1143	{
1144	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1145	AssertRC(rc);
1146	}
1147	# ifdef LOG_ENABLED
1148	if (pDesc->Gen.u1Present)
1149	Log(("LDT selector marked not present!!\n"));
1150	# endif
1151	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1152	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1153	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1154	{
1155	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1156	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1157	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1158	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1159	}
1160	else if (RT_SUCCESS(rc))
1161	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1162	else
1163	{
1164	CPUMSetHyperLDTR(pVCpu, 0);
1165	return rc;
1166	}
1167	# else
1168	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1169	# endif
1170	pVM->selm.s.cbLdtLimit = cbLdt;
1171	}
1172	}
1173
1174	/*
1175	* Calc Shadow LDT base.
1176	*/
1177	unsigned off;
1178	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1179	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1180	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1181
1182	/*
1183	* Enable the LDT selector in the shadow GDT.
1184	*/
1185	pDesc->Gen.u1Present = 1;
1186	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1187	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1188	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1189	pDesc->Gen.u1Available = 0;
1190	pDesc->Gen.u1Long = 0;
1191	if (cbLdt > 0xffff)
1192	{
1193	cbLdt = 0xffff;
1194	pDesc->Gen.u4LimitHigh = 0;
1195	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1196	}
1197
1198	/*
1199	* Set Hyper LDTR and notify TRPM.
1200	*/
1201	CPUMSetHyperLDTR(pVCpu, SelLdt);
1202
1203	/*
1204	* Loop synchronising the LDT page by page.
1205	*/
1206	/** @todo investigate how intel handle various operations on half present cross page entries. */
1207	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1208	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1209
1210	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1211	unsigned cbLeft = cbLdt + 1;
1212	PX86DESC pLDTE = pShadowLDT;
1213	while (cbLeft)
1214	{
1215	/*
1216	* Read a chunk.
1217	*/
1218	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1219	if (cbChunk > cbLeft)
1220	cbChunk = cbLeft;
1221	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1222	if (RT_SUCCESS(rc))
1223	{
1224	/*
1225	* Mark page
1226	*/
1227	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1228	AssertRC(rc);
1229
1230	/*
1231	* Loop thru the available LDT entries.
1232	* Figure out where to start and end and the potential cross pageness of
1233	* things adds a little complexity. pLDTE is updated there and not in the
1234	* 'next' part of the loop. The pLDTEEnd is inclusive.
1235	*/
1236	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1237	if (pLDTE + 1 < pShadowLDT)
1238	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1239	while (pLDTE <= pLDTEEnd)
1240	{
1241	if (pLDTE->Gen.u1Present)
1242	selmGuestToShadowDesc(pVM, pLDTE);
1243
1244	/* Next LDT entry. */
1245	pLDTE++;
1246	}
1247	}
1248	else
1249	{
1250	RT_BZERO(pShadowLDT, cbChunk);
1251	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1252	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1253	AssertRC(rc);
1254	}
1255
1256	/*
1257	* Advance to the next page.
1258	*/
1259	cbLeft -= cbChunk;
1260	GCPtrShadowLDT += cbChunk;
1261	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1262	GCPtrLdt += cbChunk;
1263	}
1264
1265	return VINF_SUCCESS;
1266	}
1267
1268
1269	/**
1270	* Checks and updates segment selector registers.
1271	*
1272	* @returns VBox strict status code.
1273	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1274	*
1275	* @param pVM The VM handle.
1276	* @param pVCpu The current virtual CPU.
1277	*/
1278	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1279	{
1280	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1281	Assert(!HMIsEnabled(pVM));
1282
1283	/*
1284	* No stale selectors in V8086 mode.
1285	*/
1286	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1287	if (pCtx->eflags.Bits.u1VM)
1288	return VINF_SUCCESS;
1289
1290	/*
1291	* Check for stale selectors and load hidden register bits where they
1292	* are missing.
1293	*/
1294	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1295	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1296	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1297	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1298	{
1299	RTSEL const Sel = paSReg[iSReg].Sel;
1300	if (Sel & X86_SEL_MASK_OFF_RPL)
1301	{
1302	/* Get the shadow descriptor entry corresponding to this. */
1303	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1304	PCX86DESC pDesc;
1305	if (!(Sel & X86_SEL_LDT))
1306	{
1307	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1308	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1309	else
1310	pDesc = &s_NotPresentDesc;
1311	}
1312	else
1313	{
1314	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1315	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1316	else
1317	pDesc = &s_NotPresentDesc;
1318	}
1319
1320	/* Check the segment register. */
1321	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1322	{
1323	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1324	{
1325	/* Did it go stale? */
1326	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1327	{
1328	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1329	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1330	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1331	rcStrict = VINF_EM_RESCHEDULE_REM;
1332	}
1333	}
1334	else
1335	{
1336	/* Did it stop being stale? I.e. did the guest change it things
1337	back to the way they were? */
1338	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1339	{
1340	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1341	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1342	}
1343	else
1344	{
1345	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1346	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1347	rcStrict = VINF_EM_RESCHEDULE_REM;
1348	}
1349	}
1350	}
1351	/* Load the hidden registers if it's a valid descriptor for the
1352	current segment register. */
1353	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1354	{
1355	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1356	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1357	}
1358	/* It's stale. */
1359	else
1360	{
1361	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1362	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1363	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1364	rcStrict = VINF_EM_RESCHEDULE_REM;
1365	}
1366	}
1367	/* else: 0 selector, ignore. */
1368	}
1369
1370	return rcStrict;
1371	}
1372
1373
1374	/**
1375	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1376	*
1377	* @returns VBox status code.
1378	* @param pVM Pointer to the VM.
1379	* @param pVCpu Pointer to the VMCPU.
1380	*/
1381	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1382	{
1383	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1384	AssertReturn(!HMIsEnabled(pVM), VERR_SELM_HM_IPE);
1385
1386	/*
1387	* GDT sync
1388	*/
1389	int rc;
1390	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1391	{
1392	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1393	if (RT_FAILURE(rc))
1394	return rc; /* We're toast, so forget the profiling. */
1395	AssertRCSuccess(rc);
1396	}
1397
1398	/*
1399	* TSS sync
1400	*/
1401	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1402	{
1403	rc = SELMR3SyncTSS(pVM, pVCpu);
1404	if (RT_FAILURE(rc))
1405	return rc;
1406	AssertRCSuccess(rc);
1407	}
1408
1409	/*
1410	* LDT sync
1411	*/
1412	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1413	{
1414	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1415	if (RT_FAILURE(rc))
1416	return rc;
1417	AssertRCSuccess(rc);
1418	}
1419
1420	/*
1421	* Check selector registers.
1422	*/
1423	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1424
1425	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1426	return rcStrict;
1427	}
1428
1429	#endif /VBOX_WITH_RAW_MODE/
1430
1431	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1432	/**
1433	* \#PF Handler callback for virtual access handler ranges.
1434	*
1435	* Important to realize that a physical page in a range can have aliases, and
1436	* for ALL and WRITE handlers these will also trigger.
1437	*
1438	* @returns VINF_SUCCESS if the handler have carried out the operation.
1439	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1440	* @param pVM Pointer to the VM.
1441	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1442	* @param pvPtr The HC mapping of that address.
1443	* @param pvBuf What the guest is reading/writing.
1444	* @param cbBuf How much it's reading/writing.
1445	* @param enmAccessType The access type.
1446	* @param pvUser User argument.
1447	*/
1448	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1449	PGMACCESSTYPE enmAccessType, void *pvUser)
1450	{
1451	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1452	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1453	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1454
1455	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1456	return VINF_PGM_HANDLER_DO_DEFAULT;
1457	}
1458	#endif
1459
1460	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1461	/**
1462	* \#PF Handler callback for virtual access handler ranges.
1463	*
1464	* Important to realize that a physical page in a range can have aliases, and
1465	* for ALL and WRITE handlers these will also trigger.
1466	*
1467	* @returns VINF_SUCCESS if the handler have carried out the operation.
1468	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1469	* @param pVM Pointer to the VM.
1470	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1471	* @param pvPtr The HC mapping of that address.
1472	* @param pvBuf What the guest is reading/writing.
1473	* @param cbBuf How much it's reading/writing.
1474	* @param enmAccessType The access type.
1475	* @param pvUser User argument.
1476	*/
1477	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1478	PGMACCESSTYPE enmAccessType, void *pvUser)
1479	{
1480	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1481	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1482	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1483
1484	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1485	return VINF_PGM_HANDLER_DO_DEFAULT;
1486	}
1487	#endif
1488
1489
1490	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1491	/**
1492	* \#PF Handler callback for virtual access handler ranges.
1493	*
1494	* Important to realize that a physical page in a range can have aliases, and
1495	* for ALL and WRITE handlers these will also trigger.
1496	*
1497	* @returns VINF_SUCCESS if the handler have carried out the operation.
1498	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1499	* @param pVM Pointer to the VM.
1500	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1501	* @param pvPtr The HC mapping of that address.
1502	* @param pvBuf What the guest is reading/writing.
1503	* @param cbBuf How much it's reading/writing.
1504	* @param enmAccessType The access type.
1505	* @param pvUser User argument.
1506	*/
1507	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1508	PGMACCESSTYPE enmAccessType, void *pvUser)
1509	{
1510	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1511	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1512	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1513
1514	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1515	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1516	* should probably also deregister the virtual handler if TR.base/size
1517	* changes while we're in REM. */
1518
1519	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1520	return VINF_PGM_HANDLER_DO_DEFAULT;
1521	}
1522	#endif
1523
1524	#ifdef VBOX_WITH_RAW_MODE
1525
1526	/**
1527	* Synchronize the shadowed fields in the TSS.
1528	*
1529	* At present we're shadowing the ring-0 stack selector & pointer, and the
1530	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1531	* REM and this function is called both if REM made any changes to the TSS or
1532	* loaded TR.
1533	*
1534	* @returns VBox status code.
1535	* @param pVM Pointer to the VM.
1536	* @param pVCpu Pointer to the VMCPU.
1537	*/
1538	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1539	{
1540	int rc;
1541	AssertReturnStmt(!HMIsEnabled(pVM), VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS), VINF_SUCCESS);
1542
1543	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1544	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1545
1546	/*
1547	* Get TR and extract and store the basic info.
1548	*
1549	* Note! The TSS limit is not checked by the LTR code, so we
1550	* have to be a bit careful with it. We make sure cbTss
1551	* won't be zero if TR is valid and if it's NULL we'll
1552	* make sure cbTss is 0.
1553	*/
1554	/** @todo use the hidden bits, not shadow GDT. */
1555	CPUMSELREGHID trHid;
1556	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1557	RTGCPTR GCPtrTss = trHid.u64Base;
1558	uint32_t cbTss = trHid.u32Limit;
1559	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1560	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1561	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1562	if (SelTss & X86_SEL_MASK_OFF_RPL)
1563	{
1564	Assert(!(SelTss & X86_SEL_LDT));
1565	Assert(trHid.Attr.n.u1DescType == 0);
1566	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1567	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1568	if (!++cbTss)
1569	cbTss = UINT32_MAX;
1570	}
1571	else
1572	{
1573	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1574	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1575	cbTss = 0; /* the reset case. */
1576	}
1577	pVM->selm.s.cbGuestTss = cbTss;
1578	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1579	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1580
1581	/*
1582	* Figure out the size of what need to monitor.
1583	*/
1584	/* We're not interested in any 16-bit TSSes. */
1585	uint32_t cbMonitoredTss = cbTss;
1586	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1587	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1588	cbMonitoredTss = 0;
1589
1590	pVM->selm.s.offGuestIoBitmap = 0;
1591	bool fNoRing1Stack = true;
1592	if (cbMonitoredTss)
1593	{
1594	/*
1595	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1596	* If VME is enabled we also want to keep an eye on the interrupt
1597	* redirection bitmap.
1598	*/
1599	VBOXTSS Tss;
1600	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1601	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1602	if ( !(cr4 & X86_CR4_VME)
1603	\|\| ( RT_SUCCESS(rc)
1604	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1605	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1606	)
1607	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1608	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1609	else if (RT_SUCCESS(rc))
1610	{
1611	/*
1612	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1613	* this can be quite a large chunk. We use to skip it earlier and just hope it
1614	* was kind of static...
1615	*
1616	* Update the virtual interrupt redirection bitmap while we're here.
1617	* (It is located in the 32 bytes before TR:offIoBitmap.)
1618	*/
1619	cbMonitoredTss = Tss.offIoBitmap;
1620	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1621
1622	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1623	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1624	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1625	AssertRC(rc);
1626	/** @todo memset the bitmap on failure? */
1627	Log2(("Redirection bitmap:\n"));
1628	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1629	}
1630	else
1631	{
1632	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1633	pVM->selm.s.offGuestIoBitmap = 0;
1634	/** @todo memset the bitmap? */
1635	}
1636
1637	/*
1638	* Update the ring 0 stack selector and base address.
1639	*/
1640	if (RT_SUCCESS(rc))
1641	{
1642	# ifdef LOG_ENABLED
1643	if (LogIsEnabled())
1644	{
1645	uint32_t ssr0, espr0;
1646	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1647	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1648	{
1649	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1650	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1651	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1652	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1653	AssertMsg(ssr0 != Tss.ss0,
1654	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1655	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1656	}
1657	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1658	}
1659	# endif /* LOG_ENABLED */
1660	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1661
1662	/* Update our TSS structure for the guest's ring 1 stack */
1663	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1664	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1665
1666	# ifdef VBOX_WITH_RAW_RING1
1667	/* Update our TSS structure for the guest's ring 2 stack */
1668	if (EMIsRawRing1Enabled(pVM))
1669	{
1670	if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) \| 1))
1671	\|\| pVM->selm.s.Tss.esp2 != Tss.esp1)
1672	Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) \| 1, pVM->selm.s.Tss.esp2));
1673	selmSetRing2Stack(pVM, (Tss.ss1 & ~1) \| 2, Tss.esp1);
1674	}
1675	# endif
1676	}
1677	}
1678
1679	/*
1680	* Flush the ring-1 stack and the direct syscall dispatching if we
1681	* cannot obtain SS0:ESP0.
1682	*/
1683	if (fNoRing1Stack)
1684	{
1685	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1686	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1687
1688	/** @todo handle these dependencies better! */
1689	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1690	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1691	}
1692
1693	/*
1694	* Check for monitor changes and apply them.
1695	*/
1696	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1697	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1698	{
1699	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1700	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1701
1702	/* Release the old range first. */
1703	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1704	{
1705	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1706	AssertRC(rc);
1707	}
1708
1709	/* Register the write handler if TS != 0. */
1710	if (cbMonitoredTss != 0)
1711	{
1712	# ifdef SELM_TRACK_GUEST_TSS_CHANGES
1713	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1714	0, selmR3GuestTSSWriteHandler,
1715	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1716	if (RT_FAILURE(rc))
1717	{
1718	# ifdef VBOX_WITH_RAW_RING1
1719	/** @todo !HACK ALERT!
1720	* Some guest OSes (QNX) share code and the TSS on the same page;
1721	* PGMR3HandlerVirtualRegister doesn't support more than one
1722	* handler, so we kick out the PATM handler as this one is more
1723	* important. Fix this properly in PGMR3HandlerVirtualRegister?
1724	*/
1725	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1726	{
1727	LogRel(("SELMR3SyncTSS: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority TSS page monitor\n", GCPtrTss));
1728	rc = PGMHandlerVirtualDeregister(pVM, GCPtrTss & PAGE_BASE_GC_MASK);
1729	AssertRC(rc);
1730
1731	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1732	0, selmR3GuestTSSWriteHandler,
1733	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1734	if (RT_FAILURE(rc))
1735	{
1736	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1737	return rc;
1738	}
1739	}
1740	# else
1741	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1742	return rc;
1743	# endif
1744	}
1745	# endif /* SELM_TRACK_GUEST_TSS_CHANGES */
1746
1747	/* Update saved Guest TSS info. */
1748	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1749	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1750	pVM->selm.s.GCSelTss = SelTss;
1751	}
1752	else
1753	{
1754	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1755	pVM->selm.s.cbMonitoredGuestTss = 0;
1756	pVM->selm.s.GCSelTss = 0;
1757	}
1758	}
1759
1760	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1761
1762	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1763	return VINF_SUCCESS;
1764	}
1765
1766
1767	/**
1768	* Compares the Guest GDT and LDT with the shadow tables.
1769	* This is a VBOX_STRICT only function.
1770	*
1771	* @returns VBox status code.
1772	* @param pVM Pointer to the VM.
1773	*/
1774	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1775	{
1776	#ifdef VBOX_STRICT
1777	PVMCPU pVCpu = VMMGetCpu(pVM);
1778	AssertReturn(!HMIsEnabled(pVM), VERR_SELM_HM_IPE);
1779
1780	/*
1781	* Get GDTR and check for conflict.
1782	*/
1783	VBOXGDTR GDTR;
1784	CPUMGetGuestGDTR(pVCpu, &GDTR);
1785	if (GDTR.cbGdt == 0)
1786	return VINF_SUCCESS;
1787
1788	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1789	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1790
1791	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1792	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1793
1794	/*
1795	* Loop thru the GDT checking each entry.
1796	*/
1797	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1798	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1799	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1800	while (pGDTE < pGDTEEnd)
1801	{
1802	X86DESC GDTEGuest;
1803	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1804	if (RT_SUCCESS(rc))
1805	{
1806	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1807	{
1808	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1809	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1810	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1811	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1812	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1813	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1814	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1815	{
1816	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1817	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1818	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1819	}
1820	}
1821	}
1822
1823	/* Advance to the next descriptor. */
1824	GCPtrGDTEGuest += sizeof(X86DESC);
1825	pGDTE++;
1826	}
1827
1828
1829	/*
1830	* LDT?
1831	*/
1832	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1833	if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1834	return VINF_SUCCESS;
1835	Assert(!(SelLdt & X86_SEL_LDT));
1836	if (SelLdt > GDTR.cbGdt)
1837	{
1838	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1839	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1840	}
1841	X86DESC LDTDesc;
1842	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1843	if (RT_FAILURE(rc))
1844	{
1845	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1846	return rc;
1847	}
1848	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1849	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1850
1851	/*
1852	* Validate it.
1853	*/
1854	if (!cbLdt)
1855	return VINF_SUCCESS;
1856	/** @todo check what intel does about odd limits. */
1857	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1858	if ( LDTDesc.Gen.u1DescType
1859	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1860	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1861	{
1862	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1863	return VERR_SELM_INVALID_LDT;
1864	}
1865
1866	/*
1867	* Loop thru the LDT checking each entry.
1868	*/
1869	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1870	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1871	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1872	while (pLDTE < pLDTEEnd)
1873	{
1874	X86DESC LDTEGuest;
1875	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1876	if (RT_SUCCESS(rc))
1877	{
1878	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1879	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1880	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1881	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1882	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1883	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1884	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1885	{
1886	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1887	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1888	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1889	}
1890	}
1891
1892	/* Advance to the next descriptor. */
1893	GCPtrLDTEGuest += sizeof(X86DESC);
1894	pLDTE++;
1895	}
1896
1897	#else /* !VBOX_STRICT */
1898	NOREF(pVM);
1899	#endif /* !VBOX_STRICT */
1900
1901	return VINF_SUCCESS;
1902	}
1903
1904
1905	/**
1906	* Validates the RawR0 TSS values against the one in the Guest TSS.
1907	*
1908	* @returns true if it matches.
1909	* @returns false and assertions on mismatch..
1910	* @param pVM Pointer to the VM.
1911	*/
1912	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1913	{
1914	#if defined(VBOX_STRICT) && defined(SELM_TRACK_GUEST_TSS_CHANGES)
1915	PVMCPU pVCpu = VMMGetCpu(pVM);
1916
1917	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1918	return true;
1919
1920	/*
1921	* Get TR and extract the basic info.
1922	*/
1923	CPUMSELREGHID trHid;
1924	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1925	RTGCPTR GCPtrTss = trHid.u64Base;
1926	uint32_t cbTss = trHid.u32Limit;
1927	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1928	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1929	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1930	if (SelTss & X86_SEL_MASK_OFF_RPL)
1931	{
1932	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1933	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1934	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1935	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1936	false);
1937	if (!++cbTss)
1938	cbTss = UINT32_MAX;
1939	}
1940	else
1941	{
1942	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1943	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1944	false);
1945	cbTss = 0; /* the reset case. */
1946	}
1947	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1948	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1949	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1950	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1951	false);
1952	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1953	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1954	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1955	false);
1956	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1957	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1958	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1959	false);
1960
1961
1962	/*
1963	* Figure out the size of what need to monitor.
1964	*/
1965	/* We're not interested in any 16-bit TSSes. */
1966	uint32_t cbMonitoredTss = cbTss;
1967	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1968	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1969	cbMonitoredTss = 0;
1970	if (cbMonitoredTss)
1971	{
1972	VBOXTSS Tss;
1973	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1974	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1975	AssertReturn( rc == VINF_SUCCESS
1976	/* Happens early in XP boot during page table switching. */
1977	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
1978	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1979	false);
1980	if ( !(cr4 & X86_CR4_VME)
1981	\|\| ( RT_SUCCESS(rc)
1982	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1983	&& Tss.offIoBitmap > cbTss)
1984	)
1985	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1986	else if (RT_SUCCESS(rc))
1987	{
1988	cbMonitoredTss = Tss.offIoBitmap;
1989	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1990	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1991	false);
1992
1993	/* check the bitmap */
1994	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1995	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1996	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1997	AssertRCReturn(rc, false);
1998	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1999	("offIoBitmap=%#x cbTss=%#x\n"
2000	" Guest: %.32Rhxs\n"
2001	"Shadow: %.32Rhxs\n",
2002	Tss.offIoBitmap, cbTss,
2003	&Tss.IntRedirBitmap[0],
2004	&pVM->selm.s.Tss.IntRedirBitmap[0]),
2005	false);
2006	}
2007	else
2008	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
2009
2010	/*
2011	* Check SS0 and ESP0.
2012	*/
2013	if ( !pVM->selm.s.fSyncTSSRing0Stack
2014	&& RT_SUCCESS(rc))
2015	{
2016	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
2017	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
2018	{
2019	RTGCPHYS GCPhys;
2020	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
2021	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
2022	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
2023	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
2024	return false;
2025	}
2026	}
2027	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2028	}
2029	else
2030	{
2031	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
2032	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
2033	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2034	}
2035
2036
2037
2038	return true;
2039
2040	#else /* !VBOX_STRICT */
2041	NOREF(pVM);
2042	return true;
2043	#endif /* !VBOX_STRICT */
2044	}
2045
2046
2047	# ifdef VBOX_WITH_SAFE_STR
2048	/**
2049	* Validates the RawR0 TR shadow GDT entry.
2050	*
2051	* @returns true if it matches.
2052	* @returns false and assertions on mismatch..
2053	* @param pVM Pointer to the VM.
2054	*/
2055	VMMR3DECL(bool) SELMR3CheckShadowTR(PVM pVM)
2056	{
2057	# ifdef VBOX_STRICT
2058	PX86DESC paGdt = pVM->selm.s.paGdtR3;
2059
2060	/*
2061	* TSS descriptor
2062	*/
2063	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
2064	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
2065
2066	if ( pDesc->Gen.u16BaseLow != RT_LOWORD(RCPtrTSS)
2067	\|\| pDesc->Gen.u8BaseHigh1 != RT_BYTE3(RCPtrTSS)
2068	\|\| pDesc->Gen.u8BaseHigh2 != RT_BYTE4(RCPtrTSS)
2069	\|\| pDesc->Gen.u16LimitLow != sizeof(VBOXTSS) - 1
2070	\|\| pDesc->Gen.u4LimitHigh != 0
2071	\|\| (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL && pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2072	\|\| pDesc->Gen.u1DescType != 0 /* system */
2073	\|\| pDesc->Gen.u2Dpl != 0 /* supervisor */
2074	\|\| pDesc->Gen.u1Present != 1
2075	\|\| pDesc->Gen.u1Available != 0
2076	\|\| pDesc->Gen.u1Long != 0
2077	\|\| pDesc->Gen.u1DefBig != 0
2078	\|\| pDesc->Gen.u1Granularity != 0 /* byte limit */
2079	)
2080	{
2081	AssertFailed();
2082	return false;
2083	}
2084	# endif
2085	return true;
2086	}
2087	# endif /* VBOX_WITH_SAFE_STR */
2088
2089	#endif /* VBOX_WITH_RAW_MODE */
2090
2091	/**
2092	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2093	*
2094	* See SELMR3GetSelectorInfo for details.
2095	*
2096	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2097	*
2098	* @param pVCpu Pointer to the VMCPU.
2099	* @param Sel The selector to get info about.
2100	* @param pSelInfo Where to store the information.
2101	*/
2102	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2103	{
2104	/*
2105	* Read it from the guest descriptor table.
2106	*/
2107	/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2108	X86DESC64 Desc;
2109	RTGCPTR GCPtrDesc;
2110	if (!(Sel & X86_SEL_LDT))
2111	{
2112	/* GDT */
2113	VBOXGDTR Gdtr;
2114	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2115	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2116	return VERR_INVALID_SELECTOR;
2117	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2118	}
2119	else
2120	{
2121	/* LDT */
2122	uint64_t GCPtrBase;
2123	uint32_t cbLimit;
2124	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2125	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2126	return VERR_INVALID_SELECTOR;
2127
2128	/* calc the descriptor location. */
2129	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2130	}
2131
2132	/* read the descriptor. */
2133	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2134	if (RT_FAILURE(rc))
2135	{
2136	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2137	if (RT_FAILURE(rc))
2138	return rc;
2139	Desc.au64[1] = 0;
2140	}
2141
2142	/*
2143	* Extract the base and limit
2144	* (We ignore the present bit here, which is probably a bit silly...)
2145	*/
2146	pSelInfo->Sel = Sel;
2147	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2148	pSelInfo->u.Raw64 = Desc;
2149	if (Desc.Gen.u1DescType)
2150	{
2151	/*
2152	* 64-bit code selectors are wide open, it's not possible to detect
2153	* 64-bit data or stack selectors without also dragging in assumptions
2154	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2155	* the selinfo user needs to deal with this in the context the info is
2156	* used unfortunately.
2157	*/
2158	if ( Desc.Gen.u1Long
2159	&& !Desc.Gen.u1DefBig
2160	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2161	{
2162	/* Note! We ignore the segment limit hacks that was added by AMD. */
2163	pSelInfo->GCPtrBase = 0;
2164	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2165	}
2166	else
2167	{
2168	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2169	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2170	}
2171	pSelInfo->SelGate = 0;
2172	}
2173	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2174	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2175	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2176	{
2177	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2178	in the AMD manual here as a simplification. */
2179	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2180	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2181	pSelInfo->SelGate = 0;
2182	}
2183	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2184	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2185	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2186	{
2187	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2188	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2189	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2190	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2191	pSelInfo->SelGate = Desc.Gate.u16Sel;
2192	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2193	}
2194	else
2195	{
2196	pSelInfo->cbLimit = 0;
2197	pSelInfo->GCPtrBase = 0;
2198	pSelInfo->SelGate = 0;
2199	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2200	}
2201	if (!Desc.Gen.u1Present)
2202	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2203
2204	return VINF_SUCCESS;
2205	}
2206
2207
2208	/**
2209	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2210	* interprets a legacy descriptor table entry and fills in the selector info
2211	* structure from it.
2212	*
2213	* @param pSelInfo Where to store the selector info. Only the fFlags and
2214	* Sel members have been initialized.
2215	* @param pDesc The legacy descriptor to parse.
2216	*/
2217	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2218	{
2219	pSelInfo->u.Raw64.au64[1] = 0;
2220	pSelInfo->u.Raw = *pDesc;
2221	if ( pDesc->Gen.u1DescType
2222	\|\| !(pDesc->Gen.u4Type & 4))
2223	{
2224	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2225	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2226	pSelInfo->SelGate = 0;
2227	}
2228	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2229	{
2230	pSelInfo->cbLimit = 0;
2231	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2232	pSelInfo->GCPtrBase = 0;
2233	else
2234	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2235	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2236	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2237	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2238	}
2239	else
2240	{
2241	pSelInfo->cbLimit = 0;
2242	pSelInfo->GCPtrBase = 0;
2243	pSelInfo->SelGate = 0;
2244	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2245	}
2246	if (!pDesc->Gen.u1Present)
2247	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2248	}
2249
2250
2251	/**
2252	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2253	*
2254	* See SELMR3GetSelectorInfo for details.
2255	*
2256	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2257	*
2258	* @param pVM Pointer to the VM.
2259	* @param pVCpu Pointer to the VMCPU.
2260	* @param Sel The selector to get info about.
2261	* @param pSelInfo Where to store the information.
2262	*/
2263	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2264	{
2265	/*
2266	* Read the descriptor entry
2267	*/
2268	pSelInfo->fFlags = 0;
2269	X86DESC Desc;
2270	if ( !(Sel & X86_SEL_LDT)
2271	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2272	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2273	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2274	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2275	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2276	)
2277	{
2278	/*
2279	* Hypervisor descriptor.
2280	*/
2281	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2282	if (CPUMIsGuestInProtectedMode(pVCpu))
2283	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2284	else
2285	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2286
2287	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2288	}
2289	else if (CPUMIsGuestInProtectedMode(pVCpu))
2290	{
2291	/*
2292	* Read it from the guest descriptor table.
2293	*/
2294	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2295
2296	RTGCPTR GCPtrDesc;
2297	if (!(Sel & X86_SEL_LDT))
2298	{
2299	/* GDT */
2300	VBOXGDTR Gdtr;
2301	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2302	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2303	return VERR_INVALID_SELECTOR;
2304	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2305	}
2306	else
2307	{
2308	/* LDT */
2309	uint64_t GCPtrBase;
2310	uint32_t cbLimit;
2311	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2312	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2313	return VERR_INVALID_SELECTOR;
2314
2315	/* calc the descriptor location. */
2316	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2317	}
2318
2319	/* read the descriptor. */
2320	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2321	if (RT_FAILURE(rc))
2322	return rc;
2323	}
2324	else
2325	{
2326	/*
2327	* We're in real mode.
2328	*/
2329	pSelInfo->Sel = Sel;
2330	pSelInfo->GCPtrBase = Sel << 4;
2331	pSelInfo->cbLimit = 0xffff;
2332	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2333	pSelInfo->u.Raw64.au64[0] = 0;
2334	pSelInfo->u.Raw64.au64[1] = 0;
2335	pSelInfo->SelGate = 0;
2336	return VINF_SUCCESS;
2337	}
2338
2339	/*
2340	* Extract the base and limit or sel:offset for gates.
2341	*/
2342	pSelInfo->Sel = Sel;
2343	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2344
2345	return VINF_SUCCESS;
2346	}
2347
2348
2349	/**
2350	* Gets information about a selector.
2351	*
2352	* Intended for the debugger mostly and will prefer the guest descriptor tables
2353	* over the shadow ones.
2354	*
2355	* @retval VINF_SUCCESS on success.
2356	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2357	* descriptor table.
2358	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2359	* is not returned if the selector itself isn't present, you have to
2360	* check that for yourself (see DBGFSELINFO::fFlags).
2361	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2362	* pagetable or page backing the selector table wasn't present.
2363	* @returns Other VBox status code on other errors.
2364	*
2365	* @param pVM Pointer to the VM.
2366	* @param pVCpu Pointer to the VMCPU.
2367	* @param Sel The selector to get info about.
2368	* @param pSelInfo Where to store the information.
2369	*/
2370	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2371	{
2372	AssertPtr(pSelInfo);
2373	if (CPUMIsGuestInLongMode(pVCpu))
2374	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2375	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2376	}
2377
2378
2379	/**
2380	* Gets information about a selector from the shadow tables.
2381	*
2382	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2383	* requires that the caller ensures that the shadow tables are up to date.
2384	*
2385	* @retval VINF_SUCCESS on success.
2386	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2387	* descriptor table.
2388	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2389	* is not returned if the selector itself isn't present, you have to
2390	* check that for yourself (see DBGFSELINFO::fFlags).
2391	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2392	* pagetable or page backing the selector table wasn't present.
2393	* @returns Other VBox status code on other errors.
2394	*
2395	* @param pVM Pointer to the VM.
2396	* @param Sel The selector to get info about.
2397	* @param pSelInfo Where to store the information.
2398	*
2399	* @remarks Don't use this when in hardware assisted virtualization mode.
2400	*/
2401	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2402	{
2403	Assert(pSelInfo);
2404
2405	/*
2406	* Read the descriptor entry
2407	*/
2408	X86DESC Desc;
2409	if (!(Sel & X86_SEL_LDT))
2410	{
2411	/*
2412	* Global descriptor.
2413	*/
2414	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2415	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2416	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2417	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2418	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2419	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2420	? DBGFSELINFO_FLAGS_HYPER
2421	: 0;
2422	/** @todo check that the GDT offset is valid. */
2423	}
2424	else
2425	{
2426	/*
2427	* Local Descriptor.
2428	*/
2429	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2430	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2431	/** @todo check if the LDT page is actually available. */
2432	/** @todo check that the LDT offset is valid. */
2433	pSelInfo->fFlags = 0;
2434	}
2435	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2436	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2437	else
2438	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2439
2440	/*
2441	* Extract the base and limit or sel:offset for gates.
2442	*/
2443	pSelInfo->Sel = Sel;
2444	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2445
2446	return VINF_SUCCESS;
2447	}
2448
2449
2450	/**
2451	* Formats a descriptor.
2452	*
2453	* @param Desc Descriptor to format.
2454	* @param Sel Selector number.
2455	* @param pszOutput Output buffer.
2456	* @param cchOutput Size of output buffer.
2457	*/
2458	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2459	{
2460	/*
2461	* Make variable description string.
2462	*/
2463	static struct
2464	{
2465	unsigned cch;
2466	const char *psz;
2467	} const aTypes[32] =
2468	{
2469	#define STRENTRY(str) { sizeof(str) - 1, str }
2470	/* system */
2471	STRENTRY("Reserved0 "), /* 0x00 */
2472	STRENTRY("TSS16Avail "), /* 0x01 */
2473	STRENTRY("LDT "), /* 0x02 */
2474	STRENTRY("TSS16Busy "), /* 0x03 */
2475	STRENTRY("Call16 "), /* 0x04 */
2476	STRENTRY("Task "), /* 0x05 */
2477	STRENTRY("Int16 "), /* 0x06 */
2478	STRENTRY("Trap16 "), /* 0x07 */
2479	STRENTRY("Reserved8 "), /* 0x08 */
2480	STRENTRY("TSS32Avail "), /* 0x09 */
2481	STRENTRY("ReservedA "), /* 0x0a */
2482	STRENTRY("TSS32Busy "), /* 0x0b */
2483	STRENTRY("Call32 "), /* 0x0c */
2484	STRENTRY("ReservedD "), /* 0x0d */
2485	STRENTRY("Int32 "), /* 0x0e */
2486	STRENTRY("Trap32 "), /* 0x0f */
2487	/* non system */
2488	STRENTRY("DataRO "), /* 0x10 */
2489	STRENTRY("DataRO Accessed "), /* 0x11 */
2490	STRENTRY("DataRW "), /* 0x12 */
2491	STRENTRY("DataRW Accessed "), /* 0x13 */
2492	STRENTRY("DataDownRO "), /* 0x14 */
2493	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2494	STRENTRY("DataDownRW "), /* 0x16 */
2495	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2496	STRENTRY("CodeEO "), /* 0x18 */
2497	STRENTRY("CodeEO Accessed "), /* 0x19 */
2498	STRENTRY("CodeER "), /* 0x1a */
2499	STRENTRY("CodeER Accessed "), /* 0x1b */
2500	STRENTRY("CodeConfEO "), /* 0x1c */
2501	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2502	STRENTRY("CodeConfER "), /* 0x1e */
2503	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2504	#undef SYSENTRY
2505	};
2506	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2507	char szMsg[128];
2508	char *psz = &szMsg[0];
2509	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2510	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2511	psz += aTypes[i].cch;
2512
2513	if (Desc.Gen.u1Present)
2514	ADD_STR(psz, "Present ");
2515	else
2516	ADD_STR(psz, "Not-Present ");
2517	if (Desc.Gen.u1Granularity)
2518	ADD_STR(psz, "Page ");
2519	if (Desc.Gen.u1DefBig)
2520	ADD_STR(psz, "32-bit ");
2521	else
2522	ADD_STR(psz, "16-bit ");
2523	#undef ADD_STR
2524	*psz = '\0';
2525
2526	/*
2527	* Limit and Base and format the output.
2528	*/
2529	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2530	uint32_t u32Base = X86DESC_BASE(&Desc);
2531
2532	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2533	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2534	}
2535
2536
2537	/**
2538	* Dumps a descriptor.
2539	*
2540	* @param Desc Descriptor to dump.
2541	* @param Sel Selector number.
2542	* @param pszMsg Message to prepend the log entry with.
2543	*/
2544	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2545	{
2546	char szOutput[128];
2547	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2548	Log(("%s: %s\n", pszMsg, szOutput));
2549	NOREF(szOutput[0]);
2550	}
2551
2552
2553	/**
2554	* Display the shadow gdt.
2555	*
2556	* @param pVM Pointer to the VM.
2557	* @param pHlp The info helpers.
2558	* @param pszArgs Arguments, ignored.
2559	*/
2560	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2561	{
2562	NOREF(pszArgs);
2563	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2564	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2565	{
2566	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2567	{
2568	char szOutput[128];
2569	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2570	const char *psz = "";
2571	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2572	psz = " HyperCS";
2573	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2574	psz = " HyperDS";
2575	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2576	psz = " HyperCS64";
2577	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2578	psz = " HyperTSS";
2579	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2580	psz = " HyperTSSTrap08";
2581	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2582	}
2583	}
2584	}
2585
2586
2587	/**
2588	* Display the guest gdt.
2589	*
2590	* @param pVM Pointer to the VM.
2591	* @param pHlp The info helpers.
2592	* @param pszArgs Arguments, ignored.
2593	*/
2594	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2595	{
2596	/** @todo SMP support! */
2597	PVMCPU pVCpu = &pVM->aCpus[0];
2598
2599	VBOXGDTR GDTR;
2600	CPUMGetGuestGDTR(pVCpu, &GDTR);
2601	RTGCPTR GCPtrGDT = GDTR.pGdt;
2602	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2603
2604	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2605	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2606	{
2607	X86DESC GDTE;
2608	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2609	if (RT_SUCCESS(rc))
2610	{
2611	if (GDTE.Gen.u1Present)
2612	{
2613	char szOutput[128];
2614	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2615	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2616	}
2617	}
2618	else if (rc == VERR_PAGE_NOT_PRESENT)
2619	{
2620	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2621	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2622	}
2623	else
2624	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2625	}
2626	NOREF(pszArgs);
2627	}
2628
2629
2630	/**
2631	* Display the shadow ldt.
2632	*
2633	* @param pVM Pointer to the VM.
2634	* @param pHlp The info helpers.
2635	* @param pszArgs Arguments, ignored.
2636	*/
2637	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2638	{
2639	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2640	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2641	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2642	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2643	{
2644	if (paLDT[iLDT].Gen.u1Present)
2645	{
2646	char szOutput[128];
2647	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2648	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2649	}
2650	}
2651	NOREF(pszArgs);
2652	}
2653
2654
2655	/**
2656	* Display the guest ldt.
2657	*
2658	* @param pVM Pointer to the VM.
2659	* @param pHlp The info helpers.
2660	* @param pszArgs Arguments, ignored.
2661	*/
2662	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2663	{
2664	/** @todo SMP support! */
2665	PVMCPU pVCpu = &pVM->aCpus[0];
2666
2667	uint64_t GCPtrLdt;
2668	uint32_t cbLdt;
2669	RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2670	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2671	{
2672	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2673	return;
2674	}
2675
2676	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2677	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2678	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2679	{
2680	X86DESC LdtE;
2681	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2682	if (RT_SUCCESS(rc))
2683	{
2684	if (LdtE.Gen.u1Present)
2685	{
2686	char szOutput[128];
2687	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2688	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2689	}
2690	}
2691	else if (rc == VERR_PAGE_NOT_PRESENT)
2692	{
2693	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2694	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2695	}
2696	else
2697	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2698	}
2699	NOREF(pszArgs);
2700	}
2701
2702
2703	/**
2704	* Dumps the hypervisor GDT
2705	*
2706	* @param pVM Pointer to the VM.
2707	*/
2708	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2709	{
2710	DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2711	}
2712
2713
2714	/**
2715	* Dumps the hypervisor LDT
2716	*
2717	* @param pVM Pointer to the VM.
2718	*/
2719	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2720	{
2721	DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2722	}
2723
2724
2725	/**
2726	* Dumps the guest GDT
2727	*
2728	* @param pVM Pointer to the VM.
2729	*/
2730	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2731	{
2732	DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2733	}
2734
2735
2736	/**
2737	* Dumps the guest LDT
2738	*
2739	* @param pVM Pointer to the VM.
2740	*/
2741	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2742	{
2743	DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2744	}
2745

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 45728

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