SELM.cpp@ 55966

Last change on this file since 55966 was 55900, checked in by vboxsync, 10 years ago
PGM: Added a pVCpu parameter to all virtual handler callouts and also a PGMACCESSORIGIN parameter to the ring-3 one.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 110.7 KB

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1	/* $Id: SELM.cpp 55900 2015-05-18 10:17:35Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/em.h>
66	#include <VBox/vmm/hm.h>
67	#include <VBox/vmm/mm.h>
68	#include <VBox/vmm/ssm.h>
69	#include <VBox/vmm/pgm.h>
70	#include <VBox/vmm/trpm.h>
71	#include <VBox/vmm/dbgf.h>
72	#include "SELMInternal.h"
73	#include <VBox/vmm/vm.h>
74	#include <VBox/err.h>
75	#include <VBox/param.h>
76
77	#include <iprt/assert.h>
78	#include <VBox/log.h>
79	#include <iprt/asm.h>
80	#include <iprt/string.h>
81	#include <iprt/thread.h>
82	#include <iprt/string.h>
83
84	#include "SELMInline.h"
85
86
87	/** SELM saved state version. */
88	#define SELM_SAVED_STATE_VERSION 5
89
90
91	/*******************************************************************************
92	* Internal Functions *
93	*******************************************************************************/
94	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
95	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
96	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
97	static FNPGMR3VIRTHANDLER selmR3GuestGDTWriteHandler;
98	static FNPGMR3VIRTHANDLER selmR3GuestLDTWriteHandler;
99	static FNPGMR3VIRTHANDLER selmR3GuestTSSWriteHandler;
100	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106
107
108	/*******************************************************************************
109	* Global Variables *
110	*******************************************************************************/
111	#ifdef LOG_ENABLED
112	/** Segment register names. */
113	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
114	#endif
115
116
117	/**
118	* Initializes the SELM.
119	*
120	* @returns VBox status code.
121	* @param pVM Pointer to the VM.
122	*/
123	VMMR3DECL(int) SELMR3Init(PVM pVM)
124	{
125	int rc;
126	LogFlow(("SELMR3Init\n"));
127
128	/*
129	* Assert alignment and sizes.
130	* (The TSS block requires contiguous back.)
131	*/
132	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
133	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
134	#if 0 /* doesn't work */
135	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
136	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
137	#endif
138	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
139	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
140	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
141
142	/*
143	* Init the structure.
144	*/
145	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
146	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
147	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
148	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
149	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
150	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
151
152	if (HMIsRawModeCtxNeeded(pVM))
153	{
154	/*
155	* Allocate GDT table.
156	*/
157	rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
158	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
159	AssertRCReturn(rc, rc);
160
161	/*
162	* Allocate LDT area.
163	*/
164	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
165	AssertRCReturn(rc, rc);
166	}
167
168	/*
169	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
170	*/
171	pVM->selm.s.cbEffGuestGdtLimit = 0;
172	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
173	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
174	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
175
176	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
177	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
178	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
179	pVM->selm.s.GCSelTss = RTSEL_MAX;
180
181	pVM->selm.s.fSyncTSSRing0Stack = false;
182
183	/* The I/O bitmap starts right after the virtual interrupt redirection
184	bitmap. Outside the TSS on purpose; the CPU will not check it for
185	I/O operations. */
186	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
187	/* bit set to 1 means no redirection */
188	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
189
190	/*
191	* Register the virtual access handlers.
192	*/
193	pVM->selm.s.hShadowGdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
194	pVM->selm.s.hShadowLdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
195	pVM->selm.s.hShadowTssWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
196	pVM->selm.s.hGuestGdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
197	pVM->selm.s.hGuestLdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
198	pVM->selm.s.hGuestTssWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
199	#ifdef VBOX_WITH_RAW_MODE
200	if (!HMIsEnabled(pVM))
201	{
202	# ifdef SELM_TRACK_SHADOW_GDT_CHANGES
203	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
204	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
205	"selmRCShadowGDTWritePfHandler",
206	"Shadow GDT write access handler", &pVM->selm.s.hShadowGdtWriteHandlerType);
207	AssertRCReturn(rc, rc);
208	# endif
209	# ifdef SELM_TRACK_SHADOW_TSS_CHANGES
210	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
211	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
212	"selmRCShadowTSSWritePfHandler",
213	"Shadow TSS write access handler", &pVM->selm.s.hShadowTssWriteHandlerType);
214	AssertRCReturn(rc, rc);
215	# endif
216	# ifdef SELM_TRACK_SHADOW_LDT_CHANGES
217	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
218	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
219	"selmRCShadowLDTWritePfHandler",
220	"Shadow LDT write access handler", &pVM->selm.s.hShadowLdtWriteHandlerType);
221	AssertRCReturn(rc, rc);
222	# endif
223	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
224	NULL /pfnInvalidateR3/, selmR3GuestGDTWriteHandler,
225	"selmRCGuestGDTWritePfHandler",
226	"Guest GDT write access handler", &pVM->selm.s.hGuestGdtWriteHandlerType);
227	AssertRCReturn(rc, rc);
228	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
229	NULL /pfnInvalidateR3/, selmR3GuestLDTWriteHandler,
230	"selmRCGuestLDTWritePfHandler",
231	"Guest LDT write access handler", &pVM->selm.s.hGuestLdtWriteHandlerType);
232	AssertRCReturn(rc, rc);
233	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
234	NULL /pfnInvalidateR3/, selmR3GuestTSSWriteHandler,
235	"selmRCGuestTSSWritePfHandler",
236	"Guest TSS write access handler", &pVM->selm.s.hGuestTssWriteHandlerType);
237	AssertRCReturn(rc, rc);
238	}
239	#endif /* VBOX_WITH_RAW_MODE */
240
241	/*
242	* Register the saved state data unit.
243	*/
244	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
245	NULL, NULL, NULL,
246	NULL, selmR3Save, NULL,
247	NULL, selmR3Load, selmR3LoadDone);
248	if (RT_FAILURE(rc))
249	return rc;
250
251	/*
252	* Statistics.
253	*/
254	if (!HMIsEnabled(pVM))
255	{
256	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
257	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
258	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
259	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
260	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
261	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
262	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
263	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
264	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
265
266	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
267	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
268
269	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
270	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
271	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
272	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
273	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
274	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
275
276	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
277	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
278	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
279	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
280	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
281	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
282
283	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
284
285	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
286	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
287	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
288	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
289	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
290	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
291	}
292
293	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
294	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
295	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
296	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
297
298	#ifdef VBOX_WITH_RAW_MODE
299	/*
300	* Default action when entering raw mode for the first time
301	*/
302	if (!HMIsEnabled(pVM))
303	{
304	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
305	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
306	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
307	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
308	}
309	#endif
310
311	/*
312	* Register info handlers.
313	*/
314	if (HMIsRawModeCtxNeeded(pVM))
315	{
316	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
317	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
318	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
319	}
320	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
321	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
322	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
323
324	return rc;
325	}
326
327
328	/**
329	* Finalizes HMA page attributes.
330	*
331	* @returns VBox status code.
332	* @param pVM Pointer to the VM.
333	*/
334	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
335	{
336	#ifdef VBOX_WITH_RAW_MODE
337	/** @cfgm{/DoubleFault,bool,false}
338	* Enables catching of double faults in the raw-mode context VMM code. This can
339	* be used when the triple faults or hangs occur and one suspect an unhandled
340	* double fault. This is not enabled by default because it means making the
341	* hyper selectors writeable for all supervisor code, including the guest's.
342	* The double fault is a task switch and thus requires write access to the GDT
343	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
344	* 8 TSS for the back link.
345	*/
346	bool f;
347	# if defined(DEBUG_bird)
348	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
349	# else
350	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
351	# endif
352	AssertLogRelRCReturn(rc, rc);
353	if (f && HMIsRawModeCtxNeeded(pVM))
354	{
355	PX86DESC paGdt = pVM->selm.s.paGdtR3;
356	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
357	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
358	AssertRC(rc);
359	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
360	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
361	AssertRC(rc);
362	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
363	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
364	AssertRC(rc);
365	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
366	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
367	AssertRC(rc);
368	}
369	#endif /* VBOX_WITH_RAW_MODE */
370	return VINF_SUCCESS;
371	}
372
373
374	/**
375	* Setup the hypervisor GDT selectors in our shadow table
376	*
377	* @param pVM Pointer to the VM.
378	*/
379	static void selmR3SetupHyperGDTSelectors(PVM pVM)
380	{
381	PX86DESC paGdt = pVM->selm.s.paGdtR3;
382
383	/*
384	* Set up global code and data descriptors for use in the guest context.
385	* Both are wide open (base 0, limit 4GB)
386	*/
387	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
388	pDesc->Gen.u16LimitLow = 0xffff;
389	pDesc->Gen.u4LimitHigh = 0xf;
390	pDesc->Gen.u16BaseLow = 0;
391	pDesc->Gen.u8BaseHigh1 = 0;
392	pDesc->Gen.u8BaseHigh2 = 0;
393	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
394	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
395	pDesc->Gen.u2Dpl = 0; /* supervisor */
396	pDesc->Gen.u1Present = 1;
397	pDesc->Gen.u1Available = 0;
398	pDesc->Gen.u1Long = 0;
399	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
400	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
401
402	/* data */
403	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
404	pDesc->Gen.u16LimitLow = 0xffff;
405	pDesc->Gen.u4LimitHigh = 0xf;
406	pDesc->Gen.u16BaseLow = 0;
407	pDesc->Gen.u8BaseHigh1 = 0;
408	pDesc->Gen.u8BaseHigh2 = 0;
409	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
410	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
411	pDesc->Gen.u2Dpl = 0; /* supervisor */
412	pDesc->Gen.u1Present = 1;
413	pDesc->Gen.u1Available = 0;
414	pDesc->Gen.u1Long = 0;
415	pDesc->Gen.u1DefBig = 1; /* big */
416	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
417
418	/* 64-bit mode code (& data?) */
419	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
420	pDesc->Gen.u16LimitLow = 0xffff;
421	pDesc->Gen.u4LimitHigh = 0xf;
422	pDesc->Gen.u16BaseLow = 0;
423	pDesc->Gen.u8BaseHigh1 = 0;
424	pDesc->Gen.u8BaseHigh2 = 0;
425	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
426	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
427	pDesc->Gen.u2Dpl = 0; /* supervisor */
428	pDesc->Gen.u1Present = 1;
429	pDesc->Gen.u1Available = 0;
430	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
431	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
432	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
433
434	/*
435	* TSS descriptor
436	*/
437	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
438	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
439	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
440	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
441	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
442	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
443	pDesc->Gen.u4LimitHigh = 0;
444	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
445	pDesc->Gen.u1DescType = 0; /* system */
446	pDesc->Gen.u2Dpl = 0; /* supervisor */
447	pDesc->Gen.u1Present = 1;
448	pDesc->Gen.u1Available = 0;
449	pDesc->Gen.u1Long = 0;
450	pDesc->Gen.u1DefBig = 0;
451	pDesc->Gen.u1Granularity = 0; /* byte limit */
452
453	/*
454	* TSS descriptor for trap 08
455	*/
456	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
457	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
458	pDesc->Gen.u4LimitHigh = 0;
459	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
460	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
461	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
462	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
463	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
464	pDesc->Gen.u1DescType = 0; /* system */
465	pDesc->Gen.u2Dpl = 0; /* supervisor */
466	pDesc->Gen.u1Present = 1;
467	pDesc->Gen.u1Available = 0;
468	pDesc->Gen.u1Long = 0;
469	pDesc->Gen.u1DefBig = 0;
470	pDesc->Gen.u1Granularity = 0; /* byte limit */
471	}
472
473	/**
474	* Applies relocations to data and code managed by this
475	* component. This function will be called at init and
476	* whenever the VMM need to relocate it self inside the GC.
477	*
478	* @param pVM The VM.
479	*/
480	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
481	{
482	PX86DESC paGdt = pVM->selm.s.paGdtR3;
483	LogFlow(("SELMR3Relocate\n"));
484
485	if (HMIsRawModeCtxNeeded(pVM))
486	{
487	for (VMCPUID i = 0; i < pVM->cCpus; i++)
488	{
489	PVMCPU pVCpu = &pVM->aCpus[i];
490
491	/*
492	* Update GDTR and selector.
493	*/
494	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
495
496	/** @todo selector relocations should be a separate operation? */
497	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
498	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
499	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
500	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
501	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
502	}
503
504	selmR3SetupHyperGDTSelectors(pVM);
505
506	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
507	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
508	/*
509	* Update the TSSes.
510	*/
511	/* Only applies to raw mode which supports only 1 VCPU */
512	PVMCPU pVCpu = &pVM->aCpus[0];
513
514	/* Current TSS */
515	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
516	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
517	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
518	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
519	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
520	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
521	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
522
523	/* trap 08 */
524	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
525	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
526	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
527	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
528	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
529	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
530	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
531	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
532	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
533	pVM->selm.s.TssTrap08.fs = 0;
534	pVM->selm.s.TssTrap08.gs = 0;
535	pVM->selm.s.TssTrap08.selLdt = 0;
536	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
537	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
538	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
539	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
540	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
541	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
542	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
543	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
544	/* TRPM will be updating the eip */
545	}
546
547	if (!HMIsEnabled(pVM))
548	{
549	/*
550	* Update shadow GDT/LDT/TSS write access handlers.
551	*/
552	PVMCPU pVCpu = VMMGetCpu(pVM); NOREF(pVCpu);
553	int rc; NOREF(rc);
554	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
555	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
556	{
557	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.paGdtRC, true /fHypervisor/);
558	AssertRC(rc);
559	}
560	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
561	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowGdtWriteHandlerType,
562	pVM->selm.s.paGdtRC,
563	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
564	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
565	AssertRC(rc);
566	#endif
567	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
568	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
569	{
570	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.pvMonShwTssRC, true /fHypervisor/);
571	AssertRC(rc);
572	}
573	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
574	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowTssWriteHandlerType,
575	pVM->selm.s.pvMonShwTssRC,
576	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
577	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
578	AssertRC(rc);
579	#endif
580
581	/*
582	* Update the GC LDT region handler and address.
583	*/
584	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
585	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
586	{
587	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.pvLdtRC, true /fHypervisor/);
588	AssertRC(rc);
589	}
590	#endif
591	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
592	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
593	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowLdtWriteHandlerType,
594	pVM->selm.s.pvLdtRC,
595	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
596	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
597	AssertRC(rc);
598	#endif
599	}
600	}
601
602
603	/**
604	* Terminates the SELM.
605	*
606	* Termination means cleaning up and freeing all resources,
607	* the VM it self is at this point powered off or suspended.
608	*
609	* @returns VBox status code.
610	* @param pVM Pointer to the VM.
611	*/
612	VMMR3DECL(int) SELMR3Term(PVM pVM)
613	{
614	NOREF(pVM);
615	return VINF_SUCCESS;
616	}
617
618
619	/**
620	* The VM is being reset.
621	*
622	* For the SELM component this means that any GDT/LDT/TSS monitors
623	* needs to be removed.
624	*
625	* @param pVM Pointer to the VM.
626	*/
627	VMMR3DECL(void) SELMR3Reset(PVM pVM)
628	{
629	LogFlow(("SELMR3Reset:\n"));
630	VM_ASSERT_EMT(pVM);
631
632	/*
633	* Uninstall guest GDT/LDT/TSS write access handlers.
634	*/
635	PVMCPU pVCpu = VMMGetCpu(pVM); NOREF(pVCpu);
636	int rc = VINF_SUCCESS;
637	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
638	{
639	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
640	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GuestGdtr.pGdt, false /fHypervisor/);
641	AssertRC(rc);
642	#endif
643	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
644	pVM->selm.s.GuestGdtr.cbGdt = 0;
645	}
646	pVM->selm.s.fGDTRangeRegistered = false;
647	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
648	{
649	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
650	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /fHypervisor/);
651	AssertRC(rc);
652	#endif
653	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
654	}
655	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
656	{
657	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
658	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestTss, false /fHypervisor/);
659	AssertRC(rc);
660	#endif
661	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
662	pVM->selm.s.GCSelTss = RTSEL_MAX;
663	}
664
665	/*
666	* Re-initialize other members.
667	*/
668	pVM->selm.s.cbLdtLimit = 0;
669	pVM->selm.s.offLdtHyper = 0;
670	pVM->selm.s.cbMonitoredGuestTss = 0;
671
672	pVM->selm.s.fSyncTSSRing0Stack = false;
673
674	#ifdef VBOX_WITH_RAW_MODE
675	if (!HMIsEnabled(pVM))
676	{
677	/*
678	* Default action when entering raw mode for the first time
679	*/
680	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
681	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
682	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
683	}
684	#endif
685	}
686
687
688	/**
689	* Execute state save operation.
690	*
691	* @returns VBox status code.
692	* @param pVM Pointer to the VM.
693	* @param pSSM SSM operation handle.
694	*/
695	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
696	{
697	LogFlow(("selmR3Save:\n"));
698
699	/*
700	* Save the basic bits - fortunately all the other things can be resynced on load.
701	*/
702	PSELM pSelm = &pVM->selm.s;
703
704	SSMR3PutBool(pSSM, HMIsEnabled(pVM));
705	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
706	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
707	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
708	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
709	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
710	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
711	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
712	}
713
714
715	/**
716	* Execute state load operation.
717	*
718	* @returns VBox status code.
719	* @param pVM Pointer to the VM.
720	* @param pSSM SSM operation handle.
721	* @param uVersion Data layout version.
722	* @param uPass The data pass.
723	*/
724	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
725	{
726	LogFlow(("selmR3Load:\n"));
727	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
728
729	/*
730	* Validate version.
731	*/
732	if (uVersion != SELM_SAVED_STATE_VERSION)
733	{
734	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
735	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
736	}
737
738	/*
739	* Do a reset.
740	*/
741	SELMR3Reset(pVM);
742
743	/* Get the monitoring flag. */
744	bool fIgnored;
745	SSMR3GetBool(pSSM, &fIgnored);
746
747	/* Get the TSS state flag. */
748	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
749
750	/*
751	* Get the selectors.
752	*/
753	RTSEL SelCS;
754	SSMR3GetSel(pSSM, &SelCS);
755	RTSEL SelDS;
756	SSMR3GetSel(pSSM, &SelDS);
757	RTSEL SelCS64;
758	SSMR3GetSel(pSSM, &SelCS64);
759	RTSEL SelDS64;
760	SSMR3GetSel(pSSM, &SelDS64);
761	RTSEL SelTSS;
762	SSMR3GetSel(pSSM, &SelTSS);
763	RTSEL SelTSSTrap08;
764	SSMR3GetSel(pSSM, &SelTSSTrap08);
765
766	/* Copy the selectors; they will be checked during relocation. */
767	PSELM pSelm = &pVM->selm.s;
768	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
769	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
770	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
771	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
772	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
773
774	return VINF_SUCCESS;
775	}
776
777
778	/**
779	* Sync the GDT, LDT and TSS after loading the state.
780	*
781	* Just to play save, we set the FFs to force syncing before
782	* executing GC code.
783	*
784	* @returns VBox status code.
785	* @param pVM Pointer to the VM.
786	* @param pSSM SSM operation handle.
787	*/
788	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
789	{
790	#ifdef VBOX_WITH_RAW_MODE
791	if (!HMIsEnabled(pVM))
792	{
793	PVMCPU pVCpu = VMMGetCpu(pVM);
794
795	LogFlow(("selmR3LoadDone:\n"));
796
797	/*
798	* Don't do anything if it's a load failure.
799	*/
800	int rc = SSMR3HandleGetStatus(pSSM);
801	if (RT_FAILURE(rc))
802	return VINF_SUCCESS;
803
804	/*
805	* Do the syncing if we're in protected mode and using raw-mode.
806	*/
807	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
808	{
809	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
810	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
811	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
812	SELMR3UpdateFromCPUM(pVM, pVCpu);
813	}
814
815	/*
816	* Flag everything for resync on next raw mode entry.
817	*/
818	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
819	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
820	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
821	}
822	#endif /VBOX_WITH_RAW_MODE/
823	return VINF_SUCCESS;
824	}
825
826	#ifdef VBOX_WITH_RAW_MODE
827
828	/**
829	* Updates (syncs) the shadow GDT.
830	*
831	* @returns VBox status code.
832	* @param pVM The VM handle.
833	* @param pVCpu The current virtual CPU.
834	*/
835	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
836	{
837	Assert(!HMIsEnabled(pVM));
838
839	/*
840	* Always assume the best...
841	*/
842	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
843
844	/* If the GDT was changed, then make sure the LDT is checked too */
845	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
846	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
847	/* Same goes for the TSS selector */
848	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
849
850	/*
851	* Get the GDTR and check if there is anything to do (there usually is).
852	*/
853	VBOXGDTR GDTR;
854	CPUMGetGuestGDTR(pVCpu, &GDTR);
855	if (GDTR.cbGdt < sizeof(X86DESC))
856	{
857	Log(("No GDT entries...\n"));
858	return VINF_SUCCESS;
859	}
860
861	/*
862	* Read the Guest GDT.
863	* ASSUMES that the entire GDT is in memory.
864	*/
865	RTUINT cbEffLimit = GDTR.cbGdt;
866	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
867	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
868	if (RT_FAILURE(rc))
869	{
870	/*
871	* Read it page by page.
872	*
873	* Keep track of the last valid page and delay memsets and
874	* adjust cbEffLimit to reflect the effective size. The latter
875	* is something we do in the belief that the guest will probably
876	* never actually commit the last page, thus allowing us to keep
877	* our selectors in the high end of the GDT.
878	*/
879	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
880	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
881	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
882	uint8_t *pu8DstInvalid = pu8Dst;
883
884	while (cbLeft)
885	{
886	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
887	cb = RT_MIN(cb, cbLeft);
888	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
889	if (RT_SUCCESS(rc))
890	{
891	if (pu8DstInvalid != pu8Dst)
892	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
893	GCPtrSrc += cb;
894	pu8Dst += cb;
895	pu8DstInvalid = pu8Dst;
896	}
897	else if ( rc == VERR_PAGE_NOT_PRESENT
898	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
899	{
900	GCPtrSrc += cb;
901	pu8Dst += cb;
902	}
903	else
904	{
905	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
906	return VERR_SELM_GDT_READ_ERROR;
907	}
908	cbLeft -= cb;
909	}
910
911	/* any invalid pages at the end? */
912	if (pu8DstInvalid != pu8Dst)
913	{
914	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
915	/* If any GDTEs was invalidated, zero them. */
916	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
917	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
918	}
919
920	/* keep track of the effective limit. */
921	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
922	{
923	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
924	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
925	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
926	}
927	}
928
929	/*
930	* Check if the Guest GDT intrudes on our GDT entries.
931	*/
932	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
933	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
934	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
935	{
936	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
937	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
938	int iGDT = 0;
939
940	Log(("Internal SELM GDT conflict: use non-present entries\n"));
941	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
942	while ((uintptr_t)pGDTECur > (uintptr_t)pGDTEStart)
943	{
944	/* We can reuse non-present entries */
945	if (!pGDTECur->Gen.u1Present)
946	{
947	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
948	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
949	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
950	iGDT++;
951	if (iGDT >= SELM_HYPER_SEL_MAX)
952	break;
953	}
954
955	pGDTECur--;
956	}
957	if (iGDT != SELM_HYPER_SEL_MAX)
958	{
959	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
960	return VERR_SELM_GDT_TOO_FULL;
961	}
962	}
963	else
964	{
965	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
966	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
967	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
968	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
969	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
970	}
971
972	# ifdef VBOX_WITH_SAFE_STR
973	/* Use the guest's TR selector to plug the str virtualization hole. */
974	if (CPUMGetGuestTR(pVCpu, NULL) != 0)
975	{
976	Log(("SELM: Use guest TSS selector %x\n", CPUMGetGuestTR(pVCpu, NULL)));
977	aHyperSel[SELM_HYPER_SEL_TSS] = CPUMGetGuestTR(pVCpu, NULL);
978	}
979	# endif
980
981	/*
982	* Work thru the copied GDT entries adjusting them for correct virtualization.
983	*/
984	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
985	while (pGDTE < pGDTEEnd)
986	{
987	if (pGDTE->Gen.u1Present)
988	selmGuestToShadowDesc(pVM, pGDTE);
989
990	/* Next GDT entry. */
991	pGDTE++;
992	}
993
994	/*
995	* Check if our hypervisor selectors were changed.
996	*/
997	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
998	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
999	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
1000	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
1001	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
1002	{
1003	/* Reinitialize our hypervisor GDTs */
1004	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1005	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1006	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1007	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1008	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1009
1010	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1011
1012	/*
1013	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
1014	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1015	*/
1016	VMR3Relocate(pVM, 0);
1017	}
1018	# ifdef VBOX_WITH_SAFE_STR
1019	else if ( cbEffLimit >= SELM_HYPER_DEFAULT_BASE
1020	\|\| CPUMGetGuestTR(pVCpu, NULL) != 0) /* Our shadow TR entry was overwritten when we synced the guest's GDT. */
1021	# else
1022	else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1023	# endif
1024	/* We overwrote all entries above, so we have to save them again. */
1025	selmR3SetupHyperGDTSelectors(pVM);
1026
1027	/*
1028	* Adjust the cached GDT limit.
1029	* Any GDT entries which have been removed must be cleared.
1030	*/
1031	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1032	{
1033	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1034	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1035	}
1036
1037	/*
1038	* Check if Guest's GDTR is changed.
1039	*/
1040	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1041	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1042	{
1043	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1044
1045	# ifdef SELM_TRACK_GUEST_GDT_CHANGES
1046	/*
1047	* [Re]Register write virtual handler for guest's GDT.
1048	*/
1049	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1050	{
1051	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GuestGdtr.pGdt, false /fHypervisor/);
1052	AssertRC(rc);
1053	}
1054	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestGdtWriteHandlerType,
1055	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1056	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1057	# ifdef VBOX_WITH_RAW_RING1
1058	/** @todo !HACK ALERT!
1059	* Some guest OSes (QNX) share code and the GDT on the same page;
1060	* PGMR3HandlerVirtualRegister doesn't support more than one handler,
1061	* so we kick out the PATM handler as this one is more important. Fix this
1062	* properly in PGMR3HandlerVirtualRegister?
1063	*/
1064	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1065	{
1066	LogRel(("selmR3UpdateShadowGdt: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority GDT page monitor\n", GDTR.pGdt));
1067	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, GDTR.pGdt & PAGE_BASE_GC_MASK, false /fHypervisor/);
1068	AssertRC(rc);
1069	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestGdtWriteHandlerType,
1070	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1071	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1072	}
1073	# endif
1074	if (RT_FAILURE(rc))
1075	return rc;
1076	# endif /* SELM_TRACK_GUEST_GDT_CHANGES */
1077
1078	/* Update saved Guest GDTR. */
1079	pVM->selm.s.GuestGdtr = GDTR;
1080	pVM->selm.s.fGDTRangeRegistered = true;
1081	}
1082
1083	return VINF_SUCCESS;
1084	}
1085
1086
1087	/**
1088	* Updates (syncs) the shadow LDT.
1089	*
1090	* @returns VBox status code.
1091	* @param pVM The VM handle.
1092	* @param pVCpu The current virtual CPU.
1093	*/
1094	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1095	{
1096	int rc = VINF_SUCCESS;
1097	Assert(!HMIsEnabled(pVM));
1098
1099	/*
1100	* Always assume the best...
1101	*/
1102	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1103
1104	/*
1105	* LDT handling is done similarly to the GDT handling with a shadow
1106	* array. However, since the LDT is expected to be swappable (at least
1107	* some ancient OSes makes it swappable) it must be floating and
1108	* synced on a per-page basis.
1109	*
1110	* Eventually we will change this to be fully on demand. Meaning that
1111	* we will only sync pages containing LDT selectors actually used and
1112	* let the #PF handler lazily sync pages as they are used.
1113	* (This applies to GDT too, when we start making OS/2 fast.)
1114	*/
1115
1116	/*
1117	* First, determine the current LDT selector.
1118	*/
1119	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1120	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1121	{
1122	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1123	CPUMSetHyperLDTR(pVCpu, 0);
1124	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1125	{
1126	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /fHypervisor/);
1127	AssertRC(rc);
1128	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1129	}
1130	pVM->selm.s.cbLdtLimit = 0;
1131	return VINF_SUCCESS;
1132	}
1133
1134	/*
1135	* Get the LDT selector.
1136	*/
1137	/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1138	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1139	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1140	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1141
1142	/*
1143	* Validate it.
1144	*/
1145	if ( !cbLdt
1146	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1147	\|\| pDesc->Gen.u1DescType
1148	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1149	{
1150	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1151
1152	/* cbLdt > 0:
1153	* This is quite impossible, so we do as most people do when faced with
1154	* the impossible, we simply ignore it.
1155	*/
1156	CPUMSetHyperLDTR(pVCpu, 0);
1157	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1158	{
1159	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /fHypervisor/);
1160	AssertRC(rc);
1161	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1162	}
1163	return VINF_SUCCESS;
1164	}
1165	/** @todo check what intel does about odd limits. */
1166	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1167
1168	/*
1169	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1170	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1171	*/
1172	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1173	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1174
1175
1176	/** @todo Handle only present LDT segments. */
1177	// if (pDesc->Gen.u1Present)
1178	{
1179	/*
1180	* Check if Guest's LDT address/limit is changed.
1181	*/
1182	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1183	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1184	{
1185	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1186	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1187
1188	# ifdef SELM_TRACK_GUEST_LDT_CHANGES
1189	/*
1190	* [Re]Register write virtual handler for guest's GDT.
1191	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1192	*/
1193	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1194	{
1195	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /fHypervisor/);
1196	AssertRC(rc);
1197	}
1198	# ifdef LOG_ENABLED
1199	if (pDesc->Gen.u1Present)
1200	Log(("LDT selector marked not present!!\n"));
1201	# endif
1202	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestLdtWriteHandlerType,
1203	GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1204	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1205	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1206	{
1207	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1208	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1209	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1210	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1211	}
1212	else if (RT_SUCCESS(rc))
1213	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1214	else
1215	{
1216	CPUMSetHyperLDTR(pVCpu, 0);
1217	return rc;
1218	}
1219	# else
1220	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1221	# endif
1222	pVM->selm.s.cbLdtLimit = cbLdt;
1223	}
1224	}
1225
1226	/*
1227	* Calc Shadow LDT base.
1228	*/
1229	unsigned off;
1230	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1231	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1232	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1233
1234	/*
1235	* Enable the LDT selector in the shadow GDT.
1236	*/
1237	pDesc->Gen.u1Present = 1;
1238	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1239	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1240	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1241	pDesc->Gen.u1Available = 0;
1242	pDesc->Gen.u1Long = 0;
1243	if (cbLdt > 0xffff)
1244	{
1245	cbLdt = 0xffff;
1246	pDesc->Gen.u4LimitHigh = 0;
1247	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1248	}
1249
1250	/*
1251	* Set Hyper LDTR and notify TRPM.
1252	*/
1253	CPUMSetHyperLDTR(pVCpu, SelLdt);
1254
1255	/*
1256	* Loop synchronising the LDT page by page.
1257	*/
1258	/** @todo investigate how intel handle various operations on half present cross page entries. */
1259	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1260	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1261
1262	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1263	unsigned cbLeft = cbLdt + 1;
1264	PX86DESC pLDTE = pShadowLDT;
1265	while (cbLeft)
1266	{
1267	/*
1268	* Read a chunk.
1269	*/
1270	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1271	if (cbChunk > cbLeft)
1272	cbChunk = cbLeft;
1273	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1274	if (RT_SUCCESS(rc))
1275	{
1276	/*
1277	* Mark page
1278	*/
1279	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1280	AssertRC(rc);
1281
1282	/*
1283	* Loop thru the available LDT entries.
1284	* Figure out where to start and end and the potential cross pageness of
1285	* things adds a little complexity. pLDTE is updated there and not in the
1286	* 'next' part of the loop. The pLDTEEnd is inclusive.
1287	*/
1288	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1289	if (pLDTE + 1 < pShadowLDT)
1290	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1291	while (pLDTE <= pLDTEEnd)
1292	{
1293	if (pLDTE->Gen.u1Present)
1294	selmGuestToShadowDesc(pVM, pLDTE);
1295
1296	/* Next LDT entry. */
1297	pLDTE++;
1298	}
1299	}
1300	else
1301	{
1302	RT_BZERO(pShadowLDT, cbChunk);
1303	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1304	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1305	AssertRC(rc);
1306	}
1307
1308	/*
1309	* Advance to the next page.
1310	*/
1311	cbLeft -= cbChunk;
1312	GCPtrShadowLDT += cbChunk;
1313	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1314	GCPtrLdt += cbChunk;
1315	}
1316
1317	return VINF_SUCCESS;
1318	}
1319
1320
1321	/**
1322	* Checks and updates segment selector registers.
1323	*
1324	* @returns VBox strict status code.
1325	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1326	*
1327	* @param pVM The VM handle.
1328	* @param pVCpu The current virtual CPU.
1329	*/
1330	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1331	{
1332	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1333	Assert(!HMIsEnabled(pVM));
1334
1335	/*
1336	* No stale selectors in V8086 mode.
1337	*/
1338	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1339	if (pCtx->eflags.Bits.u1VM)
1340	return VINF_SUCCESS;
1341
1342	/*
1343	* Check for stale selectors and load hidden register bits where they
1344	* are missing.
1345	*/
1346	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1347	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1348	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1349	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1350	{
1351	RTSEL const Sel = paSReg[iSReg].Sel;
1352	if (Sel & X86_SEL_MASK_OFF_RPL)
1353	{
1354	/* Get the shadow descriptor entry corresponding to this. */
1355	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1356	PCX86DESC pDesc;
1357	if (!(Sel & X86_SEL_LDT))
1358	{
1359	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1360	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1361	else
1362	pDesc = &s_NotPresentDesc;
1363	}
1364	else
1365	{
1366	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1367	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1368	else
1369	pDesc = &s_NotPresentDesc;
1370	}
1371
1372	/* Check the segment register. */
1373	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1374	{
1375	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1376	{
1377	/* Did it go stale? */
1378	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1379	{
1380	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1381	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1382	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1383	rcStrict = VINF_EM_RESCHEDULE_REM;
1384	}
1385	}
1386	else
1387	{
1388	/* Did it stop being stale? I.e. did the guest change it things
1389	back to the way they were? */
1390	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1391	{
1392	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1393	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1394	}
1395	else
1396	{
1397	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1398	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1399	rcStrict = VINF_EM_RESCHEDULE_REM;
1400	}
1401	}
1402	}
1403	/* Load the hidden registers if it's a valid descriptor for the
1404	current segment register. */
1405	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1406	{
1407	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1408	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1409	}
1410	/* It's stale. */
1411	else
1412	{
1413	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1414	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1415	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1416	rcStrict = VINF_EM_RESCHEDULE_REM;
1417	}
1418	}
1419	/* else: 0 selector, ignore. */
1420	}
1421
1422	return rcStrict;
1423	}
1424
1425
1426	/**
1427	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1428	*
1429	* @returns VBox status code.
1430	* @param pVM Pointer to the VM.
1431	* @param pVCpu Pointer to the VMCPU.
1432	*/
1433	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1434	{
1435	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1436	AssertReturn(!HMIsEnabled(pVM), VERR_SELM_HM_IPE);
1437
1438	/*
1439	* GDT sync
1440	*/
1441	int rc;
1442	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1443	{
1444	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1445	if (RT_FAILURE(rc))
1446	return rc; /* We're toast, so forget the profiling. */
1447	AssertRCSuccess(rc);
1448	}
1449
1450	/*
1451	* TSS sync
1452	*/
1453	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1454	{
1455	rc = SELMR3SyncTSS(pVM, pVCpu);
1456	if (RT_FAILURE(rc))
1457	return rc;
1458	AssertRCSuccess(rc);
1459	}
1460
1461	/*
1462	* LDT sync
1463	*/
1464	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1465	{
1466	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1467	if (RT_FAILURE(rc))
1468	return rc;
1469	AssertRCSuccess(rc);
1470	}
1471
1472	/*
1473	* Check selector registers.
1474	*/
1475	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1476
1477	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1478	return rcStrict;
1479	}
1480
1481	#endif /VBOX_WITH_RAW_MODE/
1482
1483	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1484	/**
1485	* \#PF Handler callback for virtual access handler ranges.
1486	*
1487	* Important to realize that a physical page in a range can have aliases, and
1488	* for ALL and WRITE handlers these will also trigger.
1489	*
1490	* @returns VINF_SUCCESS if the handler have carried out the operation.
1491	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1492	* @param pVM Pointer to the VM.
1493	* @param pVCpu Pointer to the cross context CPU context for the
1494	* calling EMT.
1495	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1496	* @param pvPtr The HC mapping of that address.
1497	* @param pvBuf What the guest is reading/writing.
1498	* @param cbBuf How much it's reading/writing.
1499	* @param enmAccessType The access type.
1500	* @param enmOrigin Who is making this write.
1501	* @param pvUser Unused.
1502	*/
1503	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1504	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1505	{
1506	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1507	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1508	NOREF(pvPtr); NOREF(pvBuf); NOREF(enmOrigin); NOREF(pvUser);
1509
1510	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
1511	return VINF_PGM_HANDLER_DO_DEFAULT;
1512	}
1513	#endif
1514
1515	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1516	/**
1517	* \#PF Handler callback for virtual access handler ranges.
1518	*
1519	* Important to realize that a physical page in a range can have aliases, and
1520	* for ALL and WRITE handlers these will also trigger.
1521	*
1522	* @returns VINF_SUCCESS if the handler have carried out the operation.
1523	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1524	* @param pVM Pointer to the VM.
1525	* @param pVCpu Pointer to the cross context CPU context for the
1526	* calling EMT.
1527	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1528	* @param pvPtr The HC mapping of that address.
1529	* @param pvBuf What the guest is reading/writing.
1530	* @param cbBuf How much it's reading/writing.
1531	* @param enmAccessType The access type.
1532	* @param enmOrigin Who is making this write.
1533	* @param pvUser Unused.
1534	*/
1535	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1536	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1537	{
1538	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1539	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1540	NOREF(pvPtr); NOREF(pvBuf); NOREF(enmOrigin); NOREF(pvUser);
1541
1542	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1543	return VINF_PGM_HANDLER_DO_DEFAULT;
1544	}
1545	#endif
1546
1547
1548	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1549	/**
1550	* \#PF Handler callback for virtual access handler ranges.
1551	*
1552	* Important to realize that a physical page in a range can have aliases, and
1553	* for ALL and WRITE handlers these will also trigger.
1554	*
1555	* @returns VINF_SUCCESS if the handler have carried out the operation.
1556	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1557	* @param pVM Pointer to the VM.
1558	* @param pVCpu Pointer to the cross context CPU context for the
1559	* calling EMT.
1560	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1561	* @param pvPtr The HC mapping of that address.
1562	* @param pvBuf What the guest is reading/writing.
1563	* @param cbBuf How much it's reading/writing.
1564	* @param enmAccessType The access type.
1565	* @param enmOrigin Who is making this write.
1566	* @param pvUser Unused.
1567	*/
1568	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1569	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1570	{
1571	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1572	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1573	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(enmOrigin); NOREF(pvUser); NOREF(pvPtr);
1574
1575	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1576	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1577	* should probably also deregister the virtual handler if TR.base/size
1578	* changes while we're in REM. */
1579
1580	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1581	return VINF_PGM_HANDLER_DO_DEFAULT;
1582	}
1583	#endif
1584
1585	#ifdef VBOX_WITH_RAW_MODE
1586
1587	/**
1588	* Synchronize the shadowed fields in the TSS.
1589	*
1590	* At present we're shadowing the ring-0 stack selector & pointer, and the
1591	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1592	* REM and this function is called both if REM made any changes to the TSS or
1593	* loaded TR.
1594	*
1595	* @returns VBox status code.
1596	* @param pVM Pointer to the VM.
1597	* @param pVCpu Pointer to the VMCPU.
1598	*/
1599	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1600	{
1601	int rc;
1602	AssertReturnStmt(!HMIsEnabled(pVM), VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS), VINF_SUCCESS);
1603
1604	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1605	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1606
1607	/*
1608	* Get TR and extract and store the basic info.
1609	*
1610	* Note! The TSS limit is not checked by the LTR code, so we
1611	* have to be a bit careful with it. We make sure cbTss
1612	* won't be zero if TR is valid and if it's NULL we'll
1613	* make sure cbTss is 0.
1614	*/
1615	/** @todo use the hidden bits, not shadow GDT. */
1616	CPUMSELREGHID trHid;
1617	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1618	RTGCPTR GCPtrTss = trHid.u64Base;
1619	uint32_t cbTss = trHid.u32Limit;
1620	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1621	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1622	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1623	if (SelTss & X86_SEL_MASK_OFF_RPL)
1624	{
1625	Assert(!(SelTss & X86_SEL_LDT));
1626	Assert(trHid.Attr.n.u1DescType == 0);
1627	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1628	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1629	if (!++cbTss)
1630	cbTss = UINT32_MAX;
1631	}
1632	else
1633	{
1634	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1635	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1636	cbTss = 0; /* the reset case. */
1637	}
1638	pVM->selm.s.cbGuestTss = cbTss;
1639	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1640	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1641
1642	/*
1643	* Figure out the size of what need to monitor.
1644	*/
1645	/* We're not interested in any 16-bit TSSes. */
1646	uint32_t cbMonitoredTss = cbTss;
1647	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1648	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1649	cbMonitoredTss = 0;
1650
1651	pVM->selm.s.offGuestIoBitmap = 0;
1652	bool fNoRing1Stack = true;
1653	if (cbMonitoredTss)
1654	{
1655	/*
1656	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1657	* If VME is enabled we also want to keep an eye on the interrupt
1658	* redirection bitmap.
1659	*/
1660	VBOXTSS Tss;
1661	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1662	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1663	if ( !(cr4 & X86_CR4_VME)
1664	\|\| ( RT_SUCCESS(rc)
1665	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1666	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1667	)
1668	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1669	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1670	else if (RT_SUCCESS(rc))
1671	{
1672	/*
1673	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1674	* this can be quite a large chunk. We use to skip it earlier and just hope it
1675	* was kind of static...
1676	*
1677	* Update the virtual interrupt redirection bitmap while we're here.
1678	* (It is located in the 32 bytes before TR:offIoBitmap.)
1679	*/
1680	cbMonitoredTss = Tss.offIoBitmap;
1681	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1682
1683	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1684	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1685	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1686	AssertRC(rc);
1687	/** @todo memset the bitmap on failure? */
1688	Log2(("Redirection bitmap:\n"));
1689	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1690	}
1691	else
1692	{
1693	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1694	pVM->selm.s.offGuestIoBitmap = 0;
1695	/** @todo memset the bitmap? */
1696	}
1697
1698	/*
1699	* Update the ring 0 stack selector and base address.
1700	*/
1701	if (RT_SUCCESS(rc))
1702	{
1703	# ifdef LOG_ENABLED
1704	if (LogIsEnabled())
1705	{
1706	uint32_t ssr0, espr0;
1707	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1708	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1709	{
1710	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1711	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1712	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1713	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1714	AssertMsg(ssr0 != Tss.ss0,
1715	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1716	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1717	}
1718	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1719	}
1720	# endif /* LOG_ENABLED */
1721	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1722
1723	/* Update our TSS structure for the guest's ring 1 stack */
1724	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1725	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1726
1727	# ifdef VBOX_WITH_RAW_RING1
1728	/* Update our TSS structure for the guest's ring 2 stack */
1729	if (EMIsRawRing1Enabled(pVM))
1730	{
1731	if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) \| 1))
1732	\|\| pVM->selm.s.Tss.esp2 != Tss.esp1)
1733	Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) \| 1, pVM->selm.s.Tss.esp2));
1734	selmSetRing2Stack(pVM, (Tss.ss1 & ~1) \| 2, Tss.esp1);
1735	}
1736	# endif
1737	}
1738	}
1739
1740	/*
1741	* Flush the ring-1 stack and the direct syscall dispatching if we
1742	* cannot obtain SS0:ESP0.
1743	*/
1744	if (fNoRing1Stack)
1745	{
1746	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1747	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1748
1749	/** @todo handle these dependencies better! */
1750	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1751	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1752	}
1753
1754	/*
1755	* Check for monitor changes and apply them.
1756	*/
1757	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1758	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1759	{
1760	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1761	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1762
1763	/* Release the old range first. */
1764	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1765	{
1766	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestTss, false /fHypervisor/);
1767	AssertRC(rc);
1768	}
1769
1770	/* Register the write handler if TS != 0. */
1771	if (cbMonitoredTss != 0)
1772	{
1773	# ifdef SELM_TRACK_GUEST_TSS_CHANGES
1774	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestTssWriteHandlerType,
1775	GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1776	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1777	if (RT_FAILURE(rc))
1778	{
1779	# ifdef VBOX_WITH_RAW_RING1
1780	/** @todo !HACK ALERT!
1781	* Some guest OSes (QNX) share code and the TSS on the same page;
1782	* PGMR3HandlerVirtualRegister doesn't support more than one
1783	* handler, so we kick out the PATM handler as this one is more
1784	* important. Fix this properly in PGMR3HandlerVirtualRegister?
1785	*/
1786	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1787	{
1788	LogRel(("SELMR3SyncTSS: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority TSS page monitor\n", GCPtrTss));
1789	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, GCPtrTss & PAGE_BASE_GC_MASK, false /fHypervisor/);
1790	AssertRC(rc);
1791
1792	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestTssWriteHandlerType,
1793	GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1794	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1795	if (RT_FAILURE(rc))
1796	{
1797	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1798	return rc;
1799	}
1800	}
1801	# else
1802	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1803	return rc;
1804	# endif
1805	}
1806	# endif /* SELM_TRACK_GUEST_TSS_CHANGES */
1807
1808	/* Update saved Guest TSS info. */
1809	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1810	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1811	pVM->selm.s.GCSelTss = SelTss;
1812	}
1813	else
1814	{
1815	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1816	pVM->selm.s.cbMonitoredGuestTss = 0;
1817	pVM->selm.s.GCSelTss = 0;
1818	}
1819	}
1820
1821	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1822
1823	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1824	return VINF_SUCCESS;
1825	}
1826
1827
1828	/**
1829	* Compares the Guest GDT and LDT with the shadow tables.
1830	* This is a VBOX_STRICT only function.
1831	*
1832	* @returns VBox status code.
1833	* @param pVM Pointer to the VM.
1834	*/
1835	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1836	{
1837	#ifdef VBOX_STRICT
1838	PVMCPU pVCpu = VMMGetCpu(pVM);
1839	AssertReturn(!HMIsEnabled(pVM), VERR_SELM_HM_IPE);
1840
1841	/*
1842	* Get GDTR and check for conflict.
1843	*/
1844	VBOXGDTR GDTR;
1845	CPUMGetGuestGDTR(pVCpu, &GDTR);
1846	if (GDTR.cbGdt == 0)
1847	return VINF_SUCCESS;
1848
1849	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1850	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1851
1852	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1853	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1854
1855	/*
1856	* Loop thru the GDT checking each entry.
1857	*/
1858	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1859	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1860	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1861	while (pGDTE < pGDTEEnd)
1862	{
1863	X86DESC GDTEGuest;
1864	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1865	if (RT_SUCCESS(rc))
1866	{
1867	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1868	{
1869	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1870	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1871	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1872	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1873	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1874	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1875	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1876	{
1877	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1878	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1879	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1880	}
1881	}
1882	}
1883
1884	/* Advance to the next descriptor. */
1885	GCPtrGDTEGuest += sizeof(X86DESC);
1886	pGDTE++;
1887	}
1888
1889
1890	/*
1891	* LDT?
1892	*/
1893	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1894	if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1895	return VINF_SUCCESS;
1896	Assert(!(SelLdt & X86_SEL_LDT));
1897	if (SelLdt > GDTR.cbGdt)
1898	{
1899	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1900	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1901	}
1902	X86DESC LDTDesc;
1903	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1904	if (RT_FAILURE(rc))
1905	{
1906	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1907	return rc;
1908	}
1909	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1910	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1911
1912	/*
1913	* Validate it.
1914	*/
1915	if (!cbLdt)
1916	return VINF_SUCCESS;
1917	/** @todo check what intel does about odd limits. */
1918	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1919	if ( LDTDesc.Gen.u1DescType
1920	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1921	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1922	{
1923	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1924	return VERR_SELM_INVALID_LDT;
1925	}
1926
1927	/*
1928	* Loop thru the LDT checking each entry.
1929	*/
1930	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1931	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1932	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1933	while (pLDTE < pLDTEEnd)
1934	{
1935	X86DESC LDTEGuest;
1936	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1937	if (RT_SUCCESS(rc))
1938	{
1939	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1940	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1941	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1942	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1943	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1944	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1945	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1946	{
1947	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1948	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1949	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1950	}
1951	}
1952
1953	/* Advance to the next descriptor. */
1954	GCPtrLDTEGuest += sizeof(X86DESC);
1955	pLDTE++;
1956	}
1957
1958	#else /* !VBOX_STRICT */
1959	NOREF(pVM);
1960	#endif /* !VBOX_STRICT */
1961
1962	return VINF_SUCCESS;
1963	}
1964
1965
1966	/**
1967	* Validates the RawR0 TSS values against the one in the Guest TSS.
1968	*
1969	* @returns true if it matches.
1970	* @returns false and assertions on mismatch..
1971	* @param pVM Pointer to the VM.
1972	*/
1973	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1974	{
1975	#if defined(VBOX_STRICT) && defined(SELM_TRACK_GUEST_TSS_CHANGES)
1976	PVMCPU pVCpu = VMMGetCpu(pVM);
1977
1978	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1979	return true;
1980
1981	/*
1982	* Get TR and extract the basic info.
1983	*/
1984	CPUMSELREGHID trHid;
1985	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1986	RTGCPTR GCPtrTss = trHid.u64Base;
1987	uint32_t cbTss = trHid.u32Limit;
1988	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1989	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1990	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1991	if (SelTss & X86_SEL_MASK_OFF_RPL)
1992	{
1993	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1994	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1995	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1996	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1997	false);
1998	if (!++cbTss)
1999	cbTss = UINT32_MAX;
2000	}
2001	else
2002	{
2003	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
2004	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
2005	false);
2006	cbTss = 0; /* the reset case. */
2007	}
2008	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
2009	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2010	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
2011	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
2012	false);
2013	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
2014	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
2015	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
2016	false);
2017	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
2018	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
2019	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
2020	false);
2021
2022
2023	/*
2024	* Figure out the size of what need to monitor.
2025	*/
2026	/* We're not interested in any 16-bit TSSes. */
2027	uint32_t cbMonitoredTss = cbTss;
2028	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
2029	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2030	cbMonitoredTss = 0;
2031	if (cbMonitoredTss)
2032	{
2033	VBOXTSS Tss;
2034	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
2035	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
2036	AssertReturn( rc == VINF_SUCCESS
2037	/* Happens early in XP boot during page table switching. */
2038	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
2039	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
2040	false);
2041	if ( !(cr4 & X86_CR4_VME)
2042	\|\| ( RT_SUCCESS(rc)
2043	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
2044	&& Tss.offIoBitmap > cbTss)
2045	)
2046	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
2047	else if (RT_SUCCESS(rc))
2048	{
2049	cbMonitoredTss = Tss.offIoBitmap;
2050	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
2051	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
2052	false);
2053
2054	/* check the bitmap */
2055	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
2056	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
2057	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
2058	AssertRCReturn(rc, false);
2059	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
2060	("offIoBitmap=%#x cbTss=%#x\n"
2061	" Guest: %.32Rhxs\n"
2062	"Shadow: %.32Rhxs\n",
2063	Tss.offIoBitmap, cbTss,
2064	&Tss.IntRedirBitmap[0],
2065	&pVM->selm.s.Tss.IntRedirBitmap[0]),
2066	false);
2067	}
2068	else
2069	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
2070
2071	/*
2072	* Check SS0 and ESP0.
2073	*/
2074	if ( !pVM->selm.s.fSyncTSSRing0Stack
2075	&& RT_SUCCESS(rc))
2076	{
2077	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
2078	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
2079	{
2080	RTGCPHYS GCPhys;
2081	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
2082	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
2083	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
2084	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
2085	return false;
2086	}
2087	}
2088	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2089	}
2090	else
2091	{
2092	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
2093	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
2094	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2095	}
2096
2097
2098
2099	return true;
2100
2101	#else /* !VBOX_STRICT */
2102	NOREF(pVM);
2103	return true;
2104	#endif /* !VBOX_STRICT */
2105	}
2106
2107
2108	# ifdef VBOX_WITH_SAFE_STR
2109	/**
2110	* Validates the RawR0 TR shadow GDT entry.
2111	*
2112	* @returns true if it matches.
2113	* @returns false and assertions on mismatch..
2114	* @param pVM Pointer to the VM.
2115	*/
2116	VMMR3DECL(bool) SELMR3CheckShadowTR(PVM pVM)
2117	{
2118	# ifdef VBOX_STRICT
2119	PX86DESC paGdt = pVM->selm.s.paGdtR3;
2120
2121	/*
2122	* TSS descriptor
2123	*/
2124	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
2125	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
2126
2127	if ( pDesc->Gen.u16BaseLow != RT_LOWORD(RCPtrTSS)
2128	\|\| pDesc->Gen.u8BaseHigh1 != RT_BYTE3(RCPtrTSS)
2129	\|\| pDesc->Gen.u8BaseHigh2 != RT_BYTE4(RCPtrTSS)
2130	\|\| pDesc->Gen.u16LimitLow != sizeof(VBOXTSS) - 1
2131	\|\| pDesc->Gen.u4LimitHigh != 0
2132	\|\| (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL && pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2133	\|\| pDesc->Gen.u1DescType != 0 /* system */
2134	\|\| pDesc->Gen.u2Dpl != 0 /* supervisor */
2135	\|\| pDesc->Gen.u1Present != 1
2136	\|\| pDesc->Gen.u1Available != 0
2137	\|\| pDesc->Gen.u1Long != 0
2138	\|\| pDesc->Gen.u1DefBig != 0
2139	\|\| pDesc->Gen.u1Granularity != 0 /* byte limit */
2140	)
2141	{
2142	AssertFailed();
2143	return false;
2144	}
2145	# endif
2146	return true;
2147	}
2148	# endif /* VBOX_WITH_SAFE_STR */
2149
2150	#endif /* VBOX_WITH_RAW_MODE */
2151
2152	/**
2153	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2154	*
2155	* See SELMR3GetSelectorInfo for details.
2156	*
2157	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2158	*
2159	* @param pVCpu Pointer to the VMCPU.
2160	* @param Sel The selector to get info about.
2161	* @param pSelInfo Where to store the information.
2162	*/
2163	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2164	{
2165	/*
2166	* Read it from the guest descriptor table.
2167	*/
2168	/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2169	X86DESC64 Desc;
2170	RTGCPTR GCPtrDesc;
2171	if (!(Sel & X86_SEL_LDT))
2172	{
2173	/* GDT */
2174	VBOXGDTR Gdtr;
2175	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2176	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2177	return VERR_INVALID_SELECTOR;
2178	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2179	}
2180	else
2181	{
2182	/* LDT */
2183	uint64_t GCPtrBase;
2184	uint32_t cbLimit;
2185	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2186	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2187	return VERR_INVALID_SELECTOR;
2188
2189	/* calc the descriptor location. */
2190	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2191	}
2192
2193	/* read the descriptor. */
2194	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2195	if (RT_FAILURE(rc))
2196	{
2197	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2198	if (RT_FAILURE(rc))
2199	return rc;
2200	Desc.au64[1] = 0;
2201	}
2202
2203	/*
2204	* Extract the base and limit
2205	* (We ignore the present bit here, which is probably a bit silly...)
2206	*/
2207	pSelInfo->Sel = Sel;
2208	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2209	pSelInfo->u.Raw64 = Desc;
2210	if (Desc.Gen.u1DescType)
2211	{
2212	/*
2213	* 64-bit code selectors are wide open, it's not possible to detect
2214	* 64-bit data or stack selectors without also dragging in assumptions
2215	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2216	* the selinfo user needs to deal with this in the context the info is
2217	* used unfortunately.
2218	*/
2219	if ( Desc.Gen.u1Long
2220	&& !Desc.Gen.u1DefBig
2221	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2222	{
2223	/* Note! We ignore the segment limit hacks that was added by AMD. */
2224	pSelInfo->GCPtrBase = 0;
2225	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2226	}
2227	else
2228	{
2229	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2230	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2231	}
2232	pSelInfo->SelGate = 0;
2233	}
2234	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2235	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2236	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2237	{
2238	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2239	in the AMD manual here as a simplification. */
2240	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2241	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2242	pSelInfo->SelGate = 0;
2243	}
2244	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2245	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2246	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2247	{
2248	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2249	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2250	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2251	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2252	pSelInfo->SelGate = Desc.Gate.u16Sel;
2253	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2254	}
2255	else
2256	{
2257	pSelInfo->cbLimit = 0;
2258	pSelInfo->GCPtrBase = 0;
2259	pSelInfo->SelGate = 0;
2260	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2261	}
2262	if (!Desc.Gen.u1Present)
2263	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2264
2265	return VINF_SUCCESS;
2266	}
2267
2268
2269	/**
2270	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2271	* interprets a legacy descriptor table entry and fills in the selector info
2272	* structure from it.
2273	*
2274	* @param pSelInfo Where to store the selector info. Only the fFlags and
2275	* Sel members have been initialized.
2276	* @param pDesc The legacy descriptor to parse.
2277	*/
2278	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2279	{
2280	pSelInfo->u.Raw64.au64[1] = 0;
2281	pSelInfo->u.Raw = *pDesc;
2282	if ( pDesc->Gen.u1DescType
2283	\|\| !(pDesc->Gen.u4Type & 4))
2284	{
2285	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2286	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2287	pSelInfo->SelGate = 0;
2288	}
2289	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2290	{
2291	pSelInfo->cbLimit = 0;
2292	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2293	pSelInfo->GCPtrBase = 0;
2294	else
2295	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2296	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2297	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2298	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2299	}
2300	else
2301	{
2302	pSelInfo->cbLimit = 0;
2303	pSelInfo->GCPtrBase = 0;
2304	pSelInfo->SelGate = 0;
2305	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2306	}
2307	if (!pDesc->Gen.u1Present)
2308	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2309	}
2310
2311
2312	/**
2313	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2314	*
2315	* See SELMR3GetSelectorInfo for details.
2316	*
2317	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2318	*
2319	* @param pVM Pointer to the VM.
2320	* @param pVCpu Pointer to the VMCPU.
2321	* @param Sel The selector to get info about.
2322	* @param pSelInfo Where to store the information.
2323	*/
2324	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2325	{
2326	/*
2327	* Read the descriptor entry
2328	*/
2329	pSelInfo->fFlags = 0;
2330	X86DESC Desc;
2331	if ( !(Sel & X86_SEL_LDT)
2332	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2333	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2334	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2335	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2336	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2337	)
2338	{
2339	/*
2340	* Hypervisor descriptor.
2341	*/
2342	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2343	if (CPUMIsGuestInProtectedMode(pVCpu))
2344	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2345	else
2346	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2347
2348	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2349	}
2350	else if (CPUMIsGuestInProtectedMode(pVCpu))
2351	{
2352	/*
2353	* Read it from the guest descriptor table.
2354	*/
2355	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2356
2357	RTGCPTR GCPtrDesc;
2358	if (!(Sel & X86_SEL_LDT))
2359	{
2360	/* GDT */
2361	VBOXGDTR Gdtr;
2362	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2363	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2364	return VERR_INVALID_SELECTOR;
2365	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2366	}
2367	else
2368	{
2369	/* LDT */
2370	uint64_t GCPtrBase;
2371	uint32_t cbLimit;
2372	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2373	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2374	return VERR_INVALID_SELECTOR;
2375
2376	/* calc the descriptor location. */
2377	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2378	}
2379
2380	/* read the descriptor. */
2381	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2382	if (RT_FAILURE(rc))
2383	return rc;
2384	}
2385	else
2386	{
2387	/*
2388	* We're in real mode.
2389	*/
2390	pSelInfo->Sel = Sel;
2391	pSelInfo->GCPtrBase = Sel << 4;
2392	pSelInfo->cbLimit = 0xffff;
2393	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2394	pSelInfo->u.Raw64.au64[0] = 0;
2395	pSelInfo->u.Raw64.au64[1] = 0;
2396	pSelInfo->SelGate = 0;
2397	return VINF_SUCCESS;
2398	}
2399
2400	/*
2401	* Extract the base and limit or sel:offset for gates.
2402	*/
2403	pSelInfo->Sel = Sel;
2404	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2405
2406	return VINF_SUCCESS;
2407	}
2408
2409
2410	/**
2411	* Gets information about a selector.
2412	*
2413	* Intended for the debugger mostly and will prefer the guest descriptor tables
2414	* over the shadow ones.
2415	*
2416	* @retval VINF_SUCCESS on success.
2417	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2418	* descriptor table.
2419	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2420	* is not returned if the selector itself isn't present, you have to
2421	* check that for yourself (see DBGFSELINFO::fFlags).
2422	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2423	* pagetable or page backing the selector table wasn't present.
2424	* @returns Other VBox status code on other errors.
2425	*
2426	* @param pVM Pointer to the VM.
2427	* @param pVCpu Pointer to the VMCPU.
2428	* @param Sel The selector to get info about.
2429	* @param pSelInfo Where to store the information.
2430	*/
2431	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2432	{
2433	AssertPtr(pSelInfo);
2434	if (CPUMIsGuestInLongMode(pVCpu))
2435	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2436	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2437	}
2438
2439
2440	/**
2441	* Gets information about a selector from the shadow tables.
2442	*
2443	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2444	* requires that the caller ensures that the shadow tables are up to date.
2445	*
2446	* @retval VINF_SUCCESS on success.
2447	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2448	* descriptor table.
2449	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2450	* is not returned if the selector itself isn't present, you have to
2451	* check that for yourself (see DBGFSELINFO::fFlags).
2452	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2453	* pagetable or page backing the selector table wasn't present.
2454	* @returns Other VBox status code on other errors.
2455	*
2456	* @param pVM Pointer to the VM.
2457	* @param Sel The selector to get info about.
2458	* @param pSelInfo Where to store the information.
2459	*
2460	* @remarks Don't use this when in hardware assisted virtualization mode.
2461	*/
2462	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2463	{
2464	Assert(pSelInfo);
2465
2466	/*
2467	* Read the descriptor entry
2468	*/
2469	X86DESC Desc;
2470	if (!(Sel & X86_SEL_LDT))
2471	{
2472	/*
2473	* Global descriptor.
2474	*/
2475	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2476	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2477	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2478	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2479	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2480	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2481	? DBGFSELINFO_FLAGS_HYPER
2482	: 0;
2483	/** @todo check that the GDT offset is valid. */
2484	}
2485	else
2486	{
2487	/*
2488	* Local Descriptor.
2489	*/
2490	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2491	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2492	/** @todo check if the LDT page is actually available. */
2493	/** @todo check that the LDT offset is valid. */
2494	pSelInfo->fFlags = 0;
2495	}
2496	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2497	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2498	else
2499	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2500
2501	/*
2502	* Extract the base and limit or sel:offset for gates.
2503	*/
2504	pSelInfo->Sel = Sel;
2505	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2506
2507	return VINF_SUCCESS;
2508	}
2509
2510
2511	/**
2512	* Formats a descriptor.
2513	*
2514	* @param Desc Descriptor to format.
2515	* @param Sel Selector number.
2516	* @param pszOutput Output buffer.
2517	* @param cchOutput Size of output buffer.
2518	*/
2519	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2520	{
2521	/*
2522	* Make variable description string.
2523	*/
2524	static struct
2525	{
2526	unsigned cch;
2527	const char *psz;
2528	} const aTypes[32] =
2529	{
2530	#define STRENTRY(str) { sizeof(str) - 1, str }
2531	/* system */
2532	STRENTRY("Reserved0 "), /* 0x00 */
2533	STRENTRY("TSS16Avail "), /* 0x01 */
2534	STRENTRY("LDT "), /* 0x02 */
2535	STRENTRY("TSS16Busy "), /* 0x03 */
2536	STRENTRY("Call16 "), /* 0x04 */
2537	STRENTRY("Task "), /* 0x05 */
2538	STRENTRY("Int16 "), /* 0x06 */
2539	STRENTRY("Trap16 "), /* 0x07 */
2540	STRENTRY("Reserved8 "), /* 0x08 */
2541	STRENTRY("TSS32Avail "), /* 0x09 */
2542	STRENTRY("ReservedA "), /* 0x0a */
2543	STRENTRY("TSS32Busy "), /* 0x0b */
2544	STRENTRY("Call32 "), /* 0x0c */
2545	STRENTRY("ReservedD "), /* 0x0d */
2546	STRENTRY("Int32 "), /* 0x0e */
2547	STRENTRY("Trap32 "), /* 0x0f */
2548	/* non system */
2549	STRENTRY("DataRO "), /* 0x10 */
2550	STRENTRY("DataRO Accessed "), /* 0x11 */
2551	STRENTRY("DataRW "), /* 0x12 */
2552	STRENTRY("DataRW Accessed "), /* 0x13 */
2553	STRENTRY("DataDownRO "), /* 0x14 */
2554	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2555	STRENTRY("DataDownRW "), /* 0x16 */
2556	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2557	STRENTRY("CodeEO "), /* 0x18 */
2558	STRENTRY("CodeEO Accessed "), /* 0x19 */
2559	STRENTRY("CodeER "), /* 0x1a */
2560	STRENTRY("CodeER Accessed "), /* 0x1b */
2561	STRENTRY("CodeConfEO "), /* 0x1c */
2562	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2563	STRENTRY("CodeConfER "), /* 0x1e */
2564	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2565	#undef SYSENTRY
2566	};
2567	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2568	char szMsg[128];
2569	char *psz = &szMsg[0];
2570	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2571	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2572	psz += aTypes[i].cch;
2573
2574	if (Desc.Gen.u1Present)
2575	ADD_STR(psz, "Present ");
2576	else
2577	ADD_STR(psz, "Not-Present ");
2578	if (Desc.Gen.u1Granularity)
2579	ADD_STR(psz, "Page ");
2580	if (Desc.Gen.u1DefBig)
2581	ADD_STR(psz, "32-bit ");
2582	else
2583	ADD_STR(psz, "16-bit ");
2584	#undef ADD_STR
2585	*psz = '\0';
2586
2587	/*
2588	* Limit and Base and format the output.
2589	*/
2590	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2591	uint32_t u32Base = X86DESC_BASE(&Desc);
2592
2593	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2594	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2595	}
2596
2597
2598	/**
2599	* Dumps a descriptor.
2600	*
2601	* @param Desc Descriptor to dump.
2602	* @param Sel Selector number.
2603	* @param pszMsg Message to prepend the log entry with.
2604	*/
2605	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2606	{
2607	char szOutput[128];
2608	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2609	Log(("%s: %s\n", pszMsg, szOutput));
2610	NOREF(szOutput[0]);
2611	}
2612
2613
2614	/**
2615	* Display the shadow gdt.
2616	*
2617	* @param pVM Pointer to the VM.
2618	* @param pHlp The info helpers.
2619	* @param pszArgs Arguments, ignored.
2620	*/
2621	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2622	{
2623	NOREF(pszArgs);
2624	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2625	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2626	{
2627	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2628	{
2629	char szOutput[128];
2630	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2631	const char *psz = "";
2632	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2633	psz = " HyperCS";
2634	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2635	psz = " HyperDS";
2636	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2637	psz = " HyperCS64";
2638	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2639	psz = " HyperTSS";
2640	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2641	psz = " HyperTSSTrap08";
2642	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2643	}
2644	}
2645	}
2646
2647
2648	/**
2649	* Display the guest gdt.
2650	*
2651	* @param pVM Pointer to the VM.
2652	* @param pHlp The info helpers.
2653	* @param pszArgs Arguments, ignored.
2654	*/
2655	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2656	{
2657	/** @todo SMP support! */
2658	PVMCPU pVCpu = &pVM->aCpus[0];
2659
2660	VBOXGDTR GDTR;
2661	CPUMGetGuestGDTR(pVCpu, &GDTR);
2662	RTGCPTR GCPtrGDT = GDTR.pGdt;
2663	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2664
2665	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2666	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2667	{
2668	X86DESC GDTE;
2669	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2670	if (RT_SUCCESS(rc))
2671	{
2672	if (GDTE.Gen.u1Present)
2673	{
2674	char szOutput[128];
2675	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2676	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2677	}
2678	}
2679	else if (rc == VERR_PAGE_NOT_PRESENT)
2680	{
2681	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2682	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2683	}
2684	else
2685	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2686	}
2687	NOREF(pszArgs);
2688	}
2689
2690
2691	/**
2692	* Display the shadow ldt.
2693	*
2694	* @param pVM Pointer to the VM.
2695	* @param pHlp The info helpers.
2696	* @param pszArgs Arguments, ignored.
2697	*/
2698	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2699	{
2700	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2701	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2702	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2703	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2704	{
2705	if (paLDT[iLDT].Gen.u1Present)
2706	{
2707	char szOutput[128];
2708	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2709	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2710	}
2711	}
2712	NOREF(pszArgs);
2713	}
2714
2715
2716	/**
2717	* Display the guest ldt.
2718	*
2719	* @param pVM Pointer to the VM.
2720	* @param pHlp The info helpers.
2721	* @param pszArgs Arguments, ignored.
2722	*/
2723	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2724	{
2725	/** @todo SMP support! */
2726	PVMCPU pVCpu = &pVM->aCpus[0];
2727
2728	uint64_t GCPtrLdt;
2729	uint32_t cbLdt;
2730	RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2731	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2732	{
2733	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2734	return;
2735	}
2736
2737	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2738	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2739	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2740	{
2741	X86DESC LdtE;
2742	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2743	if (RT_SUCCESS(rc))
2744	{
2745	if (LdtE.Gen.u1Present)
2746	{
2747	char szOutput[128];
2748	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2749	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2750	}
2751	}
2752	else if (rc == VERR_PAGE_NOT_PRESENT)
2753	{
2754	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2755	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2756	}
2757	else
2758	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2759	}
2760	NOREF(pszArgs);
2761	}
2762
2763
2764	/**
2765	* Dumps the hypervisor GDT
2766	*
2767	* @param pVM Pointer to the VM.
2768	*/
2769	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2770	{
2771	DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2772	}
2773
2774
2775	/**
2776	* Dumps the hypervisor LDT
2777	*
2778	* @param pVM Pointer to the VM.
2779	*/
2780	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2781	{
2782	DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2783	}
2784
2785
2786	/**
2787	* Dumps the guest GDT
2788	*
2789	* @param pVM Pointer to the VM.
2790	*/
2791	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2792	{
2793	DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2794	}
2795
2796
2797	/**
2798	* Dumps the guest LDT
2799	*
2800	* @param pVM Pointer to the VM.
2801	*/
2802	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2803	{
2804	DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2805	}
2806

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 55966

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