TRPM.cpp@ 60682

Last change on this file since 60682 was 60573, checked in by vboxsync, 9 years ago
VMM/APIC: Fix INIT IPI handling, and handle callers of PDMGetInterrupt() expecting a valid vector which may not be the case with the new APIC code.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 78.5 KB

Line
1	/* $Id: TRPM.cpp 60573 2016-04-19 13:27:45Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72
73	/*********************************************************************************************************************************
74	* Header Files *
75	*********************************************************************************************************************************/
76	#define LOG_GROUP LOG_GROUP_TRPM
77	#include <VBox/vmm/trpm.h>
78	#include <VBox/vmm/cpum.h>
79	#include <VBox/vmm/selm.h>
80	#include <VBox/vmm/ssm.h>
81	#include <VBox/vmm/pdmapi.h>
82	#include <VBox/vmm/em.h>
83	#include <VBox/vmm/pgm.h>
84	#include "internal/pgm.h"
85	#include <VBox/vmm/dbgf.h>
86	#include <VBox/vmm/mm.h>
87	#include <VBox/vmm/stam.h>
88	#include <VBox/vmm/csam.h>
89	#include <VBox/vmm/patm.h>
90	#include "TRPMInternal.h"
91	#include <VBox/vmm/vm.h>
92	#include <VBox/vmm/em.h>
93	#ifdef VBOX_WITH_REM
94	# include <VBox/vmm/rem.h>
95	#endif
96	#include <VBox/vmm/hm.h>
97
98	#include <VBox/err.h>
99	#include <VBox/param.h>
100	#include <VBox/log.h>
101	#include <iprt/assert.h>
102	#include <iprt/asm.h>
103	#include <iprt/string.h>
104	#include <iprt/alloc.h>
105
106
107	/*********************************************************************************************************************************
108	* Structures and Typedefs *
109	*********************************************************************************************************************************/
110	/**
111	* Trap handler function.
112	* @todo need to specialize this as we go along.
113	*/
114	typedef enum TRPMHANDLER
115	{
116	/** Generic Interrupt handler. */
117	TRPM_HANDLER_INT = 0,
118	/** Generic Trap handler. */
119	TRPM_HANDLER_TRAP,
120	/** Trap 8 (\#DF) handler. */
121	TRPM_HANDLER_TRAP_08,
122	/** Trap 12 (\#MC) handler. */
123	TRPM_HANDLER_TRAP_12,
124	/** Max. */
125	TRPM_HANDLER_MAX
126	} TRPMHANDLER, *PTRPMHANDLER;
127
128
129	/*********************************************************************************************************************************
130	* Global Variables *
131	*********************************************************************************************************************************/
132	/** Preinitialized IDT.
133	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
134	* will use to pick the right address. The u16SegSel is always VMM CS.
135	*/
136	static VBOXIDTE_GENERIC g_aIdt[256] =
137	{
138	/* special trap handler - still, this is an interrupt gate not a trap gate... */
139	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
140	/* generic trap handler. */
141	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
142	/* special interrupt handler. */
143	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
144	/* generic interrupt handler. */
145	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
146	/* special task gate IDT entry (for critical exceptions like #DF). */
147	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
148	/* draft, fixme later when the handler is written. */
149	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
150
151	/* N - M M - T - C - D i */
152	/* o - n o - y - o - e p */
153	/* - e n - p - d - s t */
154	/* - i - e - e - c . */
155	/* - c - - - r */
156	/* ============================================================= */
157	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
158	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
159	#ifdef VBOX_WITH_NMI
160	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
161	#else
162	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
163	#endif
164	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
165	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
166	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
167	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
168	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
169	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
170	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
171	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
172	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
173	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
174	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
175	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
176	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
177	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
178	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
179	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
180	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
181	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
190	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
191	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
192	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
193	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
414	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
415	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
416	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
417	#undef IDTE_TRAP
418	#undef IDTE_TRAP_GEN
419	#undef IDTE_INT
420	#undef IDTE_INT_GEN
421	#undef IDTE_TASK
422	#undef IDTE_UNUSED
423	#undef IDTE_RESERVED
424	};
425
426
427	/** TRPM saved state version. */
428	#define TRPM_SAVED_STATE_VERSION 9
429	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
430
431
432	/*********************************************************************************************************************************
433	* Internal Functions *
434	*********************************************************************************************************************************/
435	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
436	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
437
438
439	/**
440	* Initializes the Trap Manager
441	*
442	* @returns VBox status code.
443	* @param pVM The cross context VM structure.
444	*/
445	VMMR3DECL(int) TRPMR3Init(PVM pVM)
446	{
447	LogFlow(("TRPMR3Init\n"));
448	int rc;
449
450	/*
451	* Assert sizes and alignments.
452	*/
453	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
454	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
455	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
456	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
457
458	/*
459	* Initialize members.
460	*/
461	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
462	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
463
464	for (VMCPUID i = 0; i < pVM->cCpus; i++)
465	{
466	PVMCPU pVCpu = &pVM->aCpus[i];
467
468	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
469	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
470	pVCpu->trpm.s.uActiveVector = ~0U;
471	}
472
473	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
474	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
475	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
476
477	/*
478	* Read the configuration (if any).
479	*/
480	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
481	if (pTRPMNode)
482	{
483	bool f;
484	rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
485	if (RT_SUCCESS(rc))
486	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
487	}
488
489	/* write config summary to log */
490	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
491	LogRel(("TRPM: Dropping Guest IDT Monitoring\n"));
492
493	/*
494	* Initialize the IDT.
495	* The handler addresses will be set in the TRPMR3Relocate() function.
496	*/
497	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
498	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
499
500	/*
501	* Register virtual access handlers.
502	*/
503	pVM->trpm.s.hShadowIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
504	pVM->trpm.s.hGuestIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
505	#ifdef VBOX_WITH_RAW_MODE
506	if (!HMIsEnabled(pVM))
507	{
508	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
509	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
510	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
511	NULL /pszHandlerRC/, "trpmRCShadowIDTWritePfHandler",
512	"Shadow IDT write access handler", &pVM->trpm.s.hShadowIdtWriteHandlerType);
513	AssertRCReturn(rc, rc);
514	# endif
515	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
516	NULL /pfnInvalidateR3/, trpmGuestIDTWriteHandler,
517	"trpmGuestIDTWriteHandler", "trpmRCGuestIDTWritePfHandler",
518	"Guest IDT write access handler", &pVM->trpm.s.hGuestIdtWriteHandlerType);
519	AssertRCReturn(rc, rc);
520	}
521	#endif /* VBOX_WITH_RAW_MODE */
522
523	/*
524	* Register the saved state data unit.
525	*/
526	rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
527	NULL, NULL, NULL,
528	NULL, trpmR3Save, NULL,
529	NULL, trpmR3Load, NULL);
530	if (RT_FAILURE(rc))
531	return rc;
532
533	/*
534	* Statistics.
535	*/
536	#ifdef VBOX_WITH_RAW_MODE
537	if (!HMIsEnabled(pVM))
538	{
539	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
540	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
541	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
542
543	/* traps */
544	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
545	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
546	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
547	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
548	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
549	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
550	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
551	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
552	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
553	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
554	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
555	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
556	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
557	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
558	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
559	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
560	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
561	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
562	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
563	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
564	}
565	#endif
566
567	# ifdef VBOX_WITH_STATISTICS
568	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
569	AssertRCReturn(rc, rc);
570	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
571	for (unsigned i = 0; i < 256; i++)
572	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
573	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
574
575	# ifdef VBOX_WITH_RAW_MODE
576	if (!HMIsEnabled(pVM))
577	{
578	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
579	AssertRCReturn(rc, rc);
580	pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
581	for (unsigned i = 0; i < 256; i++)
582	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
583	"Host interrupts.", "/TRPM/HostIRQs/%02x", i);
584	}
585	# endif
586	# endif
587
588	#ifdef VBOX_WITH_RAW_MODE
589	if (!HMIsEnabled(pVM))
590	{
591	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
592	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
593	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
594	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
595	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
596	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
597
598	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
599	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
600	}
601	#endif
602
603	#ifdef VBOX_WITH_RAW_MODE
604	/*
605	* Default action when entering raw mode for the first time
606	*/
607	if (!HMIsEnabled(pVM))
608	{
609	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
610	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
611	}
612	#endif
613	return 0;
614	}
615
616
617	/**
618	* Applies relocations to data and code managed by this component.
619	*
620	* This function will be called at init and whenever the VMM need
621	* to relocate itself inside the GC.
622	*
623	* @param pVM The cross context VM structure.
624	* @param offDelta Relocation delta relative to old location.
625	*/
626	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
627	{
628	#ifdef VBOX_WITH_RAW_MODE
629	if (HMIsEnabled(pVM))
630	return;
631
632	/* Only applies to raw mode which supports only 1 VCPU. */
633	PVMCPU pVCpu = &pVM->aCpus[0];
634	LogFlow(("TRPMR3Relocate\n"));
635
636	/*
637	* Get the trap handler addresses.
638	*
639	* If VMMRC.rc is screwed, so are we. We'll assert here since it elsewise
640	* would make init order impossible if we should assert the presence of these
641	* exports in TRPMR3Init().
642	*/
643	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
644	RT_ZERO(aRCPtrs);
645	int rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
646	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
647
648	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
649	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMRC.rc!\n"));
650
651	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
652	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMRC.rc!\n"));
653
654	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
655	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMRC.rc!\n"));
656
657	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
658
659	/*
660	* Iterate the idt and set the addresses.
661	*/
662	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
663	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
664	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
665	{
666	if ( pIdte->Gen.u1Present
667	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
668	)
669	{
670	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
671	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
672	switch (pIdteTemplate->u16OffsetLow)
673	{
674	/*
675	* Generic handlers have different entrypoints for each possible
676	* vector number. These entrypoints makes a sort of an array with
677	* 8 byte entries where the vector number is the index.
678	* See TRPMGCHandlersA.asm for details.
679	*/
680	case TRPM_HANDLER_INT:
681	case TRPM_HANDLER_TRAP:
682	Offset += i * 8;
683	break;
684	case TRPM_HANDLER_TRAP_12:
685	break;
686	case TRPM_HANDLER_TRAP_08:
687	/* Handle #DF Task Gate in special way. */
688	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
689	pIdte->Gen.u16OffsetLow = 0;
690	pIdte->Gen.u16OffsetHigh = 0;
691	SELMSetTrap8EIP(pVM, Offset);
692	continue;
693	}
694	/* (non-task gates only ) */
695	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
696	pIdte->Gen.u16OffsetHigh = Offset >> 16;
697	pIdte->Gen.u16SegSel = SelCS;
698	}
699	}
700
701	/*
702	* Update IDTR (limit is including!).
703	*/
704	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
705
706	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
707	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
708	{
709	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.pvMonShwIdtRC, true /fHypervisor/);
710	AssertRC(rc);
711	}
712	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
713	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hShadowIdtWriteHandlerType,
714	pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
715	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
716	AssertRC(rc);
717	# endif
718
719	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
720	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
721	{
722	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
723	{
724	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
725	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
726	}
727
728	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
729	{
730	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
731	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
732
733	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
734	pHandler += offDelta;
735
736	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
737	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
738	}
739	}
740
741	# ifdef VBOX_WITH_STATISTICS
742	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
743	pVM->trpm.s.paStatHostIrqRC += offDelta;
744	# endif
745	#endif /* VBOX_WITH_RAW_MODE */
746	}
747
748
749	/**
750	* Terminates the Trap Manager
751	*
752	* @returns VBox status code.
753	* @param pVM The cross context VM structure.
754	*/
755	VMMR3DECL(int) TRPMR3Term(PVM pVM)
756	{
757	NOREF(pVM);
758	return VINF_SUCCESS;
759	}
760
761
762	/**
763	* Resets a virtual CPU.
764	*
765	* Used by TRPMR3Reset and CPU hot plugging.
766	*
767	* @param pVCpu The cross context virtual CPU structure.
768	*/
769	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
770	{
771	pVCpu->trpm.s.uActiveVector = ~0U;
772	}
773
774
775	/**
776	* The VM is being reset.
777	*
778	* For the TRPM component this means that any IDT write monitors
779	* needs to be removed, any pending trap cleared, and the IDT reset.
780	*
781	* @param pVM The cross context VM structure.
782	*/
783	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
784	{
785	/*
786	* Deregister any virtual handlers.
787	*/
788	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
789	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
790	{
791	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
792	{
793	int rc = PGMHandlerVirtualDeregister(pVM, VMMGetCpu(pVM), pVM->trpm.s.GuestIdtr.pIdt, false /fHypervisor/);
794	AssertRC(rc);
795	}
796	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
797	}
798	pVM->trpm.s.GuestIdtr.cbIdt = 0;
799	#endif
800
801	/*
802	* Reinitialize other members calling the relocator to get things right.
803	*/
804	for (VMCPUID i = 0; i < pVM->cCpus; i++)
805	TRPMR3ResetCpu(&pVM->aCpus[i]);
806	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
807	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
808	TRPMR3Relocate(pVM, 0);
809
810	#ifdef VBOX_WITH_RAW_MODE
811	/*
812	* Default action when entering raw mode for the first time
813	*/
814	if (!HMIsEnabled(pVM))
815	{
816	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
817	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
818	}
819	#endif
820	}
821
822
823	# ifdef VBOX_WITH_RAW_MODE
824	/**
825	* Resolve a builtin RC symbol.
826	*
827	* Called by PDM when loading or relocating RC modules.
828	*
829	* @returns VBox status
830	* @param pVM The cross context VM structure.
831	* @param pszSymbol Symbol to resolv
832	* @param pRCPtrValue Where to store the symbol value.
833	*
834	* @remark This has to work before VMMR3Relocate() is called.
835	*/
836	VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
837	{
838	if (!strcmp(pszSymbol, "g_TRPM"))
839	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
840	else if (!strcmp(pszSymbol, "g_TRPMCPU"))
841	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
842	else if (!strcmp(pszSymbol, "g_trpmGuestCtx"))
843	{
844	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
845	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
846	}
847	else if (!strcmp(pszSymbol, "g_trpmHyperCtx"))
848	{
849	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
850	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
851	}
852	else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
853	{
854	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
855	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
856	}
857	else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
858	{
859	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
860	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
861	}
862	else
863	return VERR_SYMBOL_NOT_FOUND;
864	return VINF_SUCCESS;
865	}
866	#endif /* VBOX_WITH_RAW_MODE */
867
868
869	/**
870	* Execute state save operation.
871	*
872	* @returns VBox status code.
873	* @param pVM The cross context VM structure.
874	* @param pSSM SSM operation handle.
875	*/
876	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
877	{
878	PTRPM pTrpm = &pVM->trpm.s;
879	LogFlow(("trpmR3Save:\n"));
880
881	/*
882	* Active and saved traps.
883	*/
884	for (VMCPUID i = 0; i < pVM->cCpus; i++)
885	{
886	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
887	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
888	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
889	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
890	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
891	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
892	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
893	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
894	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
895	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
896	}
897	SSMR3PutBool(pSSM, HMIsEnabled(pVM));
898	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
899	SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT), 0));
900	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
901	SSMR3PutU32(pSSM, ~0); /* separator. */
902
903	/*
904	* Save any trampoline gates.
905	*/
906	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
907	{
908	if (pTrpm->aGuestTrapHandler[iTrap])
909	{
910	SSMR3PutU32(pSSM, iTrap);
911	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
912	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
913	}
914	}
915
916	return SSMR3PutU32(pSSM, ~0); /* terminator */
917	}
918
919
920	/**
921	* Execute state load operation.
922	*
923	* @returns VBox status code.
924	* @param pVM The cross context VM structure.
925	* @param pSSM SSM operation handle.
926	* @param uVersion Data layout version.
927	* @param uPass The data pass.
928	*/
929	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
930	{
931	LogFlow(("trpmR3Load:\n"));
932	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
933
934	/*
935	* Validate version.
936	*/
937	if ( uVersion != TRPM_SAVED_STATE_VERSION
938	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
939	{
940	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
941	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
942	}
943
944	/*
945	* Call the reset function to kick out any handled gates and other potential trouble.
946	*/
947	TRPMR3Reset(pVM);
948
949	/*
950	* Active and saved traps.
951	*/
952	PTRPM pTrpm = &pVM->trpm.s;
953
954	if (uVersion == TRPM_SAVED_STATE_VERSION)
955	{
956	for (VMCPUID i = 0; i < pVM->cCpus; i++)
957	{
958	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
959	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
960	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
961	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
962	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
963	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
964	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
965	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
966	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
967	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
968	}
969
970	bool fIgnored;
971	SSMR3GetBool(pSSM, &fIgnored);
972	}
973	else
974	{
975	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
976	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
977	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
978	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
979	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
980	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
981	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
982	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
983	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
984	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
985
986	RTGCUINT fIgnored;
987	SSMR3GetGCUInt(pSSM, &fIgnored);
988	}
989
990	RTUINT fSyncIDT;
991	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
992	if (RT_FAILURE(rc))
993	return rc;
994	if (fSyncIDT & ~1)
995	{
996	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
997	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
998	}
999	#ifdef VBOX_WITH_RAW_MODE
1000	if (fSyncIDT)
1001	{
1002	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
1003	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1004	}
1005	/* else: cleared by reset call above. */
1006	#endif
1007
1008	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
1009
1010	/* check the separator */
1011	uint32_t u32Sep;
1012	rc = SSMR3GetU32(pSSM, &u32Sep);
1013	if (RT_FAILURE(rc))
1014	return rc;
1015	if (u32Sep != (uint32_t)~0)
1016	{
1017	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1018	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1019	}
1020
1021	/*
1022	* Restore any trampoline gates.
1023	*/
1024	for (;;)
1025	{
1026	/* gate number / terminator */
1027	uint32_t iTrap;
1028	rc = SSMR3GetU32(pSSM, &iTrap);
1029	if (RT_FAILURE(rc))
1030	return rc;
1031	if (iTrap == (uint32_t)~0)
1032	break;
1033	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
1034	\|\| pTrpm->aGuestTrapHandler[iTrap])
1035	{
1036	AssertMsgFailed(("iTrap=%#x\n", iTrap));
1037	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1038	}
1039
1040	/* restore the IDT entry. */
1041	RTGCPTR GCPtrHandler;
1042	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1043	VBOXIDTE Idte;
1044	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1045	if (RT_FAILURE(rc))
1046	return rc;
1047	Assert(GCPtrHandler);
1048	pTrpm->aIdt[iTrap] = Idte;
1049	}
1050
1051	return VINF_SUCCESS;
1052	}
1053
1054	#ifdef VBOX_WITH_RAW_MODE
1055
1056	/**
1057	* Check if gate handlers were updated
1058	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1059	*
1060	* @returns VBox status code.
1061	* @param pVM The cross context VM structure.
1062	* @param pVCpu The cross context virtual CPU structure.
1063	*/
1064	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1065	{
1066	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1067	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1068	int rc;
1069
1070	AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1071
1072	if (fRawRing0 && CSAMIsEnabled(pVM))
1073	{
1074	/* Clear all handlers */
1075	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1076	/** @todo inefficient, but simple */
1077	for (unsigned iGate = 0; iGate < 256; iGate++)
1078	trpmClearGuestTrapHandler(pVM, iGate);
1079
1080	/* Scan them all (only the first time) */
1081	CSAMR3CheckGates(pVM, 0, 256);
1082	}
1083
1084	/*
1085	* Get the IDTR.
1086	*/
1087	VBOXIDTR IDTR;
1088	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1089	if (!IDTR.cbIdt)
1090	{
1091	Log(("No IDT entries...\n"));
1092	return DBGFSTOP(pVM);
1093	}
1094
1095	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1096	/*
1097	* Check if Guest's IDTR has changed.
1098	*/
1099	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1100	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1101	{
1102	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1103	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1104	{
1105	/*
1106	* [Re]Register write virtual handler for guest's IDT.
1107	*/
1108	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1109	{
1110	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.GuestIdtr.pIdt, false /fHypervisor/);
1111	AssertRCReturn(rc, rc);
1112	}
1113	/* limit is including */
1114	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1115	IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1116	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1117
1118	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1119	{
1120	/* Could be a conflict with CSAM */
1121	CSAMR3RemovePage(pVM, IDTR.pIdt);
1122	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1123	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1124
1125	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1126	IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1127	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1128	}
1129
1130	AssertRCReturn(rc, rc);
1131	}
1132
1133	/* Update saved Guest IDTR. */
1134	pVM->trpm.s.GuestIdtr = IDTR;
1135	}
1136	# endif
1137
1138	/*
1139	* Sync the interrupt gate.
1140	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1141	*/
1142	X86DESC Idte3;
1143	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1144	if (RT_FAILURE(rc))
1145	{
1146	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1147	return DBGFSTOP(pVM);
1148	}
1149	AssertRCReturn(rc, rc);
1150	if (fRawRing0)
1151	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1152	else
1153	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1154
1155	/*
1156	* Clear the FF and we're done.
1157	*/
1158	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1159	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1160	return VINF_SUCCESS;
1161	}
1162
1163
1164	/**
1165	* Clear passthrough interrupt gate handler (reset to default handler)
1166	*
1167	* @returns VBox status code.
1168	* @param pVM The cross context VM structure.
1169	* @param iTrap Trap/interrupt gate number.
1170	*/
1171	int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1172	{
1173	/* Only applies to raw mode which supports only 1 VCPU. */
1174	PVMCPU pVCpu = &pVM->aCpus[0];
1175	Assert(!HMIsEnabled(pVM));
1176
1177	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1178	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1179	int rc;
1180
1181	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1182
1183	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1184	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
1185
1186	if ( iTrap < TRPM_HANDLER_INT_BASE
1187	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1188	{
1189	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1190	return VERR_INVALID_PARAMETER;
1191	}
1192	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1193
1194	/* Unmark it for relocation purposes. */
1195	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1196
1197	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1198	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1199	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1200	if (pIdte->Gen.u1Present)
1201	{
1202	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1203	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1204	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1205
1206	/*
1207	* Generic handlers have different entrypoints for each possible
1208	* vector number. These entrypoints make a sort of an array with
1209	* 8 byte entries where the vector number is the index.
1210	* See TRPMGCHandlersA.asm for details.
1211	*/
1212	Offset += iTrap * 8;
1213
1214	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1215	{
1216	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1217	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1218	pIdte->Gen.u16SegSel = SelCS;
1219	}
1220	}
1221
1222	return VINF_SUCCESS;
1223	}
1224
1225
1226	/**
1227	* Check if address is a gate handler (interrupt or trap).
1228	*
1229	* @returns gate nr or ~0 is not found
1230	*
1231	* @param pVM The cross context VM structure.
1232	* @param GCPtr GC address to check.
1233	*/
1234	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1235	{
1236	AssertReturn(!HMIsEnabled(pVM), ~0U);
1237
1238	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1239	{
1240	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1241	return iTrap;
1242
1243	/* redundant */
1244	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1245	{
1246	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1247	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1248
1249	if (pHandler == GCPtr)
1250	return iTrap;
1251	}
1252	}
1253	return ~0;
1254	}
1255
1256
1257	/**
1258	* Get guest trap/interrupt gate handler
1259	*
1260	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1261	* @param pVM The cross context VM structure.
1262	* @param iTrap Interrupt/trap number.
1263	*/
1264	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1265	{
1266	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1267	AssertReturn(!HMIsEnabled(pVM), TRPM_INVALID_HANDLER);
1268
1269	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1270	}
1271
1272
1273	/**
1274	* Set guest trap/interrupt gate handler
1275	* Used for setting up trap gates used for kernel calls.
1276	*
1277	* @returns VBox status code.
1278	* @param pVM The cross context VM structure.
1279	* @param iTrap Interrupt/trap number.
1280	* @param pHandler GC handler pointer
1281	*/
1282	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1283	{
1284	/* Only valid in raw mode which implies 1 VCPU */
1285	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1286	AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1287	PVMCPU pVCpu = &pVM->aCpus[0];
1288
1289	/*
1290	* Validate.
1291	*/
1292	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1293	{
1294	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1295	return VERR_INVALID_PARAMETER;
1296	}
1297
1298	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1299
1300	uint16_t cbIDT;
1301	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1302	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1303	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1304
1305	if (pHandler == TRPM_INVALID_HANDLER)
1306	{
1307	/* clear trap handler */
1308	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1309	return trpmClearGuestTrapHandler(pVM, iTrap);
1310	}
1311
1312	/*
1313	* Read the guest IDT entry.
1314	*/
1315	VBOXIDTE GuestIdte;
1316	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1317	if (RT_FAILURE(rc))
1318	{
1319	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1320	return rc;
1321	}
1322
1323	if ( EMIsRawRing0Enabled(pVM)
1324	&& !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1325	{
1326	/*
1327	* Only replace handlers for which we are 100% certain there won't be
1328	* any host interrupts.
1329	*
1330	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1331	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1332	*
1333	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1334	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1335	* and will therefor never assign hardware interrupts to 0x80.
1336	*
1337	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1338	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1339	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1340	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1341	* @bugref{3604}.
1342	*
1343	* PORTME - Check if your host keeps any of these gates free from hw ints.
1344	*
1345	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1346	*/
1347	/** @todo handle those dependencies better! */
1348	/** @todo Solve this in a proper manner. see @bugref{1186} */
1349	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1350	if (iTrap == 0x2E)
1351	#elif defined(RT_OS_LINUX)
1352	if (iTrap == 0x80)
1353	#else
1354	if (0)
1355	#endif
1356	{
1357	if ( GuestIdte.Gen.u1Present
1358	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1359	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1360	&& GuestIdte.Gen.u2DPL == 3)
1361	{
1362	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1363
1364	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1365	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1366	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1367	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1368	*pIdte = GuestIdte;
1369
1370	/* Mark it for relocation purposes. */
1371	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1372
1373	/* Also store it in our guest trap array. */
1374	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1375
1376	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1377	return VINF_SUCCESS;
1378	}
1379	/* ok, let's try to install a trampoline handler then. */
1380	}
1381	}
1382
1383	if ( GuestIdte.Gen.u1Present
1384	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1385	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1386	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1387	{
1388	/*
1389	* Save handler which can be used for a trampoline call inside the GC
1390	*/
1391	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1392	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1393	return VINF_SUCCESS;
1394	}
1395	return VERR_INVALID_PARAMETER;
1396	}
1397
1398
1399	/**
1400	* Check if address is a gate handler (interrupt/trap/task/anything).
1401	*
1402	* @returns True is gate handler, false if not.
1403	*
1404	* @param pVM The cross context VM structure.
1405	* @param GCPtr GC address to check.
1406	*/
1407	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1408	{
1409	/* Only valid in raw mode which implies 1 VCPU */
1410	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1411	PVMCPU pVCpu = &pVM->aCpus[0];
1412
1413	/*
1414	* Read IDTR and calc last entry.
1415	*/
1416	uint16_t cbIDT;
1417	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1418	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1419	if (!cEntries)
1420	return false;
1421	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1422
1423	/*
1424	* Outer loop: iterate pages.
1425	*/
1426	while (GCPtrIDTE <= GCPtrIDTELast)
1427	{
1428	/*
1429	* Convert this page to a HC address.
1430	* (This function checks for not-present pages.)
1431	*/
1432	PCVBOXIDTE pIDTE;
1433	PGMPAGEMAPLOCK Lock;
1434	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1435	if (RT_SUCCESS(rc))
1436	{
1437	/*
1438	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1439	* N.B. Member of the Flat Earth Society...
1440	*/
1441	while (GCPtrIDTE <= GCPtrIDTELast)
1442	{
1443	if (pIDTE->Gen.u1Present)
1444	{
1445	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1446	if (GCPtr == GCPtrHandler)
1447	{
1448	PGMPhysReleasePageMappingLock(pVM, &Lock);
1449	return true;
1450	}
1451	}
1452
1453	/* next entry */
1454	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1455	{
1456	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1457	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1458	GCPtrIDTE += sizeof(VBOXIDTE);
1459	break;
1460	}
1461	GCPtrIDTE += sizeof(VBOXIDTE);
1462	pIDTE++;
1463	}
1464	PGMPhysReleasePageMappingLock(pVM, &Lock);
1465	}
1466	else
1467	{
1468	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1469	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1470	return false;
1471	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1472	}
1473	}
1474	return false;
1475	}
1476
1477	#endif /* VBOX_WITH_RAW_MODE */
1478
1479	/**
1480	* Inject event (such as external irq or trap)
1481	*
1482	* @returns VBox status code.
1483	* @param pVM The cross context VM structure.
1484	* @param pVCpu The cross context virtual CPU structure.
1485	* @param enmEvent Trpm event type
1486	*/
1487	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1488	{
1489	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1490	#ifdef VBOX_WITH_RAW_MODE
1491	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1492	#endif
1493	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1494
1495	/* Currently only useful for external hardware interrupts. */
1496	Assert(enmEvent == TRPM_HARDWARE_INT);
1497
1498	if ( !EMIsSupervisorCodeRecompiled(pVM)
1499	#ifdef VBOX_WITH_REM
1500	&& REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ
1501	#endif
1502	)
1503	{
1504	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1505
1506	# ifdef LOG_ENABLED
1507	DBGFR3_INFO_LOG(pVM, "cpumguest", "TRPMInject");
1508	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1509	# endif
1510
1511	uint8_t u8Interrupt;
1512	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1513	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1514	if (RT_SUCCESS(rc))
1515	{
1516	# ifndef IEM_VERIFICATION_MODE
1517	if (HMIsEnabled(pVM))
1518	# endif
1519	{
1520	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1521	AssertRC(rc);
1522	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1523	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1524	}
1525	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1526	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1527	{
1528	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1529	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1530	}
1531
1532	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1533	{
1534	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1535	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1536	if (rc == VINF_SUCCESS)
1537	{
1538	/* There's a handler -> let's execute it in raw mode */
1539	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1540	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1541	{
1542	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1543
1544	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1545	return VINF_EM_RESCHEDULE_RAW;
1546	}
1547	}
1548	}
1549	else
1550	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1551	# ifdef VBOX_WITH_REM
1552	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1553	# endif
1554	}
1555	else
1556	{
1557	#ifndef VBOX_WITH_NEW_APIC
1558	AssertRC(rc);
1559	#endif
1560	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1561	}
1562	#else /* !TRPM_FORWARD_TRAPS_IN_GC */
1563	uint8_t u8Interrupt;
1564	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1565	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1566	if (RT_SUCCESS(rc))
1567	{
1568	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1569	AssertRC(rc);
1570	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1571	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1572	}
1573	#endif /* !TRPM_FORWARD_TRAPS_IN_GC */
1574	}
1575	/** @todo check if it's safe to translate the patch address to the original guest address.
1576	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1577	*/
1578	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1579
1580	/* Fall back to the recompiler */
1581	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1582	}
1583

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source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 60682

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