TRPM.cpp@ 41783

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Line
1	/* $Id: TRPM.cpp 41783 2012-06-16 19:24:15Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72	/*******************************************************************************
73	* Header Files *
74	*******************************************************************************/
75	#define LOG_GROUP LOG_GROUP_TRPM
76	#include <VBox/vmm/trpm.h>
77	#include <VBox/vmm/cpum.h>
78	#include <VBox/vmm/selm.h>
79	#include <VBox/vmm/ssm.h>
80	#include <VBox/vmm/pdmapi.h>
81	#include <VBox/vmm/em.h>
82	#include <VBox/vmm/pgm.h>
83	#include "internal/pgm.h"
84	#include <VBox/vmm/dbgf.h>
85	#include <VBox/vmm/mm.h>
86	#include <VBox/vmm/stam.h>
87	#include <VBox/vmm/csam.h>
88	#include <VBox/vmm/patm.h>
89	#include "TRPMInternal.h"
90	#include <VBox/vmm/vm.h>
91	#include <VBox/vmm/em.h>
92	#ifdef VBOX_WITH_REM
93	# include <VBox/vmm/rem.h>
94	#endif
95	#include <VBox/vmm/hwaccm.h>
96
97	#include <VBox/err.h>
98	#include <VBox/param.h>
99	#include <VBox/log.h>
100	#include <iprt/assert.h>
101	#include <iprt/asm.h>
102	#include <iprt/string.h>
103	#include <iprt/alloc.h>
104
105
106	/*******************************************************************************
107	* Structures and Typedefs *
108	*******************************************************************************/
109	/**
110	* Trap handler function.
111	* @todo need to specialize this as we go along.
112	*/
113	typedef enum TRPMHANDLER
114	{
115	/** Generic Interrupt handler. */
116	TRPM_HANDLER_INT = 0,
117	/** Generic Trap handler. */
118	TRPM_HANDLER_TRAP,
119	/** Trap 8 (\#DF) handler. */
120	TRPM_HANDLER_TRAP_08,
121	/** Trap 12 (\#MC) handler. */
122	TRPM_HANDLER_TRAP_12,
123	/** Max. */
124	TRPM_HANDLER_MAX
125	} TRPMHANDLER, *PTRPMHANDLER;
126
127
128	/*******************************************************************************
129	* Global Variables *
130	*******************************************************************************/
131	/** Preinitialized IDT.
132	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
133	* will use to pick the right address. The u16SegSel is always VMM CS.
134	*/
135	static VBOXIDTE_GENERIC g_aIdt[256] =
136	{
137	/* special trap handler - still, this is an interrupt gate not a trap gate... */
138	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139	/* generic trap handler. */
140	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
141	/* special interrupt handler. */
142	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
143	/* generic interrupt handler. */
144	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
145	/* special task gate IDT entry (for critical exceptions like #DF). */
146	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
147	/* draft, fixme later when the handler is written. */
148	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
149
150	/* N - M M - T - C - D i */
151	/* o - n o - y - o - e p */
152	/* - e n - p - d - s t */
153	/* - i - e - e - c . */
154	/* - c - - - r */
155	/* ============================================================= */
156	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
157	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
158	#ifdef VBOX_WITH_NMI
159	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160	#else
161	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
162	#endif
163	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
164	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
165	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
166	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
167	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
168	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
169	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
170	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
171	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
172	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
173	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
174	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
175	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
176	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
177	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
178	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
179	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
180	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
190	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
191	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
192	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
414	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
415	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
416	#undef IDTE_TRAP
417	#undef IDTE_TRAP_GEN
418	#undef IDTE_INT
419	#undef IDTE_INT_GEN
420	#undef IDTE_TASK
421	#undef IDTE_UNUSED
422	#undef IDTE_RESERVED
423	};
424
425
426	/** Enable or disable tracking of Guest's IDT. */
427	#define TRPM_TRACK_GUEST_IDT_CHANGES
428
429	/** Enable or disable tracking of Shadow IDT. */
430	#define TRPM_TRACK_SHADOW_IDT_CHANGES
431
432	/** TRPM saved state version. */
433	#define TRPM_SAVED_STATE_VERSION 9
434	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
435
436
437	/*******************************************************************************
438	* Internal Functions *
439	*******************************************************************************/
440	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
441	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
442	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
443
444
445	/**
446	* Initializes the Trap Manager
447	*
448	* @returns VBox status code.
449	* @param pVM The VM to operate on.
450	*/
451	VMMR3DECL(int) TRPMR3Init(PVM pVM)
452	{
453	LogFlow(("TRPMR3Init\n"));
454
455	/*
456	* Assert sizes and alignments.
457	*/
458	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
459	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
460	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
461	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
462
463	/*
464	* Initialize members.
465	*/
466	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
467	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
468
469	for (VMCPUID i = 0; i < pVM->cCpus; i++)
470	{
471	PVMCPU pVCpu = &pVM->aCpus[i];
472
473	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
474	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
475	pVCpu->trpm.s.uActiveVector = ~0;
476	}
477
478	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
479	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
480	pVM->trpm.s.fDisableMonitoring = false;
481	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
482
483	/*
484	* Read the configuration (if any).
485	*/
486	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
487	if (pTRPMNode)
488	{
489	bool f;
490	int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
491	if (RT_SUCCESS(rc))
492	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
493	}
494
495	/* write config summary to log */
496	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
497	LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
498
499	/*
500	* Initialize the IDT.
501	* The handler addresses will be set in the TRPMR3Relocate() function.
502	*/
503	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
504	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
505
506	/*
507	* Register the saved state data unit.
508	*/
509	int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
510	NULL, NULL, NULL,
511	NULL, trpmR3Save, NULL,
512	NULL, trpmR3Load, NULL);
513	if (RT_FAILURE(rc))
514	return rc;
515
516	/*
517	* Statistics.
518	*/
519	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
520	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
521	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
522
523	/* traps */
524	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
525	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
526	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
527	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
528	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
529	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
530	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
531	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
532	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
533	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
534	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
535	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
536	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
537	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
538	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
539	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
540	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
541	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
542	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
543	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
544
545	#ifdef VBOX_WITH_STATISTICS
546	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
547	AssertRCReturn(rc, rc);
548	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
549	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
550	for (unsigned i = 0; i < 256; i++)
551	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
552	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
553
554	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
555	AssertRCReturn(rc, rc);
556	pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
557	pVM->trpm.s.paStatHostIrqR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatHostIrqR3);
558	for (unsigned i = 0; i < 256; i++)
559	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
560	"Host interrupts.", "/TRPM/HostIRQs/%02x", i);
561	#endif
562
563	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
564	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
565	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
566	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
567	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
568	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
569
570	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
571	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
572
573	/*
574	* Default action when entering raw mode for the first time
575	*/
576	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
577	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
578	return 0;
579	}
580
581
582	/**
583	* Applies relocations to data and code managed by this component.
584	*
585	* This function will be called at init and whenever the VMM need
586	* to relocate itself inside the GC.
587	*
588	* @param pVM Pointer to the VM.
589	* @param offDelta Relocation delta relative to old location.
590	*/
591	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
592	{
593	/* Only applies to raw mode which supports only 1 VCPU. */
594	PVMCPU pVCpu = &pVM->aCpus[0];
595
596	LogFlow(("TRPMR3Relocate\n"));
597	/*
598	* Get the trap handler addresses.
599	*
600	* If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
601	* would make init order impossible if we should assert the presence of these
602	* exports in TRPMR3Init().
603	*/
604	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
605	RT_ZERO(aRCPtrs);
606	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
607	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
608
609	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
610	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
611
612	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
613	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
614
615	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
616	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
617
618	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
619
620	/*
621	* Iterate the idt and set the addresses.
622	*/
623	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
624	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
625	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
626	{
627	if ( pIdte->Gen.u1Present
628	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
629	)
630	{
631	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
632	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
633	switch (pIdteTemplate->u16OffsetLow)
634	{
635	/*
636	* Generic handlers have different entrypoints for each possible
637	* vector number. These entrypoints makes a sort of an array with
638	* 8 byte entries where the vector number is the index.
639	* See TRPMGCHandlersA.asm for details.
640	*/
641	case TRPM_HANDLER_INT:
642	case TRPM_HANDLER_TRAP:
643	Offset += i * 8;
644	break;
645	case TRPM_HANDLER_TRAP_12:
646	break;
647	case TRPM_HANDLER_TRAP_08:
648	/* Handle #DF Task Gate in special way. */
649	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
650	pIdte->Gen.u16OffsetLow = 0;
651	pIdte->Gen.u16OffsetHigh = 0;
652	SELMSetTrap8EIP(pVM, Offset);
653	continue;
654	}
655	/* (non-task gates only ) */
656	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
657	pIdte->Gen.u16OffsetHigh = Offset >> 16;
658	pIdte->Gen.u16SegSel = SelCS;
659	}
660	}
661
662	/*
663	* Update IDTR (limit is including!).
664	*/
665	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
666
667	if ( !pVM->trpm.s.fDisableMonitoring
668	&& !VMMIsHwVirtExtForced(pVM))
669	{
670	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
671	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
672	{
673	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
674	AssertRC(rc);
675	}
676	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
677	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
678	0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
679	AssertRC(rc);
680	#endif
681	}
682
683	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
684	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
685	{
686	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
687	{
688	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
689	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
690	}
691
692	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
693	{
694	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
695	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
696
697	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
698	pHandler += offDelta;
699
700	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
701	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
702	}
703	}
704
705	#ifdef VBOX_WITH_STATISTICS
706	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
707	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
708	pVM->trpm.s.paStatHostIrqRC += offDelta;
709	pVM->trpm.s.paStatHostIrqR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatHostIrqR3);
710	#endif
711	}
712
713
714	/**
715	* Terminates the Trap Manager
716	*
717	* @returns VBox status code.
718	* @param pVM The VM to operate on.
719	*/
720	VMMR3DECL(int) TRPMR3Term(PVM pVM)
721	{
722	NOREF(pVM);
723	return 0;
724	}
725
726
727	/**
728	* Resets a virtual CPU.
729	*
730	* Used by TRPMR3Reset and CPU hot plugging.
731	*
732	* @param pVCpu The virtual CPU handle.
733	*/
734	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
735	{
736	pVCpu->trpm.s.uActiveVector = ~0;
737	}
738
739
740	/**
741	* The VM is being reset.
742	*
743	* For the TRPM component this means that any IDT write monitors
744	* needs to be removed, any pending trap cleared, and the IDT reset.
745	*
746	* @param pVM VM handle.
747	*/
748	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
749	{
750	/*
751	* Deregister any virtual handlers.
752	*/
753	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
754	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
755	{
756	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
757	{
758	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
759	AssertRC(rc);
760	}
761	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
762	}
763	pVM->trpm.s.GuestIdtr.cbIdt = 0;
764	#endif
765
766	/*
767	* Reinitialize other members calling the relocator to get things right.
768	*/
769	for (VMCPUID i = 0; i < pVM->cCpus; i++)
770	TRPMR3ResetCpu(&pVM->aCpus[i]);
771	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
772	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
773	TRPMR3Relocate(pVM, 0);
774
775	/*
776	* Default action when entering raw mode for the first time
777	*/
778	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
779	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
780	}
781
782
783	/**
784	* Execute state save operation.
785	*
786	* @returns VBox status code.
787	* @param pVM VM Handle.
788	* @param pSSM SSM operation handle.
789	*/
790	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
791	{
792	PTRPM pTrpm = &pVM->trpm.s;
793	LogFlow(("trpmR3Save:\n"));
794
795	/*
796	* Active and saved traps.
797	*/
798	for (VMCPUID i = 0; i < pVM->cCpus; i++)
799	{
800	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
801	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
802	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
803	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
804	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
805	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
806	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
807	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
808	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
809	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
810	}
811	SSMR3PutBool(pSSM, pTrpm->fDisableMonitoring);
812	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
813	SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT));
814	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
815	SSMR3PutU32(pSSM, ~0); /* separator. */
816
817	/*
818	* Save any trampoline gates.
819	*/
820	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
821	{
822	if (pTrpm->aGuestTrapHandler[iTrap])
823	{
824	SSMR3PutU32(pSSM, iTrap);
825	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
826	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
827	}
828	}
829
830	return SSMR3PutU32(pSSM, ~0); /* terminator */
831	}
832
833
834	/**
835	* Execute state load operation.
836	*
837	* @returns VBox status code.
838	* @param pVM VM Handle.
839	* @param pSSM SSM operation handle.
840	* @param uVersion Data layout version.
841	* @param uPass The data pass.
842	*/
843	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
844	{
845	LogFlow(("trpmR3Load:\n"));
846	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
847
848	/*
849	* Validate version.
850	*/
851	if ( uVersion != TRPM_SAVED_STATE_VERSION
852	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
853	{
854	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
855	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
856	}
857
858	/*
859	* Call the reset function to kick out any handled gates and other potential trouble.
860	*/
861	TRPMR3Reset(pVM);
862
863	/*
864	* Active and saved traps.
865	*/
866	PTRPM pTrpm = &pVM->trpm.s;
867
868	if (uVersion == TRPM_SAVED_STATE_VERSION)
869	{
870	for (VMCPUID i = 0; i < pVM->cCpus; i++)
871	{
872	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
873	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
874	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
875	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
876	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
877	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
878	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
879	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
880	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
881	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
882	}
883
884	SSMR3GetBool(pSSM, &pVM->trpm.s.fDisableMonitoring);
885	}
886	else
887	{
888	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
889	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
890	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
891	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
892	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
893	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
894	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
895	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
896	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
897	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
898
899	RTGCUINT fDisableMonitoring;
900	SSMR3GetGCUInt(pSSM, &fDisableMonitoring);
901	pTrpm->fDisableMonitoring = !!fDisableMonitoring;
902	}
903
904	RTUINT fSyncIDT;
905	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
906	if (RT_FAILURE(rc))
907	return rc;
908	if (fSyncIDT & ~1)
909	{
910	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
911	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
912	}
913	if (fSyncIDT)
914	{
915	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
916	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
917	}
918	/* else: cleared by reset call above. */
919
920	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
921
922	/* check the separator */
923	uint32_t u32Sep;
924	rc = SSMR3GetU32(pSSM, &u32Sep);
925	if (RT_FAILURE(rc))
926	return rc;
927	if (u32Sep != (uint32_t)~0)
928	{
929	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
930	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
931	}
932
933	/*
934	* Restore any trampoline gates.
935	*/
936	for (;;)
937	{
938	/* gate number / terminator */
939	uint32_t iTrap;
940	rc = SSMR3GetU32(pSSM, &iTrap);
941	if (RT_FAILURE(rc))
942	return rc;
943	if (iTrap == (uint32_t)~0)
944	break;
945	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
946	\|\| pTrpm->aGuestTrapHandler[iTrap])
947	{
948	AssertMsgFailed(("iTrap=%#x\n", iTrap));
949	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
950	}
951
952	/* restore the IDT entry. */
953	RTGCPTR GCPtrHandler;
954	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
955	VBOXIDTE Idte;
956	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
957	if (RT_FAILURE(rc))
958	return rc;
959	Assert(GCPtrHandler);
960	pTrpm->aIdt[iTrap] = Idte;
961	}
962
963	return VINF_SUCCESS;
964	}
965
966
967	/**
968	* Check if gate handlers were updated
969	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
970	*
971	* @returns VBox status code.
972	* @param pVM Pointer to the VM.
973	* @param pVCpu The VMCPU handle.
974	*/
975	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
976	{
977	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
978	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
979	int rc;
980
981	if (pVM->trpm.s.fDisableMonitoring)
982	{
983	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
984	return VINF_SUCCESS; /* Nothing to do */
985	}
986
987	if (fRawRing0 && CSAMIsEnabled(pVM))
988	{
989	/* Clear all handlers */
990	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
991	/** @todo inefficient, but simple */
992	for (unsigned iGate = 0; iGate < 256; iGate++)
993	trpmClearGuestTrapHandler(pVM, iGate);
994
995	/* Scan them all (only the first time) */
996	CSAMR3CheckGates(pVM, 0, 256);
997	}
998
999	/*
1000	* Get the IDTR.
1001	*/
1002	VBOXIDTR IDTR;
1003	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1004	if (!IDTR.cbIdt)
1005	{
1006	Log(("No IDT entries...\n"));
1007	return DBGFSTOP(pVM);
1008	}
1009
1010	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1011	/*
1012	* Check if Guest's IDTR has changed.
1013	*/
1014	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1015	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1016	{
1017	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1018	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1019	{
1020	/*
1021	* [Re]Register write virtual handler for guest's IDT.
1022	*/
1023	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1024	{
1025	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1026	AssertRCReturn(rc, rc);
1027	}
1028	/* limit is including */
1029	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1030	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1031
1032	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1033	{
1034	/* Could be a conflict with CSAM */
1035	CSAMR3RemovePage(pVM, IDTR.pIdt);
1036	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1037	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1038
1039	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1040	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1041	}
1042
1043	AssertRCReturn(rc, rc);
1044	}
1045
1046	/* Update saved Guest IDTR. */
1047	pVM->trpm.s.GuestIdtr = IDTR;
1048	}
1049	#endif
1050
1051	/*
1052	* Sync the interrupt gate.
1053	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1054	*/
1055	X86DESC Idte3;
1056	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1057	if (RT_FAILURE(rc))
1058	{
1059	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1060	return DBGFSTOP(pVM);
1061	}
1062	AssertRCReturn(rc, rc);
1063	if (fRawRing0)
1064	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1065	else
1066	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1067
1068	/*
1069	* Clear the FF and we're done.
1070	*/
1071	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1072	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1073	return VINF_SUCCESS;
1074	}
1075
1076
1077	/**
1078	* Disable IDT monitoring and syncing
1079	*
1080	* @param pVM The VM to operate on.
1081	*/
1082	VMMR3DECL(void) TRPMR3DisableMonitoring(PVM pVM)
1083	{
1084	/*
1085	* Deregister any virtual handlers.
1086	*/
1087	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1088	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1089	{
1090	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1091	{
1092	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1093	AssertRC(rc);
1094	}
1095	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
1096	}
1097	pVM->trpm.s.GuestIdtr.cbIdt = 0;
1098	#endif
1099
1100	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
1101	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
1102	{
1103	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
1104	AssertRC(rc);
1105	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
1106	}
1107	#endif
1108
1109	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
1110	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1111
1112	pVM->trpm.s.fDisableMonitoring = true;
1113	}
1114
1115
1116	/**
1117	* \#PF Handler callback for virtual access handler ranges.
1118	*
1119	* Important to realize that a physical page in a range can have aliases, and
1120	* for ALL and WRITE handlers these will also trigger.
1121	*
1122	* @returns VINF_SUCCESS if the handler have carried out the operation.
1123	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1124	* @param pVM VM Handle.
1125	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1126	* @param pvPtr The HC mapping of that address.
1127	* @param pvBuf What the guest is reading/writing.
1128	* @param cbBuf How much it's reading/writing.
1129	* @param enmAccessType The access type.
1130	* @param pvUser User argument.
1131	*/
1132	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1133	PGMACCESSTYPE enmAccessType, void *pvUser)
1134	{
1135	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1136	Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1137	NOREF(pvPtr); NOREF(pvUser); NOREF(pvBuf);
1138
1139	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1140	return VINF_PGM_HANDLER_DO_DEFAULT;
1141	}
1142
1143
1144	/**
1145	* Clear passthrough interrupt gate handler (reset to default handler)
1146	*
1147	* @returns VBox status code.
1148	* @param pVM The VM to operate on.
1149	* @param iTrap Trap/interrupt gate number.
1150	*/
1151	VMMR3DECL(int) trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1152	{
1153	/* Only applies to raw mode which supports only 1 VCPU. */
1154	PVMCPU pVCpu = &pVM->aCpus[0];
1155
1156	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1157	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1158	int rc;
1159
1160	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1161
1162	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1163	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1164
1165	if ( iTrap < TRPM_HANDLER_INT_BASE
1166	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1167	{
1168	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1169	return VERR_INVALID_PARAMETER;
1170	}
1171	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1172
1173	/* Unmark it for relocation purposes. */
1174	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1175
1176	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1177	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1178	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1179	if (pIdte->Gen.u1Present)
1180	{
1181	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1182	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1183	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1184
1185	/*
1186	* Generic handlers have different entrypoints for each possible
1187	* vector number. These entrypoints make a sort of an array with
1188	* 8 byte entries where the vector number is the index.
1189	* See TRPMGCHandlersA.asm for details.
1190	*/
1191	Offset += iTrap * 8;
1192
1193	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1194	{
1195	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1196	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1197	pIdte->Gen.u16SegSel = SelCS;
1198	}
1199	}
1200
1201	return VINF_SUCCESS;
1202	}
1203
1204
1205	/**
1206	* Check if address is a gate handler (interrupt or trap).
1207	*
1208	* @returns gate nr or ~0 is not found
1209	*
1210	* @param pVM VM handle.
1211	* @param GCPtr GC address to check.
1212	*/
1213	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1214	{
1215	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1216	{
1217	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1218	return iTrap;
1219
1220	/* redundant */
1221	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1222	{
1223	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1224	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1225
1226	if (pHandler == GCPtr)
1227	return iTrap;
1228	}
1229	}
1230	return ~0;
1231	}
1232
1233
1234	/**
1235	* Get guest trap/interrupt gate handler
1236	*
1237	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1238	* @param pVM The VM to operate on.
1239	* @param iTrap Interrupt/trap number.
1240	*/
1241	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1242	{
1243	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1244
1245	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1246	}
1247
1248
1249	/**
1250	* Set guest trap/interrupt gate handler
1251	* Used for setting up trap gates used for kernel calls.
1252	*
1253	* @returns VBox status code.
1254	* @param pVM The VM to operate on.
1255	* @param iTrap Interrupt/trap number.
1256	* @param pHandler GC handler pointer
1257	*/
1258	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1259	{
1260	/* Only valid in raw mode which implies 1 VCPU */
1261	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1262	PVMCPU pVCpu = &pVM->aCpus[0];
1263
1264	/*
1265	* Validate.
1266	*/
1267	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1268	{
1269	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1270	return VERR_INVALID_PARAMETER;
1271	}
1272
1273	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1274
1275	uint16_t cbIDT;
1276	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1277	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1278	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1279
1280	if (pHandler == TRPM_INVALID_HANDLER)
1281	{
1282	/* clear trap handler */
1283	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1284	return trpmClearGuestTrapHandler(pVM, iTrap);
1285	}
1286
1287	/*
1288	* Read the guest IDT entry.
1289	*/
1290	VBOXIDTE GuestIdte;
1291	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1292	if (RT_FAILURE(rc))
1293	{
1294	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1295	return rc;
1296	}
1297
1298	if (EMIsRawRing0Enabled(pVM))
1299	{
1300	/*
1301	* Only replace handlers for which we are 100% certain there won't be
1302	* any host interrupts.
1303	*
1304	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1305	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1306	*
1307	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1308	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1309	* and will therefor never assign hardware interrupts to 0x80.
1310	*
1311	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1312	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1313	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1314	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1315	* @bugref{3604}.
1316	*
1317	* PORTME - Check if your host keeps any of these gates free from hw ints.
1318	*
1319	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1320	*/
1321	/** @todo handle those dependencies better! */
1322	/** @todo Solve this in a proper manner. see @bugref{1186} */
1323	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1324	if (iTrap == 0x2E)
1325	#elif defined(RT_OS_LINUX)
1326	if (iTrap == 0x80)
1327	#else
1328	if (0)
1329	#endif
1330	{
1331	if ( GuestIdte.Gen.u1Present
1332	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1333	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1334	&& GuestIdte.Gen.u2DPL == 3)
1335	{
1336	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1337
1338	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1339	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1340	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1341	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1342	*pIdte = GuestIdte;
1343
1344	/* Mark it for relocation purposes. */
1345	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1346
1347	/* Also store it in our guest trap array. */
1348	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1349
1350	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1351	return VINF_SUCCESS;
1352	}
1353	/* ok, let's try to install a trampoline handler then. */
1354	}
1355	}
1356
1357	if ( GuestIdte.Gen.u1Present
1358	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1359	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1360	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1361	{
1362	/*
1363	* Save handler which can be used for a trampoline call inside the GC
1364	*/
1365	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1366	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1367	return VINF_SUCCESS;
1368	}
1369	return VERR_INVALID_PARAMETER;
1370	}
1371
1372
1373	/**
1374	* Check if address is a gate handler (interrupt/trap/task/anything).
1375	*
1376	* @returns True is gate handler, false if not.
1377	*
1378	* @param pVM VM handle.
1379	* @param GCPtr GC address to check.
1380	*/
1381	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1382	{
1383	/* Only valid in raw mode which implies 1 VCPU */
1384	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1385	PVMCPU pVCpu = &pVM->aCpus[0];
1386
1387	/*
1388	* Read IDTR and calc last entry.
1389	*/
1390	uint16_t cbIDT;
1391	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1392	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1393	if (!cEntries)
1394	return false;
1395	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1396
1397	/*
1398	* Outer loop: iterate pages.
1399	*/
1400	while (GCPtrIDTE <= GCPtrIDTELast)
1401	{
1402	/*
1403	* Convert this page to a HC address.
1404	* (This function checks for not-present pages.)
1405	*/
1406	PCVBOXIDTE pIDTE;
1407	PGMPAGEMAPLOCK Lock;
1408	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1409	if (RT_SUCCESS(rc))
1410	{
1411	/*
1412	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1413	* N.B. Member of the Flat Earth Society...
1414	*/
1415	while (GCPtrIDTE <= GCPtrIDTELast)
1416	{
1417	if (pIDTE->Gen.u1Present)
1418	{
1419	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1420	if (GCPtr == GCPtrHandler)
1421	{
1422	PGMPhysReleasePageMappingLock(pVM, &Lock);
1423	return true;
1424	}
1425	}
1426
1427	/* next entry */
1428	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1429	{
1430	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1431	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1432	GCPtrIDTE += sizeof(VBOXIDTE);
1433	break;
1434	}
1435	GCPtrIDTE += sizeof(VBOXIDTE);
1436	pIDTE++;
1437	}
1438	PGMPhysReleasePageMappingLock(pVM, &Lock);
1439	}
1440	else
1441	{
1442	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1443	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1444	return false;
1445	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1446	}
1447	}
1448	return false;
1449	}
1450
1451
1452	/**
1453	* Inject event (such as external irq or trap)
1454	*
1455	* @returns VBox status code.
1456	* @param pVM The VM to operate on.
1457	* @param pVCpu The VMCPU to operate on.
1458	* @param enmEvent Trpm event type
1459	*/
1460	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1461	{
1462	PCPUMCTX pCtx;
1463	int rc;
1464
1465	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1466	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1467	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1468
1469	/* Currently only useful for external hardware interrupts. */
1470	Assert(enmEvent == TRPM_HARDWARE_INT);
1471
1472	if ( !EMIsSupervisorCodeRecompiled(pVM)
1473	#ifdef VBOX_WITH_REM
1474	&& REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ
1475	#endif
1476	)
1477	{
1478	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1479
1480	# ifdef LOG_ENABLED
1481	DBGFR3InfoLog(pVM, "cpumguest", "TRPMInject");
1482	DBGFR3DisasInstrCurrentLog(pVCpu, "TRPMInject");
1483	# endif
1484
1485	uint8_t u8Interrupt;
1486	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1487	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1488	if (RT_SUCCESS(rc))
1489	{
1490	# ifndef IEM_VERIFICATION_MODE
1491	if (HWACCMIsEnabled(pVM))
1492	# endif
1493	{
1494	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1495	AssertRC(rc);
1496	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1497	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM;
1498	}
1499	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1500	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1501	{
1502	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1503	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1504	}
1505
1506	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1507	{
1508	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1509	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1510	if (rc == VINF_SUCCESS)
1511	{
1512	/* There's a handler -> let's execute it in raw mode */
1513	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1514	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1515	{
1516	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1517
1518	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1519	return VINF_EM_RESCHEDULE_RAW;
1520	}
1521	}
1522	}
1523	else
1524	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1525	#ifdef VBOX_WITH_REM
1526	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1527	#endif
1528	}
1529	else
1530	{
1531	AssertRC(rc);
1532	return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1533	}
1534	#else
1535	if (HWACCMR3IsActive(pVM))
1536	{
1537	uint8_t u8Interrupt;
1538	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1539	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1540	if (RT_SUCCESS(rc))
1541	{
1542	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
1543	AssertRC(rc);
1544	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1545	return VINF_EM_RESCHEDULE_HWACC;
1546	}
1547	}
1548	else
1549	AssertRC(rc);
1550	#endif
1551	}
1552	/** @todo check if it's safe to translate the patch address to the original guest address.
1553	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1554	*/
1555	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1556
1557	/* Fall back to the recompiler */
1558	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1559	}
1560

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source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 41783

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