TRPM.cpp@ 45578

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1	/* $Id: TRPM.cpp 45536 2013-04-13 16:25:46Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72	/*******************************************************************************
73	* Header Files *
74	*******************************************************************************/
75	#define LOG_GROUP LOG_GROUP_TRPM
76	#include <VBox/vmm/trpm.h>
77	#include <VBox/vmm/cpum.h>
78	#include <VBox/vmm/selm.h>
79	#include <VBox/vmm/ssm.h>
80	#include <VBox/vmm/pdmapi.h>
81	#include <VBox/vmm/em.h>
82	#include <VBox/vmm/pgm.h>
83	#include "internal/pgm.h"
84	#include <VBox/vmm/dbgf.h>
85	#include <VBox/vmm/mm.h>
86	#include <VBox/vmm/stam.h>
87	#include <VBox/vmm/csam.h>
88	#include <VBox/vmm/patm.h>
89	#include "TRPMInternal.h"
90	#include <VBox/vmm/vm.h>
91	#include <VBox/vmm/em.h>
92	#ifdef VBOX_WITH_REM
93	# include <VBox/vmm/rem.h>
94	#endif
95	#include <VBox/vmm/hm.h>
96
97	#include <VBox/err.h>
98	#include <VBox/param.h>
99	#include <VBox/log.h>
100	#include <iprt/assert.h>
101	#include <iprt/asm.h>
102	#include <iprt/string.h>
103	#include <iprt/alloc.h>
104
105
106	/*******************************************************************************
107	* Structures and Typedefs *
108	*******************************************************************************/
109	/**
110	* Trap handler function.
111	* @todo need to specialize this as we go along.
112	*/
113	typedef enum TRPMHANDLER
114	{
115	/** Generic Interrupt handler. */
116	TRPM_HANDLER_INT = 0,
117	/** Generic Trap handler. */
118	TRPM_HANDLER_TRAP,
119	/** Trap 8 (\#DF) handler. */
120	TRPM_HANDLER_TRAP_08,
121	/** Trap 12 (\#MC) handler. */
122	TRPM_HANDLER_TRAP_12,
123	/** Max. */
124	TRPM_HANDLER_MAX
125	} TRPMHANDLER, *PTRPMHANDLER;
126
127
128	/*******************************************************************************
129	* Global Variables *
130	*******************************************************************************/
131	/** Preinitialized IDT.
132	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
133	* will use to pick the right address. The u16SegSel is always VMM CS.
134	*/
135	static VBOXIDTE_GENERIC g_aIdt[256] =
136	{
137	/* special trap handler - still, this is an interrupt gate not a trap gate... */
138	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139	/* generic trap handler. */
140	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
141	/* special interrupt handler. */
142	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
143	/* generic interrupt handler. */
144	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
145	/* special task gate IDT entry (for critical exceptions like #DF). */
146	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
147	/* draft, fixme later when the handler is written. */
148	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
149
150	/* N - M M - T - C - D i */
151	/* o - n o - y - o - e p */
152	/* - e n - p - d - s t */
153	/* - i - e - e - c . */
154	/* - c - - - r */
155	/* ============================================================= */
156	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
157	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
158	#ifdef VBOX_WITH_NMI
159	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160	#else
161	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
162	#endif
163	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
164	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
165	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
166	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
167	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
168	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
169	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
170	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
171	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
172	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
173	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
174	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
175	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
176	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
177	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
178	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
179	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
180	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
190	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
191	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
192	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
414	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
415	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
416	#undef IDTE_TRAP
417	#undef IDTE_TRAP_GEN
418	#undef IDTE_INT
419	#undef IDTE_INT_GEN
420	#undef IDTE_TASK
421	#undef IDTE_UNUSED
422	#undef IDTE_RESERVED
423	};
424
425
426	#ifdef VBOX_WITH_RAW_MODE
427	/** Enable or disable tracking of Guest's IDT. */
428	# define TRPM_TRACK_GUEST_IDT_CHANGES
429	/** Enable or disable tracking of Shadow IDT. */
430	# define TRPM_TRACK_SHADOW_IDT_CHANGES
431	#endif
432
433	/** TRPM saved state version. */
434	#define TRPM_SAVED_STATE_VERSION 9
435	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
436
437
438	/*******************************************************************************
439	* Internal Functions *
440	*******************************************************************************/
441	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
442	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
443	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
444	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
445	#endif
446
447
448	/**
449	* Initializes the Trap Manager
450	*
451	* @returns VBox status code.
452	* @param pVM Pointer to the VM.
453	*/
454	VMMR3DECL(int) TRPMR3Init(PVM pVM)
455	{
456	LogFlow(("TRPMR3Init\n"));
457
458	/*
459	* Assert sizes and alignments.
460	*/
461	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
462	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
463	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
464	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
465
466	/*
467	* Initialize members.
468	*/
469	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
470	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
471
472	for (VMCPUID i = 0; i < pVM->cCpus; i++)
473	{
474	PVMCPU pVCpu = &pVM->aCpus[i];
475
476	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
477	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
478	pVCpu->trpm.s.uActiveVector = ~0;
479	}
480
481	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
482	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
483	pVM->trpm.s.fDisableMonitoring = false;
484	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
485
486	/*
487	* Read the configuration (if any).
488	*/
489	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
490	if (pTRPMNode)
491	{
492	bool f;
493	int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
494	if (RT_SUCCESS(rc))
495	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
496	}
497
498	/* write config summary to log */
499	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
500	LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
501
502	/*
503	* Initialize the IDT.
504	* The handler addresses will be set in the TRPMR3Relocate() function.
505	*/
506	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
507	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
508
509	/*
510	* Register the saved state data unit.
511	*/
512	int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
513	NULL, NULL, NULL,
514	NULL, trpmR3Save, NULL,
515	NULL, trpmR3Load, NULL);
516	if (RT_FAILURE(rc))
517	return rc;
518
519	/*
520	* Statistics.
521	*/
522	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
523	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
524	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
525
526	/* traps */
527	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
528	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
529	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
530	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
531	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
532	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
533	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
534	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
535	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
536	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
537	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
538	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
539	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
540	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
541	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
542	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
543	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
544	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
545	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
546	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
547
548	#ifdef VBOX_WITH_STATISTICS
549	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
550	AssertRCReturn(rc, rc);
551	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
552	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
553	for (unsigned i = 0; i < 256; i++)
554	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
555	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
556
557	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
558	AssertRCReturn(rc, rc);
559	pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
560	pVM->trpm.s.paStatHostIrqR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatHostIrqR3);
561	for (unsigned i = 0; i < 256; i++)
562	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
563	"Host interrupts.", "/TRPM/HostIRQs/%02x", i);
564	#endif
565
566	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
567	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
568	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
569	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
570	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
571	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
572
573	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
574	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
575
576	#ifdef VBOX_WITH_RAW_MODE
577	/*
578	* Default action when entering raw mode for the first time
579	*/
580	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
581	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
582	#endif
583	return 0;
584	}
585
586
587	/**
588	* Applies relocations to data and code managed by this component.
589	*
590	* This function will be called at init and whenever the VMM need
591	* to relocate itself inside the GC.
592	*
593	* @param pVM Pointer to the VM.
594	* @param offDelta Relocation delta relative to old location.
595	*/
596	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
597	{
598	/* Only applies to raw mode which supports only 1 VCPU. */
599	PVMCPU pVCpu = &pVM->aCpus[0];
600
601	LogFlow(("TRPMR3Relocate\n"));
602	/*
603	* Get the trap handler addresses.
604	*
605	* If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
606	* would make init order impossible if we should assert the presence of these
607	* exports in TRPMR3Init().
608	*/
609	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
610	RT_ZERO(aRCPtrs);
611	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
612	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
613
614	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
615	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
616
617	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
618	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
619
620	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
621	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
622
623	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
624
625	/*
626	* Iterate the idt and set the addresses.
627	*/
628	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
629	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
630	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
631	{
632	if ( pIdte->Gen.u1Present
633	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
634	)
635	{
636	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
637	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
638	switch (pIdteTemplate->u16OffsetLow)
639	{
640	/*
641	* Generic handlers have different entrypoints for each possible
642	* vector number. These entrypoints makes a sort of an array with
643	* 8 byte entries where the vector number is the index.
644	* See TRPMGCHandlersA.asm for details.
645	*/
646	case TRPM_HANDLER_INT:
647	case TRPM_HANDLER_TRAP:
648	Offset += i * 8;
649	break;
650	case TRPM_HANDLER_TRAP_12:
651	break;
652	case TRPM_HANDLER_TRAP_08:
653	/* Handle #DF Task Gate in special way. */
654	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
655	pIdte->Gen.u16OffsetLow = 0;
656	pIdte->Gen.u16OffsetHigh = 0;
657	SELMSetTrap8EIP(pVM, Offset);
658	continue;
659	}
660	/* (non-task gates only ) */
661	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
662	pIdte->Gen.u16OffsetHigh = Offset >> 16;
663	pIdte->Gen.u16SegSel = SelCS;
664	}
665	}
666
667	/*
668	* Update IDTR (limit is including!).
669	*/
670	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
671
672	if ( !pVM->trpm.s.fDisableMonitoring
673	&& !VMMIsHwVirtExtForced(pVM))
674	{
675	#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
676	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
677	{
678	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
679	AssertRC(rc);
680	}
681	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
682	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
683	0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
684	AssertRC(rc);
685	#endif
686	}
687
688	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
689	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
690	{
691	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
692	{
693	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
694	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
695	}
696
697	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
698	{
699	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
700	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
701
702	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
703	pHandler += offDelta;
704
705	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
706	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
707	}
708	}
709
710	#ifdef VBOX_WITH_STATISTICS
711	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
712	pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
713	pVM->trpm.s.paStatHostIrqRC += offDelta;
714	pVM->trpm.s.paStatHostIrqR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatHostIrqR3);
715	#endif
716	}
717
718
719	/**
720	* Terminates the Trap Manager
721	*
722	* @returns VBox status code.
723	* @param pVM Pointer to the VM.
724	*/
725	VMMR3DECL(int) TRPMR3Term(PVM pVM)
726	{
727	NOREF(pVM);
728	return 0;
729	}
730
731
732	/**
733	* Resets a virtual CPU.
734	*
735	* Used by TRPMR3Reset and CPU hot plugging.
736	*
737	* @param pVCpu Pointer to the VMCPU.
738	*/
739	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
740	{
741	pVCpu->trpm.s.uActiveVector = ~0;
742	}
743
744
745	/**
746	* The VM is being reset.
747	*
748	* For the TRPM component this means that any IDT write monitors
749	* needs to be removed, any pending trap cleared, and the IDT reset.
750	*
751	* @param pVM Pointer to the VM.
752	*/
753	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
754	{
755	/*
756	* Deregister any virtual handlers.
757	*/
758	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
759	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
760	{
761	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
762	{
763	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
764	AssertRC(rc);
765	}
766	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
767	}
768	pVM->trpm.s.GuestIdtr.cbIdt = 0;
769	#endif
770
771	/*
772	* Reinitialize other members calling the relocator to get things right.
773	*/
774	for (VMCPUID i = 0; i < pVM->cCpus; i++)
775	TRPMR3ResetCpu(&pVM->aCpus[i]);
776	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
777	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
778	TRPMR3Relocate(pVM, 0);
779
780	#ifdef VBOX_WITH_RAW_MODE
781	/*
782	* Default action when entering raw mode for the first time
783	*/
784	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
785	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
786	#endif
787	}
788
789
790	# ifdef VBOX_WITH_RAW_MODE
791	/**
792	* Resolve a builtin RC symbol.
793	*
794	* Called by PDM when loading or relocating RC modules.
795	*
796	* @returns VBox status
797	* @param pVM Pointer to the VM.
798	* @param pszSymbol Symbol to resolv
799	* @param pRCPtrValue Where to store the symbol value.
800	*
801	* @remark This has to work before VMMR3Relocate() is called.
802	*/
803	VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
804	{
805	if (!strcmp(pszSymbol, "g_TRPM"))
806	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
807	else if (!strcmp(pszSymbol, "g_TRPMCPU"))
808	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
809	else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
810	{
811	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
812	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
813	}
814	else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
815	{
816	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
817	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
818	}
819	else
820	return VERR_SYMBOL_NOT_FOUND;
821	return VINF_SUCCESS;
822	}
823	#endif /* VBOX_WITH_RAW_MODE */
824
825
826	/**
827	* Execute state save operation.
828	*
829	* @returns VBox status code.
830	* @param pVM Pointer to the VM.
831	* @param pSSM SSM operation handle.
832	*/
833	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
834	{
835	PTRPM pTrpm = &pVM->trpm.s;
836	LogFlow(("trpmR3Save:\n"));
837
838	/*
839	* Active and saved traps.
840	*/
841	for (VMCPUID i = 0; i < pVM->cCpus; i++)
842	{
843	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
844	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
845	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
846	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
847	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
848	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
849	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
850	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
851	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
852	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
853	}
854	SSMR3PutBool(pSSM, pTrpm->fDisableMonitoring);
855	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
856	SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT), 0));
857	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
858	SSMR3PutU32(pSSM, ~0); /* separator. */
859
860	/*
861	* Save any trampoline gates.
862	*/
863	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
864	{
865	if (pTrpm->aGuestTrapHandler[iTrap])
866	{
867	SSMR3PutU32(pSSM, iTrap);
868	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
869	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
870	}
871	}
872
873	return SSMR3PutU32(pSSM, ~0); /* terminator */
874	}
875
876
877	/**
878	* Execute state load operation.
879	*
880	* @returns VBox status code.
881	* @param pVM Pointer to the VM.
882	* @param pSSM SSM operation handle.
883	* @param uVersion Data layout version.
884	* @param uPass The data pass.
885	*/
886	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
887	{
888	LogFlow(("trpmR3Load:\n"));
889	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
890
891	/*
892	* Validate version.
893	*/
894	if ( uVersion != TRPM_SAVED_STATE_VERSION
895	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
896	{
897	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
898	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
899	}
900
901	/*
902	* Call the reset function to kick out any handled gates and other potential trouble.
903	*/
904	TRPMR3Reset(pVM);
905
906	/*
907	* Active and saved traps.
908	*/
909	PTRPM pTrpm = &pVM->trpm.s;
910
911	if (uVersion == TRPM_SAVED_STATE_VERSION)
912	{
913	for (VMCPUID i = 0; i < pVM->cCpus; i++)
914	{
915	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
916	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
917	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
918	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
919	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
920	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
921	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
922	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
923	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
924	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
925	}
926
927	SSMR3GetBool(pSSM, &pVM->trpm.s.fDisableMonitoring);
928	}
929	else
930	{
931	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
932	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
933	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
934	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
935	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
936	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
937	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
938	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
939	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
940	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
941
942	RTGCUINT fDisableMonitoring;
943	SSMR3GetGCUInt(pSSM, &fDisableMonitoring);
944	pTrpm->fDisableMonitoring = !!fDisableMonitoring;
945	}
946
947	RTUINT fSyncIDT;
948	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
949	if (RT_FAILURE(rc))
950	return rc;
951	if (fSyncIDT & ~1)
952	{
953	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
954	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
955	}
956	#ifdef VBOX_WITH_RAW_MODE
957	if (fSyncIDT)
958	{
959	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
960	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
961	}
962	/* else: cleared by reset call above. */
963	#endif
964
965	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
966
967	/* check the separator */
968	uint32_t u32Sep;
969	rc = SSMR3GetU32(pSSM, &u32Sep);
970	if (RT_FAILURE(rc))
971	return rc;
972	if (u32Sep != (uint32_t)~0)
973	{
974	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
975	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
976	}
977
978	/*
979	* Restore any trampoline gates.
980	*/
981	for (;;)
982	{
983	/* gate number / terminator */
984	uint32_t iTrap;
985	rc = SSMR3GetU32(pSSM, &iTrap);
986	if (RT_FAILURE(rc))
987	return rc;
988	if (iTrap == (uint32_t)~0)
989	break;
990	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
991	\|\| pTrpm->aGuestTrapHandler[iTrap])
992	{
993	AssertMsgFailed(("iTrap=%#x\n", iTrap));
994	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
995	}
996
997	/* restore the IDT entry. */
998	RTGCPTR GCPtrHandler;
999	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1000	VBOXIDTE Idte;
1001	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1002	if (RT_FAILURE(rc))
1003	return rc;
1004	Assert(GCPtrHandler);
1005	pTrpm->aIdt[iTrap] = Idte;
1006	}
1007
1008	return VINF_SUCCESS;
1009	}
1010
1011	#ifdef VBOX_WITH_RAW_MODE
1012
1013	/**
1014	* Check if gate handlers were updated
1015	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1016	*
1017	* @returns VBox status code.
1018	* @param pVM Pointer to the VM.
1019	* @param pVCpu Pointer to the VMCPU.
1020	*/
1021	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1022	{
1023	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1024	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1025	int rc;
1026
1027	if (pVM->trpm.s.fDisableMonitoring)
1028	{
1029	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1030	return VINF_SUCCESS; /* Nothing to do */
1031	}
1032
1033	if (fRawRing0 && CSAMIsEnabled(pVM))
1034	{
1035	/* Clear all handlers */
1036	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1037	/** @todo inefficient, but simple */
1038	for (unsigned iGate = 0; iGate < 256; iGate++)
1039	trpmClearGuestTrapHandler(pVM, iGate);
1040
1041	/* Scan them all (only the first time) */
1042	CSAMR3CheckGates(pVM, 0, 256);
1043	}
1044
1045	/*
1046	* Get the IDTR.
1047	*/
1048	VBOXIDTR IDTR;
1049	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1050	if (!IDTR.cbIdt)
1051	{
1052	Log(("No IDT entries...\n"));
1053	return DBGFSTOP(pVM);
1054	}
1055
1056	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1057	/*
1058	* Check if Guest's IDTR has changed.
1059	*/
1060	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1061	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1062	{
1063	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1064	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1065	{
1066	/*
1067	* [Re]Register write virtual handler for guest's IDT.
1068	*/
1069	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1070	{
1071	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1072	AssertRCReturn(rc, rc);
1073	}
1074	/* limit is including */
1075	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1076	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1077
1078	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1079	{
1080	/* Could be a conflict with CSAM */
1081	CSAMR3RemovePage(pVM, IDTR.pIdt);
1082	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1083	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1084
1085	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1086	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1087	}
1088
1089	AssertRCReturn(rc, rc);
1090	}
1091
1092	/* Update saved Guest IDTR. */
1093	pVM->trpm.s.GuestIdtr = IDTR;
1094	}
1095	# endif
1096
1097	/*
1098	* Sync the interrupt gate.
1099	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1100	*/
1101	X86DESC Idte3;
1102	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1103	if (RT_FAILURE(rc))
1104	{
1105	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1106	return DBGFSTOP(pVM);
1107	}
1108	AssertRCReturn(rc, rc);
1109	if (fRawRing0)
1110	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1111	else
1112	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1113
1114	/*
1115	* Clear the FF and we're done.
1116	*/
1117	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1118	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1119	return VINF_SUCCESS;
1120	}
1121
1122
1123	/**
1124	* Disable IDT monitoring and syncing
1125	*
1126	* @param pVM Pointer to the VM.
1127	*/
1128	VMMR3DECL(void) TRPMR3DisableMonitoring(PVM pVM)
1129	{
1130	/*
1131	* Deregister any virtual handlers.
1132	*/
1133	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1134	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1135	{
1136	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1137	{
1138	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1139	AssertRC(rc);
1140	}
1141	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
1142	}
1143	pVM->trpm.s.GuestIdtr.cbIdt = 0;
1144	# endif
1145
1146	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
1147	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
1148	{
1149	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
1150	AssertRC(rc);
1151	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
1152	}
1153	# endif
1154
1155	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
1156	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1157
1158	pVM->trpm.s.fDisableMonitoring = true;
1159	}
1160
1161
1162	/**
1163	* \#PF Handler callback for virtual access handler ranges.
1164	*
1165	* Important to realize that a physical page in a range can have aliases, and
1166	* for ALL and WRITE handlers these will also trigger.
1167	*
1168	* @returns VINF_SUCCESS if the handler have carried out the operation.
1169	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1170	* @param pVM Pointer to the VM.
1171	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1172	* @param pvPtr The HC mapping of that address.
1173	* @param pvBuf What the guest is reading/writing.
1174	* @param cbBuf How much it's reading/writing.
1175	* @param enmAccessType The access type.
1176	* @param pvUser User argument.
1177	*/
1178	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1179	PGMACCESSTYPE enmAccessType, void *pvUser)
1180	{
1181	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1182	Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1183	NOREF(pvPtr); NOREF(pvUser); NOREF(pvBuf);
1184
1185	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1186	return VINF_PGM_HANDLER_DO_DEFAULT;
1187	}
1188
1189
1190	/**
1191	* Clear passthrough interrupt gate handler (reset to default handler)
1192	*
1193	* @returns VBox status code.
1194	* @param pVM Pointer to the VM.
1195	* @param iTrap Trap/interrupt gate number.
1196	*/
1197	VMMR3DECL(int) trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1198	{
1199	/* Only applies to raw mode which supports only 1 VCPU. */
1200	PVMCPU pVCpu = &pVM->aCpus[0];
1201
1202	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1203	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1204	int rc;
1205
1206	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1207
1208	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1209	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1210
1211	if ( iTrap < TRPM_HANDLER_INT_BASE
1212	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1213	{
1214	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1215	return VERR_INVALID_PARAMETER;
1216	}
1217	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1218
1219	/* Unmark it for relocation purposes. */
1220	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1221
1222	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1223	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1224	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1225	if (pIdte->Gen.u1Present)
1226	{
1227	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1228	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1229	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1230
1231	/*
1232	* Generic handlers have different entrypoints for each possible
1233	* vector number. These entrypoints make a sort of an array with
1234	* 8 byte entries where the vector number is the index.
1235	* See TRPMGCHandlersA.asm for details.
1236	*/
1237	Offset += iTrap * 8;
1238
1239	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1240	{
1241	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1242	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1243	pIdte->Gen.u16SegSel = SelCS;
1244	}
1245	}
1246
1247	return VINF_SUCCESS;
1248	}
1249
1250
1251	/**
1252	* Check if address is a gate handler (interrupt or trap).
1253	*
1254	* @returns gate nr or ~0 is not found
1255	*
1256	* @param pVM Pointer to the VM.
1257	* @param GCPtr GC address to check.
1258	*/
1259	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1260	{
1261	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1262	{
1263	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1264	return iTrap;
1265
1266	/* redundant */
1267	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1268	{
1269	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1270	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1271
1272	if (pHandler == GCPtr)
1273	return iTrap;
1274	}
1275	}
1276	return ~0;
1277	}
1278
1279
1280	/**
1281	* Get guest trap/interrupt gate handler
1282	*
1283	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1284	* @param pVM Pointer to the VM.
1285	* @param iTrap Interrupt/trap number.
1286	*/
1287	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1288	{
1289	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1290
1291	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1292	}
1293
1294
1295	/**
1296	* Set guest trap/interrupt gate handler
1297	* Used for setting up trap gates used for kernel calls.
1298	*
1299	* @returns VBox status code.
1300	* @param pVM Pointer to the VM.
1301	* @param iTrap Interrupt/trap number.
1302	* @param pHandler GC handler pointer
1303	*/
1304	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1305	{
1306	/* Only valid in raw mode which implies 1 VCPU */
1307	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1308	PVMCPU pVCpu = &pVM->aCpus[0];
1309
1310	/*
1311	* Validate.
1312	*/
1313	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1314	{
1315	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1316	return VERR_INVALID_PARAMETER;
1317	}
1318
1319	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1320
1321	uint16_t cbIDT;
1322	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1323	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1324	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1325
1326	if (pHandler == TRPM_INVALID_HANDLER)
1327	{
1328	/* clear trap handler */
1329	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1330	return trpmClearGuestTrapHandler(pVM, iTrap);
1331	}
1332
1333	/*
1334	* Read the guest IDT entry.
1335	*/
1336	VBOXIDTE GuestIdte;
1337	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1338	if (RT_FAILURE(rc))
1339	{
1340	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1341	return rc;
1342	}
1343
1344	if ( EMIsRawRing0Enabled(pVM)
1345	&& !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1346	{
1347	/*
1348	* Only replace handlers for which we are 100% certain there won't be
1349	* any host interrupts.
1350	*
1351	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1352	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1353	*
1354	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1355	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1356	* and will therefor never assign hardware interrupts to 0x80.
1357	*
1358	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1359	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1360	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1361	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1362	* @bugref{3604}.
1363	*
1364	* PORTME - Check if your host keeps any of these gates free from hw ints.
1365	*
1366	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1367	*/
1368	/** @todo handle those dependencies better! */
1369	/** @todo Solve this in a proper manner. see @bugref{1186} */
1370	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1371	if (iTrap == 0x2E)
1372	#elif defined(RT_OS_LINUX)
1373	if (iTrap == 0x80)
1374	#else
1375	if (0)
1376	#endif
1377	{
1378	if ( GuestIdte.Gen.u1Present
1379	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1380	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1381	&& GuestIdte.Gen.u2DPL == 3)
1382	{
1383	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1384
1385	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1386	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1387	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1388	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1389	*pIdte = GuestIdte;
1390
1391	/* Mark it for relocation purposes. */
1392	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1393
1394	/* Also store it in our guest trap array. */
1395	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1396
1397	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1398	return VINF_SUCCESS;
1399	}
1400	/* ok, let's try to install a trampoline handler then. */
1401	}
1402	}
1403
1404	if ( GuestIdte.Gen.u1Present
1405	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1406	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1407	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1408	{
1409	/*
1410	* Save handler which can be used for a trampoline call inside the GC
1411	*/
1412	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1413	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1414	return VINF_SUCCESS;
1415	}
1416	return VERR_INVALID_PARAMETER;
1417	}
1418
1419
1420	/**
1421	* Check if address is a gate handler (interrupt/trap/task/anything).
1422	*
1423	* @returns True is gate handler, false if not.
1424	*
1425	* @param pVM Pointer to the VM.
1426	* @param GCPtr GC address to check.
1427	*/
1428	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1429	{
1430	/* Only valid in raw mode which implies 1 VCPU */
1431	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1432	PVMCPU pVCpu = &pVM->aCpus[0];
1433
1434	/*
1435	* Read IDTR and calc last entry.
1436	*/
1437	uint16_t cbIDT;
1438	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1439	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1440	if (!cEntries)
1441	return false;
1442	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1443
1444	/*
1445	* Outer loop: iterate pages.
1446	*/
1447	while (GCPtrIDTE <= GCPtrIDTELast)
1448	{
1449	/*
1450	* Convert this page to a HC address.
1451	* (This function checks for not-present pages.)
1452	*/
1453	PCVBOXIDTE pIDTE;
1454	PGMPAGEMAPLOCK Lock;
1455	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1456	if (RT_SUCCESS(rc))
1457	{
1458	/*
1459	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1460	* N.B. Member of the Flat Earth Society...
1461	*/
1462	while (GCPtrIDTE <= GCPtrIDTELast)
1463	{
1464	if (pIDTE->Gen.u1Present)
1465	{
1466	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1467	if (GCPtr == GCPtrHandler)
1468	{
1469	PGMPhysReleasePageMappingLock(pVM, &Lock);
1470	return true;
1471	}
1472	}
1473
1474	/* next entry */
1475	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1476	{
1477	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1478	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1479	GCPtrIDTE += sizeof(VBOXIDTE);
1480	break;
1481	}
1482	GCPtrIDTE += sizeof(VBOXIDTE);
1483	pIDTE++;
1484	}
1485	PGMPhysReleasePageMappingLock(pVM, &Lock);
1486	}
1487	else
1488	{
1489	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1490	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1491	return false;
1492	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1493	}
1494	}
1495	return false;
1496	}
1497
1498	#endif /* VBOX_WITH_RAW_MODE */
1499
1500	/**
1501	* Inject event (such as external irq or trap)
1502	*
1503	* @returns VBox status code.
1504	* @param pVM Pointer to the VM.
1505	* @param pVCpu Pointer to the VMCPU.
1506	* @param enmEvent Trpm event type
1507	*/
1508	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1509	{
1510	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1511	#ifdef VBOX_WITH_RAW_MODE
1512	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1513	#endif
1514	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1515
1516	/* Currently only useful for external hardware interrupts. */
1517	Assert(enmEvent == TRPM_HARDWARE_INT);
1518
1519	if ( !EMIsSupervisorCodeRecompiled(pVM)
1520	#ifdef VBOX_WITH_REM
1521	&& REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ
1522	#endif
1523	)
1524	{
1525	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1526
1527	# ifdef LOG_ENABLED
1528	DBGFR3_INFO_LOG(pVM, "cpumguest", "TRPMInject");
1529	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1530	# endif
1531
1532	uint8_t u8Interrupt;
1533	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1534	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1535	if (RT_SUCCESS(rc))
1536	{
1537	# ifndef IEM_VERIFICATION_MODE
1538	if (HMIsEnabled(pVM))
1539	# endif
1540	{
1541	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1542	AssertRC(rc);
1543	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1544	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1545	}
1546	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1547	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1548	{
1549	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1550	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1551	}
1552
1553	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1554	{
1555	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1556	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1557	if (rc == VINF_SUCCESS)
1558	{
1559	/* There's a handler -> let's execute it in raw mode */
1560	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1561	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1562	{
1563	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1564
1565	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1566	return VINF_EM_RESCHEDULE_RAW;
1567	}
1568	}
1569	}
1570	else
1571	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1572	# ifdef VBOX_WITH_REM
1573	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1574	# endif
1575	}
1576	else
1577	{
1578	AssertRC(rc);
1579	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1580	}
1581	#else /* !TRPM_FORWARD_TRAPS_IN_GC */
1582	if (HMR3IsActive(pVCpu))
1583	{
1584	uint8_t u8Interrupt;
1585	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1586	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1587	if (RT_SUCCESS(rc))
1588	{
1589	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1590	AssertRC(rc);
1591	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1592	return VINF_EM_RESCHEDULE_HM;
1593	}
1594	}
1595	#endif /* !TRPM_FORWARD_TRAPS_IN_GC */
1596	}
1597	/** @todo check if it's safe to translate the patch address to the original guest address.
1598	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1599	*/
1600	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1601
1602	/* Fall back to the recompiler */
1603	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1604	}
1605

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source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 45578

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