TRPM.cpp@ 55438

Last change on this file since 55438 was 55000, checked in by vboxsync, 10 years ago
CPUMCTXCORE elimination.
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Line
1	/* $Id: TRPM.cpp 55000 2015-03-29 16:42:16Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72	/*******************************************************************************
73	* Header Files *
74	*******************************************************************************/
75	#define LOG_GROUP LOG_GROUP_TRPM
76	#include <VBox/vmm/trpm.h>
77	#include <VBox/vmm/cpum.h>
78	#include <VBox/vmm/selm.h>
79	#include <VBox/vmm/ssm.h>
80	#include <VBox/vmm/pdmapi.h>
81	#include <VBox/vmm/em.h>
82	#include <VBox/vmm/pgm.h>
83	#include "internal/pgm.h"
84	#include <VBox/vmm/dbgf.h>
85	#include <VBox/vmm/mm.h>
86	#include <VBox/vmm/stam.h>
87	#include <VBox/vmm/csam.h>
88	#include <VBox/vmm/patm.h>
89	#include "TRPMInternal.h"
90	#include <VBox/vmm/vm.h>
91	#include <VBox/vmm/em.h>
92	#ifdef VBOX_WITH_REM
93	# include <VBox/vmm/rem.h>
94	#endif
95	#include <VBox/vmm/hm.h>
96
97	#include <VBox/err.h>
98	#include <VBox/param.h>
99	#include <VBox/log.h>
100	#include <iprt/assert.h>
101	#include <iprt/asm.h>
102	#include <iprt/string.h>
103	#include <iprt/alloc.h>
104
105
106	/*******************************************************************************
107	* Structures and Typedefs *
108	*******************************************************************************/
109	/**
110	* Trap handler function.
111	* @todo need to specialize this as we go along.
112	*/
113	typedef enum TRPMHANDLER
114	{
115	/** Generic Interrupt handler. */
116	TRPM_HANDLER_INT = 0,
117	/** Generic Trap handler. */
118	TRPM_HANDLER_TRAP,
119	/** Trap 8 (\#DF) handler. */
120	TRPM_HANDLER_TRAP_08,
121	/** Trap 12 (\#MC) handler. */
122	TRPM_HANDLER_TRAP_12,
123	/** Max. */
124	TRPM_HANDLER_MAX
125	} TRPMHANDLER, *PTRPMHANDLER;
126
127
128	/*******************************************************************************
129	* Global Variables *
130	*******************************************************************************/
131	/** Preinitialized IDT.
132	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
133	* will use to pick the right address. The u16SegSel is always VMM CS.
134	*/
135	static VBOXIDTE_GENERIC g_aIdt[256] =
136	{
137	/* special trap handler - still, this is an interrupt gate not a trap gate... */
138	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139	/* generic trap handler. */
140	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
141	/* special interrupt handler. */
142	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
143	/* generic interrupt handler. */
144	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
145	/* special task gate IDT entry (for critical exceptions like #DF). */
146	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
147	/* draft, fixme later when the handler is written. */
148	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
149
150	/* N - M M - T - C - D i */
151	/* o - n o - y - o - e p */
152	/* - e n - p - d - s t */
153	/* - i - e - e - c . */
154	/* - c - - - r */
155	/* ============================================================= */
156	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
157	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
158	#ifdef VBOX_WITH_NMI
159	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160	#else
161	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
162	#endif
163	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
164	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
165	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
166	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
167	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
168	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
169	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
170	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
171	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
172	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
173	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
174	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
175	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
176	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
177	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
178	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
179	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
180	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
190	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
191	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
192	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
414	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
415	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
416	#undef IDTE_TRAP
417	#undef IDTE_TRAP_GEN
418	#undef IDTE_INT
419	#undef IDTE_INT_GEN
420	#undef IDTE_TASK
421	#undef IDTE_UNUSED
422	#undef IDTE_RESERVED
423	};
424
425
426	#ifdef VBOX_WITH_RAW_MODE
427	/** Enable or disable tracking of Guest's IDT. */
428	# define TRPM_TRACK_GUEST_IDT_CHANGES
429	/** Enable or disable tracking of Shadow IDT. */
430	# define TRPM_TRACK_SHADOW_IDT_CHANGES
431	#endif
432
433	/** TRPM saved state version. */
434	#define TRPM_SAVED_STATE_VERSION 9
435	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
436
437
438	/*******************************************************************************
439	* Internal Functions *
440	*******************************************************************************/
441	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
442	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
443	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
444	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
445	#endif
446
447
448	/**
449	* Initializes the Trap Manager
450	*
451	* @returns VBox status code.
452	* @param pVM Pointer to the VM.
453	*/
454	VMMR3DECL(int) TRPMR3Init(PVM pVM)
455	{
456	LogFlow(("TRPMR3Init\n"));
457
458	/*
459	* Assert sizes and alignments.
460	*/
461	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
462	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
463	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
464	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
465
466	/*
467	* Initialize members.
468	*/
469	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
470	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
471
472	for (VMCPUID i = 0; i < pVM->cCpus; i++)
473	{
474	PVMCPU pVCpu = &pVM->aCpus[i];
475
476	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
477	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
478	pVCpu->trpm.s.uActiveVector = ~0U;
479	}
480
481	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
482	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
483	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
484
485	/*
486	* Read the configuration (if any).
487	*/
488	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
489	if (pTRPMNode)
490	{
491	bool f;
492	int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
493	if (RT_SUCCESS(rc))
494	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
495	}
496
497	/* write config summary to log */
498	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
499	LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
500
501	/*
502	* Initialize the IDT.
503	* The handler addresses will be set in the TRPMR3Relocate() function.
504	*/
505	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
506	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
507
508	/*
509	* Register the saved state data unit.
510	*/
511	int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
512	NULL, NULL, NULL,
513	NULL, trpmR3Save, NULL,
514	NULL, trpmR3Load, NULL);
515	if (RT_FAILURE(rc))
516	return rc;
517
518	/*
519	* Statistics.
520	*/
521	#ifdef VBOX_WITH_RAW_MODE
522	if (!HMIsEnabled(pVM))
523	{
524	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
525	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
526	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
527
528	/* traps */
529	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
530	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
531	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
532	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
533	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
534	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
535	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
536	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
537	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
538	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
539	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
540	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
541	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
542	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
543	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
544	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
545	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
546	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
547	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
548	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
549	}
550	#endif
551
552	# ifdef VBOX_WITH_STATISTICS
553	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
554	AssertRCReturn(rc, rc);
555	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
556	for (unsigned i = 0; i < 256; i++)
557	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
558	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
559
560	# ifdef VBOX_WITH_RAW_MODE
561	if (!HMIsEnabled(pVM))
562	{
563	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
564	AssertRCReturn(rc, rc);
565	pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
566	for (unsigned i = 0; i < 256; i++)
567	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
568	"Host interrupts.", "/TRPM/HostIRQs/%02x", i);
569	}
570	# endif
571	# endif
572
573	#ifdef VBOX_WITH_RAW_MODE
574	if (!HMIsEnabled(pVM))
575	{
576	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
577	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
578	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
579	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
580	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
581	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
582
583	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
584	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
585	}
586	#endif
587
588	#ifdef VBOX_WITH_RAW_MODE
589	/*
590	* Default action when entering raw mode for the first time
591	*/
592	if (!HMIsEnabled(pVM))
593	{
594	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
595	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
596	}
597	#endif
598	return 0;
599	}
600
601
602	/**
603	* Applies relocations to data and code managed by this component.
604	*
605	* This function will be called at init and whenever the VMM need
606	* to relocate itself inside the GC.
607	*
608	* @param pVM Pointer to the VM.
609	* @param offDelta Relocation delta relative to old location.
610	*/
611	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
612	{
613	#ifdef VBOX_WITH_RAW_MODE
614	if (HMIsEnabled(pVM))
615	return;
616
617	/* Only applies to raw mode which supports only 1 VCPU. */
618	PVMCPU pVCpu = &pVM->aCpus[0];
619	LogFlow(("TRPMR3Relocate\n"));
620
621	/*
622	* Get the trap handler addresses.
623	*
624	* If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
625	* would make init order impossible if we should assert the presence of these
626	* exports in TRPMR3Init().
627	*/
628	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
629	RT_ZERO(aRCPtrs);
630	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
631	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
632
633	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
634	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
635
636	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
637	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
638
639	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
640	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
641
642	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
643
644	/*
645	* Iterate the idt and set the addresses.
646	*/
647	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
648	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
649	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
650	{
651	if ( pIdte->Gen.u1Present
652	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
653	)
654	{
655	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
656	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
657	switch (pIdteTemplate->u16OffsetLow)
658	{
659	/*
660	* Generic handlers have different entrypoints for each possible
661	* vector number. These entrypoints makes a sort of an array with
662	* 8 byte entries where the vector number is the index.
663	* See TRPMGCHandlersA.asm for details.
664	*/
665	case TRPM_HANDLER_INT:
666	case TRPM_HANDLER_TRAP:
667	Offset += i * 8;
668	break;
669	case TRPM_HANDLER_TRAP_12:
670	break;
671	case TRPM_HANDLER_TRAP_08:
672	/* Handle #DF Task Gate in special way. */
673	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
674	pIdte->Gen.u16OffsetLow = 0;
675	pIdte->Gen.u16OffsetHigh = 0;
676	SELMSetTrap8EIP(pVM, Offset);
677	continue;
678	}
679	/* (non-task gates only ) */
680	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
681	pIdte->Gen.u16OffsetHigh = Offset >> 16;
682	pIdte->Gen.u16SegSel = SelCS;
683	}
684	}
685
686	/*
687	* Update IDTR (limit is including!).
688	*/
689	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
690
691	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
692	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
693	{
694	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
695	AssertRC(rc);
696	}
697	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
698	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
699	0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
700	AssertRC(rc);
701	# endif
702
703	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
704	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
705	{
706	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
707	{
708	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
709	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
710	}
711
712	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
713	{
714	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
715	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
716
717	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
718	pHandler += offDelta;
719
720	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
721	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
722	}
723	}
724
725	# ifdef VBOX_WITH_STATISTICS
726	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
727	pVM->trpm.s.paStatHostIrqRC += offDelta;
728	# endif
729	#endif /* VBOX_WITH_RAW_MODE */
730	}
731
732
733	/**
734	* Terminates the Trap Manager
735	*
736	* @returns VBox status code.
737	* @param pVM Pointer to the VM.
738	*/
739	VMMR3DECL(int) TRPMR3Term(PVM pVM)
740	{
741	NOREF(pVM);
742	return VINF_SUCCESS;
743	}
744
745
746	/**
747	* Resets a virtual CPU.
748	*
749	* Used by TRPMR3Reset and CPU hot plugging.
750	*
751	* @param pVCpu Pointer to the VMCPU.
752	*/
753	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
754	{
755	pVCpu->trpm.s.uActiveVector = ~0U;
756	}
757
758
759	/**
760	* The VM is being reset.
761	*
762	* For the TRPM component this means that any IDT write monitors
763	* needs to be removed, any pending trap cleared, and the IDT reset.
764	*
765	* @param pVM Pointer to the VM.
766	*/
767	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
768	{
769	/*
770	* Deregister any virtual handlers.
771	*/
772	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
773	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
774	{
775	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
776	{
777	int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
778	AssertRC(rc);
779	}
780	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
781	}
782	pVM->trpm.s.GuestIdtr.cbIdt = 0;
783	#endif
784
785	/*
786	* Reinitialize other members calling the relocator to get things right.
787	*/
788	for (VMCPUID i = 0; i < pVM->cCpus; i++)
789	TRPMR3ResetCpu(&pVM->aCpus[i]);
790	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
791	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
792	TRPMR3Relocate(pVM, 0);
793
794	#ifdef VBOX_WITH_RAW_MODE
795	/*
796	* Default action when entering raw mode for the first time
797	*/
798	if (!HMIsEnabled(pVM))
799	{
800	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
801	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
802	}
803	#endif
804	}
805
806
807	# ifdef VBOX_WITH_RAW_MODE
808	/**
809	* Resolve a builtin RC symbol.
810	*
811	* Called by PDM when loading or relocating RC modules.
812	*
813	* @returns VBox status
814	* @param pVM Pointer to the VM.
815	* @param pszSymbol Symbol to resolv
816	* @param pRCPtrValue Where to store the symbol value.
817	*
818	* @remark This has to work before VMMR3Relocate() is called.
819	*/
820	VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
821	{
822	if (!strcmp(pszSymbol, "g_TRPM"))
823	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
824	else if (!strcmp(pszSymbol, "g_TRPMCPU"))
825	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
826	else if (!strcmp(pszSymbol, "g_trpmGuestCtx"))
827	{
828	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
829	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
830	}
831	else if (!strcmp(pszSymbol, "g_trpmHyperCtx"))
832	{
833	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
834	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
835	}
836	else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
837	{
838	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
839	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
840	}
841	else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
842	{
843	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
844	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
845	}
846	else
847	return VERR_SYMBOL_NOT_FOUND;
848	return VINF_SUCCESS;
849	}
850	#endif /* VBOX_WITH_RAW_MODE */
851
852
853	/**
854	* Execute state save operation.
855	*
856	* @returns VBox status code.
857	* @param pVM Pointer to the VM.
858	* @param pSSM SSM operation handle.
859	*/
860	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
861	{
862	PTRPM pTrpm = &pVM->trpm.s;
863	LogFlow(("trpmR3Save:\n"));
864
865	/*
866	* Active and saved traps.
867	*/
868	for (VMCPUID i = 0; i < pVM->cCpus; i++)
869	{
870	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
871	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
872	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
873	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
874	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
875	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
876	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
877	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
878	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
879	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
880	}
881	SSMR3PutBool(pSSM, HMIsEnabled(pVM));
882	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
883	SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT), 0));
884	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
885	SSMR3PutU32(pSSM, ~0); /* separator. */
886
887	/*
888	* Save any trampoline gates.
889	*/
890	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
891	{
892	if (pTrpm->aGuestTrapHandler[iTrap])
893	{
894	SSMR3PutU32(pSSM, iTrap);
895	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
896	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
897	}
898	}
899
900	return SSMR3PutU32(pSSM, ~0); /* terminator */
901	}
902
903
904	/**
905	* Execute state load operation.
906	*
907	* @returns VBox status code.
908	* @param pVM Pointer to the VM.
909	* @param pSSM SSM operation handle.
910	* @param uVersion Data layout version.
911	* @param uPass The data pass.
912	*/
913	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
914	{
915	LogFlow(("trpmR3Load:\n"));
916	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
917
918	/*
919	* Validate version.
920	*/
921	if ( uVersion != TRPM_SAVED_STATE_VERSION
922	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
923	{
924	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
925	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
926	}
927
928	/*
929	* Call the reset function to kick out any handled gates and other potential trouble.
930	*/
931	TRPMR3Reset(pVM);
932
933	/*
934	* Active and saved traps.
935	*/
936	PTRPM pTrpm = &pVM->trpm.s;
937
938	if (uVersion == TRPM_SAVED_STATE_VERSION)
939	{
940	for (VMCPUID i = 0; i < pVM->cCpus; i++)
941	{
942	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
943	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
944	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
945	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
946	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
947	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
948	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
949	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
950	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
951	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
952	}
953
954	bool fIgnored;
955	SSMR3GetBool(pSSM, &fIgnored);
956	}
957	else
958	{
959	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
960	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
961	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
962	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
963	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
964	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
965	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
966	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
967	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
968	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
969
970	RTGCUINT fIgnored;
971	SSMR3GetGCUInt(pSSM, &fIgnored);
972	}
973
974	RTUINT fSyncIDT;
975	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
976	if (RT_FAILURE(rc))
977	return rc;
978	if (fSyncIDT & ~1)
979	{
980	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
981	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
982	}
983	#ifdef VBOX_WITH_RAW_MODE
984	if (fSyncIDT)
985	{
986	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
987	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
988	}
989	/* else: cleared by reset call above. */
990	#endif
991
992	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
993
994	/* check the separator */
995	uint32_t u32Sep;
996	rc = SSMR3GetU32(pSSM, &u32Sep);
997	if (RT_FAILURE(rc))
998	return rc;
999	if (u32Sep != (uint32_t)~0)
1000	{
1001	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1002	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1003	}
1004
1005	/*
1006	* Restore any trampoline gates.
1007	*/
1008	for (;;)
1009	{
1010	/* gate number / terminator */
1011	uint32_t iTrap;
1012	rc = SSMR3GetU32(pSSM, &iTrap);
1013	if (RT_FAILURE(rc))
1014	return rc;
1015	if (iTrap == (uint32_t)~0)
1016	break;
1017	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
1018	\|\| pTrpm->aGuestTrapHandler[iTrap])
1019	{
1020	AssertMsgFailed(("iTrap=%#x\n", iTrap));
1021	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1022	}
1023
1024	/* restore the IDT entry. */
1025	RTGCPTR GCPtrHandler;
1026	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1027	VBOXIDTE Idte;
1028	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1029	if (RT_FAILURE(rc))
1030	return rc;
1031	Assert(GCPtrHandler);
1032	pTrpm->aIdt[iTrap] = Idte;
1033	}
1034
1035	return VINF_SUCCESS;
1036	}
1037
1038	#ifdef VBOX_WITH_RAW_MODE
1039
1040	/**
1041	* Check if gate handlers were updated
1042	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1043	*
1044	* @returns VBox status code.
1045	* @param pVM Pointer to the VM.
1046	* @param pVCpu Pointer to the VMCPU.
1047	*/
1048	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1049	{
1050	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1051	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1052	int rc;
1053
1054	AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1055
1056	if (fRawRing0 && CSAMIsEnabled(pVM))
1057	{
1058	/* Clear all handlers */
1059	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1060	/** @todo inefficient, but simple */
1061	for (unsigned iGate = 0; iGate < 256; iGate++)
1062	trpmClearGuestTrapHandler(pVM, iGate);
1063
1064	/* Scan them all (only the first time) */
1065	CSAMR3CheckGates(pVM, 0, 256);
1066	}
1067
1068	/*
1069	* Get the IDTR.
1070	*/
1071	VBOXIDTR IDTR;
1072	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1073	if (!IDTR.cbIdt)
1074	{
1075	Log(("No IDT entries...\n"));
1076	return DBGFSTOP(pVM);
1077	}
1078
1079	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1080	/*
1081	* Check if Guest's IDTR has changed.
1082	*/
1083	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1084	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1085	{
1086	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1087	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1088	{
1089	/*
1090	* [Re]Register write virtual handler for guest's IDT.
1091	*/
1092	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1093	{
1094	rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1095	AssertRCReturn(rc, rc);
1096	}
1097	/* limit is including */
1098	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1099	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1100
1101	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1102	{
1103	/* Could be a conflict with CSAM */
1104	CSAMR3RemovePage(pVM, IDTR.pIdt);
1105	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1106	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1107
1108	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1109	0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1110	}
1111
1112	AssertRCReturn(rc, rc);
1113	}
1114
1115	/* Update saved Guest IDTR. */
1116	pVM->trpm.s.GuestIdtr = IDTR;
1117	}
1118	# endif
1119
1120	/*
1121	* Sync the interrupt gate.
1122	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1123	*/
1124	X86DESC Idte3;
1125	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1126	if (RT_FAILURE(rc))
1127	{
1128	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1129	return DBGFSTOP(pVM);
1130	}
1131	AssertRCReturn(rc, rc);
1132	if (fRawRing0)
1133	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1134	else
1135	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1136
1137	/*
1138	* Clear the FF and we're done.
1139	*/
1140	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1141	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1142	return VINF_SUCCESS;
1143	}
1144
1145
1146	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1147	/**
1148	* \#PF Handler callback for virtual access handler ranges.
1149	*
1150	* Important to realize that a physical page in a range can have aliases, and
1151	* for ALL and WRITE handlers these will also trigger.
1152	*
1153	* @returns VINF_SUCCESS if the handler have carried out the operation.
1154	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1155	* @param pVM Pointer to the VM.
1156	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1157	* @param pvPtr The HC mapping of that address.
1158	* @param pvBuf What the guest is reading/writing.
1159	* @param cbBuf How much it's reading/writing.
1160	* @param enmAccessType The access type.
1161	* @param pvUser User argument.
1162	*/
1163	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1164	PGMACCESSTYPE enmAccessType, void *pvUser)
1165	{
1166	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1167	Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1168	NOREF(pvPtr); NOREF(pvUser); NOREF(pvBuf);
1169	Assert(!HMIsEnabled(pVM));
1170
1171	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1172	return VINF_PGM_HANDLER_DO_DEFAULT;
1173	}
1174	# endif /* TRPM_TRACK_GUEST_IDT_CHANGES */
1175
1176
1177	/**
1178	* Clear passthrough interrupt gate handler (reset to default handler)
1179	*
1180	* @returns VBox status code.
1181	* @param pVM Pointer to the VM.
1182	* @param iTrap Trap/interrupt gate number.
1183	*/
1184	int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1185	{
1186	/* Only applies to raw mode which supports only 1 VCPU. */
1187	PVMCPU pVCpu = &pVM->aCpus[0];
1188	Assert(!HMIsEnabled(pVM));
1189
1190	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1191	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1192	int rc;
1193
1194	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1195
1196	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1197	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1198
1199	if ( iTrap < TRPM_HANDLER_INT_BASE
1200	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1201	{
1202	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1203	return VERR_INVALID_PARAMETER;
1204	}
1205	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1206
1207	/* Unmark it for relocation purposes. */
1208	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1209
1210	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1211	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1212	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1213	if (pIdte->Gen.u1Present)
1214	{
1215	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1216	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1217	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1218
1219	/*
1220	* Generic handlers have different entrypoints for each possible
1221	* vector number. These entrypoints make a sort of an array with
1222	* 8 byte entries where the vector number is the index.
1223	* See TRPMGCHandlersA.asm for details.
1224	*/
1225	Offset += iTrap * 8;
1226
1227	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1228	{
1229	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1230	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1231	pIdte->Gen.u16SegSel = SelCS;
1232	}
1233	}
1234
1235	return VINF_SUCCESS;
1236	}
1237
1238
1239	/**
1240	* Check if address is a gate handler (interrupt or trap).
1241	*
1242	* @returns gate nr or ~0 is not found
1243	*
1244	* @param pVM Pointer to the VM.
1245	* @param GCPtr GC address to check.
1246	*/
1247	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1248	{
1249	AssertReturn(!HMIsEnabled(pVM), ~0U);
1250
1251	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1252	{
1253	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1254	return iTrap;
1255
1256	/* redundant */
1257	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1258	{
1259	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1260	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1261
1262	if (pHandler == GCPtr)
1263	return iTrap;
1264	}
1265	}
1266	return ~0;
1267	}
1268
1269
1270	/**
1271	* Get guest trap/interrupt gate handler
1272	*
1273	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1274	* @param pVM Pointer to the VM.
1275	* @param iTrap Interrupt/trap number.
1276	*/
1277	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1278	{
1279	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1280	AssertReturn(!HMIsEnabled(pVM), TRPM_INVALID_HANDLER);
1281
1282	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1283	}
1284
1285
1286	/**
1287	* Set guest trap/interrupt gate handler
1288	* Used for setting up trap gates used for kernel calls.
1289	*
1290	* @returns VBox status code.
1291	* @param pVM Pointer to the VM.
1292	* @param iTrap Interrupt/trap number.
1293	* @param pHandler GC handler pointer
1294	*/
1295	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1296	{
1297	/* Only valid in raw mode which implies 1 VCPU */
1298	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1299	AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1300	PVMCPU pVCpu = &pVM->aCpus[0];
1301
1302	/*
1303	* Validate.
1304	*/
1305	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1306	{
1307	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1308	return VERR_INVALID_PARAMETER;
1309	}
1310
1311	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1312
1313	uint16_t cbIDT;
1314	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1315	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1316	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1317
1318	if (pHandler == TRPM_INVALID_HANDLER)
1319	{
1320	/* clear trap handler */
1321	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1322	return trpmClearGuestTrapHandler(pVM, iTrap);
1323	}
1324
1325	/*
1326	* Read the guest IDT entry.
1327	*/
1328	VBOXIDTE GuestIdte;
1329	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1330	if (RT_FAILURE(rc))
1331	{
1332	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1333	return rc;
1334	}
1335
1336	if ( EMIsRawRing0Enabled(pVM)
1337	&& !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1338	{
1339	/*
1340	* Only replace handlers for which we are 100% certain there won't be
1341	* any host interrupts.
1342	*
1343	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1344	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1345	*
1346	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1347	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1348	* and will therefor never assign hardware interrupts to 0x80.
1349	*
1350	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1351	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1352	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1353	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1354	* @bugref{3604}.
1355	*
1356	* PORTME - Check if your host keeps any of these gates free from hw ints.
1357	*
1358	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1359	*/
1360	/** @todo handle those dependencies better! */
1361	/** @todo Solve this in a proper manner. see @bugref{1186} */
1362	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1363	if (iTrap == 0x2E)
1364	#elif defined(RT_OS_LINUX)
1365	if (iTrap == 0x80)
1366	#else
1367	if (0)
1368	#endif
1369	{
1370	if ( GuestIdte.Gen.u1Present
1371	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1372	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1373	&& GuestIdte.Gen.u2DPL == 3)
1374	{
1375	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1376
1377	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1378	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1379	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1380	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1381	*pIdte = GuestIdte;
1382
1383	/* Mark it for relocation purposes. */
1384	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1385
1386	/* Also store it in our guest trap array. */
1387	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1388
1389	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1390	return VINF_SUCCESS;
1391	}
1392	/* ok, let's try to install a trampoline handler then. */
1393	}
1394	}
1395
1396	if ( GuestIdte.Gen.u1Present
1397	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1398	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1399	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1400	{
1401	/*
1402	* Save handler which can be used for a trampoline call inside the GC
1403	*/
1404	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1405	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1406	return VINF_SUCCESS;
1407	}
1408	return VERR_INVALID_PARAMETER;
1409	}
1410
1411
1412	/**
1413	* Check if address is a gate handler (interrupt/trap/task/anything).
1414	*
1415	* @returns True is gate handler, false if not.
1416	*
1417	* @param pVM Pointer to the VM.
1418	* @param GCPtr GC address to check.
1419	*/
1420	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1421	{
1422	/* Only valid in raw mode which implies 1 VCPU */
1423	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1424	PVMCPU pVCpu = &pVM->aCpus[0];
1425
1426	/*
1427	* Read IDTR and calc last entry.
1428	*/
1429	uint16_t cbIDT;
1430	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1431	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1432	if (!cEntries)
1433	return false;
1434	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1435
1436	/*
1437	* Outer loop: iterate pages.
1438	*/
1439	while (GCPtrIDTE <= GCPtrIDTELast)
1440	{
1441	/*
1442	* Convert this page to a HC address.
1443	* (This function checks for not-present pages.)
1444	*/
1445	PCVBOXIDTE pIDTE;
1446	PGMPAGEMAPLOCK Lock;
1447	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1448	if (RT_SUCCESS(rc))
1449	{
1450	/*
1451	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1452	* N.B. Member of the Flat Earth Society...
1453	*/
1454	while (GCPtrIDTE <= GCPtrIDTELast)
1455	{
1456	if (pIDTE->Gen.u1Present)
1457	{
1458	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1459	if (GCPtr == GCPtrHandler)
1460	{
1461	PGMPhysReleasePageMappingLock(pVM, &Lock);
1462	return true;
1463	}
1464	}
1465
1466	/* next entry */
1467	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1468	{
1469	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1470	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1471	GCPtrIDTE += sizeof(VBOXIDTE);
1472	break;
1473	}
1474	GCPtrIDTE += sizeof(VBOXIDTE);
1475	pIDTE++;
1476	}
1477	PGMPhysReleasePageMappingLock(pVM, &Lock);
1478	}
1479	else
1480	{
1481	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1482	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1483	return false;
1484	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1485	}
1486	}
1487	return false;
1488	}
1489
1490	#endif /* VBOX_WITH_RAW_MODE */
1491
1492	/**
1493	* Inject event (such as external irq or trap)
1494	*
1495	* @returns VBox status code.
1496	* @param pVM Pointer to the VM.
1497	* @param pVCpu Pointer to the VMCPU.
1498	* @param enmEvent Trpm event type
1499	*/
1500	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1501	{
1502	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1503	#ifdef VBOX_WITH_RAW_MODE
1504	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1505	#endif
1506	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1507
1508	/* Currently only useful for external hardware interrupts. */
1509	Assert(enmEvent == TRPM_HARDWARE_INT);
1510
1511	if ( !EMIsSupervisorCodeRecompiled(pVM)
1512	#ifdef VBOX_WITH_REM
1513	&& REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ
1514	#endif
1515	)
1516	{
1517	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1518
1519	# ifdef LOG_ENABLED
1520	DBGFR3_INFO_LOG(pVM, "cpumguest", "TRPMInject");
1521	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1522	# endif
1523
1524	uint8_t u8Interrupt;
1525	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1526	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1527	if (RT_SUCCESS(rc))
1528	{
1529	# ifndef IEM_VERIFICATION_MODE
1530	if (HMIsEnabled(pVM))
1531	# endif
1532	{
1533	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1534	AssertRC(rc);
1535	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1536	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1537	}
1538	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1539	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1540	{
1541	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1542	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1543	}
1544
1545	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1546	{
1547	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1548	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1549	if (rc == VINF_SUCCESS)
1550	{
1551	/* There's a handler -> let's execute it in raw mode */
1552	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1553	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1554	{
1555	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1556
1557	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1558	return VINF_EM_RESCHEDULE_RAW;
1559	}
1560	}
1561	}
1562	else
1563	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1564	# ifdef VBOX_WITH_REM
1565	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1566	# endif
1567	}
1568	else
1569	{
1570	AssertRC(rc);
1571	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1572	}
1573	#else /* !TRPM_FORWARD_TRAPS_IN_GC */
1574	uint8_t u8Interrupt;
1575	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1576	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1577	if (RT_SUCCESS(rc))
1578	{
1579	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1580	AssertRC(rc);
1581	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1582	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1583	}
1584	#endif /* !TRPM_FORWARD_TRAPS_IN_GC */
1585	}
1586	/** @todo check if it's safe to translate the patch address to the original guest address.
1587	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1588	*/
1589	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1590
1591	/* Fall back to the recompiler */
1592	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1593	}
1594

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source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 55438

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