TRPM.cpp@ 55897

Last change on this file since 55897 was 55897, checked in by vboxsync, 10 years ago
PGMR3HandlerVirtualTypeRegister: Dropped the pszModRC parameter as all users passed NULL.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 79.4 KB

Line
1	/* $Id: TRPM.cpp 55897 2015-05-18 09:02:07Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72	/*******************************************************************************
73	* Header Files *
74	*******************************************************************************/
75	#define LOG_GROUP LOG_GROUP_TRPM
76	#include <VBox/vmm/trpm.h>
77	#include <VBox/vmm/cpum.h>
78	#include <VBox/vmm/selm.h>
79	#include <VBox/vmm/ssm.h>
80	#include <VBox/vmm/pdmapi.h>
81	#include <VBox/vmm/em.h>
82	#include <VBox/vmm/pgm.h>
83	#include "internal/pgm.h"
84	#include <VBox/vmm/dbgf.h>
85	#include <VBox/vmm/mm.h>
86	#include <VBox/vmm/stam.h>
87	#include <VBox/vmm/csam.h>
88	#include <VBox/vmm/patm.h>
89	#include "TRPMInternal.h"
90	#include <VBox/vmm/vm.h>
91	#include <VBox/vmm/em.h>
92	#ifdef VBOX_WITH_REM
93	# include <VBox/vmm/rem.h>
94	#endif
95	#include <VBox/vmm/hm.h>
96
97	#include <VBox/err.h>
98	#include <VBox/param.h>
99	#include <VBox/log.h>
100	#include <iprt/assert.h>
101	#include <iprt/asm.h>
102	#include <iprt/string.h>
103	#include <iprt/alloc.h>
104
105
106	/*******************************************************************************
107	* Structures and Typedefs *
108	*******************************************************************************/
109	/**
110	* Trap handler function.
111	* @todo need to specialize this as we go along.
112	*/
113	typedef enum TRPMHANDLER
114	{
115	/** Generic Interrupt handler. */
116	TRPM_HANDLER_INT = 0,
117	/** Generic Trap handler. */
118	TRPM_HANDLER_TRAP,
119	/** Trap 8 (\#DF) handler. */
120	TRPM_HANDLER_TRAP_08,
121	/** Trap 12 (\#MC) handler. */
122	TRPM_HANDLER_TRAP_12,
123	/** Max. */
124	TRPM_HANDLER_MAX
125	} TRPMHANDLER, *PTRPMHANDLER;
126
127
128	/*******************************************************************************
129	* Global Variables *
130	*******************************************************************************/
131	/** Preinitialized IDT.
132	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
133	* will use to pick the right address. The u16SegSel is always VMM CS.
134	*/
135	static VBOXIDTE_GENERIC g_aIdt[256] =
136	{
137	/* special trap handler - still, this is an interrupt gate not a trap gate... */
138	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139	/* generic trap handler. */
140	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
141	/* special interrupt handler. */
142	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
143	/* generic interrupt handler. */
144	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
145	/* special task gate IDT entry (for critical exceptions like #DF). */
146	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
147	/* draft, fixme later when the handler is written. */
148	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
149
150	/* N - M M - T - C - D i */
151	/* o - n o - y - o - e p */
152	/* - e n - p - d - s t */
153	/* - i - e - e - c . */
154	/* - c - - - r */
155	/* ============================================================= */
156	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
157	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
158	#ifdef VBOX_WITH_NMI
159	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160	#else
161	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
162	#endif
163	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
164	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
165	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
166	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
167	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
168	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
169	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
170	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
171	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
172	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
173	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
174	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
175	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
176	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
177	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
178	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
179	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
180	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
190	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
191	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
192	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
414	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
415	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
416	#undef IDTE_TRAP
417	#undef IDTE_TRAP_GEN
418	#undef IDTE_INT
419	#undef IDTE_INT_GEN
420	#undef IDTE_TASK
421	#undef IDTE_UNUSED
422	#undef IDTE_RESERVED
423	};
424
425
426	#ifdef VBOX_WITH_RAW_MODE
427	/** Enable or disable tracking of Guest's IDT. */
428	# define TRPM_TRACK_GUEST_IDT_CHANGES
429	/** Enable or disable tracking of Shadow IDT. */
430	# define TRPM_TRACK_SHADOW_IDT_CHANGES
431	#endif
432
433	/** TRPM saved state version. */
434	#define TRPM_SAVED_STATE_VERSION 9
435	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
436
437
438	/*******************************************************************************
439	* Internal Functions *
440	*******************************************************************************/
441	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
442	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
443	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
444	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
445	#endif
446
447
448	/**
449	* Initializes the Trap Manager
450	*
451	* @returns VBox status code.
452	* @param pVM Pointer to the VM.
453	*/
454	VMMR3DECL(int) TRPMR3Init(PVM pVM)
455	{
456	LogFlow(("TRPMR3Init\n"));
457	int rc;
458
459	/*
460	* Assert sizes and alignments.
461	*/
462	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
463	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
464	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
465	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
466
467	/*
468	* Initialize members.
469	*/
470	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
471	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
472
473	for (VMCPUID i = 0; i < pVM->cCpus; i++)
474	{
475	PVMCPU pVCpu = &pVM->aCpus[i];
476
477	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
478	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
479	pVCpu->trpm.s.uActiveVector = ~0U;
480	}
481
482	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
483	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
484	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
485
486	/*
487	* Read the configuration (if any).
488	*/
489	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
490	if (pTRPMNode)
491	{
492	bool f;
493	rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
494	if (RT_SUCCESS(rc))
495	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
496	}
497
498	/* write config summary to log */
499	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
500	LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
501
502	/*
503	* Initialize the IDT.
504	* The handler addresses will be set in the TRPMR3Relocate() function.
505	*/
506	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
507	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
508
509	/*
510	* Register virtual access handlers.
511	*/
512	pVM->trpm.s.hShadowIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
513	pVM->trpm.s.hGuestIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
514	#ifdef VBOX_WITH_RAW_MODE
515	if (!HMIsEnabled(pVM))
516	{
517	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
518	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
519	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
520	"trpmRCShadowIDTWritePfHandler",
521	"Shadow IDT write access handler", &pVM->trpm.s.hShadowIdtWriteHandlerType);
522	AssertRCReturn(rc, rc);
523	# endif
524	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
525	NULL /pfnInvalidateR3/, trpmR3GuestIDTWriteHandler,
526	"trpmRCGuestIDTWritePfHandler",
527	"Guest IDT write access handler", &pVM->trpm.s.hGuestIdtWriteHandlerType);
528	AssertRCReturn(rc, rc);
529	}
530	#endif /* VBOX_WITH_RAW_MODE */
531
532	/*
533	* Register the saved state data unit.
534	*/
535	rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
536	NULL, NULL, NULL,
537	NULL, trpmR3Save, NULL,
538	NULL, trpmR3Load, NULL);
539	if (RT_FAILURE(rc))
540	return rc;
541
542	/*
543	* Statistics.
544	*/
545	#ifdef VBOX_WITH_RAW_MODE
546	if (!HMIsEnabled(pVM))
547	{
548	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
549	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
550	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
551
552	/* traps */
553	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
554	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
555	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
556	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
557	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
558	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
559	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
560	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
561	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
562	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
563	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
564	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
565	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
566	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
567	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
568	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
569	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
570	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
571	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
572	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
573	}
574	#endif
575
576	# ifdef VBOX_WITH_STATISTICS
577	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
578	AssertRCReturn(rc, rc);
579	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
580	for (unsigned i = 0; i < 256; i++)
581	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
582	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
583
584	# ifdef VBOX_WITH_RAW_MODE
585	if (!HMIsEnabled(pVM))
586	{
587	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
588	AssertRCReturn(rc, rc);
589	pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
590	for (unsigned i = 0; i < 256; i++)
591	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
592	"Host interrupts.", "/TRPM/HostIRQs/%02x", i);
593	}
594	# endif
595	# endif
596
597	#ifdef VBOX_WITH_RAW_MODE
598	if (!HMIsEnabled(pVM))
599	{
600	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
601	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
602	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
603	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
604	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
605	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
606
607	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
608	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
609	}
610	#endif
611
612	#ifdef VBOX_WITH_RAW_MODE
613	/*
614	* Default action when entering raw mode for the first time
615	*/
616	if (!HMIsEnabled(pVM))
617	{
618	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
619	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
620	}
621	#endif
622	return 0;
623	}
624
625
626	/**
627	* Applies relocations to data and code managed by this component.
628	*
629	* This function will be called at init and whenever the VMM need
630	* to relocate itself inside the GC.
631	*
632	* @param pVM Pointer to the VM.
633	* @param offDelta Relocation delta relative to old location.
634	*/
635	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
636	{
637	#ifdef VBOX_WITH_RAW_MODE
638	if (HMIsEnabled(pVM))
639	return;
640
641	/* Only applies to raw mode which supports only 1 VCPU. */
642	PVMCPU pVCpu = &pVM->aCpus[0];
643	LogFlow(("TRPMR3Relocate\n"));
644
645	/*
646	* Get the trap handler addresses.
647	*
648	* If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
649	* would make init order impossible if we should assert the presence of these
650	* exports in TRPMR3Init().
651	*/
652	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
653	RT_ZERO(aRCPtrs);
654	int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
655	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
656
657	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
658	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
659
660	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
661	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
662
663	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
664	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
665
666	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
667
668	/*
669	* Iterate the idt and set the addresses.
670	*/
671	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
672	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
673	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
674	{
675	if ( pIdte->Gen.u1Present
676	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
677	)
678	{
679	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
680	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
681	switch (pIdteTemplate->u16OffsetLow)
682	{
683	/*
684	* Generic handlers have different entrypoints for each possible
685	* vector number. These entrypoints makes a sort of an array with
686	* 8 byte entries where the vector number is the index.
687	* See TRPMGCHandlersA.asm for details.
688	*/
689	case TRPM_HANDLER_INT:
690	case TRPM_HANDLER_TRAP:
691	Offset += i * 8;
692	break;
693	case TRPM_HANDLER_TRAP_12:
694	break;
695	case TRPM_HANDLER_TRAP_08:
696	/* Handle #DF Task Gate in special way. */
697	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
698	pIdte->Gen.u16OffsetLow = 0;
699	pIdte->Gen.u16OffsetHigh = 0;
700	SELMSetTrap8EIP(pVM, Offset);
701	continue;
702	}
703	/* (non-task gates only ) */
704	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
705	pIdte->Gen.u16OffsetHigh = Offset >> 16;
706	pIdte->Gen.u16SegSel = SelCS;
707	}
708	}
709
710	/*
711	* Update IDTR (limit is including!).
712	*/
713	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
714
715	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
716	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
717	{
718	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.pvMonShwIdtRC, true /fHypervisor/);
719	AssertRC(rc);
720	}
721	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
722	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hShadowIdtWriteHandlerType,
723	pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
724	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
725	AssertRC(rc);
726	# endif
727
728	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
729	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
730	{
731	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
732	{
733	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
734	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
735	}
736
737	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
738	{
739	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
740	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
741
742	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
743	pHandler += offDelta;
744
745	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
746	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
747	}
748	}
749
750	# ifdef VBOX_WITH_STATISTICS
751	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
752	pVM->trpm.s.paStatHostIrqRC += offDelta;
753	# endif
754	#endif /* VBOX_WITH_RAW_MODE */
755	}
756
757
758	/**
759	* Terminates the Trap Manager
760	*
761	* @returns VBox status code.
762	* @param pVM Pointer to the VM.
763	*/
764	VMMR3DECL(int) TRPMR3Term(PVM pVM)
765	{
766	NOREF(pVM);
767	return VINF_SUCCESS;
768	}
769
770
771	/**
772	* Resets a virtual CPU.
773	*
774	* Used by TRPMR3Reset and CPU hot plugging.
775	*
776	* @param pVCpu Pointer to the VMCPU.
777	*/
778	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
779	{
780	pVCpu->trpm.s.uActiveVector = ~0U;
781	}
782
783
784	/**
785	* The VM is being reset.
786	*
787	* For the TRPM component this means that any IDT write monitors
788	* needs to be removed, any pending trap cleared, and the IDT reset.
789	*
790	* @param pVM Pointer to the VM.
791	*/
792	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
793	{
794	/*
795	* Deregister any virtual handlers.
796	*/
797	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
798	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
799	{
800	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
801	{
802	int rc = PGMHandlerVirtualDeregister(pVM, VMMGetCpu(pVM), pVM->trpm.s.GuestIdtr.pIdt, false /fHypervisor/);
803	AssertRC(rc);
804	}
805	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
806	}
807	pVM->trpm.s.GuestIdtr.cbIdt = 0;
808	#endif
809
810	/*
811	* Reinitialize other members calling the relocator to get things right.
812	*/
813	for (VMCPUID i = 0; i < pVM->cCpus; i++)
814	TRPMR3ResetCpu(&pVM->aCpus[i]);
815	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
816	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
817	TRPMR3Relocate(pVM, 0);
818
819	#ifdef VBOX_WITH_RAW_MODE
820	/*
821	* Default action when entering raw mode for the first time
822	*/
823	if (!HMIsEnabled(pVM))
824	{
825	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
826	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
827	}
828	#endif
829	}
830
831
832	# ifdef VBOX_WITH_RAW_MODE
833	/**
834	* Resolve a builtin RC symbol.
835	*
836	* Called by PDM when loading or relocating RC modules.
837	*
838	* @returns VBox status
839	* @param pVM Pointer to the VM.
840	* @param pszSymbol Symbol to resolv
841	* @param pRCPtrValue Where to store the symbol value.
842	*
843	* @remark This has to work before VMMR3Relocate() is called.
844	*/
845	VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
846	{
847	if (!strcmp(pszSymbol, "g_TRPM"))
848	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
849	else if (!strcmp(pszSymbol, "g_TRPMCPU"))
850	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
851	else if (!strcmp(pszSymbol, "g_trpmGuestCtx"))
852	{
853	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
854	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
855	}
856	else if (!strcmp(pszSymbol, "g_trpmHyperCtx"))
857	{
858	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
859	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
860	}
861	else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
862	{
863	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
864	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
865	}
866	else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
867	{
868	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
869	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
870	}
871	else
872	return VERR_SYMBOL_NOT_FOUND;
873	return VINF_SUCCESS;
874	}
875	#endif /* VBOX_WITH_RAW_MODE */
876
877
878	/**
879	* Execute state save operation.
880	*
881	* @returns VBox status code.
882	* @param pVM Pointer to the VM.
883	* @param pSSM SSM operation handle.
884	*/
885	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
886	{
887	PTRPM pTrpm = &pVM->trpm.s;
888	LogFlow(("trpmR3Save:\n"));
889
890	/*
891	* Active and saved traps.
892	*/
893	for (VMCPUID i = 0; i < pVM->cCpus; i++)
894	{
895	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
896	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
897	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
898	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
899	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
900	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
901	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
902	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
903	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
904	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
905	}
906	SSMR3PutBool(pSSM, HMIsEnabled(pVM));
907	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
908	SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT), 0));
909	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
910	SSMR3PutU32(pSSM, ~0); /* separator. */
911
912	/*
913	* Save any trampoline gates.
914	*/
915	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
916	{
917	if (pTrpm->aGuestTrapHandler[iTrap])
918	{
919	SSMR3PutU32(pSSM, iTrap);
920	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
921	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
922	}
923	}
924
925	return SSMR3PutU32(pSSM, ~0); /* terminator */
926	}
927
928
929	/**
930	* Execute state load operation.
931	*
932	* @returns VBox status code.
933	* @param pVM Pointer to the VM.
934	* @param pSSM SSM operation handle.
935	* @param uVersion Data layout version.
936	* @param uPass The data pass.
937	*/
938	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
939	{
940	LogFlow(("trpmR3Load:\n"));
941	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
942
943	/*
944	* Validate version.
945	*/
946	if ( uVersion != TRPM_SAVED_STATE_VERSION
947	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
948	{
949	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
950	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
951	}
952
953	/*
954	* Call the reset function to kick out any handled gates and other potential trouble.
955	*/
956	TRPMR3Reset(pVM);
957
958	/*
959	* Active and saved traps.
960	*/
961	PTRPM pTrpm = &pVM->trpm.s;
962
963	if (uVersion == TRPM_SAVED_STATE_VERSION)
964	{
965	for (VMCPUID i = 0; i < pVM->cCpus; i++)
966	{
967	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
968	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
969	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
970	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
971	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
972	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
973	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
974	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
975	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
976	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
977	}
978
979	bool fIgnored;
980	SSMR3GetBool(pSSM, &fIgnored);
981	}
982	else
983	{
984	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
985	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
986	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
987	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
988	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
989	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
990	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
991	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
992	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
993	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
994
995	RTGCUINT fIgnored;
996	SSMR3GetGCUInt(pSSM, &fIgnored);
997	}
998
999	RTUINT fSyncIDT;
1000	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
1001	if (RT_FAILURE(rc))
1002	return rc;
1003	if (fSyncIDT & ~1)
1004	{
1005	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
1006	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1007	}
1008	#ifdef VBOX_WITH_RAW_MODE
1009	if (fSyncIDT)
1010	{
1011	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
1012	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1013	}
1014	/* else: cleared by reset call above. */
1015	#endif
1016
1017	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
1018
1019	/* check the separator */
1020	uint32_t u32Sep;
1021	rc = SSMR3GetU32(pSSM, &u32Sep);
1022	if (RT_FAILURE(rc))
1023	return rc;
1024	if (u32Sep != (uint32_t)~0)
1025	{
1026	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1027	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1028	}
1029
1030	/*
1031	* Restore any trampoline gates.
1032	*/
1033	for (;;)
1034	{
1035	/* gate number / terminator */
1036	uint32_t iTrap;
1037	rc = SSMR3GetU32(pSSM, &iTrap);
1038	if (RT_FAILURE(rc))
1039	return rc;
1040	if (iTrap == (uint32_t)~0)
1041	break;
1042	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
1043	\|\| pTrpm->aGuestTrapHandler[iTrap])
1044	{
1045	AssertMsgFailed(("iTrap=%#x\n", iTrap));
1046	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1047	}
1048
1049	/* restore the IDT entry. */
1050	RTGCPTR GCPtrHandler;
1051	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1052	VBOXIDTE Idte;
1053	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1054	if (RT_FAILURE(rc))
1055	return rc;
1056	Assert(GCPtrHandler);
1057	pTrpm->aIdt[iTrap] = Idte;
1058	}
1059
1060	return VINF_SUCCESS;
1061	}
1062
1063	#ifdef VBOX_WITH_RAW_MODE
1064
1065	/**
1066	* Check if gate handlers were updated
1067	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1068	*
1069	* @returns VBox status code.
1070	* @param pVM Pointer to the VM.
1071	* @param pVCpu Pointer to the VMCPU.
1072	*/
1073	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1074	{
1075	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1076	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1077	int rc;
1078
1079	AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1080
1081	if (fRawRing0 && CSAMIsEnabled(pVM))
1082	{
1083	/* Clear all handlers */
1084	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1085	/** @todo inefficient, but simple */
1086	for (unsigned iGate = 0; iGate < 256; iGate++)
1087	trpmClearGuestTrapHandler(pVM, iGate);
1088
1089	/* Scan them all (only the first time) */
1090	CSAMR3CheckGates(pVM, 0, 256);
1091	}
1092
1093	/*
1094	* Get the IDTR.
1095	*/
1096	VBOXIDTR IDTR;
1097	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1098	if (!IDTR.cbIdt)
1099	{
1100	Log(("No IDT entries...\n"));
1101	return DBGFSTOP(pVM);
1102	}
1103
1104	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1105	/*
1106	* Check if Guest's IDTR has changed.
1107	*/
1108	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1109	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1110	{
1111	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1112	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1113	{
1114	/*
1115	* [Re]Register write virtual handler for guest's IDT.
1116	*/
1117	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1118	{
1119	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.GuestIdtr.pIdt, false /fHypervisor/);
1120	AssertRCReturn(rc, rc);
1121	}
1122	/* limit is including */
1123	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1124	IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1125	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1126
1127	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1128	{
1129	/* Could be a conflict with CSAM */
1130	CSAMR3RemovePage(pVM, IDTR.pIdt);
1131	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1132	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1133
1134	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1135	IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1136	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1137	}
1138
1139	AssertRCReturn(rc, rc);
1140	}
1141
1142	/* Update saved Guest IDTR. */
1143	pVM->trpm.s.GuestIdtr = IDTR;
1144	}
1145	# endif
1146
1147	/*
1148	* Sync the interrupt gate.
1149	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1150	*/
1151	X86DESC Idte3;
1152	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1153	if (RT_FAILURE(rc))
1154	{
1155	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1156	return DBGFSTOP(pVM);
1157	}
1158	AssertRCReturn(rc, rc);
1159	if (fRawRing0)
1160	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1161	else
1162	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1163
1164	/*
1165	* Clear the FF and we're done.
1166	*/
1167	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1168	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1169	return VINF_SUCCESS;
1170	}
1171
1172
1173	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1174	/**
1175	* \#PF Handler callback for virtual access handler ranges.
1176	*
1177	* Important to realize that a physical page in a range can have aliases, and
1178	* for ALL and WRITE handlers these will also trigger.
1179	*
1180	* @returns VINF_SUCCESS if the handler have carried out the operation.
1181	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1182	* @param pVM Pointer to the VM.
1183	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1184	* @param pvPtr The HC mapping of that address.
1185	* @param pvBuf What the guest is reading/writing.
1186	* @param cbBuf How much it's reading/writing.
1187	* @param enmAccessType The access type.
1188	* @param pvUser User argument.
1189	*/
1190	static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1191	PGMACCESSTYPE enmAccessType, void *pvUser)
1192	{
1193	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1194	Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1195	NOREF(pvPtr); NOREF(pvUser); NOREF(pvBuf);
1196	Assert(!HMIsEnabled(pVM));
1197
1198	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1199	return VINF_PGM_HANDLER_DO_DEFAULT;
1200	}
1201	# endif /* TRPM_TRACK_GUEST_IDT_CHANGES */
1202
1203
1204	/**
1205	* Clear passthrough interrupt gate handler (reset to default handler)
1206	*
1207	* @returns VBox status code.
1208	* @param pVM Pointer to the VM.
1209	* @param iTrap Trap/interrupt gate number.
1210	*/
1211	int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1212	{
1213	/* Only applies to raw mode which supports only 1 VCPU. */
1214	PVMCPU pVCpu = &pVM->aCpus[0];
1215	Assert(!HMIsEnabled(pVM));
1216
1217	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1218	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1219	int rc;
1220
1221	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1222
1223	rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1224	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1225
1226	if ( iTrap < TRPM_HANDLER_INT_BASE
1227	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1228	{
1229	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1230	return VERR_INVALID_PARAMETER;
1231	}
1232	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1233
1234	/* Unmark it for relocation purposes. */
1235	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1236
1237	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1238	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1239	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1240	if (pIdte->Gen.u1Present)
1241	{
1242	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1243	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1244	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1245
1246	/*
1247	* Generic handlers have different entrypoints for each possible
1248	* vector number. These entrypoints make a sort of an array with
1249	* 8 byte entries where the vector number is the index.
1250	* See TRPMGCHandlersA.asm for details.
1251	*/
1252	Offset += iTrap * 8;
1253
1254	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1255	{
1256	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1257	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1258	pIdte->Gen.u16SegSel = SelCS;
1259	}
1260	}
1261
1262	return VINF_SUCCESS;
1263	}
1264
1265
1266	/**
1267	* Check if address is a gate handler (interrupt or trap).
1268	*
1269	* @returns gate nr or ~0 is not found
1270	*
1271	* @param pVM Pointer to the VM.
1272	* @param GCPtr GC address to check.
1273	*/
1274	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1275	{
1276	AssertReturn(!HMIsEnabled(pVM), ~0U);
1277
1278	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1279	{
1280	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1281	return iTrap;
1282
1283	/* redundant */
1284	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1285	{
1286	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1287	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1288
1289	if (pHandler == GCPtr)
1290	return iTrap;
1291	}
1292	}
1293	return ~0;
1294	}
1295
1296
1297	/**
1298	* Get guest trap/interrupt gate handler
1299	*
1300	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1301	* @param pVM Pointer to the VM.
1302	* @param iTrap Interrupt/trap number.
1303	*/
1304	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1305	{
1306	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1307	AssertReturn(!HMIsEnabled(pVM), TRPM_INVALID_HANDLER);
1308
1309	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1310	}
1311
1312
1313	/**
1314	* Set guest trap/interrupt gate handler
1315	* Used for setting up trap gates used for kernel calls.
1316	*
1317	* @returns VBox status code.
1318	* @param pVM Pointer to the VM.
1319	* @param iTrap Interrupt/trap number.
1320	* @param pHandler GC handler pointer
1321	*/
1322	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1323	{
1324	/* Only valid in raw mode which implies 1 VCPU */
1325	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1326	AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1327	PVMCPU pVCpu = &pVM->aCpus[0];
1328
1329	/*
1330	* Validate.
1331	*/
1332	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1333	{
1334	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1335	return VERR_INVALID_PARAMETER;
1336	}
1337
1338	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1339
1340	uint16_t cbIDT;
1341	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1342	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1343	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1344
1345	if (pHandler == TRPM_INVALID_HANDLER)
1346	{
1347	/* clear trap handler */
1348	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1349	return trpmClearGuestTrapHandler(pVM, iTrap);
1350	}
1351
1352	/*
1353	* Read the guest IDT entry.
1354	*/
1355	VBOXIDTE GuestIdte;
1356	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1357	if (RT_FAILURE(rc))
1358	{
1359	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1360	return rc;
1361	}
1362
1363	if ( EMIsRawRing0Enabled(pVM)
1364	&& !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1365	{
1366	/*
1367	* Only replace handlers for which we are 100% certain there won't be
1368	* any host interrupts.
1369	*
1370	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1371	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1372	*
1373	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1374	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1375	* and will therefor never assign hardware interrupts to 0x80.
1376	*
1377	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1378	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1379	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1380	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1381	* @bugref{3604}.
1382	*
1383	* PORTME - Check if your host keeps any of these gates free from hw ints.
1384	*
1385	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1386	*/
1387	/** @todo handle those dependencies better! */
1388	/** @todo Solve this in a proper manner. see @bugref{1186} */
1389	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1390	if (iTrap == 0x2E)
1391	#elif defined(RT_OS_LINUX)
1392	if (iTrap == 0x80)
1393	#else
1394	if (0)
1395	#endif
1396	{
1397	if ( GuestIdte.Gen.u1Present
1398	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1399	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1400	&& GuestIdte.Gen.u2DPL == 3)
1401	{
1402	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1403
1404	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1405	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1406	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1407	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1408	*pIdte = GuestIdte;
1409
1410	/* Mark it for relocation purposes. */
1411	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1412
1413	/* Also store it in our guest trap array. */
1414	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1415
1416	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1417	return VINF_SUCCESS;
1418	}
1419	/* ok, let's try to install a trampoline handler then. */
1420	}
1421	}
1422
1423	if ( GuestIdte.Gen.u1Present
1424	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1425	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1426	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1427	{
1428	/*
1429	* Save handler which can be used for a trampoline call inside the GC
1430	*/
1431	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1432	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1433	return VINF_SUCCESS;
1434	}
1435	return VERR_INVALID_PARAMETER;
1436	}
1437
1438
1439	/**
1440	* Check if address is a gate handler (interrupt/trap/task/anything).
1441	*
1442	* @returns True is gate handler, false if not.
1443	*
1444	* @param pVM Pointer to the VM.
1445	* @param GCPtr GC address to check.
1446	*/
1447	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1448	{
1449	/* Only valid in raw mode which implies 1 VCPU */
1450	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1451	PVMCPU pVCpu = &pVM->aCpus[0];
1452
1453	/*
1454	* Read IDTR and calc last entry.
1455	*/
1456	uint16_t cbIDT;
1457	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1458	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1459	if (!cEntries)
1460	return false;
1461	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1462
1463	/*
1464	* Outer loop: iterate pages.
1465	*/
1466	while (GCPtrIDTE <= GCPtrIDTELast)
1467	{
1468	/*
1469	* Convert this page to a HC address.
1470	* (This function checks for not-present pages.)
1471	*/
1472	PCVBOXIDTE pIDTE;
1473	PGMPAGEMAPLOCK Lock;
1474	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1475	if (RT_SUCCESS(rc))
1476	{
1477	/*
1478	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1479	* N.B. Member of the Flat Earth Society...
1480	*/
1481	while (GCPtrIDTE <= GCPtrIDTELast)
1482	{
1483	if (pIDTE->Gen.u1Present)
1484	{
1485	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1486	if (GCPtr == GCPtrHandler)
1487	{
1488	PGMPhysReleasePageMappingLock(pVM, &Lock);
1489	return true;
1490	}
1491	}
1492
1493	/* next entry */
1494	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1495	{
1496	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1497	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1498	GCPtrIDTE += sizeof(VBOXIDTE);
1499	break;
1500	}
1501	GCPtrIDTE += sizeof(VBOXIDTE);
1502	pIDTE++;
1503	}
1504	PGMPhysReleasePageMappingLock(pVM, &Lock);
1505	}
1506	else
1507	{
1508	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1509	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1510	return false;
1511	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1512	}
1513	}
1514	return false;
1515	}
1516
1517	#endif /* VBOX_WITH_RAW_MODE */
1518
1519	/**
1520	* Inject event (such as external irq or trap)
1521	*
1522	* @returns VBox status code.
1523	* @param pVM Pointer to the VM.
1524	* @param pVCpu Pointer to the VMCPU.
1525	* @param enmEvent Trpm event type
1526	*/
1527	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1528	{
1529	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1530	#ifdef VBOX_WITH_RAW_MODE
1531	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1532	#endif
1533	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1534
1535	/* Currently only useful for external hardware interrupts. */
1536	Assert(enmEvent == TRPM_HARDWARE_INT);
1537
1538	if ( !EMIsSupervisorCodeRecompiled(pVM)
1539	#ifdef VBOX_WITH_REM
1540	&& REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ
1541	#endif
1542	)
1543	{
1544	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1545
1546	# ifdef LOG_ENABLED
1547	DBGFR3_INFO_LOG(pVM, "cpumguest", "TRPMInject");
1548	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1549	# endif
1550
1551	uint8_t u8Interrupt;
1552	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1553	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1554	if (RT_SUCCESS(rc))
1555	{
1556	# ifndef IEM_VERIFICATION_MODE
1557	if (HMIsEnabled(pVM))
1558	# endif
1559	{
1560	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1561	AssertRC(rc);
1562	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1563	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1564	}
1565	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1566	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1567	{
1568	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1569	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1570	}
1571
1572	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1573	{
1574	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1575	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1576	if (rc == VINF_SUCCESS)
1577	{
1578	/* There's a handler -> let's execute it in raw mode */
1579	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1580	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1581	{
1582	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1583
1584	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1585	return VINF_EM_RESCHEDULE_RAW;
1586	}
1587	}
1588	}
1589	else
1590	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1591	# ifdef VBOX_WITH_REM
1592	REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1593	# endif
1594	}
1595	else
1596	{
1597	AssertRC(rc);
1598	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1599	}
1600	#else /* !TRPM_FORWARD_TRAPS_IN_GC */
1601	uint8_t u8Interrupt;
1602	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1603	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1604	if (RT_SUCCESS(rc))
1605	{
1606	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1607	AssertRC(rc);
1608	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1609	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1610	}
1611	#endif /* !TRPM_FORWARD_TRAPS_IN_GC */
1612	}
1613	/** @todo check if it's safe to translate the patch address to the original guest address.
1614	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1615	*/
1616	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1617
1618	/* Fall back to the recompiler */
1619	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1620	}
1621

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source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 55897

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