TRPM.cpp@ 62291

Last change on this file since 62291 was 62291, checked in by vboxsync, 8 years ago
Removed empty internal/pgm.h header file. (That stuff moved into VBox/vmm/pgm.h a long time ago. Internal APIs are using VMM_INT_DECL and similar now.)
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 78.8 KB

Line
1	/* $Id: TRPM.cpp 62291 2016-07-16 13:37:33Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72
73	/*********************************************************************************************************************************
74	* Header Files *
75	*********************************************************************************************************************************/
76	#define LOG_GROUP LOG_GROUP_TRPM
77	#include <VBox/vmm/trpm.h>
78	#include <VBox/vmm/cpum.h>
79	#include <VBox/vmm/selm.h>
80	#include <VBox/vmm/ssm.h>
81	#include <VBox/vmm/pdmapi.h>
82	#include <VBox/vmm/em.h>
83	#include <VBox/vmm/pgm.h>
84	#include <VBox/vmm/dbgf.h>
85	#include <VBox/vmm/mm.h>
86	#include <VBox/vmm/stam.h>
87	#include <VBox/vmm/csam.h>
88	#include <VBox/vmm/patm.h>
89	#include "TRPMInternal.h"
90	#include <VBox/vmm/vm.h>
91	#include <VBox/vmm/em.h>
92	#ifdef VBOX_WITH_REM
93	# include <VBox/vmm/rem.h>
94	#endif
95	#include <VBox/vmm/hm.h>
96
97	#include <VBox/err.h>
98	#include <VBox/param.h>
99	#include <VBox/log.h>
100	#include <iprt/assert.h>
101	#include <iprt/asm.h>
102	#include <iprt/string.h>
103	#include <iprt/alloc.h>
104
105
106	/*********************************************************************************************************************************
107	* Structures and Typedefs *
108	*********************************************************************************************************************************/
109	/**
110	* Trap handler function.
111	* @todo need to specialize this as we go along.
112	*/
113	typedef enum TRPMHANDLER
114	{
115	/** Generic Interrupt handler. */
116	TRPM_HANDLER_INT = 0,
117	/** Generic Trap handler. */
118	TRPM_HANDLER_TRAP,
119	/** Trap 8 (\#DF) handler. */
120	TRPM_HANDLER_TRAP_08,
121	/** Trap 12 (\#MC) handler. */
122	TRPM_HANDLER_TRAP_12,
123	/** Max. */
124	TRPM_HANDLER_MAX
125	} TRPMHANDLER, *PTRPMHANDLER;
126
127
128	/*********************************************************************************************************************************
129	* Global Variables *
130	*********************************************************************************************************************************/
131	/** Preinitialized IDT.
132	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
133	* will use to pick the right address. The u16SegSel is always VMM CS.
134	*/
135	static VBOXIDTE_GENERIC g_aIdt[256] =
136	{
137	/* special trap handler - still, this is an interrupt gate not a trap gate... */
138	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139	/* generic trap handler. */
140	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
141	/* special interrupt handler. */
142	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
143	/* generic interrupt handler. */
144	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
145	/* special task gate IDT entry (for critical exceptions like #DF). */
146	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
147	/* draft, fixme later when the handler is written. */
148	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
149
150	/* N - M M - T - C - D i */
151	/* o - n o - y - o - e p */
152	/* - e n - p - d - s t */
153	/* - i - e - e - c . */
154	/* - c - - - r */
155	/* ============================================================= */
156	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
157	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
158	#ifdef VBOX_WITH_NMI
159	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160	#else
161	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
162	#endif
163	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
164	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
165	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
166	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
167	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
168	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
169	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
170	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
171	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
172	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
173	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
174	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
175	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
176	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
177	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
178	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
179	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
180	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
190	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
191	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
192	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
414	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
415	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
416	#undef IDTE_TRAP
417	#undef IDTE_TRAP_GEN
418	#undef IDTE_INT
419	#undef IDTE_INT_GEN
420	#undef IDTE_TASK
421	#undef IDTE_UNUSED
422	#undef IDTE_RESERVED
423	};
424
425
426	/** TRPM saved state version. */
427	#define TRPM_SAVED_STATE_VERSION 9
428	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
429
430
431	/*********************************************************************************************************************************
432	* Internal Functions *
433	*********************************************************************************************************************************/
434	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
435	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
436
437
438	/**
439	* Initializes the Trap Manager
440	*
441	* @returns VBox status code.
442	* @param pVM The cross context VM structure.
443	*/
444	VMMR3DECL(int) TRPMR3Init(PVM pVM)
445	{
446	LogFlow(("TRPMR3Init\n"));
447	int rc;
448
449	/*
450	* Assert sizes and alignments.
451	*/
452	AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
453	AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
454	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
455	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
456
457	/*
458	* Initialize members.
459	*/
460	pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
461	pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
462
463	for (VMCPUID i = 0; i < pVM->cCpus; i++)
464	{
465	PVMCPU pVCpu = &pVM->aCpus[i];
466
467	pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
468	pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
469	pVCpu->trpm.s.uActiveVector = ~0U;
470	}
471
472	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
473	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
474	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
475
476	/*
477	* Read the configuration (if any).
478	*/
479	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
480	if (pTRPMNode)
481	{
482	bool f;
483	rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
484	if (RT_SUCCESS(rc))
485	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
486	}
487
488	/* write config summary to log */
489	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
490	LogRel(("TRPM: Dropping Guest IDT Monitoring\n"));
491
492	/*
493	* Initialize the IDT.
494	* The handler addresses will be set in the TRPMR3Relocate() function.
495	*/
496	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
497	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
498
499	/*
500	* Register virtual access handlers.
501	*/
502	pVM->trpm.s.hShadowIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
503	pVM->trpm.s.hGuestIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
504	#ifdef VBOX_WITH_RAW_MODE
505	if (!HMIsEnabled(pVM))
506	{
507	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
508	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
509	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
510	NULL /pszHandlerRC/, "trpmRCShadowIDTWritePfHandler",
511	"Shadow IDT write access handler", &pVM->trpm.s.hShadowIdtWriteHandlerType);
512	AssertRCReturn(rc, rc);
513	# endif
514	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
515	NULL /pfnInvalidateR3/, trpmGuestIDTWriteHandler,
516	"trpmGuestIDTWriteHandler", "trpmRCGuestIDTWritePfHandler",
517	"Guest IDT write access handler", &pVM->trpm.s.hGuestIdtWriteHandlerType);
518	AssertRCReturn(rc, rc);
519	}
520	#endif /* VBOX_WITH_RAW_MODE */
521
522	/*
523	* Register the saved state data unit.
524	*/
525	rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
526	NULL, NULL, NULL,
527	NULL, trpmR3Save, NULL,
528	NULL, trpmR3Load, NULL);
529	if (RT_FAILURE(rc))
530	return rc;
531
532	/*
533	* Statistics.
534	*/
535	#ifdef VBOX_WITH_RAW_MODE
536	if (!HMIsEnabled(pVM))
537	{
538	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
539	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
540	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
541
542	/* traps */
543	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
544	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
545	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
546	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
547	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
548	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
549	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
550	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
551	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
552	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
553	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
554	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
555	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
556	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
557	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
558	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
559	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
560	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
561	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
562	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
563	}
564	#endif
565
566	# ifdef VBOX_WITH_STATISTICS
567	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
568	AssertRCReturn(rc, rc);
569	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
570	for (unsigned i = 0; i < 256; i++)
571	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
572	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
573
574	# ifdef VBOX_WITH_RAW_MODE
575	if (!HMIsEnabled(pVM))
576	{
577	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
578	AssertRCReturn(rc, rc);
579	pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
580	for (unsigned i = 0; i < 256; i++)
581	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
582	"Host interrupts.", "/TRPM/HostIRQs/%02x", i);
583	}
584	# endif
585	# endif
586
587	#ifdef VBOX_WITH_RAW_MODE
588	if (!HMIsEnabled(pVM))
589	{
590	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
591	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
592	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
593	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
594	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
595	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
596
597	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
598	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
599	}
600	#endif
601
602	#ifdef VBOX_WITH_RAW_MODE
603	/*
604	* Default action when entering raw mode for the first time
605	*/
606	if (!HMIsEnabled(pVM))
607	{
608	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
609	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
610	}
611	#endif
612	return 0;
613	}
614
615
616	/**
617	* Applies relocations to data and code managed by this component.
618	*
619	* This function will be called at init and whenever the VMM need
620	* to relocate itself inside the GC.
621	*
622	* @param pVM The cross context VM structure.
623	* @param offDelta Relocation delta relative to old location.
624	*/
625	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
626	{
627	#ifdef VBOX_WITH_RAW_MODE
628	if (HMIsEnabled(pVM))
629	return;
630
631	/* Only applies to raw mode which supports only 1 VCPU. */
632	PVMCPU pVCpu = &pVM->aCpus[0];
633	LogFlow(("TRPMR3Relocate\n"));
634
635	/*
636	* Get the trap handler addresses.
637	*
638	* If VMMRC.rc is screwed, so are we. We'll assert here since it elsewise
639	* would make init order impossible if we should assert the presence of these
640	* exports in TRPMR3Init().
641	*/
642	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
643	RT_ZERO(aRCPtrs);
644	int rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
645	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
646
647	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
648	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMRC.rc!\n"));
649
650	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
651	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMRC.rc!\n"));
652
653	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
654	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMRC.rc!\n"));
655
656	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
657
658	/*
659	* Iterate the idt and set the addresses.
660	*/
661	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
662	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
663	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
664	{
665	if ( pIdte->Gen.u1Present
666	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
667	)
668	{
669	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
670	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
671	switch (pIdteTemplate->u16OffsetLow)
672	{
673	/*
674	* Generic handlers have different entrypoints for each possible
675	* vector number. These entrypoints makes a sort of an array with
676	* 8 byte entries where the vector number is the index.
677	* See TRPMGCHandlersA.asm for details.
678	*/
679	case TRPM_HANDLER_INT:
680	case TRPM_HANDLER_TRAP:
681	Offset += i * 8;
682	break;
683	case TRPM_HANDLER_TRAP_12:
684	break;
685	case TRPM_HANDLER_TRAP_08:
686	/* Handle #DF Task Gate in special way. */
687	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
688	pIdte->Gen.u16OffsetLow = 0;
689	pIdte->Gen.u16OffsetHigh = 0;
690	SELMSetTrap8EIP(pVM, Offset);
691	continue;
692	}
693	/* (non-task gates only ) */
694	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
695	pIdte->Gen.u16OffsetHigh = Offset >> 16;
696	pIdte->Gen.u16SegSel = SelCS;
697	}
698	}
699
700	/*
701	* Update IDTR (limit is including!).
702	*/
703	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
704
705	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
706	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
707	{
708	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.pvMonShwIdtRC, true /fHypervisor/);
709	AssertRC(rc);
710	}
711	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
712	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hShadowIdtWriteHandlerType,
713	pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
714	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
715	AssertRC(rc);
716	# endif
717
718	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
719	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
720	{
721	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
722	{
723	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
724	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
725	}
726
727	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
728	{
729	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
730	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
731
732	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
733	pHandler += offDelta;
734
735	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
736	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
737	}
738	}
739
740	# ifdef VBOX_WITH_STATISTICS
741	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
742	pVM->trpm.s.paStatHostIrqRC += offDelta;
743	# endif
744	#endif /* VBOX_WITH_RAW_MODE */
745	}
746
747
748	/**
749	* Terminates the Trap Manager
750	*
751	* @returns VBox status code.
752	* @param pVM The cross context VM structure.
753	*/
754	VMMR3DECL(int) TRPMR3Term(PVM pVM)
755	{
756	NOREF(pVM);
757	return VINF_SUCCESS;
758	}
759
760
761	/**
762	* Resets a virtual CPU.
763	*
764	* Used by TRPMR3Reset and CPU hot plugging.
765	*
766	* @param pVCpu The cross context virtual CPU structure.
767	*/
768	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
769	{
770	pVCpu->trpm.s.uActiveVector = ~0U;
771	}
772
773
774	/**
775	* The VM is being reset.
776	*
777	* For the TRPM component this means that any IDT write monitors
778	* needs to be removed, any pending trap cleared, and the IDT reset.
779	*
780	* @param pVM The cross context VM structure.
781	*/
782	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
783	{
784	/*
785	* Deregister any virtual handlers.
786	*/
787	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
788	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
789	{
790	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
791	{
792	int rc = PGMHandlerVirtualDeregister(pVM, VMMGetCpu(pVM), pVM->trpm.s.GuestIdtr.pIdt, false /fHypervisor/);
793	AssertRC(rc);
794	}
795	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
796	}
797	pVM->trpm.s.GuestIdtr.cbIdt = 0;
798	#endif
799
800	/*
801	* Reinitialize other members calling the relocator to get things right.
802	*/
803	for (VMCPUID i = 0; i < pVM->cCpus; i++)
804	TRPMR3ResetCpu(&pVM->aCpus[i]);
805	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
806	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
807	TRPMR3Relocate(pVM, 0);
808
809	#ifdef VBOX_WITH_RAW_MODE
810	/*
811	* Default action when entering raw mode for the first time
812	*/
813	if (!HMIsEnabled(pVM))
814	{
815	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
816	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
817	}
818	#endif
819	}
820
821
822	# ifdef VBOX_WITH_RAW_MODE
823	/**
824	* Resolve a builtin RC symbol.
825	*
826	* Called by PDM when loading or relocating RC modules.
827	*
828	* @returns VBox status
829	* @param pVM The cross context VM structure.
830	* @param pszSymbol Symbol to resolv
831	* @param pRCPtrValue Where to store the symbol value.
832	*
833	* @remark This has to work before VMMR3Relocate() is called.
834	*/
835	VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
836	{
837	if (!strcmp(pszSymbol, "g_TRPM"))
838	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
839	else if (!strcmp(pszSymbol, "g_TRPMCPU"))
840	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
841	else if (!strcmp(pszSymbol, "g_trpmGuestCtx"))
842	{
843	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
844	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
845	}
846	else if (!strcmp(pszSymbol, "g_trpmHyperCtx"))
847	{
848	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
849	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
850	}
851	else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
852	{
853	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
854	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
855	}
856	else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
857	{
858	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
859	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
860	}
861	else
862	return VERR_SYMBOL_NOT_FOUND;
863	return VINF_SUCCESS;
864	}
865	#endif /* VBOX_WITH_RAW_MODE */
866
867
868	/**
869	* Execute state save operation.
870	*
871	* @returns VBox status code.
872	* @param pVM The cross context VM structure.
873	* @param pSSM SSM operation handle.
874	*/
875	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
876	{
877	PTRPM pTrpm = &pVM->trpm.s;
878	LogFlow(("trpmR3Save:\n"));
879
880	/*
881	* Active and saved traps.
882	*/
883	for (VMCPUID i = 0; i < pVM->cCpus; i++)
884	{
885	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
886	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
887	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
888	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
889	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
890	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
891	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
892	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
893	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
894	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
895	}
896	SSMR3PutBool(pSSM, HMIsEnabled(pVM));
897	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
898	SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT), 0));
899	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
900	SSMR3PutU32(pSSM, ~0); /* separator. */
901
902	/*
903	* Save any trampoline gates.
904	*/
905	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
906	{
907	if (pTrpm->aGuestTrapHandler[iTrap])
908	{
909	SSMR3PutU32(pSSM, iTrap);
910	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
911	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
912	}
913	}
914
915	return SSMR3PutU32(pSSM, ~0); /* terminator */
916	}
917
918
919	/**
920	* Execute state load operation.
921	*
922	* @returns VBox status code.
923	* @param pVM The cross context VM structure.
924	* @param pSSM SSM operation handle.
925	* @param uVersion Data layout version.
926	* @param uPass The data pass.
927	*/
928	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
929	{
930	LogFlow(("trpmR3Load:\n"));
931	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
932
933	/*
934	* Validate version.
935	*/
936	if ( uVersion != TRPM_SAVED_STATE_VERSION
937	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
938	{
939	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
940	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
941	}
942
943	/*
944	* Call the reset function to kick out any handled gates and other potential trouble.
945	*/
946	TRPMR3Reset(pVM);
947
948	/*
949	* Active and saved traps.
950	*/
951	PTRPM pTrpm = &pVM->trpm.s;
952
953	if (uVersion == TRPM_SAVED_STATE_VERSION)
954	{
955	for (VMCPUID i = 0; i < pVM->cCpus; i++)
956	{
957	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
958	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
959	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
960	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
961	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
962	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
963	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
964	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
965	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
966	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
967	}
968
969	bool fIgnored;
970	SSMR3GetBool(pSSM, &fIgnored);
971	}
972	else
973	{
974	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
975	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
976	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
977	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
978	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
979	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
980	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
981	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
982	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
983	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
984
985	RTGCUINT fIgnored;
986	SSMR3GetGCUInt(pSSM, &fIgnored);
987	}
988
989	RTUINT fSyncIDT;
990	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
991	if (RT_FAILURE(rc))
992	return rc;
993	if (fSyncIDT & ~1)
994	{
995	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
996	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
997	}
998	#ifdef VBOX_WITH_RAW_MODE
999	if (fSyncIDT)
1000	{
1001	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
1002	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1003	}
1004	/* else: cleared by reset call above. */
1005	#endif
1006
1007	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
1008
1009	/* check the separator */
1010	uint32_t u32Sep;
1011	rc = SSMR3GetU32(pSSM, &u32Sep);
1012	if (RT_FAILURE(rc))
1013	return rc;
1014	if (u32Sep != (uint32_t)~0)
1015	{
1016	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1017	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1018	}
1019
1020	/*
1021	* Restore any trampoline gates.
1022	*/
1023	for (;;)
1024	{
1025	/* gate number / terminator */
1026	uint32_t iTrap;
1027	rc = SSMR3GetU32(pSSM, &iTrap);
1028	if (RT_FAILURE(rc))
1029	return rc;
1030	if (iTrap == (uint32_t)~0)
1031	break;
1032	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
1033	\|\| pTrpm->aGuestTrapHandler[iTrap])
1034	{
1035	AssertMsgFailed(("iTrap=%#x\n", iTrap));
1036	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1037	}
1038
1039	/* restore the IDT entry. */
1040	RTGCPTR GCPtrHandler;
1041	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1042	VBOXIDTE Idte;
1043	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1044	if (RT_FAILURE(rc))
1045	return rc;
1046	Assert(GCPtrHandler);
1047	pTrpm->aIdt[iTrap] = Idte;
1048	}
1049
1050	return VINF_SUCCESS;
1051	}
1052
1053	#ifdef VBOX_WITH_RAW_MODE
1054
1055	/**
1056	* Check if gate handlers were updated
1057	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1058	*
1059	* @returns VBox status code.
1060	* @param pVM The cross context VM structure.
1061	* @param pVCpu The cross context virtual CPU structure.
1062	*/
1063	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1064	{
1065	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1066	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1067	int rc;
1068
1069	AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1070
1071	if (fRawRing0 && CSAMIsEnabled(pVM))
1072	{
1073	/* Clear all handlers */
1074	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1075	/** @todo inefficient, but simple */
1076	for (unsigned iGate = 0; iGate < 256; iGate++)
1077	trpmClearGuestTrapHandler(pVM, iGate);
1078
1079	/* Scan them all (only the first time) */
1080	CSAMR3CheckGates(pVM, 0, 256);
1081	}
1082
1083	/*
1084	* Get the IDTR.
1085	*/
1086	VBOXIDTR IDTR;
1087	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1088	if (!IDTR.cbIdt)
1089	{
1090	Log(("No IDT entries...\n"));
1091	return DBGFSTOP(pVM);
1092	}
1093
1094	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1095	/*
1096	* Check if Guest's IDTR has changed.
1097	*/
1098	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1099	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1100	{
1101	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1102	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1103	{
1104	/*
1105	* [Re]Register write virtual handler for guest's IDT.
1106	*/
1107	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1108	{
1109	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.GuestIdtr.pIdt, false /fHypervisor/);
1110	AssertRCReturn(rc, rc);
1111	}
1112	/* limit is including */
1113	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1114	IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1115	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1116
1117	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1118	{
1119	/* Could be a conflict with CSAM */
1120	CSAMR3RemovePage(pVM, IDTR.pIdt);
1121	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1122	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1123
1124	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1125	IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1126	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1127	}
1128
1129	AssertRCReturn(rc, rc);
1130	}
1131
1132	/* Update saved Guest IDTR. */
1133	pVM->trpm.s.GuestIdtr = IDTR;
1134	}
1135	# endif
1136
1137	/*
1138	* Sync the interrupt gate.
1139	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1140	*/
1141	X86DESC Idte3;
1142	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1143	if (RT_FAILURE(rc))
1144	{
1145	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1146	return DBGFSTOP(pVM);
1147	}
1148	AssertRCReturn(rc, rc);
1149	if (fRawRing0)
1150	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1151	else
1152	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1153
1154	/*
1155	* Clear the FF and we're done.
1156	*/
1157	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1158	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1159	return VINF_SUCCESS;
1160	}
1161
1162
1163	/**
1164	* Clear passthrough interrupt gate handler (reset to default handler)
1165	*
1166	* @returns VBox status code.
1167	* @param pVM The cross context VM structure.
1168	* @param iTrap Trap/interrupt gate number.
1169	*/
1170	int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1171	{
1172	/* Only applies to raw mode which supports only 1 VCPU. */
1173	PVMCPU pVCpu = &pVM->aCpus[0];
1174	Assert(!HMIsEnabled(pVM));
1175
1176	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1177	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1178	int rc;
1179
1180	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1181
1182	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1183	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
1184
1185	if ( iTrap < TRPM_HANDLER_INT_BASE
1186	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1187	{
1188	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1189	return VERR_INVALID_PARAMETER;
1190	}
1191	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1192
1193	/* Unmark it for relocation purposes. */
1194	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1195
1196	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1197	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1198	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1199	if (pIdte->Gen.u1Present)
1200	{
1201	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1202	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1203	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1204
1205	/*
1206	* Generic handlers have different entrypoints for each possible
1207	* vector number. These entrypoints make a sort of an array with
1208	* 8 byte entries where the vector number is the index.
1209	* See TRPMGCHandlersA.asm for details.
1210	*/
1211	Offset += iTrap * 8;
1212
1213	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1214	{
1215	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1216	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1217	pIdte->Gen.u16SegSel = SelCS;
1218	}
1219	}
1220
1221	return VINF_SUCCESS;
1222	}
1223
1224
1225	/**
1226	* Check if address is a gate handler (interrupt or trap).
1227	*
1228	* @returns gate nr or ~0 is not found
1229	*
1230	* @param pVM The cross context VM structure.
1231	* @param GCPtr GC address to check.
1232	*/
1233	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1234	{
1235	AssertReturn(!HMIsEnabled(pVM), ~0U);
1236
1237	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1238	{
1239	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1240	return iTrap;
1241
1242	/* redundant */
1243	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1244	{
1245	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1246	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1247
1248	if (pHandler == GCPtr)
1249	return iTrap;
1250	}
1251	}
1252	return ~0;
1253	}
1254
1255
1256	/**
1257	* Get guest trap/interrupt gate handler
1258	*
1259	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1260	* @param pVM The cross context VM structure.
1261	* @param iTrap Interrupt/trap number.
1262	*/
1263	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1264	{
1265	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1266	AssertReturn(!HMIsEnabled(pVM), TRPM_INVALID_HANDLER);
1267
1268	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1269	}
1270
1271
1272	/**
1273	* Set guest trap/interrupt gate handler
1274	* Used for setting up trap gates used for kernel calls.
1275	*
1276	* @returns VBox status code.
1277	* @param pVM The cross context VM structure.
1278	* @param iTrap Interrupt/trap number.
1279	* @param pHandler GC handler pointer
1280	*/
1281	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1282	{
1283	/* Only valid in raw mode which implies 1 VCPU */
1284	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1285	AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1286	PVMCPU pVCpu = &pVM->aCpus[0];
1287
1288	/*
1289	* Validate.
1290	*/
1291	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1292	{
1293	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1294	return VERR_INVALID_PARAMETER;
1295	}
1296
1297	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1298
1299	uint16_t cbIDT;
1300	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1301	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1302	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1303
1304	if (pHandler == TRPM_INVALID_HANDLER)
1305	{
1306	/* clear trap handler */
1307	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1308	return trpmClearGuestTrapHandler(pVM, iTrap);
1309	}
1310
1311	/*
1312	* Read the guest IDT entry.
1313	*/
1314	VBOXIDTE GuestIdte;
1315	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1316	if (RT_FAILURE(rc))
1317	{
1318	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1319	return rc;
1320	}
1321
1322	if ( EMIsRawRing0Enabled(pVM)
1323	&& !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1324	{
1325	/*
1326	* Only replace handlers for which we are 100% certain there won't be
1327	* any host interrupts.
1328	*
1329	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1330	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1331	*
1332	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1333	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1334	* and will therefor never assign hardware interrupts to 0x80.
1335	*
1336	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1337	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1338	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1339	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1340	* @bugref{3604}.
1341	*
1342	* PORTME - Check if your host keeps any of these gates free from hw ints.
1343	*
1344	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1345	*/
1346	/** @todo handle those dependencies better! */
1347	/** @todo Solve this in a proper manner. see @bugref{1186} */
1348	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1349	if (iTrap == 0x2E)
1350	#elif defined(RT_OS_LINUX)
1351	if (iTrap == 0x80)
1352	#else
1353	if (0)
1354	#endif
1355	{
1356	if ( GuestIdte.Gen.u1Present
1357	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1358	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1359	&& GuestIdte.Gen.u2DPL == 3)
1360	{
1361	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1362
1363	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1364	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1365	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1366	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1367	*pIdte = GuestIdte;
1368
1369	/* Mark it for relocation purposes. */
1370	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1371
1372	/* Also store it in our guest trap array. */
1373	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1374
1375	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1376	return VINF_SUCCESS;
1377	}
1378	/* ok, let's try to install a trampoline handler then. */
1379	}
1380	}
1381
1382	if ( GuestIdte.Gen.u1Present
1383	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1384	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1385	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1386	{
1387	/*
1388	* Save handler which can be used for a trampoline call inside the GC
1389	*/
1390	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1391	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1392	return VINF_SUCCESS;
1393	}
1394	return VERR_INVALID_PARAMETER;
1395	}
1396
1397
1398	/**
1399	* Check if address is a gate handler (interrupt/trap/task/anything).
1400	*
1401	* @returns True is gate handler, false if not.
1402	*
1403	* @param pVM The cross context VM structure.
1404	* @param GCPtr GC address to check.
1405	*/
1406	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1407	{
1408	/* Only valid in raw mode which implies 1 VCPU */
1409	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1410	PVMCPU pVCpu = &pVM->aCpus[0];
1411
1412	/*
1413	* Read IDTR and calc last entry.
1414	*/
1415	uint16_t cbIDT;
1416	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1417	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1418	if (!cEntries)
1419	return false;
1420	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1421
1422	/*
1423	* Outer loop: iterate pages.
1424	*/
1425	while (GCPtrIDTE <= GCPtrIDTELast)
1426	{
1427	/*
1428	* Convert this page to a HC address.
1429	* (This function checks for not-present pages.)
1430	*/
1431	PCVBOXIDTE pIDTE;
1432	PGMPAGEMAPLOCK Lock;
1433	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1434	if (RT_SUCCESS(rc))
1435	{
1436	/*
1437	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1438	* N.B. Member of the Flat Earth Society...
1439	*/
1440	while (GCPtrIDTE <= GCPtrIDTELast)
1441	{
1442	if (pIDTE->Gen.u1Present)
1443	{
1444	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1445	if (GCPtr == GCPtrHandler)
1446	{
1447	PGMPhysReleasePageMappingLock(pVM, &Lock);
1448	return true;
1449	}
1450	}
1451
1452	/* next entry */
1453	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1454	{
1455	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1456	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1457	GCPtrIDTE += sizeof(VBOXIDTE);
1458	break;
1459	}
1460	GCPtrIDTE += sizeof(VBOXIDTE);
1461	pIDTE++;
1462	}
1463	PGMPhysReleasePageMappingLock(pVM, &Lock);
1464	}
1465	else
1466	{
1467	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1468	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1469	return false;
1470	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1471	}
1472	}
1473	return false;
1474	}
1475
1476	#endif /* VBOX_WITH_RAW_MODE */
1477
1478	/**
1479	* Inject event (such as external irq or trap)
1480	*
1481	* @returns VBox status code.
1482	* @param pVM The cross context VM structure.
1483	* @param pVCpu The cross context virtual CPU structure.
1484	* @param enmEvent Trpm event type
1485	*/
1486	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1487	{
1488	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1489	#ifdef VBOX_WITH_RAW_MODE
1490	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1491	#endif
1492	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1493
1494	/* Currently only useful for external hardware interrupts. */
1495	Assert(enmEvent == TRPM_HARDWARE_INT);
1496
1497	if (!EMIsSupervisorCodeRecompiled(pVM))
1498	{
1499	#ifdef TRPM_FORWARD_TRAPS_IN_GC
1500
1501	# ifdef LOG_ENABLED
1502	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "TRPMInject");
1503	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1504	# endif
1505
1506	uint8_t u8Interrupt = 0;
1507	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1508	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1509	if (RT_SUCCESS(rc))
1510	{
1511	# ifndef IEM_VERIFICATION_MODE
1512	if (HMIsEnabled(pVM))
1513	# endif
1514	{
1515	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1516	AssertRC(rc);
1517	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1518	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1519	}
1520	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1521	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1522	{
1523	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1524	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1525	}
1526
1527	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1528	{
1529	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1530	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1531	if (rc == VINF_SUCCESS)
1532	{
1533	/* There's a handler -> let's execute it in raw mode */
1534	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1535	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1536	{
1537	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1538
1539	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1540	return VINF_EM_RESCHEDULE_RAW;
1541	}
1542	}
1543	}
1544	else
1545	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1546
1547	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1548	AssertRCReturn(rc, rc);
1549	}
1550	else
1551	{
1552	/* Can happen if the interrupt is masked by TPR or APIC is disabled. */
1553	AssertMsg(rc == VERR_APIC_INTR_MASKED_BY_TPR \|\| rc == VERR_NO_DATA, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
1554	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1555	}
1556	#else /* !TRPM_FORWARD_TRAPS_IN_GC */
1557	uint8_t u8Interrupt = 0;
1558	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1559	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1560	if (RT_SUCCESS(rc))
1561	{
1562	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1563	AssertRC(rc);
1564	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1565	}
1566	else
1567	{
1568	/* Can happen if the interrupt is masked by TPR or APIC is disabled. */
1569	AssertMsg(rc == VERR_APIC_INTR_MASKED_BY_TPR \|\| rc == VERR_NO_DATA, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
1570	}
1571	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1572	#endif /* !TRPM_FORWARD_TRAPS_IN_GC */
1573	}
1574	/** @todo check if it's safe to translate the patch address to the original guest address.
1575	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1576	*/
1577	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1578
1579	/* Fall back to the recompiler */
1580	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1581	}
1582

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 62291

Download in other formats: