VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 68155

Last change on this file since 68155 was 64828, checked in by vboxsync, 8 years ago

VMM/TRPM: fixed warning
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 80.7 KB
Line 
1/* $Id: TRPM.cpp 64828 2016-12-11 09:59:51Z vboxsync $ */
2/** @file
3 * TRPM - The Trap Monitor.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_trpm TRPM - The Trap Monitor
19 *
20 * The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21 * the VMM. It plays a major role in raw-mode execution and a lesser one in the
22 * hardware assisted mode.
23 *
24 * Note first, the following will use trap as a collective term for faults,
25 * aborts and traps.
26 *
27 * @see grp_trpm
28 *
29 *
30 * @section sec_trpm_rc Raw-Mode Context
31 *
32 * When executing in the raw-mode context, TRPM will be managing the IDT and
33 * processing all traps and interrupts. It will also monitor the guest IDT
34 * because CSAM wishes to know about changes to it (trap/interrupt/syscall
35 * handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36 * considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37 *
38 * External interrupts will be forwarded to the host context by the quickest
39 * possible route where they will be reasserted. The other events will be
40 * categorized into virtualization traps, genuine guest traps and hypervisor
41 * traps. The latter group may be recoverable depending on when they happen and
42 * whether there is a handler for it, otherwise it will cause a guru meditation.
43 *
44 * TRPM distinguishes the between the first two (virt and guest traps) and the
45 * latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46 * it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47 * dispatcher tables, one ad-hoc for one time traps registered via
48 * TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49 * The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50 *
51 * The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52 * part), will call up the other VMM sub-systems depending on what it things
53 * happens. The two most busy traps are page faults (\#PF) and general
54 * protection fault/trap (\#GP).
55 *
56 * Before resuming guest code after having taken a virtualization trap or
57 * injected a guest trap, TRPM will check for pending forced action and
58 * every now and again let TM check for timed out timers. This allows code that
59 * is being executed as part of virtualization traps to signal ring-3 exits,
60 * page table resyncs and similar without necessarily using the status code. It
61 * also make sure we're more responsive to timers and requests from other
62 * threads (necessarily running on some different core/cpu in most cases).
63 *
64 *
65 * @section sec_trpm_all All Contexts
66 *
67 * TRPM will also dispatch / inject interrupts and traps to the guest, both when
68 * in raw-mode and when in hardware assisted mode. See TRPMInject().
69 *
70 */
71
72
73/*********************************************************************************************************************************
74* Header Files *
75*********************************************************************************************************************************/
76#define LOG_GROUP LOG_GROUP_TRPM
77#include <VBox/vmm/trpm.h>
78#include <VBox/vmm/cpum.h>
79#include <VBox/vmm/selm.h>
80#include <VBox/vmm/ssm.h>
81#include <VBox/vmm/pdmapi.h>
82#include <VBox/vmm/em.h>
83#include <VBox/vmm/pgm.h>
84#include <VBox/vmm/dbgf.h>
85#include <VBox/vmm/mm.h>
86#include <VBox/vmm/stam.h>
87#include <VBox/vmm/csam.h>
88#include <VBox/vmm/patm.h>
89#include "TRPMInternal.h"
90#include <VBox/vmm/vm.h>
91#include <VBox/vmm/em.h>
92#ifdef VBOX_WITH_REM
93# include <VBox/vmm/rem.h>
94#endif
95#include <VBox/vmm/hm.h>
96
97#include <VBox/err.h>
98#include <VBox/param.h>
99#include <VBox/log.h>
100#include <iprt/assert.h>
101#include <iprt/asm.h>
102#include <iprt/string.h>
103#include <iprt/alloc.h>
104
105
106/*********************************************************************************************************************************
107* Structures and Typedefs *
108*********************************************************************************************************************************/
109/**
110 * Trap handler function.
111 * @todo need to specialize this as we go along.
112 */
113typedef enum TRPMHANDLER
114{
115 /** Generic Interrupt handler. */
116 TRPM_HANDLER_INT = 0,
117 /** Generic Trap handler. */
118 TRPM_HANDLER_TRAP,
119 /** Trap 8 (\#DF) handler. */
120 TRPM_HANDLER_TRAP_08,
121 /** Trap 12 (\#MC) handler. */
122 TRPM_HANDLER_TRAP_12,
123 /** Max. */
124 TRPM_HANDLER_MAX
125} TRPMHANDLER, *PTRPMHANDLER;
126
127
128/*********************************************************************************************************************************
129* Global Variables *
130*********************************************************************************************************************************/
131/** Preinitialized IDT.
132 * The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
133 * will use to pick the right address. The u16SegSel is always VMM CS.
134 */
135static VBOXIDTE_GENERIC g_aIdt[256] =
136{
137/* special trap handler - still, this is an interrupt gate not a trap gate... */
138#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139/* generic trap handler. */
140#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
141/* special interrupt handler. */
142#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
143/* generic interrupt handler. */
144#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
145/* special task gate IDT entry (for critical exceptions like #DF). */
146#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
147/* draft, fixme later when the handler is written. */
148#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
149
150 /* N - M M - T - C - D i */
151 /* o - n o - y - o - e p */
152 /* - e n - p - d - s t */
153 /* - i - e - e - c . */
154 /* - c - - - r */
155 /* ============================================================= */
156 IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
157 IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
158#ifdef VBOX_WITH_NMI
159 IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
160#else
161 IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
162#endif
163 IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
164 IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
165 IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
166 IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
167 IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
168 IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
169 IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
170 IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
171 IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
172 IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
173 IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
174 IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
175 IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
176 IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
177 IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
178 IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
179 IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
180 IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
181 IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
182 IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
183 IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
184 IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
185 IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
186 IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
187 IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
188 IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
189 IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
190 IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
191 IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
192 IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
193 IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
194 IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
195 IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
196 IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
197 IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
198 IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
199 IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
200 IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
201 IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
202 IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
203 IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
204 IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
205 IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
206 IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
207 IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
208 IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
209 IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
210 IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
211 IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
212 IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
213 IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
214 IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
215 IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
216 IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
217 IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
218 IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
219 IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
220 IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
221 IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
222 IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
223 IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
224 IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
225 IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
226 IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
227 IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
228 IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
229 IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
230 IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
231 IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
232 IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
233 IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
234 IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
235 IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
236 IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
237 IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
238 IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
239 IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
240 IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
241 IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
242 IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
243 IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
244 IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
245 IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
246 IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
247 IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
248 IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
249 IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
250 IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
251 IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
252 IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
253 IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
254 IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
255 IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
256 IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
257 IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
258 IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
259 IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
260 IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
261 IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
262 IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
263 IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
264 IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
265 IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
266 IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
267 IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
268 IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
269 IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
270 IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
271 IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
272 IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
273 IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
274 IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
275 IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
276 IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
277 IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
278 IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
279 IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
280 IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
281 IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
282 IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
283 IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
284 IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
285 IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
286 IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
287 IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
288 IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
289 IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
290 IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
291 IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
292 IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
293 IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
294 IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
295 IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
296 IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
297 IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
298 IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
299 IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
300 IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
301 IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
302 IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
303 IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
304 IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
305 IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
306 IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
307 IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
308 IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
309 IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
310 IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
311 IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
312 IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
313 IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
314 IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
315 IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
316 IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
317 IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
318 IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
319 IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
320 IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
321 IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
322 IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
323 IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
324 IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
325 IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
326 IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
327 IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
328 IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
329 IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
330 IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
331 IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
332 IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
333 IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
334 IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
335 IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
336 IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
337 IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
338 IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
339 IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
340 IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
341 IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
342 IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
343 IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
344 IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
345 IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
346 IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
347 IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
348 IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
349 IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
350 IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
351 IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
352 IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
353 IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
354 IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
355 IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
356 IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
357 IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
358 IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
359 IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
360 IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
361 IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
362 IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
363 IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
364 IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
365 IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
366 IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
367 IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
368 IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
369 IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
370 IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
371 IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
372 IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
373 IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
374 IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
375 IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
376 IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
377 IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
378 IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
379 IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
380 IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
381 IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
382 IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
383 IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
384 IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
385 IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
386 IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
387 IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
388 IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
389 IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
390 IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
391 IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
392 IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
393 IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
394 IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
395 IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
396 IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
397 IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
398 IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
399 IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
400 IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
401 IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
402 IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
403 IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
404 IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
405 IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
406 IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
407 IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
408 IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
409 IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
410 IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
411 IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
412 IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
413 IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
414 IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
415 IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
416#undef IDTE_TRAP
417#undef IDTE_TRAP_GEN
418#undef IDTE_INT
419#undef IDTE_INT_GEN
420#undef IDTE_TASK
421#undef IDTE_UNUSED
422#undef IDTE_RESERVED
423};
424
425
426/** TRPM saved state version. */
427#define TRPM_SAVED_STATE_VERSION 9
428#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
429
430
431/*********************************************************************************************************************************
432* Internal Functions *
433*********************************************************************************************************************************/
434static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
435static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
436static DECLCALLBACK(void) trpmR3InfoEvent(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
437
438
439/**
440 * Initializes the Trap Manager
441 *
442 * @returns VBox status code.
443 * @param pVM The cross context VM structure.
444 */
445VMMR3DECL(int) TRPMR3Init(PVM pVM)
446{
447 LogFlow(("TRPMR3Init\n"));
448 int rc;
449
450 /*
451 * Assert sizes and alignments.
452 */
453 AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
454 AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
455 AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
456 AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
457
458 /*
459 * Initialize members.
460 */
461 pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
462 pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
463
464 for (VMCPUID i = 0; i < pVM->cCpus; i++)
465 {
466 PVMCPU pVCpu = &pVM->aCpus[i];
467
468 pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
469 pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
470 pVCpu->trpm.s.uActiveVector = ~0U;
471 }
472
473 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
474 pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
475 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
476
477 /*
478 * Read the configuration (if any).
479 */
480 PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
481 if (pTRPMNode)
482 {
483 bool f;
484 rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
485 if (RT_SUCCESS(rc))
486 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
487 }
488
489 /* write config summary to log */
490 if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
491 LogRel(("TRPM: Dropping Guest IDT Monitoring\n"));
492
493 /*
494 * Initialize the IDT.
495 * The handler addresses will be set in the TRPMR3Relocate() function.
496 */
497 Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
498 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
499
500 /*
501 * Register virtual access handlers.
502 */
503 pVM->trpm.s.hShadowIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
504 pVM->trpm.s.hGuestIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
505#ifdef VBOX_WITH_RAW_MODE
506 if (!HMIsEnabled(pVM))
507 {
508# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
509 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /*fRelocUserRC*/,
510 NULL /*pfnInvalidateR3*/, NULL /*pfnHandlerR3*/,
511 NULL /*pszHandlerRC*/, "trpmRCShadowIDTWritePfHandler",
512 "Shadow IDT write access handler", &pVM->trpm.s.hShadowIdtWriteHandlerType);
513 AssertRCReturn(rc, rc);
514# endif
515 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /*fRelocUserRC*/,
516 NULL /*pfnInvalidateR3*/, trpmGuestIDTWriteHandler,
517 "trpmGuestIDTWriteHandler", "trpmRCGuestIDTWritePfHandler",
518 "Guest IDT write access handler", &pVM->trpm.s.hGuestIdtWriteHandlerType);
519 AssertRCReturn(rc, rc);
520 }
521#endif /* VBOX_WITH_RAW_MODE */
522
523 /*
524 * Register the saved state data unit.
525 */
526 rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
527 NULL, NULL, NULL,
528 NULL, trpmR3Save, NULL,
529 NULL, trpmR3Load, NULL);
530 if (RT_FAILURE(rc))
531 return rc;
532
533 /*
534 * Register info handlers.
535 */
536 rc = DBGFR3InfoRegisterInternalEx(pVM, "trpmevent", "Dumps TRPM pending event.", trpmR3InfoEvent,
537 DBGFINFO_FLAGS_ALL_EMTS);
538 AssertRCReturn(rc, rc);
539
540 /*
541 * Statistics.
542 */
543#ifdef VBOX_WITH_RAW_MODE
544 if (!HMIsEnabled(pVM))
545 {
546 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
547 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
548 STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
549
550 /* traps */
551 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
552 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
553 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
554 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
555 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
556 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
557 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
558 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
559 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
560 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
561 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
562 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
563 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
564 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
565 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
566 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
567 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
568 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
569 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
570 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
571 }
572#endif
573
574# ifdef VBOX_WITH_STATISTICS
575 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
576 AssertRCReturn(rc, rc);
577 pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
578 for (unsigned i = 0; i < 256; i++)
579 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
580 i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
581
582# ifdef VBOX_WITH_RAW_MODE
583 if (!HMIsEnabled(pVM))
584 {
585 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
586 AssertRCReturn(rc, rc);
587 pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
588 for (unsigned i = 0; i < 256; i++)
589 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
590 "Host interrupts.", "/TRPM/HostIRQs/%02x", i);
591 }
592# endif
593# endif
594
595#ifdef VBOX_WITH_RAW_MODE
596 if (!HMIsEnabled(pVM))
597 {
598 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
599 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
600 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
601 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
602 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
603 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
604
605 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
606 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
607 }
608#endif
609
610#ifdef VBOX_WITH_RAW_MODE
611 /*
612 * Default action when entering raw mode for the first time
613 */
614 if (!HMIsEnabled(pVM))
615 {
616 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
617 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
618 }
619#endif
620 return 0;
621}
622
623
624/**
625 * Applies relocations to data and code managed by this component.
626 *
627 * This function will be called at init and whenever the VMM need
628 * to relocate itself inside the GC.
629 *
630 * @param pVM The cross context VM structure.
631 * @param offDelta Relocation delta relative to old location.
632 */
633VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
634{
635#ifdef VBOX_WITH_RAW_MODE
636 if (HMIsEnabled(pVM))
637 return;
638
639 /* Only applies to raw mode which supports only 1 VCPU. */
640 PVMCPU pVCpu = &pVM->aCpus[0];
641 LogFlow(("TRPMR3Relocate\n"));
642
643 /*
644 * Get the trap handler addresses.
645 *
646 * If VMMRC.rc is screwed, so are we. We'll assert here since it elsewise
647 * would make init order impossible if we should assert the presence of these
648 * exports in TRPMR3Init().
649 */
650 RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
651 RT_ZERO(aRCPtrs);
652 int rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
653 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
654
655 rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
656 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMRC.rc!\n"));
657
658 rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
659 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMRC.rc!\n"));
660
661 rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
662 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMRC.rc!\n"));
663
664 RTSEL SelCS = CPUMGetHyperCS(pVCpu);
665
666 /*
667 * Iterate the idt and set the addresses.
668 */
669 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
670 PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
671 for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
672 {
673 if ( pIdte->Gen.u1Present
674 && !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
675 )
676 {
677 Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
678 RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
679 switch (pIdteTemplate->u16OffsetLow)
680 {
681 /*
682 * Generic handlers have different entrypoints for each possible
683 * vector number. These entrypoints makes a sort of an array with
684 * 8 byte entries where the vector number is the index.
685 * See TRPMGCHandlersA.asm for details.
686 */
687 case TRPM_HANDLER_INT:
688 case TRPM_HANDLER_TRAP:
689 Offset += i * 8;
690 break;
691 case TRPM_HANDLER_TRAP_12:
692 break;
693 case TRPM_HANDLER_TRAP_08:
694 /* Handle #DF Task Gate in special way. */
695 pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
696 pIdte->Gen.u16OffsetLow = 0;
697 pIdte->Gen.u16OffsetHigh = 0;
698 SELMSetTrap8EIP(pVM, Offset);
699 continue;
700 }
701 /* (non-task gates only ) */
702 pIdte->Gen.u16OffsetLow = Offset & 0xffff;
703 pIdte->Gen.u16OffsetHigh = Offset >> 16;
704 pIdte->Gen.u16SegSel = SelCS;
705 }
706 }
707
708 /*
709 * Update IDTR (limit is including!).
710 */
711 CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
712
713# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
714 if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
715 {
716 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.pvMonShwIdtRC, true /*fHypervisor*/);
717 AssertRC(rc);
718 }
719 pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
720 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hShadowIdtWriteHandlerType,
721 pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
722 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
723 AssertRC(rc);
724# endif
725
726 /* Relocate IDT handlers for forwarding guest traps/interrupts. */
727 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
728 {
729 if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
730 {
731 Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
732 pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
733 }
734
735 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
736 {
737 PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
738 RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
739
740 Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
741 pHandler += offDelta;
742
743 pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
744 pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
745 }
746 }
747
748# ifdef VBOX_WITH_STATISTICS
749 pVM->trpm.s.paStatForwardedIRQRC += offDelta;
750 pVM->trpm.s.paStatHostIrqRC += offDelta;
751# endif
752
753#else /* !VBOX_WITH_RAW_MODE */
754 RT_NOREF(pVM, offDelta);
755#endif /* !VBOX_WITH_RAW_MODE */
756}
757
758
759/**
760 * Terminates the Trap Manager
761 *
762 * @returns VBox status code.
763 * @param pVM The cross context VM structure.
764 */
765VMMR3DECL(int) TRPMR3Term(PVM pVM)
766{
767 NOREF(pVM);
768 return VINF_SUCCESS;
769}
770
771
772/**
773 * Resets a virtual CPU.
774 *
775 * Used by TRPMR3Reset and CPU hot plugging.
776 *
777 * @param pVCpu The cross context virtual CPU structure.
778 */
779VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
780{
781 pVCpu->trpm.s.uActiveVector = ~0U;
782}
783
784
785/**
786 * The VM is being reset.
787 *
788 * For the TRPM component this means that any IDT write monitors
789 * needs to be removed, any pending trap cleared, and the IDT reset.
790 *
791 * @param pVM The cross context VM structure.
792 */
793VMMR3DECL(void) TRPMR3Reset(PVM pVM)
794{
795 /*
796 * Deregister any virtual handlers.
797 */
798#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
799 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
800 {
801 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
802 {
803 int rc = PGMHandlerVirtualDeregister(pVM, VMMGetCpu(pVM), pVM->trpm.s.GuestIdtr.pIdt, false /*fHypervisor*/);
804 AssertRC(rc);
805 }
806 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
807 }
808 pVM->trpm.s.GuestIdtr.cbIdt = 0;
809#endif
810
811 /*
812 * Reinitialize other members calling the relocator to get things right.
813 */
814 for (VMCPUID i = 0; i < pVM->cCpus; i++)
815 TRPMR3ResetCpu(&pVM->aCpus[i]);
816 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
817 memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
818 TRPMR3Relocate(pVM, 0);
819
820#ifdef VBOX_WITH_RAW_MODE
821 /*
822 * Default action when entering raw mode for the first time
823 */
824 if (!HMIsEnabled(pVM))
825 {
826 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
827 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
828 }
829#endif
830}
831
832
833# ifdef VBOX_WITH_RAW_MODE
834/**
835 * Resolve a builtin RC symbol.
836 *
837 * Called by PDM when loading or relocating RC modules.
838 *
839 * @returns VBox status
840 * @param pVM The cross context VM structure.
841 * @param pszSymbol Symbol to resolv
842 * @param pRCPtrValue Where to store the symbol value.
843 *
844 * @remark This has to work before VMMR3Relocate() is called.
845 */
846VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
847{
848 if (!strcmp(pszSymbol, "g_TRPM"))
849 *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
850 else if (!strcmp(pszSymbol, "g_TRPMCPU"))
851 *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
852 else if (!strcmp(pszSymbol, "g_trpmGuestCtx"))
853 {
854 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
855 *pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
856 }
857 else if (!strcmp(pszSymbol, "g_trpmHyperCtx"))
858 {
859 PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
860 *pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
861 }
862 else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
863 {
864 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
865 *pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
866 }
867 else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
868 {
869 PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
870 *pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
871 }
872 else
873 return VERR_SYMBOL_NOT_FOUND;
874 return VINF_SUCCESS;
875}
876#endif /* VBOX_WITH_RAW_MODE */
877
878
879/**
880 * Execute state save operation.
881 *
882 * @returns VBox status code.
883 * @param pVM The cross context VM structure.
884 * @param pSSM SSM operation handle.
885 */
886static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
887{
888 PTRPM pTrpm = &pVM->trpm.s;
889 LogFlow(("trpmR3Save:\n"));
890
891 /*
892 * Active and saved traps.
893 */
894 for (VMCPUID i = 0; i < pVM->cCpus; i++)
895 {
896 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
897 SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
898 SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
899 SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
900 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
901 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
902 SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
903 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
904 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
905 SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
906 }
907 SSMR3PutBool(pSSM, HMIsEnabled(pVM));
908 PVMCPU pVCpu0 = &pVM->aCpus[0]; NOREF(pVCpu0); /* raw mode implies 1 VCPU */
909 SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_IS_SET(pVCpu0, VMCPU_FF_TRPM_SYNC_IDT), 0));
910 SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
911 SSMR3PutU32(pSSM, UINT32_MAX); /* separator. */
912
913 /*
914 * Save any trampoline gates.
915 */
916 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
917 {
918 if (pTrpm->aGuestTrapHandler[iTrap])
919 {
920 SSMR3PutU32(pSSM, iTrap);
921 SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
922 SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
923 }
924 }
925
926 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
927}
928
929
930/**
931 * Execute state load operation.
932 *
933 * @returns VBox status code.
934 * @param pVM The cross context VM structure.
935 * @param pSSM SSM operation handle.
936 * @param uVersion Data layout version.
937 * @param uPass The data pass.
938 */
939static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
940{
941 LogFlow(("trpmR3Load:\n"));
942 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
943
944 /*
945 * Validate version.
946 */
947 if ( uVersion != TRPM_SAVED_STATE_VERSION
948 && uVersion != TRPM_SAVED_STATE_VERSION_UNI)
949 {
950 AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
951 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
952 }
953
954 /*
955 * Call the reset function to kick out any handled gates and other potential trouble.
956 */
957 TRPMR3Reset(pVM);
958
959 /*
960 * Active and saved traps.
961 */
962 PTRPM pTrpm = &pVM->trpm.s;
963
964 if (uVersion == TRPM_SAVED_STATE_VERSION)
965 {
966 for (VMCPUID i = 0; i < pVM->cCpus; i++)
967 {
968 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
969 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
970 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
971 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
972 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
973 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
974 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
975 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
976 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
977 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
978 }
979
980 bool fIgnored;
981 SSMR3GetBool(pSSM, &fIgnored);
982 }
983 else
984 {
985 PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
986 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
987 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
988 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
989 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
990 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
991 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
992 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
993 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
994 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
995
996 RTGCUINT fIgnored;
997 SSMR3GetGCUInt(pSSM, &fIgnored);
998 }
999
1000 RTUINT fSyncIDT;
1001 int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
1002 if (RT_FAILURE(rc))
1003 return rc;
1004 if (fSyncIDT & ~1)
1005 {
1006 AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
1007 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1008 }
1009#ifdef VBOX_WITH_RAW_MODE
1010 if (fSyncIDT)
1011 {
1012 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
1013 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1014 }
1015 /* else: cleared by reset call above. */
1016#endif
1017
1018 SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
1019
1020 /* check the separator */
1021 uint32_t u32Sep;
1022 rc = SSMR3GetU32(pSSM, &u32Sep);
1023 if (RT_FAILURE(rc))
1024 return rc;
1025 if (u32Sep != (uint32_t)~0)
1026 {
1027 AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1028 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1029 }
1030
1031 /*
1032 * Restore any trampoline gates.
1033 */
1034 for (;;)
1035 {
1036 /* gate number / terminator */
1037 uint32_t iTrap;
1038 rc = SSMR3GetU32(pSSM, &iTrap);
1039 if (RT_FAILURE(rc))
1040 return rc;
1041 if (iTrap == (uint32_t)~0)
1042 break;
1043 if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
1044 || pTrpm->aGuestTrapHandler[iTrap])
1045 {
1046 AssertMsgFailed(("iTrap=%#x\n", iTrap));
1047 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1048 }
1049
1050 /* restore the IDT entry. */
1051 RTGCPTR GCPtrHandler;
1052 SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1053 VBOXIDTE Idte;
1054 rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1055 if (RT_FAILURE(rc))
1056 return rc;
1057 Assert(GCPtrHandler);
1058 pTrpm->aIdt[iTrap] = Idte;
1059 }
1060
1061 return VINF_SUCCESS;
1062}
1063
1064#ifdef VBOX_WITH_RAW_MODE
1065
1066/**
1067 * Check if gate handlers were updated
1068 * (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1069 *
1070 * @returns VBox status code.
1071 * @param pVM The cross context VM structure.
1072 * @param pVCpu The cross context virtual CPU structure.
1073 */
1074VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1075{
1076 STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1077 const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1078 int rc;
1079
1080 AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1081
1082 if (fRawRing0 && CSAMIsEnabled(pVM))
1083 {
1084 /* Clear all handlers */
1085 Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1086 /** @todo inefficient, but simple */
1087 for (unsigned iGate = 0; iGate < 256; iGate++)
1088 trpmClearGuestTrapHandler(pVM, iGate);
1089
1090 /* Scan them all (only the first time) */
1091 CSAMR3CheckGates(pVM, 0, 256);
1092 }
1093
1094 /*
1095 * Get the IDTR.
1096 */
1097 VBOXIDTR IDTR;
1098 IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1099 if (!IDTR.cbIdt)
1100 {
1101 Log(("No IDT entries...\n"));
1102 return DBGFSTOP(pVM);
1103 }
1104
1105# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1106 /*
1107 * Check if Guest's IDTR has changed.
1108 */
1109 if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1110 || IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1111 {
1112 Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1113 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1114 {
1115 /*
1116 * [Re]Register write virtual handler for guest's IDT.
1117 */
1118 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1119 {
1120 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.GuestIdtr.pIdt, false /*fHypervisor*/);
1121 AssertRCReturn(rc, rc);
1122 }
1123 /* limit is including */
1124 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1125 IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1126 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1127
1128 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1129 {
1130 /* Could be a conflict with CSAM */
1131 CSAMR3RemovePage(pVM, IDTR.pIdt);
1132 if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1133 CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1134
1135 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1136 IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1137 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1138 }
1139
1140 AssertRCReturn(rc, rc);
1141 }
1142
1143 /* Update saved Guest IDTR. */
1144 pVM->trpm.s.GuestIdtr = IDTR;
1145 }
1146# endif
1147
1148 /*
1149 * Sync the interrupt gate.
1150 * Should probably check/sync the others too, but for now we'll handle that in #GP.
1151 */
1152 X86DESC Idte3;
1153 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1154 if (RT_FAILURE(rc))
1155 {
1156 AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1157 return DBGFSTOP(pVM);
1158 }
1159 AssertRCReturn(rc, rc);
1160 if (fRawRing0)
1161 pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1162 else
1163 pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1164
1165 /*
1166 * Clear the FF and we're done.
1167 */
1168 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1169 STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1170 return VINF_SUCCESS;
1171}
1172
1173
1174/**
1175 * Clear passthrough interrupt gate handler (reset to default handler)
1176 *
1177 * @returns VBox status code.
1178 * @param pVM The cross context VM structure.
1179 * @param iTrap Trap/interrupt gate number.
1180 */
1181int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1182{
1183 /* Only applies to raw mode which supports only 1 VCPU. */
1184 PVMCPU pVCpu = &pVM->aCpus[0];
1185 Assert(!HMIsEnabled(pVM));
1186
1187 /** @todo cleanup trpmR3ClearPassThroughHandler()! */
1188 RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1189 int rc;
1190
1191 memset(aGCPtrs, 0, sizeof(aGCPtrs));
1192
1193 rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1194 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
1195
1196 if ( iTrap < TRPM_HANDLER_INT_BASE
1197 || iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1198 {
1199 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1200 return VERR_INVALID_PARAMETER;
1201 }
1202 memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1203
1204 /* Unmark it for relocation purposes. */
1205 ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1206
1207 RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1208 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1209 PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1210 if (pIdte->Gen.u1Present)
1211 {
1212 Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1213 Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1214 RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1215
1216 /*
1217 * Generic handlers have different entrypoints for each possible
1218 * vector number. These entrypoints make a sort of an array with
1219 * 8 byte entries where the vector number is the index.
1220 * See TRPMGCHandlersA.asm for details.
1221 */
1222 Offset += iTrap * 8;
1223
1224 if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1225 {
1226 pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1227 pIdte->Gen.u16OffsetHigh = Offset >> 16;
1228 pIdte->Gen.u16SegSel = SelCS;
1229 }
1230 }
1231
1232 return VINF_SUCCESS;
1233}
1234
1235
1236/**
1237 * Check if address is a gate handler (interrupt or trap).
1238 *
1239 * @returns gate nr or UINT32_MAX is not found
1240 *
1241 * @param pVM The cross context VM structure.
1242 * @param GCPtr GC address to check.
1243 */
1244VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1245{
1246 AssertReturn(!HMIsEnabled(pVM), ~0U);
1247
1248 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1249 {
1250 if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1251 return iTrap;
1252
1253 /* redundant */
1254 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1255 {
1256 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1257 RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1258
1259 if (pHandler == GCPtr)
1260 return iTrap;
1261 }
1262 }
1263 return UINT32_MAX;
1264}
1265
1266
1267/**
1268 * Get guest trap/interrupt gate handler
1269 *
1270 * @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1271 * @param pVM The cross context VM structure.
1272 * @param iTrap Interrupt/trap number.
1273 */
1274VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1275{
1276 AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1277 AssertReturn(!HMIsEnabled(pVM), TRPM_INVALID_HANDLER);
1278
1279 return pVM->trpm.s.aGuestTrapHandler[iTrap];
1280}
1281
1282
1283/**
1284 * Set guest trap/interrupt gate handler
1285 * Used for setting up trap gates used for kernel calls.
1286 *
1287 * @returns VBox status code.
1288 * @param pVM The cross context VM structure.
1289 * @param iTrap Interrupt/trap number.
1290 * @param pHandler GC handler pointer
1291 */
1292VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1293{
1294 /* Only valid in raw mode which implies 1 VCPU */
1295 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1296 AssertReturn(!HMIsEnabled(pVM), VERR_TRPM_HM_IPE);
1297 PVMCPU pVCpu = &pVM->aCpus[0];
1298
1299 /*
1300 * Validate.
1301 */
1302 if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1303 {
1304 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1305 return VERR_INVALID_PARAMETER;
1306 }
1307
1308 AssertReturn(pHandler == TRPM_INVALID_HANDLER || PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1309
1310 uint16_t cbIDT;
1311 RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1312 if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1313 return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1314
1315 if (pHandler == TRPM_INVALID_HANDLER)
1316 {
1317 /* clear trap handler */
1318 Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1319 return trpmClearGuestTrapHandler(pVM, iTrap);
1320 }
1321
1322 /*
1323 * Read the guest IDT entry.
1324 */
1325 VBOXIDTE GuestIdte;
1326 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1327 if (RT_FAILURE(rc))
1328 {
1329 AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1330 return rc;
1331 }
1332
1333 if ( EMIsRawRing0Enabled(pVM)
1334 && !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1335 {
1336 /*
1337 * Only replace handlers for which we are 100% certain there won't be
1338 * any host interrupts.
1339 *
1340 * 0x2E is safe on Windows because it's the system service interrupt gate. Not
1341 * quite certain if this is safe or not on 64-bit Vista, it probably is.
1342 *
1343 * 0x80 is safe on Linux because it's the syscall vector and is part of the
1344 * 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1345 * and will therefor never assign hardware interrupts to 0x80.
1346 *
1347 * Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1348 * to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1349 * Booting Linux/BSD guest will cause system lockups on most of the computers.
1350 * -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1351 * @bugref{3604}.
1352 *
1353 * PORTME - Check if your host keeps any of these gates free from hw ints.
1354 *
1355 * Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1356 */
1357 /** @todo handle those dependencies better! */
1358 /** @todo Solve this in a proper manner. see @bugref{1186} */
1359#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1360 if (iTrap == 0x2E)
1361#elif defined(RT_OS_LINUX)
1362 if (iTrap == 0x80)
1363#else
1364 if (0)
1365#endif
1366 {
1367 if ( GuestIdte.Gen.u1Present
1368 && ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1369 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1370 && GuestIdte.Gen.u2DPL == 3)
1371 {
1372 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1373
1374 GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1375 GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1376 GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1377 GuestIdte.Gen.u16SegSel |= 1; //ring 1
1378 *pIdte = GuestIdte;
1379
1380 /* Mark it for relocation purposes. */
1381 ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1382
1383 /* Also store it in our guest trap array. */
1384 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1385
1386 Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1387 return VINF_SUCCESS;
1388 }
1389 /* ok, let's try to install a trampoline handler then. */
1390 }
1391 }
1392
1393 if ( GuestIdte.Gen.u1Present
1394 && ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1395 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1396 && (GuestIdte.Gen.u2DPL == 3 || GuestIdte.Gen.u2DPL == 0))
1397 {
1398 /*
1399 * Save handler which can be used for a trampoline call inside the GC
1400 */
1401 Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1402 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1403 return VINF_SUCCESS;
1404 }
1405 return VERR_INVALID_PARAMETER;
1406}
1407
1408
1409/**
1410 * Check if address is a gate handler (interrupt/trap/task/anything).
1411 *
1412 * @returns True is gate handler, false if not.
1413 *
1414 * @param pVM The cross context VM structure.
1415 * @param GCPtr GC address to check.
1416 */
1417VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1418{
1419 /* Only valid in raw mode which implies 1 VCPU */
1420 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1421 PVMCPU pVCpu = &pVM->aCpus[0];
1422
1423 /*
1424 * Read IDTR and calc last entry.
1425 */
1426 uint16_t cbIDT;
1427 RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1428 unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1429 if (!cEntries)
1430 return false;
1431 RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1432
1433 /*
1434 * Outer loop: iterate pages.
1435 */
1436 while (GCPtrIDTE <= GCPtrIDTELast)
1437 {
1438 /*
1439 * Convert this page to a HC address.
1440 * (This function checks for not-present pages.)
1441 */
1442 PCVBOXIDTE pIDTE;
1443 PGMPAGEMAPLOCK Lock;
1444 int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1445 if (RT_SUCCESS(rc))
1446 {
1447 /*
1448 * Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1449 * N.B. Member of the Flat Earth Society...
1450 */
1451 while (GCPtrIDTE <= GCPtrIDTELast)
1452 {
1453 if (pIDTE->Gen.u1Present)
1454 {
1455 RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1456 if (GCPtr == GCPtrHandler)
1457 {
1458 PGMPhysReleasePageMappingLock(pVM, &Lock);
1459 return true;
1460 }
1461 }
1462
1463 /* next entry */
1464 if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1465 {
1466 AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1467 ("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1468 GCPtrIDTE += sizeof(VBOXIDTE);
1469 break;
1470 }
1471 GCPtrIDTE += sizeof(VBOXIDTE);
1472 pIDTE++;
1473 }
1474 PGMPhysReleasePageMappingLock(pVM, &Lock);
1475 }
1476 else
1477 {
1478 /* Skip to the next page (if any). Take care not to wrap around the address space. */
1479 if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1480 return false;
1481 GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1482 }
1483 }
1484 return false;
1485}
1486
1487#endif /* VBOX_WITH_RAW_MODE */
1488
1489/**
1490 * Inject event (such as external irq or trap)
1491 *
1492 * @returns VBox status code.
1493 * @param pVM The cross context VM structure.
1494 * @param pVCpu The cross context virtual CPU structure.
1495 * @param enmEvent Trpm event type
1496 */
1497VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1498{
1499#ifdef VBOX_WITH_RAW_MODE
1500 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1501 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1502#endif
1503 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1504
1505 /* Currently only useful for external hardware interrupts. */
1506 Assert(enmEvent == TRPM_HARDWARE_INT);
1507
1508#if defined(TRPM_FORWARD_TRAPS_IN_GC) && !defined(IEM_VERIFICATION_MODE)
1509
1510# ifdef LOG_ENABLED
1511 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "TRPMInject");
1512 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1513# endif
1514
1515 uint8_t u8Interrupt = 0;
1516 int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1517 Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1518 if (RT_SUCCESS(rc))
1519 {
1520 if (HMIsEnabled(pVM) || EMIsSupervisorCodeRecompiled(pVM))
1521 {
1522 rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1523 AssertRC(rc);
1524 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1525 return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1526 }
1527 /* If the guest gate is not patched, then we will check (again) if we can patch it. */
1528 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1529 {
1530 CSAMR3CheckGates(pVM, u8Interrupt, 1);
1531 Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1532 }
1533
1534 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1535 {
1536 /* Must check pending forced actions as our IDT or GDT might be out of sync */
1537 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1538 if (rc == VINF_SUCCESS)
1539 {
1540 /* There's a handler -> let's execute it in raw mode */
1541 rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1542 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1543 {
1544 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
1545
1546 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1547 return VINF_EM_RESCHEDULE_RAW;
1548 }
1549 }
1550 }
1551 else
1552 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1553
1554 rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1555 AssertRCReturn(rc, rc);
1556 }
1557 else
1558 {
1559 /* Can happen if the interrupt is masked by TPR or APIC is disabled. */
1560 AssertMsg(rc == VERR_APIC_INTR_MASKED_BY_TPR || rc == VERR_NO_DATA, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
1561 return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1562 }
1563
1564 /** @todo check if it's safe to translate the patch address to the original guest address.
1565 * this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1566 */
1567 /* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return codes below. */
1568
1569 /* Fall back to the recompiler */
1570 return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1571
1572#else /* !TRPM_FORWARD_TRAPS_IN_GC || IEM_VERIFICATION_MODE */
1573 RT_NOREF(pVM, enmEvent);
1574 uint8_t u8Interrupt = 0;
1575 int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1576 Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1577 if (RT_SUCCESS(rc))
1578 {
1579 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1580 AssertRC(rc);
1581 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1582 }
1583 else
1584 {
1585 /* Can happen if the interrupt is masked by TPR or APIC is disabled. */
1586 AssertMsg(rc == VERR_APIC_INTR_MASKED_BY_TPR || rc == VERR_NO_DATA, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
1587 }
1588 return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1589#endif /* !TRPM_FORWARD_TRAPS_IN_GC || IEM_VERIFICATION_MODE */
1590
1591}
1592
1593
1594/**
1595 * Displays the pending TRPM event.
1596 *
1597 * @param pVM The cross context VM structure.
1598 * @param pHlp The info helper functions.
1599 * @param pszArgs Arguments, ignored.
1600 */
1601static DECLCALLBACK(void) trpmR3InfoEvent(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1602{
1603 NOREF(pszArgs);
1604 PVMCPU pVCpu = VMMGetCpu(pVM);
1605 if (!pVCpu)
1606 pVCpu = &pVM->aCpus[0];
1607
1608 uint8_t uVector;
1609 uint8_t cbInstr;
1610 TRPMEVENT enmTrapEvent;
1611 RTGCUINT uErrorCode;
1612 RTGCUINTPTR uCR2;
1613 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrapEvent, &uErrorCode, &uCR2, &cbInstr);
1614 if (RT_SUCCESS(rc))
1615 {
1616 pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event\n", pVCpu->idCpu);
1617 static const char * const s_apszTrpmEventType[] =
1618 {
1619 "Trap",
1620 "Hardware Int",
1621 "Software Int"
1622 };
1623 if (RT_LIKELY((size_t)enmTrapEvent < RT_ELEMENTS(s_apszTrpmEventType)))
1624 {
1625 pHlp->pfnPrintf(pHlp, " Type = %s\n", s_apszTrpmEventType[enmTrapEvent]);
1626 pHlp->pfnPrintf(pHlp, " uVector = %#x\n", uVector);
1627 pHlp->pfnPrintf(pHlp, " uErrorCode = %#RGu\n", uErrorCode);
1628 pHlp->pfnPrintf(pHlp, " uCR2 = %#RGp\n", uCR2);
1629 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", cbInstr);
1630 }
1631 else
1632 pHlp->pfnPrintf(pHlp, " Type = %#x (Invalid!)\n", enmTrapEvent);
1633 }
1634 else if (rc == VERR_TRPM_NO_ACTIVE_TRAP)
1635 pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event (None)\n", pVCpu->idCpu);
1636 else
1637 pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event - Query failed! rc=%Rrc\n", pVCpu->idCpu, rc);
1638}
1639
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