TRPM.cpp@ 80007

Last change on this file since 80007 was 80007, checked in by vboxsync, 6 years ago
VMM: Kicking out raw-mode (work in progress). bugref:9517
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 82.0 KB

Line
1	/* $Id: TRPM.cpp 80007 2019-07-26 13:57:38Z vboxsync $ */
2	/** @file
3	* TRPM - The Trap Monitor.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_trpm TRPM - The Trap Monitor
19	*
20	* The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21	* the VMM. It plays a major role in raw-mode execution and a lesser one in the
22	* hardware assisted mode.
23	*
24	* Note first, the following will use trap as a collective term for faults,
25	* aborts and traps.
26	*
27	* @see grp_trpm
28	*
29	*
30	* @section sec_trpm_rc Raw-Mode Context
31	*
32	* When executing in the raw-mode context, TRPM will be managing the IDT and
33	* processing all traps and interrupts. It will also monitor the guest IDT
34	* because CSAM wishes to know about changes to it (trap/interrupt/syscall
35	* handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36	* considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37	*
38	* External interrupts will be forwarded to the host context by the quickest
39	* possible route where they will be reasserted. The other events will be
40	* categorized into virtualization traps, genuine guest traps and hypervisor
41	* traps. The latter group may be recoverable depending on when they happen and
42	* whether there is a handler for it, otherwise it will cause a guru meditation.
43	*
44	* TRPM distinguishes the between the first two (virt and guest traps) and the
45	* latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46	* it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47	* dispatcher tables, one ad-hoc for one time traps registered via
48	* TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49	* The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50	*
51	* The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52	* part), will call up the other VMM sub-systems depending on what it things
53	* happens. The two most busy traps are page faults (\#PF) and general
54	* protection fault/trap (\#GP).
55	*
56	* Before resuming guest code after having taken a virtualization trap or
57	* injected a guest trap, TRPM will check for pending forced action and
58	* every now and again let TM check for timed out timers. This allows code that
59	* is being executed as part of virtualization traps to signal ring-3 exits,
60	* page table resyncs and similar without necessarily using the status code. It
61	* also make sure we're more responsive to timers and requests from other
62	* threads (necessarily running on some different core/cpu in most cases).
63	*
64	*
65	* @section sec_trpm_all All Contexts
66	*
67	* TRPM will also dispatch / inject interrupts and traps to the guest, both when
68	* in raw-mode and when in hardware assisted mode. See TRPMInject().
69	*
70	*/
71
72
73	/*********************************************************************************************************************************
74	* Header Files *
75	*********************************************************************************************************************************/
76	#define LOG_GROUP LOG_GROUP_TRPM
77	#include <VBox/vmm/trpm.h>
78	#include <VBox/vmm/cpum.h>
79	#include <VBox/vmm/selm.h>
80	#include <VBox/vmm/ssm.h>
81	#include <VBox/vmm/pdmapi.h>
82	#include <VBox/vmm/em.h>
83	#include <VBox/vmm/pgm.h>
84	#include <VBox/vmm/dbgf.h>
85	#include <VBox/vmm/mm.h>
86	#include <VBox/vmm/stam.h>
87	#include <VBox/vmm/iem.h>
88	#include "TRPMInternal.h"
89	#include <VBox/vmm/vm.h>
90	#include <VBox/vmm/em.h>
91	#ifdef VBOX_WITH_REM
92	# include <VBox/vmm/rem.h>
93	#endif
94	#include <VBox/vmm/hm.h>
95
96	#include <VBox/err.h>
97	#include <VBox/param.h>
98	#include <VBox/log.h>
99	#include <iprt/assert.h>
100	#include <iprt/asm.h>
101	#include <iprt/string.h>
102	#include <iprt/alloc.h>
103
104
105	/*********************************************************************************************************************************
106	* Structures and Typedefs *
107	*********************************************************************************************************************************/
108	/**
109	* Trap handler function.
110	* @todo need to specialize this as we go along.
111	*/
112	typedef enum TRPMHANDLER
113	{
114	/** Generic Interrupt handler. */
115	TRPM_HANDLER_INT = 0,
116	/** Generic Trap handler. */
117	TRPM_HANDLER_TRAP,
118	/** Trap 8 (\#DF) handler. */
119	TRPM_HANDLER_TRAP_08,
120	/** Trap 12 (\#MC) handler. */
121	TRPM_HANDLER_TRAP_12,
122	/** Max. */
123	TRPM_HANDLER_MAX
124	} TRPMHANDLER, *PTRPMHANDLER;
125
126
127	/*********************************************************************************************************************************
128	* Global Variables *
129	*********************************************************************************************************************************/
130	/** Preinitialized IDT.
131	* The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
132	* will use to pick the right address. The u16SegSel is always VMM CS.
133	*/
134	static VBOXIDTE_GENERIC g_aIdt[256] =
135	{
136	/* special trap handler - still, this is an interrupt gate not a trap gate... */
137	#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
138	/* generic trap handler. */
139	#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
140	/* special interrupt handler. */
141	#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
142	/* generic interrupt handler. */
143	#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
144	/* special task gate IDT entry (for critical exceptions like #DF). */
145	#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
146	/* draft, fixme later when the handler is written. */
147	#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
148
149	/* N - M M - T - C - D i */
150	/* o - n o - y - o - e p */
151	/* - e n - p - d - s t */
152	/* - i - e - e - c . */
153	/* - c - - - r */
154	/* ============================================================= */
155	IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
156	IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
157	#ifdef VBOX_WITH_NMI
158	IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
159	#else
160	IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
161	#endif
162	IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
163	IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
164	IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
165	IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
166	IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
167	IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
168	IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
169	IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
170	IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
171	IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
172	IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
173	IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
174	IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
175	IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
176	IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
177	IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
178	IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
179	IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
180	IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
181	IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
182	IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
183	IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
184	IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
185	IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
186	IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
187	IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
188	IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
189	IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
190	IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
191	IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
192	IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
193	IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
194	IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
195	IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
196	IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
197	IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
198	IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
199	IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
200	IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
201	IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
202	IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
203	IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
204	IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
205	IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
206	IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
207	IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
208	IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
209	IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
210	IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
211	IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
212	IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
213	IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
214	IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
215	IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
216	IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
217	IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
218	IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
219	IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
220	IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
221	IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
222	IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
223	IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
224	IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
225	IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
226	IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
227	IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
228	IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
229	IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
230	IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
231	IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
232	IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
233	IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
234	IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
235	IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
236	IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
237	IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
238	IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
239	IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
240	IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
241	IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
242	IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
243	IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
244	IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
245	IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
246	IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
247	IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
248	IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
249	IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
250	IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
251	IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
252	IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
253	IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
254	IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
255	IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
256	IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
257	IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
258	IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
259	IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
260	IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
261	IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
262	IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
263	IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
264	IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
265	IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
266	IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
267	IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
268	IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
269	IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
270	IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
271	IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
272	IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
273	IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
274	IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
275	IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
276	IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
277	IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
278	IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
279	IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
280	IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
281	IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
282	IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
283	IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
284	IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
285	IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
286	IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
287	IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
288	IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
289	IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
290	IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
291	IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
292	IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
293	IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
294	IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
295	IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
296	IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
297	IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
298	IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
299	IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
300	IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
301	IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
302	IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
303	IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
304	IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
305	IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
306	IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
307	IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
308	IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
309	IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
310	IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
311	IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
312	IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
313	IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
314	IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
315	IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
316	IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
317	IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
318	IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
319	IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
320	IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
321	IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
322	IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
323	IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
324	IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
325	IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
326	IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
327	IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
328	IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
329	IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
330	IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
331	IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
332	IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
333	IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
334	IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
335	IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
336	IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
337	IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
338	IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
339	IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
340	IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
341	IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
342	IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
343	IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
344	IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
345	IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
346	IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
347	IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
348	IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
349	IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
350	IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
351	IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
352	IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
353	IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
354	IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
355	IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
356	IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
357	IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
358	IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
359	IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
360	IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
361	IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
362	IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
363	IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
364	IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
365	IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
366	IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
367	IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
368	IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
369	IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
370	IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
371	IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
372	IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
373	IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
374	IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
375	IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
376	IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
377	IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
378	IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
379	IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
380	IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
381	IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
382	IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
383	IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
384	IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
385	IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
386	IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
387	IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
388	IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
389	IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
390	IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
391	IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
392	IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
393	IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
394	IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
395	IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
396	IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
397	IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
398	IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
399	IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
400	IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
401	IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
402	IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
403	IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
404	IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
405	IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
406	IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
407	IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
408	IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
409	IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
410	IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
411	IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
412	IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
413	IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
414	IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
415	#undef IDTE_TRAP
416	#undef IDTE_TRAP_GEN
417	#undef IDTE_INT
418	#undef IDTE_INT_GEN
419	#undef IDTE_TASK
420	#undef IDTE_UNUSED
421	#undef IDTE_RESERVED
422	};
423
424
425	/** TRPM saved state version. */
426	#define TRPM_SAVED_STATE_VERSION 9
427	#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
428
429
430	/*********************************************************************************************************************************
431	* Internal Functions *
432	*********************************************************************************************************************************/
433	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
434	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
435	static DECLCALLBACK(void) trpmR3InfoEvent(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
436
437
438	/**
439	* Initializes the Trap Manager
440	*
441	* @returns VBox status code.
442	* @param pVM The cross context VM structure.
443	*/
444	VMMR3DECL(int) TRPMR3Init(PVM pVM)
445	{
446	LogFlow(("TRPMR3Init\n"));
447	int rc;
448
449	/*
450	* Assert sizes and alignments.
451	*/
452	AssertRelease(!(RT_UOFFSETOF(VM, trpm.s) & 31));
453	AssertRelease(!(RT_UOFFSETOF(VM, trpm.s.aIdt) & 15));
454	AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
455	AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
456
457	/*
458	* Initialize members.
459	*/
460	pVM->trpm.s.offVM = RT_UOFFSETOF(VM, trpm);
461	pVM->trpm.s.offTRPMCPU = RT_UOFFSETOF(VM, aCpus[0].trpm) - RT_UOFFSETOF(VM, trpm);
462
463	for (VMCPUID i = 0; i < pVM->cCpus; i++)
464	{
465	PVMCPU pVCpu = &pVM->aCpus[i];
466
467	pVCpu->trpm.s.offVM = RT_UOFFSETOF_DYN(VM, aCpus[i].trpm);
468	pVCpu->trpm.s.offVMCpu = RT_UOFFSETOF(VMCPU, trpm);
469	pVCpu->trpm.s.uActiveVector = ~0U;
470	}
471
472	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
473	pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
474	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
475
476	/*
477	* Read the configuration (if any).
478	*/
479	PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
480	if (pTRPMNode)
481	{
482	bool f;
483	rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
484	if (RT_SUCCESS(rc))
485	pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
486	}
487
488	/* write config summary to log */
489	if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
490	LogRel(("TRPM: Dropping Guest IDT Monitoring\n"));
491
492	/*
493	* Initialize the IDT.
494	* The handler addresses will be set in the TRPMR3Relocate() function.
495	*/
496	Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
497	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
498
499	/*
500	* Register virtual access handlers.
501	*/
502	pVM->trpm.s.hShadowIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
503	pVM->trpm.s.hGuestIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
504	#ifdef VBOX_WITH_RAW_MODE
505	if (VM_IS_RAW_MODE_ENABLED(pVM))
506	{
507	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
508	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
509	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
510	NULL /pszHandlerRC/, "trpmRCShadowIDTWritePfHandler",
511	"Shadow IDT write access handler", &pVM->trpm.s.hShadowIdtWriteHandlerType);
512	AssertRCReturn(rc, rc);
513	# endif
514	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
515	NULL /pfnInvalidateR3/, trpmGuestIDTWriteHandler,
516	"trpmGuestIDTWriteHandler", "trpmRCGuestIDTWritePfHandler",
517	"Guest IDT write access handler", &pVM->trpm.s.hGuestIdtWriteHandlerType);
518	AssertRCReturn(rc, rc);
519	}
520	#endif /* VBOX_WITH_RAW_MODE */
521
522	/*
523	* Register the saved state data unit.
524	*/
525	rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
526	NULL, NULL, NULL,
527	NULL, trpmR3Save, NULL,
528	NULL, trpmR3Load, NULL);
529	if (RT_FAILURE(rc))
530	return rc;
531
532	/*
533	* Register info handlers.
534	*/
535	rc = DBGFR3InfoRegisterInternalEx(pVM, "trpmevent", "Dumps TRPM pending event.", trpmR3InfoEvent,
536	DBGFINFO_FLAGS_ALL_EMTS);
537	AssertRCReturn(rc, rc);
538
539	/*
540	* Statistics.
541	*/
542	#ifdef VBOX_WITH_RAW_MODE
543	if (VM_IS_RAW_MODE_ENABLED(pVM))
544	{
545	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
546	STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
547	STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
548
549	/* traps */
550	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
551	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
552	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
553	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
554	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
555	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
556	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
557	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
558	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
559	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
560	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
561	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
562	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
563	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
564	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
565	//STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
566	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
567	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
568	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
569	STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
570	}
571	#endif
572
573	# ifdef VBOX_WITH_STATISTICS
574	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
575	AssertRCReturn(rc, rc);
576	pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
577	for (unsigned i = 0; i < 256; i++)
578	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
579	i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
580
581	# ifdef VBOX_WITH_RAW_MODE
582	if (VM_IS_RAW_MODE_ENABLED(pVM))
583	{
584	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
585	AssertRCReturn(rc, rc);
586	pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
587	for (unsigned i = 0; i < 256; i++)
588	STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
589	"Host interrupts.", "/TRPM/HostIRQs/%02x", i);
590	}
591	# endif
592	# endif
593
594	#ifdef VBOX_WITH_RAW_MODE
595	if (VM_IS_RAW_MODE_ENABLED(pVM))
596	{
597	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
598	STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
599	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
600	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
601	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
602	STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
603
604	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
605	STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
606	}
607	#endif
608
609	#ifdef VBOX_WITH_RAW_MODE
610	/*
611	* Default action when entering raw mode for the first time
612	*/
613	if (VM_IS_RAW_MODE_ENABLED(pVM))
614	{
615	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
616	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
617	}
618	#endif
619	return 0;
620	}
621
622
623	/**
624	* Applies relocations to data and code managed by this component.
625	*
626	* This function will be called at init and whenever the VMM need
627	* to relocate itself inside the GC.
628	*
629	* @param pVM The cross context VM structure.
630	* @param offDelta Relocation delta relative to old location.
631	*/
632	VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
633	{
634	#ifdef VBOX_WITH_RAW_MODE
635	if (!VM_IS_RAW_MODE_ENABLED(pVM))
636	return;
637
638	/* Only applies to raw mode which supports only 1 VCPU. */
639	PVMCPU pVCpu = &pVM->aCpus[0];
640	LogFlow(("TRPMR3Relocate\n"));
641
642	/*
643	* Get the trap handler addresses.
644	*
645	* If VMMRC.rc is screwed, so are we. We'll assert here since it elsewise
646	* would make init order impossible if we should assert the presence of these
647	* exports in TRPMR3Init().
648	*/
649	RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
650	RT_ZERO(aRCPtrs);
651	int rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
652	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
653
654	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
655	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMRC.rc!\n"));
656
657	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
658	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMRC.rc!\n"));
659
660	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
661	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMRC.rc!\n"));
662
663	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
664
665	/*
666	* Iterate the idt and set the addresses.
667	*/
668	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
669	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
670	for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
671	{
672	if ( pIdte->Gen.u1Present
673	&& !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
674	)
675	{
676	Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
677	RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
678	switch (pIdteTemplate->u16OffsetLow)
679	{
680	/*
681	* Generic handlers have different entrypoints for each possible
682	* vector number. These entrypoints makes a sort of an array with
683	* 8 byte entries where the vector number is the index.
684	* See TRPMGCHandlersA.asm for details.
685	*/
686	case TRPM_HANDLER_INT:
687	case TRPM_HANDLER_TRAP:
688	Offset += i * 8;
689	break;
690	case TRPM_HANDLER_TRAP_12:
691	break;
692	case TRPM_HANDLER_TRAP_08:
693	/* Handle #DF Task Gate in special way. */
694	pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
695	pIdte->Gen.u16OffsetLow = 0;
696	pIdte->Gen.u16OffsetHigh = 0;
697	SELMSetTrap8EIP(pVM, Offset);
698	continue;
699	}
700	/* (non-task gates only ) */
701	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
702	pIdte->Gen.u16OffsetHigh = Offset >> 16;
703	pIdte->Gen.u16SegSel = SelCS;
704	}
705	}
706
707	/*
708	* Update IDTR (limit is including!).
709	*/
710	CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
711
712	# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
713	if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
714	{
715	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.pvMonShwIdtRC, true /fHypervisor/);
716	AssertRC(rc);
717	}
718	pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
719	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hShadowIdtWriteHandlerType,
720	pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
721	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
722	AssertRC(rc);
723	# endif
724
725	/* Relocate IDT handlers for forwarding guest traps/interrupts. */
726	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
727	{
728	if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
729	{
730	Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
731	pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
732	}
733
734	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
735	{
736	PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
737	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
738
739	Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
740	pHandler += offDelta;
741
742	pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
743	pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
744	}
745	}
746
747	# ifdef VBOX_WITH_STATISTICS
748	pVM->trpm.s.paStatForwardedIRQRC += offDelta;
749	pVM->trpm.s.paStatHostIrqRC += offDelta;
750	# endif
751
752	#else /* !VBOX_WITH_RAW_MODE */
753	RT_NOREF(pVM, offDelta);
754	#endif /* !VBOX_WITH_RAW_MODE */
755	}
756
757
758	/**
759	* Terminates the Trap Manager
760	*
761	* @returns VBox status code.
762	* @param pVM The cross context VM structure.
763	*/
764	VMMR3DECL(int) TRPMR3Term(PVM pVM)
765	{
766	NOREF(pVM);
767	return VINF_SUCCESS;
768	}
769
770
771	/**
772	* Resets a virtual CPU.
773	*
774	* Used by TRPMR3Reset and CPU hot plugging.
775	*
776	* @param pVCpu The cross context virtual CPU structure.
777	*/
778	VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
779	{
780	pVCpu->trpm.s.uActiveVector = ~0U;
781	}
782
783
784	/**
785	* The VM is being reset.
786	*
787	* For the TRPM component this means that any IDT write monitors
788	* needs to be removed, any pending trap cleared, and the IDT reset.
789	*
790	* @param pVM The cross context VM structure.
791	*/
792	VMMR3DECL(void) TRPMR3Reset(PVM pVM)
793	{
794	/*
795	* Deregister any virtual handlers.
796	*/
797	#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
798	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
799	{
800	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
801	{
802	int rc = PGMHandlerVirtualDeregister(pVM, VMMGetCpu(pVM), pVM->trpm.s.GuestIdtr.pIdt, false /fHypervisor/);
803	AssertRC(rc);
804	}
805	pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
806	}
807	pVM->trpm.s.GuestIdtr.cbIdt = 0;
808	#endif
809
810	/*
811	* Reinitialize other members calling the relocator to get things right.
812	*/
813	for (VMCPUID i = 0; i < pVM->cCpus; i++)
814	TRPMR3ResetCpu(&pVM->aCpus[i]);
815	memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
816	memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
817	TRPMR3Relocate(pVM, 0);
818
819	#ifdef VBOX_WITH_RAW_MODE
820	/*
821	* Default action when entering raw mode for the first time
822	*/
823	if (VM_IS_RAW_MODE_ENABLED(pVM))
824	{
825	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
826	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
827	}
828	#endif
829	}
830
831
832	# ifdef VBOX_WITH_RAW_MODE
833	/**
834	* Resolve a builtin RC symbol.
835	*
836	* Called by PDM when loading or relocating RC modules.
837	*
838	* @returns VBox status
839	* @param pVM The cross context VM structure.
840	* @param pszSymbol Symbol to resolv
841	* @param pRCPtrValue Where to store the symbol value.
842	*
843	* @remark This has to work before VMMR3Relocate() is called.
844	*/
845	VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
846	{
847	if (!strcmp(pszSymbol, "g_TRPM"))
848	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
849	else if (!strcmp(pszSymbol, "g_TRPMCPU"))
850	*pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
851	else if (!strcmp(pszSymbol, "g_trpmGuestCtx"))
852	{
853	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
854	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
855	}
856	else if (!strcmp(pszSymbol, "g_trpmHyperCtx"))
857	{
858	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
859	*pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
860	}
861	else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
862	{
863	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
864	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
865	}
866	else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
867	{
868	PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
869	*pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
870	}
871	else
872	return VERR_SYMBOL_NOT_FOUND;
873	return VINF_SUCCESS;
874	}
875	#endif /* VBOX_WITH_RAW_MODE */
876
877
878	/**
879	* Execute state save operation.
880	*
881	* @returns VBox status code.
882	* @param pVM The cross context VM structure.
883	* @param pSSM SSM operation handle.
884	*/
885	static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
886	{
887	PTRPM pTrpm = &pVM->trpm.s;
888	LogFlow(("trpmR3Save:\n"));
889
890	/*
891	* Active and saved traps.
892	*/
893	for (VMCPUID i = 0; i < pVM->cCpus; i++)
894	{
895	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
896	SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
897	SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
898	SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
899	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
900	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
901	SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
902	SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
903	SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
904	SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
905	}
906	SSMR3PutBool(pSSM, !VM_IS_RAW_MODE_ENABLED(pVM));
907	PVMCPU pVCpu0 = &pVM->aCpus[0]; NOREF(pVCpu0); /* raw mode implies 1 VCPU */
908	SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_IS_SET(pVCpu0, VMCPU_FF_TRPM_SYNC_IDT), 0));
909	SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
910	SSMR3PutU32(pSSM, UINT32_MAX); /* separator. */
911
912	/*
913	* Save any trampoline gates.
914	*/
915	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
916	{
917	if (pTrpm->aGuestTrapHandler[iTrap])
918	{
919	SSMR3PutU32(pSSM, iTrap);
920	SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
921	SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
922	}
923	}
924
925	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
926	}
927
928
929	/**
930	* Execute state load operation.
931	*
932	* @returns VBox status code.
933	* @param pVM The cross context VM structure.
934	* @param pSSM SSM operation handle.
935	* @param uVersion Data layout version.
936	* @param uPass The data pass.
937	*/
938	static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
939	{
940	LogFlow(("trpmR3Load:\n"));
941	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
942
943	/*
944	* Validate version.
945	*/
946	if ( uVersion != TRPM_SAVED_STATE_VERSION
947	&& uVersion != TRPM_SAVED_STATE_VERSION_UNI)
948	{
949	AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
950	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
951	}
952
953	/*
954	* Call the reset function to kick out any handled gates and other potential trouble.
955	*/
956	TRPMR3Reset(pVM);
957
958	/*
959	* Active and saved traps.
960	*/
961	PTRPM pTrpm = &pVM->trpm.s;
962
963	if (uVersion == TRPM_SAVED_STATE_VERSION)
964	{
965	for (VMCPUID i = 0; i < pVM->cCpus; i++)
966	{
967	PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
968	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
969	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
970	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
971	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
972	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
973	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
974	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
975	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
976	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
977	}
978
979	bool fIgnored;
980	SSMR3GetBool(pSSM, &fIgnored);
981	}
982	else
983	{
984	PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
985	SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
986	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
987	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
988	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
989	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
990	SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
991	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
992	SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
993	SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
994
995	RTGCUINT fIgnored;
996	SSMR3GetGCUInt(pSSM, &fIgnored);
997	}
998
999	RTUINT fSyncIDT;
1000	int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
1001	if (RT_FAILURE(rc))
1002	return rc;
1003	if (fSyncIDT & ~1)
1004	{
1005	AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
1006	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1007	}
1008	#ifdef VBOX_WITH_RAW_MODE
1009	if (fSyncIDT)
1010	{
1011	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
1012	VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1013	}
1014	/* else: cleared by reset call above. */
1015	#endif
1016
1017	SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
1018
1019	/* check the separator */
1020	uint32_t u32Sep;
1021	rc = SSMR3GetU32(pSSM, &u32Sep);
1022	if (RT_FAILURE(rc))
1023	return rc;
1024	if (u32Sep != (uint32_t)~0)
1025	{
1026	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1027	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1028	}
1029
1030	/*
1031	* Restore any trampoline gates.
1032	*/
1033	for (;;)
1034	{
1035	/* gate number / terminator */
1036	uint32_t iTrap;
1037	rc = SSMR3GetU32(pSSM, &iTrap);
1038	if (RT_FAILURE(rc))
1039	return rc;
1040	if (iTrap == (uint32_t)~0)
1041	break;
1042	if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
1043	\|\| pTrpm->aGuestTrapHandler[iTrap])
1044	{
1045	AssertMsgFailed(("iTrap=%#x\n", iTrap));
1046	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1047	}
1048
1049	/* restore the IDT entry. */
1050	RTGCPTR GCPtrHandler;
1051	SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1052	VBOXIDTE Idte;
1053	rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1054	if (RT_FAILURE(rc))
1055	return rc;
1056	Assert(GCPtrHandler);
1057	pTrpm->aIdt[iTrap] = Idte;
1058	}
1059
1060	return VINF_SUCCESS;
1061	}
1062
1063	#ifdef VBOX_WITH_RAW_MODE
1064
1065	/**
1066	* Check if gate handlers were updated
1067	* (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1068	*
1069	* @returns VBox status code.
1070	* @param pVM The cross context VM structure.
1071	* @param pVCpu The cross context virtual CPU structure.
1072	*/
1073	VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1074	{
1075	STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1076	const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1077	int rc;
1078
1079	AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), VERR_TRPM_HM_IPE);
1080
1081	if (fRawRing0 && CSAMIsEnabled(pVM))
1082	{
1083	/* Clear all handlers */
1084	Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1085	/** @todo inefficient, but simple */
1086	for (unsigned iGate = 0; iGate < 256; iGate++)
1087	trpmClearGuestTrapHandler(pVM, iGate);
1088
1089	/* Scan them all (only the first time) */
1090	CSAMR3CheckGates(pVM, 0, 256);
1091	}
1092
1093	/*
1094	* Get the IDTR.
1095	*/
1096	VBOXIDTR IDTR;
1097	IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1098	if (!IDTR.cbIdt)
1099	{
1100	Log(("No IDT entries...\n"));
1101	return DBGFSTOP(pVM);
1102	}
1103
1104	# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1105	/*
1106	* Check if Guest's IDTR has changed.
1107	*/
1108	if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1109	\|\| IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1110	{
1111	Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1112	if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1113	{
1114	/*
1115	* [Re]Register write virtual handler for guest's IDT.
1116	*/
1117	if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1118	{
1119	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.GuestIdtr.pIdt, false /fHypervisor/);
1120	AssertRCReturn(rc, rc);
1121	}
1122	/* limit is including */
1123	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1124	IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1125	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1126
1127	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1128	{
1129	/* Could be a conflict with CSAM */
1130	CSAMR3RemovePage(pVM, IDTR.pIdt);
1131	if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1132	CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1133
1134	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1135	IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1136	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1137	}
1138
1139	AssertRCReturn(rc, rc);
1140	}
1141
1142	/* Update saved Guest IDTR. */
1143	pVM->trpm.s.GuestIdtr = IDTR;
1144	}
1145	# endif
1146
1147	/*
1148	* Sync the interrupt gate.
1149	* Should probably check/sync the others too, but for now we'll handle that in #GP.
1150	*/
1151	X86DESC Idte3;
1152	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1153	if (RT_FAILURE(rc))
1154	{
1155	AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1156	return DBGFSTOP(pVM);
1157	}
1158	AssertRCReturn(rc, rc);
1159	if (fRawRing0)
1160	pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1161	else
1162	pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1163
1164	/*
1165	* Clear the FF and we're done.
1166	*/
1167	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1168	STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1169	return VINF_SUCCESS;
1170	}
1171
1172
1173	/**
1174	* Clear passthrough interrupt gate handler (reset to default handler)
1175	*
1176	* @returns VBox status code.
1177	* @param pVM The cross context VM structure.
1178	* @param iTrap Trap/interrupt gate number.
1179	*/
1180	int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1181	{
1182	/* Only applies to raw mode which supports only 1 VCPU. */
1183	PVMCPU pVCpu = &pVM->aCpus[0];
1184	Assert(VM_IS_RAW_MODE_ENABLED(pVM));
1185
1186	/** @todo cleanup trpmR3ClearPassThroughHandler()! */
1187	RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1188	int rc;
1189
1190	memset(aGCPtrs, 0, sizeof(aGCPtrs));
1191
1192	rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1193	AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
1194
1195	if ( iTrap < TRPM_HANDLER_INT_BASE
1196	\|\| iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1197	{
1198	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1199	return VERR_INVALID_PARAMETER;
1200	}
1201	memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1202
1203	/* Unmark it for relocation purposes. */
1204	ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1205
1206	RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1207	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1208	PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1209	if (pIdte->Gen.u1Present)
1210	{
1211	Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1212	Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1213	RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1214
1215	/*
1216	* Generic handlers have different entrypoints for each possible
1217	* vector number. These entrypoints make a sort of an array with
1218	* 8 byte entries where the vector number is the index.
1219	* See TRPMGCHandlersA.asm for details.
1220	*/
1221	Offset += iTrap * 8;
1222
1223	if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1224	{
1225	pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1226	pIdte->Gen.u16OffsetHigh = Offset >> 16;
1227	pIdte->Gen.u16SegSel = SelCS;
1228	}
1229	}
1230
1231	return VINF_SUCCESS;
1232	}
1233
1234
1235	/**
1236	* Check if address is a gate handler (interrupt or trap).
1237	*
1238	* @returns gate nr or UINT32_MAX is not found
1239	*
1240	* @param pVM The cross context VM structure.
1241	* @param GCPtr GC address to check.
1242	*/
1243	VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1244	{
1245	AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), ~0U);
1246
1247	for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1248	{
1249	if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1250	return iTrap;
1251
1252	/* redundant */
1253	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1254	{
1255	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1256	RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1257
1258	if (pHandler == GCPtr)
1259	return iTrap;
1260	}
1261	}
1262	return UINT32_MAX;
1263	}
1264
1265
1266	/**
1267	* Get guest trap/interrupt gate handler
1268	*
1269	* @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1270	* @param pVM The cross context VM structure.
1271	* @param iTrap Interrupt/trap number.
1272	*/
1273	VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1274	{
1275	AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1276	AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), TRPM_INVALID_HANDLER);
1277
1278	return pVM->trpm.s.aGuestTrapHandler[iTrap];
1279	}
1280
1281
1282	/**
1283	* Set guest trap/interrupt gate handler
1284	* Used for setting up trap gates used for kernel calls.
1285	*
1286	* @returns VBox status code.
1287	* @param pVM The cross context VM structure.
1288	* @param iTrap Interrupt/trap number.
1289	* @param pHandler GC handler pointer
1290	*/
1291	VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1292	{
1293	/* Only valid in raw mode which implies 1 VCPU */
1294	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1295	AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), VERR_TRPM_HM_IPE);
1296	PVMCPU pVCpu = &pVM->aCpus[0];
1297
1298	/*
1299	* Validate.
1300	*/
1301	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1302	{
1303	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1304	return VERR_INVALID_PARAMETER;
1305	}
1306
1307	AssertReturn(pHandler == TRPM_INVALID_HANDLER \|\| PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1308
1309	uint16_t cbIDT;
1310	RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1311	if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1312	return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1313
1314	if (pHandler == TRPM_INVALID_HANDLER)
1315	{
1316	/* clear trap handler */
1317	Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1318	return trpmClearGuestTrapHandler(pVM, iTrap);
1319	}
1320
1321	/*
1322	* Read the guest IDT entry.
1323	*/
1324	VBOXIDTE GuestIdte;
1325	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1326	if (RT_FAILURE(rc))
1327	{
1328	AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1329	return rc;
1330	}
1331
1332	if ( EMIsRawRing0Enabled(pVM)
1333	&& !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1334	{
1335	/*
1336	* Only replace handlers for which we are 100% certain there won't be
1337	* any host interrupts.
1338	*
1339	* 0x2E is safe on Windows because it's the system service interrupt gate. Not
1340	* quite certain if this is safe or not on 64-bit Vista, it probably is.
1341	*
1342	* 0x80 is safe on Linux because it's the syscall vector and is part of the
1343	* 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1344	* and will therefor never assign hardware interrupts to 0x80.
1345	*
1346	* Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1347	* to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1348	* Booting Linux/BSD guest will cause system lockups on most of the computers.
1349	* -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1350	* @bugref{3604}.
1351	*
1352	* PORTME - Check if your host keeps any of these gates free from hw ints.
1353	*
1354	* Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1355	*/
1356	/** @todo handle those dependencies better! */
1357	/** @todo Solve this in a proper manner. see @bugref{1186} */
1358	#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1359	if (iTrap == 0x2E)
1360	#elif defined(RT_OS_LINUX)
1361	if (iTrap == 0x80)
1362	#else
1363	if (0)
1364	#endif
1365	{
1366	if ( GuestIdte.Gen.u1Present
1367	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1368	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1369	&& GuestIdte.Gen.u2DPL == 3)
1370	{
1371	PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1372
1373	GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1374	GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1375	GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1376	GuestIdte.Gen.u16SegSel \|= 1; //ring 1
1377	*pIdte = GuestIdte;
1378
1379	/* Mark it for relocation purposes. */
1380	ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1381
1382	/* Also store it in our guest trap array. */
1383	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1384
1385	Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1386	return VINF_SUCCESS;
1387	}
1388	/* ok, let's try to install a trampoline handler then. */
1389	}
1390	}
1391
1392	if ( GuestIdte.Gen.u1Present
1393	&& ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1394	\|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1395	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0))
1396	{
1397	/*
1398	* Save handler which can be used for a trampoline call inside the GC
1399	*/
1400	Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1401	pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1402	return VINF_SUCCESS;
1403	}
1404	return VERR_INVALID_PARAMETER;
1405	}
1406
1407
1408	/**
1409	* Check if address is a gate handler (interrupt/trap/task/anything).
1410	*
1411	* @returns True is gate handler, false if not.
1412	*
1413	* @param pVM The cross context VM structure.
1414	* @param GCPtr GC address to check.
1415	*/
1416	VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1417	{
1418	/* Only valid in raw mode which implies 1 VCPU */
1419	Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1420	PVMCPU pVCpu = &pVM->aCpus[0];
1421
1422	/*
1423	* Read IDTR and calc last entry.
1424	*/
1425	uint16_t cbIDT;
1426	RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1427	unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1428	if (!cEntries)
1429	return false;
1430	RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1431
1432	/*
1433	* Outer loop: iterate pages.
1434	*/
1435	while (GCPtrIDTE <= GCPtrIDTELast)
1436	{
1437	/*
1438	* Convert this page to a HC address.
1439	* (This function checks for not-present pages.)
1440	*/
1441	PCVBOXIDTE pIDTE;
1442	PGMPAGEMAPLOCK Lock;
1443	int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1444	if (RT_SUCCESS(rc))
1445	{
1446	/*
1447	* Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1448	* N.B. Member of the Flat Earth Society...
1449	*/
1450	while (GCPtrIDTE <= GCPtrIDTELast)
1451	{
1452	if (pIDTE->Gen.u1Present)
1453	{
1454	RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1455	if (GCPtr == GCPtrHandler)
1456	{
1457	PGMPhysReleasePageMappingLock(pVM, &Lock);
1458	return true;
1459	}
1460	}
1461
1462	/* next entry */
1463	if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1464	{
1465	AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1466	("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1467	GCPtrIDTE += sizeof(VBOXIDTE);
1468	break;
1469	}
1470	GCPtrIDTE += sizeof(VBOXIDTE);
1471	pIDTE++;
1472	}
1473	PGMPhysReleasePageMappingLock(pVM, &Lock);
1474	}
1475	else
1476	{
1477	/* Skip to the next page (if any). Take care not to wrap around the address space. */
1478	if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1479	return false;
1480	GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1481	}
1482	}
1483	return false;
1484	}
1485
1486	#endif /* VBOX_WITH_RAW_MODE */
1487
1488	/**
1489	* Inject event (such as external irq or trap).
1490	*
1491	* @returns VBox status code.
1492	* @param pVM The cross context VM structure.
1493	* @param pVCpu The cross context virtual CPU structure.
1494	* @param enmEvent Trpm event type
1495	* @param pfInjected Where to store whether the event was injected or not.
1496	*/
1497	VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent, bool *pfInjected)
1498	{
1499	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1500	#ifdef VBOX_WITH_RAW_MODE
1501	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1502	#endif
1503	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1504	Assert(pfInjected);
1505	*pfInjected = false;
1506
1507	/* Currently only useful for external hardware interrupts. */
1508	Assert(enmEvent == TRPM_HARDWARE_INT);
1509
1510	#if defined(TRPM_FORWARD_TRAPS_IN_GC)
1511
1512	# ifdef LOG_ENABLED
1513	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "TRPMInject");
1514	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1515	# endif
1516
1517	Assert( !CPUMIsGuestInNestedHwvirtMode(pCtx)
1518	\|\| CPUMIsGuestVmxExitCtlsSet(pVCpu, pCtx, VMX_EXIT_CTLS_ACK_EXT_INT));
1519	uint8_t u8Interrupt = 0;
1520	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1521	Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1522	if (RT_SUCCESS(rc))
1523	{
1524	if (EMIsSupervisorCodeRecompiled(pVM) \|\| !VM_IS_RAW_MODE_ENABLED(pVM))
1525	{
1526	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1527	if (!VM_IS_NEM_ENABLED(pVM))
1528	{
1529	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1530	AssertRC(rc);
1531	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1532	}
1533	VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, u8Interrupt, enmEvent, 0, 0, 0);
1534	if (rcStrict == VINF_SUCCESS)
1535	return VINF_EM_RESCHEDULE;
1536	return VBOXSTRICTRC_TODO(rcStrict);
1537	}
1538
1539	/* If the guest gate is not patched, then we will check (again) if we can patch it. */
1540	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1541	{
1542	CSAMR3CheckGates(pVM, u8Interrupt, 1);
1543	Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1544	}
1545
1546	if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1547	{
1548	/* Must check pending forced actions as our IDT or GDT might be out of sync */
1549	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1550	if (rc == VINF_SUCCESS)
1551	{
1552	/* There's a handler -> let's execute it in raw mode */
1553	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1554	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1555	{
1556	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1557
1558	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1559	return VINF_EM_RESCHEDULE_RAW;
1560	}
1561	}
1562	}
1563	else
1564	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1565
1566	rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1567	AssertRCReturn(rc, rc);
1568	}
1569	else
1570	{
1571	/* Can happen if the interrupt is masked by TPR or APIC is disabled. */
1572	AssertMsg(rc == VERR_APIC_INTR_MASKED_BY_TPR \|\| rc == VERR_NO_DATA, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
1573	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM
1574	: VM_IS_NEM_ENABLED(pVM) ? VINF_EM_RESCHEDULE
1575	: VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1576	}
1577
1578	/** @todo check if it's safe to translate the patch address to the original guest address.
1579	* this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1580	*/
1581	/* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return codes below. */
1582
1583	/* Fall back to the recompiler */
1584	return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1585
1586	#else /* !TRPM_FORWARD_TRAPS_IN_GC */
1587	RT_NOREF3(pVM, enmEvent, pCtx);
1588	uint8_t u8Interrupt = 0;
1589	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1590	Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1591	if (RT_SUCCESS(rc))
1592	{
1593	*pfInjected = true;
1594	if (!VM_IS_NEM_ENABLED(pVM))
1595	{
1596	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1597	AssertRC(rc);
1598	}
1599	else
1600	{
1601	VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, u8Interrupt, enmEvent, 0, 0, 0);
1602	/** @todo NSTVMX: NSTSVM: We don't support nested VMX or nested SVM with NEM yet.
1603	* If so we should handle VINF_SVM_VMEXIT and VINF_VMX_VMEXIT codes here. */
1604	if (rcStrict != VINF_SUCCESS)
1605	return VBOXSTRICTRC_TODO(rcStrict);
1606	}
1607	STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1608	}
1609	else
1610	{
1611	/* Can happen if the interrupt is masked by TPR or APIC is disabled. */
1612	AssertMsg(rc == VERR_APIC_INTR_MASKED_BY_TPR \|\| rc == VERR_NO_DATA, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
1613	}
1614	return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM
1615	: VM_IS_NEM_ENABLED(pVM) ? VINF_EM_RESCHEDULE
1616	: VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1617	#endif /* !TRPM_FORWARD_TRAPS_IN_GC */
1618	}
1619
1620
1621	/**
1622	* Displays the pending TRPM event.
1623	*
1624	* @param pVM The cross context VM structure.
1625	* @param pHlp The info helper functions.
1626	* @param pszArgs Arguments, ignored.
1627	*/
1628	static DECLCALLBACK(void) trpmR3InfoEvent(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1629	{
1630	NOREF(pszArgs);
1631	PVMCPU pVCpu = VMMGetCpu(pVM);
1632	if (!pVCpu)
1633	pVCpu = &pVM->aCpus[0];
1634
1635	uint8_t uVector;
1636	uint8_t cbInstr;
1637	TRPMEVENT enmTrapEvent;
1638	RTGCUINT uErrorCode;
1639	RTGCUINTPTR uCR2;
1640	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrapEvent, &uErrorCode, &uCR2, &cbInstr);
1641	if (RT_SUCCESS(rc))
1642	{
1643	pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event\n", pVCpu->idCpu);
1644	static const char * const s_apszTrpmEventType[] =
1645	{
1646	"Trap",
1647	"Hardware Int",
1648	"Software Int"
1649	};
1650	if (RT_LIKELY((size_t)enmTrapEvent < RT_ELEMENTS(s_apszTrpmEventType)))
1651	{
1652	pHlp->pfnPrintf(pHlp, " Type = %s\n", s_apszTrpmEventType[enmTrapEvent]);
1653	pHlp->pfnPrintf(pHlp, " uVector = %#x\n", uVector);
1654	pHlp->pfnPrintf(pHlp, " uErrorCode = %#RGu\n", uErrorCode);
1655	pHlp->pfnPrintf(pHlp, " uCR2 = %#RGp\n", uCR2);
1656	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", cbInstr);
1657	}
1658	else
1659	pHlp->pfnPrintf(pHlp, " Type = %#x (Invalid!)\n", enmTrapEvent);
1660	}
1661	else if (rc == VERR_TRPM_NO_ACTIVE_TRAP)
1662	pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event (None)\n", pVCpu->idCpu);
1663	else
1664	pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event - Query failed! rc=%Rrc\n", pVCpu->idCpu, rc);
1665	}
1666

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source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 80007

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