VMMSwitcher.cpp@ 41671

Last change on this file since 41671 was 41671, checked in by vboxsync, 12 years ago
DISInstr* -> DISInstrToStr + cbOutput argument.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 37.7 KB

Line
1	/* $Id: VMMSwitcher.cpp 41671 2012-06-12 15:22:43Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_VMM
22	#include <VBox/vmm/vmm.h>
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/sup.h>
27	#include "VMMInternal.h"
28	#include "VMMSwitcher.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/dis.h>
31
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/alloc.h>
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/string.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Global Variables *
44	*******************************************************************************/
45	/** Array of switcher definitions.
46	* The type and index shall match!
47	*/
48	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
49	{
50	NULL, /* invalid entry */
51	#ifdef VBOX_WITH_RAW_MODE
52	# ifndef RT_ARCH_AMD64
53	&vmmR3Switcher32BitTo32Bit_Def,
54	&vmmR3Switcher32BitToPAE_Def,
55	&vmmR3Switcher32BitToAMD64_Def,
56	&vmmR3SwitcherPAETo32Bit_Def,
57	&vmmR3SwitcherPAEToPAE_Def,
58	&vmmR3SwitcherPAEToAMD64_Def,
59	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
60	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
61	&vmmR3SwitcherAMD64ToPAE_Def,
62	# else
63	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
64	# endif
65	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
66	# else /* RT_ARCH_AMD64 */
67	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
68	NULL, //&vmmR3Switcher32BitToPAE_Def,
69	NULL, //&vmmR3Switcher32BitToAMD64_Def,
70	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
71	NULL, //&vmmR3SwitcherPAEToPAE_Def,
72	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
73	&vmmR3SwitcherAMD64To32Bit_Def,
74	&vmmR3SwitcherAMD64ToPAE_Def,
75	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
76	# endif /* RT_ARCH_AMD64 */
77	#else /* !VBOX_WITH_RAW_MODE */
78	NULL,
79	NULL,
80	NULL,
81	NULL,
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL
87	#endif /* !VBOX_WITH_RAW_MODE */
88	};
89
90
91	/**
92	* VMMR3Init worker that initiates the switcher code (aka core code).
93	*
94	* This is core per VM code which might need fixups and/or for ease of use are
95	* put on linear contiguous backing.
96	*
97	* @returns VBox status code.
98	* @param pVM Pointer to the shared VM structure.
99	*/
100	int vmmR3SwitcherInit(PVM pVM)
101	{
102	#ifndef VBOX_WITH_RAW_MODE
103	return VINF_SUCCESS;
104	#else
105	/*
106	* Calc the size.
107	*/
108	unsigned cbCoreCode = 0;
109	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
110	{
111	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
112	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
113	if (pSwitcher)
114	{
115	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
116	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
117	}
118	}
119
120	/*
121	* Allocate contiguous pages for switchers and deal with
122	* conflicts in the intermediate mapping of the code.
123	*/
124	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
125	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
126	int rc = VERR_NO_MEMORY;
127	if (pVM->vmm.s.pvCoreCodeR3)
128	{
129	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
130	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
131	{
132	/* try more allocations - Solaris, Linux. */
133	const unsigned cTries = 8234;
134	struct VMMInitBadTry
135	{
136	RTR0PTR pvR0;
137	void *pvR3;
138	RTHCPHYS HCPhys;
139	RTUINT cb;
140	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
141	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
142	unsigned i = 0;
143	do
144	{
145	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
146	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
147	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
148	i++;
149	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
150	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
151	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
152	if (!pVM->vmm.s.pvCoreCodeR3)
153	break;
154	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
155	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
156	&& i < cTries - 1);
157
158	/* cleanup */
159	if (RT_FAILURE(rc))
160	{
161	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
162	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
163	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
164	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
165	i++;
166	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
167	}
168	while (i-- > 0)
169	{
170	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
171	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
172	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
173	}
174	RTMemTmpFree(paBadTries);
175	}
176	}
177	if (RT_SUCCESS(rc))
178	{
179	/*
180	* copy the code.
181	*/
182	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
183	{
184	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
185	if (pSwitcher)
186	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
187	pSwitcher->pvCode, pSwitcher->cbCode);
188	}
189
190	/*
191	* Map the code into the GC address space.
192	*/
193	RTGCPTR GCPtr;
194	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
195	cbCoreCode, "Core Code", &GCPtr);
196	if (RT_SUCCESS(rc))
197	{
198	pVM->vmm.s.pvCoreCodeRC = GCPtr;
199	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
200	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
201	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
202
203	/*
204	* Finally, PGM probably has selected a switcher already but we need
205	* to get the routine addresses, so we'll reselect it.
206	* This may legally fail so, we're ignoring the rc.
207	*/
208	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
209	return rc;
210	}
211
212	/* shit */
213	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
214	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
215	}
216	else
217	VMSetError(pVM, rc, RT_SRC_POS,
218	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
219	cbCoreCode);
220
221	pVM->vmm.s.pvCoreCodeR3 = NULL;
222	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
223	pVM->vmm.s.pvCoreCodeRC = 0;
224	return rc;
225	#endif
226	}
227
228	/**
229	* Relocate the switchers, called by VMMR#Relocate.
230	*
231	* @param pVM Pointer to the shared VM structure.
232	* @param offDelta The relocation delta.
233	*/
234	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
235	{
236	#ifdef VBOX_WITH_RAW_MODE
237	/*
238	* Relocate all the switchers.
239	*/
240	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
241	{
242	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
243	if (pSwitcher && pSwitcher->pfnRelocate)
244	{
245	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
246	pSwitcher->pfnRelocate(pVM,
247	pSwitcher,
248	pVM->vmm.s.pvCoreCodeR0 + off,
249	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
250	pVM->vmm.s.pvCoreCodeRC + off,
251	pVM->vmm.s.HCPhysCoreCode + off);
252	}
253	}
254
255	/*
256	* Recalc the RC address for the current switcher.
257	*/
258	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
259	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
260	pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
261	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
262	pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
263	pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
264	pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
265
266	// AssertFailed();
267	#else
268	NOREF(pVM);
269	#endif
270	NOREF(offDelta);
271	}
272
273
274	/**
275	* Generic switcher code relocator.
276	*
277	* @param pVM The VM handle.
278	* @param pSwitcher The switcher definition.
279	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
280	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
281	* @param GCPtrCode The guest context address corresponding to pu8Code.
282	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
283	* @param SelCS The hypervisor CS selector.
284	* @param SelDS The hypervisor DS selector.
285	* @param SelTSS The hypervisor TSS selector.
286	* @param GCPtrGDT The GC address of the hypervisor GDT.
287	* @param SelCS64 The 64-bit mode hypervisor CS selector.
288	*/
289	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
290	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
291	{
292	union
293	{
294	const uint8_t *pu8;
295	const uint16_t *pu16;
296	const uint32_t *pu32;
297	const uint64_t *pu64;
298	const void *pv;
299	uintptr_t u;
300	} u;
301	u.pv = pSwitcher->pvFixups;
302
303	/*
304	* Process fixups.
305	*/
306	uint8_t u8;
307	while ((u8 = *u.pu8++) != FIX_THE_END)
308	{
309	/*
310	* Get the source (where to write the fixup).
311	*/
312	uint32_t offSrc = *u.pu32++;
313	Assert(offSrc < pSwitcher->cbCode);
314	union
315	{
316	uint8_t *pu8;
317	uint16_t *pu16;
318	uint32_t *pu32;
319	uint64_t *pu64;
320	uintptr_t u;
321	} uSrc;
322	uSrc.pu8 = pu8CodeR3 + offSrc;
323
324	/* The fixup target and method depends on the type. */
325	switch (u8)
326	{
327	/*
328	* 32-bit relative, source in HC and target in GC.
329	*/
330	case FIX_HC_2_GC_NEAR_REL:
331	{
332	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
333	uint32_t offTrg = *u.pu32++;
334	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
335	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
336	break;
337	}
338
339	/*
340	* 32-bit relative, source in HC and target in ID.
341	*/
342	case FIX_HC_2_ID_NEAR_REL:
343	{
344	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
345	uint32_t offTrg = *u.pu32++;
346	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
347	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
348	break;
349	}
350
351	/*
352	* 32-bit relative, source in GC and target in HC.
353	*/
354	case FIX_GC_2_HC_NEAR_REL:
355	{
356	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
357	uint32_t offTrg = *u.pu32++;
358	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
359	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
360	break;
361	}
362
363	/*
364	* 32-bit relative, source in GC and target in ID.
365	*/
366	case FIX_GC_2_ID_NEAR_REL:
367	{
368	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
369	uint32_t offTrg = *u.pu32++;
370	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
371	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
372	break;
373	}
374
375	/*
376	* 32-bit relative, source in ID and target in HC.
377	*/
378	case FIX_ID_2_HC_NEAR_REL:
379	{
380	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
381	uint32_t offTrg = *u.pu32++;
382	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
383	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
384	break;
385	}
386
387	/*
388	* 32-bit relative, source in ID and target in HC.
389	*/
390	case FIX_ID_2_GC_NEAR_REL:
391	{
392	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
393	uint32_t offTrg = *u.pu32++;
394	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
395	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
396	break;
397	}
398
399	/*
400	* 16:32 far jump, target in GC.
401	*/
402	case FIX_GC_FAR32:
403	{
404	uint32_t offTrg = *u.pu32++;
405	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
406	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
407	*uSrc.pu16++ = SelCS;
408	break;
409	}
410
411	/*
412	* Make 32-bit GC pointer given CPUM offset.
413	*/
414	case FIX_GC_CPUM_OFF:
415	{
416	uint32_t offCPUM = *u.pu32++;
417	Assert(offCPUM < sizeof(pVM->cpum));
418	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
419	break;
420	}
421
422	/*
423	* Make 32-bit GC pointer given CPUMCPU offset.
424	*/
425	case FIX_GC_CPUMCPU_OFF:
426	{
427	uint32_t offCPUM = *u.pu32++;
428	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
429	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
430	break;
431	}
432
433	/*
434	* Make 32-bit GC pointer given VM offset.
435	*/
436	case FIX_GC_VM_OFF:
437	{
438	uint32_t offVM = *u.pu32++;
439	Assert(offVM < sizeof(VM));
440	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
441	break;
442	}
443
444	/*
445	* Make 32-bit HC pointer given CPUM offset.
446	*/
447	case FIX_HC_CPUM_OFF:
448	{
449	uint32_t offCPUM = *u.pu32++;
450	Assert(offCPUM < sizeof(pVM->cpum));
451	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
452	break;
453	}
454
455	/*
456	* Make 32-bit R0 pointer given VM offset.
457	*/
458	case FIX_HC_VM_OFF:
459	{
460	uint32_t offVM = *u.pu32++;
461	Assert(offVM < sizeof(VM));
462	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
463	break;
464	}
465
466	/*
467	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
468	*/
469	case FIX_INTER_32BIT_CR3:
470	{
471
472	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
473	break;
474	}
475
476	/*
477	* Store the PAE CR3 (32-bit) for the intermediate memory context.
478	*/
479	case FIX_INTER_PAE_CR3:
480	{
481
482	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
483	break;
484	}
485
486	/*
487	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
488	*/
489	case FIX_INTER_AMD64_CR3:
490	{
491
492	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
493	break;
494	}
495
496	/*
497	* Store Hypervisor CS (16-bit).
498	*/
499	case FIX_HYPER_CS:
500	{
501	*uSrc.pu16 = SelCS;
502	break;
503	}
504
505	/*
506	* Store Hypervisor DS (16-bit).
507	*/
508	case FIX_HYPER_DS:
509	{
510	*uSrc.pu16 = SelDS;
511	break;
512	}
513
514	/*
515	* Store Hypervisor TSS (16-bit).
516	*/
517	case FIX_HYPER_TSS:
518	{
519	*uSrc.pu16 = SelTSS;
520	break;
521	}
522
523	/*
524	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
525	*/
526	case FIX_GC_TSS_GDTE_DW2:
527	{
528	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
529	*uSrc.pu32 = (uint32_t)GCPtr;
530	break;
531	}
532
533	/*
534	* Store the EFER or mask for the 32->64 bit switcher.
535	*/
536	case FIX_EFER_OR_MASK:
537	{
538	uint32_t u32OrMask = MSR_K6_EFER_LME \| MSR_K6_EFER_SCE;
539	/** note: we don't care if cpuid 0x8000001 isn't supported as that implies long mode isn't either, so this switcher would never be used. */
540	if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
541	u32OrMask \|= MSR_K6_EFER_NXE;
542
543	*uSrc.pu32 = u32OrMask;
544	break;
545	}
546
547	/*
548	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
549	*/
550	case FIX_NO_FXSAVE_JMP:
551	{
552	uint32_t offTrg = *u.pu32++;
553	Assert(offTrg < pSwitcher->cbCode);
554	if (!CPUMSupportsFXSR(pVM))
555	{
556	uSrc.pu8++ = 0xe9; / jmp rel32 */
557	*uSrc.pu32++ = offTrg - (offSrc + 5);
558	}
559	else
560	{
561	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
562	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
563	}
564	break;
565	}
566
567	/*
568	* Insert relative jump to specified target it SYSENTER isn't used by the host.
569	*/
570	case FIX_NO_SYSENTER_JMP:
571	{
572	uint32_t offTrg = *u.pu32++;
573	Assert(offTrg < pSwitcher->cbCode);
574	if (!CPUMIsHostUsingSysEnter(pVM))
575	{
576	uSrc.pu8++ = 0xe9; / jmp rel32 */
577	*uSrc.pu32++ = offTrg - (offSrc + 5);
578	}
579	else
580	{
581	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
582	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
583	}
584	break;
585	}
586
587	/*
588	* Insert relative jump to specified target it SYSCALL isn't used by the host.
589	*/
590	case FIX_NO_SYSCALL_JMP:
591	{
592	uint32_t offTrg = *u.pu32++;
593	Assert(offTrg < pSwitcher->cbCode);
594	if (!CPUMIsHostUsingSysCall(pVM))
595	{
596	uSrc.pu8++ = 0xe9; / jmp rel32 */
597	*uSrc.pu32++ = offTrg - (offSrc + 5);
598	}
599	else
600	{
601	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
602	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
603	}
604	break;
605	}
606
607	/*
608	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
609	*/
610	case FIX_HC_32BIT:
611	{
612	uint32_t offTrg = *u.pu32++;
613	Assert(offSrc < pSwitcher->cbCode);
614	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
615	*uSrc.pu32 = R0PtrCode + offTrg;
616	break;
617	}
618
619	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
620	/*
621	* 64-bit HC Code Selector (no argument).
622	*/
623	case FIX_HC_64BIT_CS:
624	{
625	Assert(offSrc < pSwitcher->cbCode);
626	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
627	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
628	# else
629	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
630	# endif
631	break;
632	}
633
634	/*
635	* 64-bit HC pointer to the CPUM instance data (no argument).
636	*/
637	case FIX_HC_64BIT_CPUM:
638	{
639	Assert(offSrc < pSwitcher->cbCode);
640	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
641	break;
642	}
643	#endif
644	/*
645	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
646	*/
647	case FIX_HC_64BIT:
648	{
649	uint32_t offTrg = *u.pu32++;
650	Assert(offSrc < pSwitcher->cbCode);
651	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
652	*uSrc.pu64 = R0PtrCode + offTrg;
653	break;
654	}
655
656	#ifdef RT_ARCH_X86
657	case FIX_GC_64_BIT_CPUM_OFF:
658	{
659	uint32_t offCPUM = *u.pu32++;
660	Assert(offCPUM < sizeof(pVM->cpum));
661	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
662	break;
663	}
664	#endif
665
666	/*
667	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
668	*/
669	case FIX_ID_32BIT:
670	{
671	uint32_t offTrg = *u.pu32++;
672	Assert(offSrc < pSwitcher->cbCode);
673	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
674	*uSrc.pu32 = u32IDCode + offTrg;
675	break;
676	}
677
678	/*
679	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
680	*/
681	case FIX_ID_64BIT:
682	case FIX_HC_64BIT_NOCHECK:
683	{
684	uint32_t offTrg = *u.pu32++;
685	Assert(offSrc < pSwitcher->cbCode);
686	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
687	*uSrc.pu64 = u32IDCode + offTrg;
688	break;
689	}
690
691	/*
692	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
693	*/
694	case FIX_ID_FAR32_TO_64BIT_MODE:
695	{
696	uint32_t offTrg = *u.pu32++;
697	Assert(offSrc < pSwitcher->cbCode);
698	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
699	*uSrc.pu32++ = u32IDCode + offTrg;
700	*uSrc.pu16 = SelCS64;
701	AssertRelease(SelCS64);
702	break;
703	}
704
705	#ifdef VBOX_WITH_NMI
706	/*
707	* 32-bit address to the APIC base.
708	*/
709	case FIX_GC_APIC_BASE_32BIT:
710	{
711	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
712	break;
713	}
714	#endif
715
716	default:
717	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
718	break;
719	}
720	}
721
722	#ifdef LOG_ENABLED
723	/*
724	* If Log2 is enabled disassemble the switcher code.
725	*
726	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
727	*/
728	if (LogIs2Enabled())
729	{
730	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
731	" R0PtrCode = %p\n"
732	" pu8CodeR3 = %p\n"
733	" GCPtrCode = %RGv\n"
734	" u32IDCode = %08x\n"
735	" pVMRC = %RRv\n"
736	" pCPUMRC = %RRv\n"
737	" pVMR3 = %p\n"
738	" pCPUMR3 = %p\n"
739	" GCPtrGDT = %RGv\n"
740	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
741	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
742	" SelCS = %04x\n"
743	" SelDS = %04x\n"
744	" SelCS64 = %04x\n"
745	" SelTSS = %04x\n",
746	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
747	R0PtrCode,
748	pu8CodeR3,
749	GCPtrCode,
750	u32IDCode,
751	VM_RC_ADDR(pVM, pVM),
752	VM_RC_ADDR(pVM, &pVM->cpum),
753	pVM,
754	&pVM->cpum,
755	GCPtrGDT,
756	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
757	PGMGetHyperCR3(VMMGetCpu(pVM)),
758	SelCS, SelDS, SelCS64, SelTSS);
759
760	uint32_t offCode = 0;
761	while (offCode < pSwitcher->cbCode)
762	{
763	/*
764	* Figure out where this is.
765	*/
766	const char *pszDesc = NULL;
767	RTUINTPTR uBase;
768	uint32_t cbCode;
769	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
770	{
771	pszDesc = "HCCode0";
772	uBase = R0PtrCode;
773	offCode = pSwitcher->offHCCode0;
774	cbCode = pSwitcher->cbHCCode0;
775	}
776	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
777	{
778	pszDesc = "HCCode1";
779	uBase = R0PtrCode;
780	offCode = pSwitcher->offHCCode1;
781	cbCode = pSwitcher->cbHCCode1;
782	}
783	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
784	{
785	pszDesc = "GCCode";
786	uBase = GCPtrCode;
787	offCode = pSwitcher->offGCCode;
788	cbCode = pSwitcher->cbGCCode;
789	}
790	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
791	{
792	pszDesc = "IDCode0";
793	uBase = u32IDCode;
794	offCode = pSwitcher->offIDCode0;
795	cbCode = pSwitcher->cbIDCode0;
796	}
797	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
798	{
799	pszDesc = "IDCode1";
800	uBase = u32IDCode;
801	offCode = pSwitcher->offIDCode1;
802	cbCode = pSwitcher->cbIDCode1;
803	}
804	else
805	{
806	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
807	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
808	offCode++;
809	continue;
810	}
811
812	/*
813	* Disassemble it.
814	*/
815	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
816
817	while (cbCode > 0)
818	{
819	/* try label it */
820	if (pSwitcher->offR0HostToGuest == offCode)
821	RTLogPrintf(" *R0HostToGuest:\n");
822	if (pSwitcher->offGCGuestToHost == offCode)
823	RTLogPrintf(" *GCGuestToHost:\n");
824	if (pSwitcher->offGCCallTrampoline == offCode)
825	RTLogPrintf(" *GCCallTrampoline:\n");
826	if (pSwitcher->offGCGuestToHostAsm == offCode)
827	RTLogPrintf(" *GCGuestToHostAsm:\n");
828	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
829	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
830	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
831	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
832
833	/* disas */
834	uint32_t cbInstr = 0;
835	DISCPUSTATE Cpu;
836	char szDisas[256];
837	int rc = DISCoreOne((uintptr_t)pu8CodeR3 + offCode, CPUMODE_32BIT, &Cpu, &cbInstr);
838	if (RT_SUCCESS(rc))
839	{
840	Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
841	rc = DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
842	DIS_FMT_FLAGS_ADDR_LEFT \| DIS_FMT_FLAGS_BYTES_LEFT \| DIS_FMT_FLAGS_BYTES_SPACED
843	\| DIS_FMT_FLAGS_RELATIVE_BRANCH,
844	NULL, NULL);
845	}
846	if (RT_SUCCESS(rc))
847	RTLogPrintf(" %04x: %s\n", offCode, szDisas);
848	else
849	{
850	RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
851	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
852	cbInstr = 1;
853	}
854	offCode += cbInstr;
855	cbCode -= RT_MIN(cbInstr, cbCode);
856	}
857	}
858	}
859	#endif
860	}
861
862
863	/**
864	* Relocator for the 32-Bit to 32-Bit world switcher.
865	*/
866	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
867	{
868	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
869	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
870	}
871
872
873	/**
874	* Relocator for the 32-Bit to PAE world switcher.
875	*/
876	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
877	{
878	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
879	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
880	}
881
882
883	/**
884	* Relocator for the 32-Bit to AMD64 world switcher.
885	*/
886	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
887	{
888	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
889	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
890	}
891
892
893	/**
894	* Relocator for the PAE to 32-Bit world switcher.
895	*/
896	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
897	{
898	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
899	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
900	}
901
902
903	/**
904	* Relocator for the PAE to PAE world switcher.
905	*/
906	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
907	{
908	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
909	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
910	}
911
912	/**
913	* Relocator for the PAE to AMD64 world switcher.
914	*/
915	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
916	{
917	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
918	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
919	}
920
921
922	/**
923	* Relocator for the AMD64 to 32-bit world switcher.
924	*/
925	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
926	{
927	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
928	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
929	}
930
931
932	/**
933	* Relocator for the AMD64 to PAE world switcher.
934	*/
935	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
936	{
937	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
938	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
939	}
940
941
942	/**
943	* Selects the switcher to be used for switching to raw-mode context.
944	*
945	* @returns VBox status code.
946	* @param pVM VM handle.
947	* @param enmSwitcher The new switcher.
948	* @remark This function may be called before the VMM is initialized.
949	*/
950	VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
951	{
952	/*
953	* Validate input.
954	*/
955	if ( enmSwitcher < VMMSWITCHER_INVALID
956	\|\| enmSwitcher >= VMMSWITCHER_MAX)
957	{
958	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
959	return VERR_INVALID_PARAMETER;
960	}
961
962	/* Do nothing if the switcher is disabled. */
963	if (pVM->vmm.s.fSwitcherDisabled)
964	return VINF_SUCCESS;
965
966	/*
967	* Select the new switcher.
968	*/
969	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
970	if (pSwitcher)
971	{
972	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
973	pVM->vmm.s.enmSwitcher = enmSwitcher;
974
975	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
976	pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
977
978	RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
979	pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
980	pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
981	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
982	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
983	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
984	return VINF_SUCCESS;
985	}
986
987	return VERR_NOT_IMPLEMENTED;
988	}
989
990
991	/**
992	* Disable the switcher logic permanently.
993	*
994	* @returns VBox status code.
995	* @param pVM VM handle.
996	*/
997	VMMR3_INT_DECL(int) VMMR3DisableSwitcher(PVM pVM)
998	{
999	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1000	* @code
1001	* mov eax, VERR_VMM_DUMMY_SWITCHER
1002	* ret
1003	* @endcode
1004	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1005	*/
1006	pVM->vmm.s.fSwitcherDisabled = true;
1007	return VINF_SUCCESS;
1008	}
1009
1010
1011	/**
1012	* Gets the switcher to be used for switching to GC.
1013	*
1014	* @returns host to guest ring 0 switcher entrypoint
1015	* @param pVM VM handle.
1016	* @param enmSwitcher The new switcher.
1017	*/
1018	VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1019	{
1020	/*
1021	* Validate input.
1022	*/
1023	if ( enmSwitcher < VMMSWITCHER_INVALID
1024	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1025	{
1026	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1027	return NIL_RTR0PTR;
1028	}
1029
1030	/*
1031	* Select the new switcher.
1032	*/
1033	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1034	if (pSwitcher)
1035	{
1036	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1037	return pbCodeR0 + pSwitcher->offR0HostToGuest;
1038	}
1039	return NIL_RTR0PTR;
1040	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 41671

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