VMMSwitcher.cpp@ 41965

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1	/* $Id: VMMSwitcher.cpp 41965 2012-06-29 02:52:49Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_VMM
22	#include <VBox/vmm/vmm.h>
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/sup.h>
27	#include "VMMInternal.h"
28	#include "VMMSwitcher.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/dis.h>
31
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/alloc.h>
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/string.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Global Variables *
44	*******************************************************************************/
45	/** Array of switcher definitions.
46	* The type and index shall match!
47	*/
48	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
49	{
50	NULL, /* invalid entry */
51	#ifdef VBOX_WITH_RAW_MODE
52	# ifndef RT_ARCH_AMD64
53	&vmmR3Switcher32BitTo32Bit_Def,
54	&vmmR3Switcher32BitToPAE_Def,
55	&vmmR3Switcher32BitToAMD64_Def,
56	&vmmR3SwitcherPAETo32Bit_Def,
57	&vmmR3SwitcherPAEToPAE_Def,
58	&vmmR3SwitcherPAEToAMD64_Def,
59	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
60	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
61	&vmmR3SwitcherAMD64ToPAE_Def,
62	# else
63	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
64	# endif
65	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
66	# else /* RT_ARCH_AMD64 */
67	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
68	NULL, //&vmmR3Switcher32BitToPAE_Def,
69	NULL, //&vmmR3Switcher32BitToAMD64_Def,
70	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
71	NULL, //&vmmR3SwitcherPAEToPAE_Def,
72	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
73	&vmmR3SwitcherAMD64To32Bit_Def,
74	&vmmR3SwitcherAMD64ToPAE_Def,
75	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
76	# endif /* RT_ARCH_AMD64 */
77	#else /* !VBOX_WITH_RAW_MODE */
78	NULL,
79	NULL,
80	NULL,
81	NULL,
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL
87	#endif /* !VBOX_WITH_RAW_MODE */
88	};
89
90
91	/**
92	* VMMR3Init worker that initiates the switcher code (aka core code).
93	*
94	* This is core per VM code which might need fixups and/or for ease of use are
95	* put on linear contiguous backing.
96	*
97	* @returns VBox status code.
98	* @param pVM Pointer to the VM.
99	*/
100	int vmmR3SwitcherInit(PVM pVM)
101	{
102	#ifndef VBOX_WITH_RAW_MODE
103	return VINF_SUCCESS;
104	#else
105	/*
106	* Calc the size.
107	*/
108	unsigned cbCoreCode = 0;
109	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
110	{
111	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
112	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
113	if (pSwitcher)
114	{
115	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
116	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
117	}
118	}
119
120	/*
121	* Allocate contiguous pages for switchers and deal with
122	* conflicts in the intermediate mapping of the code.
123	*/
124	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
125	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
126	int rc = VERR_NO_MEMORY;
127	if (pVM->vmm.s.pvCoreCodeR3)
128	{
129	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
130	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
131	{
132	/* try more allocations - Solaris, Linux. */
133	const unsigned cTries = 8234;
134	struct VMMInitBadTry
135	{
136	RTR0PTR pvR0;
137	void *pvR3;
138	RTHCPHYS HCPhys;
139	RTUINT cb;
140	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
141	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
142	unsigned i = 0;
143	do
144	{
145	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
146	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
147	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
148	i++;
149	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
150	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
151	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
152	if (!pVM->vmm.s.pvCoreCodeR3)
153	break;
154	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
155	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
156	&& i < cTries - 1);
157
158	/* cleanup */
159	if (RT_FAILURE(rc))
160	{
161	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
162	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
163	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
164	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
165	i++;
166	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
167	}
168	while (i-- > 0)
169	{
170	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
171	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
172	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
173	}
174	RTMemTmpFree(paBadTries);
175	}
176	}
177	if (RT_SUCCESS(rc))
178	{
179	/*
180	* copy the code.
181	*/
182	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
183	{
184	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
185	if (pSwitcher)
186	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
187	pSwitcher->pvCode, pSwitcher->cbCode);
188	}
189
190	/*
191	* Map the code into the GC address space.
192	*/
193	RTGCPTR GCPtr;
194	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
195	cbCoreCode, "Core Code", &GCPtr);
196	if (RT_SUCCESS(rc))
197	{
198	pVM->vmm.s.pvCoreCodeRC = GCPtr;
199	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
200	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
201	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
202
203	/*
204	* Finally, PGM probably has selected a switcher already but we need
205	* to get the routine addresses, so we'll reselect it.
206	* This may legally fail so, we're ignoring the rc.
207	*/
208	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
209	return rc;
210	}
211
212	/* shit */
213	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
214	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
215	}
216	else
217	VMSetError(pVM, rc, RT_SRC_POS,
218	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
219	cbCoreCode);
220
221	pVM->vmm.s.pvCoreCodeR3 = NULL;
222	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
223	pVM->vmm.s.pvCoreCodeRC = 0;
224	return rc;
225	#endif
226	}
227
228	/**
229	* Relocate the switchers, called by VMMR#Relocate.
230	*
231	* @param pVM Pointer to the VM.
232	* @param offDelta The relocation delta.
233	*/
234	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
235	{
236	#ifdef VBOX_WITH_RAW_MODE
237	/*
238	* Relocate all the switchers.
239	*/
240	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
241	{
242	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
243	if (pSwitcher && pSwitcher->pfnRelocate)
244	{
245	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
246	pSwitcher->pfnRelocate(pVM,
247	pSwitcher,
248	pVM->vmm.s.pvCoreCodeR0 + off,
249	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
250	pVM->vmm.s.pvCoreCodeRC + off,
251	pVM->vmm.s.HCPhysCoreCode + off);
252	}
253	}
254
255	/*
256	* Recalc the RC address for the current switcher.
257	*/
258	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
259	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
260	pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
261	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
262	pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
263
264	// AssertFailed();
265	#else
266	NOREF(pVM);
267	#endif
268	NOREF(offDelta);
269	}
270
271
272	/**
273	* Generic switcher code relocator.
274	*
275	* @param pVM Pointer to the VM.
276	* @param pSwitcher The switcher definition.
277	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
278	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
279	* @param GCPtrCode The guest context address corresponding to pu8Code.
280	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
281	* @param SelCS The hypervisor CS selector.
282	* @param SelDS The hypervisor DS selector.
283	* @param SelTSS The hypervisor TSS selector.
284	* @param GCPtrGDT The GC address of the hypervisor GDT.
285	* @param SelCS64 The 64-bit mode hypervisor CS selector.
286	*/
287	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
288	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
289	{
290	union
291	{
292	const uint8_t *pu8;
293	const uint16_t *pu16;
294	const uint32_t *pu32;
295	const uint64_t *pu64;
296	const void *pv;
297	uintptr_t u;
298	} u;
299	u.pv = pSwitcher->pvFixups;
300
301	/*
302	* Process fixups.
303	*/
304	uint8_t u8;
305	while ((u8 = *u.pu8++) != FIX_THE_END)
306	{
307	/*
308	* Get the source (where to write the fixup).
309	*/
310	uint32_t offSrc = *u.pu32++;
311	Assert(offSrc < pSwitcher->cbCode);
312	union
313	{
314	uint8_t *pu8;
315	uint16_t *pu16;
316	uint32_t *pu32;
317	uint64_t *pu64;
318	uintptr_t u;
319	} uSrc;
320	uSrc.pu8 = pu8CodeR3 + offSrc;
321
322	/* The fixup target and method depends on the type. */
323	switch (u8)
324	{
325	/*
326	* 32-bit relative, source in HC and target in GC.
327	*/
328	case FIX_HC_2_GC_NEAR_REL:
329	{
330	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
331	uint32_t offTrg = *u.pu32++;
332	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
333	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
334	break;
335	}
336
337	/*
338	* 32-bit relative, source in HC and target in ID.
339	*/
340	case FIX_HC_2_ID_NEAR_REL:
341	{
342	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
343	uint32_t offTrg = *u.pu32++;
344	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
345	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
346	break;
347	}
348
349	/*
350	* 32-bit relative, source in GC and target in HC.
351	*/
352	case FIX_GC_2_HC_NEAR_REL:
353	{
354	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
355	uint32_t offTrg = *u.pu32++;
356	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
357	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
358	break;
359	}
360
361	/*
362	* 32-bit relative, source in GC and target in ID.
363	*/
364	case FIX_GC_2_ID_NEAR_REL:
365	{
366	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
367	uint32_t offTrg = *u.pu32++;
368	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
369	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
370	break;
371	}
372
373	/*
374	* 32-bit relative, source in ID and target in HC.
375	*/
376	case FIX_ID_2_HC_NEAR_REL:
377	{
378	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
379	uint32_t offTrg = *u.pu32++;
380	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
381	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
382	break;
383	}
384
385	/*
386	* 32-bit relative, source in ID and target in HC.
387	*/
388	case FIX_ID_2_GC_NEAR_REL:
389	{
390	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
391	uint32_t offTrg = *u.pu32++;
392	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
393	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
394	break;
395	}
396
397	/*
398	* 16:32 far jump, target in GC.
399	*/
400	case FIX_GC_FAR32:
401	{
402	uint32_t offTrg = *u.pu32++;
403	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
404	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
405	*uSrc.pu16++ = SelCS;
406	break;
407	}
408
409	/*
410	* Make 32-bit GC pointer given CPUM offset.
411	*/
412	case FIX_GC_CPUM_OFF:
413	{
414	uint32_t offCPUM = *u.pu32++;
415	Assert(offCPUM < sizeof(pVM->cpum));
416	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
417	break;
418	}
419
420	/*
421	* Make 32-bit GC pointer given CPUMCPU offset.
422	*/
423	case FIX_GC_CPUMCPU_OFF:
424	{
425	uint32_t offCPUM = *u.pu32++;
426	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
427	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
428	break;
429	}
430
431	/*
432	* Make 32-bit GC pointer given VM offset.
433	*/
434	case FIX_GC_VM_OFF:
435	{
436	uint32_t offVM = *u.pu32++;
437	Assert(offVM < sizeof(VM));
438	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
439	break;
440	}
441
442	/*
443	* Make 32-bit HC pointer given CPUM offset.
444	*/
445	case FIX_HC_CPUM_OFF:
446	{
447	uint32_t offCPUM = *u.pu32++;
448	Assert(offCPUM < sizeof(pVM->cpum));
449	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
450	break;
451	}
452
453	/*
454	* Make 32-bit R0 pointer given VM offset.
455	*/
456	case FIX_HC_VM_OFF:
457	{
458	uint32_t offVM = *u.pu32++;
459	Assert(offVM < sizeof(VM));
460	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
461	break;
462	}
463
464	/*
465	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
466	*/
467	case FIX_INTER_32BIT_CR3:
468	{
469
470	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
471	break;
472	}
473
474	/*
475	* Store the PAE CR3 (32-bit) for the intermediate memory context.
476	*/
477	case FIX_INTER_PAE_CR3:
478	{
479
480	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
481	break;
482	}
483
484	/*
485	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
486	*/
487	case FIX_INTER_AMD64_CR3:
488	{
489
490	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
491	break;
492	}
493
494	/*
495	* Store Hypervisor CS (16-bit).
496	*/
497	case FIX_HYPER_CS:
498	{
499	*uSrc.pu16 = SelCS;
500	break;
501	}
502
503	/*
504	* Store Hypervisor DS (16-bit).
505	*/
506	case FIX_HYPER_DS:
507	{
508	*uSrc.pu16 = SelDS;
509	break;
510	}
511
512	/*
513	* Store Hypervisor TSS (16-bit).
514	*/
515	case FIX_HYPER_TSS:
516	{
517	*uSrc.pu16 = SelTSS;
518	break;
519	}
520
521	/*
522	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
523	*/
524	case FIX_GC_TSS_GDTE_DW2:
525	{
526	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
527	*uSrc.pu32 = (uint32_t)GCPtr;
528	break;
529	}
530
531	/*
532	* Store the EFER or mask for the 32->64 bit switcher.
533	*/
534	case FIX_EFER_OR_MASK:
535	{
536	uint32_t u32OrMask = MSR_K6_EFER_LME \| MSR_K6_EFER_SCE;
537	/** note: we don't care if cpuid 0x8000001 isn't supported as that implies long mode isn't either, so this switcher would never be used. */
538	if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
539	u32OrMask \|= MSR_K6_EFER_NXE;
540
541	*uSrc.pu32 = u32OrMask;
542	break;
543	}
544
545	/*
546	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
547	*/
548	case FIX_NO_FXSAVE_JMP:
549	{
550	uint32_t offTrg = *u.pu32++;
551	Assert(offTrg < pSwitcher->cbCode);
552	if (!CPUMSupportsFXSR(pVM))
553	{
554	uSrc.pu8++ = 0xe9; / jmp rel32 */
555	*uSrc.pu32++ = offTrg - (offSrc + 5);
556	}
557	else
558	{
559	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
560	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
561	}
562	break;
563	}
564
565	/*
566	* Insert relative jump to specified target it SYSENTER isn't used by the host.
567	*/
568	case FIX_NO_SYSENTER_JMP:
569	{
570	uint32_t offTrg = *u.pu32++;
571	Assert(offTrg < pSwitcher->cbCode);
572	if (!CPUMIsHostUsingSysEnter(pVM))
573	{
574	uSrc.pu8++ = 0xe9; / jmp rel32 */
575	*uSrc.pu32++ = offTrg - (offSrc + 5);
576	}
577	else
578	{
579	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
580	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
581	}
582	break;
583	}
584
585	/*
586	* Insert relative jump to specified target it SYSCALL isn't used by the host.
587	*/
588	case FIX_NO_SYSCALL_JMP:
589	{
590	uint32_t offTrg = *u.pu32++;
591	Assert(offTrg < pSwitcher->cbCode);
592	if (!CPUMIsHostUsingSysCall(pVM))
593	{
594	uSrc.pu8++ = 0xe9; / jmp rel32 */
595	*uSrc.pu32++ = offTrg - (offSrc + 5);
596	}
597	else
598	{
599	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
600	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
601	}
602	break;
603	}
604
605	/*
606	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
607	*/
608	case FIX_HC_32BIT:
609	{
610	uint32_t offTrg = *u.pu32++;
611	Assert(offSrc < pSwitcher->cbCode);
612	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
613	*uSrc.pu32 = R0PtrCode + offTrg;
614	break;
615	}
616
617	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
618	/*
619	* 64-bit HC Code Selector (no argument).
620	*/
621	case FIX_HC_64BIT_CS:
622	{
623	Assert(offSrc < pSwitcher->cbCode);
624	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
625	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
626	# else
627	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
628	# endif
629	break;
630	}
631
632	/*
633	* 64-bit HC pointer to the CPUM instance data (no argument).
634	*/
635	case FIX_HC_64BIT_CPUM:
636	{
637	Assert(offSrc < pSwitcher->cbCode);
638	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
639	break;
640	}
641	#endif
642	/*
643	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
644	*/
645	case FIX_HC_64BIT:
646	{
647	uint32_t offTrg = *u.pu32++;
648	Assert(offSrc < pSwitcher->cbCode);
649	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
650	*uSrc.pu64 = R0PtrCode + offTrg;
651	break;
652	}
653
654	#ifdef RT_ARCH_X86
655	case FIX_GC_64_BIT_CPUM_OFF:
656	{
657	uint32_t offCPUM = *u.pu32++;
658	Assert(offCPUM < sizeof(pVM->cpum));
659	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
660	break;
661	}
662	#endif
663
664	/*
665	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
666	*/
667	case FIX_ID_32BIT:
668	{
669	uint32_t offTrg = *u.pu32++;
670	Assert(offSrc < pSwitcher->cbCode);
671	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
672	*uSrc.pu32 = u32IDCode + offTrg;
673	break;
674	}
675
676	/*
677	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
678	*/
679	case FIX_ID_64BIT:
680	case FIX_HC_64BIT_NOCHECK:
681	{
682	uint32_t offTrg = *u.pu32++;
683	Assert(offSrc < pSwitcher->cbCode);
684	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
685	*uSrc.pu64 = u32IDCode + offTrg;
686	break;
687	}
688
689	/*
690	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
691	*/
692	case FIX_ID_FAR32_TO_64BIT_MODE:
693	{
694	uint32_t offTrg = *u.pu32++;
695	Assert(offSrc < pSwitcher->cbCode);
696	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
697	*uSrc.pu32++ = u32IDCode + offTrg;
698	*uSrc.pu16 = SelCS64;
699	AssertRelease(SelCS64);
700	break;
701	}
702
703	#ifdef VBOX_WITH_NMI
704	/*
705	* 32-bit address to the APIC base.
706	*/
707	case FIX_GC_APIC_BASE_32BIT:
708	{
709	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
710	break;
711	}
712	#endif
713
714	default:
715	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
716	break;
717	}
718	}
719
720	#ifdef LOG_ENABLED
721	/*
722	* If Log2 is enabled disassemble the switcher code.
723	*
724	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
725	*/
726	if (LogIs2Enabled())
727	{
728	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
729	" R0PtrCode = %p\n"
730	" pu8CodeR3 = %p\n"
731	" GCPtrCode = %RGv\n"
732	" u32IDCode = %08x\n"
733	" pVMRC = %RRv\n"
734	" pCPUMRC = %RRv\n"
735	" pVMR3 = %p\n"
736	" pCPUMR3 = %p\n"
737	" GCPtrGDT = %RGv\n"
738	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
739	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
740	" SelCS = %04x\n"
741	" SelDS = %04x\n"
742	" SelCS64 = %04x\n"
743	" SelTSS = %04x\n",
744	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
745	R0PtrCode,
746	pu8CodeR3,
747	GCPtrCode,
748	u32IDCode,
749	VM_RC_ADDR(pVM, pVM),
750	VM_RC_ADDR(pVM, &pVM->cpum),
751	pVM,
752	&pVM->cpum,
753	GCPtrGDT,
754	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
755	PGMGetHyperCR3(VMMGetCpu(pVM)),
756	SelCS, SelDS, SelCS64, SelTSS);
757
758	uint32_t offCode = 0;
759	while (offCode < pSwitcher->cbCode)
760	{
761	/*
762	* Figure out where this is.
763	*/
764	const char *pszDesc = NULL;
765	RTUINTPTR uBase;
766	uint32_t cbCode;
767	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
768	{
769	pszDesc = "HCCode0";
770	uBase = R0PtrCode;
771	offCode = pSwitcher->offHCCode0;
772	cbCode = pSwitcher->cbHCCode0;
773	}
774	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
775	{
776	pszDesc = "HCCode1";
777	uBase = R0PtrCode;
778	offCode = pSwitcher->offHCCode1;
779	cbCode = pSwitcher->cbHCCode1;
780	}
781	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
782	{
783	pszDesc = "GCCode";
784	uBase = GCPtrCode;
785	offCode = pSwitcher->offGCCode;
786	cbCode = pSwitcher->cbGCCode;
787	}
788	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
789	{
790	pszDesc = "IDCode0";
791	uBase = u32IDCode;
792	offCode = pSwitcher->offIDCode0;
793	cbCode = pSwitcher->cbIDCode0;
794	}
795	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
796	{
797	pszDesc = "IDCode1";
798	uBase = u32IDCode;
799	offCode = pSwitcher->offIDCode1;
800	cbCode = pSwitcher->cbIDCode1;
801	}
802	else
803	{
804	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
805	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
806	offCode++;
807	continue;
808	}
809
810	/*
811	* Disassemble it.
812	*/
813	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
814
815	while (cbCode > 0)
816	{
817	/* try label it */
818	if (pSwitcher->offR0HostToGuest == offCode)
819	RTLogPrintf(" *R0HostToGuest:\n");
820	if (pSwitcher->offGCGuestToHost == offCode)
821	RTLogPrintf(" *GCGuestToHost:\n");
822	if (pSwitcher->offGCCallTrampoline == offCode)
823	RTLogPrintf(" *GCCallTrampoline:\n");
824	if (pSwitcher->offGCGuestToHostAsm == offCode)
825	RTLogPrintf(" *GCGuestToHostAsm:\n");
826
827	/* disas */
828	uint32_t cbInstr = 0;
829	DISCPUSTATE Cpu;
830	char szDisas[256];
831	int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
832	if (RT_SUCCESS(rc))
833	{
834	Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
835	DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
836	DIS_FMT_FLAGS_ADDR_LEFT \| DIS_FMT_FLAGS_BYTES_LEFT \| DIS_FMT_FLAGS_BYTES_SPACED
837	\| DIS_FMT_FLAGS_RELATIVE_BRANCH,
838	NULL, NULL);
839	}
840	if (RT_SUCCESS(rc))
841	RTLogPrintf(" %04x: %s\n", offCode, szDisas);
842	else
843	{
844	RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
845	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
846	cbInstr = 1;
847	}
848	offCode += cbInstr;
849	cbCode -= RT_MIN(cbInstr, cbCode);
850	}
851	}
852	}
853	#endif
854	}
855
856
857	/**
858	* Relocator for the 32-Bit to 32-Bit world switcher.
859	*/
860	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
861	{
862	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
863	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
864	}
865
866
867	/**
868	* Relocator for the 32-Bit to PAE world switcher.
869	*/
870	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
871	{
872	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
873	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
874	}
875
876
877	/**
878	* Relocator for the 32-Bit to AMD64 world switcher.
879	*/
880	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
881	{
882	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
883	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
884	}
885
886
887	/**
888	* Relocator for the PAE to 32-Bit world switcher.
889	*/
890	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
891	{
892	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
893	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
894	}
895
896
897	/**
898	* Relocator for the PAE to PAE world switcher.
899	*/
900	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
901	{
902	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
903	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
904	}
905
906	/**
907	* Relocator for the PAE to AMD64 world switcher.
908	*/
909	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
910	{
911	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
912	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
913	}
914
915
916	/**
917	* Relocator for the AMD64 to 32-bit world switcher.
918	*/
919	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
920	{
921	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
922	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
923	}
924
925
926	/**
927	* Relocator for the AMD64 to PAE world switcher.
928	*/
929	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
930	{
931	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
932	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
933	}
934
935
936	/**
937	* Selects the switcher to be used for switching to raw-mode context.
938	*
939	* @returns VBox status code.
940	* @param pVM Pointer to the VM.
941	* @param enmSwitcher The new switcher.
942	* @remark This function may be called before the VMM is initialized.
943	*/
944	VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
945	{
946	/*
947	* Validate input.
948	*/
949	if ( enmSwitcher < VMMSWITCHER_INVALID
950	\|\| enmSwitcher >= VMMSWITCHER_MAX)
951	{
952	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
953	return VERR_INVALID_PARAMETER;
954	}
955
956	/* Do nothing if the switcher is disabled. */
957	if (pVM->vmm.s.fSwitcherDisabled)
958	return VINF_SUCCESS;
959
960	/*
961	* Select the new switcher.
962	*/
963	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
964	if (pSwitcher)
965	{
966	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
967	pVM->vmm.s.enmSwitcher = enmSwitcher;
968
969	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
970	pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
971
972	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
973	pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
974	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
975	pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
976	return VINF_SUCCESS;
977	}
978
979	return VERR_NOT_IMPLEMENTED;
980	}
981
982
983	/**
984	* Disable the switcher logic permanently.
985	*
986	* @returns VBox status code.
987	* @param pVM Pointer to the VM.
988	*/
989	VMMR3_INT_DECL(int) VMMR3DisableSwitcher(PVM pVM)
990	{
991	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
992	* @code
993	* mov eax, VERR_VMM_DUMMY_SWITCHER
994	* ret
995	* @endcode
996	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
997	*/
998	pVM->vmm.s.fSwitcherDisabled = true;
999	return VINF_SUCCESS;
1000	}
1001
1002
1003	/**
1004	* Gets the switcher to be used for switching to GC.
1005	*
1006	* @returns host to guest ring 0 switcher entrypoint
1007	* @param pVM Pointer to the VM.
1008	* @param enmSwitcher The new switcher.
1009	*/
1010	VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1011	{
1012	/*
1013	* Validate input.
1014	*/
1015	if ( enmSwitcher < VMMSWITCHER_INVALID
1016	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1017	{
1018	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1019	return NIL_RTR0PTR;
1020	}
1021
1022	/*
1023	* Select the new switcher.
1024	*/
1025	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1026	if (pSwitcher)
1027	{
1028	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1029	return pbCodeR0 + pSwitcher->offR0HostToGuest;
1030	}
1031	return NIL_RTR0PTR;
1032	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 41965

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