VMMSwitcher.cpp@ 44410

Last change on this file since 44410 was 44168, checked in by vboxsync, 12 years ago
nit
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 37.4 KB

Line
1	/* $Id: VMMSwitcher.cpp 44168 2012-12-19 17:49:07Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_VMM
22	#include <VBox/vmm/vmm.h>
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/sup.h>
27	#include "VMMInternal.h"
28	#include "VMMSwitcher.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/dis.h>
31
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/alloc.h>
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/string.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Global Variables *
44	*******************************************************************************/
45	/** Array of switcher definitions.
46	* The type and index shall match!
47	*/
48	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
49	{
50	NULL, /* invalid entry */
51	#ifdef VBOX_WITH_RAW_MODE
52	# ifndef RT_ARCH_AMD64
53	&vmmR3Switcher32BitTo32Bit_Def,
54	&vmmR3Switcher32BitToPAE_Def,
55	&vmmR3Switcher32BitToAMD64_Def,
56	&vmmR3SwitcherPAETo32Bit_Def,
57	&vmmR3SwitcherPAEToPAE_Def,
58	&vmmR3SwitcherPAEToAMD64_Def,
59	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
60	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
61	&vmmR3SwitcherAMD64ToPAE_Def,
62	# else
63	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
64	# endif
65	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
66	# else /* RT_ARCH_AMD64 */
67	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
68	NULL, //&vmmR3Switcher32BitToPAE_Def,
69	NULL, //&vmmR3Switcher32BitToAMD64_Def,
70	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
71	NULL, //&vmmR3SwitcherPAEToPAE_Def,
72	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
73	&vmmR3SwitcherAMD64To32Bit_Def,
74	&vmmR3SwitcherAMD64ToPAE_Def,
75	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
76	# endif /* RT_ARCH_AMD64 */
77	#else /* !VBOX_WITH_RAW_MODE */
78	NULL,
79	NULL,
80	NULL,
81	NULL,
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL
87	#endif /* !VBOX_WITH_RAW_MODE */
88	};
89
90
91	/**
92	* VMMR3Init worker that initiates the switcher code (aka core code).
93	*
94	* This is core per VM code which might need fixups and/or for ease of use are
95	* put on linear contiguous backing.
96	*
97	* @returns VBox status code.
98	* @param pVM Pointer to the VM.
99	*/
100	int vmmR3SwitcherInit(PVM pVM)
101	{
102	#ifndef VBOX_WITH_RAW_MODE
103	return VINF_SUCCESS;
104	#else
105	/*
106	* Calc the size.
107	*/
108	unsigned cbCoreCode = 0;
109	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
110	{
111	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
112	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
113	if (pSwitcher)
114	{
115	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
116	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
117	}
118	}
119
120	/*
121	* Allocate contiguous pages for switchers and deal with
122	* conflicts in the intermediate mapping of the code.
123	*/
124	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
125	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
126	int rc = VERR_NO_MEMORY;
127	if (pVM->vmm.s.pvCoreCodeR3)
128	{
129	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
130	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
131	{
132	/* try more allocations - Solaris, Linux. */
133	const unsigned cTries = 8234;
134	struct VMMInitBadTry
135	{
136	RTR0PTR pvR0;
137	void *pvR3;
138	RTHCPHYS HCPhys;
139	RTUINT cb;
140	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
141	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
142	unsigned i = 0;
143	do
144	{
145	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
146	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
147	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
148	i++;
149	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
150	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
151	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
152	if (!pVM->vmm.s.pvCoreCodeR3)
153	break;
154	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
155	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
156	&& i < cTries - 1);
157
158	/* cleanup */
159	if (RT_FAILURE(rc))
160	{
161	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
162	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
163	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
164	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
165	i++;
166	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
167	}
168	while (i-- > 0)
169	{
170	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
171	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
172	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
173	}
174	RTMemTmpFree(paBadTries);
175	}
176	}
177	if (RT_SUCCESS(rc))
178	{
179	/*
180	* copy the code.
181	*/
182	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
183	{
184	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
185	if (pSwitcher)
186	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
187	pSwitcher->pvCode, pSwitcher->cbCode);
188	}
189
190	/*
191	* Map the code into the GC address space.
192	*/
193	RTGCPTR GCPtr;
194	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
195	cbCoreCode, "Core Code", &GCPtr);
196	if (RT_SUCCESS(rc))
197	{
198	pVM->vmm.s.pvCoreCodeRC = GCPtr;
199	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
200	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
201	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
202
203	/*
204	* Finally, PGM probably has selected a switcher already but we need
205	* to get the routine addresses, so we'll reselect it.
206	* This may legally fail so, we're ignoring the rc.
207	*/
208	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
209	return rc;
210	}
211
212	/* shit */
213	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
214	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
215	}
216	else
217	VMSetError(pVM, rc, RT_SRC_POS,
218	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
219	cbCoreCode);
220
221	pVM->vmm.s.pvCoreCodeR3 = NULL;
222	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
223	pVM->vmm.s.pvCoreCodeRC = 0;
224	return rc;
225	#endif
226	}
227
228	/**
229	* Relocate the switchers, called by VMMR#Relocate.
230	*
231	* @param pVM Pointer to the VM.
232	* @param offDelta The relocation delta.
233	*/
234	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
235	{
236	#ifdef VBOX_WITH_RAW_MODE
237	/*
238	* Relocate all the switchers.
239	*/
240	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
241	{
242	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
243	if (pSwitcher && pSwitcher->pfnRelocate)
244	{
245	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
246	pSwitcher->pfnRelocate(pVM,
247	pSwitcher,
248	pVM->vmm.s.pvCoreCodeR0 + off,
249	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
250	pVM->vmm.s.pvCoreCodeRC + off,
251	pVM->vmm.s.HCPhysCoreCode + off);
252	}
253	}
254
255	/*
256	* Recalc the RC address for the current switcher.
257	*/
258	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
259	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
260	pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
261	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
262	pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
263	pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
264
265	// AssertFailed();
266	#else
267	NOREF(pVM);
268	#endif
269	NOREF(offDelta);
270	}
271
272
273	#ifdef VBOX_WITH_RAW_MODE
274
275	/**
276	* Generic switcher code relocator.
277	*
278	* @param pVM Pointer to the VM.
279	* @param pSwitcher The switcher definition.
280	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
281	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
282	* @param GCPtrCode The guest context address corresponding to pu8Code.
283	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
284	* @param SelCS The hypervisor CS selector.
285	* @param SelDS The hypervisor DS selector.
286	* @param SelTSS The hypervisor TSS selector.
287	* @param GCPtrGDT The GC address of the hypervisor GDT.
288	* @param SelCS64 The 64-bit mode hypervisor CS selector.
289	*/
290	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher,
291	RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
292	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
293	{
294	union
295	{
296	const uint8_t *pu8;
297	const uint16_t *pu16;
298	const uint32_t *pu32;
299	const uint64_t *pu64;
300	const void *pv;
301	uintptr_t u;
302	} u;
303	u.pv = pSwitcher->pvFixups;
304
305	/*
306	* Process fixups.
307	*/
308	uint8_t u8;
309	while ((u8 = *u.pu8++) != FIX_THE_END)
310	{
311	/*
312	* Get the source (where to write the fixup).
313	*/
314	uint32_t offSrc = *u.pu32++;
315	Assert(offSrc < pSwitcher->cbCode);
316	union
317	{
318	uint8_t *pu8;
319	uint16_t *pu16;
320	uint32_t *pu32;
321	uint64_t *pu64;
322	uintptr_t u;
323	} uSrc;
324	uSrc.pu8 = pu8CodeR3 + offSrc;
325
326	/* The fixup target and method depends on the type. */
327	switch (u8)
328	{
329	/*
330	* 32-bit relative, source in HC and target in GC.
331	*/
332	case FIX_HC_2_GC_NEAR_REL:
333	{
334	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
335	uint32_t offTrg = *u.pu32++;
336	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
337	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
338	break;
339	}
340
341	/*
342	* 32-bit relative, source in HC and target in ID.
343	*/
344	case FIX_HC_2_ID_NEAR_REL:
345	{
346	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
347	uint32_t offTrg = *u.pu32++;
348	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
349	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
350	break;
351	}
352
353	/*
354	* 32-bit relative, source in GC and target in HC.
355	*/
356	case FIX_GC_2_HC_NEAR_REL:
357	{
358	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
359	uint32_t offTrg = *u.pu32++;
360	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
361	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
362	break;
363	}
364
365	/*
366	* 32-bit relative, source in GC and target in ID.
367	*/
368	case FIX_GC_2_ID_NEAR_REL:
369	{
370	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
371	uint32_t offTrg = *u.pu32++;
372	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
373	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
374	break;
375	}
376
377	/*
378	* 32-bit relative, source in ID and target in HC.
379	*/
380	case FIX_ID_2_HC_NEAR_REL:
381	{
382	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
383	uint32_t offTrg = *u.pu32++;
384	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
385	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
386	break;
387	}
388
389	/*
390	* 32-bit relative, source in ID and target in HC.
391	*/
392	case FIX_ID_2_GC_NEAR_REL:
393	{
394	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
395	uint32_t offTrg = *u.pu32++;
396	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
397	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
398	break;
399	}
400
401	/*
402	* 16:32 far jump, target in GC.
403	*/
404	case FIX_GC_FAR32:
405	{
406	uint32_t offTrg = *u.pu32++;
407	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
408	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
409	*uSrc.pu16++ = SelCS;
410	break;
411	}
412
413	/*
414	* Make 32-bit GC pointer given CPUM offset.
415	*/
416	case FIX_GC_CPUM_OFF:
417	{
418	uint32_t offCPUM = *u.pu32++;
419	Assert(offCPUM < sizeof(pVM->cpum));
420	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
421	break;
422	}
423
424	/*
425	* Make 32-bit GC pointer given CPUMCPU offset.
426	*/
427	case FIX_GC_CPUMCPU_OFF:
428	{
429	uint32_t offCPUM = *u.pu32++;
430	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
431	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
432	break;
433	}
434
435	/*
436	* Make 32-bit GC pointer given VM offset.
437	*/
438	case FIX_GC_VM_OFF:
439	{
440	uint32_t offVM = *u.pu32++;
441	Assert(offVM < sizeof(VM));
442	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
443	break;
444	}
445
446	/*
447	* Make 32-bit HC pointer given CPUM offset.
448	*/
449	case FIX_HC_CPUM_OFF:
450	{
451	uint32_t offCPUM = *u.pu32++;
452	Assert(offCPUM < sizeof(pVM->cpum));
453	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
454	break;
455	}
456
457	/*
458	* Make 32-bit R0 pointer given VM offset.
459	*/
460	case FIX_HC_VM_OFF:
461	{
462	uint32_t offVM = *u.pu32++;
463	Assert(offVM < sizeof(VM));
464	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
465	break;
466	}
467
468	/*
469	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
470	*/
471	case FIX_INTER_32BIT_CR3:
472	{
473
474	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
475	break;
476	}
477
478	/*
479	* Store the PAE CR3 (32-bit) for the intermediate memory context.
480	*/
481	case FIX_INTER_PAE_CR3:
482	{
483
484	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
485	break;
486	}
487
488	/*
489	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
490	*/
491	case FIX_INTER_AMD64_CR3:
492	{
493
494	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
495	break;
496	}
497
498	/*
499	* Store Hypervisor CS (16-bit).
500	*/
501	case FIX_HYPER_CS:
502	{
503	*uSrc.pu16 = SelCS;
504	break;
505	}
506
507	/*
508	* Store Hypervisor DS (16-bit).
509	*/
510	case FIX_HYPER_DS:
511	{
512	*uSrc.pu16 = SelDS;
513	break;
514	}
515
516	/*
517	* Store Hypervisor TSS (16-bit).
518	*/
519	case FIX_HYPER_TSS:
520	{
521	*uSrc.pu16 = SelTSS;
522	break;
523	}
524
525	/*
526	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
527	*/
528	case FIX_GC_TSS_GDTE_DW2:
529	{
530	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
531	*uSrc.pu32 = (uint32_t)GCPtr;
532	break;
533	}
534
535	/*
536	* Store the EFER or mask for the 32->64 bit switcher.
537	*/
538	case FIX_EFER_OR_MASK:
539	{
540	uint32_t u32OrMask = MSR_K6_EFER_LME \| MSR_K6_EFER_SCE;
541	/*
542	* We don't care if cpuid 0x8000001 isn't supported as that implies
543	* long mode isn't supported either, so this switched would never be used.
544	*/
545	if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
546	u32OrMask \|= MSR_K6_EFER_NXE;
547
548	*uSrc.pu32 = u32OrMask;
549	break;
550	}
551
552	/*
553	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
554	*/
555	case FIX_NO_FXSAVE_JMP:
556	{
557	uint32_t offTrg = *u.pu32++;
558	Assert(offTrg < pSwitcher->cbCode);
559	if (!CPUMSupportsFXSR(pVM))
560	{
561	uSrc.pu8++ = 0xe9; / jmp rel32 */
562	*uSrc.pu32++ = offTrg - (offSrc + 5);
563	}
564	else
565	{
566	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
567	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
568	}
569	break;
570	}
571
572	/*
573	* Insert relative jump to specified target it SYSENTER isn't used by the host.
574	*/
575	case FIX_NO_SYSENTER_JMP:
576	{
577	uint32_t offTrg = *u.pu32++;
578	Assert(offTrg < pSwitcher->cbCode);
579	if (!CPUMIsHostUsingSysEnter(pVM))
580	{
581	uSrc.pu8++ = 0xe9; / jmp rel32 */
582	*uSrc.pu32++ = offTrg - (offSrc + 5);
583	}
584	else
585	{
586	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
587	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
588	}
589	break;
590	}
591
592	/*
593	* Insert relative jump to specified target it SYSCALL isn't used by the host.
594	*/
595	case FIX_NO_SYSCALL_JMP:
596	{
597	uint32_t offTrg = *u.pu32++;
598	Assert(offTrg < pSwitcher->cbCode);
599	if (!CPUMIsHostUsingSysCall(pVM))
600	{
601	uSrc.pu8++ = 0xe9; / jmp rel32 */
602	*uSrc.pu32++ = offTrg - (offSrc + 5);
603	}
604	else
605	{
606	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
607	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
608	}
609	break;
610	}
611
612	/*
613	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
614	*/
615	case FIX_HC_32BIT:
616	{
617	uint32_t offTrg = *u.pu32++;
618	Assert(offSrc < pSwitcher->cbCode);
619	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
620	*uSrc.pu32 = R0PtrCode + offTrg;
621	break;
622	}
623
624	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
625	/*
626	* 64-bit HC Code Selector (no argument).
627	*/
628	case FIX_HC_64BIT_CS:
629	{
630	Assert(offSrc < pSwitcher->cbCode);
631	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
632	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
633	# else
634	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
635	# endif
636	break;
637	}
638
639	/*
640	* 64-bit HC pointer to the CPUM instance data (no argument).
641	*/
642	case FIX_HC_64BIT_CPUM:
643	{
644	Assert(offSrc < pSwitcher->cbCode);
645	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
646	break;
647	}
648	#endif
649	/*
650	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
651	*/
652	case FIX_HC_64BIT:
653	{
654	uint32_t offTrg = *u.pu32++;
655	Assert(offSrc < pSwitcher->cbCode);
656	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
657	*uSrc.pu64 = R0PtrCode + offTrg;
658	break;
659	}
660
661	#ifdef RT_ARCH_X86
662	case FIX_GC_64_BIT_CPUM_OFF:
663	{
664	uint32_t offCPUM = *u.pu32++;
665	Assert(offCPUM < sizeof(pVM->cpum));
666	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
667	break;
668	}
669	#endif
670
671	/*
672	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
673	*/
674	case FIX_ID_32BIT:
675	{
676	uint32_t offTrg = *u.pu32++;
677	Assert(offSrc < pSwitcher->cbCode);
678	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
679	*uSrc.pu32 = u32IDCode + offTrg;
680	break;
681	}
682
683	/*
684	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
685	*/
686	case FIX_ID_64BIT:
687	case FIX_HC_64BIT_NOCHECK:
688	{
689	uint32_t offTrg = *u.pu32++;
690	Assert(offSrc < pSwitcher->cbCode);
691	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
692	*uSrc.pu64 = u32IDCode + offTrg;
693	break;
694	}
695
696	/*
697	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
698	*/
699	case FIX_ID_FAR32_TO_64BIT_MODE:
700	{
701	uint32_t offTrg = *u.pu32++;
702	Assert(offSrc < pSwitcher->cbCode);
703	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
704	*uSrc.pu32++ = u32IDCode + offTrg;
705	*uSrc.pu16 = SelCS64;
706	AssertRelease(SelCS64);
707	break;
708	}
709
710	#ifdef VBOX_WITH_NMI
711	/*
712	* 32-bit address to the APIC base.
713	*/
714	case FIX_GC_APIC_BASE_32BIT:
715	{
716	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
717	break;
718	}
719	#endif
720
721	default:
722	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
723	break;
724	}
725	}
726
727	#ifdef LOG_ENABLED
728	/*
729	* If Log2 is enabled disassemble the switcher code.
730	*
731	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
732	*/
733	if (LogIs2Enabled())
734	{
735	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
736	" R0PtrCode = %p\n"
737	" pu8CodeR3 = %p\n"
738	" GCPtrCode = %RGv\n"
739	" u32IDCode = %08x\n"
740	" pVMRC = %RRv\n"
741	" pCPUMRC = %RRv\n"
742	" pVMR3 = %p\n"
743	" pCPUMR3 = %p\n"
744	" GCPtrGDT = %RGv\n"
745	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
746	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
747	" SelCS = %04x\n"
748	" SelDS = %04x\n"
749	" SelCS64 = %04x\n"
750	" SelTSS = %04x\n",
751	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
752	R0PtrCode,
753	pu8CodeR3,
754	GCPtrCode,
755	u32IDCode,
756	VM_RC_ADDR(pVM, pVM),
757	VM_RC_ADDR(pVM, &pVM->cpum),
758	pVM,
759	&pVM->cpum,
760	GCPtrGDT,
761	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
762	PGMGetHyperCR3(VMMGetCpu(pVM)),
763	SelCS, SelDS, SelCS64, SelTSS);
764
765	uint32_t offCode = 0;
766	while (offCode < pSwitcher->cbCode)
767	{
768	/*
769	* Figure out where this is.
770	*/
771	const char *pszDesc = NULL;
772	RTUINTPTR uBase;
773	uint32_t cbCode;
774	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
775	{
776	pszDesc = "HCCode0";
777	uBase = R0PtrCode;
778	offCode = pSwitcher->offHCCode0;
779	cbCode = pSwitcher->cbHCCode0;
780	}
781	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
782	{
783	pszDesc = "HCCode1";
784	uBase = R0PtrCode;
785	offCode = pSwitcher->offHCCode1;
786	cbCode = pSwitcher->cbHCCode1;
787	}
788	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
789	{
790	pszDesc = "GCCode";
791	uBase = GCPtrCode;
792	offCode = pSwitcher->offGCCode;
793	cbCode = pSwitcher->cbGCCode;
794	}
795	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
796	{
797	pszDesc = "IDCode0";
798	uBase = u32IDCode;
799	offCode = pSwitcher->offIDCode0;
800	cbCode = pSwitcher->cbIDCode0;
801	}
802	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
803	{
804	pszDesc = "IDCode1";
805	uBase = u32IDCode;
806	offCode = pSwitcher->offIDCode1;
807	cbCode = pSwitcher->cbIDCode1;
808	}
809	else
810	{
811	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
812	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
813	offCode++;
814	continue;
815	}
816
817	/*
818	* Disassemble it.
819	*/
820	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
821
822	while (cbCode > 0)
823	{
824	/* try label it */
825	if (pSwitcher->offR0ToRawMode == offCode)
826	RTLogPrintf(" *R0ToRawMode:\n");
827	if (pSwitcher->offRCToHost == offCode)
828	RTLogPrintf(" *RCToHost:\n");
829	if (pSwitcher->offRCCallTrampoline == offCode)
830	RTLogPrintf(" *RCCallTrampoline:\n");
831	if (pSwitcher->offRCToHostAsm == offCode)
832	RTLogPrintf(" *RCToHostAsm:\n");
833	if (pSwitcher->offRCToHostAsmNoReturn == offCode)
834	RTLogPrintf(" *RCToHostAsmNoReturn:\n");
835
836	/* disas */
837	uint32_t cbInstr = 0;
838	DISCPUSTATE Cpu;
839	char szDisas[256];
840	int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
841	if (RT_SUCCESS(rc))
842	{
843	Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
844	DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
845	DIS_FMT_FLAGS_ADDR_LEFT \| DIS_FMT_FLAGS_BYTES_LEFT \| DIS_FMT_FLAGS_BYTES_SPACED
846	\| DIS_FMT_FLAGS_RELATIVE_BRANCH,
847	NULL, NULL);
848	}
849	if (RT_SUCCESS(rc))
850	RTLogPrintf(" %04x: %s\n", offCode, szDisas);
851	else
852	{
853	RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
854	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
855	cbInstr = 1;
856	}
857	offCode += cbInstr;
858	cbCode -= RT_MIN(cbInstr, cbCode);
859	}
860	}
861	}
862	#endif
863	}
864
865	/**
866	* Relocator for the 32-Bit to 32-Bit world switcher.
867	*/
868	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
869	{
870	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
871	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
872	}
873
874
875	/**
876	* Relocator for the 32-Bit to PAE world switcher.
877	*/
878	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
879	{
880	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
881	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
882	}
883
884
885	/**
886	* Relocator for the 32-Bit to AMD64 world switcher.
887	*/
888	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
889	{
890	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
891	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
892	}
893
894
895	/**
896	* Relocator for the PAE to 32-Bit world switcher.
897	*/
898	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
899	{
900	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
901	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
902	}
903
904
905	/**
906	* Relocator for the PAE to PAE world switcher.
907	*/
908	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
909	{
910	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
911	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
912	}
913
914	/**
915	* Relocator for the PAE to AMD64 world switcher.
916	*/
917	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
918	{
919	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
920	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
921	}
922
923
924	/**
925	* Relocator for the AMD64 to 32-bit world switcher.
926	*/
927	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
928	{
929	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
930	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
931	}
932
933
934	/**
935	* Relocator for the AMD64 to PAE world switcher.
936	*/
937	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
938	{
939	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
940	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
941	}
942
943
944	/**
945	* Selects the switcher to be used for switching to raw-mode context.
946	*
947	* @returns VBox status code.
948	* @param pVM Pointer to the VM.
949	* @param enmSwitcher The new switcher.
950	* @remark This function may be called before the VMM is initialized.
951	*/
952	VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
953	{
954	/*
955	* Validate input.
956	*/
957	if ( enmSwitcher < VMMSWITCHER_INVALID
958	\|\| enmSwitcher >= VMMSWITCHER_MAX)
959	{
960	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
961	return VERR_INVALID_PARAMETER;
962	}
963
964	/* Do nothing if the switcher is disabled. */
965	if (pVM->vmm.s.fSwitcherDisabled)
966	return VINF_SUCCESS;
967
968	/*
969	* Select the new switcher.
970	*/
971	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
972	if (pSwitcher)
973	{
974	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
975	pVM->vmm.s.enmSwitcher = enmSwitcher;
976
977	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
978	pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
979
980	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
981	pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
982	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
983	pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
984	pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
985	return VINF_SUCCESS;
986	}
987
988	return VERR_NOT_IMPLEMENTED;
989	}
990
991	#endif /* VBOX_WITH_RAW_MODE */
992
993
994	/**
995	* Disable the switcher logic permanently.
996	*
997	* @returns VBox status code.
998	* @param pVM Pointer to the VM.
999	*/
1000	VMMR3_INT_DECL(int) VMMR3DisableSwitcher(PVM pVM)
1001	{
1002	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1003	* @code
1004	* mov eax, VERR_VMM_DUMMY_SWITCHER
1005	* ret
1006	* @endcode
1007	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1008	*/
1009	pVM->vmm.s.fSwitcherDisabled = true;
1010	return VINF_SUCCESS;
1011	}
1012
1013
1014	/**
1015	* Gets the switcher to be used for switching to GC.
1016	*
1017	* @returns host to guest ring 0 switcher entrypoint
1018	* @param pVM Pointer to the VM.
1019	* @param enmSwitcher The new switcher.
1020	*/
1021	VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1022	{
1023	/*
1024	* Validate input.
1025	*/
1026	if ( enmSwitcher < VMMSWITCHER_INVALID
1027	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1028	{
1029	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1030	return NIL_RTR0PTR;
1031	}
1032
1033	/*
1034	* Select the new switcher.
1035	*/
1036	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1037	if (pSwitcher)
1038	{
1039	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1040	return pbCodeR0 + pSwitcher->offR0ToRawMode;
1041	}
1042	return NIL_RTR0PTR;
1043	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 44410

Download in other formats: