VMMSwitcher.cpp@ 45721

Last change on this file since 45721 was 45721, checked in by vboxsync, 12 years ago
VMM: fix r85247 for 32-bit hosts
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File size: 38.6 KB

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1	/* $Id: VMMSwitcher.cpp 45721 2013-04-25 08:11:30Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_VMM
23	#include <VBox/vmm/vmm.h>
24	#include <VBox/vmm/pgm.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/selm.h>
27	#include <VBox/vmm/mm.h>
28	#include <VBox/sup.h>
29	#include "VMMInternal.h"
30	#include "VMMSwitcher.h"
31	#include <VBox/vmm/vm.h>
32	#include <VBox/dis.h>
33
34	#include <VBox/err.h>
35	#include <VBox/param.h>
36	#include <iprt/assert.h>
37	#include <iprt/alloc.h>
38	#include <iprt/asm.h>
39	#include <iprt/asm-amd64-x86.h>
40	#include <iprt/string.h>
41	#include <iprt/ctype.h>
42
43	#include "HMInternal.h" /* for VBOX_ENABLE_64_BITS_GUESTS */
44
45
46	/*******************************************************************************
47	* Global Variables *
48	*******************************************************************************/
49	/** Array of switcher definitions.
50	* The type and index shall match!
51	*/
52	static PVMMSWITCHERDEF g_apRawModeSwitchers[VMMSWITCHER_MAX] =
53	{
54	NULL, /* invalid entry */
55	#ifdef VBOX_WITH_RAW_MODE
56	# ifndef RT_ARCH_AMD64
57	&vmmR3Switcher32BitTo32Bit_Def,
58	&vmmR3Switcher32BitToPAE_Def,
59	&vmmR3Switcher32BitToAMD64_Def,
60	&vmmR3SwitcherPAETo32Bit_Def,
61	&vmmR3SwitcherPAEToPAE_Def,
62	&vmmR3SwitcherPAEToAMD64_Def,
63	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
64	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
65	&vmmR3SwitcherAMD64ToPAE_Def,
66	# else
67	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
68	# endif
69	NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
70	# else /* RT_ARCH_AMD64 */
71	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
72	NULL, //&vmmR3Switcher32BitToPAE_Def,
73	NULL, //&vmmR3Switcher32BitToAMD64_Def,
74	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
75	NULL, //&vmmR3SwitcherPAEToPAE_Def,
76	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
77	&vmmR3SwitcherAMD64To32Bit_Def,
78	&vmmR3SwitcherAMD64ToPAE_Def,
79	NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
80	# endif /* RT_ARCH_AMD64 */
81	#else /* !VBOX_WITH_RAW_MODE */
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL,
87	NULL,
88	NULL,
89	NULL,
90	NULL,
91	#endif /* !VBOX_WITH_RAW_MODE */
92	#ifndef RT_ARCH_AMD64
93	&vmmR3SwitcherX86Stub_Def,
94	NULL,
95	#else
96	NULL,
97	&vmmR3SwitcherAMD64Stub_Def,
98	#endif
99	};
100
101	/** Array of switcher definitions.
102	* The type and index shall match!
103	*/
104	static PVMMSWITCHERDEF g_apHmSwitchers[VMMSWITCHER_MAX] =
105	{
106	NULL, /* invalid entry */
107	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
108	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
109	NULL, //&vmmR3Switcher32BitToPAE_Def,
110	&vmmR3Switcher32BitToAMD64_Def,
111	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
112	NULL, //&vmmR3SwitcherPAEToPAE_Def,
113	&vmmR3SwitcherPAEToAMD64_Def,
114	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
115	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
116	NULL, //&vmmR3SwitcherAMD64ToAMD64_Def,
117	#else /* !VBOX_WITH_RAW_MODE */
118	NULL,
119	NULL,
120	NULL,
121	NULL,
122	NULL,
123	NULL,
124	NULL,
125	NULL,
126	NULL,
127	#endif /* !VBOX_WITH_RAW_MODE */
128	#ifndef RT_ARCH_AMD64
129	&vmmR3SwitcherX86Stub_Def,
130	NULL,
131	#else
132	NULL,
133	&vmmR3SwitcherAMD64Stub_Def,
134	#endif
135	};
136
137
138	/**
139	* VMMR3Init worker that initiates the switcher code (aka core code).
140	*
141	* This is core per VM code which might need fixups and/or for ease of use are
142	* put on linear contiguous backing.
143	*
144	* @returns VBox status code.
145	* @param pVM Pointer to the VM.
146	*/
147	int vmmR3SwitcherInit(PVM pVM)
148	{
149	#ifndef VBOX_WITH_RAW_MODE /** @todo 64-bit on 32-bit. */
150	return VINF_SUCCESS;
151	#else
152	/*
153	* Calc the size.
154	*/
155	const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
156	unsigned cbCoreCode = 0;
157	for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
158	{
159	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
160	PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
161	if (pSwitcher)
162	{
163	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
164	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
165	}
166	}
167
168	/*
169	* Allocate contiguous pages for switchers and deal with
170	* conflicts in the intermediate mapping of the code.
171	*/
172	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
173	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
174	int rc = VERR_NO_MEMORY;
175	if (pVM->vmm.s.pvCoreCodeR3)
176	{
177	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
178	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
179	{
180	/* try more allocations - Solaris, Linux. */
181	const unsigned cTries = 8234;
182	struct VMMInitBadTry
183	{
184	RTR0PTR pvR0;
185	void *pvR3;
186	RTHCPHYS HCPhys;
187	RTUINT cb;
188	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
189	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
190	unsigned i = 0;
191	do
192	{
193	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
194	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
195	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
196	i++;
197	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
198	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
199	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
200	if (!pVM->vmm.s.pvCoreCodeR3)
201	break;
202	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
203	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
204	&& i < cTries - 1);
205
206	/* cleanup */
207	if (RT_FAILURE(rc))
208	{
209	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
210	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
211	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
212	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
213	i++;
214	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
215	}
216	while (i-- > 0)
217	{
218	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
219	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
220	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
221	}
222	RTMemTmpFree(paBadTries);
223	}
224	}
225	if (RT_SUCCESS(rc))
226	{
227	/*
228	* copy the code.
229	*/
230	for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
231	{
232	PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
233	if (pSwitcher)
234	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
235	pSwitcher->pvCode, pSwitcher->cbCode);
236	}
237
238	/*
239	* Map the code into the GC address space.
240	*/
241	RTGCPTR GCPtr;
242	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
243	cbCoreCode, "Core Code", &GCPtr);
244	if (RT_SUCCESS(rc))
245	{
246	pVM->vmm.s.pvCoreCodeRC = GCPtr;
247	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
248	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
249	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
250
251	/*
252	* Finally, PGM probably has selected a switcher already but we need
253	* to get the routine addresses, so we'll reselect it.
254	* This may legally fail so, we're ignoring the rc.
255	* Note! See HMIsEnabled hack in selector function.
256	*/
257	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
258	return rc;
259	}
260
261	/* shit */
262	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
263	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
264	}
265	else
266	VMSetError(pVM, rc, RT_SRC_POS,
267	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
268	cbCoreCode);
269
270	pVM->vmm.s.pvCoreCodeR3 = NULL;
271	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
272	pVM->vmm.s.pvCoreCodeRC = 0;
273	return rc;
274	#endif
275	}
276
277	/**
278	* Relocate the switchers, called by VMMR#Relocate.
279	*
280	* @param pVM Pointer to the VM.
281	* @param offDelta The relocation delta.
282	*/
283	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
284	{
285	#ifdef VBOX_WITH_RAW_MODE
286	/*
287	* Relocate all the switchers.
288	*/
289	const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
290	for (unsigned iSwitcher = 0; iSwitcher < VMMSWITCHER_MAX; iSwitcher++)
291	{
292	PVMMSWITCHERDEF pSwitcher = papSwitchers[iSwitcher];
293	if (pSwitcher && pSwitcher->pfnRelocate)
294	{
295	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
296	pSwitcher->pfnRelocate(pVM,
297	pSwitcher,
298	pVM->vmm.s.pvCoreCodeR0 + off,
299	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
300	pVM->vmm.s.pvCoreCodeRC + off,
301	pVM->vmm.s.HCPhysCoreCode + off);
302	}
303	}
304
305	/*
306	* Recalc the RC address for the current switcher.
307	*/
308	PVMMSWITCHERDEF pSwitcher = papSwitchers[pVM->vmm.s.enmSwitcher];
309	if (pSwitcher)
310	{
311	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
312	pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
313	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
314	pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
315	pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
316	}
317	else
318	AssertRelease(HMIsEnabled(pVM));
319
320	// AssertFailed();
321	#else
322	NOREF(pVM);
323	#endif
324	NOREF(offDelta);
325	}
326
327
328	#ifdef VBOX_WITH_RAW_MODE
329
330	/**
331	* Generic switcher code relocator.
332	*
333	* @param pVM Pointer to the VM.
334	* @param pSwitcher The switcher definition.
335	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
336	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
337	* @param GCPtrCode The guest context address corresponding to pu8Code.
338	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
339	* @param SelCS The hypervisor CS selector.
340	* @param SelDS The hypervisor DS selector.
341	* @param SelTSS The hypervisor TSS selector.
342	* @param GCPtrGDT The GC address of the hypervisor GDT.
343	* @param SelCS64 The 64-bit mode hypervisor CS selector.
344	*/
345	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher,
346	RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
347	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
348	{
349	union
350	{
351	const uint8_t *pu8;
352	const uint16_t *pu16;
353	const uint32_t *pu32;
354	const uint64_t *pu64;
355	const void *pv;
356	uintptr_t u;
357	} u;
358	u.pv = pSwitcher->pvFixups;
359
360	/*
361	* Process fixups.
362	*/
363	uint8_t u8;
364	while ((u8 = *u.pu8++) != FIX_THE_END)
365	{
366	/*
367	* Get the source (where to write the fixup).
368	*/
369	uint32_t offSrc = *u.pu32++;
370	Assert(offSrc < pSwitcher->cbCode);
371	union
372	{
373	uint8_t *pu8;
374	uint16_t *pu16;
375	uint32_t *pu32;
376	uint64_t *pu64;
377	uintptr_t u;
378	} uSrc;
379	uSrc.pu8 = pu8CodeR3 + offSrc;
380
381	/* The fixup target and method depends on the type. */
382	switch (u8)
383	{
384	/*
385	* 32-bit relative, source in HC and target in GC.
386	*/
387	case FIX_HC_2_GC_NEAR_REL:
388	{
389	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
390	uint32_t offTrg = *u.pu32++;
391	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
392	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
393	break;
394	}
395
396	/*
397	* 32-bit relative, source in HC and target in ID.
398	*/
399	case FIX_HC_2_ID_NEAR_REL:
400	{
401	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
402	uint32_t offTrg = *u.pu32++;
403	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
404	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
405	break;
406	}
407
408	/*
409	* 32-bit relative, source in GC and target in HC.
410	*/
411	case FIX_GC_2_HC_NEAR_REL:
412	{
413	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
414	uint32_t offTrg = *u.pu32++;
415	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
416	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
417	break;
418	}
419
420	/*
421	* 32-bit relative, source in GC and target in ID.
422	*/
423	case FIX_GC_2_ID_NEAR_REL:
424	{
425	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
426	uint32_t offTrg = *u.pu32++;
427	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
428	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
429	break;
430	}
431
432	/*
433	* 32-bit relative, source in ID and target in HC.
434	*/
435	case FIX_ID_2_HC_NEAR_REL:
436	{
437	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
438	uint32_t offTrg = *u.pu32++;
439	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
440	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
441	break;
442	}
443
444	/*
445	* 32-bit relative, source in ID and target in HC.
446	*/
447	case FIX_ID_2_GC_NEAR_REL:
448	{
449	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
450	uint32_t offTrg = *u.pu32++;
451	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
452	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
453	break;
454	}
455
456	/*
457	* 16:32 far jump, target in GC.
458	*/
459	case FIX_GC_FAR32:
460	{
461	uint32_t offTrg = *u.pu32++;
462	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
463	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
464	*uSrc.pu16++ = SelCS;
465	break;
466	}
467
468	/*
469	* Make 32-bit GC pointer given CPUM offset.
470	*/
471	case FIX_GC_CPUM_OFF:
472	{
473	uint32_t offCPUM = *u.pu32++;
474	Assert(offCPUM < sizeof(pVM->cpum));
475	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
476	break;
477	}
478
479	/*
480	* Make 32-bit GC pointer given CPUMCPU offset.
481	*/
482	case FIX_GC_CPUMCPU_OFF:
483	{
484	uint32_t offCPUM = *u.pu32++;
485	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
486	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
487	break;
488	}
489
490	/*
491	* Make 32-bit GC pointer given VM offset.
492	*/
493	case FIX_GC_VM_OFF:
494	{
495	uint32_t offVM = *u.pu32++;
496	Assert(offVM < sizeof(VM));
497	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
498	break;
499	}
500
501	/*
502	* Make 32-bit HC pointer given CPUM offset.
503	*/
504	case FIX_HC_CPUM_OFF:
505	{
506	uint32_t offCPUM = *u.pu32++;
507	Assert(offCPUM < sizeof(pVM->cpum));
508	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
509	break;
510	}
511
512	/*
513	* Make 32-bit R0 pointer given VM offset.
514	*/
515	case FIX_HC_VM_OFF:
516	{
517	uint32_t offVM = *u.pu32++;
518	Assert(offVM < sizeof(VM));
519	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
520	break;
521	}
522
523	/*
524	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
525	*/
526	case FIX_INTER_32BIT_CR3:
527	{
528
529	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
530	break;
531	}
532
533	/*
534	* Store the PAE CR3 (32-bit) for the intermediate memory context.
535	*/
536	case FIX_INTER_PAE_CR3:
537	{
538
539	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
540	break;
541	}
542
543	/*
544	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
545	*/
546	case FIX_INTER_AMD64_CR3:
547	{
548
549	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
550	break;
551	}
552
553	/*
554	* Store Hypervisor CS (16-bit).
555	*/
556	case FIX_HYPER_CS:
557	{
558	*uSrc.pu16 = SelCS;
559	break;
560	}
561
562	/*
563	* Store Hypervisor DS (16-bit).
564	*/
565	case FIX_HYPER_DS:
566	{
567	*uSrc.pu16 = SelDS;
568	break;
569	}
570
571	/*
572	* Store Hypervisor TSS (16-bit).
573	*/
574	case FIX_HYPER_TSS:
575	{
576	*uSrc.pu16 = SelTSS;
577	break;
578	}
579
580	/*
581	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
582	*/
583	case FIX_GC_TSS_GDTE_DW2:
584	{
585	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
586	*uSrc.pu32 = (uint32_t)GCPtr;
587	break;
588	}
589
590	/*
591	* Store the EFER or mask for the 32->64 bit switcher.
592	*/
593	case FIX_EFER_OR_MASK:
594	{
595	uint32_t u32OrMask = MSR_K6_EFER_LME \| MSR_K6_EFER_SCE;
596	/*
597	* We don't care if cpuid 0x8000001 isn't supported as that implies
598	* long mode isn't supported either, so this switched would never be used.
599	*/
600	if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
601	u32OrMask \|= MSR_K6_EFER_NXE;
602
603	*uSrc.pu32 = u32OrMask;
604	break;
605	}
606
607	/*
608	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
609	*/
610	case FIX_NO_FXSAVE_JMP:
611	{
612	uint32_t offTrg = *u.pu32++;
613	Assert(offTrg < pSwitcher->cbCode);
614	if (!CPUMSupportsFXSR(pVM))
615	{
616	uSrc.pu8++ = 0xe9; / jmp rel32 */
617	*uSrc.pu32++ = offTrg - (offSrc + 5);
618	}
619	else
620	{
621	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
622	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
623	}
624	break;
625	}
626
627	/*
628	* Insert relative jump to specified target it SYSENTER isn't used by the host.
629	*/
630	case FIX_NO_SYSENTER_JMP:
631	{
632	uint32_t offTrg = *u.pu32++;
633	Assert(offTrg < pSwitcher->cbCode);
634	if (!CPUMIsHostUsingSysEnter(pVM))
635	{
636	uSrc.pu8++ = 0xe9; / jmp rel32 */
637	*uSrc.pu32++ = offTrg - (offSrc + 5);
638	}
639	else
640	{
641	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
642	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
643	}
644	break;
645	}
646
647	/*
648	* Insert relative jump to specified target it SYSCALL isn't used by the host.
649	*/
650	case FIX_NO_SYSCALL_JMP:
651	{
652	uint32_t offTrg = *u.pu32++;
653	Assert(offTrg < pSwitcher->cbCode);
654	if (!CPUMIsHostUsingSysCall(pVM))
655	{
656	uSrc.pu8++ = 0xe9; / jmp rel32 */
657	*uSrc.pu32++ = offTrg - (offSrc + 5);
658	}
659	else
660	{
661	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
662	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
663	}
664	break;
665	}
666
667	/*
668	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
669	*/
670	case FIX_HC_32BIT:
671	{
672	uint32_t offTrg = *u.pu32++;
673	Assert(offSrc < pSwitcher->cbCode);
674	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
675	*uSrc.pu32 = R0PtrCode + offTrg;
676	break;
677	}
678
679	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
680	/*
681	* 64-bit HC Code Selector (no argument).
682	*/
683	case FIX_HC_64BIT_CS:
684	{
685	Assert(offSrc < pSwitcher->cbCode);
686	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
687	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
688	# else
689	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
690	# endif
691	break;
692	}
693
694	/*
695	* 64-bit HC pointer to the CPUM instance data (no argument).
696	*/
697	case FIX_HC_64BIT_CPUM:
698	{
699	Assert(offSrc < pSwitcher->cbCode);
700	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
701	break;
702	}
703	#endif
704	/*
705	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
706	*/
707	case FIX_HC_64BIT:
708	{
709	uint32_t offTrg = *u.pu32++;
710	Assert(offSrc < pSwitcher->cbCode);
711	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
712	*uSrc.pu64 = R0PtrCode + offTrg;
713	break;
714	}
715
716	#ifdef RT_ARCH_X86
717	case FIX_GC_64_BIT_CPUM_OFF:
718	{
719	uint32_t offCPUM = *u.pu32++;
720	Assert(offCPUM < sizeof(pVM->cpum));
721	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
722	break;
723	}
724	#endif
725
726	/*
727	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
728	*/
729	case FIX_ID_32BIT:
730	{
731	uint32_t offTrg = *u.pu32++;
732	Assert(offSrc < pSwitcher->cbCode);
733	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
734	*uSrc.pu32 = u32IDCode + offTrg;
735	break;
736	}
737
738	/*
739	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
740	*/
741	case FIX_ID_64BIT:
742	case FIX_HC_64BIT_NOCHECK:
743	{
744	uint32_t offTrg = *u.pu32++;
745	Assert(offSrc < pSwitcher->cbCode);
746	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
747	*uSrc.pu64 = u32IDCode + offTrg;
748	break;
749	}
750
751	/*
752	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
753	*/
754	case FIX_ID_FAR32_TO_64BIT_MODE:
755	{
756	uint32_t offTrg = *u.pu32++;
757	Assert(offSrc < pSwitcher->cbCode);
758	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
759	*uSrc.pu32++ = u32IDCode + offTrg;
760	*uSrc.pu16 = SelCS64;
761	AssertRelease(SelCS64);
762	break;
763	}
764
765	#ifdef VBOX_WITH_NMI
766	/*
767	* 32-bit address to the APIC base.
768	*/
769	case FIX_GC_APIC_BASE_32BIT:
770	{
771	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
772	break;
773	}
774	#endif
775
776	default:
777	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
778	break;
779	}
780	}
781
782	#ifdef LOG_ENABLED
783	/*
784	* If Log2 is enabled disassemble the switcher code.
785	*
786	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
787	*/
788	if (LogIs2Enabled())
789	{
790	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
791	" R0PtrCode = %p\n"
792	" pu8CodeR3 = %p\n"
793	" GCPtrCode = %RGv\n"
794	" u32IDCode = %08x\n"
795	" pVMRC = %RRv\n"
796	" pCPUMRC = %RRv\n"
797	" pVMR3 = %p\n"
798	" pCPUMR3 = %p\n"
799	" GCPtrGDT = %RGv\n"
800	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
801	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
802	" SelCS = %04x\n"
803	" SelDS = %04x\n"
804	" SelCS64 = %04x\n"
805	" SelTSS = %04x\n",
806	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
807	R0PtrCode,
808	pu8CodeR3,
809	GCPtrCode,
810	u32IDCode,
811	VM_RC_ADDR(pVM, pVM),
812	VM_RC_ADDR(pVM, &pVM->cpum),
813	pVM,
814	&pVM->cpum,
815	GCPtrGDT,
816	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
817	PGMGetHyperCR3(VMMGetCpu(pVM)),
818	SelCS, SelDS, SelCS64, SelTSS);
819
820	uint32_t offCode = 0;
821	while (offCode < pSwitcher->cbCode)
822	{
823	/*
824	* Figure out where this is.
825	*/
826	const char *pszDesc = NULL;
827	RTUINTPTR uBase;
828	uint32_t cbCode;
829	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
830	{
831	pszDesc = "HCCode0";
832	uBase = R0PtrCode;
833	offCode = pSwitcher->offHCCode0;
834	cbCode = pSwitcher->cbHCCode0;
835	}
836	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
837	{
838	pszDesc = "HCCode1";
839	uBase = R0PtrCode;
840	offCode = pSwitcher->offHCCode1;
841	cbCode = pSwitcher->cbHCCode1;
842	}
843	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
844	{
845	pszDesc = "GCCode";
846	uBase = GCPtrCode;
847	offCode = pSwitcher->offGCCode;
848	cbCode = pSwitcher->cbGCCode;
849	}
850	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
851	{
852	pszDesc = "IDCode0";
853	uBase = u32IDCode;
854	offCode = pSwitcher->offIDCode0;
855	cbCode = pSwitcher->cbIDCode0;
856	}
857	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
858	{
859	pszDesc = "IDCode1";
860	uBase = u32IDCode;
861	offCode = pSwitcher->offIDCode1;
862	cbCode = pSwitcher->cbIDCode1;
863	}
864	else
865	{
866	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
867	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
868	offCode++;
869	continue;
870	}
871
872	/*
873	* Disassemble it.
874	*/
875	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
876
877	while (cbCode > 0)
878	{
879	/* try label it */
880	if (pSwitcher->offR0ToRawMode == offCode)
881	RTLogPrintf(" *R0ToRawMode:\n");
882	if (pSwitcher->offRCToHost == offCode)
883	RTLogPrintf(" *RCToHost:\n");
884	if (pSwitcher->offRCCallTrampoline == offCode)
885	RTLogPrintf(" *RCCallTrampoline:\n");
886	if (pSwitcher->offRCToHostAsm == offCode)
887	RTLogPrintf(" *RCToHostAsm:\n");
888	if (pSwitcher->offRCToHostAsmNoReturn == offCode)
889	RTLogPrintf(" *RCToHostAsmNoReturn:\n");
890
891	/* disas */
892	uint32_t cbInstr = 0;
893	DISCPUSTATE Cpu;
894	char szDisas[256];
895	int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
896	if (RT_SUCCESS(rc))
897	{
898	Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
899	DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
900	DIS_FMT_FLAGS_ADDR_LEFT \| DIS_FMT_FLAGS_BYTES_LEFT \| DIS_FMT_FLAGS_BYTES_SPACED
901	\| DIS_FMT_FLAGS_RELATIVE_BRANCH,
902	NULL, NULL);
903	}
904	if (RT_SUCCESS(rc))
905	RTLogPrintf(" %04x: %s\n", offCode, szDisas);
906	else
907	{
908	RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
909	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
910	cbInstr = 1;
911	}
912	offCode += cbInstr;
913	cbCode -= RT_MIN(cbInstr, cbCode);
914	}
915	}
916	}
917	#endif
918	}
919
920	/**
921	* Relocator for the 32-Bit to 32-Bit world switcher.
922	*/
923	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
924	{
925	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
926	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
927	}
928
929
930	/**
931	* Relocator for the 32-Bit to PAE world switcher.
932	*/
933	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
934	{
935	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
936	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
937	}
938
939
940	/**
941	* Relocator for the 32-Bit to AMD64 world switcher.
942	*/
943	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
944	{
945	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
946	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
947	}
948
949
950	/**
951	* Relocator for the PAE to 32-Bit world switcher.
952	*/
953	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
954	{
955	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
956	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
957	}
958
959
960	/**
961	* Relocator for the PAE to PAE world switcher.
962	*/
963	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
964	{
965	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
966	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
967	}
968
969	/**
970	* Relocator for the PAE to AMD64 world switcher.
971	*/
972	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
973	{
974	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
975	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
976	}
977
978
979	/**
980	* Relocator for the AMD64 to 32-bit world switcher.
981	*/
982	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
983	{
984	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
985	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
986	}
987
988
989	/**
990	* Relocator for the AMD64 to PAE world switcher.
991	*/
992	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
993	{
994	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
995	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
996	}
997
998
999	/**
1000	* Selects the switcher to be used for switching to raw-mode context.
1001	*
1002	* @returns VBox status code.
1003	* @param pVM Pointer to the VM.
1004	* @param enmSwitcher The new switcher.
1005	* @remark This function may be called before the VMM is initialized.
1006	*/
1007	VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1008	{
1009	/*
1010	* Validate input.
1011	*/
1012	if ( enmSwitcher < VMMSWITCHER_INVALID
1013	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1014	{
1015	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1016	return VERR_INVALID_PARAMETER;
1017	}
1018
1019	/*
1020	* Override it if HM is active.
1021	*/
1022	if (HMIsEnabled(pVM))
1023	pVM->vmm.s.enmSwitcher = HC_ARCH_BITS == 64 ? VMMSWITCHER_AMD64_STUB : VMMSWITCHER_X86_STUB;
1024
1025	/*
1026	* Select the new switcher.
1027	*/
1028	const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
1029	PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
1030	if (pSwitcher)
1031	{
1032	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1033	pVM->vmm.s.enmSwitcher = enmSwitcher;
1034
1035	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1036	pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
1037
1038	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1039	pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
1040	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
1041	pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
1042	pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
1043	return VINF_SUCCESS;
1044	}
1045
1046	return VERR_NOT_IMPLEMENTED;
1047	}
1048
1049	#endif /* VBOX_WITH_RAW_MODE */
1050
1051
1052	/**
1053	* Gets the switcher to be used for switching to GC.
1054	*
1055	* @returns host to guest ring 0 switcher entrypoint
1056	* @param pVM Pointer to the VM.
1057	* @param enmSwitcher The new switcher.
1058	*/
1059	VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1060	{
1061	/*
1062	* Validate input.
1063	*/
1064	if ( enmSwitcher < VMMSWITCHER_INVALID
1065	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1066	{
1067	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1068	return NIL_RTR0PTR;
1069	}
1070
1071	/*
1072	* Select the new switcher.
1073	*/
1074	const PVMMSWITCHERDEF *papSwitchers = HMIsEnabled(pVM) ? g_apHmSwitchers : g_apRawModeSwitchers;
1075	PVMMSWITCHERDEF pSwitcher = papSwitchers[enmSwitcher];
1076	if (pSwitcher)
1077	{
1078	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1079	return pbCodeR0 + pSwitcher->offR0ToRawMode;
1080	}
1081	return NIL_RTR0PTR;
1082	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 45721

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