VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/target-x86/CPUMR3-x86.cpp

Last change on this file was 109215, checked in by vboxsync, 13 days ago

VMM: Move created target subdirs under VMMR3 and moved relevant CPUM files into them. jiraref:VBP-1653
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File size: 244.9 KB
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1/* $Id: CPUMR3-x86.cpp 109215 2025-05-09 07:50:57Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_CPUM
33#define CPUM_WITH_NONCONST_HOST_FEATURES
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/cpumctx-v1_6.h>
36#include <VBox/vmm/pgm.h>
37#include <VBox/vmm/pdmapic.h>
38#include <VBox/vmm/mm.h>
39#include <VBox/vmm/em.h>
40#include <VBox/vmm/iem.h>
41#include <VBox/vmm/selm.h>
42#include <VBox/vmm/dbgf.h>
43#include <VBox/vmm/hm.h>
44#include <VBox/vmm/hmvmxinline.h>
45#include <VBox/vmm/ssm.h>
46#include "CPUMInternal.h"
47#include <VBox/vmm/vm.h>
48#include <VBox/vmm/vmcc.h>
49
50#include <VBox/param.h>
51#include <VBox/dis.h>
52#include <VBox/err.h>
53#include <VBox/log.h>
54#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
55# include <iprt/asm-amd64-x86.h>
56#endif
57#include <iprt/assert.h>
58#include <iprt/cpuset.h>
59#include <iprt/mem.h>
60#include <iprt/mp.h>
61#include <iprt/rand.h>
62#include <iprt/string.h>
63
64
65/*********************************************************************************************************************************
66* Defined Constants And Macros *
67*********************************************************************************************************************************/
68/**
69 * This was used in the saved state up to the early life of version 14.
70 *
71 * It indicates that we may have some out-of-sync hidden segement registers.
72 * It is only relevant for raw-mode.
73 */
74#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
75
76
77/** For saved state only: Block injection of non-maskable interrupts to the guest.
78 * @note This flag was moved to CPUMCTX::eflags.uBoth in v7.0.4. */
79#define CPUM_OLD_VMCPU_FF_BLOCK_NMIS RT_BIT_64(25)
80
81
82/*********************************************************************************************************************************
83* Structures and Typedefs *
84*********************************************************************************************************************************/
85/**
86 * Map of variable-range MTRRs.
87 */
88typedef struct CPUMMTRRMAP
89{
90 /** The index of the next available MTRR. */
91 uint8_t idxMtrr;
92 /** The number of usable MTRRs. */
93 uint8_t cMtrrs;
94 /** Alignment padding. */
95 uint16_t uAlign;
96 /** The number of bytes to map via these MTRRs (not including UC regions). */
97 uint64_t cbToMap;
98 /** The number of bytes mapped via these MTRRs (not including UC regions). */
99 uint64_t cbMapped;
100 /** The variable-range MTRRs. */
101 X86MTRRVAR aMtrrs[CPUMCTX_MAX_MTRRVAR_COUNT];
102} CPUMMTRRMAP;
103/** Pointer to a CPUM variable-range MTRR structure. */
104typedef CPUMMTRRMAP *PCPUMMTRRMAP;
105/** Pointer to a const CPUM variable-range MTRR structure. */
106typedef CPUMMTRRMAP const *PCCPUMMTRRMAP;
107
108
109/*********************************************************************************************************************************
110* Internal Functions *
111*********************************************************************************************************************************/
112static int cpumR3MapMtrrs(PVM pVM);
113static DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116/*********************************************************************************************************************************
117* Global Variables *
118*********************************************************************************************************************************/
119/** Saved state field descriptors for CPUMCTX. */
120static const SSMFIELD g_aCpumCtxFields[] =
121{
122 SSMFIELD_ENTRY( CPUMCTX, rdi),
123 SSMFIELD_ENTRY( CPUMCTX, rsi),
124 SSMFIELD_ENTRY( CPUMCTX, rbp),
125 SSMFIELD_ENTRY( CPUMCTX, rax),
126 SSMFIELD_ENTRY( CPUMCTX, rbx),
127 SSMFIELD_ENTRY( CPUMCTX, rdx),
128 SSMFIELD_ENTRY( CPUMCTX, rcx),
129 SSMFIELD_ENTRY( CPUMCTX, rsp),
130 SSMFIELD_ENTRY( CPUMCTX, rflags),
131 SSMFIELD_ENTRY( CPUMCTX, rip),
132 SSMFIELD_ENTRY( CPUMCTX, r8),
133 SSMFIELD_ENTRY( CPUMCTX, r9),
134 SSMFIELD_ENTRY( CPUMCTX, r10),
135 SSMFIELD_ENTRY( CPUMCTX, r11),
136 SSMFIELD_ENTRY( CPUMCTX, r12),
137 SSMFIELD_ENTRY( CPUMCTX, r13),
138 SSMFIELD_ENTRY( CPUMCTX, r14),
139 SSMFIELD_ENTRY( CPUMCTX, r15),
140 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
141 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
142 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
143 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
144 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
145 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
146 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
147 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
148 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
149 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
150 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
151 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
152 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
153 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
154 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
155 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
156 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
157 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
158 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
159 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
160 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
161 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
162 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
163 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
164 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
165 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
166 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
167 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
168 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
169 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
170 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
171 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
172 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
173 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
174 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
175 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
176 SSMFIELD_ENTRY( CPUMCTX, cr0),
177 SSMFIELD_ENTRY( CPUMCTX, cr2),
178 SSMFIELD_ENTRY( CPUMCTX, cr3),
179 SSMFIELD_ENTRY( CPUMCTX, cr4),
180 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
181 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
182 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
183 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
184 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
185 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
186 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
187 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
188 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
189 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
190 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
191 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
192 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
193 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
194 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
195 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
196 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
197 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
198 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
199 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
200 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
201 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
202 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
203 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
204 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
205 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
206 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
207 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
208 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
209 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
210 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
211 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
212 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
213 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
214 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
215 SSMFIELD_ENTRY_TERM()
216};
217
218/** Saved state field descriptors for SVM nested hardware-virtualization
219 * Host State. */
220static const SSMFIELD g_aSvmHwvirtHostState[] =
221{
222 SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
223 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
224 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
225 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
226 SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
227 SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
228 SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
229 SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
230 SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
231 SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
232 SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
233 SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
234 SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
235 SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
236 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
237 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
238 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
239 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
240 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
241 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
242 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
243 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
244 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
245 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
246 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
247 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
248 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
249 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
250 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
251 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
252 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
253 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
254 SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
255 SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
256 SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
257 SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
258 SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
259 SSMFIELD_ENTRY_TERM()
260};
261
262/** Saved state field descriptors for VMX nested hardware-virtualization
263 * VMCS. */
264static const SSMFIELD g_aVmxHwvirtVmcs[] =
265{
266 SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
267 SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
268 SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
269 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
270 SSMFIELD_ENTRY_VER( VMXVVMCS, u32RestoreProcCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4),
271 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
272
273 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
274
275 SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
276 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
277 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
278 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
279 SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
280 SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
281 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
282 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
283 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
284
285 SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
286 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
287
288 SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
289 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
290 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
291 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
292 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
293 SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
294 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
295
296 SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
297 SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
298 SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
299 SSMFIELD_ENTRY_VER( VMXVVMCS, u16HlatPrefixSize, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
300 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
301
302 SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
303 SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
304 SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
305 SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
306 SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
307 SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
308 SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
309 SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
310 SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
311 SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
312 SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
313 SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
314 SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
315 SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
316 SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
317 SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
318 SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
319 SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
320 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
321
322 SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
323 SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
324 SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
325 SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
326 SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
327 SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
328 SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
329 SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
330 SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
331 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
332 SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
333 SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
334 SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
335 SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
336 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
337 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
338 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
339 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
340 SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
341 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
342 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
343 SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
344 SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
345 SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
346 SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
347 SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
348 SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
349 SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
350 SSMFIELD_ENTRY_VER( VMXVVMCS, u64PconfigExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
351 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HlatPtr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
352 SSMFIELD_ENTRY_VER( VMXVVMCS, u64ExitCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
353 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
354
355 SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
356 SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
357 SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
358 SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
359 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
360 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
361 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
362 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
363 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
364
365 SSMFIELD_ENTRY( VMXVVMCS, HostEs),
366 SSMFIELD_ENTRY( VMXVVMCS, HostCs),
367 SSMFIELD_ENTRY( VMXVVMCS, HostSs),
368 SSMFIELD_ENTRY( VMXVVMCS, HostDs),
369 SSMFIELD_ENTRY( VMXVVMCS, HostFs),
370 SSMFIELD_ENTRY( VMXVVMCS, HostGs),
371 SSMFIELD_ENTRY( VMXVVMCS, HostTr),
372 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
373
374 SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
375 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
376
377 SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
378 SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
379 SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
380 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
381 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
382
383 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
384 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
385 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
386 SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
387 SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
388 SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
389 SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
390 SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
391 SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
392 SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
393 SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
394 SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
395 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
396 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
397 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
398 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
399
400 SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
401 SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
402 SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
403 SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
404 SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
405 SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
406 SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
407 SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
408 SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
409 SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
410 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
411
412 SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
413 SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
414 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
415 SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
416 SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
417 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
418 SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
419 SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
420 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
421 SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
422 SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
423 SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
424 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
425 SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
426 SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
427 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
428 SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
429 SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
430 SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
431 SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
432 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
433 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
434 SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
435 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
436
437 SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
438 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
439 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
440 SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
441 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
442 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
443 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
444 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
445 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
446 SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
447 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
448 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
449 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
450
451 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
452 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
453 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
454 SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
455 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
456 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
457 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
458 SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
459 SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
460 SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
461 SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
462 SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
463 SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
464 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
465 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
466 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
467 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
468 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
469 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
470 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
471 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
472 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
473 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
474 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
475
476 SSMFIELD_ENTRY_TERM()
477};
478
479/** Saved state field descriptors for CPUMCTX. */
480static const SSMFIELD g_aCpumX87Fields[] =
481{
482 SSMFIELD_ENTRY( X86FXSTATE, FCW),
483 SSMFIELD_ENTRY( X86FXSTATE, FSW),
484 SSMFIELD_ENTRY( X86FXSTATE, FTW),
485 SSMFIELD_ENTRY( X86FXSTATE, FOP),
486 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
487 SSMFIELD_ENTRY( X86FXSTATE, CS),
488 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
489 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
490 SSMFIELD_ENTRY( X86FXSTATE, DS),
491 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
492 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
493 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
494 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
495 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
496 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
497 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
498 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
499 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
500 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
501 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
502 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
503 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
504 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
505 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
506 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
507 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
508 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
509 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
510 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
511 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
512 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
513 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
514 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
515 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
516 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
517 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
518 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
519 SSMFIELD_ENTRY_TERM()
520};
521
522/** Saved state field descriptors for X86XSAVEHDR. */
523static const SSMFIELD g_aCpumXSaveHdrFields[] =
524{
525 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
526 SSMFIELD_ENTRY_TERM()
527};
528
529/** Saved state field descriptors for X86XSAVEYMMHI. */
530static const SSMFIELD g_aCpumYmmHiFields[] =
531{
532 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
533 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
534 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
535 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
536 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
537 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
538 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
539 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
540 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
541 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
542 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
543 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
544 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
545 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
546 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
547 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
548 SSMFIELD_ENTRY_TERM()
549};
550
551/** Saved state field descriptors for X86XSAVEBNDREGS. */
552static const SSMFIELD g_aCpumBndRegsFields[] =
553{
554 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
555 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
556 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
557 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
558 SSMFIELD_ENTRY_TERM()
559};
560
561/** Saved state field descriptors for X86XSAVEBNDCFG. */
562static const SSMFIELD g_aCpumBndCfgFields[] =
563{
564 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
565 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
566 SSMFIELD_ENTRY_TERM()
567};
568
569#if 0 /** @todo */
570/** Saved state field descriptors for X86XSAVEOPMASK. */
571static const SSMFIELD g_aCpumOpmaskFields[] =
572{
573 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
574 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
575 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
576 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
577 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
578 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
579 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
580 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
581 SSMFIELD_ENTRY_TERM()
582};
583#endif
584
585/** Saved state field descriptors for X86XSAVEZMMHI256. */
586static const SSMFIELD g_aCpumZmmHi256Fields[] =
587{
588 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
589 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
590 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
591 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
592 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
593 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
594 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
595 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
596 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
597 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
598 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
599 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
600 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
601 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
602 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
603 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
604 SSMFIELD_ENTRY_TERM()
605};
606
607/** Saved state field descriptors for X86XSAVEZMM16HI. */
608static const SSMFIELD g_aCpumZmm16HiFields[] =
609{
610 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
611 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
612 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
613 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
614 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
615 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
616 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
617 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
618 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
619 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
620 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
621 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
622 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
623 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
624 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
625 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
626 SSMFIELD_ENTRY_TERM()
627};
628
629
630
631/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
632 * registeres changed. */
633static const SSMFIELD g_aCpumX87FieldsMem[] =
634{
635 SSMFIELD_ENTRY( X86FXSTATE, FCW),
636 SSMFIELD_ENTRY( X86FXSTATE, FSW),
637 SSMFIELD_ENTRY( X86FXSTATE, FTW),
638 SSMFIELD_ENTRY( X86FXSTATE, FOP),
639 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
640 SSMFIELD_ENTRY( X86FXSTATE, CS),
641 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
642 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
643 SSMFIELD_ENTRY( X86FXSTATE, DS),
644 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
645 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
646 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
647 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
648 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
649 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
650 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
651 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
652 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
653 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
654 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
655 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
656 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
657 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
658 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
659 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
660 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
661 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
662 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
663 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
664 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
665 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
666 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
667 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
668 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
669 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
670 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
671 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
672 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
673};
674
675/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
676 * registeres changed. */
677static const SSMFIELD g_aCpumCtxFieldsMem[] =
678{
679 SSMFIELD_ENTRY( CPUMCTX, rdi),
680 SSMFIELD_ENTRY( CPUMCTX, rsi),
681 SSMFIELD_ENTRY( CPUMCTX, rbp),
682 SSMFIELD_ENTRY( CPUMCTX, rax),
683 SSMFIELD_ENTRY( CPUMCTX, rbx),
684 SSMFIELD_ENTRY( CPUMCTX, rdx),
685 SSMFIELD_ENTRY( CPUMCTX, rcx),
686 SSMFIELD_ENTRY( CPUMCTX, rsp),
687 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
688 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
689 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
690 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
691 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
692 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
693 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
694 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
695 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
696 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
697 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
698 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
699 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
700 SSMFIELD_ENTRY( CPUMCTX, rflags),
701 SSMFIELD_ENTRY( CPUMCTX, rip),
702 SSMFIELD_ENTRY( CPUMCTX, r8),
703 SSMFIELD_ENTRY( CPUMCTX, r9),
704 SSMFIELD_ENTRY( CPUMCTX, r10),
705 SSMFIELD_ENTRY( CPUMCTX, r11),
706 SSMFIELD_ENTRY( CPUMCTX, r12),
707 SSMFIELD_ENTRY( CPUMCTX, r13),
708 SSMFIELD_ENTRY( CPUMCTX, r14),
709 SSMFIELD_ENTRY( CPUMCTX, r15),
710 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
711 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
712 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
713 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
714 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
715 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
716 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
717 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
718 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
719 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
720 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
721 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
722 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
723 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
724 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
725 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
726 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
727 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
728 SSMFIELD_ENTRY( CPUMCTX, cr0),
729 SSMFIELD_ENTRY( CPUMCTX, cr2),
730 SSMFIELD_ENTRY( CPUMCTX, cr3),
731 SSMFIELD_ENTRY( CPUMCTX, cr4),
732 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
733 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
734 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
735 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
736 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
737 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
738 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
739 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
740 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
741 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
742 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
743 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
744 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
745 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
746 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
747 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
748 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
749 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
750 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
751 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
752 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
753 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
754 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
755 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
756 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
757 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
758 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
759 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
760 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
761 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
762 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
763 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
764 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
765 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
766 SSMFIELD_ENTRY_TERM()
767};
768
769/** Saved state field descriptors for CPUMCTX_VER1_6. */
770static const SSMFIELD g_aCpumX87FieldsV16[] =
771{
772 SSMFIELD_ENTRY( X86FXSTATE, FCW),
773 SSMFIELD_ENTRY( X86FXSTATE, FSW),
774 SSMFIELD_ENTRY( X86FXSTATE, FTW),
775 SSMFIELD_ENTRY( X86FXSTATE, FOP),
776 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
777 SSMFIELD_ENTRY( X86FXSTATE, CS),
778 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
779 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
780 SSMFIELD_ENTRY( X86FXSTATE, DS),
781 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
782 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
783 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
784 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
785 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
786 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
787 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
788 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
789 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
790 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
791 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
792 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
793 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
794 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
795 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
796 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
797 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
798 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
799 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
800 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
801 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
802 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
803 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
804 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
805 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
806 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
807 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
808 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
809 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
810 SSMFIELD_ENTRY_TERM()
811};
812
813/** Saved state field descriptors for CPUMCTX_VER1_6. */
814static const SSMFIELD g_aCpumCtxFieldsV16[] =
815{
816 SSMFIELD_ENTRY( CPUMCTX, rdi),
817 SSMFIELD_ENTRY( CPUMCTX, rsi),
818 SSMFIELD_ENTRY( CPUMCTX, rbp),
819 SSMFIELD_ENTRY( CPUMCTX, rax),
820 SSMFIELD_ENTRY( CPUMCTX, rbx),
821 SSMFIELD_ENTRY( CPUMCTX, rdx),
822 SSMFIELD_ENTRY( CPUMCTX, rcx),
823 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
824 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
825 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
826 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
827 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
828 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
829 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
830 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
831 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
832 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
833 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
834 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
835 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
836 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
837 SSMFIELD_ENTRY( CPUMCTX, rflags),
838 SSMFIELD_ENTRY( CPUMCTX, rip),
839 SSMFIELD_ENTRY( CPUMCTX, r8),
840 SSMFIELD_ENTRY( CPUMCTX, r9),
841 SSMFIELD_ENTRY( CPUMCTX, r10),
842 SSMFIELD_ENTRY( CPUMCTX, r11),
843 SSMFIELD_ENTRY( CPUMCTX, r12),
844 SSMFIELD_ENTRY( CPUMCTX, r13),
845 SSMFIELD_ENTRY( CPUMCTX, r14),
846 SSMFIELD_ENTRY( CPUMCTX, r15),
847 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
848 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
849 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
850 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
851 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
852 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
853 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
854 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
855 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
856 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
857 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
858 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
859 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
860 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
861 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
862 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
863 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
864 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
865 SSMFIELD_ENTRY( CPUMCTX, cr0),
866 SSMFIELD_ENTRY( CPUMCTX, cr2),
867 SSMFIELD_ENTRY( CPUMCTX, cr3),
868 SSMFIELD_ENTRY( CPUMCTX, cr4),
869 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
870 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
871 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
872 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
873 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
874 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
875 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
876 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
877 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
878 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
879 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
880 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
881 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
882 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
883 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
884 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
885 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
886 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
887 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
888 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
889 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
890 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
891 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
892 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
893 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
894 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
895 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
896 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
897 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
898 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
899 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
900 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
901 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
902 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
903 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
904 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
905 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
906 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
907 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
908 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
909 SSMFIELD_ENTRY_TERM()
910};
911
912
913
914/*********************************************************************************************************************************
915* Initialization, Reset & Termination *
916*********************************************************************************************************************************/
917
918/**
919 * Initialize the SVM hardware virtualization state.
920 *
921 * @param pVM The cross context VM structure.
922 */
923static void cpumR3InitSvmHwVirtState(PVM pVM)
924{
925 LogRel(("CPUM: AMD-V nested-guest init\n"));
926 for (VMCPUID i = 0; i < pVM->cCpus; i++)
927 {
928 PVMCPU pVCpu = pVM->apCpusR3[i];
929 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
930
931 /* Initialize that SVM hardware virtualization is available. */
932 pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
933
934 AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
935 AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
936 AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
937
938 /* Initialize non-zero values. */
939 pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
940 }
941}
942
943
944/**
945 * Resets per-VCPU SVM hardware virtualization state.
946 *
947 * @param pVCpu The cross context virtual CPU structure.
948 */
949DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
950{
951 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
952 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
953
954 RT_ZERO(pCtx->hwvirt.svm.Vmcb);
955 RT_ZERO(pCtx->hwvirt.svm.HostState);
956 RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
957 RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
958
959 pCtx->hwvirt.svm.uMsrHSavePa = 0;
960 pCtx->hwvirt.svm.uPrevPauseTick = 0;
961 pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
962 pCtx->hwvirt.svm.cPauseFilter = 0;
963 pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
964 pCtx->hwvirt.svm.fInterceptEvents = false;
965}
966
967
968/**
969 * Initializes the VMX hardware virtualization state.
970 *
971 * @param pVM The cross context VM structure.
972 */
973static void cpumR3InitVmxHwVirtState(PVM pVM)
974{
975 LogRel(("CPUM: VT-x nested-guest init\n"));
976 for (VMCPUID i = 0; i < pVM->cCpus; i++)
977 {
978 PVMCPU pVCpu = pVM->apCpusR3[i];
979 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
980
981 /* Initialize that VMX hardware virtualization is available. */
982 pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
983
984 AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
985 AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
986 AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
987 AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
988 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
989 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
990 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
991 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
992 AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
993 AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
994 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
995 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
996 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
997 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
998 AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
999 AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1000 AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1001 AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1002
1003 /* Initialize non-zero values. */
1004 pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1005 pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1006 pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1007 }
1008}
1009
1010
1011/**
1012 * Resets per-VCPU VMX hardware virtualization state.
1013 *
1014 * @param pVCpu The cross context virtual CPU structure.
1015 */
1016DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1017{
1018 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1019 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1020
1021 RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1022 RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1023 RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1024 RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1025 RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1026 RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1027 RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1028 RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1029 RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1030
1031 pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1032 pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1033 pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1034 pCtx->hwvirt.vmx.fInVmxRootMode = false;
1035 pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1036 /* Don't reset diagnostics here. */
1037
1038 pCtx->hwvirt.vmx.fInterceptEvents = false;
1039 pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1040 pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1041 pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1042 pCtx->hwvirt.vmx.uEntryTick = 0;
1043 pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1044 pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1045
1046 /* Stop any VMX-preemption timer. */
1047 CPUMStopGuestVmxPremptTimer(pVCpu);
1048
1049 /* Clear all nested-guest FFs. */
1050 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1051}
1052
1053
1054/**
1055 * Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1056 * or NEM) is allowed.
1057 *
1058 * @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1059 * otherwise.
1060 * @param pVM The cross context VM structure.
1061 */
1062static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1063{
1064 AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1065#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1066 if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1067 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1068 return true;
1069#else
1070 NOREF(pVM);
1071#endif
1072 return false;
1073}
1074
1075
1076/**
1077 * Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1078 *
1079 * @param pVM The cross context VM structure.
1080 * @param pHostMsrs The host VMX MSRs. Pass NULL when fully emulating
1081 * VMX and no hardware-assisted nested-guest execution
1082 * is possible for this VM.
1083 * @param pGuestFeatures The guest features to use (only VMX features are
1084 * accessed).
1085 * @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1086 *
1087 * @remarks This function ASSUMES the VMX guest-features are already exploded!
1088 */
1089static void cpumR3InitVmxGuestMsrs(PVM pVM, PCSUPHWVIRTMSRS pHostMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1090{
1091/** @todo This needs to be rechecked for pHostMsrs == NULL on arm64 hosts. */
1092 bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1093
1094 Assert(!fIsNstGstHwExecAllowed || pHostMsrs);
1095 Assert(pGuestFeatures->fVmx);
1096
1097 /* Basic information. */
1098 uint8_t const fTrueVmxMsrs = 1;
1099 {
1100 uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1101 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1102 | RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1103 | RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1104 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1105 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1106 | RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1107 pGuestVmxMsrs->u64Basic = u64Basic;
1108 }
1109
1110 /* Pin-based VM-execution controls. */
1111 {
1112 uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1113 | (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1114 | (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1115 | (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1116 | (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1117 uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1118 uint32_t const fAllowed1 = fFeatures | VMX_PIN_CTLS_DEFAULT1;
1119 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1120 fAllowed0, fAllowed1, fFeatures));
1121 pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1122
1123 /* True pin-based VM-execution controls. */
1124 if (fTrueVmxMsrs)
1125 {
1126 /* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1127 pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1128 }
1129 }
1130
1131 /* Processor-based VM-execution controls. */
1132 {
1133 uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1134 | (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1135 | (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1136 | (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1137 | (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1138 | (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1139 | (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1140 | (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1141 | (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1142 | (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1143 | (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1144 | (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1145 | (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1146 | (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1147 | (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1148 | (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1149 | (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1150 | (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1151 | (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1152 | (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1153 | (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1154 | (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1155 uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1156 uint32_t const fAllowed1 = fFeatures | VMX_PROC_CTLS_DEFAULT1;
1157 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1158 fAllowed1, fFeatures));
1159 pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1160
1161 /* True processor-based VM-execution controls. */
1162 if (fTrueVmxMsrs)
1163 {
1164 /* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1165 uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1166 | VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1167 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1168 pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1169 }
1170 }
1171
1172 /* Secondary processor-based VM-execution controls. */
1173 if (pGuestFeatures->fVmxSecondaryExecCtls)
1174 {
1175 uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1176 | (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1177 | (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1178 | (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1179 | (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1180 | (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1181 | (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1182 | (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1183 | (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1184 | (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1185 | (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1186 | (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1187 | (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1188 | (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1189 | (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1190 | (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1191 | (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1192 | (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1193 | (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1194 | (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1195 | (pGuestFeatures->fVmxPasidTranslate << VMX_BF_PROC_CTLS2_PASID_TRANSLATE_SHIFT )
1196 | (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1197 | (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1198 | (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1199 | (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1200 | (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1201 | (pGuestFeatures->fVmxPconfig << VMX_BF_PROC_CTLS2_PCONFIG_SHIFT )
1202 | (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT )
1203 | (pGuestFeatures->fVmxBusLockDetect << VMX_BF_PROC_CTLS2_BUSLOCK_DETECT_SHIFT )
1204 | (pGuestFeatures->fVmxInstrTimeout << VMX_BF_PROC_CTLS2_INSTR_TIMEOUT_SHIFT );
1205 uint32_t const fAllowed0 = 0;
1206 uint32_t const fAllowed1 = fFeatures;
1207 pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1208 }
1209
1210 /* Tertiary processor-based VM-execution controls. */
1211 if (pGuestFeatures->fVmxTertiaryExecCtls)
1212 {
1213 pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT)
1214 | (pGuestFeatures->fVmxHlat << VMX_BF_PROC_CTLS3_HLAT_SHIFT)
1215 | (pGuestFeatures->fVmxEptPagingWrite << VMX_BF_PROC_CTLS3_EPT_PAGING_WRITE_SHIFT)
1216 | (pGuestFeatures->fVmxGstPagingVerify << VMX_BF_PROC_CTLS3_GST_PAGING_VERIFY_SHIFT)
1217 | (pGuestFeatures->fVmxIpiVirt << VMX_BF_PROC_CTLS3_IPI_VIRT_SHIFT)
1218 | (pGuestFeatures->fVmxVirtSpecCtrl << VMX_BF_PROC_CTLS3_VIRT_SPEC_CTRL_SHIFT);
1219 }
1220
1221 /* VM-exit controls. */
1222 {
1223 uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1224 | (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1225 | (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1226 | (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1227 | (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1228 | (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1229 | (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1230 | (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT )
1231 | (pGuestFeatures->fVmxSecondaryExitCtls << VMX_BF_EXIT_CTLS_USE_SECONDARY_CTLS_SHIFT );
1232 /* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1233 uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1234 uint32_t const fAllowed1 = fFeatures | VMX_EXIT_CTLS_DEFAULT1;
1235 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1236 fAllowed1, fFeatures));
1237 pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1238
1239 /* True VM-exit controls. */
1240 if (fTrueVmxMsrs)
1241 {
1242 /* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1243 uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1244 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1245 pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1246 }
1247 }
1248
1249 /* VM-entry controls. */
1250 {
1251 uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1252 | (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1253 | (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1254 | (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1255 uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1256 uint32_t const fAllowed1 = fFeatures | VMX_ENTRY_CTLS_DEFAULT1;
1257 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1258 fAllowed1, fFeatures));
1259 pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1260
1261 /* True VM-entry controls. */
1262 if (fTrueVmxMsrs)
1263 {
1264 /* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1265 uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1266 | VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1267 | VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1268 | VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1269 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1270 pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1271 }
1272 }
1273
1274 /* Miscellaneous data. */
1275 {
1276 uint64_t const uHostMsr = fIsNstGstHwExecAllowed && pHostMsrs ? pHostMsrs->u.vmx.u64Misc : 0;
1277
1278 uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1279 uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1280 pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1281 | RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1282 | RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1283 | RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1284 | RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1285 | RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1286 | RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1287 | RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1288 | RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1289 | RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1290 | RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1291 }
1292
1293 /* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1294 pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1295
1296 /* CR0 Fixed-1. */
1297 {
1298 /*
1299 * All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1300 * This is different from CR4 fixed-1 bits which are reported as per the
1301 * CPU features and/or micro-architecture/generation. Why? Ask Intel.
1302 */
1303 pGuestVmxMsrs->u64Cr0Fixed1 = fIsNstGstHwExecAllowed && pHostMsrs ? pHostMsrs->u.vmx.u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1304
1305 /* Make sure the CR0 MB1 bits are not clear. */
1306 Assert((pGuestVmxMsrs->u64Cr0Fixed1 & pGuestVmxMsrs->u64Cr0Fixed0) == pGuestVmxMsrs->u64Cr0Fixed0);
1307 }
1308
1309 /* CR4 Fixed-0. */
1310 pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1311
1312 /* CR4 Fixed-1. */
1313 {
1314 pGuestVmxMsrs->u64Cr4Fixed1 = CPUMGetGuestCR4ValidMask(pVM) & (pHostMsrs ? pHostMsrs->u.vmx.u64Cr4Fixed1 : 0);
1315
1316 /* Make sure the CR4 MB1 bits are not clear. */
1317 Assert((pGuestVmxMsrs->u64Cr4Fixed1 & pGuestVmxMsrs->u64Cr4Fixed0) == pGuestVmxMsrs->u64Cr4Fixed0);
1318
1319 /* Make sure bits that must always be set are set. */
1320 Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_PAE);
1321 Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_VMXE);
1322 }
1323
1324 /* VMCS Enumeration. */
1325 pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1326
1327 /* VPID and EPT Capabilities. */
1328 if (pGuestFeatures->fVmxEpt)
1329 {
1330 /*
1331 * INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1332 * and emulate any INVVPID flush type. However, it only makes sense to expose the types
1333 * when INVVPID instruction is supported just to be more compatible with guest
1334 * hypervisors that may make assumptions by only looking at this MSR even though they
1335 * are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1336 *
1337 * See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1338 * See Intel spec. 30.3 "VMX Instructions".
1339 */
1340 uint64_t const uHostMsr = fIsNstGstHwExecAllowed && pHostMsrs ? pHostMsrs->u.vmx.u64EptVpidCaps : UINT64_MAX;
1341 uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1342
1343 uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1344 uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1345 uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1346 uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1347 uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1348 uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1349 /** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1350 /* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1351 uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1352 uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1353 uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1354 uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1355 uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1356 uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1357 pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1358 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1359 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1360 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1361 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1362 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, 0)
1363 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1364 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1365 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1366 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1367 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1368 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1369 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1370 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1371 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1372 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1373 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1374 }
1375
1376 /* VM Functions. */
1377 if (pGuestFeatures->fVmxVmFunc)
1378 pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1379}
1380
1381
1382/**
1383 * Checks whether the given guest CPU VMX features are compatible with the provided
1384 * base features.
1385 *
1386 * @returns @c true if compatible, @c false otherwise.
1387 * @param pVM The cross context VM structure.
1388 * @param pBase The base VMX CPU features.
1389 * @param pGst The guest VMX CPU features.
1390 *
1391 * @remarks Only VMX feature bits are examined.
1392 */
1393static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1394{
1395 if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1396 return false;
1397
1398#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1399#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1400 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1401 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1402 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1403 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1404 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1405 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1406 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1407 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1408 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1409 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1410 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1411 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1412 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1413 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1414 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1415 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1416 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1417 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1418 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1419 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1420 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1421 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1422 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1423 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1424 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1425 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1426 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1427 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1428 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1429 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1430 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1431 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1432 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1433 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1434 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1435 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1436 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1437 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1438 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1439 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1440 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1441 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1442 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1443 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1444 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1445 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1446 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1447 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPasidTranslate , 49) \
1448 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 50) \
1449 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 51) \
1450 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 52) \
1451 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 53) \
1452 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 54) \
1453 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPconfig , 55) \
1454 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 56) \
1455 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxBusLockDetect , 57) \
1456 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInstrTimeout , 58) \
1457 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 59) \
1458 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHlat , 60) \
1459 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptPagingWrite , 61) \
1460 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxGstPagingVerify , 62) \
1461 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIpiVirt , 63))
1462
1463#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtSpecCtrl , 0) \
1464 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 1) \
1465 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 2) \
1466 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 3) \
1467 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 4) \
1468 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 5) \
1469 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 6) \
1470 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 7) \
1471 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 8) \
1472 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 9) \
1473 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 10) \
1474 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 12) \
1475 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 13) \
1476 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExitCtls , 14) \
1477 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 15) \
1478 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 16) \
1479 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 17) \
1480 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 18))
1481
1482 /* Check first set of feature bits. */
1483 {
1484 uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1485 uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1486 if ((fBase | fGst) != fBase)
1487 {
1488 uint64_t const fDiff = fBase ^ fGst;
1489 LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1490 fBase, fGst, fDiff));
1491 return false;
1492 }
1493 }
1494
1495 /* Check second set of feature bits. */
1496 {
1497 uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1498 uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1499 if ((fBase | fGst) != fBase)
1500 {
1501 uint64_t const fDiff = fBase ^ fGst;
1502 LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1503 fBase, fGst, fDiff));
1504 return false;
1505 }
1506 }
1507#undef CPUM_VMX_FEAT_SHIFT
1508#undef CPUM_VMX_MAKE_FEATURES_1
1509#undef CPUM_VMX_MAKE_FEATURES_2
1510
1511 return true;
1512}
1513
1514
1515/**
1516 * Initializes VMX guest features and MSRs.
1517 *
1518 * @param pVM The cross context VM structure.
1519 * @param pCpumCfg The CPUM CFGM configuration node.
1520 * @param pHostMsrs The host VMX MSRs. Pass NULL when fully emulating
1521 * VMX and no hardware-assisted nested-guest execution
1522 * is possible for this VM.
1523 * @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1524 */
1525DECLHIDDEN(void) cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCSUPHWVIRTMSRS pHostMsrs, PVMXMSRS pGuestVmxMsrs)
1526{
1527 Assert(pVM);
1528 Assert(pCpumCfg);
1529 Assert(pGuestVmxMsrs);
1530
1531 /*
1532 * Query VMX features from CFGM.
1533 */
1534 bool fVmxPreemptTimer;
1535 bool fVmxEpt;
1536 bool fVmxUnrestrictedGuest;
1537 {
1538 /** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
1539 * Whether to expose the VMX-preemption timer feature to the guest (if also
1540 * supported by the host hardware). When disabled will prevent exposing the
1541 * VMX-preemption timer feature to the guest even if the host supports it.
1542 *
1543 * @todo Currently disabled, see @bugref{9180#c108}.
1544 */
1545 int rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &fVmxPreemptTimer, false);
1546 AssertLogRelRCReturnVoid(rc);
1547
1548#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1549 /** @cfgm{/CPUM/NestedVmxEpt, bool, true}
1550 * Whether to expose the EPT feature to the guest. The default is true.
1551 * When disabled will automatically prevent exposing features that rely
1552 * on it. This is dependent upon nested paging being enabled for the VM.
1553 */
1554 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &fVmxEpt, true);
1555 AssertLogRelRCReturnVoid(rc);
1556
1557 /** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
1558 * Whether to expose the Unrestricted Guest feature to the guest. The
1559 * default is the same a /CPUM/Nested/VmxEpt. When disabled will
1560 * automatically prevent exposing features that rely on it.
1561 */
1562 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &fVmxUnrestrictedGuest, fVmxEpt);
1563 AssertLogRelRCReturnVoid(rc);
1564#else
1565 fVmxEpt = fVmxUnrestrictedGuest = false;
1566#endif
1567 }
1568
1569 if (fVmxEpt)
1570 {
1571 const char *pszWhy = NULL;
1572 if (!VM_IS_HM_ENABLED(pVM) && !VM_IS_EXEC_ENGINE_IEM(pVM))
1573 pszWhy = "execution engine is neither HM nor IEM";
1574#ifdef RT_ARCH_AMD64
1575 else if (VM_IS_HM_ENABLED(pVM) && !HMIsNestedPagingActive(pVM))
1576 pszWhy = "nested paging is not enabled for the VM or it is not supported by the host";
1577 else if (VM_IS_HM_ENABLED(pVM) && !pVM->cpum.s.HostFeatures.s.fNoExecute)
1578 pszWhy = "NX is not available on the host";
1579#endif
1580 if (pszWhy)
1581 {
1582 LogRel(("CPUM: Warning! EPT not exposed to the guest because %s\n", pszWhy));
1583 fVmxEpt = false;
1584 }
1585 }
1586 else if (fVmxUnrestrictedGuest)
1587 {
1588 LogRel(("CPUM: Warning! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
1589 fVmxUnrestrictedGuest = false;
1590 }
1591
1592 /*
1593 * Initialize the set of VMX features we emulate.
1594 *
1595 * Note! Some bits might be reported as 1 always if they fall under the
1596 * default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1597 */
1598 CPUMFEATURES EmuFeat;
1599 RT_ZERO(EmuFeat);
1600 EmuFeat.fVmx = 1;
1601 EmuFeat.fVmxInsOutInfo = 1;
1602 EmuFeat.fVmxExtIntExit = 1;
1603 EmuFeat.fVmxNmiExit = 1;
1604 EmuFeat.fVmxVirtNmi = 1;
1605 EmuFeat.fVmxPreemptTimer = fVmxPreemptTimer;
1606 EmuFeat.fVmxPostedInt = 0;
1607 EmuFeat.fVmxIntWindowExit = 1;
1608 EmuFeat.fVmxTscOffsetting = 1;
1609 EmuFeat.fVmxHltExit = 1;
1610 EmuFeat.fVmxInvlpgExit = 1;
1611 EmuFeat.fVmxMwaitExit = 1;
1612 EmuFeat.fVmxRdpmcExit = 1;
1613 EmuFeat.fVmxRdtscExit = 1;
1614 EmuFeat.fVmxCr3LoadExit = 1;
1615 EmuFeat.fVmxCr3StoreExit = 1;
1616 EmuFeat.fVmxTertiaryExecCtls = 0;
1617 EmuFeat.fVmxCr8LoadExit = 1;
1618 EmuFeat.fVmxCr8StoreExit = 1;
1619 EmuFeat.fVmxUseTprShadow = 1;
1620 EmuFeat.fVmxNmiWindowExit = 1;
1621 EmuFeat.fVmxMovDRxExit = 1;
1622 EmuFeat.fVmxUncondIoExit = 1;
1623 EmuFeat.fVmxUseIoBitmaps = 1;
1624 EmuFeat.fVmxMonitorTrapFlag = 0;
1625 EmuFeat.fVmxUseMsrBitmaps = 1;
1626 EmuFeat.fVmxMonitorExit = 1;
1627 EmuFeat.fVmxPauseExit = 1;
1628 EmuFeat.fVmxSecondaryExecCtls = 1;
1629 EmuFeat.fVmxVirtApicAccess = 1;
1630 EmuFeat.fVmxEpt = fVmxEpt;
1631 EmuFeat.fVmxDescTableExit = 1;
1632 EmuFeat.fVmxRdtscp = 1;
1633 EmuFeat.fVmxVirtX2ApicMode = 0;
1634 EmuFeat.fVmxVpid = 1;
1635 EmuFeat.fVmxWbinvdExit = 1;
1636 EmuFeat.fVmxUnrestrictedGuest = fVmxUnrestrictedGuest;
1637 EmuFeat.fVmxApicRegVirt = 0;
1638 EmuFeat.fVmxVirtIntDelivery = 0;
1639 EmuFeat.fVmxPauseLoopExit = 1;
1640 EmuFeat.fVmxRdrandExit = 1;
1641 EmuFeat.fVmxInvpcid = 1;
1642 EmuFeat.fVmxVmFunc = 0;
1643 EmuFeat.fVmxVmcsShadowing = 0;
1644 EmuFeat.fVmxRdseedExit = 1;
1645 EmuFeat.fVmxPml = 0;
1646 EmuFeat.fVmxEptXcptVe = 0;
1647 EmuFeat.fVmxConcealVmxFromPt = 0;
1648 EmuFeat.fVmxXsavesXrstors = 0;
1649 EmuFeat.fVmxPasidTranslate = 0;
1650 EmuFeat.fVmxModeBasedExecuteEpt = 0;
1651 EmuFeat.fVmxSppEpt = 0;
1652 EmuFeat.fVmxPtEpt = 0;
1653 EmuFeat.fVmxUseTscScaling = 0;
1654 EmuFeat.fVmxUserWaitPause = 0;
1655 EmuFeat.fVmxPconfig = 0;
1656 EmuFeat.fVmxEnclvExit = 0;
1657 EmuFeat.fVmxBusLockDetect = 0;
1658 EmuFeat.fVmxInstrTimeout = 0;
1659 EmuFeat.fVmxLoadIwKeyExit = 0;
1660 EmuFeat.fVmxHlat = 0;
1661 EmuFeat.fVmxEptPagingWrite = 0;
1662 EmuFeat.fVmxGstPagingVerify = 0;
1663 EmuFeat.fVmxIpiVirt = 0;
1664 EmuFeat.fVmxVirtSpecCtrl = 0;
1665 EmuFeat.fVmxEntryLoadDebugCtls = 1;
1666 EmuFeat.fVmxIa32eModeGuest = 1;
1667 EmuFeat.fVmxEntryLoadEferMsr = 1;
1668 EmuFeat.fVmxEntryLoadPatMsr = 1;
1669 EmuFeat.fVmxExitSaveDebugCtls = 1;
1670 EmuFeat.fVmxHostAddrSpaceSize = 1;
1671 EmuFeat.fVmxExitAckExtInt = 1;
1672 EmuFeat.fVmxExitSavePatMsr = 1;
1673 EmuFeat.fVmxExitLoadPatMsr = 1;
1674 EmuFeat.fVmxExitSaveEferMsr = 1;
1675 EmuFeat.fVmxExitLoadEferMsr = 1;
1676 EmuFeat.fVmxSavePreemptTimer = 0 & fVmxPreemptTimer; /* Cannot be enabled if VMX-preemption timer is disabled. */
1677 EmuFeat.fVmxSecondaryExitCtls = 0;
1678 EmuFeat.fVmxExitSaveEferLma = 1 | fVmxUnrestrictedGuest; /* Cannot be disabled if unrestricted guest is enabled. */
1679 EmuFeat.fVmxPt = 0;
1680 EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1681 EmuFeat.fVmxEntryInjectSoftInt = 1;
1682
1683 /*
1684 * Merge guest features.
1685 *
1686 * When hardware-assisted VMX may be used, any feature we emulate must also be supported
1687 * by the hardware, hence we merge our emulated features with the host features below.
1688 */
1689#ifdef RT_ARCH_AMD64
1690 PCCPUMFEATURES const pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures.s : &EmuFeat;
1691#else
1692 PCCPUMFEATURES const pBaseFeat = &EmuFeat;
1693#endif
1694 PCPUMFEATURES const pGuestFeat = &pVM->cpum.s.GuestFeatures;
1695 Assert(pBaseFeat->fVmx);
1696#define CPUMVMX_SET_GST_FEAT(a_Feat) \
1697 do { \
1698 pGuestFeat->a_Feat = (pBaseFeat->a_Feat & EmuFeat.a_Feat); \
1699 } while (0)
1700
1701 CPUMVMX_SET_GST_FEAT(fVmxInsOutInfo);
1702 CPUMVMX_SET_GST_FEAT(fVmxExtIntExit);
1703 CPUMVMX_SET_GST_FEAT(fVmxNmiExit);
1704 CPUMVMX_SET_GST_FEAT(fVmxVirtNmi);
1705 CPUMVMX_SET_GST_FEAT(fVmxPreemptTimer);
1706 CPUMVMX_SET_GST_FEAT(fVmxPostedInt);
1707 CPUMVMX_SET_GST_FEAT(fVmxIntWindowExit);
1708 CPUMVMX_SET_GST_FEAT(fVmxTscOffsetting);
1709 CPUMVMX_SET_GST_FEAT(fVmxHltExit);
1710 CPUMVMX_SET_GST_FEAT(fVmxInvlpgExit);
1711 CPUMVMX_SET_GST_FEAT(fVmxMwaitExit);
1712 CPUMVMX_SET_GST_FEAT(fVmxRdpmcExit);
1713 CPUMVMX_SET_GST_FEAT(fVmxRdtscExit);
1714 CPUMVMX_SET_GST_FEAT(fVmxCr3LoadExit);
1715 CPUMVMX_SET_GST_FEAT(fVmxCr3StoreExit);
1716 CPUMVMX_SET_GST_FEAT(fVmxTertiaryExecCtls);
1717 CPUMVMX_SET_GST_FEAT(fVmxCr8LoadExit);
1718 CPUMVMX_SET_GST_FEAT(fVmxCr8StoreExit);
1719 CPUMVMX_SET_GST_FEAT(fVmxUseTprShadow);
1720 CPUMVMX_SET_GST_FEAT(fVmxNmiWindowExit);
1721 CPUMVMX_SET_GST_FEAT(fVmxMovDRxExit);
1722 CPUMVMX_SET_GST_FEAT(fVmxUncondIoExit);
1723 CPUMVMX_SET_GST_FEAT(fVmxUseIoBitmaps);
1724 CPUMVMX_SET_GST_FEAT(fVmxMonitorTrapFlag);
1725 CPUMVMX_SET_GST_FEAT(fVmxUseMsrBitmaps);
1726 CPUMVMX_SET_GST_FEAT(fVmxMonitorExit);
1727 CPUMVMX_SET_GST_FEAT(fVmxPauseExit);
1728 CPUMVMX_SET_GST_FEAT(fVmxSecondaryExecCtls);
1729 CPUMVMX_SET_GST_FEAT(fVmxVirtApicAccess);
1730 CPUMVMX_SET_GST_FEAT(fVmxEpt);
1731 CPUMVMX_SET_GST_FEAT(fVmxDescTableExit);
1732 CPUMVMX_SET_GST_FEAT(fVmxRdtscp);
1733 CPUMVMX_SET_GST_FEAT(fVmxVirtX2ApicMode);
1734 CPUMVMX_SET_GST_FEAT(fVmxVpid);
1735 CPUMVMX_SET_GST_FEAT(fVmxWbinvdExit);
1736 CPUMVMX_SET_GST_FEAT(fVmxUnrestrictedGuest);
1737 CPUMVMX_SET_GST_FEAT(fVmxApicRegVirt);
1738 CPUMVMX_SET_GST_FEAT(fVmxVirtIntDelivery);
1739 CPUMVMX_SET_GST_FEAT(fVmxPauseLoopExit);
1740 CPUMVMX_SET_GST_FEAT(fVmxRdrandExit);
1741 CPUMVMX_SET_GST_FEAT(fVmxInvpcid);
1742 CPUMVMX_SET_GST_FEAT(fVmxVmFunc);
1743 CPUMVMX_SET_GST_FEAT(fVmxVmcsShadowing);
1744 CPUMVMX_SET_GST_FEAT(fVmxRdseedExit);
1745 CPUMVMX_SET_GST_FEAT(fVmxPml);
1746 CPUMVMX_SET_GST_FEAT(fVmxEptXcptVe);
1747 CPUMVMX_SET_GST_FEAT(fVmxConcealVmxFromPt);
1748 CPUMVMX_SET_GST_FEAT(fVmxXsavesXrstors);
1749 CPUMVMX_SET_GST_FEAT(fVmxPasidTranslate);
1750 CPUMVMX_SET_GST_FEAT(fVmxModeBasedExecuteEpt);
1751 CPUMVMX_SET_GST_FEAT(fVmxSppEpt);
1752 CPUMVMX_SET_GST_FEAT(fVmxPtEpt);
1753 CPUMVMX_SET_GST_FEAT(fVmxUseTscScaling);
1754 CPUMVMX_SET_GST_FEAT(fVmxUserWaitPause);
1755 CPUMVMX_SET_GST_FEAT(fVmxPconfig);
1756 CPUMVMX_SET_GST_FEAT(fVmxEnclvExit);
1757 CPUMVMX_SET_GST_FEAT(fVmxBusLockDetect);
1758 CPUMVMX_SET_GST_FEAT(fVmxInstrTimeout);
1759 CPUMVMX_SET_GST_FEAT(fVmxLoadIwKeyExit);
1760 CPUMVMX_SET_GST_FEAT(fVmxHlat);
1761 CPUMVMX_SET_GST_FEAT(fVmxEptPagingWrite);
1762 CPUMVMX_SET_GST_FEAT(fVmxGstPagingVerify);
1763 CPUMVMX_SET_GST_FEAT(fVmxIpiVirt);
1764 CPUMVMX_SET_GST_FEAT(fVmxVirtSpecCtrl);
1765 CPUMVMX_SET_GST_FEAT(fVmxEntryLoadDebugCtls);
1766 CPUMVMX_SET_GST_FEAT(fVmxIa32eModeGuest);
1767 CPUMVMX_SET_GST_FEAT(fVmxEntryLoadEferMsr);
1768 CPUMVMX_SET_GST_FEAT(fVmxEntryLoadPatMsr);
1769 CPUMVMX_SET_GST_FEAT(fVmxExitSaveDebugCtls);
1770 CPUMVMX_SET_GST_FEAT(fVmxHostAddrSpaceSize);
1771 CPUMVMX_SET_GST_FEAT(fVmxExitAckExtInt);
1772 CPUMVMX_SET_GST_FEAT(fVmxExitSavePatMsr);
1773 CPUMVMX_SET_GST_FEAT(fVmxExitLoadPatMsr);
1774 CPUMVMX_SET_GST_FEAT(fVmxExitSaveEferMsr);
1775 CPUMVMX_SET_GST_FEAT(fVmxExitLoadEferMsr);
1776 CPUMVMX_SET_GST_FEAT(fVmxSavePreemptTimer);
1777 CPUMVMX_SET_GST_FEAT(fVmxSecondaryExitCtls);
1778 CPUMVMX_SET_GST_FEAT(fVmxExitSaveEferLma);
1779 CPUMVMX_SET_GST_FEAT(fVmxPt);
1780 CPUMVMX_SET_GST_FEAT(fVmxVmwriteAll);
1781 CPUMVMX_SET_GST_FEAT(fVmxEntryInjectSoftInt);
1782
1783#undef CPUMVMX_SET_GST_FEAT
1784
1785#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
1786 /* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1787 if ( pGuestFeat->fVmxPreemptTimer
1788 && HMIsSubjectToVmxPreemptTimerErratum())
1789 {
1790 LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum\n"));
1791 pGuestFeat->fVmxPreemptTimer = 0;
1792 pGuestFeat->fVmxSavePreemptTimer = 0;
1793 }
1794#endif
1795
1796 /* Sanity checking. */
1797 if (!pGuestFeat->fVmxSecondaryExecCtls)
1798 {
1799 Assert(!pGuestFeat->fVmxVirtApicAccess);
1800 Assert(!pGuestFeat->fVmxEpt);
1801 Assert(!pGuestFeat->fVmxDescTableExit);
1802 Assert(!pGuestFeat->fVmxRdtscp);
1803 Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1804 Assert(!pGuestFeat->fVmxVpid);
1805 Assert(!pGuestFeat->fVmxWbinvdExit);
1806 Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1807 Assert(!pGuestFeat->fVmxApicRegVirt);
1808 Assert(!pGuestFeat->fVmxVirtIntDelivery);
1809 Assert(!pGuestFeat->fVmxPauseLoopExit);
1810 Assert(!pGuestFeat->fVmxRdrandExit);
1811 Assert(!pGuestFeat->fVmxInvpcid);
1812 Assert(!pGuestFeat->fVmxVmFunc);
1813 Assert(!pGuestFeat->fVmxVmcsShadowing);
1814 Assert(!pGuestFeat->fVmxRdseedExit);
1815 Assert(!pGuestFeat->fVmxPml);
1816 Assert(!pGuestFeat->fVmxEptXcptVe);
1817 Assert(!pGuestFeat->fVmxConcealVmxFromPt);
1818 Assert(!pGuestFeat->fVmxXsavesXrstors);
1819 Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
1820 Assert(!pGuestFeat->fVmxSppEpt);
1821 Assert(!pGuestFeat->fVmxPtEpt);
1822 Assert(!pGuestFeat->fVmxUseTscScaling);
1823 Assert(!pGuestFeat->fVmxUserWaitPause);
1824 Assert(!pGuestFeat->fVmxEnclvExit);
1825 }
1826 else if (pGuestFeat->fVmxUnrestrictedGuest)
1827 {
1828 /* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1829 Assert(pGuestFeat->fVmxExitSaveEferLma);
1830 /* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
1831 Assert(pGuestFeat->fVmxEpt);
1832 }
1833
1834 if (!pGuestFeat->fVmxTertiaryExecCtls)
1835 {
1836 Assert(!pGuestFeat->fVmxLoadIwKeyExit);
1837 Assert(!pGuestFeat->fVmxHlat);
1838 Assert(!pGuestFeat->fVmxEptPagingWrite);
1839 Assert(!pGuestFeat->fVmxGstPagingVerify);
1840 Assert(!pGuestFeat->fVmxIpiVirt);
1841 Assert(!pGuestFeat->fVmxVirtSpecCtrl);
1842 }
1843
1844 /*
1845 * Finally initialize the VMX guest MSRs.
1846 */
1847 cpumR3InitVmxGuestMsrs(pVM, pHostMsrs, pGuestFeat, pGuestVmxMsrs);
1848}
1849
1850
1851/**
1852 * @callback_method_impl{FNTMTIMERINT,
1853 * Callback that fires when the nested VMX-preemption timer expired.}
1854 */
1855static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
1856{
1857 RT_NOREF(pVM, hTimer);
1858 PVMCPU pVCpu = (PVMCPUR3)pvUser;
1859 AssertPtr(pVCpu);
1860 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
1861}
1862
1863
1864/**
1865 * X86 target specific initialization.
1866 *
1867 * @returns VBox status code.
1868 * @param pVM The cross context VM structure.
1869 * @param pHostMsrs Pointer to the host MSRs. NULL if not on an x86 host or
1870 * no support driver is being used.
1871 */
1872DECLHIDDEN(int) cpumR3InitTargetX86(PVM pVM, PCSUPHWVIRTMSRS pHostMsrs)
1873{
1874 LogFlow(("cpumR3InitTargetX86\n"));
1875
1876 /*
1877 * Register X86 specific info items.
1878 */
1879 DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1880 &cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1881 DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1882 &cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1883 DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
1884 &cpumR3InfoVmxFeatures);
1885
1886 /*
1887 * Initialize the Guest CPUID and MSR states.
1888 */
1889 int rc = cpumR3InitCpuIdAndMsrs(pVM, pHostMsrs);
1890 if (RT_FAILURE(rc))
1891 return rc;
1892
1893 /*
1894 * Generate the RFLAGS cookie.
1895 */
1896 pVM->cpum.s.fReservedRFlagsCookie = RTRandU64() & ~(CPUMX86EFLAGS_HW_MASK_64 | CPUMX86EFLAGS_INT_MASK_64);
1897
1898 /*
1899 * Init the VMX/SVM state.
1900 *
1901 * This must be done after initializing CPUID/MSR features as we access the
1902 * the VMX/SVM guest features below.
1903 *
1904 * In the case of nested VT-x, we also need to create the per-VCPU
1905 * VMX preemption timers.
1906 */
1907 if (pVM->cpum.s.GuestFeatures.fVmx)
1908 cpumR3InitVmxHwVirtState(pVM);
1909 else if (pVM->cpum.s.GuestFeatures.fSvm)
1910 cpumR3InitSvmHwVirtState(pVM);
1911 else
1912 Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
1913
1914 return VINF_SUCCESS;
1915}
1916
1917
1918DECLHIDDEN(int) cpumR3InitCompletedRing3Target(PVM pVM)
1919{
1920 /*
1921 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
1922 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
1923 */
1924 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1925 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1926 {
1927 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1928
1929 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
1930 if (fSupportsLongMode)
1931 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1932 }
1933
1934 /* Register statistic counters for MSRs. */
1935 cpumR3MsrRegStats(pVM);
1936
1937 /* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
1938 CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
1939 cpumR3CpuIdRing3InitDone(pVM);
1940
1941 /* Create VMX-preemption timer for nested guests if required. Must be
1942 done here as CPUM is initialized before TM. */
1943 if (pVM->cpum.s.GuestFeatures.fVmx)
1944 {
1945 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1946 {
1947 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1948 char szName[32];
1949 RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
1950 int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
1951 TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
1952 AssertLogRelRCReturn(rc, rc);
1953 }
1954 }
1955
1956 /*
1957 * Map guest RAM via MTRRs.
1958 */
1959 if (pVM->cpum.s.fMtrrRead)
1960 {
1961 int const rc = cpumR3MapMtrrs(pVM);
1962 if (RT_SUCCESS(rc))
1963 { /* likely */ }
1964 else
1965 return rc;
1966 }
1967 return VINF_SUCCESS;
1968}
1969
1970
1971DECLHIDDEN(int) cpumR3TermTarget(PVM pVM)
1972{
1973 if (pVM->cpum.s.GuestFeatures.fVmx)
1974 {
1975 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1976 {
1977 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1978 if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
1979 {
1980 int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
1981 pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
1982 }
1983 }
1984 }
1985 return VINF_SUCCESS;
1986}
1987
1988
1989/**
1990 * Resets a virtual CPU.
1991 *
1992 * Used by CPUMR3Reset and CPU hot plugging.
1993 *
1994 * @param pVM The cross context VM structure.
1995 * @param pVCpu The cross context virtual CPU structure of the CPU that is
1996 * being reset. This may differ from the current EMT.
1997 */
1998VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1999{
2000 /** @todo anything different for VCPU > 0? */
2001 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2002
2003 /*
2004 * Initialize everything to ZERO first.
2005 */
2006 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2007
2008 RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2009
2010 pVCpu->cpum.s.fUseFlags = fUseFlags;
2011
2012 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
2013 pCtx->eip = 0x0000fff0;
2014 pCtx->edx = 0x00000600; /* P6 processor */
2015
2016 Assert((pVM->cpum.s.fReservedRFlagsCookie & (X86_EFL_LIVE_MASK | X86_EFL_RAZ_LO_MASK | X86_EFL_RA1_MASK)) == 0);
2017 pCtx->rflags.uBoth = pVM->cpum.s.fReservedRFlagsCookie | X86_EFL_RA1_MASK;
2018
2019 pCtx->cs.Sel = 0xf000;
2020 pCtx->cs.ValidSel = 0xf000;
2021 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2022 pCtx->cs.u64Base = UINT64_C(0xffff0000);
2023 pCtx->cs.u32Limit = 0x0000ffff;
2024 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2025 pCtx->cs.Attr.n.u1Present = 1;
2026 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2027
2028 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2029 pCtx->ds.u32Limit = 0x0000ffff;
2030 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2031 pCtx->ds.Attr.n.u1Present = 1;
2032 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2033
2034 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2035 pCtx->es.u32Limit = 0x0000ffff;
2036 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2037 pCtx->es.Attr.n.u1Present = 1;
2038 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2039
2040 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2041 pCtx->fs.u32Limit = 0x0000ffff;
2042 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2043 pCtx->fs.Attr.n.u1Present = 1;
2044 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2045
2046 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2047 pCtx->gs.u32Limit = 0x0000ffff;
2048 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2049 pCtx->gs.Attr.n.u1Present = 1;
2050 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2051
2052 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2053 pCtx->ss.u32Limit = 0x0000ffff;
2054 pCtx->ss.Attr.n.u1Present = 1;
2055 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2056 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2057
2058 pCtx->idtr.cbIdt = 0xffff;
2059 pCtx->gdtr.cbGdt = 0xffff;
2060
2061 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2062 pCtx->ldtr.u32Limit = 0xffff;
2063 pCtx->ldtr.Attr.n.u1Present = 1;
2064 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2065
2066 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2067 pCtx->tr.u32Limit = 0xffff;
2068 pCtx->tr.Attr.n.u1Present = 1;
2069 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2070
2071 pCtx->dr[6] = X86_DR6_INIT_VAL;
2072 pCtx->dr[7] = X86_DR7_INIT_VAL;
2073
2074 PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2075 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2076 pFpuCtx->FCW = 0x37f;
2077
2078 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2079 IA-32 Processor States Following Power-up, Reset, or INIT */
2080 pFpuCtx->MXCSR = 0x1F80;
2081 pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2082
2083 pCtx->aXcr[0] = XSAVE_C_X87;
2084#ifdef RT_ARCH_AMD64 /** @todo x86-on-ARM64: recheck this! */
2085 if (pVM->cpum.s.HostFeatures.s.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2086#endif
2087 {
2088 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2089 as we don't know what happened before. (Bother optimize later?) */
2090 pCtx->XState.Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
2091 }
2092
2093 /*
2094 * MSRs.
2095 */
2096 /* Init PAT MSR */
2097 pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2098
2099 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2100 * The Intel docs don't mention it. */
2101 Assert(!pCtx->msrEFER);
2102
2103 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2104 is supposed to be here, just trying provide useful/sensible values. */
2105 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2106 if (pRange)
2107 {
2108 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2109 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2110 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2111 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2112 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2113 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2114 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2115 }
2116
2117 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2118
2119 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2120 * called from each EMT while we're getting called by CPUMR3Reset()
2121 * iteratively on the same thread. Fix later. */
2122#if 0 /** @todo r=bird: This we will do in TM, not here. */
2123 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2124 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2125#endif
2126
2127
2128 /* C-state control. Guesses. */
2129 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
2130 /* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2131 * it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2132 * functionality. The default value must be different due to incompatible write mask.
2133 */
2134 if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2135 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2136 else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2137 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2138
2139 /*
2140 * Hardware virtualization state.
2141 */
2142 CPUMSetGuestGif(pCtx, true);
2143 Assert(!pVM->cpum.s.GuestFeatures.fVmx || !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2144 if (pVM->cpum.s.GuestFeatures.fVmx)
2145 cpumR3ResetVmxHwVirtState(pVCpu);
2146 else if (pVM->cpum.s.GuestFeatures.fSvm)
2147 cpumR3ResetSvmHwVirtState(pVCpu);
2148}
2149
2150
2151
2152/*********************************************************************************************************************************
2153* Saved State *
2154*********************************************************************************************************************************/
2155
2156DECLCALLBACK(int) cpumR3LiveExecTarget(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2157{
2158 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2159 cpumR3SaveCpuId(pVM, pSSM);
2160 return VINF_SSM_DONT_CALL_AGAIN;
2161}
2162
2163
2164DECLCALLBACK(int) cpumR3SaveExecTarget(PVM pVM, PSSMHANDLE pSSM)
2165{
2166 /*
2167 * Save.
2168 */
2169 SSMR3PutU32(pSSM, pVM->cCpus);
2170 SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2171 CPUMCTX DummyHyperCtx;
2172 RT_ZERO(DummyHyperCtx);
2173 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2174 {
2175 PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
2176 PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
2177
2178 /** @todo ditch this the next time we change the saved state. */
2179 SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2180
2181 uint64_t const fSavedRFlags = pGstCtx->rflags.uBoth;
2182 pGstCtx->rflags.uBoth &= CPUMX86EFLAGS_HW_MASK_64; /* Temporarily clear the non-hardware bits in RFLAGS while saving. */
2183 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2184 pGstCtx->rflags.uBoth = fSavedRFlags;
2185
2186 SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2187 if (pGstCtx->fXStateMask != 0)
2188 SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2189 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2190 {
2191 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2192 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2193 }
2194 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2195 {
2196 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2197 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2198 }
2199 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2200 {
2201 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2202 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2203 }
2204 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2205 {
2206 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2207 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2208 }
2209 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2210 {
2211 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2212 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2213 }
2214 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2215 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2216 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2217 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2218 if (pVM->cpum.s.GuestFeatures.fSvm)
2219 {
2220 SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2221 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2222 SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2223 SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2224 SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2225 SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2226 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2227 g_aSvmHwvirtHostState, NULL /* pvUser */);
2228 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2229 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2230 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2231 /* This is saved in the old VMCPUM_FF format. Change if more flags are added. */
2232 SSMR3PutU32(pSSM, pGstCtx->hwvirt.fSavedInhibit & CPUMCTX_INHIBIT_NMI ? CPUM_OLD_VMCPU_FF_BLOCK_NMIS : 0);
2233 SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2234 }
2235 if (pVM->cpum.s.GuestFeatures.fVmx)
2236 {
2237 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2238 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2239 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2240 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2241 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2242 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2243 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2244 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2245 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2246 0, g_aVmxHwvirtVmcs, NULL);
2247 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2248 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2249 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2250 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2251 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2252 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2253 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2254 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2255 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2256 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2257 SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2258 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2259 SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2260 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2261 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2262 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2263 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2264 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2265 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2266 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2267 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2268 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2269 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2270 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2271 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2272 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2273 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2274 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2275 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2276 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2277 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2278 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2279 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2280 }
2281 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2282 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2283 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2284 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2285 }
2286
2287 cpumR3SaveCpuId(pVM, pSSM);
2288 return VINF_SUCCESS;
2289}
2290
2291
2292DECLCALLBACK(int) cpumR3LoadExecTarget(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2293{
2294 int rc; /* Only for AssertRCReturn use. */
2295
2296 /*
2297 * Validate version.
2298 */
2299 if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
2300 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3
2301 && uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2302 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2303 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2304 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2305 && uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2306 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2307 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2308 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2309 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2310 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2311 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2312 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2313 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2314 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2315 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2316 {
2317 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2318 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2319 }
2320
2321 if (uPass == SSM_PASS_FINAL)
2322 {
2323 /*
2324 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2325 * really old SSM file versions.)
2326 */
2327 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2328 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2329 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2330 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2331
2332 /*
2333 * Figure x86 and ctx field definitions to use for older states.
2334 */
2335 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2336 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2337 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2338 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2339 {
2340 paCpumCtx1Fields = g_aCpumX87FieldsV16;
2341 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2342 }
2343 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2344 {
2345 paCpumCtx1Fields = g_aCpumX87FieldsMem;
2346 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2347 }
2348
2349 /*
2350 * The hyper state used to preceed the CPU count. Starting with
2351 * XSAVE it was moved down till after we've got the count.
2352 */
2353 CPUMCTX HyperCtxIgnored;
2354 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2355 {
2356 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2357 {
2358 X86FXSTATE Ign;
2359 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2360 SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2361 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2362 }
2363 }
2364
2365 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2366 {
2367 uint32_t cCpus;
2368 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2369 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2370 VERR_SSM_UNEXPECTED_DATA);
2371 }
2372 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2373 || pVM->cCpus == 1,
2374 ("cCpus=%u\n", pVM->cCpus),
2375 VERR_SSM_UNEXPECTED_DATA);
2376
2377 uint32_t cbMsrs = 0;
2378 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2379 {
2380 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2381 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2382 VERR_SSM_UNEXPECTED_DATA);
2383 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2384 VERR_SSM_UNEXPECTED_DATA);
2385 }
2386
2387 /*
2388 * Do the per-CPU restoring.
2389 */
2390 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2391 {
2392 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2393 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2394
2395 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2396 {
2397 /*
2398 * The XSAVE saved state layout moved the hyper state down here.
2399 */
2400 rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2401 AssertRCReturn(rc, rc);
2402
2403 /*
2404 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2405 */
2406 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2407 AssertRCReturn(rc, rc);
2408 rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2409 AssertRCReturn(rc, rc);
2410
2411 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2412 if (pGstCtx->fXStateMask != 0)
2413 {
2414 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2415 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2416 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2417 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2418 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2419 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2420 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
2421 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2422 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
2423 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
2424 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
2425 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2426 }
2427
2428 /* Check that the XCR0 mask is valid (invalid results in #GP). */
2429 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2430 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2431 {
2432 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
2433 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2434 VERR_CPUM_INVALID_XCR0);
2435 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2436 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2437 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
2438 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2439 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
2440 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
2441 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
2442 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2443 }
2444
2445 /* Check that the XCR1 is zero, as we don't implement it yet. */
2446 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2447
2448 /*
2449 * Restore the individual extended state components we support.
2450 */
2451 if (pGstCtx->fXStateMask != 0)
2452 {
2453 rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2454 0, g_aCpumXSaveHdrFields, NULL);
2455 AssertRCReturn(rc, rc);
2456 AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2457 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
2458 pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2459 VERR_CPUM_INVALID_XSAVE_HDR);
2460 }
2461 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2462 {
2463 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2464 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2465 }
2466 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2467 {
2468 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2469 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2470 }
2471 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2472 {
2473 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2474 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2475 }
2476 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2477 {
2478 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2479 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2480 }
2481 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2482 {
2483 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2484 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2485 }
2486 if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2487 {
2488 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2489 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2490 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2491 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2492 }
2493 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2494 {
2495 if (pVM->cpum.s.GuestFeatures.fSvm)
2496 {
2497 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2498 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2499 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2500 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2501 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2502 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2503 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2504 0 /* fFlags */, g_aSvmHwvirtHostState, NULL /* pvUser */);
2505 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2506 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2507 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2508
2509 uint32_t fSavedLocalFFs = 0;
2510 rc = SSMR3GetU32(pSSM, &fSavedLocalFFs);
2511 AssertRCReturn(rc, rc);
2512 Assert(fSavedLocalFFs == 0 || fSavedLocalFFs == CPUM_OLD_VMCPU_FF_BLOCK_NMIS);
2513 pGstCtx->hwvirt.fSavedInhibit = fSavedLocalFFs & CPUM_OLD_VMCPU_FF_BLOCK_NMIS ? CPUMCTX_INHIBIT_NMI : 0;
2514
2515 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2516 }
2517 }
2518 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2519 {
2520 if (pVM->cpum.s.GuestFeatures.fVmx)
2521 {
2522 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2523 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2524 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2525 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2526 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2527 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2528 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2529 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2530 0, g_aVmxHwvirtVmcs, NULL);
2531 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2532 0, g_aVmxHwvirtVmcs, NULL);
2533 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2534 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2535 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2536 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2537 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2538 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2539 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2540 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2541 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2542 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2543 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2544 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2545 SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2546 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2547 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2548 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2549 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2550 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2551 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2552 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2553 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2554 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2555 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2556 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2557 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2558 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2559 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2560 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2561 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2562 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2563 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2564 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2565 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2566 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3)
2567 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2568 }
2569 }
2570 }
2571 else
2572 {
2573 /*
2574 * Pre XSAVE saved state.
2575 */
2576 SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2577 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2578 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2579 }
2580
2581 /*
2582 * Restore a couple of flags and the MSRs.
2583 */
2584 uint32_t fIgnoredUsedFlags = 0;
2585 rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2586 AssertRCReturn(rc, rc);
2587 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2588
2589 rc = VINF_SUCCESS;
2590 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2591 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2592 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2593 {
2594 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2595 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2596 }
2597 AssertRCReturn(rc, rc);
2598
2599 /* Deal with the reusing of reserved RFLAGS bits. */
2600 pGstCtx->rflags.uBoth |= pVM->cpum.s.fReservedRFlagsCookie;
2601
2602 /* REM and other may have cleared must-be-one fields in DR6 and
2603 DR7, fix these. */
2604 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2605 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
2606 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2607 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
2608 }
2609
2610 /* Older states does not have the internal selector register flags
2611 and valid selector value. Supply those. */
2612 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2613 {
2614 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2615 {
2616 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2617 bool const fValid = true /*!VM_IS_RAW_MODE_ENABLED(pVM)*/
2618 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2619 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2620 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2621 if (fValid)
2622 {
2623 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2624 {
2625 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2626 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2627 }
2628
2629 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2630 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2631 }
2632 else
2633 {
2634 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2635 {
2636 paSelReg[iSelReg].fFlags = 0;
2637 paSelReg[iSelReg].ValidSel = 0;
2638 }
2639
2640 /* This might not be 104% correct, but I think it's close
2641 enough for all practical purposes... (REM always loaded
2642 LDTR registers.) */
2643 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2644 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2645 }
2646 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2647 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2648 }
2649 }
2650
2651 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2652 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2653 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2654 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2655 {
2656 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2657 pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2658 }
2659
2660 /*
2661 * A quick sanity check.
2662 */
2663 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2664 {
2665 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2666 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2667 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2668 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2669 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2670 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2671 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2672 }
2673 }
2674
2675 pVM->cpum.s.fPendingRestore = false;
2676
2677 /*
2678 * Guest CPUIDs (and VMX MSR features).
2679 */
2680 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2681 {
2682 CPUMMSRS GuestMsrs;
2683 RT_ZERO(GuestMsrs);
2684
2685 CPUMFEATURES BaseFeatures;
2686 bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
2687 if (fVmxGstFeat)
2688 {
2689 /*
2690 * At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
2691 * However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
2692 * here so we can compare them for compatibility after exploding guest features.
2693 */
2694 BaseFeatures = pVM->cpum.s.GuestFeatures;
2695
2696 /* Use the VMX MSR features from the saved state while exploding guest features. */
2697 GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
2698 }
2699
2700 /* Load CPUID and explode guest features. */
2701 rc = cpumR3LoadCpuIdX86(pVM, pSSM, uVersion, &GuestMsrs);
2702 if (fVmxGstFeat)
2703 {
2704 /*
2705 * Check if the exploded VMX features from the saved state are compatible with the host-derived features
2706 * we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
2707 * VMX features presented to the guest.
2708 */
2709 bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
2710 if (!fIsCompat)
2711 return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
2712 }
2713 return rc;
2714 }
2715 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2716}
2717
2718
2719DECLHIDDEN(int) cpumR3LoadDoneTarget(PVM pVM, PSSMHANDLE pSSM)
2720{
2721 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2722 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2723 {
2724 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2725
2726 /* Notify PGM of the NXE states in case they've changed. */
2727 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2728
2729 /* During init. this is done in CPUMR3InitCompleted(). */
2730 if (fSupportsLongMode)
2731 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2732
2733 /* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
2734 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
2735 }
2736 RT_NOREF(pSSM);
2737 return VINF_SUCCESS;
2738}
2739
2740
2741/*********************************************************************************************************************************
2742* MTRR *
2743*********************************************************************************************************************************/
2744
2745
2746/**
2747 * Gets the variable-range MTRR physical address mask given an address range.
2748 *
2749 * @returns The MTRR physical address mask.
2750 * @param pVM The cross context VM structure.
2751 * @param GCPhysFirst The first guest-physical address of the memory range
2752 * (inclusive).
2753 * @param GCPhysLast The last guest-physical address of the memory range
2754 * (inclusive).
2755 */
2756static uint64_t cpumR3GetVarMtrrMask(PVM pVM, RTGCPHYS GCPhysFirst, RTGCPHYS GCPhysLast)
2757{
2758 RTGCPHYS const GCPhysLength = GCPhysLast - GCPhysFirst;
2759 uint64_t const fInvPhysMask = ~(RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
2760 RTGCPHYS const GCPhysMask = (~(GCPhysLength - 1) & ~fInvPhysMask) & X86_PAGE_BASE_MASK;
2761#ifdef VBOX_STRICT
2762 AssertMsg(GCPhysLast == ((GCPhysFirst | ~GCPhysMask) & ~fInvPhysMask),
2763 ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
2764 AssertMsg(((GCPhysLast & GCPhysMask) == (GCPhysFirst & GCPhysMask)),
2765 ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
2766 AssertMsg(((GCPhysLast + 1) & GCPhysMask) != (GCPhysFirst & GCPhysMask),
2767 ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
2768
2769 uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
2770 AssertMsg(cbRange >= _4K, ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
2771 GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
2772 AssertMsg(RT_IS_POWER_OF_TWO(cbRange), ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
2773 GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
2774 AssertMsg(GCPhysFirst == 0 || cbRange <= GCPhysFirst, ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
2775 GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
2776#endif
2777 return GCPhysMask;
2778}
2779
2780
2781/**
2782 * Gets the first and last guest-physical address for the given variable-range
2783 * MTRR.
2784 *
2785 * @param pVM The cross context VM structure.
2786 * @param pMtrrVar The variable-range MTRR.
2787 * @param pGCPhysFirst Where to store the first guest-physical address of the
2788 * memory range (inclusive).
2789 * @param pGCPhysLast Where to store the last guest-physical address of the
2790 * memory range (inclusive).
2791 */
2792static void cpumR3GetVarMtrrAddrs(PVM pVM, PCX86MTRRVAR pMtrrVar, PRTGCPHYS pGCPhysFirst, PRTGCPHYS pGCPhysLast)
2793{
2794 Assert(pMtrrVar);
2795 Assert(pGCPhysFirst);
2796 Assert(pGCPhysLast);
2797 uint64_t const fInvPhysMask = ~(RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
2798 RTGCPHYS const GCPhysMask = pMtrrVar->MtrrPhysMask & X86_PAGE_BASE_MASK;
2799 RTGCPHYS const GCPhysFirst = pMtrrVar->MtrrPhysBase & X86_PAGE_BASE_MASK;
2800 RTGCPHYS const GCPhysLast = (GCPhysFirst | ~GCPhysMask) & ~fInvPhysMask;
2801 Assert((GCPhysLast & GCPhysMask) == (GCPhysFirst & GCPhysMask));
2802 Assert(((GCPhysLast + 1) & GCPhysMask) != (GCPhysFirst & GCPhysMask));
2803 *pGCPhysFirst = GCPhysFirst;
2804 *pGCPhysLast = GCPhysLast;
2805}
2806
2807
2808/**
2809 * Gets the previous power of two for a given value.
2810 *
2811 * @returns Previous power of two.
2812 * @param uVal The value (must not be zero).
2813 */
2814static uint64_t cpumR3GetPrevPowerOfTwo(uint64_t uVal)
2815{
2816 Assert(uVal > 1);
2817 uint8_t const cBits = sizeof(uVal) << 3;
2818 return RT_BIT_64(cBits - 1 - ASMCountLeadingZerosU64(uVal));
2819}
2820
2821
2822/**
2823 * Gets the next power of two for a given value.
2824 *
2825 * @returns Next power of two.
2826 * @param uVal The value (must not be zero).
2827 */
2828static uint64_t cpumR3GetNextPowerOfTwo(uint64_t uVal)
2829{
2830 Assert(uVal > 1);
2831 uint8_t const cBits = sizeof(uVal) << 3;
2832 return RT_BIT_64(cBits - ASMCountLeadingZerosU64(uVal));
2833}
2834
2835
2836/**
2837 * Gets the MTRR memory type description.
2838 *
2839 * @returns The MTRR memory type description.
2840 * @param fType The MTRR memory type.
2841 */
2842static const char *cpumR3GetVarMtrrMemType(uint8_t fType)
2843{
2844 switch (fType)
2845 {
2846 case X86_MTRR_MT_UC: return "UC";
2847 case X86_MTRR_MT_WC: return "WC";
2848 case X86_MTRR_MT_WT: return "WT";
2849 case X86_MTRR_MT_WP: return "WP";
2850 case X86_MTRR_MT_WB: return "WB";
2851 default: return "--";
2852 }
2853}
2854
2855
2856/**
2857 * Adds a memory region to the given MTRR map.
2858 *
2859 * @returns VBox status code.
2860 * @retval VINF_SUCCESS when the map could accommodate a memory region being
2861 * added.
2862 * @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
2863 * memory region.
2864 *
2865 * @param pVM The cross context VM structure.
2866 * @param pMtrrMap The variable-range MTRR map to add to.
2867 * @param GCPhysFirst The first guest-physical address in the memory region.
2868 * @param GCPhysLast The last guest-physical address in the memory region.
2869 * @param fType The MTRR memory type of the memory region being added.
2870 */
2871static int cpumR3MtrrMapAddRegion(PVM pVM, PCPUMMTRRMAP pMtrrMap, RTGCPHYS GCPhysFirst, RTGCPHYS GCPhysLast, uint8_t fType)
2872{
2873 Assert(fType < 7 && fType != 2 && fType != 3);
2874 if (pMtrrMap->idxMtrr < pMtrrMap->cMtrrs)
2875 {
2876 /*
2877 * We must ensure the physical-address does not exceed the maximum guest-physical address width.
2878 * Otherwise, the MTRR physical mask computation gets totally busted rather than returning 0 to
2879 * indicate such mapping is impossible.
2880 */
2881 RTGCPHYS const GCPhysLastMax = RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U;
2882 if (GCPhysLast <= GCPhysLastMax)
2883 {
2884 pMtrrMap->aMtrrs[pMtrrMap->idxMtrr].MtrrPhysBase = GCPhysFirst | fType;
2885 pMtrrMap->aMtrrs[pMtrrMap->idxMtrr].MtrrPhysMask = cpumR3GetVarMtrrMask(pVM, GCPhysFirst, GCPhysLast)
2886 | MSR_IA32_MTRR_PHYSMASK_VALID;
2887 ++pMtrrMap->idxMtrr;
2888
2889 uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
2890 if (fType != X86_MTRR_MT_UC)
2891 pMtrrMap->cbMapped += cbRange;
2892 else
2893 {
2894 Assert(pMtrrMap->cbMapped >= cbRange);
2895 pMtrrMap->cbMapped -= cbRange;
2896 }
2897 return VINF_SUCCESS;
2898 }
2899 }
2900 return VERR_OUT_OF_RESOURCES;
2901}
2902
2903
2904/**
2905 * Adds an MTRR to the given MTRR map.
2906 *
2907 * @returns VBox status code.
2908 * @retval VINF_SUCCESS when the map could accommodate the MTRR being added.
2909 * @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
2910 * MTRR.
2911 *
2912 * @param pVM The cross context VM structure.
2913 * @param pMtrrMap The variable-range MTRR map to add to.
2914 * @param pVarMtrr The variable-range MTRR to add from.
2915 */
2916static int cpumR3MtrrMapAddMtrr(PVM pVM, PCPUMMTRRMAP pMtrrMap, PCX86MTRRVAR pVarMtrr)
2917{
2918 RTGCPHYS GCPhysFirst;
2919 RTGCPHYS GCPhysLast;
2920 cpumR3GetVarMtrrAddrs(pVM, pVarMtrr, &GCPhysFirst, &GCPhysLast);
2921 uint8_t const fType = pVarMtrr->MtrrPhysBase & MSR_IA32_MTRR_PHYSBASE_MT_MASK;
2922 return cpumR3MtrrMapAddRegion(pVM, pMtrrMap, GCPhysFirst, GCPhysLast, fType);
2923}
2924
2925
2926/**
2927 * Adds a source MTRR map to the given destination MTRR map.
2928 *
2929 * @returns VBox status code.
2930 * @retval VINF_SUCCESS when the map could fully accommodate the map being added.
2931 * @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
2932 * specified map.
2933 *
2934 * @param pVM The cross context VM structure.
2935 * @param pMtrrMapDst The variable-range MTRR map to add to (destination).
2936 * @param pMtrrMapSrc The variable-range MTRR map to add from (source).
2937 */
2938static int cpumR3MtrrMapAddMap(PVM pVM, PCPUMMTRRMAP pMtrrMapDst, PCCPUMMTRRMAP pMtrrMapSrc)
2939{
2940 Assert(pMtrrMapDst);
2941 Assert(pMtrrMapSrc);
2942 for (uint8_t i = 0 ; i < pMtrrMapSrc->idxMtrr; i++)
2943 {
2944 int const rc = cpumR3MtrrMapAddMtrr(pVM, pMtrrMapDst, &pMtrrMapSrc->aMtrrs[i]);
2945 if (RT_FAILURE(rc))
2946 return rc;
2947 }
2948 return VINF_SUCCESS;
2949}
2950
2951
2952/**
2953 * Maps memory using an additive method using variable-range MTRRs.
2954 *
2955 * The additive method fits as many valid MTRR WB (write-back) sub-regions to map
2956 * the specified memory size. For instance, 3584 MB is mapped as 2048 MB, 1024 MB
2957 * and 512 MB of WB memory, requiring 3 MTRRs.
2958 *
2959 * @returns VBox status code.
2960 * @retval VINF_SUCCESS when the requested memory could be fully mapped within the
2961 * given number of MTRRs.
2962 * @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
2963 * mapped within the given number of MTRRs.
2964 *
2965 * @param pVM The cross context VM structure.
2966 * @param GCPhysRegionFirst The guest-physical address in the region being
2967 * mapped.
2968 * @param cb The number of bytes being mapped.
2969 * @param pMtrrMap The variable-range MTRR map to populate.
2970 */
2971static int cpumR3MapMtrrsAdditive(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
2972{
2973 Assert(pMtrrMap);
2974 Assert(pMtrrMap->cMtrrs > 1);
2975 Assert(cb >= _4K);
2976 Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
2977
2978 uint64_t cbLeft = cb;
2979 uint64_t offRegion = GCPhysRegionFirst;
2980 while (cbLeft > 0)
2981 {
2982 uint64_t const cbRegion = !RT_IS_POWER_OF_TWO(cbLeft) ? cpumR3GetPrevPowerOfTwo(cbLeft) : cbLeft;
2983
2984 Log3(("CPUM: MTRR: Add[%u]: %Rhcb (%RU64 bytes)\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
2985 int const rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion, offRegion + cbRegion - 1, X86_MTRR_MT_WB);
2986 if (RT_FAILURE(rc))
2987 return rc;
2988
2989 cbLeft -= RT_MIN(cbRegion, cbLeft);
2990 offRegion += cbRegion;
2991 }
2992 return VINF_SUCCESS;
2993}
2994
2995
2996/**
2997 * Maps memory using a subtractive method using variable-range MTRRs.
2998 *
2999 * The subtractive method rounds up the memory region using WB (write-back) memory
3000 * type and then "subtracts" sub-regions using UC (uncacheable) memory type. For
3001 * instance, 3584 MB is mapped as 4096 MB of WB minus 512 MB of UC, requiring 2
3002 * MTRRs.
3003 *
3004 * @returns VBox status code.
3005 * @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3006 * given number of MTRRs.
3007 * @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3008 * mapped within the given number of MTRRs.
3009 *
3010 * @param pVM The cross context VM structure.
3011 * @param GCPhysRegionFirst The guest-physical address in the region being
3012 * mapped.
3013 * @param cb The number of bytes being mapped.
3014 * @param pMtrrMap The variable-range MTRR map to populate.
3015 */
3016static int cpumR3MapMtrrsSubtractive(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3017{
3018 Assert(pMtrrMap);
3019 Assert(pMtrrMap->cMtrrs > 1);
3020 Assert(cb >= _4K);
3021 Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
3022
3023 uint64_t const cbRegion = !RT_IS_POWER_OF_TWO(cb) ? cpumR3GetNextPowerOfTwo(cb) : cb;
3024 Assert(cbRegion >= cb);
3025
3026 Log3(("CPUM: MTRR: Sub[%u]: %Rhcb (%RU64 bytes) [WB]\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
3027 int rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, GCPhysRegionFirst, GCPhysRegionFirst + cbRegion - 1, X86_MTRR_MT_WB);
3028 if (RT_FAILURE(rc))
3029 return rc;
3030
3031 uint64_t cbLeft = cbRegion - cb;
3032 RTGCPHYS offRegion = GCPhysRegionFirst + cbRegion;
3033 while (cbLeft > 0)
3034 {
3035 uint64_t const cbSubRegion = cpumR3GetPrevPowerOfTwo(cbLeft);
3036
3037 Log3(("CPUM: MTRR: Sub[%u]: %Rhcb (%RU64 bytes) [UC]\n", pMtrrMap->idxMtrr, cbSubRegion, cbSubRegion));
3038 rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion - cbSubRegion, offRegion - 1, X86_MTRR_MT_UC);
3039 if (RT_FAILURE(rc))
3040 return rc;
3041
3042 cbLeft -= RT_MIN(cbSubRegion, cbLeft);
3043 offRegion -= cbSubRegion;
3044 }
3045 return rc;
3046}
3047
3048
3049/**
3050 * Optimally maps RAM when it's not necessarily aligned to a power of two using
3051 * variable-range MTRRs.
3052 *
3053 * @returns VBox status code.
3054 * @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3055 * given number of MTRRs.
3056 * @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3057 * mapped within the given number of MTRRs.
3058 *
3059 * @param pVM The cross context VM structure.
3060 * @param GCPhysRegionFirst The guest-physical address in the region being
3061 * mapped.
3062 * @param cb The number of bytes being mapped.
3063 * @param pMtrrMap The variable-range MTRR map to populate.
3064 */
3065static int cpumR3MapMtrrsOptimal(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3066{
3067 Assert(pMtrrMap);
3068 Assert(pMtrrMap->cMtrrs > 1);
3069 Assert(cb >= _4K);
3070 Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
3071
3072 /*
3073 * Additive method.
3074 */
3075 CPUMMTRRMAP MtrrMapAdd;
3076 RT_ZERO(MtrrMapAdd);
3077 MtrrMapAdd.cMtrrs = pMtrrMap->cMtrrs;
3078 MtrrMapAdd.cbToMap = cb;
3079 int rcAdd;
3080 {
3081 rcAdd = cpumR3MapMtrrsAdditive(pVM, GCPhysRegionFirst, cb, &MtrrMapAdd);
3082 if (RT_SUCCESS(rcAdd))
3083 {
3084 Assert(MtrrMapAdd.idxMtrr > 0);
3085 Assert(MtrrMapAdd.idxMtrr <= MtrrMapAdd.cMtrrs);
3086 Assert(MtrrMapAdd.cbMapped == MtrrMapAdd.cbToMap);
3087 Log3(("CPUM: MTRR: Mapped %u regions using additive method\n", MtrrMapAdd.idxMtrr));
3088
3089 /*
3090 * If we were able to map memory using 2 or fewer MTRRs, don't bother with trying
3091 * to map using the subtractive method as that requires at least 2 MTRRs anyway.
3092 */
3093 if (MtrrMapAdd.idxMtrr <= 2)
3094 return cpumR3MtrrMapAddMap(pVM, pMtrrMap, &MtrrMapAdd);
3095 }
3096 else
3097 Log3(("CPUM: MTRR: Partially mapped %u regions using additive method\n", MtrrMapAdd.idxMtrr));
3098 }
3099
3100 /*
3101 * Subtractive method.
3102 */
3103 CPUMMTRRMAP MtrrMapSub;
3104 RT_ZERO(MtrrMapSub);
3105 MtrrMapSub.cMtrrs = pMtrrMap->cMtrrs;
3106 MtrrMapSub.cbToMap = cb;
3107 int rcSub;
3108 {
3109 rcSub = cpumR3MapMtrrsSubtractive(pVM, GCPhysRegionFirst, cb, &MtrrMapSub);
3110 if (RT_SUCCESS(rcSub))
3111 {
3112 Assert(MtrrMapSub.idxMtrr > 0);
3113 Assert(MtrrMapSub.idxMtrr <= MtrrMapSub.cMtrrs);
3114 Assert(MtrrMapSub.cbMapped == MtrrMapSub.cbToMap);
3115 Log3(("CPUM: MTRR: Mapped %u regions using subtractive method\n", MtrrMapSub.idxMtrr));
3116 }
3117 else
3118 Log3(("CPUM: MTRR: Partially mapped %u regions using subtractive method\n", MtrrMapAdd.idxMtrr));
3119 }
3120
3121 /*
3122 * Pick whichever method requires fewer MTRRs to map the memory.
3123 */
3124 PCCPUMMTRRMAP pMtrrMapOptimal;
3125 if ( RT_SUCCESS(rcAdd)
3126 && RT_SUCCESS(rcSub))
3127 {
3128 Assert(MtrrMapAdd.cbMapped == MtrrMapSub.cbMapped);
3129 if (MtrrMapSub.idxMtrr < MtrrMapAdd.idxMtrr)
3130 pMtrrMapOptimal = &MtrrMapSub;
3131 else
3132 pMtrrMapOptimal = &MtrrMapAdd;
3133 }
3134 else if (RT_SUCCESS(rcAdd))
3135 pMtrrMapOptimal = &MtrrMapAdd;
3136 else if (RT_SUCCESS(rcSub))
3137 pMtrrMapOptimal = &MtrrMapSub;
3138 else
3139 {
3140 /*
3141 * If both methods fail, use the additive method as it gives partially mapped
3142 * memory as opposed to memory that isn't present.
3143 */
3144 pMtrrMapOptimal = &MtrrMapAdd;
3145 }
3146
3147 int const rc = cpumR3MtrrMapAddMap(pVM, pMtrrMap, pMtrrMapOptimal);
3148 if ( RT_SUCCESS(rc)
3149 && pMtrrMapOptimal->cbMapped == pMtrrMapOptimal->cbToMap) /* Required to distinguish full vs overflow state. */
3150 return VINF_SUCCESS;
3151 return VERR_OUT_OF_RESOURCES;
3152}
3153
3154
3155/**
3156 * Maps RAM above 4GB using variable-range MTRRs.
3157 *
3158 * @returns VBox status code.
3159 * @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3160 * given number of MTRRs.
3161 * @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3162 * mapped within the given number of MTRRs.
3163 *
3164 * @param pVM The cross context VM structure.
3165 * @param cb The number of bytes above 4GB to map.
3166 * @param pMtrrMap The variable-range MTRR map to populate.
3167 */
3168static int cpumR3MapMtrrsAbove4GB(PVM pVM, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3169{
3170 Assert(pMtrrMap);
3171 Assert(pMtrrMap->cMtrrs > 1);
3172 Assert(cb >= _4K);
3173
3174 /*
3175 * Map regions at incremental powers of two offsets and sizes.
3176 * Note: We cannot map an 8GB region in a 4GB offset.
3177 */
3178 uint64_t cbLeft = cb;
3179 uint64_t offRegion = _4G;
3180 while (cbLeft > offRegion)
3181 {
3182 uint64_t const cbRegion = offRegion;
3183
3184 Log3(("CPUM: MTRR: [%u]: %Rhcb (%RU64 bytes)\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
3185 int const rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion, offRegion + cbRegion - 1, X86_MTRR_MT_WB);
3186 if (RT_FAILURE(rc))
3187 return rc;
3188
3189 offRegion <<= 1;
3190 cbLeft -= RT_MIN(cbRegion, cbLeft);
3191 }
3192
3193 /*
3194 * Optimally try and map any remaining memory that is smaller than
3195 * the last power of two offset (size) above.
3196 */
3197 if (cbLeft > 0)
3198 {
3199 Assert(pMtrrMap->cMtrrs - pMtrrMap->idxMtrr > 0);
3200 return cpumR3MapMtrrsOptimal(pVM, offRegion, cbLeft, pMtrrMap);
3201 }
3202 return VINF_SUCCESS;
3203}
3204
3205
3206/**
3207 * Maps guest RAM via MTRRs.
3208 *
3209 * @returns VBox status code.
3210 * @param pVM The cross context VM structure.
3211 */
3212static int cpumR3MapMtrrs(PVM pVM)
3213{
3214 /*
3215 * The RAM size configured for the VM does NOT include the RAM hole!
3216 * We cannot make ANY assumptions about the RAM size or the RAM hole size
3217 * of the VM since it is configurable by the user. Hence, we must check for
3218 * atypical sizes.
3219 */
3220 uint64_t cbRam;
3221 int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
3222 if (RT_FAILURE(rc))
3223 {
3224 LogRel(("CPUM: Cannot map RAM via MTRRs since the RAM size is not configured for the VM\n"));
3225 return VINF_SUCCESS;
3226 }
3227 if (!(cbRam & ~X86_PAGE_4K_BASE_MASK))
3228 { /* likely */ }
3229 else
3230 {
3231 LogRel(("CPUM: WARNING! RAM size %RU64 bytes is not 4K aligned, using %RU64 bytes\n", cbRam, cbRam & X86_PAGE_4K_BASE_MASK));
3232 cbRam &= X86_PAGE_4K_BASE_MASK;
3233 }
3234
3235 /*
3236 * Map the RAM below 1MB.
3237 */
3238 if (cbRam >= _1M)
3239 {
3240 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3241 {
3242 PCPUMCTXMSRS pCtxMsrs = &pVM->apCpusR3[idCpu]->cpum.s.GuestMsrs;
3243 pCtxMsrs->msr.MtrrFix64K_00000 = 0x0606060606060606;
3244 pCtxMsrs->msr.MtrrFix16K_80000 = 0x0606060606060606;
3245 pCtxMsrs->msr.MtrrFix16K_A0000 = 0;
3246 pCtxMsrs->msr.MtrrFix4K_C0000 = 0x0505050505050505;
3247 pCtxMsrs->msr.MtrrFix4K_C8000 = 0x0505050505050505;
3248 pCtxMsrs->msr.MtrrFix4K_D0000 = 0x0505050505050505;
3249 pCtxMsrs->msr.MtrrFix4K_D8000 = 0x0505050505050505;
3250 pCtxMsrs->msr.MtrrFix4K_E0000 = 0x0505050505050505;
3251 pCtxMsrs->msr.MtrrFix4K_E8000 = 0x0505050505050505;
3252 pCtxMsrs->msr.MtrrFix4K_F0000 = 0x0505050505050505;
3253 pCtxMsrs->msr.MtrrFix4K_F8000 = 0x0505050505050505;
3254 }
3255 LogRel(("CPUM: Mapped %Rhcb (%u bytes) of RAM using fixed-range MTRRs\n", _1M, _1M));
3256 }
3257 else
3258 {
3259 LogRel(("CPUM: WARNING! Cannot map RAM via MTRRs since the RAM size is below 1M\n"));
3260 return VINF_SUCCESS;
3261 }
3262
3263 if (cbRam > _1M + _4K)
3264 { /* likely */ }
3265 else
3266 {
3267 LogRel(("CPUM: WARNING! Cannot map RAM above 1M via MTRRs since the RAM size above 1M is below 4K\n"));
3268 return VINF_SUCCESS;
3269 }
3270
3271 /*
3272 * Check if there is at least 1 MTRR available in addition to MTRRs reserved
3273 * for use by software for mapping guest memory, see @bugref{10498#c34}.
3274 *
3275 * Intel Pentium Pro Processor's BIOS Writers Guide and our EFI code reserves
3276 * 2 MTRRs for use by software and thus we reserve the same here.
3277 */
3278 uint8_t const cMtrrsMax = pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.MtrrCap & MSR_IA32_MTRR_CAP_VCNT_MASK;
3279 uint8_t const cMtrrsRsvd = 2;
3280 if (cMtrrsMax < cMtrrsRsvd + 1)
3281 {
3282 LogRel(("CPUM: WARNING! Variable-range MTRRs (%u) insufficient to map RAM since %u of them are reserved for software\n",
3283 cMtrrsMax, cMtrrsRsvd));
3284 return VINF_SUCCESS;
3285 }
3286
3287 CPUMMTRRMAP MtrrMap;
3288 RT_ZERO(MtrrMap);
3289 uint8_t const cMtrrsMappable = cMtrrsMax - cMtrrsRsvd;
3290 Assert(cMtrrsMappable > 0); /* Paranoia. */
3291 AssertLogRelMsgReturn(cMtrrsMappable <= RT_ELEMENTS(MtrrMap.aMtrrs),
3292 ("Mappable variable-range MTRRs (%u) exceed MTRRs available (%u)\n", cMtrrsMappable,
3293 RT_ELEMENTS(MtrrMap.aMtrrs)),
3294 VERR_CPUM_IPE_1);
3295 MtrrMap.cMtrrs = cMtrrsMappable;
3296 MtrrMap.cbToMap = cbRam;
3297
3298 /*
3299 * Get the RAM hole size configured for the VM.
3300 * Since MM has already validated it, we only debug assert the same constraints here.
3301 *
3302 * Although it is not required by the MTRR mapping code that the RAM hole size be a
3303 * power of 2, it is highly recommended to keep it this way in order to drastically
3304 * reduce the number of MTRRs used.
3305 */
3306 uint32_t const cbRamHole = MMR3PhysGet4GBRamHoleSize(pVM);
3307 AssertMsg(cbRamHole <= 4032U * _1M, ("RAM hole size (%RU32 bytes) is too large\n", cbRamHole));
3308 AssertMsg(cbRamHole > 16 * _1M, ("RAM hole size (%RU32 bytes) is too small\n", cbRamHole));
3309 AssertMsg(!(cbRamHole & (_4M - 1)), ("RAM hole size (%RU32 bytes) must be 4MB aligned\n", cbRamHole));
3310
3311 /*
3312 * Paranoia.
3313 * Ensure the maximum physical-address width can accommodate the specified RAM size.
3314 */
3315 RTGCPHYS const GCPhysEndMax = RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth);
3316 RTGCPHYS const GCPhysEnd = cbRam + cbRamHole;
3317 if (GCPhysEnd <= GCPhysEndMax)
3318 { /* likely */ }
3319 else
3320 {
3321 LogRel(("CPUM: WARNING! Cannot fully map RAM of %Rhcb (%RU64 bytes) as it exceeds maximum physical-address (%#RX64)\n",
3322 GCPhysEnd, GCPhysEnd, GCPhysEndMax - 1));
3323 }
3324
3325 /*
3326 * Map the RAM (and RAM hole) below 4GB.
3327 */
3328 uint64_t const cbBelow4GB = RT_MIN(cbRam, (uint64_t)_4G - cbRamHole);
3329 rc = cpumR3MapMtrrsOptimal(pVM, 0 /* GCPhysFirst */, cbBelow4GB, &MtrrMap);
3330 if (RT_SUCCESS(rc))
3331 {
3332 Assert(MtrrMap.idxMtrr > 0);
3333 Assert(MtrrMap.idxMtrr <= MtrrMap.cMtrrs);
3334 Assert(MtrrMap.cbMapped == cbBelow4GB);
3335
3336 /*
3337 * Map the RAM above 4GB.
3338 */
3339 uint64_t const cbAbove4GB = cbRam + cbRamHole > _4G ? cbRam + cbRamHole - _4G : 0;
3340 if (cbAbove4GB)
3341 {
3342 rc = cpumR3MapMtrrsAbove4GB(pVM, cbAbove4GB, &MtrrMap);
3343 if (RT_SUCCESS(rc))
3344 Assert(MtrrMap.cbMapped == MtrrMap.cbToMap);
3345 }
3346 LogRel(("CPUM: Mapped %Rhcb (%RU64 bytes) of RAM using %u variable-range MTRRs\n", MtrrMap.cbMapped, MtrrMap.cbMapped,
3347 MtrrMap.idxMtrr));
3348 }
3349
3350 /*
3351 * Check if we ran out of MTRRs while mapping the memory.
3352 */
3353 if (MtrrMap.cbMapped < cbRam)
3354 {
3355 Assert(rc == VERR_OUT_OF_RESOURCES);
3356 Assert(MtrrMap.idxMtrr == cMtrrsMappable);
3357 Assert(MtrrMap.idxMtrr == MtrrMap.cMtrrs);
3358 uint64_t const cbLost = cbRam - MtrrMap.cbMapped;
3359 LogRel(("CPUM: WARNING! Could not map %Rhcb (%RU64 bytes) of RAM using %u variable-range MTRRs\n", cbLost, cbLost,
3360 MtrrMap.cMtrrs));
3361 }
3362
3363 /*
3364 * Copy mapped MTRRs to all VCPUs.
3365 */
3366 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3367 {
3368 PCPUMCTXMSRS pCtxMsrs = &pVM->apCpusR3[idCpu]->cpum.s.GuestMsrs;
3369 Assert(sizeof(pCtxMsrs->msr.aMtrrVarMsrs) == sizeof(MtrrMap.aMtrrs));
3370 memcpy(&pCtxMsrs->msr.aMtrrVarMsrs[0], &MtrrMap.aMtrrs[0], sizeof(MtrrMap.aMtrrs));
3371 }
3372
3373 return VINF_SUCCESS;
3374}
3375
3376
3377
3378/*********************************************************************************************************************************
3379* Debug Info Items *
3380*********************************************************************************************************************************/
3381
3382/**
3383 * Formats a full register dump.
3384 *
3385 * @param pVM The cross context VM structure.
3386 * @param pVCpu The cross context virtual CPU structure.
3387 * @param pHlp Output functions.
3388 * @param enmType The dump type.
3389 */
3390DECLHIDDEN(void) cpumR3InfoOneTarget(PVM pVM, PCVMCPU pVCpu, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType)
3391{
3392 const char * const pszPrefix = "";
3393 PCCPUMCTX const pCtx = &pVCpu->cpum.s.Guest;
3394
3395 /*
3396 * Format the EFLAGS.
3397 */
3398 char szEFlags[80];
3399 cpumR3InfoFormatFlagsX86(&szEFlags[0], pCtx->eflags.uBoth);
3400
3401 /*
3402 * Format the registers.
3403 */
3404 uint32_t const efl = pCtx->eflags.u;
3405 switch (enmType)
3406 {
3407 case CPUMDUMPTYPE_TERSE:
3408 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3409 pHlp->pfnPrintf(pHlp,
3410 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3411 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3412 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3413 "%sr14=%016RX64 %sr15=%016RX64\n"
3414 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3415 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3416 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3417 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3418 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3419 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3420 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3421 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3422 else
3423 pHlp->pfnPrintf(pHlp,
3424 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3425 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3426 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3427 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3428 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3429 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3430 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3431 break;
3432
3433 case CPUMDUMPTYPE_DEFAULT:
3434 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3435 pHlp->pfnPrintf(pHlp,
3436 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3437 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3438 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3439 "%sr14=%016RX64 %sr15=%016RX64\n"
3440 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3441 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3442 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3443 ,
3444 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3445 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3446 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3447 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3448 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3449 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3450 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3451 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3452 else
3453 pHlp->pfnPrintf(pHlp,
3454 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3455 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3456 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3457 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3458 ,
3459 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3460 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3461 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3462 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3463 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3464 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3465 break;
3466
3467 case CPUMDUMPTYPE_VERBOSE:
3468 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3469 pHlp->pfnPrintf(pHlp,
3470 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3471 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3472 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3473 "%sr14=%016RX64 %sr15=%016RX64\n"
3474 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3475 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3476 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3477 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3478 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3479 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3480 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3481 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3482 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3483 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3484 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3485 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3486 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3487 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3488 ,
3489 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3490 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3491 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3492 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3493 pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3494 pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3495 pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3496 pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3497 pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3498 pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3499 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3500 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3501 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3502 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3503 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3504 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3505 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3506 else
3507 pHlp->pfnPrintf(pHlp,
3508 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3509 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3510 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3511 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3512 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3513 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3514 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3515 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3516 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3517 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3518 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3519 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3520 ,
3521 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3522 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3523 pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3524 pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3525 pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3526 pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3527 pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3528 pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3529 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3530 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3531 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3532 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3533
3534 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3535 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3536 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3537 {
3538 PCX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3539 pHlp->pfnPrintf(pHlp,
3540 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3541 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3542 ,
3543 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3544 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3545 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3546 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3547 );
3548 /*
3549 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3550 * not (FP)R0-7 as Intel SDM suggests.
3551 */
3552 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3553 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3554 {
3555 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3556 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3557 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3558 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3559 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3560 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3561 iExponent -= 16383; /* subtract bias */
3562 /** @todo This isn't entirenly correct and needs more work! */
3563 pHlp->pfnPrintf(pHlp,
3564 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3565 pszPrefix, iST, pszPrefix, iFPR,
3566 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3567 uTag, chSign, iInteger, u64Fraction, iExponent);
3568 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
3569 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3570 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3571 else
3572 pHlp->pfnPrintf(pHlp, "\n");
3573 }
3574
3575 /* XMM/YMM/ZMM registers. */
3576 if (pCtx->fXStateMask & XSAVE_C_YMM)
3577 {
3578 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3579 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3580 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3581 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3582 pszPrefix, i, i < 10 ? " " : "",
3583 pYmmHiCtx->aYmmHi[i].au32[3],
3584 pYmmHiCtx->aYmmHi[i].au32[2],
3585 pYmmHiCtx->aYmmHi[i].au32[1],
3586 pYmmHiCtx->aYmmHi[i].au32[0],
3587 pFpuCtx->aXMM[i].au32[3],
3588 pFpuCtx->aXMM[i].au32[2],
3589 pFpuCtx->aXMM[i].au32[1],
3590 pFpuCtx->aXMM[i].au32[0]);
3591 else
3592 {
3593 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3594 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3595 pHlp->pfnPrintf(pHlp,
3596 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3597 pszPrefix, i, i < 10 ? " " : "",
3598 pZmmHi256->aHi256Regs[i].au32[7],
3599 pZmmHi256->aHi256Regs[i].au32[6],
3600 pZmmHi256->aHi256Regs[i].au32[5],
3601 pZmmHi256->aHi256Regs[i].au32[4],
3602 pZmmHi256->aHi256Regs[i].au32[3],
3603 pZmmHi256->aHi256Regs[i].au32[2],
3604 pZmmHi256->aHi256Regs[i].au32[1],
3605 pZmmHi256->aHi256Regs[i].au32[0],
3606 pYmmHiCtx->aYmmHi[i].au32[3],
3607 pYmmHiCtx->aYmmHi[i].au32[2],
3608 pYmmHiCtx->aYmmHi[i].au32[1],
3609 pYmmHiCtx->aYmmHi[i].au32[0],
3610 pFpuCtx->aXMM[i].au32[3],
3611 pFpuCtx->aXMM[i].au32[2],
3612 pFpuCtx->aXMM[i].au32[1],
3613 pFpuCtx->aXMM[i].au32[0]);
3614
3615 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3616 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3617 pHlp->pfnPrintf(pHlp,
3618 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3619 pszPrefix, i + 16,
3620 pZmm16Hi->aRegs[i].au32[15],
3621 pZmm16Hi->aRegs[i].au32[14],
3622 pZmm16Hi->aRegs[i].au32[13],
3623 pZmm16Hi->aRegs[i].au32[12],
3624 pZmm16Hi->aRegs[i].au32[11],
3625 pZmm16Hi->aRegs[i].au32[10],
3626 pZmm16Hi->aRegs[i].au32[9],
3627 pZmm16Hi->aRegs[i].au32[8],
3628 pZmm16Hi->aRegs[i].au32[7],
3629 pZmm16Hi->aRegs[i].au32[6],
3630 pZmm16Hi->aRegs[i].au32[5],
3631 pZmm16Hi->aRegs[i].au32[4],
3632 pZmm16Hi->aRegs[i].au32[3],
3633 pZmm16Hi->aRegs[i].au32[2],
3634 pZmm16Hi->aRegs[i].au32[1],
3635 pZmm16Hi->aRegs[i].au32[0]);
3636 }
3637 }
3638 else
3639 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3640 pHlp->pfnPrintf(pHlp,
3641 i & 1
3642 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3643 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3644 pszPrefix, i, i < 10 ? " " : "",
3645 pFpuCtx->aXMM[i].au32[3],
3646 pFpuCtx->aXMM[i].au32[2],
3647 pFpuCtx->aXMM[i].au32[1],
3648 pFpuCtx->aXMM[i].au32[0]);
3649
3650 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3651 {
3652 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3653 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3654 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3655 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3656 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3657 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3658 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3659 }
3660
3661 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3662 {
3663 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3664 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3665 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3666 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3667 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3668 }
3669
3670 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3671 {
3672 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3673 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3674 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3675 }
3676
3677 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3678 if (pFpuCtx->au32RsrvdRest[i])
3679 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3680 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3681 }
3682
3683 pHlp->pfnPrintf(pHlp,
3684 "%sEFER =%016RX64\n"
3685 "%sPAT =%016RX64\n"
3686 "%sSTAR =%016RX64\n"
3687 "%sCSTAR =%016RX64\n"
3688 "%sLSTAR =%016RX64\n"
3689 "%sSFMASK =%016RX64\n"
3690 "%sKERNELGSBASE =%016RX64\n",
3691 pszPrefix, pCtx->msrEFER,
3692 pszPrefix, pCtx->msrPAT,
3693 pszPrefix, pCtx->msrSTAR,
3694 pszPrefix, pCtx->msrCSTAR,
3695 pszPrefix, pCtx->msrLSTAR,
3696 pszPrefix, pCtx->msrSFMASK,
3697 pszPrefix, pCtx->msrKERNELGSBASE);
3698
3699 if (CPUMIsGuestInPAEModeEx(pCtx))
3700 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3701 pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3702
3703 /*
3704 * MTRRs.
3705 */
3706 if (pVM->cpum.s.GuestFeatures.fMtrr)
3707 {
3708 pHlp->pfnPrintf(pHlp,
3709 "%sMTRR_CAP =%016RX64\n"
3710 "%sMTRR_DEF_TYPE =%016RX64\n"
3711 "%sMTRR_FIX64K_00000 =%016RX64\n"
3712 "%sMTRR_FIX16K_80000 =%016RX64\n"
3713 "%sMTRR_FIX16K_A0000 =%016RX64\n"
3714 "%sMTRR_FIX4K_C0000 =%016RX64\n"
3715 "%sMTRR_FIX4K_C8000 =%016RX64\n"
3716 "%sMTRR_FIX4K_D0000 =%016RX64\n"
3717 "%sMTRR_FIX4K_D8000 =%016RX64\n"
3718 "%sMTRR_FIX4K_E0000 =%016RX64\n"
3719 "%sMTRR_FIX4K_E8000 =%016RX64\n"
3720 "%sMTRR_FIX4K_F0000 =%016RX64\n"
3721 "%sMTRR_FIX4K_F8000 =%016RX64\n",
3722 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrCap,
3723 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType,
3724 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000,
3725 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000,
3726 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000,
3727 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000,
3728 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000,
3729 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000,
3730 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000,
3731 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000,
3732 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000,
3733 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000,
3734 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000);
3735
3736 for (uint8_t iRange = 0; iRange < RT_ELEMENTS(pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs); iRange++)
3737 {
3738 PCX86MTRRVAR pMtrrVar = &pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs[iRange];
3739 bool const fIsValid = RT_BOOL(pMtrrVar->MtrrPhysMask & MSR_IA32_MTRR_PHYSMASK_VALID);
3740 if (fIsValid)
3741 {
3742 RTGCPHYS GCPhysFirst;
3743 RTGCPHYS GCPhysLast;
3744 cpumR3GetVarMtrrAddrs(pVM, pMtrrVar, &GCPhysFirst, &GCPhysLast);
3745 uint8_t const fType = pMtrrVar->MtrrPhysBase & MSR_IA32_MTRR_PHYSBASE_MT_MASK;
3746 const char *pszType = cpumR3GetVarMtrrMemType(fType);
3747 uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
3748 pHlp->pfnPrintf(pHlp,
3749 "%sMTRR_PHYSBASE[%2u] =%016RX64 First=%016RX64 %6RU64 MB [%s]\n"
3750 "%sMTRR_PHYSMASK[%2u] =%016RX64 Last =%016RX64 %6RU64 MB [%RU64 MB]\n",
3751 pszPrefix, iRange, pMtrrVar->MtrrPhysBase, GCPhysFirst, GCPhysFirst / _1M, pszType,
3752 pszPrefix, iRange, pMtrrVar->MtrrPhysMask, GCPhysLast, GCPhysLast / _1M, cbRange / (uint64_t)_1M);
3753 }
3754 else
3755 pHlp->pfnPrintf(pHlp,
3756 "%sMTRR_PHYSBASE[%2u] =%016RX64\n"
3757 "%sMTRR_PHYSMASK[%2u] =%016RX64\n",
3758 pszPrefix, iRange, pMtrrVar->MtrrPhysBase,
3759 pszPrefix, iRange, pMtrrVar->MtrrPhysMask);
3760 }
3761 }
3762 break;
3763 }
3764}
3765
3766
3767/**
3768 * Displays an SVM VMCB control area.
3769 *
3770 * @param pHlp The info helper functions.
3771 * @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3772 * @param pszPrefix Caller specified string prefix.
3773 */
3774static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3775{
3776 AssertReturnVoid(pHlp);
3777 AssertReturnVoid(pVmcbCtrl);
3778
3779 pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3780 pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3781 pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3782 pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3783 pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3784 pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3785 pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3786 pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3787 pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3788 pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3789 pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3790 pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3791 pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3792 pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3793 pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3794 pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3795 pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3796 pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3797 pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3798 pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3799 pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3800 pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3801 pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3802 pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3803 pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3804 pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3805 pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3806 pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3807 pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3808 pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3809 pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3810 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3811 pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3812 pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3813 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3814 pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3815 pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3816 pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3817 pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3818 pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3819 pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3820 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3821 pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3822 pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3823 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3824 pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3825 pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3826 pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3827 pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3828 pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3829 pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3830 pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3831 pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3832 pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3833 pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3834 pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3835 pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3836 pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3837 pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3838 pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3839}
3840
3841
3842/**
3843 * Helper for dumping the SVM VMCB selector registers.
3844 *
3845 * @param pHlp The info helper functions.
3846 * @param pSel Pointer to the SVM selector register.
3847 * @param pszName Name of the selector.
3848 * @param pszPrefix Caller specified string prefix.
3849 */
3850DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char *pszName, const char *pszPrefix)
3851{
3852 /* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3853 pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3854 pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3855}
3856
3857
3858/**
3859 * Helper for dumping the SVM VMCB GDTR/IDTR registers.
3860 *
3861 * @param pHlp The info helper functions.
3862 * @param pXdtr Pointer to the descriptor table register.
3863 * @param pszName Name of the descriptor table register.
3864 * @param pszPrefix Caller specified string prefix.
3865 */
3866DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char *pszName, const char *pszPrefix)
3867{
3868 /* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3869 pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3870}
3871
3872
3873/**
3874 * Displays an SVM VMCB state-save area.
3875 *
3876 * @param pHlp The info helper functions.
3877 * @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3878 * @param pszPrefix Caller specified string prefix.
3879 */
3880static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3881{
3882 AssertReturnVoid(pHlp);
3883 AssertReturnVoid(pVmcbStateSave);
3884
3885 char szEFlags[80];
3886 cpumR3InfoFormatFlagsX86(&szEFlags[0], pVmcbStateSave->u64RFlags);
3887
3888 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3889 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3890 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3891 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3892 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3893 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3894 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3895 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3896 cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3897 cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3898 pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3899 pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3900 pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3901 pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3902 pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3903 pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3904 pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3905 pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3906 pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3907 pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3908 pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3909 pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3910 pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3911 pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3912 pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3913 pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3914 pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3915 pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3916 pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3917 pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3918 pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3919 pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3920 pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3921 pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3922 pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3923 pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3924}
3925
3926
3927/**
3928 * Displays a virtual-VMCS.
3929 *
3930 * @param pVCpu The cross context virtual CPU structure.
3931 * @param pHlp The info helper functions.
3932 * @param pVmcs Pointer to a virtual VMCS.
3933 * @param pszPrefix Caller specified string prefix.
3934 */
3935static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3936{
3937 AssertReturnVoid(pHlp);
3938 AssertReturnVoid(pVmcs);
3939
3940 /* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3941#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3942 do { \
3943 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3944 (a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3945 } while (0)
3946
3947#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3948 do { \
3949 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3950 (a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3951 } while (0)
3952
3953#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3954 do { \
3955 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3956 (a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3957 (a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3958 } while (0)
3959
3960#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3961 do { \
3962 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3963 (a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3964 } while (0)
3965
3966 /* Header. */
3967 {
3968 pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3969 pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3970 pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3971 pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3972 }
3973
3974 /* Control fields. */
3975 {
3976 /* 16-bit. */
3977 pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3978 pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3979 pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3980 pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3981 pHlp->pfnPrintf(pHlp, " %sHLAT prefix size = %#RX16\n", pszPrefix, pVmcs->u16HlatPrefixSize);
3982
3983 /* 32-bit. */
3984 pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3985 pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3986 pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3987 pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3988 pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3989 pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3990 pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3991 pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3992 pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3993 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3994 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3995 pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3996 pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3997 {
3998 uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3999 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
4000 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
4001 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
4002 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
4003 pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4004 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4005 }
4006 pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
4007 pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
4008 pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
4009 pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
4010 pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
4011
4012 /* 64-bit. */
4013 pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
4014 pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
4015 pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
4016 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
4017 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
4018 pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
4019 pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
4020 pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
4021 pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
4022 pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
4023 pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
4024 pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
4025 pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
4026 pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
4027 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
4028 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
4029 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
4030 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
4031 pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
4032 pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
4033 pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
4034 pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
4035 pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
4036 pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
4037 pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
4038 pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
4039 pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
4040 pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
4041 pHlp->pfnPrintf(pHlp, " %sPCONFIG-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64PconfigExitBitmap.u);
4042 pHlp->pfnPrintf(pHlp, " %sHLAT ptr = %#RX64\n", pszPrefix, pVmcs->u64HlatPtr.u);
4043 pHlp->pfnPrintf(pHlp, " %sSecondary VM-exit controls = %#RX64\n", pszPrefix, pVmcs->u64ExitCtls2.u);
4044
4045 /* Natural width. */
4046 pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
4047 pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
4048 pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
4049 pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
4050 pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
4051 pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
4052 pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
4053 pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
4054 }
4055
4056 /* Guest state. */
4057 {
4058 char szEFlags[80];
4059 cpumR3InfoFormatFlagsX86(&szEFlags[0], pVmcs->u64GuestRFlags.u);
4060 pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
4061
4062 /* 16-bit. */
4063 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
4064 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
4065 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
4066 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
4067 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
4068 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
4069 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
4070 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
4071 CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4072 CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4073 pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
4074 pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
4075
4076 /* 32-bit. */
4077 pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
4078 pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
4079 pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
4080 pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
4081 pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
4082
4083 /* 64-bit. */
4084 pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
4085 pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
4086 pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
4087 pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
4088 pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
4089 pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
4090 pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
4091 pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
4092 pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
4093 pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
4094 pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
4095 pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
4096
4097 /* Natural width. */
4098 pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
4099 pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
4100 pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
4101 pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
4102 pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
4103 pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
4104 pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
4105 pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
4106 pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
4107 pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
4108 pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
4109 pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
4110 pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
4111 }
4112
4113 /* Host state. */
4114 {
4115 pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
4116
4117 /* 16-bit. */
4118 pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
4119 pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
4120 pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
4121 pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
4122 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
4123 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
4124 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
4125 CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4126 CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4127
4128 /* 32-bit. */
4129 pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
4130
4131 /* 64-bit. */
4132 pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
4133 pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
4134 pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
4135 pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
4136
4137 /* Natural width. */
4138 pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
4139 pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
4140 pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
4141 pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
4142 pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
4143 pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
4144 pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
4145 pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
4146 pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
4147 pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
4148 }
4149
4150 /* Read-only fields. */
4151 {
4152 pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
4153
4154 /* 16-bit (none currently). */
4155
4156 /* 32-bit. */
4157 pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
4158 pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
4159 pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
4160 pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
4161 {
4162 uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
4163 uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
4164 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
4165 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
4166 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
4167 pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4168 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4169 }
4170 pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
4171 pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
4172 {
4173 uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
4174 uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
4175 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
4176 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
4177 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
4178 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
4179 }
4180 pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
4181 pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
4182 pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
4183
4184 /* 64-bit. */
4185 pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
4186
4187 /* Natural width. */
4188 pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
4189 pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
4190 pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
4191 pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
4192 pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
4193 }
4194
4195#ifdef DEBUG_ramshankar
4196 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4197 {
4198 void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
4199 Assert(pvPage);
4200 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4201 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
4202 if (RT_SUCCESS(rc))
4203 {
4204 pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
4205 pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
4206 pHlp->pfnPrintf(pHlp, "\n");
4207 }
4208 RTMemTmpFree(pvPage);
4209 }
4210#else
4211 NOREF(pVCpu);
4212#endif
4213
4214#undef CPUMVMX_DUMP_HOST_XDTR
4215#undef CPUMVMX_DUMP_HOST_FS_GS_TR
4216#undef CPUMVMX_DUMP_GUEST_SEGREG
4217#undef CPUMVMX_DUMP_GUEST_XDTR
4218}
4219
4220
4221/**
4222 * Display the guest's hardware-virtualization cpu state.
4223 *
4224 * @param pVM The cross context VM structure.
4225 * @param pHlp The info helper functions.
4226 * @param pszArgs Arguments, ignored.
4227 */
4228DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4229{
4230 RT_NOREF(pszArgs);
4231
4232 PVMCPU pVCpu = VMMGetCpu(pVM);
4233 if (!pVCpu)
4234 pVCpu = pVM->apCpusR3[0];
4235
4236 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4237 bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4238 bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4239
4240 pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4241 pHlp->pfnPrintf(pHlp, "fSavedInhibit = %#RX32\n", pCtx->hwvirt.fSavedInhibit);
4242 pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4243
4244 if (fSvm)
4245 {
4246 pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4247 pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4248
4249 char szEFlags[80];
4250 cpumR3InfoFormatFlagsX86(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4251 pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4252 pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4253 pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4254 cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4255 pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4256 cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4257 pHlp->pfnPrintf(pHlp, " HostState:\n");
4258 pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4259 pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4260 pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4261 pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4262 pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4263 pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4264 pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4265 pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4266 PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4267 pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4268 pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4269 PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4270 pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4271 pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4272 PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4273 pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4274 pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4275 PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4276 pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4277 pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4278 pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4279 pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4280 pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4281 pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4282 pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4283 pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4284 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4285 }
4286 else if (fVmx)
4287 {
4288 pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4289 pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4290 pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4291 pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4292 pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4293 pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4294 pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4295 pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4296 pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4297 pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4298 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4299 pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4300 pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4301 pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4302 pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4303 pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4304 pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4305 pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4306 cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4307 }
4308 else
4309 pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4310
4311#undef CPUMHWVIRTDUMP_NONE
4312#undef CPUMHWVIRTDUMP_COMMON
4313#undef CPUMHWVIRTDUMP_SVM
4314#undef CPUMHWVIRTDUMP_VMX
4315#undef CPUMHWVIRTDUMP_LAST
4316#undef CPUMHWVIRTDUMP_ALL
4317}
4318
4319
4320/**
4321 * Display the hypervisor cpu state.
4322 *
4323 * @param pVM The cross context VM structure.
4324 * @param pHlp The info helper functions.
4325 * @param pszArgs Arguments, ignored.
4326 */
4327DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4328{
4329 PVMCPU pVCpu = VMMGetCpu(pVM);
4330 if (!pVCpu)
4331 pVCpu = pVM->apCpusR3[0];
4332
4333 CPUMDUMPTYPE enmType;
4334 const char *pszComment;
4335 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4336 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4337
4338 pHlp->pfnPrintf(pHlp,
4339 ".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4340 ".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4341 pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4342 pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4343}
4344
4345
4346DECLHIDDEN(void) cpumR3LogCpuIdAndMsrFeaturesTarget(PVM pVM)
4347{
4348 /*
4349 * Log VT-x extended features.
4350 *
4351 * SVM features are currently all covered under CPUID so there is nothing
4352 * to do here for SVM.
4353 */
4354#ifdef RT_ARCH_AMD64
4355 if (pVM->cpum.s.GuestFeatures.fVmx || pVM->cpum.s.HostFeatures.s.fVmx)
4356#else
4357 if (pVM->cpum.s.GuestFeatures.fVmx)
4358#endif
4359 {
4360 LogRel(("*********************** VT-x features ***********************\n"));
4361 DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4362 LogRel(("\n******************* End of VT-x features ********************\n"));
4363 }
4364}
4365
4366
4367/**
4368 * Displays the host and guest VMX features.
4369 *
4370 * @param pVM The cross context VM structure.
4371 * @param pHlp The info helper functions.
4372 * @param pszArgs "terse", "default" or "verbose".
4373 */
4374static DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4375{
4376 RT_NOREF(pszArgs);
4377#ifdef RT_ARCH_AMD64
4378 PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures.s;
4379#else
4380 PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.GuestFeatures;
4381#endif
4382 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
4383 if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
4384 || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
4385 || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
4386 {
4387#ifdef RT_ARCH_AMD64
4388# define VMXFEATDUMP(a_szDesc, a_Var) \
4389 pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
4390#else
4391# define VMXFEATDUMP(a_szDesc, a_Var) \
4392 pHlp->pfnPrintf(pHlp, " %s = %u\n", a_szDesc, pGuestFeatures->a_Var)
4393#endif
4394
4395 pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
4396#ifdef RT_ARCH_AMD64
4397 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
4398#else
4399 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest\n");
4400#endif
4401 VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
4402 /* Basic. */
4403 VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
4404
4405 /* Pin-based controls. */
4406 VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
4407 VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
4408 VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
4409 VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
4410 VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
4411
4412 /* Processor-based controls. */
4413 VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
4414 VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
4415 VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
4416 VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
4417 VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
4418 VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
4419 VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
4420 VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
4421 VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
4422 VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
4423 VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
4424 VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
4425 VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
4426 VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
4427 VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
4428 VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
4429 VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
4430 VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
4431 VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
4432 VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
4433 VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
4434 VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
4435
4436 /* Secondary processor-based controls. */
4437 VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
4438 VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
4439 VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
4440 VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
4441 VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
4442 VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
4443 VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
4444 VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
4445 VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
4446 VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
4447 VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
4448 VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
4449 VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
4450 VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
4451 VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
4452 VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
4453 VMXFEATDUMP("PML - Page-Modification Log ", fVmxPml);
4454 VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
4455 VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
4456 VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
4457 VMXFEATDUMP("PasidTranslate - PASID translation ", fVmxPasidTranslate);
4458 VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
4459 VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
4460 VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
4461 VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
4462 VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
4463 VMXFEATDUMP("Pconfig - Enable PCONFIG ", fVmxPconfig);
4464 VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
4465 VMXFEATDUMP("BusLockDetect - VMM Bus-Lock detection ", fVmxBusLockDetect);
4466 VMXFEATDUMP("InstrTimeout - Instruction timeout ", fVmxInstrTimeout);
4467
4468 /* Tertiary processor-based controls. */
4469 VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
4470 VMXFEATDUMP("HLAT - Hypervisor-managed linear-address translation ", fVmxHlat);
4471 VMXFEATDUMP("EptPagingWrite - EPT paging-write ", fVmxEptPagingWrite);
4472 VMXFEATDUMP("GstPagingVerify - Guest-paging verification ", fVmxGstPagingVerify);
4473 VMXFEATDUMP("IpiVirt - IPI virtualization ", fVmxIpiVirt);
4474 VMXFEATDUMP("VirtSpecCtrl - Virtualize IA32_SPEC_CTRL ", fVmxVirtSpecCtrl);
4475
4476 /* VM-entry controls. */
4477 VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
4478 VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
4479 VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
4480 VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
4481
4482 /* VM-exit controls. */
4483 VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
4484 VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
4485 VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
4486 VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
4487 VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
4488 VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
4489 VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
4490 VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
4491 VMXFEATDUMP("SecondaryExitCtls - Secondary VM-exit controls ", fVmxSecondaryExitCtls);
4492
4493 /* Miscellaneous data. */
4494 VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
4495 VMXFEATDUMP("IntelPt - Intel Processor Trace in VMX operation ", fVmxPt);
4496 VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
4497 VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
4498#undef VMXFEATDUMP
4499 }
4500 else
4501 pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
4502}
4503
4504
4505/**
4506 * Marks the guest debug state as active.
4507 *
4508 * @param pVCpu The cross context virtual CPU structure.
4509 *
4510 * @note This is used solely by NEM (hence the name) to set the correct flags here
4511 * without loading the host's DRx registers, which is not possible from ring-3 anyway.
4512 * The specific NEM backends have to make sure to load the correct values.
4513 */
4514VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
4515{
4516 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
4517 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
4518}
4519
4520
4521/**
4522 * Marks the hyper debug state as active.
4523 *
4524 * @param pVCpu The cross context virtual CPU structure.
4525 *
4526 * @note This is used solely by NEM (hence the name) to set the correct flags here
4527 * without loading the host's DRx registers, which is not possible from ring-3 anyway.
4528 * The specific NEM backends have to make sure to load the correct values.
4529 */
4530VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
4531{
4532 /*
4533 * Make sure the hypervisor values are up to date.
4534 */
4535 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
4536
4537 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
4538 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
4539}
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