VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMRC/CPUMRC.cpp@ 45865

Last change on this file since 45865 was 45485, checked in by vboxsync, 12 years ago
  • *: Where possible, drop the #ifdef VBOX_WITH_RAW_RING1 when EMIsRawRing1Enabled is used.
  • SELM: Don't shadow TSS.esp1/ss1 unless ring-1 compression is enabled (also fixed a log statement there).
  • SELM: selmGuestToShadowDesc should not push ring-1 selectors into ring-2 unless EMIsRawRing1Enabled() holds true.
  • REM: Don't set CPU_INTERRUPT_EXTERNAL_EXIT in helper_ltr() for now.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 8.5 KB
Line 
1/* $Id: CPUMRC.cpp 45485 2013-04-11 14:46:04Z vboxsync $ */
2/** @file
3 * CPUM - Raw-mode Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/vmm.h>
25#include <VBox/vmm/patm.h>
26#include <VBox/vmm/trpm.h>
27#include <VBox/vmm/em.h>
28#include "CPUMInternal.h"
29#include <VBox/vmm/vm.h>
30#include <VBox/err.h>
31#include <iprt/assert.h>
32#include <VBox/log.h>
33
34
35/*******************************************************************************
36* Internal Functions *
37*******************************************************************************/
38RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
39DECLCALLBACK(int) cpumRCHandleNPAndGP(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
40RT_C_DECLS_END
41
42
43/**
44 * Deal with traps occurring during segment loading and IRET when resuming guest
45 * context execution.
46 *
47 * @returns VBox status code.
48 * @param pVM Pointer to the VM.
49 * @param pRegFrame The register frame.
50 * @param uUser User argument. In this case a combination of the
51 * CPUM_HANDLER_* \#defines.
52 */
53DECLCALLBACK(int) cpumRCHandleNPAndGP(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
54{
55 Log(("********************************************************\n"));
56 Log(("cpumRCHandleNPAndGP: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
57 Log(("********************************************************\n"));
58
59 /*
60 * Take action based on what's happened.
61 */
62 switch (uUser & CPUM_HANDLER_TYPEMASK)
63 {
64 case CPUM_HANDLER_GS:
65 case CPUM_HANDLER_DS:
66 case CPUM_HANDLER_ES:
67 case CPUM_HANDLER_FS:
68 TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_STALE_SELECTOR);
69 break;
70
71 case CPUM_HANDLER_IRET:
72 TRPMGCHyperReturnToHost(pVM, VINF_EM_RAW_IRET_TRAP);
73 break;
74 }
75
76 AssertMsgFailed(("uUser=%#x eip=%#x\n", uUser, pRegFrame->eip));
77 return VERR_TRPM_DONT_PANIC;
78}
79
80
81/**
82 * Called by TRPM and CPUM assembly code to make sure the guest state is
83 * ready for execution.
84 *
85 * @param pVM The VM handle.
86 */
87DECLASM(void) CPUMRCAssertPreExecutionSanity(PVM pVM)
88{
89 /*
90 * Check some important assumptions before resuming guest execution.
91 */
92 PVMCPU pVCpu = VMMGetCpu0(pVM);
93 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
94 uint8_t const uRawCpl = CPUMGetGuestCPL(pVCpu);
95 uint32_t const u32EFlags = CPUMRawGetEFlags(pVCpu);
96 bool const fPatch = PATMIsPatchGCAddr(pVM, pCtx->eip);
97 AssertMsg(pCtx->eflags.Bits.u1IF, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
98 AssertMsg(pCtx->eflags.Bits.u2IOPL < RT_MAX(uRawCpl, 1U),
99 ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
100 if (!(u32EFlags & X86_EFL_VM))
101 {
102 AssertMsg((u32EFlags & X86_EFL_IF) || fPatch,("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
103 AssertMsg((pCtx->cs.Sel & X86_SEL_RPL) > 0, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
104 AssertMsg((pCtx->ss.Sel & X86_SEL_RPL) > 0, ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
105 }
106 AssertMsg(CPUMIsGuestInRawMode(pVCpu), ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
107 //Log2(("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
108}
109
110
111/**
112 * Get the current privilege level of the guest.
113 *
114 * @returns CPL
115 * @param pVCpu The current virtual CPU.
116 * @param pRegFrame Pointer to the register frame.
117 *
118 * @todo r=bird: This is very similar to CPUMGetGuestCPL and I cannot quite
119 * see why this variant of the code is necessary.
120 */
121VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
122{
123 /*
124 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
125 *
126 * Note! We used to check CS.DPL here, assuming it was always equal to
127 * CPL even if a conforming segment was loaded. But this truned out to
128 * only apply to older AMD-V. With VT-x we had an ACP2 regression
129 * during install after a far call to ring 2 with VT-x. Then on newer
130 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
131 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
132 *
133 * So, forget CS.DPL, always use SS.DPL.
134 *
135 * Note! The SS RPL is always equal to the CPL, while the CS RPL
136 * isn't necessarily equal if the segment is conforming.
137 * See section 4.11.1 in the AMD manual.
138 */
139 uint32_t uCpl;
140 if (!pRegFrame->eflags.Bits.u1VM)
141 {
142 uCpl = (pRegFrame->ss.Sel & X86_SEL_RPL);
143#ifdef VBOX_WITH_RAW_MODE_NOT_R0
144# ifdef VBOX_WITH_RAW_RING1
145 if (pVCpu->cpum.s.fRawEntered)
146 {
147 if ( uCpl == 2
148 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)) )
149 uCpl = 1;
150 else if (uCpl == 1)
151 uCpl = 0;
152 }
153 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
154# else
155 if (uCpl == 1)
156 uCpl = 0;
157# endif
158#endif
159 }
160 else
161 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
162
163 return uCpl;
164}
165
166
167#ifdef VBOX_WITH_RAW_RING1
168/**
169 * Transforms the guest CPU state to raw-ring mode.
170 *
171 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
172 *
173 * Used by emInterpretIret() after the new state has been loaded.
174 *
175 * @param pVCpu Pointer to the VMCPU.
176 * @param pCtxCore The context core (for trap usage).
177 * @see @ref pg_raw
178 * @remarks Will be probably obsoleted by #5653 (it will leave and reenter raw
179 * mode instead, I think).
180 */
181VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
182{
183 /*
184 * Are we in Ring-0?
185 */
186 if ( pCtxCore->ss.Sel
187 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
188 && !pCtxCore->eflags.Bits.u1VM)
189 {
190 /*
191 * Set CPL to Ring-1.
192 */
193 pCtxCore->ss.Sel |= 1;
194 if ( pCtxCore->cs.Sel
195 && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
196 pCtxCore->cs.Sel |= 1;
197 }
198 else
199 {
200 if ( EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM))
201 && !pCtxCore->eflags.Bits.u1VM
202 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
203 {
204 /* Set CPL to Ring-2. */
205 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
206 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
207 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
208 }
209 }
210
211 /*
212 * Assert sanity.
213 */
214 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
215 AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
216 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
217
218 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
219}
220#endif /* VBOX_WITH_RAW_RING1 */
221
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette