CPUMRCA.asm@ 41931

Last change on this file since 41931 was 41931, checked in by vboxsync, 13 years ago
TRPM: Save state directly to the CPUMCPU context member instead of putting on the stack. this avoid copying the state around before returning to host context to service an IRQ, or before using IEM.
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1	; $Id: CPUMRCA.asm 41931 2012-06-27 16:12:16Z vboxsync $
2	;; @file
3	; CPUM - Guest Context Assembly Routines.
4	;
5
6	; Copyright (C) 2006-2007 Oracle Corporation
7	;
8	; This file is part of VirtualBox Open Source Edition (OSE), as
9	; available from http://www.virtualbox.org. This file is free software;
10	; you can redistribute it and/or modify it under the terms of the GNU
11	; General Public License (GPL) as published by the Free Software
12	; Foundation, in version 2 as it comes in the "COPYING" file of the
13	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	;
16
17	;*******************************************************************************
18	;* Header Files *
19	;*******************************************************************************
20	%include "VMMRC.mac"
21	%include "VBox/vmm/vm.mac"
22	%include "VBox/err.mac"
23	%include "VBox/vmm/stam.mac"
24	%include "CPUMInternal.mac"
25	%include "iprt/x86.mac"
26	%include "VBox/vmm/cpum.mac"
27
28
29	;*******************************************************************************
30	;* External Symbols *
31	;*******************************************************************************
32	extern IMPNAME(g_CPUM) ; VMM GC Builtin import
33	extern IMPNAME(g_VM) ; VMM GC Builtin import
34	extern NAME(cpumGCHandleNPAndGP) ; CPUMGC.cpp
35
36	;
37	; Enables write protection of Hypervisor memory pages.
38	; !note! Must be commented out for Trap8 debug handler.
39	;
40	%define ENABLE_WRITE_PROTECTION 1
41
42	BEGINCODE
43
44
45	;;
46	; Calls a guest trap/interrupt handler directly
47	; Assumes a trap stack frame has already been setup on the guest's stack!
48	;
49	; @param pRegFrame [esp + 4] Original trap/interrupt context
50	; @param selCS [esp + 8] Code selector of handler
51	; @param pHandler [esp + 12] GC virtual address of handler
52	; @param eflags [esp + 16] Callee's EFLAGS
53	; @param selSS [esp + 20] Stack selector for handler
54	; @param pEsp [esp + 24] Stack address for handler
55	;
56	; @remark This call never returns!
57	;
58	; VMMRCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
59	align 16
60	BEGINPROC_EXPORTED CPUMGCCallGuestTrapHandler
61	mov ebp, esp
62
63	; construct iret stack frame
64	push dword [ebp + 20] ; SS
65	push dword [ebp + 24] ; ESP
66	push dword [ebp + 16] ; EFLAGS
67	push dword [ebp + 8] ; CS
68	push dword [ebp + 12] ; EIP
69
70	;
71	; enable WP
72	;
73	%ifdef ENABLE_WRITE_PROTECTION
74	mov eax, cr0
75	or eax, X86_CR0_WRITE_PROTECT
76	mov cr0, eax
77	%endif
78
79	; restore CPU context (all except cs, eip, ss, esp & eflags; which are restored or overwritten by iret)
80	mov ebp, [ebp + 4] ; pRegFrame
81	mov ebx, [ebp + CPUMCTXCORE.ebx]
82	mov ecx, [ebp + CPUMCTXCORE.ecx]
83	mov edx, [ebp + CPUMCTXCORE.edx]
84	mov esi, [ebp + CPUMCTXCORE.esi]
85	mov edi, [ebp + CPUMCTXCORE.edi]
86
87	;; @todo load segment registers before enabling WP.
88	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS \| CPUM_HANDLER_CTXCORE_IN_EBP
89	mov gs, [ebp + CPUMCTXCORE.gs.Sel]
90	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS \| CPUM_HANDLER_CTXCORE_IN_EBP
91	mov fs, [ebp + CPUMCTXCORE.fs.Sel]
92	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES \| CPUM_HANDLER_CTXCORE_IN_EBP
93	mov es, [ebp + CPUMCTXCORE.es.Sel]
94	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS \| CPUM_HANDLER_CTXCORE_IN_EBP
95	mov ds, [ebp + CPUMCTXCORE.ds.Sel]
96
97	mov eax, [ebp + CPUMCTXCORE.eax]
98	mov ebp, [ebp + CPUMCTXCORE.ebp]
99
100	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
101	iret
102	ENDPROC CPUMGCCallGuestTrapHandler
103
104
105	;;
106	; Performs an iret to V86 code
107	; Assumes a trap stack frame has already been setup on the guest's stack!
108	;
109	; @param pRegFrame Original trap/interrupt context
110	;
111	; This function does not return!
112	;
113	;VMMRCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
114	align 16
115	BEGINPROC CPUMGCCallV86Code
116	mov ebp, [esp + 4] ; pRegFrame
117
118	; construct iret stack frame
119	push dword [ebp + CPUMCTXCORE.gs.Sel]
120	push dword [ebp + CPUMCTXCORE.fs.Sel]
121	push dword [ebp + CPUMCTXCORE.ds.Sel]
122	push dword [ebp + CPUMCTXCORE.es.Sel]
123	push dword [ebp + CPUMCTXCORE.ss.Sel]
124	push dword [ebp + CPUMCTXCORE.esp]
125	push dword [ebp + CPUMCTXCORE.eflags]
126	push dword [ebp + CPUMCTXCORE.cs.Sel]
127	push dword [ebp + CPUMCTXCORE.eip]
128
129	;
130	; enable WP
131	;
132	%ifdef ENABLE_WRITE_PROTECTION
133	mov eax, cr0
134	or eax, X86_CR0_WRITE_PROTECT
135	mov cr0, eax
136	%endif
137
138	; restore CPU context (all except cs, eip, ss, esp, eflags, ds, es, fs & gs; which are restored or overwritten by iret)
139	mov eax, [ebp + CPUMCTXCORE.eax]
140	mov ebx, [ebp + CPUMCTXCORE.ebx]
141	mov ecx, [ebp + CPUMCTXCORE.ecx]
142	mov edx, [ebp + CPUMCTXCORE.edx]
143	mov esi, [ebp + CPUMCTXCORE.esi]
144	mov edi, [ebp + CPUMCTXCORE.edi]
145	mov ebp, [ebp + CPUMCTXCORE.ebp]
146
147	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
148	iret
149	ENDPROC CPUMGCCallV86Code
150
151
152	;;
153	; This is a main entry point for resuming (or starting) guest
154	; code execution.
155	;
156	; We get here directly from VMMSwitcher.asm (jmp at the end
157	; of VMMSwitcher_HostToGuest).
158	;
159	; This call never returns!
160	;
161	; @param edx Pointer to CPUM structure.
162	;
163	align 16
164	BEGINPROC_EXPORTED CPUMGCResumeGuest
165	; Convert to CPUMCPU pointer
166	add edx, [edx + CPUM.offCPUMCPU0]
167	;
168	; Setup iretd
169	;
170	push dword [edx + CPUMCPU.Guest.ss.Sel]
171	push dword [edx + CPUMCPU.Guest.esp]
172	push dword [edx + CPUMCPU.Guest.eflags]
173	push dword [edx + CPUMCPU.Guest.cs.Sel]
174	push dword [edx + CPUMCPU.Guest.eip]
175
176	;
177	; Restore registers.
178	;
179	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES
180	mov es, [edx + CPUMCPU.Guest.es.Sel]
181	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS
182	mov fs, [edx + CPUMCPU.Guest.fs.Sel]
183	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS
184	mov gs, [edx + CPUMCPU.Guest.gs.Sel]
185
186	%ifdef VBOX_WITH_STATISTICS
187	;
188	; Statistics.
189	;
190	push edx
191	mov edx, IMP(g_VM)
192	lea edx, [edx + VM.StatTotalQemuToGC]
193	STAM_PROFILE_ADV_STOP edx
194
195	mov edx, IMP(g_VM)
196	lea edx, [edx + VM.StatTotalInGC]
197	STAM_PROFILE_ADV_START edx
198	pop edx
199	%endif
200
201	;
202	; enable WP
203	;
204	%ifdef ENABLE_WRITE_PROTECTION
205	mov eax, cr0
206	or eax, X86_CR0_WRITE_PROTECT
207	mov cr0, eax
208	%endif
209
210	;
211	; Continue restore.
212	;
213	mov esi, [edx + CPUMCPU.Guest.esi]
214	mov edi, [edx + CPUMCPU.Guest.edi]
215	mov ebp, [edx + CPUMCPU.Guest.ebp]
216	mov ebx, [edx + CPUMCPU.Guest.ebx]
217	mov ecx, [edx + CPUMCPU.Guest.ecx]
218	mov eax, [edx + CPUMCPU.Guest.eax]
219	push dword [edx + CPUMCPU.Guest.ds.Sel]
220	mov edx, [edx + CPUMCPU.Guest.edx]
221	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS
222	pop ds
223
224	; restart execution.
225	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
226	iretd
227	ENDPROC CPUMGCResumeGuest
228
229
230	;;
231	; This is a main entry point for resuming (or starting) guest
232	; code execution for raw V86 mode
233	;
234	; We get here directly from VMMSwitcher.asm (jmp at the end
235	; of VMMSwitcher_HostToGuest).
236	;
237	; This call never returns!
238	;
239	; @param edx Pointer to CPUM structure.
240	;
241	align 16
242	BEGINPROC_EXPORTED CPUMGCResumeGuestV86
243	; Convert to CPUMCPU pointer
244	add edx, [edx + CPUM.offCPUMCPU0]
245	;
246	; Setup iretd
247	;
248	push dword [edx + CPUMCPU.Guest.gs.Sel]
249	push dword [edx + CPUMCPU.Guest.fs.Sel]
250	push dword [edx + CPUMCPU.Guest.ds.Sel]
251	push dword [edx + CPUMCPU.Guest.es.Sel]
252
253	push dword [edx + CPUMCPU.Guest.ss.Sel]
254	push dword [edx + CPUMCPU.Guest.esp]
255
256	push dword [edx + CPUMCPU.Guest.eflags]
257	push dword [edx + CPUMCPU.Guest.cs.Sel]
258	push dword [edx + CPUMCPU.Guest.eip]
259
260	;
261	; Restore registers.
262	;
263
264	%ifdef VBOX_WITH_STATISTICS
265	;
266	; Statistics.
267	;
268	push edx
269	mov edx, IMP(g_VM)
270	lea edx, [edx + VM.StatTotalQemuToGC]
271	STAM_PROFILE_ADV_STOP edx
272
273	mov edx, IMP(g_VM)
274	lea edx, [edx + VM.StatTotalInGC]
275	STAM_PROFILE_ADV_START edx
276	pop edx
277	%endif
278
279	;
280	; enable WP
281	;
282	%ifdef ENABLE_WRITE_PROTECTION
283	mov eax, cr0
284	or eax, X86_CR0_WRITE_PROTECT
285	mov cr0, eax
286	%endif
287
288	;
289	; Continue restore.
290	;
291	mov esi, [edx + CPUMCPU.Guest.esi]
292	mov edi, [edx + CPUMCPU.Guest.edi]
293	mov ebp, [edx + CPUMCPU.Guest.ebp]
294	mov ecx, [edx + CPUMCPU.Guest.ecx]
295	mov ebx, [edx + CPUMCPU.Guest.ebx]
296	mov eax, [edx + CPUMCPU.Guest.eax]
297	mov edx, [edx + CPUMCPU.Guest.edx]
298
299	; restart execution.
300	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
301	iretd
302	ENDPROC CPUMGCResumeGuestV86
303

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source: vbox/trunk/src/VBox/VMM/VMMRC/CPUMRCA.asm@ 41931

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