TRPMRCHandlers.cpp@ 39723

Last change on this file since 39723 was 39402, checked in by vboxsync, 13 years ago
VMM: don't use generic IPE status codes, use specific ones. Part 1.
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1	/* $Id: TRPMRCHandlers.cpp 39402 2011-11-23 16:25:04Z vboxsync $ */
2	/** @file
3	* TRPM - Guest Context Trap Handlers, CPP part
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_TRPM
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/iom.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/em.h>
29	#include <VBox/vmm/csam.h>
30	#include <VBox/vmm/patm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/cpum.h>
33	#include "TRPMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/vmm.h>
36	#include <VBox/param.h>
37
38	#include <VBox/err.h>
39	#include <VBox/dis.h>
40	#include <VBox/disopcode.h>
41	#include <VBox/log.h>
42	#include <VBox/vmm/tm.h>
43	#include <iprt/asm.h>
44	#include <iprt/asm-amd64-x86.h>
45	#include <iprt/assert.h>
46	#include <iprt/x86.h>
47
48
49	/*******************************************************************************
50	* Defined Constants And Macros *
51	*******************************************************************************/
52	/* still here. MODR/M byte parsing */
53	#define X86_OPCODE_MODRM_MOD_MASK 0xc0
54	#define X86_OPCODE_MODRM_REG_MASK 0x38
55	#define X86_OPCODE_MODRM_RM_MASK 0x07
56
57	/** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
58	#define DTRACE_EXPERIMENT
59
60
61	/*******************************************************************************
62	* Structures and Typedefs *
63	*******************************************************************************/
64	/** Pointer to a readonly hypervisor trap record. */
65	typedef const struct TRPMGCHYPER *PCTRPMGCHYPER;
66
67	/**
68	* A hypervisor trap record.
69	* This contains information about a handler for a instruction range.
70	*
71	* @remark This must match what TRPM_HANDLER outputs.
72	*/
73	typedef struct TRPMGCHYPER
74	{
75	/** The start address. */
76	uintptr_t uStartEIP;
77	/** The end address. (exclusive)
78	* If NULL the it's only for the instruction at pvStartEIP. */
79	uintptr_t uEndEIP;
80	/**
81	* The handler.
82	*
83	* @returns VBox status code
84	* VINF_SUCCESS means we've handled the trap.
85	* Any other error code means returning to the host context.
86	* @param pVM The VM handle.
87	* @param pRegFrame The register frame.
88	* @param uUser The user argument.
89	*/
90	DECLRCCALLBACKMEMBER(int, pfnHandler, (PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser));
91	/** Whatever the handler desires to put here. */
92	uintptr_t uUser;
93	} TRPMGCHYPER;
94
95
96	/*******************************************************************************
97	* Global Variables *
98	*******************************************************************************/
99	RT_C_DECLS_BEGIN
100	/** Defined in VMMGC0.asm or VMMGC99.asm.
101	* @{ */
102	extern const TRPMGCHYPER g_aTrap0bHandlers[1];
103	extern const TRPMGCHYPER g_aTrap0bHandlersEnd[1];
104	extern const TRPMGCHYPER g_aTrap0dHandlers[1];
105	extern const TRPMGCHYPER g_aTrap0dHandlersEnd[1];
106	extern const TRPMGCHYPER g_aTrap0eHandlers[1];
107	extern const TRPMGCHYPER g_aTrap0eHandlersEnd[1];
108	/** @} */
109	RT_C_DECLS_END
110
111
112	/*******************************************************************************
113	* Internal Functions *
114	*******************************************************************************/
115	RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
116	DECLCALLBACK(int) trpmGCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
117	RT_C_DECLS_END
118
119
120
121	/**
122	* Exits the trap, called when exiting a trap handler.
123	*
124	* Will reset the trap if it's not a guest trap or the trap
125	* is already handled. Will process resume guest FFs.
126	*
127	* @returns rc, can be adjusted if its VINF_SUCCESS or something really bad
128	* happened.
129	* @param pVM VM handle.
130	* @param pVCpu The virtual CPU handle.
131	* @param rc The VBox status code to return.
132	* @param pRegFrame Pointer to the register frame for the trap.
133	*
134	* @remarks This must not be used for hypervisor traps, only guest traps.
135	*/
136	static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame)
137	{
138	uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
139	NOREF(uOldActiveVector);
140
141	/* Reset trap? */
142	if ( rc != VINF_EM_RAW_GUEST_TRAP
143	&& rc != VINF_EM_RAW_RING_SWITCH_INT)
144	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
145
146	#ifdef VBOX_HIGH_RES_TIMERS_HACK
147	/*
148	* We should poll the timers occasionally.
149	* We must NOT do this too frequently as it adds a significant overhead
150	* and it'll kill us if the trap load is high. (See #1354.)
151	* (The heuristic is not very intelligent, we should really check trap
152	* frequency etc. here, but alas, we lack any such information atm.)
153	*/
154	static unsigned s_iTimerPoll = 0;
155	if (rc == VINF_SUCCESS)
156	{
157	if (!(++s_iTimerPoll & 0xf))
158	{
159	TMTimerPollVoid(pVM, pVCpu);
160	Log2(("TMTimerPoll at %08RX32 - VM_FF_TM_VIRTUAL_SYNC=%d VM_FF_TM_VIRTUAL_SYNC=%d\n", pRegFrame->eip,
161	VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)));
162	}
163	}
164	else
165	s_iTimerPoll = 0;
166	#endif
167
168	/* Clear pending inhibit interrupt state if required. (necessary for dispatching interrupts later on) */
169	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
170	{
171	Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
172	if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVCpu))
173	{
174	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
175	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
176	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
177	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
178	*/
179	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
180	}
181	}
182
183	/*
184	* Pending resume-guest-FF?
185	* Or pending (A)PIC interrupt? Windows XP will crash if we delay APIC interrupts.
186	*/
187	if ( rc == VINF_SUCCESS
188	&& ( VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC \| VM_FF_REQUEST \| VM_FF_PGM_NO_MEMORY \| VM_FF_PDM_DMA)
189	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_TO_R3 \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
190	\| VMCPU_FF_REQUEST \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
191	\| VMCPU_FF_PDM_CRITSECT)
192	)
193	)
194	{
195	/* The out of memory condition naturally outranks the others. */
196	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
197	rc = VINF_EM_NO_MEMORY;
198	/* Pending Ring-3 action. */
199	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TO_R3 \| VMCPU_FF_PDM_CRITSECT))
200	{
201	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
202	rc = VINF_EM_RAW_TO_R3;
203	}
204	/* Pending timer action. */
205	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER))
206	rc = VINF_EM_RAW_TIMER_PENDING;
207	/* The Virtual Sync clock has stopped. */
208	else if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
209	rc = VINF_EM_RAW_TO_R3;
210	/* DMA work pending? */
211	else if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA))
212	rc = VINF_EM_RAW_TO_R3;
213	/* Pending request packets might contain actions that need immediate
214	attention, such as pending hardware interrupts. */
215	else if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
216	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
217	rc = VINF_EM_PENDING_REQUEST;
218	/* Pending interrupt: dispatch it. */
219	else if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
220	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
221	&& PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame)
222	)
223	{
224	uint8_t u8Interrupt;
225	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
226	Log(("trpmGCExitTrap: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
227	AssertFatalMsgRC(rc, ("PDMGetInterrupt failed with %Rrc\n", rc));
228	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_HARDWARE_INT, uOldActiveVector);
229	/* can't return if successful */
230	Assert(rc != VINF_SUCCESS);
231
232	/* Stop the profile counter that was started in TRPMGCHandlersA.asm */
233	Assert(uOldActiveVector <= 16);
234	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
235
236	/* Assert the trap and go to the recompiler to dispatch it. */
237	TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
238
239	STAM_PROFILE_ADV_START(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
240	rc = VINF_EM_RAW_INTERRUPT_PENDING;
241	}
242	/*
243	* Try sync CR3?
244	*/
245	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
246	{
247	#if 1
248	PGMRZDynMapReleaseAutoSet(pVCpu);
249	PGMRZDynMapStartAutoSet(pVCpu);
250	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
251	#else
252	rc = VINF_PGM_SYNC_CR3;
253	#endif
254	}
255	}
256
257	AssertMsg( rc != VINF_SUCCESS
258	\|\| ( pRegFrame->eflags.Bits.u1IF
259	&& ( pRegFrame->eflags.Bits.u2IOPL < (unsigned)(pRegFrame->ss & X86_SEL_RPL) \|\| pRegFrame->eflags.Bits.u1VM))
260	, ("rc=%Rrc\neflags=%RX32 ss=%RTsel IOPL=%d\n", rc, pRegFrame->eflags.u32, pRegFrame->ss, pRegFrame->eflags.Bits.u2IOPL));
261	PGMRZDynMapReleaseAutoSet(pVCpu);
262	return rc;
263	}
264
265
266	/**
267	* \#DB (Debug event) handler.
268	*
269	* @returns VBox status code.
270	* VINF_SUCCESS means we completely handled this trap,
271	* other codes are passed execution to host context.
272	*
273	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
274	* @param pRegFrame Pointer to the register frame for the trap.
275	* @internal
276	*/
277	DECLASM(int) TRPMGCTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
278	{
279	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
280	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
281	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
282
283	LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
284
285	/*
286	* We currently don't make use of the X86_DR7_GD bit, but
287	* there might come a time when we do.
288	*/
289	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
290	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
291	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
292	VERR_NOT_IMPLEMENTED);
293	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
294
295	/*
296	* Now leave the rest to the DBGF.
297	*/
298	PGMRZDynMapStartAutoSet(pVCpu);
299	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6);
300	if (rc == VINF_EM_RAW_GUEST_TRAP)
301	CPUMSetGuestDR6(pVCpu, uDr6);
302
303	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
304	Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs, pRegFrame->eip, uDr6));
305	return rc;
306	}
307
308
309	/**
310	* \#DB (Debug event) handler for the hypervisor code.
311	*
312	* This is mostly the same as TRPMGCTrap01Handler, but we skip the PGM auto
313	* mapping set as well as the default trap exit path since they are both really
314	* bad ideas in this context.
315	*
316	* @returns VBox status code.
317	* VINF_SUCCESS means we completely handled this trap,
318	* other codes are passed execution to host context.
319	*
320	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
321	* @param pRegFrame Pointer to the register frame for the trap.
322	* @internal
323	*/
324	DECLASM(int) TRPMGCHyperTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
325	{
326	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
327	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
328	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
329
330	LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
331
332	/*
333	* We currently don't make use of the X86_DR7_GD bit, but
334	* there might come a time when we do.
335	*/
336	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
337	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
338	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
339	VERR_NOT_IMPLEMENTED);
340	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
341
342	/*
343	* Now leave the rest to the DBGF.
344	*/
345	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6);
346	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_1);
347
348	Log6(("TRPMGCHyper01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs, pRegFrame->eip, uDr6));
349	return rc;
350	}
351
352
353	/**
354	* NMI handler, for when we are using NMIs to debug things.
355	*
356	* @returns VBox status code.
357	* VINF_SUCCESS means we completely handled this trap,
358	* other codes are passed execution to host context.
359	*
360	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
361	* @param pRegFrame Pointer to the register frame for the trap.
362	* @internal
363	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
364	*/
365	DECLASM(int) TRPMGCTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
366	{
367	LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
368	RTLogComPrintf("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip);
369	NOREF(pTrpmCpu);
370	return VERR_TRPM_DONT_PANIC;
371	}
372
373
374	/**
375	* NMI handler, for when we are using NMIs to debug things.
376	*
377	* This is the handler we're most likely to hit when the NMI fires (it is
378	* unlikely that we'll be stuck in guest code).
379	*
380	* @returns VBox status code.
381	* VINF_SUCCESS means we completely handled this trap,
382	* other codes are passed execution to host context.
383	*
384	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
385	* @param pRegFrame Pointer to the register frame for the trap.
386	* @internal
387	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
388	*/
389	DECLASM(int) TRPMGCHyperTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
390	{
391	LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
392	RTLogComPrintf("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip);
393	NOREF(pTrpmCpu);
394	return VERR_TRPM_DONT_PANIC;
395	}
396
397
398	/**
399	* \#BP (Breakpoint) handler.
400	*
401	* @returns VBox status code.
402	* VINF_SUCCESS means we completely handled this trap,
403	* other codes are passed execution to host context.
404	*
405	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
406	* @param pRegFrame Pointer to the register frame for the trap.
407	* @internal
408	*/
409	DECLASM(int) TRPMGCTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
410	{
411	LogFlow(("TRPMGC03: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
412	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
413	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
414	int rc;
415	PGMRZDynMapStartAutoSet(pVCpu);
416
417	/*
418	* PATM is using INT3s, let them have a go first.
419	*/
420	if ( (pRegFrame->ss & X86_SEL_RPL) == 1
421	&& !pRegFrame->eflags.Bits.u1VM)
422	{
423	rc = PATMHandleInt3PatchTrap(pVM, pRegFrame);
424	if (rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PATM_PATCH_INT3 \|\| rc == VINF_PATM_DUPLICATE_FUNCTION)
425	{
426	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
427	Log6(("TRPMGC03: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs, pRegFrame->eip));
428	return rc;
429	}
430	}
431	rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
432
433	/* anything we should do with this? Schedule it in GC? */
434	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
435	Log6(("TRPMGC03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
436	return rc;
437	}
438
439
440	/**
441	* \#BP (Breakpoint) handler.
442	*
443	* This is similar to TRPMGCTrap03Handler but we bits which are potentially
444	* harmful to us (common trap exit and the auto mapping set).
445	*
446	* @returns VBox status code.
447	* VINF_SUCCESS means we completely handled this trap,
448	* other codes are passed execution to host context.
449	*
450	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
451	* @param pRegFrame Pointer to the register frame for the trap.
452	* @internal
453	*/
454	DECLASM(int) TRPMGCHyperTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
455	{
456	LogFlow(("TRPMGCHyper03: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
457	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
458	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
459
460	/*
461	* Hand it over to DBGF.
462	*/
463	int rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
464	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_2);
465
466	Log6(("TRPMGCHyper03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
467	return rc;
468	}
469
470
471	/**
472	* Trap handler for illegal opcode fault (\#UD).
473	*
474	* @returns VBox status code.
475	* VINF_SUCCESS means we completely handled this trap,
476	* other codes are passed execution to host context.
477	*
478	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
479	* @param pRegFrame Pointer to the register frame for the trap.
480	* @internal
481	*/
482	DECLASM(int) TRPMGCTrap06Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
483	{
484	LogFlow(("TRPMGC06: %04x:%08x efl=%x\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->eflags.u32));
485	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
486	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
487	int rc;
488	PGMRZDynMapStartAutoSet(pVCpu);
489
490	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
491	{
492	/*
493	* Decode the instruction.
494	*/
495	RTGCPTR PC;
496	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
497	(RTGCPTR)pRegFrame->eip, &PC);
498	if (RT_FAILURE(rc))
499	{
500	Log(("TRPMGCTrap06Handler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->ss & X86_SEL_RPL, rc));
501	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
502	Log6(("TRPMGC06: %Rrc (%04x:%08x) (SELM)\n", rc, pRegFrame->cs, pRegFrame->eip));
503	return rc;
504	}
505
506	DISCPUSTATE Cpu;
507	uint32_t cbOp;
508	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
509	if (RT_FAILURE(rc))
510	{
511	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
512	Log6(("TRPMGC06: %Rrc (%04x:%08x) (EM)\n", rc, pRegFrame->cs, pRegFrame->eip));
513	return rc;
514	}
515
516	/*
517	* UD2 in a patch?
518	* Note! PATMGCHandleIllegalInstrTrap doesn't always return.
519	*/
520	if ( Cpu.pCurInstr->opcode == OP_ILLUD2
521	&& PATMIsPatchGCAddr(pVM, pRegFrame->eip))
522	{
523	LogFlow(("TRPMGCTrap06Handler: -> PATMGCHandleIllegalInstrTrap\n"));
524	rc = PATMGCHandleIllegalInstrTrap(pVM, pRegFrame);
525	/** @todo These tests are completely unnecessary, should just follow the
526	* flow and return at the end of the function. */
527	if ( rc == VINF_SUCCESS
528	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
529	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION
530	\|\| rc == VINF_PATM_PENDING_IRQ_AFTER_IRET
531	\|\| rc == VINF_EM_RESCHEDULE)
532	{
533	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
534	Log6(("TRPMGC06: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs, pRegFrame->eip));
535	return rc;
536	}
537	}
538	/*
539	* Speed up dtrace and don't entrust invalid lock sequences to the recompiler.
540	*/
541	else if (Cpu.prefix & PREFIX_LOCK)
542	{
543	Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->opcode));
544	#ifdef DTRACE_EXPERIMENT /** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
545	Assert(!PATMIsPatchGCAddr(pVM, pRegFrame->eip));
546	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0x6, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, 0x6);
547	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
548	#else
549	rc = VINF_EM_RAW_EMULATE_INSTR;
550	#endif
551	}
552	/*
553	* Handle MONITOR - it causes an #UD exception instead of #GP when not executed in ring 0.
554	*/
555	else if (Cpu.pCurInstr->opcode == OP_MONITOR)
556	{
557	LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n"));
558	uint32_t cbIgnored;
559	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored);
560	if (RT_SUCCESS(rc))
561	pRegFrame->eip += Cpu.opsize;
562	}
563	/* Never generate a raw trap here; it might be an instruction, that requires emulation. */
564	else
565	{
566	LogFlow(("TRPMGCTrap06Handler: -> VINF_EM_RAW_EMULATE_INSTR\n"));
567	rc = VINF_EM_RAW_EMULATE_INSTR;
568	}
569	}
570	else
571	{
572	LogFlow(("TRPMGCTrap06Handler: -> TRPMForwardTrap\n"));
573	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0x6, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, 0x6);
574	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
575	}
576
577	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
578	Log6(("TRPMGC06: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
579	return rc;
580	}
581
582
583	/**
584	* Trap handler for device not present fault (\#NM).
585	*
586	* Device not available, FP or (F)WAIT instruction.
587	*
588	* @returns VBox status code.
589	* VINF_SUCCESS means we completely handled this trap,
590	* other codes are passed execution to host context.
591	*
592	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
593	* @param pRegFrame Pointer to the register frame for the trap.
594	* @internal
595	*/
596	DECLASM(int) TRPMGCTrap07Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
597	{
598	LogFlow(("TRPMGC07: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
599	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
600	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
601	PGMRZDynMapStartAutoSet(pVCpu);
602
603	int rc = CPUMHandleLazyFPU(pVCpu);
604	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
605	Log6(("TRPMGC07: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
606	return rc;
607	}
608
609
610	/**
611	* \#NP ((segment) Not Present) handler.
612	*
613	* @returns VBox status code.
614	* VINF_SUCCESS means we completely handled this trap,
615	* other codes are passed execution to host context.
616	*
617	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
618	* @param pRegFrame Pointer to the register frame for the trap.
619	* @internal
620	*/
621	DECLASM(int) TRPMGCTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
622	{
623	LogFlow(("TRPMGC0b: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
624	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
625	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
626	PGMRZDynMapStartAutoSet(pVCpu);
627
628	/*
629	* Try to detect instruction by opcode which caused trap.
630	* XXX note: this code may cause \#PF (trap e) or \#GP (trap d) while
631	* accessing user code. need to handle it somehow in future!
632	*/
633	RTGCPTR GCPtr;
634	if ( SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
635	(RTGCPTR)pRegFrame->eip, &GCPtr)
636	== VINF_SUCCESS)
637	{
638	uint8_t pu8Code = (uint8_t )(uintptr_t)GCPtr;
639
640	/*
641	* First skip possible instruction prefixes, such as:
642	* OS, AS
643	* CS:, DS:, ES:, SS:, FS:, GS:
644	* REPE, REPNE
645	*
646	* note: Currently we supports only up to 4 prefixes per opcode, more
647	* prefixes (normally not used anyway) will cause trap d in guest.
648	* note: Instruction length in IA-32 may be up to 15 bytes, we dont
649	* check this issue, its too hard.
650	*/
651	for (unsigned i = 0; i < 4; i++)
652	{
653	if ( pu8Code[0] != 0xf2 /* REPNE/REPNZ */
654	&& pu8Code[0] != 0xf3 /* REP/REPE/REPZ */
655	&& pu8Code[0] != 0x2e /* CS: */
656	&& pu8Code[0] != 0x36 /* SS: */
657	&& pu8Code[0] != 0x3e /* DS: */
658	&& pu8Code[0] != 0x26 /* ES: */
659	&& pu8Code[0] != 0x64 /* FS: */
660	&& pu8Code[0] != 0x65 /* GS: */
661	&& pu8Code[0] != 0x66 /* OS */
662	&& pu8Code[0] != 0x67 /* AS */
663	)
664	break;
665	pu8Code++;
666	}
667
668	/*
669	* Detect right switch using a callgate.
670	*
671	* We recognize the following causes for the trap 0b:
672	* CALL FAR, CALL FAR []
673	* JMP FAR, JMP FAR []
674	* IRET (may cause a task switch)
675	*
676	* Note: we can't detect whether the trap was caused by a call to a
677	* callgate descriptor or it is a real trap 0b due to a bad selector.
678	* In both situations we'll pass execution to our recompiler so we don't
679	* have to worry.
680	* If we wanted to do better detection, we have set GDT entries to callgate
681	* descriptors pointing to our own handlers.
682	*/
683	/** @todo not sure about IRET, may generate Trap 0d (\#GP), NEED TO CHECK! */
684	if ( pu8Code[0] == 0x9a /* CALL FAR */
685	\|\| ( pu8Code[0] == 0xff /* CALL FAR [] */
686	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x18)
687	\|\| pu8Code[0] == 0xea /* JMP FAR */
688	\|\| ( pu8Code[0] == 0xff /* JMP FAR [] */
689	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x28)
690	\|\| pu8Code[0] == 0xcf /* IRET */
691	)
692	{
693	/*
694	* Got potential call to callgate.
695	* We simply return execution to the recompiler to do emulation
696	* starting from the instruction which caused the trap.
697	*/
698	pTrpmCpu->uActiveVector = UINT32_MAX;
699	Log6(("TRPMGC0b: %Rrc (%04x:%08x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs, pRegFrame->eip));
700	PGMRZDynMapReleaseAutoSet(pVCpu);
701	return VINF_EM_RAW_RING_SWITCH;
702	}
703	}
704
705	/*
706	* Pass trap 0b as is to the recompiler in all other cases.
707	*/
708	Log6(("TRPMGC0b: %Rrc (%04x:%08x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs, pRegFrame->eip));
709	PGMRZDynMapReleaseAutoSet(pVCpu);
710	return VINF_EM_RAW_GUEST_TRAP;
711	}
712
713
714	/**
715	* \#GP (General Protection Fault) handler for Ring-0 privileged instructions.
716	*
717	* @returns VBox status code.
718	* VINF_SUCCESS means we completely handled this trap,
719	* other codes are passed execution to host context.
720	*
721	* @param pVM The VM handle.
722	* @param pVCpu The virtual CPU handle.
723	* @param pRegFrame Pointer to the register frame for the trap.
724	* @param pCpu The opcode info.
725	* @param PC The program counter corresponding to cs:eip in pRegFrame.
726	*/
727	static int trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
728	{
729	int rc;
730
731	/*
732	* Try handle it here, if not return to HC and emulate/interpret it there.
733	*/
734	switch (pCpu->pCurInstr->opcode)
735	{
736	case OP_INT3:
737	/*
738	* Little hack to make the code below not fail
739	*/
740	pCpu->param1.flags = USE_IMMEDIATE8;
741	pCpu->param1.parval = 3;
742	/* fallthru */
743	case OP_INT:
744	{
745	Assert(pCpu->param1.flags & USE_IMMEDIATE8);
746	Assert(!(PATMIsPatchGCAddr(pVM, PC)));
747	if (pCpu->param1.parval == 3)
748	{
749	/* Int 3 replacement patch? */
750	if (PATMHandleInt3PatchTrap(pVM, pRegFrame) == VINF_SUCCESS)
751	{
752	AssertFailed();
753	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
754	}
755	}
756	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->opsize, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
757	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
758	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
759
760	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
761	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
762	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
763	}
764
765	#ifdef PATM_EMULATE_SYSENTER
766	case OP_SYSEXIT:
767	case OP_SYSRET:
768	rc = PATMSysCall(pVM, pRegFrame, pCpu);
769	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
770	#endif
771
772	case OP_HLT:
773	/* If it's in patch code, defer to ring-3. */
774	if (PATMIsPatchGCAddr(pVM, PC))
775	break;
776
777	pRegFrame->eip += pCpu->opsize;
778	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_HALT, pRegFrame);
779
780
781	/*
782	* These instructions are used by PATM and CASM for finding
783	* dangerous non-trapping instructions. Thus, since all
784	* scanning and patching is done in ring-3 we'll have to
785	* return to ring-3 on the first encounter of these instructions.
786	*/
787	case OP_MOV_CR:
788	case OP_MOV_DR:
789	/* We can safely emulate control/debug register move instructions in patched code. */
790	if ( !PATMIsPatchGCAddr(pVM, PC)
791	&& !CSAMIsKnownDangerousInstr(pVM, PC))
792	break;
793	case OP_INVLPG:
794	case OP_LLDT:
795	case OP_STI:
796	case OP_RDTSC: /* just in case */
797	case OP_RDPMC:
798	case OP_CLTS:
799	case OP_WBINVD: /* nop */
800	case OP_RDMSR:
801	case OP_WRMSR:
802	{
803	uint32_t cbIgnored;
804	rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored);
805	if (RT_SUCCESS(rc))
806	pRegFrame->eip += pCpu->opsize;
807	else if (rc == VERR_EM_INTERPRETER)
808	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
809	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
810	}
811	}
812
813	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EXCEPTION_PRIVILEGED, pRegFrame);
814	}
815
816
817	/**
818	* \#GP (General Protection Fault) handler for Ring-3.
819	*
820	* @returns VBox status code.
821	* VINF_SUCCESS means we completely handled this trap,
822	* other codes are passed execution to host context.
823	*
824	* @param pVM The VM handle.
825	* @param pVCpu The virtual CPU handle.
826	* @param pRegFrame Pointer to the register frame for the trap.
827	* @param pCpu The opcode info.
828	* @param PC The program counter corresponding to cs:eip in pRegFrame.
829	*/
830	static int trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
831	{
832	int rc;
833	Assert(!pRegFrame->eflags.Bits.u1VM);
834
835	switch (pCpu->pCurInstr->opcode)
836	{
837	/*
838	* INT3 and INT xx are ring-switching.
839	* (The shadow IDT will have set the entries to DPL=0, that's why we're here.)
840	*/
841	case OP_INT3:
842	/*
843	* Little hack to make the code below not fail
844	*/
845	pCpu->param1.flags = USE_IMMEDIATE8;
846	pCpu->param1.parval = 3;
847	/* fall thru */
848	case OP_INT:
849	{
850	Assert(pCpu->param1.flags & USE_IMMEDIATE8);
851	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->opsize, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
852	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
853	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
854
855	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
856	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
857	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
858	}
859
860	/*
861	* SYSCALL, SYSENTER, INTO and BOUND are also ring-switchers.
862	*/
863	case OP_SYSCALL:
864	case OP_SYSENTER:
865	#ifdef PATM_EMULATE_SYSENTER
866	rc = PATMSysCall(pVM, pRegFrame, pCpu);
867	if (rc == VINF_SUCCESS)
868	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
869	/* else no break; */
870	#endif
871	case OP_BOUND:
872	case OP_INTO:
873	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
874	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH, pRegFrame);
875
876	/*
877	* Handle virtualized TSC & PMC reads, just in case.
878	*/
879	case OP_RDTSC:
880	case OP_RDPMC:
881	{
882	uint32_t cbIgnored;
883	rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored);
884	if (RT_SUCCESS(rc))
885	pRegFrame->eip += pCpu->opsize;
886	else if (rc == VERR_EM_INTERPRETER)
887	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
888	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
889	}
890
891	/*
892	* STI and CLI are I/O privileged, i.e. if IOPL
893	*/
894	case OP_STI:
895	case OP_CLI:
896	{
897	uint32_t efl = CPUMRawGetEFlags(pVCpu, pRegFrame);
898	if (X86_EFL_GET_IOPL(efl) >= (unsigned)(pRegFrame->ss & X86_SEL_RPL))
899	{
900	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> REM\n"));
901	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RESCHEDULE_REM, pRegFrame);
902	}
903	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> #GP(0)\n"));
904	break;
905	}
906	}
907
908	/*
909	* A genuine guest fault.
910	*/
911	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
912	}
913
914
915	/**
916	* Emulates RDTSC for the \#GP handler.
917	*
918	* @returns VINF_SUCCESS or VINF_EM_RAW_EMULATE_INSTR.
919	*
920	* @param pVM Pointer to the shared VM structure.
921	* @param pVCpu The virtual CPU handle.
922	* @param pRegFrame Pointer to the register frame for the trap.
923	* This will be updated on successful return.
924	*/
925	DECLINLINE(int) trpmGCTrap0dHandlerRdTsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
926	{
927	STAM_COUNTER_INC(&pVM->trpm.s.StatTrap0dRdTsc);
928
929	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_TSD)
930	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame); /* will trap (optimize later). */
931
932	uint64_t uTicks = TMCpuTickGet(pVCpu);
933	pRegFrame->eax = uTicks;
934	pRegFrame->edx = uTicks >> 32;
935	pRegFrame->eip += 2;
936	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
937	}
938
939
940	/**
941	* \#GP (General Protection Fault) handler.
942	*
943	* @returns VBox status code.
944	* VINF_SUCCESS means we completely handled this trap,
945	* other codes are passed execution to host context.
946	*
947	* @param pVM The VM handle.
948	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
949	* @param pRegFrame Pointer to the register frame for the trap.
950	*/
951	static int trpmGCTrap0dHandler(PVM pVM, PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
952	{
953	LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv\n", pRegFrame->ss, pRegFrame->eip, pTrpmCpu->uActiveErrorCode));
954	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
955
956	/*
957	* Convert and validate CS.
958	*/
959	STAM_PROFILE_START(&pVM->trpm.s.StatTrap0dDisasm, a);
960	RTGCPTR PC;
961	uint32_t cBits;
962	int rc = SELMValidateAndConvertCSAddrGCTrap(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
963	(RTGCPTR)pRegFrame->eip, &PC, &cBits);
964	if (RT_FAILURE(rc))
965	{
966	Log(("trpmGCTrap0dHandler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n",
967	pRegFrame->cs, pRegFrame->eip, pRegFrame->ss & X86_SEL_RPL, rc));
968	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
969	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
970	}
971
972	/*
973	* Disassemble the instruction.
974	*/
975	DISCPUSTATE Cpu;
976	uint32_t cbOp;
977	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
978	if (RT_FAILURE(rc))
979	{
980	AssertMsgFailed(("DISCoreOneEx failed to PC=%RGv rc=%Rrc\n", PC, rc));
981	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
982	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
983	}
984	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
985
986	/*
987	* Optimize RDTSC traps.
988	* Some guests (like Solaris) are using RDTSC all over the place and
989	* will end up trapping a lot because of that.
990	*
991	* Note: it's no longer safe to access the instruction opcode directly due to possible stale code TLB entries
992	*/
993	if (Cpu.pCurInstr->opcode == OP_RDTSC)
994	return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame);
995
996	/*
997	* Deal with I/O port access.
998	*/
999	if ( pVCpu->trpm.s.uActiveErrorCode == 0
1000	&& (Cpu.pCurInstr->optype & OPTYPE_PORTIO))
1001	{
1002	VBOXSTRICTRC rcStrict = EMInterpretPortIO(pVM, pVCpu, pRegFrame, &Cpu, cbOp);
1003	rc = VBOXSTRICTRC_TODO(rcStrict);
1004	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1005	}
1006
1007	/*
1008	* Deal with Ring-0 (privileged instructions)
1009	*/
1010	if ( (pRegFrame->ss & X86_SEL_RPL) <= 1
1011	&& !pRegFrame->eflags.Bits.u1VM)
1012	return trpmGCTrap0dHandlerRing0(pVM, pVCpu, pRegFrame, &Cpu, PC);
1013
1014	/*
1015	* Deal with Ring-3 GPs.
1016	*/
1017	if (!pRegFrame->eflags.Bits.u1VM)
1018	return trpmGCTrap0dHandlerRing3(pVM, pVCpu, pRegFrame, &Cpu, PC);
1019
1020	/*
1021	* Deal with v86 code.
1022	*
1023	* We always set IOPL to zero which makes e.g. pushf fault in V86
1024	* mode. The guest might use IOPL=3 and therefore not expect a #GP.
1025	* Simply fall back to the recompiler to emulate this instruction if
1026	* that's the case. To get the correct we must use CPUMRawGetEFlags.
1027	*/
1028	X86EFLAGS eflags;
1029	eflags.u32 = CPUMRawGetEFlags(pVCpu, pRegFrame); /* Get the correct value. */
1030	Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
1031	if (eflags.Bits.u2IOPL != 3)
1032	{
1033	Assert(eflags.Bits.u2IOPL == 0);
1034
1035	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xD, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xd);
1036	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1037	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1038	}
1039	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1040	}
1041
1042
1043	/**
1044	* \#GP (General Protection Fault) handler.
1045	*
1046	* @returns VBox status code.
1047	* VINF_SUCCESS means we completely handled this trap,
1048	* other codes are passed execution to host context.
1049	*
1050	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1051	* @param pRegFrame Pointer to the register frame for the trap.
1052	* @internal
1053	*/
1054	DECLASM(int) TRPMGCTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1055	{
1056	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1057	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1058
1059	LogFlow(("TRPMGC0d: %04x:%08x err=%x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode));
1060
1061	PGMRZDynMapStartAutoSet(pVCpu);
1062	int rc = trpmGCTrap0dHandler(pVM, pTrpmCpu, pRegFrame);
1063	switch (rc)
1064	{
1065	case VINF_EM_RAW_GUEST_TRAP:
1066	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1067	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1068	rc = VINF_PATM_PATCH_TRAP_GP;
1069	break;
1070
1071	case VINF_EM_RAW_INTERRUPT_PENDING:
1072	Assert(TRPMHasTrap(pVCpu));
1073	/* no break; */
1074	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1075	case VINF_EM_RAW_EMULATE_INSTR:
1076	case VINF_IOM_HC_IOPORT_READ:
1077	case VINF_IOM_HC_IOPORT_WRITE:
1078	case VINF_IOM_HC_MMIO_WRITE:
1079	case VINF_IOM_HC_MMIO_READ:
1080	case VINF_IOM_HC_MMIO_READ_WRITE:
1081	case VINF_PATM_PATCH_INT3:
1082	case VINF_EM_NO_MEMORY:
1083	case VINF_EM_RAW_TO_R3:
1084	case VINF_EM_RAW_TIMER_PENDING:
1085	case VINF_EM_PENDING_REQUEST:
1086	case VINF_EM_HALT:
1087	case VINF_SUCCESS:
1088	break;
1089
1090	default:
1091	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("return code %d\n", rc));
1092	break;
1093	}
1094	Log6(("TRPMGC0d: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
1095	return rc;
1096	}
1097
1098
1099	/**
1100	* \#PF (Page Fault) handler.
1101	*
1102	* Calls PGM which does the actual handling.
1103	*
1104	*
1105	* @returns VBox status code.
1106	* VINF_SUCCESS means we completely handled this trap,
1107	* other codes are passed execution to host context.
1108	*
1109	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1110	* @param pRegFrame Pointer to the register frame for the trap.
1111	* @internal
1112	*/
1113	DECLASM(int) TRPMGCTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1114	{
1115	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1116	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1117
1118	LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2));
1119
1120	/*
1121	* This is all PGM stuff.
1122	*/
1123	PGMRZDynMapStartAutoSet(pVCpu);
1124	int rc = PGMTrap0eHandler(pVCpu, pVCpu->trpm.s.uActiveErrorCode, pRegFrame, (RTGCPTR)pVCpu->trpm.s.uActiveCR2);
1125	switch (rc)
1126	{
1127	case VINF_EM_RAW_EMULATE_INSTR:
1128	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
1129	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
1130	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
1131	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
1132	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
1133	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1134	rc = VINF_PATCH_EMULATE_INSTR;
1135	break;
1136
1137	case VINF_EM_RAW_GUEST_TRAP:
1138	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1139	{
1140	PGMRZDynMapReleaseAutoSet(pVCpu);
1141	return VINF_PATM_PATCH_TRAP_PF;
1142	}
1143
1144	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xE, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xe);
1145	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1146	break;
1147
1148	case VINF_EM_RAW_INTERRUPT_PENDING:
1149	Assert(TRPMHasTrap(pVCpu));
1150	/* no break; */
1151	case VINF_IOM_HC_MMIO_READ:
1152	case VINF_IOM_HC_MMIO_WRITE:
1153	case VINF_IOM_HC_MMIO_READ_WRITE:
1154	case VINF_PATM_HC_MMIO_PATCH_READ:
1155	case VINF_PATM_HC_MMIO_PATCH_WRITE:
1156	case VINF_SUCCESS:
1157	case VINF_EM_RAW_TO_R3:
1158	case VINF_EM_PENDING_REQUEST:
1159	case VINF_EM_RAW_TIMER_PENDING:
1160	case VINF_EM_NO_MEMORY:
1161	case VINF_CSAM_PENDING_ACTION:
1162	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1163	break;
1164
1165	default:
1166	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("Patch address for return code %d. eip=%08x\n", rc, pRegFrame->eip));
1167	break;
1168	}
1169	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1170	Log6(("TRPMGC0e: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
1171	return rc;
1172	}
1173
1174
1175	/**
1176	* Scans for the EIP in the specified array of trap handlers.
1177	*
1178	* If we don't fine the EIP, we'll panic.
1179	*
1180	* @returns VBox status code.
1181	*
1182	* @param pVM The VM handle.
1183	* @param pRegFrame Pointer to the register frame for the trap.
1184	* @param paHandlers The array of trap handler records.
1185	* @param pEndRecord The end record (exclusive).
1186	*/
1187	static int trpmGCHyperGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, PCTRPMGCHYPER paHandlers, PCTRPMGCHYPER pEndRecord)
1188	{
1189	uintptr_t uEip = (uintptr_t)pRegFrame->eip;
1190	Assert(paHandlers <= pEndRecord);
1191
1192	Log(("trpmGCHyperGeneric: uEip=%x %p-%p\n", uEip, paHandlers, pEndRecord));
1193
1194	#if 0 /// @todo later
1195	/*
1196	* Start by doing a kind of binary search.
1197	*/
1198	unsigned iStart = 0;
1199	unsigned iEnd = pEndRecord - paHandlers;
1200	unsigned i = iEnd / 2;
1201	#endif
1202
1203	/*
1204	* Do a linear search now (in case the array wasn't properly sorted).
1205	*/
1206	for (PCTRPMGCHYPER pCur = paHandlers; pCur < pEndRecord; pCur++)
1207	{
1208	if ( pCur->uStartEIP <= uEip
1209	&& (pCur->uEndEIP ? pCur->uEndEIP > uEip : pCur->uStartEIP == uEip))
1210	return pCur->pfnHandler(pVM, pRegFrame, pCur->uUser);
1211	}
1212
1213	return VERR_TRPM_DONT_PANIC;
1214	}
1215
1216
1217	/**
1218	* Hypervisor \#NP ((segment) Not Present) handler.
1219	*
1220	* Scans for the EIP in the registered trap handlers.
1221	*
1222	* @returns VBox status code.
1223	* VINF_SUCCESS means we completely handled this trap,
1224	* other codes are passed back to host context.
1225	*
1226	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1227	* @param pRegFrame Pointer to the register frame for the trap.
1228	* @internal
1229	*/
1230	DECLASM(int) TRPMGCHyperTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1231	{
1232	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0bHandlers, g_aTrap0bHandlersEnd);
1233	}
1234
1235
1236	/**
1237	* Hypervisor \#GP (General Protection Fault) handler.
1238	*
1239	* Scans for the EIP in the registered trap handlers.
1240	*
1241	* @returns VBox status code.
1242	* VINF_SUCCESS means we completely handled this trap,
1243	* other codes are passed back to host context.
1244	*
1245	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1246	* @param pRegFrame Pointer to the register frame for the trap.
1247	* @internal
1248	*/
1249	DECLASM(int) TRPMGCHyperTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1250	{
1251	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1252	}
1253
1254
1255	/**
1256	* Hypervisor \#PF (Page Fault) handler.
1257	*
1258	* Scans for the EIP in the registered trap handlers.
1259	*
1260	* @returns VBox status code.
1261	* VINF_SUCCESS means we completely handled this trap,
1262	* other codes are passed back to host context.
1263	*
1264	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1265	* @param pRegFrame Pointer to the register frame for the trap.
1266	* @internal
1267	*/
1268	DECLASM(int) TRPMGCHyperTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1269	{
1270	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1271	}
1272
1273
1274	/**
1275	* Deal with hypervisor traps occurring when resuming execution on a trap.
1276	*
1277	* @returns VBox status code.
1278	* @param pVM The VM handle.
1279	* @param pRegFrame Register frame.
1280	* @param uUser User arg.
1281	*/
1282	DECLCALLBACK(int) trpmGCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
1283	{
1284	Log(("********************************************************\n"));
1285	Log(("trpmGCTrapInGeneric: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
1286	Log(("********************************************************\n"));
1287
1288	if (uUser & TRPM_TRAP_IN_HYPER)
1289	{
1290	/*
1291	* Check that there is still some stack left, if not we'll flag
1292	* a guru meditation (the alternative is a triple fault).
1293	*/
1294	RTRCUINTPTR cbStackUsed = (RTRCUINTPTR)VMMGetStackRC(VMMGetCpu(pVM)) - pRegFrame->esp;
1295	if (cbStackUsed > VMM_STACK_SIZE - _1K)
1296	{
1297	LogRel(("trpmGCTrapInGeneric: ran out of stack: esp=#x cbStackUsed=%#x\n", pRegFrame->esp, cbStackUsed));
1298	return VERR_TRPM_DONT_PANIC;
1299	}
1300
1301	/*
1302	* Just zero the register containing the selector in question.
1303	* We'll deal with the actual stale or troublesome selector value in
1304	* the outermost trap frame.
1305	*/
1306	switch (uUser & TRPM_TRAP_IN_OP_MASK)
1307	{
1308	case TRPM_TRAP_IN_MOV_GS:
1309	pRegFrame->eax = 0;
1310	pRegFrame->gs = 0; /* prevent recursive trouble. */
1311	break;
1312	case TRPM_TRAP_IN_MOV_FS:
1313	pRegFrame->eax = 0;
1314	pRegFrame->fs = 0; /* prevent recursive trouble. */
1315	return VINF_SUCCESS;
1316
1317	default:
1318	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1319	return VERR_TRPM_BAD_TRAP_IN_OP;
1320	}
1321	}
1322	else
1323	{
1324	/*
1325	* Reconstruct the guest context and switch to the recompiler.
1326	* We ASSUME we're only at
1327	*/
1328	CPUMCTXCORE CtxCore = *pRegFrame;
1329	uint32_t pEsp = (uint32_t )pRegFrame->esp;
1330	int rc;
1331
1332	switch (uUser)
1333	{
1334	/*
1335	* This will only occur when resuming guest code in a trap handler!
1336	*/
1337	/* @note ASSUMES esp points to the temporary guest CPUMCTXCORE!!! */
1338	case TRPM_TRAP_IN_MOV_GS:
1339	case TRPM_TRAP_IN_MOV_FS:
1340	case TRPM_TRAP_IN_MOV_ES:
1341	case TRPM_TRAP_IN_MOV_DS:
1342	{
1343	PCPUMCTXCORE pTempGuestCtx = (PCPUMCTXCORE)pEsp;
1344
1345	/* Just copy the whole thing; several selector registers, eip (etc) and eax are not yet in pRegFrame. */
1346	CtxCore = *pTempGuestCtx;
1347	rc = VINF_EM_RAW_STALE_SELECTOR;
1348	break;
1349	}
1350
1351	/*
1352	* This will only occur when resuming guest code!
1353	*/
1354	case TRPM_TRAP_IN_IRET:
1355	CtxCore.eip = *pEsp++;
1356	CtxCore.cs = (RTSEL)*pEsp++;
1357	CtxCore.eflags.u32 = *pEsp++;
1358	CtxCore.esp = *pEsp++;
1359	CtxCore.ss = (RTSEL)*pEsp++;
1360	rc = VINF_EM_RAW_IRET_TRAP;
1361	break;
1362
1363	/*
1364	* This will only occur when resuming V86 guest code!
1365	*/
1366	case TRPM_TRAP_IN_IRET \| TRPM_TRAP_IN_V86:
1367	CtxCore.eip = *pEsp++;
1368	CtxCore.cs = (RTSEL)*pEsp++;
1369	CtxCore.eflags.u32 = *pEsp++;
1370	CtxCore.esp = *pEsp++;
1371	CtxCore.ss = (RTSEL)*pEsp++;
1372	CtxCore.es = (RTSEL)*pEsp++;
1373	CtxCore.ds = (RTSEL)*pEsp++;
1374	CtxCore.fs = (RTSEL)*pEsp++;
1375	CtxCore.gs = (RTSEL)*pEsp++;
1376	rc = VINF_EM_RAW_IRET_TRAP;
1377	break;
1378
1379	default:
1380	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1381	return VERR_TRPM_BAD_TRAP_IN_OP;
1382	}
1383
1384
1385	CPUMSetGuestCtxCore(VMMGetCpu0(pVM), &CtxCore);
1386	TRPMGCHyperReturnToHost(pVM, rc);
1387	}
1388
1389	AssertMsgFailed(("Impossible!\n"));
1390	return VERR_TRPM_IPE_3;
1391	}
1392

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source: vbox/trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp@ 39723

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