TRPMRCHandlers.cpp@ 40449

Last change on this file since 40449 was 40449, checked in by vboxsync, 13 years ago
SELM: Refactoring (PVM -> PVMCPU).
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1	/* $Id: TRPMRCHandlers.cpp 40449 2012-03-13 15:51:02Z vboxsync $ */
2	/** @file
3	* TRPM - Guest Context Trap Handlers, CPP part
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_TRPM
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/iom.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/em.h>
29	#include <VBox/vmm/csam.h>
30	#include <VBox/vmm/patm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/cpum.h>
33	#include "TRPMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/vmm.h>
36	#include <VBox/param.h>
37
38	#include <VBox/err.h>
39	#include <VBox/dis.h>
40	#include <VBox/disopcode.h>
41	#include <VBox/log.h>
42	#include <VBox/vmm/tm.h>
43	#include <iprt/asm.h>
44	#include <iprt/asm-amd64-x86.h>
45	#include <iprt/assert.h>
46	#include <iprt/x86.h>
47
48
49	/*******************************************************************************
50	* Defined Constants And Macros *
51	*******************************************************************************/
52	/* still here. MODR/M byte parsing */
53	#define X86_OPCODE_MODRM_MOD_MASK 0xc0
54	#define X86_OPCODE_MODRM_REG_MASK 0x38
55	#define X86_OPCODE_MODRM_RM_MASK 0x07
56
57	/** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
58	#define DTRACE_EXPERIMENT
59
60
61	/*******************************************************************************
62	* Structures and Typedefs *
63	*******************************************************************************/
64	/** Pointer to a readonly hypervisor trap record. */
65	typedef const struct TRPMGCHYPER *PCTRPMGCHYPER;
66
67	/**
68	* A hypervisor trap record.
69	* This contains information about a handler for a instruction range.
70	*
71	* @remark This must match what TRPM_HANDLER outputs.
72	*/
73	typedef struct TRPMGCHYPER
74	{
75	/** The start address. */
76	uintptr_t uStartEIP;
77	/** The end address. (exclusive)
78	* If NULL the it's only for the instruction at pvStartEIP. */
79	uintptr_t uEndEIP;
80	/**
81	* The handler.
82	*
83	* @returns VBox status code
84	* VINF_SUCCESS means we've handled the trap.
85	* Any other error code means returning to the host context.
86	* @param pVM The VM handle.
87	* @param pRegFrame The register frame.
88	* @param uUser The user argument.
89	*/
90	DECLRCCALLBACKMEMBER(int, pfnHandler, (PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser));
91	/** Whatever the handler desires to put here. */
92	uintptr_t uUser;
93	} TRPMGCHYPER;
94
95
96	/*******************************************************************************
97	* Global Variables *
98	*******************************************************************************/
99	RT_C_DECLS_BEGIN
100	/** Defined in VMMGC0.asm or VMMGC99.asm.
101	* @{ */
102	extern const TRPMGCHYPER g_aTrap0bHandlers[1];
103	extern const TRPMGCHYPER g_aTrap0bHandlersEnd[1];
104	extern const TRPMGCHYPER g_aTrap0dHandlers[1];
105	extern const TRPMGCHYPER g_aTrap0dHandlersEnd[1];
106	extern const TRPMGCHYPER g_aTrap0eHandlers[1];
107	extern const TRPMGCHYPER g_aTrap0eHandlersEnd[1];
108	/** @} */
109	RT_C_DECLS_END
110
111
112	/*******************************************************************************
113	* Internal Functions *
114	*******************************************************************************/
115	RT_C_DECLS_BEGIN /* addressed from asm (not called so no DECLASM). */
116	DECLCALLBACK(int) trpmGCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser);
117	RT_C_DECLS_END
118
119
120
121	/**
122	* Exits the trap, called when exiting a trap handler.
123	*
124	* Will reset the trap if it's not a guest trap or the trap
125	* is already handled. Will process resume guest FFs.
126	*
127	* @returns rc, can be adjusted if its VINF_SUCCESS or something really bad
128	* happened.
129	* @param pVM VM handle.
130	* @param pVCpu The virtual CPU handle.
131	* @param rc The VBox status code to return.
132	* @param pRegFrame Pointer to the register frame for the trap.
133	*
134	* @remarks This must not be used for hypervisor traps, only guest traps.
135	*/
136	static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame)
137	{
138	uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
139	NOREF(uOldActiveVector);
140
141	/* Reset trap? */
142	if ( rc != VINF_EM_RAW_GUEST_TRAP
143	&& rc != VINF_EM_RAW_RING_SWITCH_INT)
144	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
145
146	#ifdef VBOX_HIGH_RES_TIMERS_HACK
147	/*
148	* We should poll the timers occasionally.
149	* We must NOT do this too frequently as it adds a significant overhead
150	* and it'll kill us if the trap load is high. (See #1354.)
151	* (The heuristic is not very intelligent, we should really check trap
152	* frequency etc. here, but alas, we lack any such information atm.)
153	*/
154	static unsigned s_iTimerPoll = 0;
155	if (rc == VINF_SUCCESS)
156	{
157	if (!(++s_iTimerPoll & 0xf))
158	{
159	TMTimerPollVoid(pVM, pVCpu);
160	Log2(("TMTimerPoll at %08RX32 - VM_FF_TM_VIRTUAL_SYNC=%d VM_FF_TM_VIRTUAL_SYNC=%d\n", pRegFrame->eip,
161	VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)));
162	}
163	}
164	else
165	s_iTimerPoll = 0;
166	#endif
167
168	/* Clear pending inhibit interrupt state if required. (necessary for dispatching interrupts later on) */
169	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
170	{
171	Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
172	if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVCpu))
173	{
174	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
175	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
176	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
177	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
178	*/
179	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
180	}
181	}
182
183	/*
184	* Pending resume-guest-FF?
185	* Or pending (A)PIC interrupt? Windows XP will crash if we delay APIC interrupts.
186	*/
187	if ( rc == VINF_SUCCESS
188	&& ( VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC \| VM_FF_REQUEST \| VM_FF_PGM_NO_MEMORY \| VM_FF_PDM_DMA)
189	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_TO_R3 \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
190	\| VMCPU_FF_REQUEST \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
191	\| VMCPU_FF_PDM_CRITSECT)
192	)
193	)
194	{
195	/* The out of memory condition naturally outranks the others. */
196	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
197	rc = VINF_EM_NO_MEMORY;
198	/* Pending Ring-3 action. */
199	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TO_R3 \| VMCPU_FF_PDM_CRITSECT))
200	{
201	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
202	rc = VINF_EM_RAW_TO_R3;
203	}
204	/* Pending timer action. */
205	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER))
206	rc = VINF_EM_RAW_TIMER_PENDING;
207	/* The Virtual Sync clock has stopped. */
208	else if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
209	rc = VINF_EM_RAW_TO_R3;
210	/* DMA work pending? */
211	else if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA))
212	rc = VINF_EM_RAW_TO_R3;
213	/* Pending request packets might contain actions that need immediate
214	attention, such as pending hardware interrupts. */
215	else if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
216	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
217	rc = VINF_EM_PENDING_REQUEST;
218	/* Pending interrupt: dispatch it. */
219	else if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
220	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
221	&& PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame)
222	)
223	{
224	uint8_t u8Interrupt;
225	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
226	Log(("trpmGCExitTrap: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
227	AssertFatalMsgRC(rc, ("PDMGetInterrupt failed with %Rrc\n", rc));
228	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_HARDWARE_INT, uOldActiveVector);
229	/* can't return if successful */
230	Assert(rc != VINF_SUCCESS);
231
232	/* Stop the profile counter that was started in TRPMGCHandlersA.asm */
233	Assert(uOldActiveVector <= 16);
234	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
235
236	/* Assert the trap and go to the recompiler to dispatch it. */
237	TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
238
239	STAM_PROFILE_ADV_START(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
240	rc = VINF_EM_RAW_INTERRUPT_PENDING;
241	}
242	/*
243	* Try sync CR3?
244	*/
245	else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
246	{
247	#if 1
248	PGMRZDynMapReleaseAutoSet(pVCpu);
249	PGMRZDynMapStartAutoSet(pVCpu);
250	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
251	#else
252	rc = VINF_PGM_SYNC_CR3;
253	#endif
254	}
255	}
256
257	AssertMsg( rc != VINF_SUCCESS
258	\|\| ( pRegFrame->eflags.Bits.u1IF
259	&& ( pRegFrame->eflags.Bits.u2IOPL < (unsigned)(pRegFrame->ss & X86_SEL_RPL) \|\| pRegFrame->eflags.Bits.u1VM))
260	, ("rc=%Rrc\neflags=%RX32 ss=%RTsel IOPL=%d\n", rc, pRegFrame->eflags.u32, pRegFrame->ss, pRegFrame->eflags.Bits.u2IOPL));
261	PGMRZDynMapReleaseAutoSet(pVCpu);
262	return rc;
263	}
264
265
266	/**
267	* \#DB (Debug event) handler.
268	*
269	* @returns VBox status code.
270	* VINF_SUCCESS means we completely handled this trap,
271	* other codes are passed execution to host context.
272	*
273	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
274	* @param pRegFrame Pointer to the register frame for the trap.
275	* @internal
276	*/
277	DECLASM(int) TRPMGCTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
278	{
279	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
280	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
281	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
282
283	LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
284
285	/*
286	* We currently don't make use of the X86_DR7_GD bit, but
287	* there might come a time when we do.
288	*/
289	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
290	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
291	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
292	VERR_NOT_IMPLEMENTED);
293	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
294
295	/*
296	* Now leave the rest to the DBGF.
297	*/
298	PGMRZDynMapStartAutoSet(pVCpu);
299	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6);
300	if (rc == VINF_EM_RAW_GUEST_TRAP)
301	CPUMSetGuestDR6(pVCpu, uDr6);
302
303	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
304	Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs, pRegFrame->eip, uDr6));
305	return rc;
306	}
307
308
309	/**
310	* \#DB (Debug event) handler for the hypervisor code.
311	*
312	* This is mostly the same as TRPMGCTrap01Handler, but we skip the PGM auto
313	* mapping set as well as the default trap exit path since they are both really
314	* bad ideas in this context.
315	*
316	* @returns VBox status code.
317	* VINF_SUCCESS means we completely handled this trap,
318	* other codes are passed execution to host context.
319	*
320	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
321	* @param pRegFrame Pointer to the register frame for the trap.
322	* @internal
323	*/
324	DECLASM(int) TRPMGCHyperTrap01Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
325	{
326	RTGCUINTREG uDr6 = ASMGetAndClearDR6();
327	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
328	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
329
330	LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
331
332	/*
333	* We currently don't make use of the X86_DR7_GD bit, but
334	* there might come a time when we do.
335	*/
336	AssertReleaseMsgReturn((uDr6 & X86_DR6_BD) != X86_DR6_BD,
337	("X86_DR6_BD isn't used, but it's set! dr7=%RTreg(%RTreg) dr6=%RTreg\n",
338	ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
339	VERR_NOT_IMPLEMENTED);
340	AssertReleaseMsg(!(uDr6 & X86_DR6_BT), ("X86_DR6_BT is impossible!\n"));
341
342	/*
343	* Now leave the rest to the DBGF.
344	*/
345	int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6);
346	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_1);
347
348	Log6(("TRPMGCHyper01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs, pRegFrame->eip, uDr6));
349	return rc;
350	}
351
352
353	/**
354	* NMI handler, for when we are using NMIs to debug things.
355	*
356	* @returns VBox status code.
357	* VINF_SUCCESS means we completely handled this trap,
358	* other codes are passed execution to host context.
359	*
360	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
361	* @param pRegFrame Pointer to the register frame for the trap.
362	* @internal
363	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
364	*/
365	DECLASM(int) TRPMGCTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
366	{
367	LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
368	RTLogComPrintf("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip);
369	NOREF(pTrpmCpu);
370	return VERR_TRPM_DONT_PANIC;
371	}
372
373
374	/**
375	* NMI handler, for when we are using NMIs to debug things.
376	*
377	* This is the handler we're most likely to hit when the NMI fires (it is
378	* unlikely that we'll be stuck in guest code).
379	*
380	* @returns VBox status code.
381	* VINF_SUCCESS means we completely handled this trap,
382	* other codes are passed execution to host context.
383	*
384	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
385	* @param pRegFrame Pointer to the register frame for the trap.
386	* @internal
387	* @remark This is not hooked up unless you're building with VBOX_WITH_NMI defined.
388	*/
389	DECLASM(int) TRPMGCHyperTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
390	{
391	LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
392	RTLogComPrintf("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip);
393	NOREF(pTrpmCpu);
394	return VERR_TRPM_DONT_PANIC;
395	}
396
397
398	/**
399	* \#BP (Breakpoint) handler.
400	*
401	* @returns VBox status code.
402	* VINF_SUCCESS means we completely handled this trap,
403	* other codes are passed execution to host context.
404	*
405	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
406	* @param pRegFrame Pointer to the register frame for the trap.
407	* @internal
408	*/
409	DECLASM(int) TRPMGCTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
410	{
411	LogFlow(("TRPMGC03: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
412	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
413	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
414	int rc;
415	PGMRZDynMapStartAutoSet(pVCpu);
416
417	/*
418	* PATM is using INT3s, let them have a go first.
419	*/
420	if ( (pRegFrame->ss & X86_SEL_RPL) == 1
421	&& !pRegFrame->eflags.Bits.u1VM)
422	{
423	rc = PATMHandleInt3PatchTrap(pVM, pRegFrame);
424	if (rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PATM_PATCH_INT3 \|\| rc == VINF_PATM_DUPLICATE_FUNCTION)
425	{
426	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
427	Log6(("TRPMGC03: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs, pRegFrame->eip));
428	return rc;
429	}
430	}
431	rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
432
433	/* anything we should do with this? Schedule it in GC? */
434	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
435	Log6(("TRPMGC03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
436	return rc;
437	}
438
439
440	/**
441	* \#BP (Breakpoint) handler.
442	*
443	* This is similar to TRPMGCTrap03Handler but we bits which are potentially
444	* harmful to us (common trap exit and the auto mapping set).
445	*
446	* @returns VBox status code.
447	* VINF_SUCCESS means we completely handled this trap,
448	* other codes are passed execution to host context.
449	*
450	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
451	* @param pRegFrame Pointer to the register frame for the trap.
452	* @internal
453	*/
454	DECLASM(int) TRPMGCHyperTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
455	{
456	LogFlow(("TRPMGCHyper03: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
457	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
458	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
459
460	/*
461	* Hand it over to DBGF.
462	*/
463	int rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
464	AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_2);
465
466	Log6(("TRPMGCHyper03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
467	return rc;
468	}
469
470
471	/**
472	* Trap handler for illegal opcode fault (\#UD).
473	*
474	* @returns VBox status code.
475	* VINF_SUCCESS means we completely handled this trap,
476	* other codes are passed execution to host context.
477	*
478	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
479	* @param pRegFrame Pointer to the register frame for the trap.
480	* @internal
481	*/
482	DECLASM(int) TRPMGCTrap06Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
483	{
484	LogFlow(("TRPMGC06: %04x:%08x efl=%x\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->eflags.u32));
485	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
486	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
487	int rc;
488	PGMRZDynMapStartAutoSet(pVCpu);
489
490	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
491	{
492	/*
493	* Decode the instruction.
494	*/
495	RTGCPTR PC;
496	rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
497	(RTGCPTR)pRegFrame->eip, &PC);
498	if (RT_FAILURE(rc))
499	{
500	Log(("TRPMGCTrap06Handler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->ss & X86_SEL_RPL, rc));
501	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
502	Log6(("TRPMGC06: %Rrc (%04x:%08x) (SELM)\n", rc, pRegFrame->cs, pRegFrame->eip));
503	return rc;
504	}
505
506	DISCPUSTATE Cpu;
507	uint32_t cbOp;
508	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
509	if (RT_FAILURE(rc))
510	{
511	rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
512	Log6(("TRPMGC06: %Rrc (%04x:%08x) (EM)\n", rc, pRegFrame->cs, pRegFrame->eip));
513	return rc;
514	}
515
516	/*
517	* UD2 in a patch?
518	* Note! PATMGCHandleIllegalInstrTrap doesn't always return.
519	*/
520	if ( Cpu.pCurInstr->opcode == OP_ILLUD2
521	&& PATMIsPatchGCAddr(pVM, pRegFrame->eip))
522	{
523	LogFlow(("TRPMGCTrap06Handler: -> PATMGCHandleIllegalInstrTrap\n"));
524	rc = PATMGCHandleIllegalInstrTrap(pVM, pRegFrame);
525	/** @todo These tests are completely unnecessary, should just follow the
526	* flow and return at the end of the function. */
527	if ( rc == VINF_SUCCESS
528	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
529	\|\| rc == VINF_PATM_DUPLICATE_FUNCTION
530	\|\| rc == VINF_PATM_PENDING_IRQ_AFTER_IRET
531	\|\| rc == VINF_EM_RESCHEDULE)
532	{
533	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
534	Log6(("TRPMGC06: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs, pRegFrame->eip));
535	return rc;
536	}
537	}
538	/*
539	* Speed up dtrace and don't entrust invalid lock sequences to the recompiler.
540	*/
541	else if (Cpu.prefix & PREFIX_LOCK)
542	{
543	Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->opcode));
544	#ifdef DTRACE_EXPERIMENT /** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
545	Assert(!PATMIsPatchGCAddr(pVM, pRegFrame->eip));
546	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0x6, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, 0x6);
547	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
548	#else
549	rc = VINF_EM_RAW_EMULATE_INSTR;
550	#endif
551	}
552	/*
553	* Handle MONITOR - it causes an #UD exception instead of #GP when not executed in ring 0.
554	*/
555	else if (Cpu.pCurInstr->opcode == OP_MONITOR)
556	{
557	LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n"));
558	rc = EMInterpretInstructionCpuUpdtPC(pVM, pVCpu, &Cpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
559	}
560	/* Never generate a raw trap here; it might be an instruction, that requires emulation. */
561	else
562	{
563	LogFlow(("TRPMGCTrap06Handler: -> VINF_EM_RAW_EMULATE_INSTR\n"));
564	rc = VINF_EM_RAW_EMULATE_INSTR;
565	}
566	}
567	else
568	{
569	LogFlow(("TRPMGCTrap06Handler: -> TRPMForwardTrap\n"));
570	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0x6, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, 0x6);
571	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
572	}
573
574	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
575	Log6(("TRPMGC06: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
576	return rc;
577	}
578
579
580	/**
581	* Trap handler for device not present fault (\#NM).
582	*
583	* Device not available, FP or (F)WAIT instruction.
584	*
585	* @returns VBox status code.
586	* VINF_SUCCESS means we completely handled this trap,
587	* other codes are passed execution to host context.
588	*
589	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
590	* @param pRegFrame Pointer to the register frame for the trap.
591	* @internal
592	*/
593	DECLASM(int) TRPMGCTrap07Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
594	{
595	LogFlow(("TRPMGC07: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
596	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
597	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
598	PGMRZDynMapStartAutoSet(pVCpu);
599
600	int rc = CPUMHandleLazyFPU(pVCpu);
601	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
602	Log6(("TRPMGC07: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
603	return rc;
604	}
605
606
607	/**
608	* \#NP ((segment) Not Present) handler.
609	*
610	* @returns VBox status code.
611	* VINF_SUCCESS means we completely handled this trap,
612	* other codes are passed execution to host context.
613	*
614	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
615	* @param pRegFrame Pointer to the register frame for the trap.
616	* @internal
617	*/
618	DECLASM(int) TRPMGCTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
619	{
620	LogFlow(("TRPMGC0b: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
621	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
622	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
623	PGMRZDynMapStartAutoSet(pVCpu);
624
625	/*
626	* Try to detect instruction by opcode which caused trap.
627	* XXX note: this code may cause \#PF (trap e) or \#GP (trap d) while
628	* accessing user code. need to handle it somehow in future!
629	*/
630	RTGCPTR GCPtr;
631	if ( SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
632	(RTGCPTR)pRegFrame->eip, &GCPtr)
633	== VINF_SUCCESS)
634	{
635	uint8_t pu8Code = (uint8_t )(uintptr_t)GCPtr;
636
637	/*
638	* First skip possible instruction prefixes, such as:
639	* OS, AS
640	* CS:, DS:, ES:, SS:, FS:, GS:
641	* REPE, REPNE
642	*
643	* note: Currently we supports only up to 4 prefixes per opcode, more
644	* prefixes (normally not used anyway) will cause trap d in guest.
645	* note: Instruction length in IA-32 may be up to 15 bytes, we dont
646	* check this issue, its too hard.
647	*/
648	for (unsigned i = 0; i < 4; i++)
649	{
650	if ( pu8Code[0] != 0xf2 /* REPNE/REPNZ */
651	&& pu8Code[0] != 0xf3 /* REP/REPE/REPZ */
652	&& pu8Code[0] != 0x2e /* CS: */
653	&& pu8Code[0] != 0x36 /* SS: */
654	&& pu8Code[0] != 0x3e /* DS: */
655	&& pu8Code[0] != 0x26 /* ES: */
656	&& pu8Code[0] != 0x64 /* FS: */
657	&& pu8Code[0] != 0x65 /* GS: */
658	&& pu8Code[0] != 0x66 /* OS */
659	&& pu8Code[0] != 0x67 /* AS */
660	)
661	break;
662	pu8Code++;
663	}
664
665	/*
666	* Detect right switch using a callgate.
667	*
668	* We recognize the following causes for the trap 0b:
669	* CALL FAR, CALL FAR []
670	* JMP FAR, JMP FAR []
671	* IRET (may cause a task switch)
672	*
673	* Note: we can't detect whether the trap was caused by a call to a
674	* callgate descriptor or it is a real trap 0b due to a bad selector.
675	* In both situations we'll pass execution to our recompiler so we don't
676	* have to worry.
677	* If we wanted to do better detection, we have set GDT entries to callgate
678	* descriptors pointing to our own handlers.
679	*/
680	/** @todo not sure about IRET, may generate Trap 0d (\#GP), NEED TO CHECK! */
681	if ( pu8Code[0] == 0x9a /* CALL FAR */
682	\|\| ( pu8Code[0] == 0xff /* CALL FAR [] */
683	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x18)
684	\|\| pu8Code[0] == 0xea /* JMP FAR */
685	\|\| ( pu8Code[0] == 0xff /* JMP FAR [] */
686	&& (pu8Code[1] & X86_OPCODE_MODRM_REG_MASK) == 0x28)
687	\|\| pu8Code[0] == 0xcf /* IRET */
688	)
689	{
690	/*
691	* Got potential call to callgate.
692	* We simply return execution to the recompiler to do emulation
693	* starting from the instruction which caused the trap.
694	*/
695	pTrpmCpu->uActiveVector = UINT32_MAX;
696	Log6(("TRPMGC0b: %Rrc (%04x:%08x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs, pRegFrame->eip));
697	PGMRZDynMapReleaseAutoSet(pVCpu);
698	return VINF_EM_RAW_RING_SWITCH;
699	}
700	}
701
702	/*
703	* Pass trap 0b as is to the recompiler in all other cases.
704	*/
705	Log6(("TRPMGC0b: %Rrc (%04x:%08x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs, pRegFrame->eip));
706	PGMRZDynMapReleaseAutoSet(pVCpu);
707	return VINF_EM_RAW_GUEST_TRAP;
708	}
709
710
711	/**
712	* \#GP (General Protection Fault) handler for Ring-0 privileged instructions.
713	*
714	* @returns VBox status code.
715	* VINF_SUCCESS means we completely handled this trap,
716	* other codes are passed execution to host context.
717	*
718	* @param pVM The VM handle.
719	* @param pVCpu The virtual CPU handle.
720	* @param pRegFrame Pointer to the register frame for the trap.
721	* @param pCpu The opcode info.
722	* @param PC The program counter corresponding to cs:eip in pRegFrame.
723	*/
724	static int trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
725	{
726	int rc;
727
728	/*
729	* Try handle it here, if not return to HC and emulate/interpret it there.
730	*/
731	switch (pCpu->pCurInstr->opcode)
732	{
733	case OP_INT3:
734	/*
735	* Little hack to make the code below not fail
736	*/
737	pCpu->param1.flags = USE_IMMEDIATE8;
738	pCpu->param1.parval = 3;
739	/* fallthru */
740	case OP_INT:
741	{
742	Assert(pCpu->param1.flags & USE_IMMEDIATE8);
743	Assert(!(PATMIsPatchGCAddr(pVM, PC)));
744	if (pCpu->param1.parval == 3)
745	{
746	/* Int 3 replacement patch? */
747	if (PATMHandleInt3PatchTrap(pVM, pRegFrame) == VINF_SUCCESS)
748	{
749	AssertFailed();
750	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
751	}
752	}
753	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->opsize, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
754	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
755	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
756
757	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
758	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
759	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
760	}
761
762	#ifdef PATM_EMULATE_SYSENTER
763	case OP_SYSEXIT:
764	case OP_SYSRET:
765	rc = PATMSysCall(pVM, pRegFrame, pCpu);
766	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
767	#endif
768
769	case OP_HLT:
770	/* If it's in patch code, defer to ring-3. */
771	if (PATMIsPatchGCAddr(pVM, PC))
772	break;
773
774	pRegFrame->eip += pCpu->opsize;
775	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_HALT, pRegFrame);
776
777
778	/*
779	* These instructions are used by PATM and CASM for finding
780	* dangerous non-trapping instructions. Thus, since all
781	* scanning and patching is done in ring-3 we'll have to
782	* return to ring-3 on the first encounter of these instructions.
783	*/
784	case OP_MOV_CR:
785	case OP_MOV_DR:
786	/* We can safely emulate control/debug register move instructions in patched code. */
787	if ( !PATMIsPatchGCAddr(pVM, PC)
788	&& !CSAMIsKnownDangerousInstr(pVM, PC))
789	break;
790	case OP_INVLPG:
791	case OP_LLDT:
792	case OP_STI:
793	case OP_RDTSC: /* just in case */
794	case OP_RDPMC:
795	case OP_CLTS:
796	case OP_WBINVD: /* nop */
797	case OP_RDMSR:
798	case OP_WRMSR:
799	{
800	rc = EMInterpretInstructionCpuUpdtPC(pVM, pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
801	if (rc == VERR_EM_INTERPRETER)
802	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
803	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
804	}
805	}
806
807	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EXCEPTION_PRIVILEGED, pRegFrame);
808	}
809
810
811	/**
812	* \#GP (General Protection Fault) handler for Ring-3.
813	*
814	* @returns VBox status code.
815	* VINF_SUCCESS means we completely handled this trap,
816	* other codes are passed execution to host context.
817	*
818	* @param pVM The VM handle.
819	* @param pVCpu The virtual CPU handle.
820	* @param pRegFrame Pointer to the register frame for the trap.
821	* @param pCpu The opcode info.
822	* @param PC The program counter corresponding to cs:eip in pRegFrame.
823	*/
824	static int trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
825	{
826	int rc;
827	Assert(!pRegFrame->eflags.Bits.u1VM);
828
829	switch (pCpu->pCurInstr->opcode)
830	{
831	/*
832	* INT3 and INT xx are ring-switching.
833	* (The shadow IDT will have set the entries to DPL=0, that's why we're here.)
834	*/
835	case OP_INT3:
836	/*
837	* Little hack to make the code below not fail
838	*/
839	pCpu->param1.flags = USE_IMMEDIATE8;
840	pCpu->param1.parval = 3;
841	/* fall thru */
842	case OP_INT:
843	{
844	Assert(pCpu->param1.flags & USE_IMMEDIATE8);
845	rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->opsize, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
846	if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
847	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
848
849	pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
850	pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
851	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
852	}
853
854	/*
855	* SYSCALL, SYSENTER, INTO and BOUND are also ring-switchers.
856	*/
857	case OP_SYSCALL:
858	case OP_SYSENTER:
859	#ifdef PATM_EMULATE_SYSENTER
860	rc = PATMSysCall(pVM, pRegFrame, pCpu);
861	if (rc == VINF_SUCCESS)
862	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
863	/* else no break; */
864	#endif
865	case OP_BOUND:
866	case OP_INTO:
867	pVCpu->trpm.s.uActiveVector = UINT32_MAX;
868	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH, pRegFrame);
869
870	/*
871	* Handle virtualized TSC & PMC reads, just in case.
872	*/
873	case OP_RDTSC:
874	case OP_RDPMC:
875	{
876	rc = EMInterpretInstructionCpuUpdtPC(pVM, pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
877	if (rc == VERR_EM_INTERPRETER)
878	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
879	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
880	}
881
882	/*
883	* STI and CLI are I/O privileged, i.e. if IOPL
884	*/
885	case OP_STI:
886	case OP_CLI:
887	{
888	uint32_t efl = CPUMRawGetEFlags(pVCpu, pRegFrame);
889	if (X86_EFL_GET_IOPL(efl) >= (unsigned)(pRegFrame->ss & X86_SEL_RPL))
890	{
891	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> REM\n"));
892	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RESCHEDULE_REM, pRegFrame);
893	}
894	LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> #GP(0)\n"));
895	break;
896	}
897	}
898
899	/*
900	* A genuine guest fault.
901	*/
902	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
903	}
904
905
906	/**
907	* Emulates RDTSC for the \#GP handler.
908	*
909	* @returns VINF_SUCCESS or VINF_EM_RAW_EMULATE_INSTR.
910	*
911	* @param pVM Pointer to the shared VM structure.
912	* @param pVCpu The virtual CPU handle.
913	* @param pRegFrame Pointer to the register frame for the trap.
914	* This will be updated on successful return.
915	*/
916	DECLINLINE(int) trpmGCTrap0dHandlerRdTsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
917	{
918	STAM_COUNTER_INC(&pVM->trpm.s.StatTrap0dRdTsc);
919
920	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_TSD)
921	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame); /* will trap (optimize later). */
922
923	uint64_t uTicks = TMCpuTickGet(pVCpu);
924	pRegFrame->eax = uTicks;
925	pRegFrame->edx = uTicks >> 32;
926	pRegFrame->eip += 2;
927	return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
928	}
929
930
931	/**
932	* \#GP (General Protection Fault) handler.
933	*
934	* @returns VBox status code.
935	* VINF_SUCCESS means we completely handled this trap,
936	* other codes are passed execution to host context.
937	*
938	* @param pVM The VM handle.
939	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
940	* @param pRegFrame Pointer to the register frame for the trap.
941	*/
942	static int trpmGCTrap0dHandler(PVM pVM, PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
943	{
944	LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv\n", pRegFrame->ss, pRegFrame->eip, pTrpmCpu->uActiveErrorCode));
945	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
946
947	/*
948	* Convert and validate CS.
949	*/
950	STAM_PROFILE_START(&pVM->trpm.s.StatTrap0dDisasm, a);
951	RTGCPTR PC;
952	uint32_t cBits;
953	int rc = SELMValidateAndConvertCSAddrGCTrap(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
954	(RTGCPTR)pRegFrame->eip, &PC, &cBits);
955	if (RT_FAILURE(rc))
956	{
957	Log(("trpmGCTrap0dHandler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n",
958	pRegFrame->cs, pRegFrame->eip, pRegFrame->ss & X86_SEL_RPL, rc));
959	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
960	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
961	}
962
963	/*
964	* Disassemble the instruction.
965	*/
966	DISCPUSTATE Cpu;
967	uint32_t cbOp;
968	rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
969	if (RT_FAILURE(rc))
970	{
971	AssertMsgFailed(("DISCoreOneEx failed to PC=%RGv rc=%Rrc\n", PC, rc));
972	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
973	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
974	}
975	STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
976
977	/*
978	* Optimize RDTSC traps.
979	* Some guests (like Solaris) are using RDTSC all over the place and
980	* will end up trapping a lot because of that.
981	*
982	* Note: it's no longer safe to access the instruction opcode directly due to possible stale code TLB entries
983	*/
984	if (Cpu.pCurInstr->opcode == OP_RDTSC)
985	return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame);
986
987	/*
988	* Deal with I/O port access.
989	*/
990	if ( pVCpu->trpm.s.uActiveErrorCode == 0
991	&& (Cpu.pCurInstr->optype & OPTYPE_PORTIO))
992	{
993	VBOXSTRICTRC rcStrict = IOMRCIOPortHandler(pVM, pRegFrame, &Cpu);
994	if (IOM_SUCCESS(rcStrict))
995	pRegFrame->rip += cbOp;
996	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
997	}
998
999	/*
1000	* Deal with Ring-0 (privileged instructions)
1001	*/
1002	if ( (pRegFrame->ss & X86_SEL_RPL) <= 1
1003	&& !pRegFrame->eflags.Bits.u1VM)
1004	return trpmGCTrap0dHandlerRing0(pVM, pVCpu, pRegFrame, &Cpu, PC);
1005
1006	/*
1007	* Deal with Ring-3 GPs.
1008	*/
1009	if (!pRegFrame->eflags.Bits.u1VM)
1010	return trpmGCTrap0dHandlerRing3(pVM, pVCpu, pRegFrame, &Cpu, PC);
1011
1012	/*
1013	* Deal with v86 code.
1014	*
1015	* We always set IOPL to zero which makes e.g. pushf fault in V86
1016	* mode. The guest might use IOPL=3 and therefore not expect a #GP.
1017	* Simply fall back to the recompiler to emulate this instruction if
1018	* that's the case. To get the correct we must use CPUMRawGetEFlags.
1019	*/
1020	X86EFLAGS eflags;
1021	eflags.u32 = CPUMRawGetEFlags(pVCpu, pRegFrame); /* Get the correct value. */
1022	Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
1023	if (eflags.Bits.u2IOPL != 3)
1024	{
1025	Assert(eflags.Bits.u2IOPL == 0);
1026
1027	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xD, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xd);
1028	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1029	return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1030	}
1031	return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1032	}
1033
1034
1035	/**
1036	* \#GP (General Protection Fault) handler.
1037	*
1038	* @returns VBox status code.
1039	* VINF_SUCCESS means we completely handled this trap,
1040	* other codes are passed execution to host context.
1041	*
1042	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1043	* @param pRegFrame Pointer to the register frame for the trap.
1044	* @internal
1045	*/
1046	DECLASM(int) TRPMGCTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1047	{
1048	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1049	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1050
1051	LogFlow(("TRPMGC0d: %04x:%08x err=%x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode));
1052
1053	PGMRZDynMapStartAutoSet(pVCpu);
1054	int rc = trpmGCTrap0dHandler(pVM, pTrpmCpu, pRegFrame);
1055	switch (rc)
1056	{
1057	case VINF_EM_RAW_GUEST_TRAP:
1058	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1059	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1060	rc = VINF_PATM_PATCH_TRAP_GP;
1061	break;
1062
1063	case VINF_EM_RAW_INTERRUPT_PENDING:
1064	Assert(TRPMHasTrap(pVCpu));
1065	/* no break; */
1066	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1067	case VINF_EM_RAW_EMULATE_INSTR:
1068	case VINF_IOM_R3_IOPORT_READ:
1069	case VINF_IOM_R3_IOPORT_WRITE:
1070	case VINF_IOM_R3_MMIO_WRITE:
1071	case VINF_IOM_R3_MMIO_READ:
1072	case VINF_IOM_R3_MMIO_READ_WRITE:
1073	case VINF_PATM_PATCH_INT3:
1074	case VINF_EM_NO_MEMORY:
1075	case VINF_EM_RAW_TO_R3:
1076	case VINF_EM_RAW_TIMER_PENDING:
1077	case VINF_EM_PENDING_REQUEST:
1078	case VINF_EM_HALT:
1079	case VINF_SUCCESS:
1080	break;
1081
1082	default:
1083	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("return code %d\n", rc));
1084	break;
1085	}
1086	Log6(("TRPMGC0d: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
1087	return rc;
1088	}
1089
1090
1091	/**
1092	* \#PF (Page Fault) handler.
1093	*
1094	* Calls PGM which does the actual handling.
1095	*
1096	*
1097	* @returns VBox status code.
1098	* VINF_SUCCESS means we completely handled this trap,
1099	* other codes are passed execution to host context.
1100	*
1101	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1102	* @param pRegFrame Pointer to the register frame for the trap.
1103	* @internal
1104	*/
1105	DECLASM(int) TRPMGCTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1106	{
1107	PVM pVM = TRPMCPU_2_VM(pTrpmCpu);
1108	PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1109
1110	LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2));
1111
1112	/*
1113	* This is all PGM stuff.
1114	*/
1115	PGMRZDynMapStartAutoSet(pVCpu);
1116	int rc = PGMTrap0eHandler(pVCpu, pVCpu->trpm.s.uActiveErrorCode, pRegFrame, (RTGCPTR)pVCpu->trpm.s.uActiveCR2);
1117	switch (rc)
1118	{
1119	case VINF_EM_RAW_EMULATE_INSTR:
1120	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
1121	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
1122	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
1123	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
1124	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
1125	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1126	rc = VINF_PATCH_EMULATE_INSTR;
1127	break;
1128
1129	case VINF_EM_RAW_GUEST_TRAP:
1130	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
1131	{
1132	PGMRZDynMapReleaseAutoSet(pVCpu);
1133	return VINF_PATM_PATCH_TRAP_PF;
1134	}
1135
1136	rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xE, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xe);
1137	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
1138	break;
1139
1140	case VINF_EM_RAW_INTERRUPT_PENDING:
1141	Assert(TRPMHasTrap(pVCpu));
1142	/* no break; */
1143	case VINF_IOM_R3_MMIO_READ:
1144	case VINF_IOM_R3_MMIO_WRITE:
1145	case VINF_IOM_R3_MMIO_READ_WRITE:
1146	case VINF_PATM_HC_MMIO_PATCH_READ:
1147	case VINF_PATM_HC_MMIO_PATCH_WRITE:
1148	case VINF_SUCCESS:
1149	case VINF_EM_RAW_TO_R3:
1150	case VINF_EM_PENDING_REQUEST:
1151	case VINF_EM_RAW_TIMER_PENDING:
1152	case VINF_EM_NO_MEMORY:
1153	case VINF_CSAM_PENDING_ACTION:
1154	case VINF_PGM_SYNC_CR3: /** @todo Check this with Sander. */
1155	break;
1156
1157	default:
1158	AssertMsg(PATMIsPatchGCAddr(pVM, pRegFrame->eip) == false, ("Patch address for return code %d. eip=%08x\n", rc, pRegFrame->eip));
1159	break;
1160	}
1161	rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1162	Log6(("TRPMGC0e: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
1163	return rc;
1164	}
1165
1166
1167	/**
1168	* Scans for the EIP in the specified array of trap handlers.
1169	*
1170	* If we don't fine the EIP, we'll panic.
1171	*
1172	* @returns VBox status code.
1173	*
1174	* @param pVM The VM handle.
1175	* @param pRegFrame Pointer to the register frame for the trap.
1176	* @param paHandlers The array of trap handler records.
1177	* @param pEndRecord The end record (exclusive).
1178	*/
1179	static int trpmGCHyperGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, PCTRPMGCHYPER paHandlers, PCTRPMGCHYPER pEndRecord)
1180	{
1181	uintptr_t uEip = (uintptr_t)pRegFrame->eip;
1182	Assert(paHandlers <= pEndRecord);
1183
1184	Log(("trpmGCHyperGeneric: uEip=%x %p-%p\n", uEip, paHandlers, pEndRecord));
1185
1186	#if 0 /// @todo later
1187	/*
1188	* Start by doing a kind of binary search.
1189	*/
1190	unsigned iStart = 0;
1191	unsigned iEnd = pEndRecord - paHandlers;
1192	unsigned i = iEnd / 2;
1193	#endif
1194
1195	/*
1196	* Do a linear search now (in case the array wasn't properly sorted).
1197	*/
1198	for (PCTRPMGCHYPER pCur = paHandlers; pCur < pEndRecord; pCur++)
1199	{
1200	if ( pCur->uStartEIP <= uEip
1201	&& (pCur->uEndEIP ? pCur->uEndEIP > uEip : pCur->uStartEIP == uEip))
1202	return pCur->pfnHandler(pVM, pRegFrame, pCur->uUser);
1203	}
1204
1205	return VERR_TRPM_DONT_PANIC;
1206	}
1207
1208
1209	/**
1210	* Hypervisor \#NP ((segment) Not Present) handler.
1211	*
1212	* Scans for the EIP in the registered trap handlers.
1213	*
1214	* @returns VBox status code.
1215	* VINF_SUCCESS means we completely handled this trap,
1216	* other codes are passed back to host context.
1217	*
1218	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1219	* @param pRegFrame Pointer to the register frame for the trap.
1220	* @internal
1221	*/
1222	DECLASM(int) TRPMGCHyperTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1223	{
1224	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0bHandlers, g_aTrap0bHandlersEnd);
1225	}
1226
1227
1228	/**
1229	* Hypervisor \#GP (General Protection Fault) handler.
1230	*
1231	* Scans for the EIP in the registered trap handlers.
1232	*
1233	* @returns VBox status code.
1234	* VINF_SUCCESS means we completely handled this trap,
1235	* other codes are passed back to host context.
1236	*
1237	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1238	* @param pRegFrame Pointer to the register frame for the trap.
1239	* @internal
1240	*/
1241	DECLASM(int) TRPMGCHyperTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1242	{
1243	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1244	}
1245
1246
1247	/**
1248	* Hypervisor \#PF (Page Fault) handler.
1249	*
1250	* Scans for the EIP in the registered trap handlers.
1251	*
1252	* @returns VBox status code.
1253	* VINF_SUCCESS means we completely handled this trap,
1254	* other codes are passed back to host context.
1255	*
1256	* @param pTrpmCpu Pointer to TRPMCPU data (within VM).
1257	* @param pRegFrame Pointer to the register frame for the trap.
1258	* @internal
1259	*/
1260	DECLASM(int) TRPMGCHyperTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
1261	{
1262	return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);
1263	}
1264
1265
1266	/**
1267	* Deal with hypervisor traps occurring when resuming execution on a trap.
1268	*
1269	* @returns VBox status code.
1270	* @param pVM The VM handle.
1271	* @param pRegFrame Register frame.
1272	* @param uUser User arg.
1273	*/
1274	DECLCALLBACK(int) trpmGCTrapInGeneric(PVM pVM, PCPUMCTXCORE pRegFrame, uintptr_t uUser)
1275	{
1276	Log(("********************************************************\n"));
1277	Log(("trpmGCTrapInGeneric: eip=%RX32 uUser=%#x\n", pRegFrame->eip, uUser));
1278	Log(("********************************************************\n"));
1279
1280	if (uUser & TRPM_TRAP_IN_HYPER)
1281	{
1282	/*
1283	* Check that there is still some stack left, if not we'll flag
1284	* a guru meditation (the alternative is a triple fault).
1285	*/
1286	RTRCUINTPTR cbStackUsed = (RTRCUINTPTR)VMMGetStackRC(VMMGetCpu(pVM)) - pRegFrame->esp;
1287	if (cbStackUsed > VMM_STACK_SIZE - _1K)
1288	{
1289	LogRel(("trpmGCTrapInGeneric: ran out of stack: esp=#x cbStackUsed=%#x\n", pRegFrame->esp, cbStackUsed));
1290	return VERR_TRPM_DONT_PANIC;
1291	}
1292
1293	/*
1294	* Just zero the register containing the selector in question.
1295	* We'll deal with the actual stale or troublesome selector value in
1296	* the outermost trap frame.
1297	*/
1298	switch (uUser & TRPM_TRAP_IN_OP_MASK)
1299	{
1300	case TRPM_TRAP_IN_MOV_GS:
1301	pRegFrame->eax = 0;
1302	pRegFrame->gs = 0; /* prevent recursive trouble. */
1303	break;
1304	case TRPM_TRAP_IN_MOV_FS:
1305	pRegFrame->eax = 0;
1306	pRegFrame->fs = 0; /* prevent recursive trouble. */
1307	return VINF_SUCCESS;
1308
1309	default:
1310	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1311	return VERR_TRPM_BAD_TRAP_IN_OP;
1312	}
1313	}
1314	else
1315	{
1316	/*
1317	* Reconstruct the guest context and switch to the recompiler.
1318	* We ASSUME we're only at
1319	*/
1320	CPUMCTXCORE CtxCore = *pRegFrame;
1321	uint32_t pEsp = (uint32_t )pRegFrame->esp;
1322	int rc;
1323
1324	switch (uUser)
1325	{
1326	/*
1327	* This will only occur when resuming guest code in a trap handler!
1328	*/
1329	/* @note ASSUMES esp points to the temporary guest CPUMCTXCORE!!! */
1330	case TRPM_TRAP_IN_MOV_GS:
1331	case TRPM_TRAP_IN_MOV_FS:
1332	case TRPM_TRAP_IN_MOV_ES:
1333	case TRPM_TRAP_IN_MOV_DS:
1334	{
1335	PCPUMCTXCORE pTempGuestCtx = (PCPUMCTXCORE)pEsp;
1336
1337	/* Just copy the whole thing; several selector registers, eip (etc) and eax are not yet in pRegFrame. */
1338	CtxCore = *pTempGuestCtx;
1339	rc = VINF_EM_RAW_STALE_SELECTOR;
1340	break;
1341	}
1342
1343	/*
1344	* This will only occur when resuming guest code!
1345	*/
1346	case TRPM_TRAP_IN_IRET:
1347	CtxCore.eip = *pEsp++;
1348	CtxCore.cs = (RTSEL)*pEsp++;
1349	CtxCore.eflags.u32 = *pEsp++;
1350	CtxCore.esp = *pEsp++;
1351	CtxCore.ss = (RTSEL)*pEsp++;
1352	rc = VINF_EM_RAW_IRET_TRAP;
1353	break;
1354
1355	/*
1356	* This will only occur when resuming V86 guest code!
1357	*/
1358	case TRPM_TRAP_IN_IRET \| TRPM_TRAP_IN_V86:
1359	CtxCore.eip = *pEsp++;
1360	CtxCore.cs = (RTSEL)*pEsp++;
1361	CtxCore.eflags.u32 = *pEsp++;
1362	CtxCore.esp = *pEsp++;
1363	CtxCore.ss = (RTSEL)*pEsp++;
1364	CtxCore.es = (RTSEL)*pEsp++;
1365	CtxCore.ds = (RTSEL)*pEsp++;
1366	CtxCore.fs = (RTSEL)*pEsp++;
1367	CtxCore.gs = (RTSEL)*pEsp++;
1368	rc = VINF_EM_RAW_IRET_TRAP;
1369	break;
1370
1371	default:
1372	AssertMsgFailed(("Invalid uUser=%#x\n", uUser));
1373	return VERR_TRPM_BAD_TRAP_IN_OP;
1374	}
1375
1376
1377	CPUMSetGuestCtxCore(VMMGetCpu0(pVM), &CtxCore);
1378	TRPMGCHyperReturnToHost(pVM, rc);
1379	}
1380
1381	AssertMsgFailed(("Impossible!\n"));
1382	return VERR_TRPM_IPE_3;
1383	}
1384

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source: vbox/trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp@ 40449

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