1 | /* $Id: DBGFRZ.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
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2 | /** @file
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3 | * DBGF - Debugger Facility, RZ part.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2020 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | /*********************************************************************************************************************************
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20 | * Header Files *
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21 | *********************************************************************************************************************************/
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22 | #define LOG_GROUP LOG_GROUP_DBGF
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23 | #include <VBox/vmm/dbgf.h>
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24 | #include <VBox/vmm/selm.h>
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25 | #ifdef IN_RC
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26 | # include <VBox/vmm/trpm.h>
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27 | #endif
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28 | #include <VBox/log.h>
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29 | #include "DBGFInternal.h"
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30 | #include <VBox/vmm/vmcc.h>
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31 | #include <VBox/err.h>
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32 | #include <iprt/assert.h>
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33 |
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34 | #ifdef IN_RC
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35 | DECLASM(void) TRPMRCHandlerAsmTrap03(void);
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36 | #endif
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37 |
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38 |
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39 | /**
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40 | * \#DB (Debug event) handler.
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41 | *
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42 | * @returns VBox status code.
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43 | * VINF_SUCCESS means we completely handled this trap,
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44 | * other codes are passed execution to host context.
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45 | *
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46 | * @param pVM The cross context VM structure.
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47 | * @param pVCpu The cross context virtual CPU structure.
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48 | * @param pRegFrame Pointer to the register frame for the trap.
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49 | * @param uDr6 The DR6 hypervisor register value.
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50 | * @param fAltStepping Alternative stepping indicator.
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51 | */
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52 | VMMRZ_INT_DECL(int) DBGFRZTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping)
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53 | {
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54 | #ifdef IN_RC
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55 | const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
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56 | #else
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57 | NOREF(pRegFrame);
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58 | const bool fInHyper = false;
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59 | #endif
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60 |
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61 | /** @todo Intel docs say that X86_DR6_BS has the highest priority... */
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62 | /*
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63 | * A breakpoint?
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64 | */
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65 | AssertCompile(X86_DR6_B0 == 1 && X86_DR6_B1 == 2 && X86_DR6_B2 == 4 && X86_DR6_B3 == 8);
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66 | if ( (uDr6 & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3))
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67 | && pVM->dbgf.s.cEnabledHwBreakpoints > 0)
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68 | {
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69 | for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
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70 | {
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71 | if ( ((uint32_t)uDr6 & RT_BIT_32(iBp))
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72 | && pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG)
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73 | {
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74 | pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
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75 | pVCpu->dbgf.s.fSingleSteppingRaw = false;
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76 | LogFlow(("DBGFRZTrap03Handler: hit hw breakpoint %d at %04x:%RGv\n",
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77 | pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs.Sel, pRegFrame->rip));
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78 |
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79 | return fInHyper ? VINF_EM_DBG_HYPER_BREAKPOINT : VINF_EM_DBG_BREAKPOINT;
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80 | }
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81 | }
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82 | }
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83 |
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84 | /*
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85 | * Single step?
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86 | * Are we single stepping or is it the guest?
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87 | */
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88 | if ( (uDr6 & X86_DR6_BS)
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89 | && (fInHyper || pVCpu->dbgf.s.fSingleSteppingRaw || fAltStepping))
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90 | {
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91 | pVCpu->dbgf.s.fSingleSteppingRaw = false;
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92 | LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
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93 | return fInHyper ? VINF_EM_DBG_HYPER_STEPPED : VINF_EM_DBG_STEPPED;
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94 | }
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95 |
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96 | #ifdef IN_RC
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97 | /*
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98 | * Either an ICEBP in hypervisor code or a guest related debug exception
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99 | * of sorts.
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100 | */
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101 | if (RT_UNLIKELY(fInHyper))
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102 | {
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103 | /*
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104 | * Is this a guest debug event that was delayed past a ring transition?
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105 | *
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106 | * Since we do no allow sysenter/syscall in raw-mode, the only
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107 | * non-trap/fault type transitions that can occur are thru interrupt gates.
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108 | * Of those, only INT3 (#BP) has a DPL other than 0 with a CS.RPL of 0.
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109 | * See bugref:9171 and bs3-cpu-weird-1 for more details.
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110 | *
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111 | * We need to reconstruct the guest register state from the hypervisor one
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112 | * here, so here is the layout of the IRET frame on the stack:
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113 | * 20:[8] GS (V86 only)
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114 | * 1C:[7] FS (V86 only)
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115 | * 18:[6] DS (V86 only)
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116 | * 14:[5] ES (V86 only)
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117 | * 10:[4] SS
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118 | * 0c:[3] ESP
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119 | * 08:[2] EFLAGS
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120 | * 04:[1] CS
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121 | * 00:[0] EIP
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122 | */
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123 | if (pRegFrame->rip == (uintptr_t)TRPMRCHandlerAsmTrap03)
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124 | {
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125 | uint32_t const *pu32Stack = (uint32_t const *)pRegFrame->esp;
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126 | if ( (pu32Stack[2] & X86_EFL_VM)
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127 | || (pu32Stack[1] & X86_SEL_RPL))
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128 | {
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129 | LogFlow(("DBGFRZTrap01Handler: Detected guest #DB delayed past ring transition %04x:%RX32 %#x\n",
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130 | pu32Stack[1] & 0xffff, pu32Stack[0], pu32Stack[2]));
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131 | PCPUMCTX pGstCtx = CPUMQueryGuestCtxPtr(pVCpu);
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132 | pGstCtx->rip = pu32Stack[0];
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133 | pGstCtx->cs.Sel = pu32Stack[1];
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134 | pGstCtx->eflags.u = pu32Stack[2];
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135 | pGstCtx->rsp = pu32Stack[3];
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136 | pGstCtx->ss.Sel = pu32Stack[4];
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137 | if (pu32Stack[2] & X86_EFL_VM)
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138 | {
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139 | pGstCtx->es.Sel = pu32Stack[5];
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140 | pGstCtx->ds.Sel = pu32Stack[6];
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141 | pGstCtx->fs.Sel = pu32Stack[7];
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142 | pGstCtx->gs.Sel = pu32Stack[8];
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143 | }
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144 | else
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145 | {
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146 | pGstCtx->es.Sel = pRegFrame->es.Sel;
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147 | pGstCtx->ds.Sel = pRegFrame->ds.Sel;
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148 | pGstCtx->fs.Sel = pRegFrame->fs.Sel;
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149 | pGstCtx->gs.Sel = pRegFrame->gs.Sel;
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150 | }
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151 | pGstCtx->rax = pRegFrame->rax;
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152 | pGstCtx->rcx = pRegFrame->rcx;
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153 | pGstCtx->rdx = pRegFrame->rdx;
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154 | pGstCtx->rbx = pRegFrame->rbx;
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155 | pGstCtx->rsi = pRegFrame->rsi;
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156 | pGstCtx->rdi = pRegFrame->rdi;
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157 | pGstCtx->rbp = pRegFrame->rbp;
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158 |
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159 | /*
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160 | * We should assert a #BP followed by a #DB here, but TRPM cannot
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161 | * do that. So, we'll just assert the #BP and ignore the #DB, even
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162 | * if that isn't strictly correct.
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163 | */
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164 | TRPMResetTrap(pVCpu);
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165 | TRPMAssertTrap(pVCpu, X86_XCPT_BP, TRPM_SOFTWARE_INT);
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166 | return VINF_EM_RAW_GUEST_TRAP;
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167 | }
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168 | }
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169 |
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170 | LogFlow(("DBGFRZTrap01Handler: Unknown bp at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
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171 | return VERR_DBGF_HYPER_DB_XCPT;
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172 | }
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173 | #endif
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174 |
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175 | LogFlow(("DBGFRZTrap01Handler: guest debug event %#x at %04x:%RGv!\n", (uint32_t)uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
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176 | return VINF_EM_RAW_GUEST_TRAP;
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177 | }
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178 |
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179 |
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180 | /**
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181 | * \#BP (Breakpoint) handler.
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182 | *
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183 | * @returns VBox status code.
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184 | * VINF_SUCCESS means we completely handled this trap,
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185 | * other codes are passed execution to host context.
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186 | *
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187 | * @param pVM The cross context VM structure.
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188 | * @param pVCpu The cross context virtual CPU structure.
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189 | * @param pRegFrame Pointer to the register frame for the trap.
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190 | */
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191 | VMMRZ_INT_DECL(int) DBGFRZTrap03Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
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192 | {
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193 | #ifdef IN_RC
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194 | const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
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195 | #else
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196 | const bool fInHyper = false;
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197 | #endif
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198 |
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199 | /*
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200 | * Get the trap address and look it up in the breakpoint table.
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201 | * Don't bother if we don't have any breakpoints.
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202 | */
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203 | unsigned cToSearch = pVM->dbgf.s.Int3.cToSearch;
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204 | if (cToSearch > 0)
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205 | {
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206 | RTGCPTR pPc;
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207 | int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
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208 | #ifdef IN_RC
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209 | pRegFrame->eip - 1,
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210 | #else
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211 | pRegFrame->rip /* no -1 in R0 */,
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212 | #endif
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213 | &pPc);
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214 | AssertRCReturn(rc, rc);
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215 |
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216 | unsigned iBp = pVM->dbgf.s.Int3.iStartSearch;
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217 | while (cToSearch-- > 0)
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218 | {
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219 | if ( pVM->dbgf.s.aBreakpoints[iBp].u.GCPtr == (RTGCUINTPTR)pPc
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220 | && pVM->dbgf.s.aBreakpoints[iBp].enmType == DBGFBPTYPE_INT3)
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221 | {
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222 | pVM->dbgf.s.aBreakpoints[iBp].cHits++;
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223 | pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aBreakpoints[iBp].iBp;
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224 |
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225 | LogFlow(("DBGFRZTrap03Handler: hit breakpoint %d at %RGv (%04x:%RGv) cHits=0x%RX64\n",
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226 | pVM->dbgf.s.aBreakpoints[iBp].iBp, pPc, pRegFrame->cs.Sel, pRegFrame->rip,
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227 | pVM->dbgf.s.aBreakpoints[iBp].cHits));
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228 | return fInHyper
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229 | ? VINF_EM_DBG_HYPER_BREAKPOINT
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230 | : VINF_EM_DBG_BREAKPOINT;
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231 | }
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232 | iBp++;
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233 | }
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234 | }
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235 |
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236 | return fInHyper
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237 | ? VINF_EM_DBG_HYPER_ASSERTION
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238 | : VINF_EM_RAW_GUEST_TRAP;
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239 | }
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240 |
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