PGMRZDynMap.cpp@ 31402

Last change on this file since 31402 was 31402, checked in by vboxsync, 14 years ago
PGM: Replaced the hazzardous raw-mode context dynamic mapping code with the PGMR0DynMap code used by darwin/x86. This is a risky change but it should pay off once stable by providing 100% certainty that dynamically mapped pages aren't resued behind our back (this has been observed in seemingly benign code paths recently).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 95.4 KB

Line
1	/* $Id: PGMRZDynMap.cpp 31402 2010-08-05 12:28:18Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, dynamic mapping cache.
4	*/
5
6	/*
7	* Copyright (C) 2008-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Internal Functions *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_DYNMAP
23	#include <VBox/pgm.h>
24	#include "../PGMInternal.h"
25	#include <VBox/vm.h>
26	#include "../PGMInline.h"
27	#include <VBox/err.h>
28	#include <VBox/param.h>
29	#include <VBox/sup.h>
30	#include <iprt/asm.h>
31	#include <iprt/asm-amd64-x86.h>
32	#include <iprt/assert.h>
33	#ifndef IN_RC
34	# include <iprt/cpuset.h>
35	# include <iprt/mem.h>
36	# include <iprt/memobj.h>
37	# include <iprt/mp.h>
38	# include <iprt/semaphore.h>
39	# include <iprt/spinlock.h>
40	#endif
41	#include <iprt/string.h>
42
43
44	/*******************************************************************************
45	* Defined Constants And Macros *
46	*******************************************************************************/
47	#ifdef IN_RING0
48	/** The max size of the mapping cache (in pages). */
49	# define PGMR0DYNMAP_MAX_PAGES ((16*_1M) >> PAGE_SHIFT)
50	/** The small segment size that is adopted on out-of-memory conditions with a
51	* single big segment. */
52	# define PGMR0DYNMAP_SMALL_SEG_PAGES 128
53	/** The number of pages we reserve per CPU. */
54	# define PGMR0DYNMAP_PAGES_PER_CPU 256
55	/** The minimum number of pages we reserve per CPU.
56	* This must be equal or larger than the autoset size. */
57	# define PGMR0DYNMAP_PAGES_PER_CPU_MIN 64
58	/** Calcs the overload threshold (safety margin). Current set at 50%. */
59	# define PGMR0DYNMAP_CALC_OVERLOAD(cPages) ((cPages) / 2)
60	/** The number of guard pages.
61	* @remarks Never do tuning of the hashing or whatnot with a strict build! */
62	# if defined(VBOX_STRICT)
63	# define PGMR0DYNMAP_GUARD_PAGES 1
64	# else
65	# define PGMR0DYNMAP_GUARD_PAGES 0
66	# endif
67	#endif /* IN_RING0 */
68	/** The dummy physical address of guard pages. */
69	#define PGMR0DYNMAP_GUARD_PAGE_HCPHYS UINT32_C(0x7777feed)
70	/** The dummy reference count of guard pages. (Must be non-zero.) */
71	#define PGMR0DYNMAP_GUARD_PAGE_REF_COUNT INT32_C(0x7777feed)
72	#if 0
73	/** Define this to just clear the present bit on guard pages.
74	* The alternative is to replace the entire PTE with an bad not-present
75	* PTE. Either way, XNU will screw us. :-/ */
76	# define PGMR0DYNMAP_GUARD_NP
77	#endif
78	/** The dummy PTE value for a page. */
79	#define PGMR0DYNMAP_GUARD_PAGE_LEGACY_PTE X86_PTE_PG_MASK
80	/** The dummy PTE value for a page. */
81	#define PGMR0DYNMAP_GUARD_PAGE_PAE_PTE UINT64_MAX /X86_PTE_PAE_PG_MASK/
82
83	#ifdef IN_RING0 /* Note! Assertions causes panics if preemption is disabled,
84	* disable this to work around that. */
85	/**
86	* Acquire the spinlock.
87	* This will declare a temporary variable and expands to two statements!
88	*/
89	# define PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis) \
90	RTSPINLOCKTMP MySpinlockTmp = RTSPINLOCKTMP_INITIALIZER; \
91	RTSpinlockAcquire((pThis)->hSpinlock, &MySpinlockTmp)
92	/**
93	* Releases the spinlock.
94	*/
95	# define PGMRZDYNMAP_SPINLOCK_RELEASE(pThis) \
96	RTSpinlockRelease((pThis)->hSpinlock, &MySpinlockTmp)
97
98	/**
99	* Re-acquires the spinlock.
100	*/
101	# define PGMRZDYNMAP_SPINLOCK_REACQUIRE(pThis) \
102	RTSpinlockAcquire((pThis)->hSpinlock, &MySpinlockTmp)
103	#else
104	# define PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis) do { } while (0)
105	# define PGMRZDYNMAP_SPINLOCK_RELEASE(pThis) do { } while (0)
106	# define PGMRZDYNMAP_SPINLOCK_REACQUIRE(pThis) do { } while (0)
107	#endif
108
109
110	/** Converts a PGMCPUM::AutoSet pointer into a PVMCPU. */
111	#define PGMRZDYNMAP_SET_2_VMCPU(pSet) (RT_FROM_MEMBER(pSet, VMCPU, pgm.s.AutoSet))
112
113	/** Converts a PGMCPUM::AutoSet pointer into a PVM. */
114	#define PGMRZDYNMAP_SET_2_VM(pSet) (PGMRZDYNMAP_SET_2_VMCPU(pSet)->CTX_SUFF(pVM))
115
116	/** Converts a PGMCPUM::AutoSet pointer into a PVM. */
117	#ifdef IN_RC
118	# define PGMRZDYNMAP_SET_2_DYNMAP(pSet) (PGMRZDYNMAP_SET_2_VM(pSet)->pgm.s.pRCDynMap)
119	#else
120	# define PGMRZDYNMAP_SET_2_DYNMAP(pSet) (g_pPGMR0DynMap)
121	#endif
122
123	/**
124	* Gets the set index of the current CPU.
125	*
126	* This always returns 0 when in raw-mode context because there is only ever
127	* one EMT in that context (at least presently).
128	*/
129	#ifdef IN_RC
130	# define PGMRZDYNMAP_CUR_CPU() (0)
131	#else
132	# define PGMRZDYNMAP_CUR_CPU() RTMpCpuIdToSetIndex(RTMpCpuId())
133	#endif
134
135	/** PGMRZDYNMAP::u32Magic. (Jens Christian Bugge Wesseltoft) */
136	#define PGMRZDYNMAP_MAGIC UINT32_C(0x19640201)
137
138
139	/** Zaps an set entry. */
140	#define PGMRZDYNMAP_ZAP_ENTRY(pEntry) \
141	do \
142	{ \
143	(pEntry)->iPage = UINT16_MAX; \
144	(pEntry)->cRefs = 0; \
145	(pEntry)->cInlinedRefs = 0; \
146	(pEntry)->cUnrefs = 0; \
147	} while (0)
148
149
150	/*******************************************************************************
151	* Structures and Typedefs *
152	*******************************************************************************/
153	#ifdef IN_RING0
154	/**
155	* Ring-0 dynamic mapping cache segment.
156	*
157	* The dynamic mapping cache can be extended with additional segments if the
158	* load is found to be too high. This done the next time a VM is created, under
159	* the protection of the init mutex. The arrays is reallocated and the new
160	* segment is added to the end of these. Nothing is rehashed of course, as the
161	* indexes / addresses must remain unchanged.
162	*
163	* This structure is only modified while owning the init mutex or during module
164	* init / term.
165	*/
166	typedef struct PGMR0DYNMAPSEG
167	{
168	/** Pointer to the next segment. */
169	struct PGMR0DYNMAPSEG *pNext;
170	/** The memory object for the virtual address range that we're abusing. */
171	RTR0MEMOBJ hMemObj;
172	/** The start page in the cache. (I.e. index into the arrays.) */
173	uint16_t iPage;
174	/** The number of pages this segment contributes. */
175	uint16_t cPages;
176	/** The number of page tables. */
177	uint16_t cPTs;
178	/** The memory objects for the page tables. */
179	RTR0MEMOBJ ahMemObjPTs[1];
180	} PGMR0DYNMAPSEG;
181	/** Pointer to a ring-0 dynamic mapping cache segment. */
182	typedef PGMR0DYNMAPSEG *PPGMR0DYNMAPSEG;
183
184
185	/**
186	* Ring-0 dynamic mapping cache entry.
187	*
188	* @sa PGMRZDYNMAPENTRY, PGMRCDYNMAPENTRY.
189	*/
190	typedef struct PGMR0DYNMAPENTRY
191	{
192	/** The physical address of the currently mapped page.
193	* This is duplicate for three reasons: cache locality, cache policy of the PT
194	* mappings and sanity checks. */
195	RTHCPHYS HCPhys;
196	/** Pointer to the page. */
197	void *pvPage;
198	/** The number of references. */
199	int32_t volatile cRefs;
200	/** PTE pointer union. */
201	union PGMR0DYNMAPENTRY_PPTE
202	{
203	/** PTE pointer, 32-bit legacy version. */
204	PX86PTE pLegacy;
205	/** PTE pointer, PAE version. */
206	PX86PTEPAE pPae;
207	/** PTE pointer, the void version. */
208	void *pv;
209	} uPte;
210	# ifndef IN_RC
211	/** CPUs that haven't invalidated this entry after it's last update. */
212	RTCPUSET PendingSet;
213	# endif
214	} PGMR0DYNMAPENTRY;
215	/** Pointer a mapping cache entry for the ring-0.
216	* @sa PPGMRZDYNMAPENTRY, PPGMRCDYNMAPENTRY, */
217	typedef PGMR0DYNMAPENTRY *PPGMR0DYNMAPENTRY;
218
219
220	/**
221	* Dynamic mapping cache for ring-0.
222	*
223	* This is initialized during VMMR0 module init but no segments are allocated
224	* at that time. Segments will be added when the first VM is started and
225	* removed again when the last VM shuts down, thus avoid consuming memory while
226	* dormant. At module termination, the remaining bits will be freed up.
227	*
228	* @sa PPGMRZDYNMAP, PGMRCDYNMAP.
229	*/
230	typedef struct PGMR0DYNMAP
231	{
232	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
233	uint32_t u32Magic;
234	# ifndef IN_RC
235	/** Spinlock serializing the normal operation of the cache. */
236	RTSPINLOCK hSpinlock;
237	# endif
238	/** Array for tracking and managing the pages. */
239	PPGMR0DYNMAPENTRY paPages;
240	/** The cache size given as a number of pages. */
241	uint32_t cPages;
242	/** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
243	bool fLegacyMode;
244	/** The current load.
245	* This does not include guard pages. */
246	uint32_t cLoad;
247	/** The max load ever.
248	* This is maintained to get trigger adding of more mapping space. */
249	uint32_t cMaxLoad;
250	# ifndef IN_RC
251	/** Initialization / termination lock. */
252	RTSEMFASTMUTEX hInitLock;
253	# endif
254	/** The number of guard pages. */
255	uint32_t cGuardPages;
256	/** The number of users (protected by hInitLock). */
257	uint32_t cUsers;
258	# ifndef IN_RC
259	/** Array containing a copy of the original page tables.
260	* The entries are either X86PTE or X86PTEPAE according to fLegacyMode. */
261	void *pvSavedPTEs;
262	/** List of segments. */
263	PPGMR0DYNMAPSEG pSegHead;
264	/** The paging mode. */
265	SUPPAGINGMODE enmPgMode;
266	# endif
267	} PGMR0DYNMAP;
268
269
270	/**
271	* Paging level data.
272	*/
273	typedef struct PGMR0DYNMAPPGLVL
274	{
275	uint32_t cLevels; /*< The number of levels. /
276	struct
277	{
278	RTHCPHYS HCPhys; /**< The address of the page for the current level,
279	* i.e. what hMemObj/hMapObj is currently mapping. */
280	RTHCPHYS fPhysMask; /*< Mask for extracting HCPhys from uEntry. /
281	RTR0MEMOBJ hMemObj; /*< Memory object for HCPhys, PAGE_SIZE. /
282	RTR0MEMOBJ hMapObj; /*< Mapping object for hMemObj. /
283	uint32_t fPtrShift; /*< The pointer shift count. /
284	uint64_t fPtrMask; /*< The mask to apply to the shifted pointer to get the table index. /
285	uint64_t fAndMask; /*< And mask to check entry flags. /
286	uint64_t fResMask; /*< The result from applying fAndMask. /
287	union
288	{
289	void pv; /< hMapObj address. /
290	PX86PGUINT paLegacy; /*< Legacy table view. /
291	PX86PGPAEUINT paPae; /*< PAE/AMD64 table view. /
292	} u;
293	} a[4];
294	} PGMR0DYNMAPPGLVL;
295	/** Pointer to paging level data. */
296	typedef PGMR0DYNMAPPGLVL *PPGMR0DYNMAPPGLVL;
297	#endif
298
299	/** Mapping cache entry for the current context.
300	* @sa PGMR0DYNMAPENTRY, PGMRCDYNMAPENTRY */
301	typedef CTX_MID(PGM,DYNMAPENTRY) PGMRZDYNMAPENTRY;
302	/** Pointer a mapping cache entry for the current context.
303	* @sa PGMR0DYNMAPENTRY, PGMRCDYNMAPENTRY */
304	typedef PGMRZDYNMAPENTRY *PPGMRZDYNMAPENTRY;
305
306	/** Pointer the mapping cache instance for the current context.
307	* @sa PGMR0DYNMAP, PGMRCDYNMAP */
308	typedef CTX_MID(PGM,DYNMAP) *PPGMRZDYNMAP;
309
310
311
312	/*******************************************************************************
313	* Global Variables *
314	*******************************************************************************/
315	#ifdef IN_RING0
316	/** Pointer to the ring-0 dynamic mapping cache. */
317	static PGMR0DYNMAP *g_pPGMR0DynMap;
318	#endif
319	/** For overflow testing. */
320	static bool g_fPGMR0DynMapTestRunning = false;
321
322
323	/*******************************************************************************
324	* Internal Functions *
325	*******************************************************************************/
326	static void pgmRZDynMapReleasePage(PPGMRZDYNMAP pThis, uint32_t iPage, uint32_t cRefs);
327	#ifdef IN_RING0
328	static int pgmR0DynMapSetup(PPGMRZDYNMAP pThis);
329	static int pgmR0DynMapExpand(PPGMRZDYNMAP pThis);
330	static void pgmR0DynMapTearDown(PPGMRZDYNMAP pThis);
331	#endif
332	#if 0 /def DEBUG/
333	static int pgmR0DynMapTest(PVM pVM);
334	#endif
335
336
337	/**
338	* Initializes the auto mapping sets for a VM.
339	*
340	* @returns VINF_SUCCESS on success, VERR_INTERNAL_ERROR on failure.
341	* @param pVM The VM in question.
342	*/
343	static int pgmRZDynMapInitAutoSetsForVM(PVM pVM)
344	{
345	VMCPUID idCpu = pVM->cCpus;
346	AssertReturn(idCpu > 0 && idCpu <= VMM_MAX_CPU_COUNT, VERR_INTERNAL_ERROR);
347	while (idCpu-- > 0)
348	{
349	PPGMMAPSET pSet = &pVM->aCpus[idCpu].pgm.s.AutoSet;
350	uint32_t j = RT_ELEMENTS(pSet->aEntries);
351	while (j-- > 0)
352	{
353	pSet->aEntries[j].pvPage = NULL;
354	pSet->aEntries[j].HCPhys = NIL_RTHCPHYS;
355	PGMRZDYNMAP_ZAP_ENTRY(&pSet->aEntries[j]);
356	}
357	pSet->cEntries = PGMMAPSET_CLOSED;
358	pSet->iSubset = UINT32_MAX;
359	pSet->iCpu = -1;
360	memset(&pSet->aiHashTable[0], 0xff, sizeof(pSet->aiHashTable));
361	}
362
363	return VINF_SUCCESS;
364	}
365
366
367	#ifdef IN_RING0
368
369	/**
370	* Initializes the ring-0 dynamic mapping cache.
371	*
372	* @returns VBox status code.
373	*/
374	VMMR0DECL(int) PGMR0DynMapInit(void)
375	{
376	Assert(!g_pPGMR0DynMap);
377
378	/*
379	* Create and initialize the cache instance.
380	*/
381	PPGMRZDYNMAP pThis = (PPGMRZDYNMAP)RTMemAllocZ(sizeof(*pThis));
382	AssertLogRelReturn(pThis, VERR_NO_MEMORY);
383	int rc = VINF_SUCCESS;
384	pThis->enmPgMode = SUPR0GetPagingMode();
385	switch (pThis->enmPgMode)
386	{
387	case SUPPAGINGMODE_32_BIT:
388	case SUPPAGINGMODE_32_BIT_GLOBAL:
389	pThis->fLegacyMode = false;
390	break;
391	case SUPPAGINGMODE_PAE:
392	case SUPPAGINGMODE_PAE_GLOBAL:
393	case SUPPAGINGMODE_PAE_NX:
394	case SUPPAGINGMODE_PAE_GLOBAL_NX:
395	case SUPPAGINGMODE_AMD64:
396	case SUPPAGINGMODE_AMD64_GLOBAL:
397	case SUPPAGINGMODE_AMD64_NX:
398	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
399	pThis->fLegacyMode = false;
400	break;
401	default:
402	rc = VERR_INTERNAL_ERROR;
403	break;
404	}
405	if (RT_SUCCESS(rc))
406	{
407	rc = RTSemFastMutexCreate(&pThis->hInitLock);
408	if (RT_SUCCESS(rc))
409	{
410	rc = RTSpinlockCreate(&pThis->hSpinlock);
411	if (RT_SUCCESS(rc))
412	{
413	pThis->u32Magic = PGMRZDYNMAP_MAGIC;
414	g_pPGMR0DynMap = pThis;
415	return VINF_SUCCESS;
416	}
417	RTSemFastMutexDestroy(pThis->hInitLock);
418	}
419	}
420	RTMemFree(pThis);
421	return rc;
422	}
423
424
425	/**
426	* Terminates the ring-0 dynamic mapping cache.
427	*/
428	VMMR0DECL(void) PGMR0DynMapTerm(void)
429	{
430	/*
431	* Destroy the cache.
432	*
433	* There is not supposed to be any races here, the loader should
434	* make sure about that. So, don't bother locking anything.
435	*
436	* The VM objects should all be destroyed by now, so there is no
437	* dangling users or anything like that to clean up. This routine
438	* is just a mirror image of PGMR0DynMapInit.
439	*/
440	PPGMRZDYNMAP pThis = g_pPGMR0DynMap;
441	if (pThis)
442	{
443	AssertPtr(pThis);
444	g_pPGMR0DynMap = NULL;
445
446	/* This should never happen, but in case it does try not to leak memory. */
447	AssertLogRelMsg(!pThis->cUsers && !pThis->paPages && !pThis->pvSavedPTEs && !pThis->cPages,
448	("cUsers=%d paPages=%p pvSavedPTEs=%p cPages=%#x\n",
449	pThis->cUsers, pThis->paPages, pThis->pvSavedPTEs, pThis->cPages));
450	if (pThis->paPages)
451	pgmR0DynMapTearDown(pThis);
452
453	/* Free the associated resources. */
454	RTSemFastMutexDestroy(pThis->hInitLock);
455	pThis->hInitLock = NIL_RTSEMFASTMUTEX;
456	RTSpinlockDestroy(pThis->hSpinlock);
457	pThis->hSpinlock = NIL_RTSPINLOCK;
458	pThis->u32Magic = UINT32_MAX;
459	RTMemFree(pThis);
460	}
461	}
462
463
464	/**
465	* Initializes the dynamic mapping cache for a new VM.
466	*
467	* @returns VBox status code.
468	* @param pVM Pointer to the shared VM structure.
469	*/
470	VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM)
471	{
472	AssertMsgReturn(!pVM->pgm.s.pvR0DynMapUsed, ("%p (pThis=%p)\n", pVM->pgm.s.pvR0DynMapUsed, g_pPGMR0DynMap), VERR_WRONG_ORDER);
473
474	/*
475	* Initialize the auto sets.
476	*/
477	int rc = pgmRZDynMapInitAutoSetsForVM(pVM);
478	if (RT_FAILURE(rc))
479	return rc;
480
481	/*
482	* Do we need the cache? Skip the last bit if we don't.
483	*/
484	if (!VMMIsHwVirtExtForced(pVM))
485	return VINF_SUCCESS;
486
487	/*
488	* Reference and if necessary setup or expand the cache.
489	*/
490	PPGMRZDYNMAP pThis = g_pPGMR0DynMap;
491	AssertPtrReturn(pThis, VERR_INTERNAL_ERROR);
492	rc = RTSemFastMutexRequest(pThis->hInitLock);
493	AssertLogRelRCReturn(rc, rc);
494
495	pThis->cUsers++;
496	if (pThis->cUsers == 1)
497	{
498	rc = pgmR0DynMapSetup(pThis);
499	#if 0 /def DEBUG/
500	if (RT_SUCCESS(rc))
501	{
502	rc = pgmR0DynMapTest(pVM);
503	if (RT_FAILURE(rc))
504	pgmR0DynMapTearDown(pThis);
505	}
506	#endif
507	}
508	else if (pThis->cMaxLoad > PGMR0DYNMAP_CALC_OVERLOAD(pThis->cPages - pThis->cGuardPages))
509	rc = pgmR0DynMapExpand(pThis);
510	if (RT_SUCCESS(rc))
511	pVM->pgm.s.pvR0DynMapUsed = pThis;
512	else
513	pThis->cUsers--;
514
515	RTSemFastMutexRelease(pThis->hInitLock);
516	return rc;
517	}
518
519
520	/**
521	* Terminates the dynamic mapping cache usage for a VM.
522	*
523	* @param pVM Pointer to the shared VM structure.
524	*/
525	VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM)
526	{
527	/*
528	* Return immediately if we're not using the cache.
529	*/
530	if (!pVM->pgm.s.pvR0DynMapUsed)
531	return;
532
533	PPGMRZDYNMAP pThis = g_pPGMR0DynMap;
534	AssertPtrReturnVoid(pThis);
535
536	int rc = RTSemFastMutexRequest(pThis->hInitLock);
537	AssertLogRelRCReturnVoid(rc);
538
539	if (pVM->pgm.s.pvR0DynMapUsed == pThis)
540	{
541	pVM->pgm.s.pvR0DynMapUsed = NULL;
542
543	#ifdef VBOX_STRICT
544	PGMR0DynMapAssertIntegrity();
545	#endif
546
547	/*
548	* Clean up and check the auto sets.
549	*/
550	VMCPUID idCpu = pVM->cCpus;
551	while (idCpu-- > 0)
552	{
553	PPGMMAPSET pSet = &pVM->aCpus[idCpu].pgm.s.AutoSet;
554	uint32_t j = pSet->cEntries;
555	if (j <= RT_ELEMENTS(pSet->aEntries))
556	{
557	/*
558	* The set is open, close it.
559	*/
560	while (j-- > 0)
561	{
562	int32_t cRefs = pSet->aEntries[j].cRefs;
563	uint32_t iPage = pSet->aEntries[j].iPage;
564	LogRel(("PGMR0DynMapTermVM: %d dangling refs to %#x\n", cRefs, iPage));
565	if (iPage < pThis->cPages && cRefs > 0)
566	pgmRZDynMapReleasePage(pThis, iPage, cRefs);
567	else
568	AssertLogRelMsgFailed(("cRefs=%d iPage=%#x cPages=%u\n", cRefs, iPage, pThis->cPages));
569
570	PGMRZDYNMAP_ZAP_ENTRY(&pSet->aEntries[j]);
571	}
572	pSet->cEntries = PGMMAPSET_CLOSED;
573	pSet->iSubset = UINT32_MAX;
574	pSet->iCpu = -1;
575	}
576	else
577	AssertMsg(j == PGMMAPSET_CLOSED, ("cEntries=%#x\n", j));
578
579	j = RT_ELEMENTS(pSet->aEntries);
580	while (j-- > 0)
581	{
582	Assert(pSet->aEntries[j].iPage == UINT16_MAX);
583	Assert(!pSet->aEntries[j].cRefs);
584	}
585	}
586
587	/*
588	* Release our reference to the mapping cache.
589	*/
590	Assert(pThis->cUsers > 0);
591	pThis->cUsers--;
592	if (!pThis->cUsers)
593	pgmR0DynMapTearDown(pThis);
594	}
595	else
596	AssertLogRelMsgFailed(("pvR0DynMapUsed=%p pThis=%p\n", pVM->pgm.s.pvR0DynMapUsed, pThis));
597
598	RTSemFastMutexRelease(pThis->hInitLock);
599	}
600
601
602	/**
603	* Shoots down the TLBs for all the cache pages, pgmR0DynMapTearDown helper.
604	*
605	* @param idCpu The current CPU.
606	* @param pvUser1 The dynamic mapping cache instance.
607	* @param pvUser2 Unused, NULL.
608	*/
609	static DECLCALLBACK(void) pgmR0DynMapShootDownTlbs(RTCPUID idCpu, void pvUser1, void pvUser2)
610	{
611	Assert(!pvUser2);
612	PPGMRZDYNMAP pThis = (PPGMRZDYNMAP)pvUser1;
613	Assert(pThis == g_pPGMR0DynMap);
614	PPGMRZDYNMAPENTRY paPages = pThis->paPages;
615	uint32_t iPage = pThis->cPages;
616	while (iPage-- > 0)
617	ASMInvalidatePage(paPages[iPage].pvPage);
618	}
619
620
621	/**
622	* Shoot down the TLBs for every single cache entry on all CPUs.
623	*
624	* @returns IPRT status code (RTMpOnAll).
625	* @param pThis The dynamic mapping cache instance.
626	*/
627	static int pgmR0DynMapTlbShootDown(PPGMRZDYNMAP pThis)
628	{
629	int rc = RTMpOnAll(pgmR0DynMapShootDownTlbs, pThis, NULL);
630	AssertRC(rc);
631	if (RT_FAILURE(rc))
632	{
633	uint32_t iPage = pThis->cPages;
634	while (iPage-- > 0)
635	ASMInvalidatePage(pThis->paPages[iPage].pvPage);
636	}
637	return rc;
638	}
639
640
641	/**
642	* Calculate the new cache size based on cMaxLoad statistics.
643	*
644	* @returns Number of pages.
645	* @param pThis The dynamic mapping cache instance.
646	* @param pcMinPages The minimal size in pages.
647	*/
648	static uint32_t pgmR0DynMapCalcNewSize(PPGMRZDYNMAP pThis, uint32_t *pcMinPages)
649	{
650	Assert(pThis->cPages <= PGMR0DYNMAP_MAX_PAGES);
651
652	/* cCpus * PGMR0DYNMAP_PAGES_PER_CPU(_MIN). */
653	RTCPUID cCpus = RTMpGetCount();
654	AssertReturn(cCpus > 0 && cCpus <= RTCPUSET_MAX_CPUS, 0);
655	uint32_t cPages = cCpus * PGMR0DYNMAP_PAGES_PER_CPU;
656	uint32_t cMinPages = cCpus * PGMR0DYNMAP_PAGES_PER_CPU_MIN;
657
658	/* adjust against cMaxLoad. */
659	AssertMsg(pThis->cMaxLoad <= PGMR0DYNMAP_MAX_PAGES, ("%#x\n", pThis->cMaxLoad));
660	if (pThis->cMaxLoad > PGMR0DYNMAP_MAX_PAGES)
661	pThis->cMaxLoad = 0;
662
663	while (pThis->cMaxLoad > PGMR0DYNMAP_CALC_OVERLOAD(cPages))
664	cPages += PGMR0DYNMAP_PAGES_PER_CPU;
665
666	if (pThis->cMaxLoad > cMinPages)
667	cMinPages = pThis->cMaxLoad;
668
669	/* adjust against max and current size. */
670	if (cPages < pThis->cPages)
671	cPages = pThis->cPages;
672	cPages *= PGMR0DYNMAP_GUARD_PAGES + 1;
673	if (cPages > PGMR0DYNMAP_MAX_PAGES)
674	cPages = PGMR0DYNMAP_MAX_PAGES;
675
676	if (cMinPages < pThis->cPages)
677	cMinPages = pThis->cPages;
678	cMinPages *= PGMR0DYNMAP_GUARD_PAGES + 1;
679	if (cMinPages > PGMR0DYNMAP_MAX_PAGES)
680	cMinPages = PGMR0DYNMAP_MAX_PAGES;
681
682	Assert(cMinPages);
683	*pcMinPages = cMinPages;
684	return cPages;
685	}
686
687
688	/**
689	* Initializes the paging level data.
690	*
691	* @param pThis The dynamic mapping cache instance.
692	* @param pPgLvl The paging level data.
693	*/
694	void pgmR0DynMapPagingArrayInit(PPGMRZDYNMAP pThis, PPGMR0DYNMAPPGLVL pPgLvl)
695	{
696	RTCCUINTREG cr4 = ASMGetCR4();
697	switch (pThis->enmPgMode)
698	{
699	case SUPPAGINGMODE_32_BIT:
700	case SUPPAGINGMODE_32_BIT_GLOBAL:
701	pPgLvl->cLevels = 2;
702	pPgLvl->a[0].fPhysMask = X86_CR3_PAGE_MASK;
703	pPgLvl->a[0].fAndMask = X86_PDE_P \| X86_PDE_RW \| (cr4 & X86_CR4_PSE ? X86_PDE_PS : 0);
704	pPgLvl->a[0].fResMask = X86_PDE_P \| X86_PDE_RW;
705	pPgLvl->a[0].fPtrMask = X86_PD_MASK;
706	pPgLvl->a[0].fPtrShift = X86_PD_SHIFT;
707
708	pPgLvl->a[1].fPhysMask = X86_PDE_PG_MASK;
709	pPgLvl->a[1].fAndMask = X86_PTE_P \| X86_PTE_RW;
710	pPgLvl->a[1].fResMask = X86_PTE_P \| X86_PTE_RW;
711	pPgLvl->a[1].fPtrMask = X86_PT_MASK;
712	pPgLvl->a[1].fPtrShift = X86_PT_SHIFT;
713	break;
714
715	case SUPPAGINGMODE_PAE:
716	case SUPPAGINGMODE_PAE_GLOBAL:
717	case SUPPAGINGMODE_PAE_NX:
718	case SUPPAGINGMODE_PAE_GLOBAL_NX:
719	pPgLvl->cLevels = 3;
720	pPgLvl->a[0].fPhysMask = X86_CR3_PAE_PAGE_MASK;
721	pPgLvl->a[0].fPtrMask = X86_PDPT_MASK_PAE;
722	pPgLvl->a[0].fPtrShift = X86_PDPT_SHIFT;
723	pPgLvl->a[0].fAndMask = X86_PDPE_P;
724	pPgLvl->a[0].fResMask = X86_PDPE_P;
725
726	pPgLvl->a[1].fPhysMask = X86_PDPE_PG_MASK;
727	pPgLvl->a[1].fPtrMask = X86_PD_PAE_MASK;
728	pPgLvl->a[1].fPtrShift = X86_PD_PAE_SHIFT;
729	pPgLvl->a[1].fAndMask = X86_PDE_P \| X86_PDE_RW \| (cr4 & X86_CR4_PSE ? X86_PDE_PS : 0);
730	pPgLvl->a[1].fResMask = X86_PDE_P \| X86_PDE_RW;
731
732	pPgLvl->a[2].fPhysMask = X86_PDE_PAE_PG_MASK;
733	pPgLvl->a[2].fPtrMask = X86_PT_PAE_MASK;
734	pPgLvl->a[2].fPtrShift = X86_PT_PAE_SHIFT;
735	pPgLvl->a[2].fAndMask = X86_PTE_P \| X86_PTE_RW;
736	pPgLvl->a[2].fResMask = X86_PTE_P \| X86_PTE_RW;
737	break;
738
739	case SUPPAGINGMODE_AMD64:
740	case SUPPAGINGMODE_AMD64_GLOBAL:
741	case SUPPAGINGMODE_AMD64_NX:
742	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
743	pPgLvl->cLevels = 4;
744	pPgLvl->a[0].fPhysMask = X86_CR3_AMD64_PAGE_MASK;
745	pPgLvl->a[0].fPtrShift = X86_PML4_SHIFT;
746	pPgLvl->a[0].fPtrMask = X86_PML4_MASK;
747	pPgLvl->a[0].fAndMask = X86_PML4E_P \| X86_PML4E_RW;
748	pPgLvl->a[0].fResMask = X86_PML4E_P \| X86_PML4E_RW;
749
750	pPgLvl->a[1].fPhysMask = X86_PML4E_PG_MASK;
751	pPgLvl->a[1].fPtrShift = X86_PDPT_SHIFT;
752	pPgLvl->a[1].fPtrMask = X86_PDPT_MASK_AMD64;
753	pPgLvl->a[1].fAndMask = X86_PDPE_P \| X86_PDPE_RW /** @todo check for X86_PDPT_PS support. */;
754	pPgLvl->a[1].fResMask = X86_PDPE_P \| X86_PDPE_RW;
755
756	pPgLvl->a[2].fPhysMask = X86_PDPE_PG_MASK;
757	pPgLvl->a[2].fPtrShift = X86_PD_PAE_SHIFT;
758	pPgLvl->a[2].fPtrMask = X86_PD_PAE_MASK;
759	pPgLvl->a[2].fAndMask = X86_PDE_P \| X86_PDE_RW \| (cr4 & X86_CR4_PSE ? X86_PDE_PS : 0);
760	pPgLvl->a[2].fResMask = X86_PDE_P \| X86_PDE_RW;
761
762	pPgLvl->a[3].fPhysMask = X86_PDE_PAE_PG_MASK;
763	pPgLvl->a[3].fPtrShift = X86_PT_PAE_SHIFT;
764	pPgLvl->a[3].fPtrMask = X86_PT_PAE_MASK;
765	pPgLvl->a[3].fAndMask = X86_PTE_P \| X86_PTE_RW;
766	pPgLvl->a[3].fResMask = X86_PTE_P \| X86_PTE_RW;
767	break;
768
769	default:
770	AssertFailed();
771	pPgLvl->cLevels = 0;
772	break;
773	}
774
775	for (uint32_t i = 0; i < 4; i++) /* ASSUMING array size. */
776	{
777	pPgLvl->a[i].HCPhys = NIL_RTHCPHYS;
778	pPgLvl->a[i].hMapObj = NIL_RTR0MEMOBJ;
779	pPgLvl->a[i].hMemObj = NIL_RTR0MEMOBJ;
780	pPgLvl->a[i].u.pv = NULL;
781	}
782	}
783
784
785	/**
786	* Maps a PTE.
787	*
788	* This will update the segment structure when new PTs are mapped.
789	*
790	* It also assumes that we (for paranoid reasons) wish to establish a mapping
791	* chain from CR3 to the PT that all corresponds to the processor we're
792	* currently running on, and go about this by running with interrupts disabled
793	* and restarting from CR3 for every change.
794	*
795	* @returns VBox status code, VINF_TRY_AGAIN if we changed any mappings and had
796	* to re-enable interrupts.
797	* @param pThis The dynamic mapping cache instance.
798	* @param pPgLvl The paging level structure.
799	* @param pvPage The page.
800	* @param pSeg The segment.
801	* @param cMaxPTs The max number of PTs expected in the segment.
802	* @param ppvPTE Where to store the PTE address.
803	*/
804	static int pgmR0DynMapPagingArrayMapPte(PPGMRZDYNMAP pThis, PPGMR0DYNMAPPGLVL pPgLvl, void *pvPage,
805	PPGMR0DYNMAPSEG pSeg, uint32_t cMaxPTs, void **ppvPTE)
806	{
807	Assert(!(ASMGetFlags() & X86_EFL_IF));
808	void *pvEntry = NULL;
809	X86PGPAEUINT uEntry = ASMGetCR3();
810	for (uint32_t i = 0; i < pPgLvl->cLevels; i++)
811	{
812	RTHCPHYS HCPhys = uEntry & pPgLvl->a[i].fPhysMask;
813	if (pPgLvl->a[i].HCPhys != HCPhys)
814	{
815	/*
816	* Need to remap this level.
817	* The final level, the PT, will not be freed since that is what it's all about.
818	*/
819	ASMIntEnable();
820	if (i + 1 == pPgLvl->cLevels)
821	AssertReturn(pSeg->cPTs < cMaxPTs, VERR_INTERNAL_ERROR);
822	else
823	{
824	int rc2 = RTR0MemObjFree(pPgLvl->a[i].hMemObj, true /* fFreeMappings */); AssertRC(rc2);
825	pPgLvl->a[i].hMemObj = pPgLvl->a[i].hMapObj = NIL_RTR0MEMOBJ;
826	}
827
828	int rc = RTR0MemObjEnterPhys(&pPgLvl->a[i].hMemObj, HCPhys, PAGE_SIZE, RTMEM_CACHE_POLICY_DONT_CARE);
829	if (RT_SUCCESS(rc))
830	{
831	rc = RTR0MemObjMapKernel(&pPgLvl->a[i].hMapObj, pPgLvl->a[i].hMemObj,
832	(void )-1 / pvFixed /, 0 / cbAlignment */,
833	RTMEM_PROT_WRITE \| RTMEM_PROT_READ);
834	if (RT_SUCCESS(rc))
835	{
836	pPgLvl->a[i].u.pv = RTR0MemObjAddress(pPgLvl->a[i].hMapObj);
837	AssertMsg(((uintptr_t)pPgLvl->a[i].u.pv & ~(uintptr_t)PAGE_OFFSET_MASK), ("%p\n", pPgLvl->a[i].u.pv));
838	pPgLvl->a[i].HCPhys = HCPhys;
839	if (i + 1 == pPgLvl->cLevels)
840	pSeg->ahMemObjPTs[pSeg->cPTs++] = pPgLvl->a[i].hMemObj;
841	ASMIntDisable();
842	return VINF_TRY_AGAIN;
843	}
844
845	pPgLvl->a[i].hMapObj = NIL_RTR0MEMOBJ;
846	}
847	else
848	pPgLvl->a[i].hMemObj = NIL_RTR0MEMOBJ;
849	pPgLvl->a[i].HCPhys = NIL_RTHCPHYS;
850	return rc;
851	}
852
853	/*
854	* The next level.
855	*/
856	uint32_t iEntry = ((uint64_t)(uintptr_t)pvPage >> pPgLvl->a[i].fPtrShift) & pPgLvl->a[i].fPtrMask;
857	if (pThis->fLegacyMode)
858	{
859	pvEntry = &pPgLvl->a[i].u.paLegacy[iEntry];
860	uEntry = pPgLvl->a[i].u.paLegacy[iEntry];
861	}
862	else
863	{
864	pvEntry = &pPgLvl->a[i].u.paPae[iEntry];
865	uEntry = pPgLvl->a[i].u.paPae[iEntry];
866	}
867
868	if ((uEntry & pPgLvl->a[i].fAndMask) != pPgLvl->a[i].fResMask)
869	{
870	LogRel(("PGMR0DynMap: internal error - iPgLvl=%u cLevels=%u uEntry=%#llx fAnd=%#llx fRes=%#llx got=%#llx\n"
871	"PGMR0DynMap: pv=%p pvPage=%p iEntry=%#x fLegacyMode=%RTbool\n",
872	i, pPgLvl->cLevels, uEntry, pPgLvl->a[i].fAndMask, pPgLvl->a[i].fResMask, uEntry & pPgLvl->a[i].fAndMask,
873	pPgLvl->a[i].u.pv, pvPage, iEntry, pThis->fLegacyMode));
874	return VERR_INTERNAL_ERROR;
875	}
876	/Log(("#%d: iEntry=%4d uEntry=%#llx pvEntry=%p HCPhys=%RHp \n", i, iEntry, uEntry, pvEntry, pPgLvl->a[i].HCPhys));/
877	}
878
879	/* made it thru without needing to remap anything. */
880	*ppvPTE = pvEntry;
881	return VINF_SUCCESS;
882	}
883
884
885	/**
886	* Sets up a guard page.
887	*
888	* @param pThis The dynamic mapping cache instance.
889	* @param pPage The page.
890	*/
891	DECLINLINE(void) pgmR0DynMapSetupGuardPage(PPGMRZDYNMAP pThis, PPGMRZDYNMAPENTRY pPage)
892	{
893	memset(pPage->pvPage, 0xfd, PAGE_SIZE);
894	pPage->cRefs = PGMR0DYNMAP_GUARD_PAGE_REF_COUNT;
895	pPage->HCPhys = PGMR0DYNMAP_GUARD_PAGE_HCPHYS;
896	#ifdef PGMR0DYNMAP_GUARD_NP
897	ASMAtomicBitClear(pPage->uPte.pv, X86_PTE_BIT_P);
898	#else
899	if (pThis->fLegacyMode)
900	ASMAtomicWriteU32(&pPage->uPte.pLegacy->u, PGMR0DYNMAP_GUARD_PAGE_LEGACY_PTE);
901	else
902	ASMAtomicWriteU64(&pPage->uPte.pPae->u, PGMR0DYNMAP_GUARD_PAGE_PAE_PTE);
903	#endif
904	pThis->cGuardPages++;
905	}
906
907
908	/**
909	* Adds a new segment of the specified size.
910	*
911	* @returns VBox status code.
912	* @param pThis The dynamic mapping cache instance.
913	* @param cPages The size of the new segment, give as a page count.
914	*/
915	static int pgmR0DynMapAddSeg(PPGMRZDYNMAP pThis, uint32_t cPages)
916	{
917	int rc2;
918	AssertReturn(ASMGetFlags() & X86_EFL_IF, VERR_PREEMPT_DISABLED);
919
920	/*
921	* Do the array reallocations first.
922	* (The pages array has to be replaced behind the spinlock of course.)
923	*/
924	void pvSavedPTEs = RTMemRealloc(pThis->pvSavedPTEs, (pThis->fLegacyMode ? sizeof(X86PGUINT) : sizeof(X86PGPAEUINT)) (pThis->cPages + cPages));
925	if (!pvSavedPTEs)
926	return VERR_NO_MEMORY;
927	pThis->pvSavedPTEs = pvSavedPTEs;
928
929	void pvPages = RTMemAllocZ(sizeof(pThis->paPages[0]) (pThis->cPages + cPages));
930	if (!pvPages)
931	{
932	pvSavedPTEs = RTMemRealloc(pThis->pvSavedPTEs, (pThis->fLegacyMode ? sizeof(X86PGUINT) : sizeof(X86PGPAEUINT)) * pThis->cPages);
933	if (pvSavedPTEs)
934	pThis->pvSavedPTEs = pvSavedPTEs;
935	return VERR_NO_MEMORY;
936	}
937
938	PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis);
939
940	memcpy(pvPages, pThis->paPages, sizeof(pThis->paPages[0]) * pThis->cPages);
941	void *pvToFree = pThis->paPages;
942	pThis->paPages = (PPGMRZDYNMAPENTRY)pvPages;
943
944	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
945	RTMemFree(pvToFree);
946
947	/*
948	* Allocate the segment structure and pages of memory, then touch all the pages (paranoia).
949	*/
950	uint32_t cMaxPTs = cPages / (pThis->fLegacyMode ? X86_PG_ENTRIES : X86_PG_PAE_ENTRIES) + 2;
951	PPGMR0DYNMAPSEG pSeg = (PPGMR0DYNMAPSEG)RTMemAllocZ(RT_UOFFSETOF(PGMR0DYNMAPSEG, ahMemObjPTs[cMaxPTs]));
952	if (!pSeg)
953	return VERR_NO_MEMORY;
954	pSeg->pNext = NULL;
955	pSeg->cPages = cPages;
956	pSeg->iPage = pThis->cPages;
957	pSeg->cPTs = 0;
958	int rc = RTR0MemObjAllocPage(&pSeg->hMemObj, cPages << PAGE_SHIFT, false);
959	if (RT_SUCCESS(rc))
960	{
961	uint8_t pbPage = (uint8_t )RTR0MemObjAddress(pSeg->hMemObj);
962	AssertMsg(VALID_PTR(pbPage) && !((uintptr_t)pbPage & PAGE_OFFSET_MASK), ("%p\n", pbPage));
963	memset(pbPage, 0xfe, cPages << PAGE_SHIFT);
964
965	/*
966	* Walk thru the pages and set them up with a mapping of their PTE and everything.
967	*/
968	ASMIntDisable();
969	PGMR0DYNMAPPGLVL PgLvl;
970	pgmR0DynMapPagingArrayInit(pThis, &PgLvl);
971	uint32_t const iEndPage = pSeg->iPage + cPages;
972	for (uint32_t iPage = pSeg->iPage;
973	iPage < iEndPage;
974	iPage++, pbPage += PAGE_SIZE)
975	{
976	/* Initialize the page data. */
977	pThis->paPages[iPage].HCPhys = NIL_RTHCPHYS;
978	pThis->paPages[iPage].pvPage = pbPage;
979	pThis->paPages[iPage].cRefs = 0;
980	pThis->paPages[iPage].uPte.pPae = 0;
981	#ifndef IN_RC
982	RTCpuSetFill(&pThis->paPages[iPage].PendingSet);
983	#endif
984
985	/* Map its page table, retry until we've got a clean run (paranoia). */
986	do
987	rc = pgmR0DynMapPagingArrayMapPte(pThis, &PgLvl, pbPage, pSeg, cMaxPTs,
988	&pThis->paPages[iPage].uPte.pv);
989	while (rc == VINF_TRY_AGAIN);
990	if (RT_FAILURE(rc))
991	break;
992
993	/* Save the PTE. */
994	if (pThis->fLegacyMode)
995	((PX86PGUINT)pThis->pvSavedPTEs)[iPage] = pThis->paPages[iPage].uPte.pLegacy->u;
996	else
997	((PX86PGPAEUINT)pThis->pvSavedPTEs)[iPage] = pThis->paPages[iPage].uPte.pPae->u;
998
999	#ifdef VBOX_STRICT
1000	/* Check that we've got the right entry. */
1001	RTHCPHYS HCPhysPage = RTR0MemObjGetPagePhysAddr(pSeg->hMemObj, iPage - pSeg->iPage);
1002	RTHCPHYS HCPhysPte = pThis->fLegacyMode
1003	? pThis->paPages[iPage].uPte.pLegacy->u & X86_PTE_PG_MASK
1004	: pThis->paPages[iPage].uPte.pPae->u & X86_PTE_PAE_PG_MASK;
1005	if (HCPhysPage != HCPhysPte)
1006	{
1007	LogRel(("pgmR0DynMapAddSeg: internal error - page #%u HCPhysPage=%RHp HCPhysPte=%RHp pbPage=%p pvPte=%p\n",
1008	iPage - pSeg->iPage, HCPhysPage, HCPhysPte, pbPage, pThis->paPages[iPage].uPte.pv));
1009	rc = VERR_INTERNAL_ERROR;
1010	break;
1011	}
1012	#endif
1013	} /* for each page */
1014	ASMIntEnable();
1015
1016	/* cleanup non-PT mappings */
1017	for (uint32_t i = 0; i < PgLvl.cLevels - 1; i++)
1018	RTR0MemObjFree(PgLvl.a[i].hMemObj, true /* fFreeMappings */);
1019
1020	if (RT_SUCCESS(rc))
1021	{
1022	#if PGMR0DYNMAP_GUARD_PAGES > 0
1023	/*
1024	* Setup guard pages.
1025	* (Note: TLBs will be shot down later on.)
1026	*/
1027	uint32_t iPage = pSeg->iPage;
1028	while (iPage < iEndPage)
1029	{
1030	for (uint32_t iGPg = 0; iGPg < PGMR0DYNMAP_GUARD_PAGES && iPage < iEndPage; iGPg++, iPage++)
1031	pgmR0DynMapSetupGuardPage(pThis, &pThis->paPages[iPage]);
1032	iPage++; /* the guarded page */
1033	}
1034
1035	/* Make sure the very last page is a guard page too. */
1036	iPage = iEndPage - 1;
1037	if (pThis->paPages[iPage].cRefs != PGMR0DYNMAP_GUARD_PAGE_REF_COUNT)
1038	pgmR0DynMapSetupGuardPage(pThis, &pThis->paPages[iPage]);
1039	#endif /* PGMR0DYNMAP_GUARD_PAGES > 0 */
1040
1041	/*
1042	* Commit it by adding the segment to the list and updating the page count.
1043	*/
1044	pSeg->pNext = pThis->pSegHead;
1045	pThis->pSegHead = pSeg;
1046	pThis->cPages += cPages;
1047	return VINF_SUCCESS;
1048	}
1049
1050	/*
1051	* Bail out.
1052	*/
1053	while (pSeg->cPTs-- > 0)
1054	{
1055	rc2 = RTR0MemObjFree(pSeg->ahMemObjPTs[pSeg->cPTs], true /* fFreeMappings */);
1056	AssertRC(rc2);
1057	pSeg->ahMemObjPTs[pSeg->cPTs] = NIL_RTR0MEMOBJ;
1058	}
1059
1060	rc2 = RTR0MemObjFree(pSeg->hMemObj, true /* fFreeMappings */);
1061	AssertRC(rc2);
1062	pSeg->hMemObj = NIL_RTR0MEMOBJ;
1063	}
1064	RTMemFree(pSeg);
1065
1066	/* Don't bother resizing the arrays, but free them if we're the only user. */
1067	if (!pThis->cPages)
1068	{
1069	RTMemFree(pThis->paPages);
1070	pThis->paPages = NULL;
1071	RTMemFree(pThis->pvSavedPTEs);
1072	pThis->pvSavedPTEs = NULL;
1073	}
1074	return rc;
1075	}
1076
1077
1078	/**
1079	* Called by PGMR0DynMapInitVM under the init lock.
1080	*
1081	* @returns VBox status code.
1082	* @param pThis The dynamic mapping cache instance.
1083	*/
1084	static int pgmR0DynMapSetup(PPGMRZDYNMAP pThis)
1085	{
1086	/*
1087	* Calc the size and add a segment of that size.
1088	*/
1089	uint32_t cMinPages;
1090	uint32_t cPages = pgmR0DynMapCalcNewSize(pThis, &cMinPages);
1091	AssertReturn(cPages, VERR_INTERNAL_ERROR);
1092	int rc = pgmR0DynMapAddSeg(pThis, cPages);
1093	if (rc == VERR_NO_MEMORY)
1094	{
1095	/*
1096	* Try adding smaller segments.
1097	*/
1098	do
1099	rc = pgmR0DynMapAddSeg(pThis, PGMR0DYNMAP_SMALL_SEG_PAGES);
1100	while (RT_SUCCESS(rc) && pThis->cPages < cPages);
1101	if (rc == VERR_NO_MEMORY && pThis->cPages >= cMinPages)
1102	rc = VINF_SUCCESS;
1103	if (rc == VERR_NO_MEMORY)
1104	{
1105	if (pThis->cPages)
1106	pgmR0DynMapTearDown(pThis);
1107	rc = VERR_PGM_DYNMAP_SETUP_ERROR;
1108	}
1109	}
1110	Assert(ASMGetFlags() & X86_EFL_IF);
1111
1112	#if PGMR0DYNMAP_GUARD_PAGES > 0
1113	/* paranoia */
1114	if (RT_SUCCESS(rc))
1115	pgmR0DynMapTlbShootDown(pThis);
1116	#endif
1117	return rc;
1118	}
1119
1120
1121	/**
1122	* Called by PGMR0DynMapInitVM under the init lock.
1123	*
1124	* @returns VBox status code.
1125	* @param pThis The dynamic mapping cache instance.
1126	*/
1127	static int pgmR0DynMapExpand(PPGMRZDYNMAP pThis)
1128	{
1129	/*
1130	* Calc the new target size and add a segment of the appropriate size.
1131	*/
1132	uint32_t cMinPages;
1133	uint32_t cPages = pgmR0DynMapCalcNewSize(pThis, &cMinPages);
1134	AssertReturn(cPages, VERR_INTERNAL_ERROR);
1135	if (pThis->cPages >= cPages)
1136	return VINF_SUCCESS;
1137
1138	uint32_t cAdd = cPages - pThis->cPages;
1139	int rc = pgmR0DynMapAddSeg(pThis, cAdd);
1140	if (rc == VERR_NO_MEMORY)
1141	{
1142	/*
1143	* Try adding smaller segments.
1144	*/
1145	do
1146	rc = pgmR0DynMapAddSeg(pThis, PGMR0DYNMAP_SMALL_SEG_PAGES);
1147	while (RT_SUCCESS(rc) && pThis->cPages < cPages);
1148	if (rc == VERR_NO_MEMORY && pThis->cPages >= cMinPages)
1149	rc = VINF_SUCCESS;
1150	if (rc == VERR_NO_MEMORY)
1151	rc = VERR_PGM_DYNMAP_EXPAND_ERROR;
1152	}
1153	Assert(ASMGetFlags() & X86_EFL_IF);
1154
1155	#if PGMR0DYNMAP_GUARD_PAGES > 0
1156	/* paranoia */
1157	if (RT_SUCCESS(rc))
1158	pgmR0DynMapTlbShootDown(pThis);
1159	#endif
1160	return rc;
1161	}
1162
1163
1164	/**
1165	* Called by PGMR0DynMapTermVM under the init lock.
1166	*
1167	* @returns VBox status code.
1168	* @param pThis The dynamic mapping cache instance.
1169	*/
1170	static void pgmR0DynMapTearDown(PPGMRZDYNMAP pThis)
1171	{
1172	/*
1173	* Restore the original page table entries
1174	*/
1175	PPGMRZDYNMAPENTRY paPages = pThis->paPages;
1176	uint32_t iPage = pThis->cPages;
1177	if (pThis->fLegacyMode)
1178	{
1179	X86PGUINT const paSavedPTEs = (X86PGUINT const )pThis->pvSavedPTEs;
1180	while (iPage-- > 0)
1181	{
1182	X86PGUINT uOld = paPages[iPage].uPte.pLegacy->u;
1183	X86PGUINT uOld2 = uOld; NOREF(uOld2);
1184	X86PGUINT uNew = paSavedPTEs[iPage];
1185	while (!ASMAtomicCmpXchgExU32(&paPages[iPage].uPte.pLegacy->u, uNew, uOld, &uOld))
1186	AssertMsgFailed(("uOld=%#x uOld2=%#x uNew=%#x\n", uOld, uOld2, uNew));
1187	Assert(paPages[iPage].uPte.pLegacy->u == paSavedPTEs[iPage]);
1188	}
1189	}
1190	else
1191	{
1192	X86PGPAEUINT const paSavedPTEs = (X86PGPAEUINT const )pThis->pvSavedPTEs;
1193	while (iPage-- > 0)
1194	{
1195	X86PGPAEUINT uOld = paPages[iPage].uPte.pPae->u;
1196	X86PGPAEUINT uOld2 = uOld; NOREF(uOld2);
1197	X86PGPAEUINT uNew = paSavedPTEs[iPage];
1198	while (!ASMAtomicCmpXchgExU64(&paPages[iPage].uPte.pPae->u, uNew, uOld, &uOld))
1199	AssertMsgFailed(("uOld=%#llx uOld2=%#llx uNew=%#llx\n", uOld, uOld2, uNew));
1200	Assert(paPages[iPage].uPte.pPae->u == paSavedPTEs[iPage]);
1201	}
1202	}
1203
1204	/*
1205	* Shoot down the TLBs on all CPUs before freeing them.
1206	*/
1207	pgmR0DynMapTlbShootDown(pThis);
1208
1209	/*
1210	* Free the segments.
1211	*/
1212	while (pThis->pSegHead)
1213	{
1214	int rc;
1215	PPGMR0DYNMAPSEG pSeg = pThis->pSegHead;
1216	pThis->pSegHead = pSeg->pNext;
1217
1218	uint32_t iPT = pSeg->cPTs;
1219	while (iPT-- > 0)
1220	{
1221	rc = RTR0MemObjFree(pSeg->ahMemObjPTs[iPT], true /* fFreeMappings */); AssertRC(rc);
1222	pSeg->ahMemObjPTs[iPT] = NIL_RTR0MEMOBJ;
1223	}
1224	rc = RTR0MemObjFree(pSeg->hMemObj, true /* fFreeMappings */); AssertRC(rc);
1225	pSeg->hMemObj = NIL_RTR0MEMOBJ;
1226	pSeg->pNext = NULL;
1227	pSeg->iPage = UINT16_MAX;
1228	pSeg->cPages = 0;
1229	pSeg->cPTs = 0;
1230	RTMemFree(pSeg);
1231	}
1232
1233	/*
1234	* Free the arrays and restore the initial state.
1235	* The cLoadMax value is left behind for the next setup.
1236	*/
1237	RTMemFree(pThis->paPages);
1238	pThis->paPages = NULL;
1239	RTMemFree(pThis->pvSavedPTEs);
1240	pThis->pvSavedPTEs = NULL;
1241	pThis->cPages = 0;
1242	pThis->cLoad = 0;
1243	pThis->cGuardPages = 0;
1244	}
1245
1246	#endif /* IN_RING0 */
1247	#ifdef IN_RC
1248
1249	/**
1250	* Initializes the dynamic mapping cache in raw-mode context.
1251	*
1252	* @returns VBox status code.
1253	* @param pVM The VM handle.
1254	*/
1255	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM)
1256	{
1257	/*
1258	* Allocate and initialize the instance data and page array.
1259	*/
1260	PPGMRZDYNMAP pThis;
1261	size_t const cPages = MM_HYPER_DYNAMIC_SIZE / PAGE_SIZE;
1262	size_t const cb = RT_ALIGN_Z(sizeof(*pThis), 32)
1263	+ sizeof(PGMRZDYNMAPENTRY) * cPages;
1264	int rc = MMHyperAlloc(pVM, cb, 32, MM_TAG_PGM, (void **)&pThis);
1265	if (RT_FAILURE(rc))
1266	return rc;
1267
1268	pThis->u32Magic = PGMRZDYNMAP_MAGIC;
1269	pThis->paPages = RT_ALIGN_PT(pThis + 1, 32, PPGMRZDYNMAPENTRY);
1270	pThis->cPages = cPages;
1271	pThis->fLegacyMode = PGMGetHostMode(pVM) == PGMMODE_32_BIT;
1272	pThis->cLoad = 0;
1273	pThis->cMaxLoad = 0;
1274	pThis->cGuardPages = 0;
1275	pThis->cUsers = 1;
1276
1277	for (size_t iPage = 0; iPage < cPages; iPage++)
1278	{
1279	pThis->paPages[iPage].HCPhys = NIL_RTHCPHYS;
1280	pThis->paPages[iPage].pvPage = pVM->pgm.s.pbDynPageMapBaseGC + iPage * PAGE_SIZE;
1281	pThis->paPages[iPage].cRefs = 0;
1282	if (pThis->fLegacyMode)
1283	pThis->paPages[iPage].uPte.pLegacy = &pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage];
1284	else
1285	pThis->paPages[iPage].uPte.pPae = &pVM->pgm.s.paDynPageMapPaePTEsGC[iPage];
1286	}
1287
1288	pVM->pgm.s.pRCDynMap = pThis;
1289
1290	/*
1291	* Initialize the autosets the VM.
1292	*/
1293	rc = pgmRZDynMapInitAutoSetsForVM(pVM);
1294	if (RT_FAILURE(rc))
1295	return rc;
1296
1297	return VINF_SUCCESS;
1298	}
1299
1300	#endif /* IN_RC */
1301
1302	/**
1303	* Release references to a page, caller owns the spin lock.
1304	*
1305	* @param pThis The dynamic mapping cache instance.
1306	* @param iPage The page.
1307	* @param cRefs The number of references to release.
1308	*/
1309	DECLINLINE(void) pgmRZDynMapReleasePageLocked(PPGMRZDYNMAP pThis, uint32_t iPage, int32_t cRefs)
1310	{
1311	cRefs = ASMAtomicSubS32(&pThis->paPages[iPage].cRefs, cRefs) - cRefs;
1312	AssertMsg(cRefs >= 0, ("%d\n", cRefs));
1313	if (!cRefs)
1314	pThis->cLoad--;
1315	}
1316
1317
1318	/**
1319	* Release references to a page, caller does not own the spin lock.
1320	*
1321	* @param pThis The dynamic mapping cache instance.
1322	* @param iPage The page.
1323	* @param cRefs The number of references to release.
1324	*/
1325	static void pgmRZDynMapReleasePage(PPGMRZDYNMAP pThis, uint32_t iPage, uint32_t cRefs)
1326	{
1327	PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis);
1328	pgmRZDynMapReleasePageLocked(pThis, iPage, cRefs);
1329	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
1330	}
1331
1332
1333	/**
1334	* pgmR0DynMapPage worker that deals with the tedious bits.
1335	*
1336	* @returns The page index on success, UINT32_MAX on failure.
1337	* @param pThis The dynamic mapping cache instance.
1338	* @param HCPhys The address of the page to be mapped.
1339	* @param iPage The page index pgmR0DynMapPage hashed HCPhys to.
1340	* @param pVCpu The current CPU, for statistics.
1341	* @param pfNew Set to @c true if a new entry was made and @c false if
1342	* an old entry was found and reused.
1343	*/
1344	static uint32_t pgmR0DynMapPageSlow(PPGMRZDYNMAP pThis, RTHCPHYS HCPhys, uint32_t iPage, PVMCPU pVCpu, bool *pfNew)
1345	{
1346	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageSlow);
1347
1348	/*
1349	* Check if any of the first 3 pages are unreferenced since the caller
1350	* already has made sure they aren't matching.
1351	*/
1352	#ifdef VBOX_WITH_STATISTICS
1353	bool fLooped = false;
1354	#endif
1355	uint32_t const cPages = pThis->cPages;
1356	PPGMRZDYNMAPENTRY paPages = pThis->paPages;
1357	uint32_t iFreePage;
1358	if (!paPages[iPage].cRefs)
1359	iFreePage = iPage;
1360	else if (!paPages[(iPage + 1) % cPages].cRefs)
1361	iFreePage = (iPage + 1) % cPages;
1362	else if (!paPages[(iPage + 2) % cPages].cRefs)
1363	iFreePage = (iPage + 2) % cPages;
1364	else
1365	{
1366	/*
1367	* Search for an unused or matching entry.
1368	*/
1369	iFreePage = (iPage + 3) % cPages;
1370	for (;;)
1371	{
1372	if (paPages[iFreePage].HCPhys == HCPhys)
1373	{
1374	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageSlowLoopHits);
1375	*pfNew = false;
1376	return iFreePage;
1377	}
1378	if (!paPages[iFreePage].cRefs)
1379	break;
1380
1381	/* advance */
1382	iFreePage = (iFreePage + 1) % cPages;
1383	if (RT_UNLIKELY(iFreePage == iPage))
1384	return UINT32_MAX;
1385	}
1386	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageSlowLoopMisses);
1387	#ifdef VBOX_WITH_STATISTICS
1388	fLooped = true;
1389	#endif
1390	}
1391	Assert(iFreePage < cPages);
1392
1393	#if 0 //def VBOX_WITH_STATISTICS
1394	/* Check for lost hits. */
1395	if (!fLooped)
1396	for (uint32_t iPage2 = (iPage + 3) % cPages; iPage2 != iPage; iPage2 = (iPage2 + 1) % cPages)
1397	if (paPages[iPage2].HCPhys == HCPhys)
1398	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZDynMapPageSlowLostHits);
1399	#endif
1400
1401	/*
1402	* Setup the new entry.
1403	*/
1404	*pfNew = true;
1405	/Log6(("pgmR0DynMapPageSlow: old - %RHp %#x %#llx\n", paPages[iFreePage].HCPhys, paPages[iFreePage].cRefs, paPages[iFreePage].uPte.pPae->u));/
1406	paPages[iFreePage].HCPhys = HCPhys;
1407	#ifndef IN_RC
1408	RTCpuSetFill(&paPages[iFreePage].PendingSet);
1409	#endif
1410	if (pThis->fLegacyMode)
1411	{
1412	X86PGUINT uOld = paPages[iFreePage].uPte.pLegacy->u;
1413	X86PGUINT uOld2 = uOld; NOREF(uOld2);
1414	X86PGUINT uNew = (uOld & (X86_PTE_G \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1415	\| X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D
1416	\| (HCPhys & X86_PTE_PG_MASK);
1417	while (!ASMAtomicCmpXchgExU32(&paPages[iFreePage].uPte.pLegacy->u, uNew, uOld, &uOld))
1418	AssertMsgFailed(("uOld=%#x uOld2=%#x uNew=%#x\n", uOld, uOld2, uNew));
1419	Assert(paPages[iFreePage].uPte.pLegacy->u == uNew);
1420	}
1421	else
1422	{
1423	X86PGPAEUINT uOld = paPages[iFreePage].uPte.pPae->u;
1424	X86PGPAEUINT uOld2 = uOld; NOREF(uOld2);
1425	X86PGPAEUINT uNew = (uOld & (X86_PTE_G \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1426	\| X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D
1427	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1428	while (!ASMAtomicCmpXchgExU64(&paPages[iFreePage].uPte.pPae->u, uNew, uOld, &uOld))
1429	AssertMsgFailed(("uOld=%#llx uOld2=%#llx uNew=%#llx\n", uOld, uOld2, uNew));
1430	Assert(paPages[iFreePage].uPte.pPae->u == uNew);
1431	/Log6(("pgmR0DynMapPageSlow: #%x - %RHp %p %#llx\n", iFreePage, HCPhys, paPages[iFreePage].pvPage, uNew));/
1432	}
1433	return iFreePage;
1434	}
1435
1436
1437	/**
1438	* Maps a page into the pool.
1439	*
1440	* @returns Page index on success, UINT32_MAX on failure.
1441	* @param pThis The dynamic mapping cache instance.
1442	* @param HCPhys The address of the page to be mapped.
1443	* @param iRealCpu The real cpu set index. (optimization)
1444	* @param pVCpu The current CPU (for statistics).
1445	* @param ppvPage Where to the page address.
1446	*/
1447	DECLINLINE(uint32_t) pgmR0DynMapPage(PPGMRZDYNMAP pThis, RTHCPHYS HCPhys, int32_t iRealCpu, PVMCPU pVCpu, void **ppvPage)
1448	{
1449	PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis);
1450	AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
1451	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPage);
1452
1453	/*
1454	* Find an entry, if possible a matching one. The HCPhys address is hashed
1455	* down to a page index, collisions are handled by linear searching.
1456	* Optimized for a hit in the first 3 pages.
1457	*
1458	* Field easy hits here and defer the tedious searching and inserting
1459	* to pgmR0DynMapPageSlow().
1460	*/
1461	bool fNew = false;
1462	uint32_t const cPages = pThis->cPages;
1463	uint32_t iPage = (HCPhys >> PAGE_SHIFT) % cPages;
1464	PPGMRZDYNMAPENTRY paPages = pThis->paPages;
1465	if (RT_LIKELY(paPages[iPage].HCPhys == HCPhys))
1466	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageHits0);
1467	else
1468	{
1469	uint32_t iPage2 = (iPage + 1) % cPages;
1470	if (RT_LIKELY(paPages[iPage2].HCPhys == HCPhys))
1471	{
1472	iPage = iPage2;
1473	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageHits1);
1474	}
1475	else
1476	{
1477	iPage2 = (iPage + 2) % cPages;
1478	if (paPages[iPage2].HCPhys == HCPhys)
1479	{
1480	iPage = iPage2;
1481	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageHits2);
1482	}
1483	else
1484	{
1485	iPage = pgmR0DynMapPageSlow(pThis, HCPhys, iPage, pVCpu, &fNew);
1486	if (RT_UNLIKELY(iPage == UINT32_MAX))
1487	{
1488	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
1489	*ppvPage = NULL;
1490	return iPage;
1491	}
1492	}
1493	}
1494	}
1495
1496	/*
1497	* Reference it, update statistics and get the return address.
1498	*/
1499	int32_t cRefs = ASMAtomicIncS32(&paPages[iPage].cRefs);
1500	if (cRefs == 1)
1501	{
1502	pThis->cLoad++;
1503	if (pThis->cLoad > pThis->cMaxLoad)
1504	pThis->cMaxLoad = pThis->cLoad;
1505	AssertMsg(pThis->cLoad <= pThis->cPages - pThis->cGuardPages, ("%d/%d\n", pThis->cLoad, pThis->cPages - pThis->cGuardPages));
1506	}
1507	else if (RT_UNLIKELY(cRefs <= 0))
1508	{
1509	ASMAtomicDecS32(&paPages[iPage].cRefs);
1510	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
1511	*ppvPage = NULL;
1512	AssertLogRelMsgFailedReturn(("cRefs=%d iPage=%p HCPhys=%RHp\n", cRefs, iPage, HCPhys), UINT32_MAX);
1513	}
1514	void *pvPage = paPages[iPage].pvPage;
1515
1516	#ifndef IN_RC
1517	/*
1518	* Invalidate the entry?
1519	*/
1520	bool fInvalidateIt = RTCpuSetIsMemberByIndex(&paPages[iPage].PendingSet, iRealCpu);
1521	if (RT_UNLIKELY(fInvalidateIt))
1522	RTCpuSetDelByIndex(&paPages[iPage].PendingSet, iRealCpu);
1523	#endif
1524
1525	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
1526
1527	/*
1528	* Do the actual invalidation outside the spinlock.
1529	*/
1530	#ifdef IN_RC
1531	if (RT_UNLIKELY(fNew))
1532	#else
1533	if (RT_UNLIKELY(fInvalidateIt))
1534	#endif
1535	{
1536	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapPageInvlPg);
1537	ASMInvalidatePage(pvPage);
1538	}
1539
1540	*ppvPage = pvPage;
1541	return iPage;
1542	}
1543
1544
1545	/**
1546	* Assert the the integrity of the pool.
1547	*
1548	* @returns VBox status code.
1549	*/
1550	static int pgmRZDynMapAssertIntegrity(PPGMRZDYNMAP pThis)
1551	{
1552	/*
1553	* Basic pool stuff that doesn't require any lock, just assumes we're a user.
1554	*/
1555	if (!pThis)
1556	return VINF_SUCCESS;
1557	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1558	AssertReturn(pThis->u32Magic == PGMRZDYNMAP_MAGIC, VERR_INVALID_MAGIC);
1559	if (!pThis->cUsers)
1560	return VERR_INVALID_PARAMETER;
1561
1562
1563	int rc = VINF_SUCCESS;
1564	PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis);
1565
1566	#define CHECK_RET(expr, a) \
1567	do { \
1568	if (RT_UNLIKELY(!(expr))) \
1569	{ \
1570	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis); \
1571	RTAssertMsg1Weak(#expr, __LINE__, __FILE__, __PRETTY_FUNCTION__); \
1572	RTAssertMsg2Weak a; \
1573	return VERR_INTERNAL_ERROR; \
1574	} \
1575	} while (0)
1576
1577	/*
1578	* Check that the PTEs are correct.
1579	*/
1580	uint32_t cGuard = 0;
1581	uint32_t cLoad = 0;
1582	PPGMRZDYNMAPENTRY paPages = pThis->paPages;
1583	uint32_t iPage = pThis->cPages;
1584	if (pThis->fLegacyMode)
1585	{
1586	#ifdef IN_RING0
1587	PCX86PGUINT paSavedPTEs = (PCX86PGUINT)pThis->pvSavedPTEs; NOREF(paSavedPTEs);
1588	#endif
1589	while (iPage-- > 0)
1590	{
1591	CHECK_RET(!((uintptr_t)paPages[iPage].pvPage & PAGE_OFFSET_MASK), ("#%u: %p\n", iPage, paPages[iPage].pvPage));
1592	if ( paPages[iPage].cRefs == PGMR0DYNMAP_GUARD_PAGE_REF_COUNT
1593	&& paPages[iPage].HCPhys == PGMR0DYNMAP_GUARD_PAGE_HCPHYS)
1594	{
1595	#ifdef PGMR0DYNMAP_GUARD_NP
1596	CHECK_RET(paPages[iPage].uPte.pLegacy->u == (paSavedPTEs[iPage] & ~(X86PGUINT)X86_PTE_P),
1597	("#%u: %#x %#x", iPage, paPages[iPage].uPte.pLegacy->u, paSavedPTEs[iPage]));
1598	#else
1599	CHECK_RET(paPages[iPage].uPte.pLegacy->u == PGMR0DYNMAP_GUARD_PAGE_LEGACY_PTE,
1600	("#%u: %#x", iPage, paPages[iPage].uPte.pLegacy->u));
1601	#endif
1602	cGuard++;
1603	}
1604	else if (paPages[iPage].HCPhys != NIL_RTHCPHYS)
1605	{
1606	CHECK_RET(!(paPages[iPage].HCPhys & PAGE_OFFSET_MASK), ("#%u: %RHp\n", iPage, paPages[iPage].HCPhys));
1607	X86PGUINT uPte = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D
1608	#ifdef IN_RING0
1609	\| (paSavedPTEs[iPage] & (X86_PTE_G \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1610	#endif
1611	\| (paPages[iPage].HCPhys & X86_PTE_PAE_PG_MASK);
1612	CHECK_RET(paPages[iPage].uPte.pLegacy->u == uPte,
1613	("#%u: %#x %#x", iPage, paPages[iPage].uPte.pLegacy->u, uPte));
1614	if (paPages[iPage].cRefs)
1615	cLoad++;
1616	}
1617	#ifdef IN_RING0
1618	else
1619	CHECK_RET(paPages[iPage].uPte.pLegacy->u == paSavedPTEs[iPage],
1620	("#%u: %#x %#x", iPage, paPages[iPage].uPte.pLegacy->u, paSavedPTEs[iPage]));
1621	#endif
1622	}
1623	}
1624	else
1625	{
1626	#ifdef IN_RING0
1627	PCX86PGPAEUINT paSavedPTEs = (PCX86PGPAEUINT)pThis->pvSavedPTEs; NOREF(paSavedPTEs);
1628	#endif
1629	while (iPage-- > 0)
1630	{
1631	CHECK_RET(!((uintptr_t)paPages[iPage].pvPage & PAGE_OFFSET_MASK), ("#%u: %p\n", iPage, paPages[iPage].pvPage));
1632	if ( paPages[iPage].cRefs == PGMR0DYNMAP_GUARD_PAGE_REF_COUNT
1633	&& paPages[iPage].HCPhys == PGMR0DYNMAP_GUARD_PAGE_HCPHYS)
1634	{
1635	#ifdef PGMR0DYNMAP_GUARD_NP
1636	CHECK_RET(paPages[iPage].uPte.pPae->u == (paSavedPTEs[iPage] & ~(X86PGPAEUINT)X86_PTE_P),
1637	("#%u: %#llx %#llx", iPage, paPages[iPage].uPte.pPae->u, paSavedPTEs[iPage]));
1638	#else
1639	CHECK_RET(paPages[iPage].uPte.pPae->u == PGMR0DYNMAP_GUARD_PAGE_PAE_PTE,
1640	("#%u: %#llx", iPage, paPages[iPage].uPte.pPae->u));
1641	#endif
1642	cGuard++;
1643	}
1644	else if (paPages[iPage].HCPhys != NIL_RTHCPHYS)
1645	{
1646	CHECK_RET(!(paPages[iPage].HCPhys & PAGE_OFFSET_MASK), ("#%u: %RHp\n", iPage, paPages[iPage].HCPhys));
1647	X86PGPAEUINT uPte = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D
1648	#ifdef IN_RING0
1649	\| (paSavedPTEs[iPage] & (X86_PTE_G \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1650	#endif
1651	\| (paPages[iPage].HCPhys & X86_PTE_PAE_PG_MASK);
1652	CHECK_RET(paPages[iPage].uPte.pPae->u == uPte,
1653	("#%u: %#llx %#llx", iPage, paPages[iPage].uPte.pLegacy->u, uPte));
1654	if (paPages[iPage].cRefs)
1655	cLoad++;
1656	}
1657	#ifdef IN_RING0
1658	else
1659	CHECK_RET(paPages[iPage].uPte.pPae->u == paSavedPTEs[iPage],
1660	("#%u: %#llx %#llx", iPage, paPages[iPage].uPte.pPae->u, paSavedPTEs[iPage]));
1661	#endif
1662	}
1663	}
1664
1665	CHECK_RET(cLoad == pThis->cLoad, ("%u %u\n", cLoad, pThis->cLoad));
1666	CHECK_RET(cGuard == pThis->cGuardPages, ("%u %u\n", cGuard, pThis->cGuardPages));
1667
1668	#undef CHECK_RET
1669	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
1670	return VINF_SUCCESS;
1671	}
1672
1673	#ifdef IN_RING0
1674	/**
1675	* Assert the the integrity of the pool.
1676	*
1677	* @returns VBox status code.
1678	*/
1679	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void)
1680	{
1681	return pgmRZDynMapAssertIntegrity(g_pPGMR0DynMap);
1682	}
1683	#endif /* IN_RING0 */
1684
1685	#ifdef IN_RC
1686	/**
1687	* Assert the the integrity of the pool.
1688	*
1689	* @returns VBox status code.
1690	*/
1691	VMMRCDECL(int) PGMRCDynMapAssertIntegrity(PVM pVM)
1692	{
1693	return pgmRZDynMapAssertIntegrity((PPGMRZDYNMAP)pVM->pgm.s.pRCDynMap);
1694	}
1695	#endif /* IN_RC */
1696
1697
1698	/**
1699	* As a final resort for a (somewhat) full auto set or full cache, try merge
1700	* duplicate entries and flush the ones we can.
1701	*
1702	* @param pSet The set.
1703	*/
1704	static void pgmDynMapOptimizeAutoSet(PPGMMAPSET pSet)
1705	{
1706	LogFlow(("pgmDynMapOptimizeAutoSet\n"));
1707
1708	for (uint32_t i = 0 ; i < pSet->cEntries; i++)
1709	{
1710	/*
1711	* Try merge entries.
1712	*/
1713	uint16_t const iPage = pSet->aEntries[i].iPage;
1714	uint32_t j = i + 1;
1715	while ( j < pSet->cEntries
1716	&& ( pSet->iSubset == UINT32_MAX
1717	\|\| pSet->iSubset < pSet->cEntries) )
1718	{
1719	if (pSet->aEntries[j].iPage != iPage)
1720	j++;
1721	else
1722	{
1723	uint32_t const cHardRefs = (uint32_t)pSet->aEntries[i].cRefs
1724	+ (uint32_t)pSet->aEntries[j].cRefs;
1725	uint32_t cInlinedRefs = (uint32_t)pSet->aEntries[i].cInlinedRefs
1726	+ (uint32_t)pSet->aEntries[j].cInlinedRefs;
1727	uint32_t cUnrefs = (uint32_t)pSet->aEntries[i].cUnrefs
1728	+ (uint32_t)pSet->aEntries[j].cUnrefs;
1729	uint32_t cSub = RT_MIN(cUnrefs, cInlinedRefs);
1730	cInlinedRefs -= cSub;
1731	cUnrefs -= cSub;
1732
1733	if ( cHardRefs < UINT16_MAX
1734	&& cInlinedRefs < UINT16_MAX
1735	&& cUnrefs < UINT16_MAX)
1736	{
1737	/* merge j into i removing j. */
1738	Log2(("pgmDynMapOptimizeAutoSet: Merging #%u into #%u\n", j, i));
1739	pSet->aEntries[i].cRefs = cHardRefs;
1740	pSet->aEntries[i].cInlinedRefs = cInlinedRefs;
1741	pSet->aEntries[i].cUnrefs = cUnrefs;
1742	pSet->cEntries--;
1743	if (j < pSet->cEntries)
1744	{
1745	pSet->aEntries[j] = pSet->aEntries[pSet->cEntries];
1746	PGMRZDYNMAP_ZAP_ENTRY(&pSet->aEntries[pSet->cEntries]);
1747	}
1748	else
1749	PGMRZDYNMAP_ZAP_ENTRY(&pSet->aEntries[j]);
1750	}
1751	#if 0 /* too complicated, skip it. */
1752	else
1753	{
1754	/* migrate the max number of refs from j into i and quit the inner loop. */
1755	uint32_t cMigrate = UINT16_MAX - 1 - pSet->aEntries[i].cRefs;
1756	Assert(pSet->aEntries[j].cRefs > cMigrate);
1757	pSet->aEntries[j].cRefs -= cMigrate;
1758	pSet->aEntries[i].cRefs = UINT16_MAX - 1;
1759	break;
1760	}
1761	#endif
1762	}
1763	}
1764
1765	/*
1766	* Try make use of the unused hinting (cUnrefs) to evict entries
1767	* from both the set as well as the mapping cache.
1768	*/
1769
1770	uint32_t const cTotalRefs = (uint32_t)pSet->aEntries[i].cRefs + pSet->aEntries[i].cInlinedRefs;
1771	Log2(("pgmDynMapOptimizeAutoSet: #%u/%u/%u pvPage=%p iPage=%u cRefs=%u cInlinedRefs=%u cUnrefs=%u cTotalRefs=%u\n",
1772	i,
1773	pSet->iSubset,
1774	pSet->cEntries,
1775	pSet->aEntries[i].pvPage,
1776	pSet->aEntries[i].iPage,
1777	pSet->aEntries[i].cRefs,
1778	pSet->aEntries[i].cInlinedRefs,
1779	pSet->aEntries[i].cUnrefs,
1780	cTotalRefs));
1781	Assert(cTotalRefs >= pSet->aEntries[i].cUnrefs);
1782
1783	if ( cTotalRefs == pSet->aEntries[i].cUnrefs
1784	&& ( pSet->iSubset == UINT32_MAX
1785	\|\| pSet->iSubset < pSet->cEntries)
1786	)
1787	{
1788	Log2(("pgmDynMapOptimizeAutoSet: Releasing iPage=%d/%p\n", pSet->aEntries[i].iPage, pSet->aEntries[i].pvPage));
1789	//LogFlow(("pgmDynMapOptimizeAutoSet: Releasing iPage=%d/%p\n", pSet->aEntries[i].iPage, pSet->aEntries[i].pvPage));
1790	pgmRZDynMapReleasePage(PGMRZDYNMAP_SET_2_DYNMAP(pSet),
1791	pSet->aEntries[i].iPage,
1792	pSet->aEntries[i].cRefs);
1793	pSet->cEntries--;
1794	if (i < pSet->cEntries)
1795	{
1796	pSet->aEntries[i] = pSet->aEntries[pSet->cEntries];
1797	PGMRZDYNMAP_ZAP_ENTRY(&pSet->aEntries[pSet->cEntries]);
1798	}
1799
1800	i--;
1801	}
1802	}
1803	}
1804
1805
1806
1807
1808	/**
1809	* Signals the start of a new set of mappings.
1810	*
1811	* Mostly for strictness. PGMDynMapHCPage won't work unless this
1812	* API is called.
1813	*
1814	* @param pVCpu The shared data for the current virtual CPU.
1815	*/
1816	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu)
1817	{
1818	LogFlow(("PGMRZDynMapStartAutoSet:\n"));
1819	Assert(pVCpu->pgm.s.AutoSet.cEntries == PGMMAPSET_CLOSED);
1820	Assert(pVCpu->pgm.s.AutoSet.iSubset == UINT32_MAX);
1821	pVCpu->pgm.s.AutoSet.cEntries = 0;
1822	pVCpu->pgm.s.AutoSet.iCpu = PGMRZDYNMAP_CUR_CPU();
1823	}
1824
1825
1826	#ifdef IN_RING0
1827	/**
1828	* Starts or migrates the autoset of a virtual CPU.
1829	*
1830	* This is used by HWACCMR0Enter. When we've longjumped out of the HWACCM
1831	* execution loop with the set open, we'll migrate it when re-entering. While
1832	* under normal circumstances, we'll start it so VMXR0LoadGuestState can access
1833	* guest memory.
1834	*
1835	* @returns @c true if started, @c false if migrated.
1836	* @param pVCpu The shared data for the current virtual CPU.
1837	* @thread EMT
1838	*/
1839	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu)
1840	{
1841	bool fStartIt = pVCpu->pgm.s.AutoSet.cEntries == PGMMAPSET_CLOSED;
1842	if (fStartIt)
1843	PGMRZDynMapStartAutoSet(pVCpu);
1844	else
1845	PGMR0DynMapMigrateAutoSet(pVCpu);
1846	return fStartIt;
1847	}
1848	#endif /* IN_RING0 */
1849
1850
1851	/**
1852	* Worker that performs the actual flushing of the set.
1853	*
1854	* @param pSet The set to flush.
1855	* @param cEntries The number of entries.
1856	*/
1857	DECLINLINE(void) pgmDynMapFlushAutoSetWorker(PPGMMAPSET pSet, uint32_t cEntries)
1858	{
1859	/*
1860	* Release any pages it's referencing.
1861	*/
1862	if ( cEntries != 0
1863	&& RT_LIKELY(cEntries <= RT_ELEMENTS(pSet->aEntries)))
1864	{
1865	PPGMRZDYNMAP pThis = PGMRZDYNMAP_SET_2_DYNMAP(pSet);
1866	PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis);
1867
1868	uint32_t i = cEntries;
1869	while (i-- > 0)
1870	{
1871	uint32_t iPage = pSet->aEntries[i].iPage;
1872	Assert(iPage < pThis->cPages);
1873	int32_t cRefs = pSet->aEntries[i].cRefs;
1874	Assert(cRefs > 0);
1875	pgmRZDynMapReleasePageLocked(pThis, iPage, cRefs);
1876
1877	PGMRZDYNMAP_ZAP_ENTRY(&pSet->aEntries[i]);
1878	}
1879
1880	Assert(pThis->cLoad <= pThis->cPages - pThis->cGuardPages);
1881	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
1882	}
1883	}
1884
1885
1886	/**
1887	* Releases the dynamic memory mappings made by PGMDynMapHCPage and associates
1888	* since the PGMDynMapStartAutoSet call.
1889	*
1890	* @param pVCpu The shared data for the current virtual CPU.
1891	*/
1892	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu)
1893	{
1894	PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
1895
1896	/*
1897	* Close and flush the set.
1898	*/
1899	uint32_t cEntries = pSet->cEntries;
1900	AssertReturnVoid(cEntries != PGMMAPSET_CLOSED);
1901	pSet->cEntries = PGMMAPSET_CLOSED;
1902	pSet->iSubset = UINT32_MAX;
1903	pSet->iCpu = -1;
1904
1905	#ifdef IN_RC
1906	if (RT_ELEMENTS(pSet->aEntries) > MM_HYPER_DYNAMIC_SIZE / PAGE_SIZE)
1907	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->aStatRZDynMapSetFilledPct[(cEntries * 10 / (MM_HYPER_DYNAMIC_SIZE / PAGE_SIZE)) % 11]);
1908	else
1909	#endif
1910	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->aStatRZDynMapSetFilledPct[(cEntries * 10 / RT_ELEMENTS(pSet->aEntries)) % 11]);
1911	AssertMsg(cEntries < PGMMAPSET_MAX_FILL, ("%u\n", cEntries));
1912	if (cEntries > RT_ELEMENTS(pSet->aEntries) * 50 / 100)
1913	Log(("PGMRZDynMapReleaseAutoSet: cEntries=%d\n", cEntries));
1914	else
1915	LogFlow(("PGMRZDynMapReleaseAutoSet: cEntries=%d\n", cEntries));
1916
1917	pgmDynMapFlushAutoSetWorker(pSet, cEntries);
1918	}
1919
1920
1921	/**
1922	* Flushes the set if it's above a certain threshold.
1923	*
1924	* @param pVCpu The shared data for the current virtual CPU.
1925	*/
1926	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu)
1927	{
1928	PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
1929	AssertMsg(pSet->iCpu == PGMRZDYNMAP_CUR_CPU(), ("%d %d efl=%#x\n", pSet->iCpu, PGMRZDYNMAP_CUR_CPU(), ASMGetFlags()));
1930
1931	/*
1932	* Only flush it if it's 45% full.
1933	*/
1934	uint32_t cEntries = pSet->cEntries;
1935	AssertReturnVoid(cEntries != PGMMAPSET_CLOSED);
1936	#ifdef IN_RC
1937	if (RT_ELEMENTS(pSet->aEntries) > MM_HYPER_DYNAMIC_SIZE / PAGE_SIZE)
1938	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->aStatRZDynMapSetFilledPct[(cEntries * 10 / (MM_HYPER_DYNAMIC_SIZE / PAGE_SIZE)) % 11]);
1939	else
1940	#endif
1941	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->aStatRZDynMapSetFilledPct[(cEntries * 10 / RT_ELEMENTS(pSet->aEntries)) % 11]);
1942	if (cEntries >= RT_ELEMENTS(pSet->aEntries) * 45 / 100)
1943	{
1944	pSet->cEntries = 0;
1945
1946	AssertMsg(cEntries < PGMMAPSET_MAX_FILL, ("%u\n", cEntries));
1947	Log(("PGMDynMapFlushAutoSet: cEntries=%d\n", pSet->cEntries));
1948
1949	pgmDynMapFlushAutoSetWorker(pSet, cEntries);
1950	AssertMsg(pSet->iCpu == PGMRZDYNMAP_CUR_CPU(), ("%d %d efl=%#x\n", pSet->iCpu, PGMRZDYNMAP_CUR_CPU(), ASMGetFlags()));
1951	}
1952	}
1953
1954
1955	#ifndef IN_RC
1956	/**
1957	* Migrates the automatic mapping set of the current vCPU if it's active and
1958	* necessary.
1959	*
1960	* This is called when re-entering the hardware assisted execution mode after a
1961	* nip down to ring-3. We run the risk that the CPU might have change and we
1962	* will therefore make sure all the cache entries currently in the auto set will
1963	* be valid on the new CPU. If the cpu didn't change nothing will happen as all
1964	* the entries will have been flagged as invalidated.
1965	*
1966	* @param pVCpu The shared data for the current virtual CPU.
1967	* @thread EMT
1968	*/
1969	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu)
1970	{
1971	LogFlow(("PGMR0DynMapMigrateAutoSet\n"));
1972	PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
1973	int32_t iRealCpu = PGMRZDYNMAP_CUR_CPU();
1974	if (pSet->iCpu != iRealCpu)
1975	{
1976	uint32_t i = pSet->cEntries;
1977	if (i != PGMMAPSET_CLOSED)
1978	{
1979	AssertMsg(i <= RT_ELEMENTS(pSet->aEntries), ("%#x (%u)\n", i, i));
1980	if (i != 0 && RT_LIKELY(i <= RT_ELEMENTS(pSet->aEntries)))
1981	{
1982	PPGMRZDYNMAP pThis = PGMRZDYNMAP_SET_2_DYNMAP(pSet);
1983	PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis);
1984
1985	while (i-- > 0)
1986	{
1987	Assert(pSet->aEntries[i].cRefs > 0);
1988	uint32_t iPage = pSet->aEntries[i].iPage;
1989	Assert(iPage < pThis->cPages);
1990	if (RTCpuSetIsMemberByIndex(&pThis->paPages[iPage].PendingSet, iRealCpu))
1991	{
1992	RTCpuSetDelByIndex(&pThis->paPages[iPage].PendingSet, iRealCpu);
1993	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
1994
1995	ASMInvalidatePage(pThis->paPages[iPage].pvPage);
1996	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapMigrateInvlPg);
1997
1998	PGMRZDYNMAP_SPINLOCK_REACQUIRE(pThis);
1999	}
2000	}
2001
2002	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
2003	}
2004	}
2005	pSet->iCpu = iRealCpu;
2006	}
2007	}
2008	#endif /* !IN_RC */
2009
2010
2011	/**
2012	* Worker function that flushes the current subset.
2013	*
2014	* This is called when the set is popped or when the set
2015	* hash a too high load. As also pointed out elsewhere, the
2016	* whole subset thing is a hack for working around code that
2017	* accesses too many pages. Like PGMPool.
2018	*
2019	* @param pSet The set which subset to flush.
2020	*/
2021	static void pgmDynMapFlushSubset(PPGMMAPSET pSet)
2022	{
2023	uint32_t iSubset = pSet->iSubset;
2024	uint32_t i = pSet->cEntries;
2025	Assert(i <= RT_ELEMENTS(pSet->aEntries));
2026	if ( i > iSubset
2027	&& i <= RT_ELEMENTS(pSet->aEntries))
2028	{
2029	Log(("pgmDynMapFlushSubset: cEntries=%d iSubset=%d\n", pSet->cEntries, iSubset));
2030	pSet->cEntries = iSubset;
2031
2032	PPGMRZDYNMAP pThis = PGMRZDYNMAP_SET_2_DYNMAP(pSet);
2033	PGMRZDYNMAP_SPINLOCK_ACQUIRE(pThis);
2034
2035	while (i-- > iSubset)
2036	{
2037	uint32_t iPage = pSet->aEntries[i].iPage;
2038	Assert(iPage < pThis->cPages);
2039	int32_t cRefs = pSet->aEntries[i].cRefs;
2040	Assert(cRefs > 0);
2041	pgmRZDynMapReleasePageLocked(pThis, iPage, cRefs);
2042
2043	PGMRZDYNMAP_ZAP_ENTRY(&pSet->aEntries[i]);
2044	}
2045
2046	PGMRZDYNMAP_SPINLOCK_RELEASE(pThis);
2047	}
2048	}
2049
2050
2051	/**
2052	* Creates a subset.
2053	*
2054	* A subset is a hack to avoid having to rewrite code that touches a lot of
2055	* pages. It prevents the mapping set from being overflowed by automatically
2056	* flushing previous mappings when a certain threshold is reached.
2057	*
2058	* Pages mapped after calling this function are only valid until the next page
2059	* is mapped.
2060	*
2061	* @returns The index of the previous subset. Pass this to
2062	* PGMDynMapPopAutoSubset when popping it.
2063	* @param pVCpu Pointer to the virtual cpu data.
2064	*/
2065	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu)
2066	{
2067	PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
2068	AssertReturn(pSet->cEntries != PGMMAPSET_CLOSED, UINT32_MAX);
2069	uint32_t iPrevSubset = pSet->iSubset;
2070	LogFlow(("PGMRZDynMapPushAutoSubset: pVCpu=%p iPrevSubset=%u\n", pVCpu, iPrevSubset));
2071
2072	#ifdef IN_RC
2073	/* kludge */
2074	if (pSet->cEntries > MM_HYPER_DYNAMIC_SIZE / PAGE_SIZE / 2)
2075	{
2076	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapSetOptimize);
2077	pgmDynMapOptimizeAutoSet(pSet);
2078	}
2079	#endif
2080
2081	pSet->iSubset = pSet->cEntries;
2082	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapSubsets);
2083
2084	return iPrevSubset;
2085	}
2086
2087
2088	/**
2089	* Pops a subset created by a previous call to PGMDynMapPushAutoSubset.
2090	*
2091	* @param pVCpu Pointer to the virtual cpu data.
2092	* @param iPrevSubset What PGMDynMapPushAutoSubset returned.
2093	*/
2094	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset)
2095	{
2096	PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
2097	uint32_t cEntries = pSet->cEntries;
2098	LogFlow(("PGMRZDynMapPopAutoSubset: pVCpu=%p iPrevSubset=%u iSubset=%u cEntries=%u\n", pVCpu, iPrevSubset, pSet->iSubset, cEntries));
2099	AssertReturnVoid(cEntries != PGMMAPSET_CLOSED);
2100	AssertReturnVoid(pSet->iSubset >= iPrevSubset \|\| iPrevSubset == UINT32_MAX);
2101	#ifdef IN_RC
2102	if (RT_ELEMENTS(pSet->aEntries) > MM_HYPER_DYNAMIC_SIZE / PAGE_SIZE)
2103	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->aStatRZDynMapSetFilledPct[(cEntries * 10 / (MM_HYPER_DYNAMIC_SIZE / PAGE_SIZE)) % 11]);
2104	else
2105	#endif
2106	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->aStatRZDynMapSetFilledPct[(cEntries * 10 / RT_ELEMENTS(pSet->aEntries)) % 11]);
2107	if ( cEntries >= RT_ELEMENTS(pSet->aEntries) * 40 / 100
2108	&& cEntries != pSet->iSubset)
2109	{
2110	AssertMsg(cEntries < PGMMAPSET_MAX_FILL, ("%u\n", cEntries));
2111	pgmDynMapFlushSubset(pSet);
2112	}
2113	pSet->iSubset = iPrevSubset;
2114	}
2115
2116
2117	/**
2118	* Indicates that the given page is unused and its mapping can be re-used.
2119	*
2120	* @param pVCpu The current CPU.
2121	* @param pvHint The page that is now unused. This does not have to
2122	* point at the start of the page. NULL is ignored.
2123	*/
2124	#ifdef LOG_ENABLED
2125	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL)
2126	#else
2127	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint)
2128	#endif
2129	{
2130	/*
2131	* Ignore NULL pointers and mask off the page offset bits.
2132	*/
2133	if (pvHint == NULL)
2134	return;
2135	pvHint = (void *)((uintptr_t)pvHint & ~(uintptr_t)PAGE_OFFSET_MASK);
2136
2137	PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
2138	uint32_t iEntry = pSet->cEntries;
2139	AssertReturnVoid(iEntry > 0);
2140
2141	/*
2142	* Find the entry in the usual unrolled fashion.
2143	*/
2144	#define IS_MATCHING_ENTRY(pSet, iEntry, pvHint) \
2145	( (pSet)->aEntries[(iEntry)].pvPage == (pvHint) \
2146	&& (uint32_t)(pSet)->aEntries[(iEntry)].cRefs + (pSet)->aEntries[(iEntry)].cInlinedRefs \
2147	> (pSet)->aEntries[(iEntry)].cUnrefs )
2148	if ( iEntry >= 1 && IS_MATCHING_ENTRY(pSet, iEntry - 1, pvHint))
2149	iEntry = iEntry - 1;
2150	else if (iEntry >= 2 && IS_MATCHING_ENTRY(pSet, iEntry - 2, pvHint))
2151	iEntry = iEntry - 2;
2152	else if (iEntry >= 3 && IS_MATCHING_ENTRY(pSet, iEntry - 3, pvHint))
2153	iEntry = iEntry - 3;
2154	else if (iEntry >= 4 && IS_MATCHING_ENTRY(pSet, iEntry - 4, pvHint))
2155	iEntry = iEntry - 4;
2156	else if (iEntry >= 5 && IS_MATCHING_ENTRY(pSet, iEntry - 5, pvHint))
2157	iEntry = iEntry - 5;
2158	else if (iEntry >= 6 && IS_MATCHING_ENTRY(pSet, iEntry - 6, pvHint))
2159	iEntry = iEntry - 6;
2160	else if (iEntry >= 7 && IS_MATCHING_ENTRY(pSet, iEntry - 7, pvHint))
2161	iEntry = iEntry - 7;
2162	else
2163	{
2164	/*
2165	* Loop till we find it.
2166	*/
2167	bool fFound = false;
2168	if (iEntry > 7)
2169	{
2170	iEntry -= 7;
2171	while (iEntry-- > 0)
2172	if (IS_MATCHING_ENTRY(pSet, iEntry, pvHint))
2173	{
2174	fFound = true;
2175	break;
2176	}
2177	}
2178	AssertMsgReturnVoid(fFound,
2179	("pvHint=%p cEntries=%#x iSubset=%#x\n"
2180	"aEntries[0] = {%#x, %#x, %#x, %#x, %p}\n"
2181	"aEntries[1] = {%#x, %#x, %#x, %#x, %p}\n"
2182	"aEntries[2] = {%#x, %#x, %#x, %#x, %p}\n"
2183	"aEntries[3] = {%#x, %#x, %#x, %#x, %p}\n"
2184	"aEntries[4] = {%#x, %#x, %#x, %#x, %p}\n"
2185	"aEntries[5] = {%#x, %#x, %#x, %#x, %p}\n"
2186	,
2187	pvHint, pSet->cEntries, pSet->iSubset,
2188	pSet->aEntries[0].iPage, pSet->aEntries[0].cRefs, pSet->aEntries[0].cInlinedRefs, pSet->aEntries[0].cUnrefs, pSet->aEntries[0].pvPage,
2189	pSet->aEntries[1].iPage, pSet->aEntries[1].cRefs, pSet->aEntries[1].cInlinedRefs, pSet->aEntries[1].cUnrefs, pSet->aEntries[1].pvPage,
2190	pSet->aEntries[2].iPage, pSet->aEntries[2].cRefs, pSet->aEntries[2].cInlinedRefs, pSet->aEntries[2].cUnrefs, pSet->aEntries[2].pvPage,
2191	pSet->aEntries[3].iPage, pSet->aEntries[3].cRefs, pSet->aEntries[3].cInlinedRefs, pSet->aEntries[3].cUnrefs, pSet->aEntries[3].pvPage,
2192	pSet->aEntries[4].iPage, pSet->aEntries[4].cRefs, pSet->aEntries[4].cInlinedRefs, pSet->aEntries[4].cUnrefs, pSet->aEntries[4].pvPage,
2193	pSet->aEntries[5].iPage, pSet->aEntries[5].cRefs, pSet->aEntries[5].cInlinedRefs, pSet->aEntries[5].cUnrefs, pSet->aEntries[5].pvPage));
2194	}
2195	#undef IS_MATCHING_ENTRY
2196
2197	/*
2198	* Update it.
2199	*/
2200	uint32_t const cTotalRefs = (uint32_t)pSet->aEntries[iEntry].cRefs + pSet->aEntries[iEntry].cInlinedRefs;
2201	uint32_t const cUnrefs = pSet->aEntries[iEntry].cUnrefs;
2202	LogFlow(("pgmRZDynMapUnusedHint: pvHint=%p #%u cRefs=%d cInlinedRefs=%d cUnrefs=%d (+1) cTotalRefs=%d %s(%d) %s\n",
2203	pvHint, iEntry, pSet->aEntries[iEntry].cRefs, pSet->aEntries[iEntry].cInlinedRefs, cUnrefs, cTotalRefs, pszFile, iLine, pszFunction));
2204	AssertReturnVoid(cTotalRefs > cUnrefs);
2205
2206	if (RT_LIKELY(cUnrefs < UINT16_MAX - 1))
2207	pSet->aEntries[iEntry].cUnrefs++;
2208	else if (pSet->aEntries[iEntry].cInlinedRefs)
2209	{
2210	uint32_t cSub = RT_MIN(pSet->aEntries[iEntry].cInlinedRefs, pSet->aEntries[iEntry].cUnrefs);
2211	pSet->aEntries[iEntry].cInlinedRefs -= cSub;
2212	pSet->aEntries[iEntry].cUnrefs -= cSub;
2213	pSet->aEntries[iEntry].cUnrefs++;
2214	}
2215	else
2216	Log(("pgmRZDynMapUnusedHint: pvHint=%p ignored because of overflow! %s(%d) %s\n", pvHint, pszFile, iLine, pszFunction));
2217	}
2218
2219
2220	/**
2221	* Common worker code for pgmRZDynMapHCPageInlined, pgmRZDynMapHCPageV2Inlined
2222	* and pgmR0DynMapGCPageOffInlined.
2223	*
2224	* @returns VINF_SUCCESS, bails out to ring-3 on failure.
2225	* @param pSet The set.
2226	* @param HCPhys The physical address of the page.
2227	* @param ppv Where to store the address of the mapping on success.
2228	*
2229	* @remarks This is a very hot path.
2230	*/
2231	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2232	{
2233	AssertMsg(pSet->iCpu == PGMRZDYNMAP_CUR_CPU(), ("%d %d efl=%#x\n", pSet->iCpu, PGMRZDYNMAP_CUR_CPU(), ASMGetFlags()));
2234	PVMCPU pVCpu = PGMRZDYNMAP_SET_2_VMCPU(pSet);
2235	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapHCPage, a);
2236
2237	/*
2238	* Map it.
2239	*/
2240	void *pvPage;
2241	PPGMRZDYNMAP pThis = PGMRZDYNMAP_SET_2_DYNMAP(pSet);
2242	uint32_t iPage = pgmR0DynMapPage(pThis, HCPhys, pSet->iCpu, pVCpu, &pvPage);
2243	if (RT_UNLIKELY(iPage == UINT32_MAX))
2244	{
2245	/*
2246	* We're out of mapping space, optimize our set to try remedy the
2247	* situation. (Only works if there are unreference hints.)
2248	*/
2249	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapSetOptimize);
2250	pgmDynMapOptimizeAutoSet(pSet);
2251
2252	iPage = pgmR0DynMapPage(pThis, HCPhys, pSet->iCpu, pVCpu, &pvPage);
2253	if (RT_UNLIKELY(iPage == UINT32_MAX))
2254	{
2255	RTAssertMsg2Weak("pgmRZDynMapHCPageCommon: cLoad=%u/%u cPages=%u cGuardPages=%u\n",
2256	pThis->cLoad, pThis->cMaxLoad, pThis->cPages, pThis->cGuardPages);
2257	if (!g_fPGMR0DynMapTestRunning)
2258	VMMRZCallRing3NoCpu(PGMRZDYNMAP_SET_2_VM(pSet), VMMCALLRING3_VM_R0_ASSERTION, 0);
2259	*ppv = NULL;
2260	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapHCPage, a);
2261	return VERR_PGM_DYNMAP_FAILED;
2262	}
2263	}
2264
2265	/*
2266	* Add the page to the auto reference set.
2267	*
2268	* The typical usage pattern means that the same pages will be mapped
2269	* several times in the same set. We can catch most of these
2270	* remappings by looking a few pages back into the set. (The searching
2271	* and set optimizing path will hardly ever be used when doing this.)
2272	*/
2273	AssertCompile(RT_ELEMENTS(pSet->aEntries) >= 8);
2274	int32_t i = pSet->cEntries;
2275	if (i-- < 5)
2276	{
2277	unsigned iEntry = pSet->cEntries++;
2278	pSet->aEntries[iEntry].cRefs = 1;
2279	pSet->aEntries[iEntry].cUnrefs = 0;
2280	pSet->aEntries[iEntry].cInlinedRefs = 0;
2281	pSet->aEntries[iEntry].iPage = iPage;
2282	pSet->aEntries[iEntry].pvPage = pvPage;
2283	pSet->aEntries[iEntry].HCPhys = HCPhys;
2284	pSet->aiHashTable[PGMMAPSET_HASH(HCPhys)] = iEntry;
2285	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=%u/0/0 iPage=%#x [a] %s(%d) %s\n",
2286	pSet, HCPhys, iEntry, iEntry + 1, pvPage, 1, iPage, pszFile, iLine, pszFunction));
2287	}
2288	/* Any of the last 5 pages? */
2289	else if ( pSet->aEntries[i - 0].iPage == iPage
2290	&& pSet->aEntries[i - 0].cRefs < UINT16_MAX - 1)
2291	{
2292	pSet->aEntries[i - 0].cRefs++;
2293	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=%u/%u/%u iPage=%#x [0] %s(%d) %s\n", pSet, HCPhys, i - 0, pSet->cEntries, pvPage, pSet->aEntries[i - 0].cRefs, pSet->aEntries[i - 0].cInlinedRefs, pSet->aEntries[i - 0].cUnrefs, iPage, pszFile, iLine, pszFunction));
2294	}
2295	else if ( pSet->aEntries[i - 1].iPage == iPage
2296	&& pSet->aEntries[i - 1].cRefs < UINT16_MAX - 1)
2297	{
2298	pSet->aEntries[i - 1].cRefs++;
2299	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=%u/%u/%u iPage=%#x [1] %s(%d) %s\n", pSet, HCPhys, i - 1, pSet->cEntries, pvPage, pSet->aEntries[i - 1].cRefs, pSet->aEntries[i - 1].cInlinedRefs, pSet->aEntries[i - 1].cUnrefs, iPage, pszFile, iLine, pszFunction));
2300	}
2301	else if ( pSet->aEntries[i - 2].iPage == iPage
2302	&& pSet->aEntries[i - 2].cRefs < UINT16_MAX - 1)
2303	{
2304	pSet->aEntries[i - 2].cRefs++;
2305	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=%u/%u/%u iPage=%#x [2] %s(%d) %s\n", pSet, HCPhys, i - 2, pSet->cEntries, pvPage, pSet->aEntries[i - 2].cRefs, pSet->aEntries[i - 2].cInlinedRefs, pSet->aEntries[i - 2].cUnrefs, iPage, pszFile, iLine, pszFunction));
2306	}
2307	else if ( pSet->aEntries[i - 3].iPage == iPage
2308	&& pSet->aEntries[i - 3].cRefs < UINT16_MAX - 1)
2309	{
2310	pSet->aEntries[i - 3].cRefs++;
2311	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=%u/%u/%u iPage=%#x [4] %s(%d) %s\n", pSet, HCPhys, i - 3, pSet->cEntries, pvPage, pSet->aEntries[i - 3].cRefs, pSet->aEntries[i - 3].cInlinedRefs, pSet->aEntries[i - 3].cUnrefs, iPage, pszFile, iLine, pszFunction));
2312	}
2313	else if ( pSet->aEntries[i - 4].iPage == iPage
2314	&& pSet->aEntries[i - 4].cRefs < UINT16_MAX - 1)
2315	{
2316	pSet->aEntries[i - 4].cRefs++;
2317	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=%u/%u/%u iPage=%#x [4] %s(%d) %s\n", pSet, HCPhys, i - 4, pSet->cEntries, pvPage, pSet->aEntries[i - 4].cRefs, pSet->aEntries[i - 4].cInlinedRefs, pSet->aEntries[i - 4].cUnrefs, iPage, pszFile, iLine, pszFunction));
2318	}
2319	/* Don't bother searching unless we're above a 60% load. */
2320	else if (RT_LIKELY(i <= (int32_t)RT_ELEMENTS(pSet->aEntries) * 60 / 100))
2321	{
2322	unsigned iEntry = pSet->cEntries++;
2323	pSet->aEntries[iEntry].cRefs = 1;
2324	pSet->aEntries[iEntry].cUnrefs = 0;
2325	pSet->aEntries[iEntry].cInlinedRefs = 0;
2326	pSet->aEntries[iEntry].iPage = iPage;
2327	pSet->aEntries[iEntry].pvPage = pvPage;
2328	pSet->aEntries[iEntry].HCPhys = HCPhys;
2329	pSet->aiHashTable[PGMMAPSET_HASH(HCPhys)] = iEntry;
2330	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=1/0/0 iPage=%#x [b] %s(%d) %s\n", pSet, HCPhys, iEntry, pSet->cEntries, pvPage, iPage, pszFile, iLine, pszFunction));
2331	}
2332	else
2333	{
2334	/* Search the rest of the set. */
2335	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
2336	i -= 4;
2337	while (i-- > 0)
2338	if ( pSet->aEntries[i].iPage == iPage
2339	&& pSet->aEntries[i].cRefs < UINT16_MAX - 1)
2340	{
2341	pSet->aEntries[i].cRefs++;
2342	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapSetSearchHits);
2343	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=%u/%u/%u iPage=%#x [c] %s(%d) %s\n", pSet, HCPhys, i, pSet->cEntries, pvPage, pSet->aEntries[i].cRefs, pSet->aEntries[i].cInlinedRefs, pSet->aEntries[i].cUnrefs, iPage, pszFile, iLine, pszFunction));
2344	break;
2345	}
2346	if (i < 0)
2347	{
2348	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapSetSearchMisses);
2349	if (pSet->iSubset < pSet->cEntries)
2350	{
2351	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapSetSearchFlushes);
2352	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->aStatRZDynMapSetFilledPct[(pSet->cEntries * 10 / RT_ELEMENTS(pSet->aEntries)) % 11]);
2353	AssertMsg(pSet->cEntries < PGMMAPSET_MAX_FILL, ("%u\n", pSet->cEntries));
2354	pgmDynMapFlushSubset(pSet);
2355	}
2356
2357	if (RT_UNLIKELY(pSet->cEntries >= RT_ELEMENTS(pSet->aEntries)))
2358	{
2359	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapSetOptimize);
2360	pgmDynMapOptimizeAutoSet(pSet);
2361	}
2362
2363	if (RT_LIKELY(pSet->cEntries < RT_ELEMENTS(pSet->aEntries)))
2364	{
2365	unsigned iEntry = pSet->cEntries++;
2366	pSet->aEntries[iEntry].cRefs = 1;
2367	pSet->aEntries[iEntry].cUnrefs = 0;
2368	pSet->aEntries[iEntry].cInlinedRefs = 0;
2369	pSet->aEntries[iEntry].iPage = iPage;
2370	pSet->aEntries[iEntry].pvPage = pvPage;
2371	pSet->aEntries[iEntry].HCPhys = HCPhys;
2372	pSet->aiHashTable[PGMMAPSET_HASH(HCPhys)] = iEntry;
2373	LogFlow(("pgmRZDynMapHCPageCommon: pSet=%p HCPhys=%RHp #%u/%u/%p cRefs=1/0/0 iPage=%#x [d] %s(%d) %s\n", pSet, HCPhys, iEntry, pSet->cEntries, pvPage, iPage, pszFile, iLine, pszFunction));
2374	}
2375	else
2376	{
2377	/* We're screwed. */
2378	pgmRZDynMapReleasePage(pThis, iPage, 1);
2379
2380	RTAssertMsg2Weak("pgmRZDynMapHCPageCommon: set is full!\n");
2381	if (!g_fPGMR0DynMapTestRunning)
2382	VMMRZCallRing3NoCpu(PGMRZDYNMAP_SET_2_VM(pSet), VMMCALLRING3_VM_R0_ASSERTION, 0);
2383	*ppv = NULL;
2384	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapHCPage, a);
2385	return VERR_PGM_DYNMAP_FULL_SET;
2386	}
2387	}
2388	}
2389
2390	*ppv = pvPage;
2391	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZDynMapHCPage, a);
2392	return VINF_SUCCESS;
2393	}
2394
2395
2396	#if 0 /def DEBUG/
2397	/** For pgmR0DynMapTest3PerCpu. */
2398	typedef struct PGMR0DYNMAPTEST
2399	{
2400	uint32_t u32Expect;
2401	uint32_t *pu32;
2402	uint32_t volatile cFailures;
2403	} PGMR0DYNMAPTEST;
2404	typedef PGMR0DYNMAPTEST *PPGMR0DYNMAPTEST;
2405
2406	/**
2407	* Checks that the content of the page is the same on all CPUs, i.e. that there
2408	* are no CPU specfic PTs or similar nasty stuff involved.
2409	*
2410	* @param idCpu The current CPU.
2411	* @param pvUser1 Pointer a PGMR0DYNMAPTEST structure.
2412	* @param pvUser2 Unused, ignored.
2413	*/
2414	static DECLCALLBACK(void) pgmR0DynMapTest3PerCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
2415	{
2416	PPGMR0DYNMAPTEST pTest = (PPGMR0DYNMAPTEST)pvUser1;
2417	ASMInvalidatePage(pTest->pu32);
2418	if (*pTest->pu32 != pTest->u32Expect)
2419	ASMAtomicIncU32(&pTest->cFailures);
2420	NOREF(pvUser2); NOREF(idCpu);
2421	}
2422
2423
2424	/**
2425	* Performs some basic tests in debug builds.
2426	*/
2427	static int pgmR0DynMapTest(PVM pVM)
2428	{
2429	LogRel(("pgmR0DynMapTest: **** START ****\n"));
2430	PPGMMAPSET pSet = &pVM->aCpus[0].pgm.s.AutoSet;
2431	PPGMRZDYNMAP pThis = PGMRZDYNMAP_SET_2_DYNMAP(pSet);
2432	uint32_t i;
2433
2434	/*
2435	* Assert internal integrity first.
2436	*/
2437	LogRel(("Test #0\n"));
2438	int rc = PGMR0DynMapAssertIntegrity();
2439	if (RT_FAILURE(rc))
2440	return rc;
2441
2442	void *pvR0DynMapUsedSaved = pVM->pgm.s.pvR0DynMapUsed;
2443	pVM->pgm.s.pvR0DynMapUsed = pThis;
2444	g_fPGMR0DynMapTestRunning = true;
2445
2446	/*
2447	* Simple test, map CR3 twice and check that we're getting the
2448	* same mapping address back.
2449	*/
2450	LogRel(("Test #1\n"));
2451	ASMIntDisable();
2452	PGMRZDynMapStartAutoSet(&pVM->aCpus[0]);
2453
2454	uint64_t cr3 = ASMGetCR3() & ~(uint64_t)PAGE_OFFSET_MASK;
2455	void pv = (void )(intptr_t)-1;
2456	void pv2 = (void )(intptr_t)-2;
2457	rc = pgmRZDynMapHCPageCommon(pVM, cr3, &pv RTLOG_COMMA_SRC_POS);
2458	int rc2 = pgmRZDynMapHCPageCommon(pVM, cr3, &pv2 RTLOG_COMMA_SRC_POS);
2459	ASMIntEnable();
2460	if ( RT_SUCCESS(rc2)
2461	&& RT_SUCCESS(rc)
2462	&& pv == pv2)
2463	{
2464	LogRel(("Load=%u/%u/%u Set=%u/%u\n", pThis->cLoad, pThis->cMaxLoad, pThis->cPages - pThis->cPages, pSet->cEntries, RT_ELEMENTS(pSet->aEntries)));
2465	rc = PGMR0DynMapAssertIntegrity();
2466
2467	/*
2468	* Check that the simple set overflow code works by filling it
2469	* with more CR3 mappings.
2470	*/
2471	LogRel(("Test #2\n"));
2472	ASMIntDisable();
2473	PGMR0DynMapMigrateAutoSet(&pVM->aCpus[0]);
2474	for (i = 0 ; i < UINT16_MAX*2 - 1 && RT_SUCCESS(rc) && pv2 == pv; i++)
2475	{
2476	pv2 = (void *)(intptr_t)-4;
2477	rc = pgmRZDynMapHCPageCommon(pVM, cr3, &pv2 RTLOG_COMMA_SRC_POS);
2478	}
2479	ASMIntEnable();
2480	if (RT_FAILURE(rc) \|\| pv != pv2)
2481	{
2482	LogRel(("failed(%d): rc=%Rrc; pv=%p pv2=%p i=%p\n", __LINE__, rc, pv, pv2, i));
2483	if (RT_SUCCESS(rc)) rc = VERR_INTERNAL_ERROR;
2484	}
2485	else if (pSet->cEntries != 5)
2486	{
2487	LogRel(("failed(%d): cEntries=%d expected %d\n", __LINE__, pSet->cEntries, RT_ELEMENTS(pSet->aEntries) / 2));
2488	rc = VERR_INTERNAL_ERROR;
2489	}
2490	else if ( pSet->aEntries[4].cRefs != UINT16_MAX - 1
2491	\|\| pSet->aEntries[3].cRefs != UINT16_MAX - 1
2492	\|\| pSet->aEntries[2].cRefs != 1
2493	\|\| pSet->aEntries[1].cRefs != 1
2494	\|\| pSet->aEntries[0].cRefs != 1)
2495	{
2496	LogRel(("failed(%d): bad set dist: ", __LINE__));
2497	for (i = 0; i < pSet->cEntries; i++)
2498	LogRel(("[%d]=%d, ", i, pSet->aEntries[i].cRefs));
2499	LogRel(("\n"));
2500	rc = VERR_INTERNAL_ERROR;
2501	}
2502	if (RT_SUCCESS(rc))
2503	rc = PGMR0DynMapAssertIntegrity();
2504	if (RT_SUCCESS(rc))
2505	{
2506	/*
2507	* Trigger an set optimization run (exactly).
2508	*/
2509	LogRel(("Test #3\n"));
2510	ASMIntDisable();
2511	PGMR0DynMapMigrateAutoSet(&pVM->aCpus[0]);
2512	pv2 = NULL;
2513	for (i = 0 ; i < RT_ELEMENTS(pSet->aEntries) - 5 && RT_SUCCESS(rc) && pv2 != pv; i++)
2514	{
2515	pv2 = (void *)(intptr_t)(-5 - i);
2516	rc = pgmRZDynMapHCPageCommon(pVM, cr3 + PAGE_SIZE * (i + 5), &pv2 RTLOG_COMMA_SRC_POS);
2517	}
2518	ASMIntEnable();
2519	if (RT_FAILURE(rc) \|\| pv == pv2)
2520	{
2521	LogRel(("failed(%d): rc=%Rrc; pv=%p pv2=%p i=%d\n", __LINE__, rc, pv, pv2, i));
2522	if (RT_SUCCESS(rc)) rc = VERR_INTERNAL_ERROR;
2523	}
2524	else if (pSet->cEntries != RT_ELEMENTS(pSet->aEntries))
2525	{
2526	LogRel(("failed(%d): cEntries=%d expected %d\n", __LINE__, pSet->cEntries, RT_ELEMENTS(pSet->aEntries)));
2527	rc = VERR_INTERNAL_ERROR;
2528	}
2529	LogRel(("Load=%u/%u/%u Set=%u/%u\n", pThis->cLoad, pThis->cMaxLoad, pThis->cPages - pThis->cPages, pSet->cEntries, RT_ELEMENTS(pSet->aEntries)));
2530	if (RT_SUCCESS(rc))
2531	rc = PGMR0DynMapAssertIntegrity();
2532	if (RT_SUCCESS(rc))
2533	{
2534	/*
2535	* Trigger an overflow error.
2536	*/
2537	LogRel(("Test #4\n"));
2538	ASMIntDisable();
2539	PGMR0DynMapMigrateAutoSet(&pVM->aCpus[0]);
2540	for (i = 0 ; i < RT_ELEMENTS(pSet->aEntries) + 2; i++)
2541	{
2542	rc = pgmRZDynMapHCPageCommon(pVM, cr3 - PAGE_SIZE * (i + 5), &pv2 RTLOG_COMMA_SRC_POS);
2543	if (RT_SUCCESS(rc))
2544	rc = PGMR0DynMapAssertIntegrity();
2545	if (RT_FAILURE(rc))
2546	break;
2547	}
2548	ASMIntEnable();
2549	if (rc == VERR_PGM_DYNMAP_FULL_SET)
2550	{
2551	/* flush the set. */
2552	LogRel(("Test #5\n"));
2553	ASMIntDisable();
2554	PGMR0DynMapMigrateAutoSet(&pVM->aCpus[0]);
2555	PGMRZDynMapReleaseAutoSet(&pVM->aCpus[0]);
2556	PGMRZDynMapStartAutoSet(&pVM->aCpus[0]);
2557	ASMIntEnable();
2558
2559	rc = PGMR0DynMapAssertIntegrity();
2560	}
2561	else
2562	{
2563	LogRel(("failed(%d): rc=%Rrc, wanted %d ; pv2=%p Set=%u/%u; i=%d\n", __LINE__,
2564	rc, VERR_PGM_DYNMAP_FULL_SET, pv2, pSet->cEntries, RT_ELEMENTS(pSet->aEntries), i));
2565	if (RT_SUCCESS(rc)) rc = VERR_INTERNAL_ERROR;
2566	}
2567	}
2568	}
2569	}
2570	else
2571	{
2572	LogRel(("failed(%d): rc=%Rrc rc2=%Rrc; pv=%p pv2=%p\n", __LINE__, rc, rc2, pv, pv2));
2573	if (RT_SUCCESS(rc))
2574	rc = rc2;
2575	}
2576
2577	/*
2578	* Check that everyone sees the same stuff.
2579	*/
2580	if (RT_SUCCESS(rc))
2581	{
2582	LogRel(("Test #5\n"));
2583	ASMIntDisable();
2584	PGMR0DynMapMigrateAutoSet(&pVM->aCpus[0]);
2585	RTHCPHYS HCPhysPT = RTR0MemObjGetPagePhysAddr(pThis->pSegHead->ahMemObjPTs[0], 0);
2586	rc = pgmRZDynMapHCPageCommon(pVM, HCPhysPT, &pv RTLOG_COMMA_SRC_POS);
2587	if (RT_SUCCESS(rc))
2588	{
2589	PGMR0DYNMAPTEST Test;
2590	uint32_t *pu32Real = &pThis->paPages[pThis->pSegHead->iPage].uPte.pLegacy->u;
2591	Test.pu32 = (uint32_t *)((uintptr_t)pv \| ((uintptr_t)pu32Real & PAGE_OFFSET_MASK));
2592	Test.u32Expect = *pu32Real;
2593	ASMAtomicWriteU32(&Test.cFailures, 0);
2594	ASMIntEnable();
2595
2596	rc = RTMpOnAll(pgmR0DynMapTest3PerCpu, &Test, NULL);
2597	if (RT_FAILURE(rc))
2598	LogRel(("failed(%d): RTMpOnAll rc=%Rrc\n", __LINE__, rc));
2599	else if (Test.cFailures)
2600	{
2601	LogRel(("failed(%d): cFailures=%d pu32Real=%p pu32=%p u32Expect=%#x *pu32=%#x\n", __LINE__,
2602	Test.cFailures, pu32Real, Test.pu32, Test.u32Expect, *Test.pu32));
2603	rc = VERR_INTERNAL_ERROR;
2604	}
2605	else
2606	LogRel(("pu32Real=%p pu32=%p u32Expect=%#x *pu32=%#x\n",
2607	pu32Real, Test.pu32, Test.u32Expect, *Test.pu32));
2608	}
2609	else
2610	{
2611	ASMIntEnable();
2612	LogRel(("failed(%d): rc=%Rrc\n", rc));
2613	}
2614	}
2615
2616	/*
2617	* Clean up.
2618	*/
2619	LogRel(("Cleanup.\n"));
2620	ASMIntDisable();
2621	PGMR0DynMapMigrateAutoSet(&pVM->aCpus[0]);
2622	PGMRZDynMapFlushAutoSet(&pVM->aCpus[0]);
2623	PGMRZDynMapReleaseAutoSet(&pVM->aCpus[0]);
2624	ASMIntEnable();
2625
2626	if (RT_SUCCESS(rc))
2627	rc = PGMR0DynMapAssertIntegrity();
2628	else
2629	PGMR0DynMapAssertIntegrity();
2630
2631	g_fPGMR0DynMapTestRunning = false;
2632	LogRel(("Result: rc=%Rrc Load=%u/%u/%u Set=%#x/%u\n", rc,
2633	pThis->cLoad, pThis->cMaxLoad, pThis->cPages - pThis->cPages, pSet->cEntries, RT_ELEMENTS(pSet->aEntries)));
2634	pVM->pgm.s.pvR0DynMapUsed = pvR0DynMapUsedSaved;
2635	LogRel(("pgmR0DynMapTest: **** END ****\n"));
2636	return rc;
2637	}
2638	#endif /* DEBUG */
2639

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMRZ/PGMRZDynMap.cpp@ 31402

Download in other formats: