VMMSwitcher.cpp@ 30148

Last change on this file since 30148 was 30148, checked in by vboxsync, 15 years ago
Too early to check guest cpuid features; use host
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1	/* $Id: VMMSwitcher.cpp 30148 2010-06-10 12:17:16Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_VMM
22	#include <VBox/vmm.h>
23	#include <VBox/pgm.h>
24	#include <VBox/selm.h>
25	#include <VBox/mm.h>
26	#include <VBox/sup.h>
27	#include "VMMInternal.h"
28	#include "VMMSwitcher/VMMSwitcher.h"
29	#include <VBox/vm.h>
30	#include <VBox/dis.h>
31
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/alloc.h>
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/string.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Global Variables *
44	*******************************************************************************/
45	/** Array of switcher defininitions.
46	* The type and index shall match!
47	*/
48	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
49	{
50	NULL, /* invalid entry */
51	#ifdef VBOX_WITH_RAW_MODE
52	# ifndef RT_ARCH_AMD64
53	&vmmR3Switcher32BitTo32Bit_Def,
54	&vmmR3Switcher32BitToPAE_Def,
55	&vmmR3Switcher32BitToAMD64_Def,
56	&vmmR3SwitcherPAETo32Bit_Def,
57	&vmmR3SwitcherPAEToPAE_Def,
58	&vmmR3SwitcherPAEToAMD64_Def,
59	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
60	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
61	&vmmR3SwitcherAMD64ToPAE_Def,
62	# else
63	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
64	# endif
65	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
66	# else /* RT_ARCH_AMD64 */
67	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
68	NULL, //&vmmR3Switcher32BitToPAE_Def,
69	NULL, //&vmmR3Switcher32BitToAMD64_Def,
70	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
71	NULL, //&vmmR3SwitcherPAEToPAE_Def,
72	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
73	&vmmR3SwitcherAMD64To32Bit_Def,
74	&vmmR3SwitcherAMD64ToPAE_Def,
75	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
76	# endif /* RT_ARCH_AMD64 */
77	#else /* !VBOX_WITH_RAW_MODE */
78	NULL,
79	NULL,
80	NULL,
81	NULL,
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL
87	#endif /* !VBOX_WITH_RAW_MODE */
88	};
89
90
91	/**
92	* VMMR3Init worker that initiates the switcher code (aka core code).
93	*
94	* This is core per VM code which might need fixups and/or for ease of use are
95	* put on linear contiguous backing.
96	*
97	* @returns VBox status code.
98	* @param pVM Pointer to the shared VM structure.
99	*/
100	int vmmR3SwitcherInit(PVM pVM)
101	{
102	#ifndef VBOX_WITH_RAW_MODE
103	return VINF_SUCCESS;
104	#else
105	/*
106	* Calc the size.
107	*/
108	unsigned cbCoreCode = 0;
109	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
110	{
111	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
112	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
113	if (pSwitcher)
114	{
115	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
116	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
117	}
118	}
119
120	/*
121	* Allocate continguous pages for switchers and deal with
122	* conflicts in the intermediate mapping of the code.
123	*/
124	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
125	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
126	int rc = VERR_NO_MEMORY;
127	if (pVM->vmm.s.pvCoreCodeR3)
128	{
129	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
130	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
131	{
132	/* try more allocations - Solaris, Linux. */
133	const unsigned cTries = 8234;
134	struct VMMInitBadTry
135	{
136	RTR0PTR pvR0;
137	void *pvR3;
138	RTHCPHYS HCPhys;
139	RTUINT cb;
140	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
141	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
142	unsigned i = 0;
143	do
144	{
145	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
146	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
147	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
148	i++;
149	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
150	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
151	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
152	if (!pVM->vmm.s.pvCoreCodeR3)
153	break;
154	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
155	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
156	&& i < cTries - 1);
157
158	/* cleanup */
159	if (RT_FAILURE(rc))
160	{
161	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
162	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
163	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
164	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
165	i++;
166	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
167	}
168	while (i-- > 0)
169	{
170	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
171	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
172	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
173	}
174	RTMemTmpFree(paBadTries);
175	}
176	}
177	if (RT_SUCCESS(rc))
178	{
179	/*
180	* copy the code.
181	*/
182	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
183	{
184	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
185	if (pSwitcher)
186	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
187	pSwitcher->pvCode, pSwitcher->cbCode);
188	}
189
190	/*
191	* Map the code into the GC address space.
192	*/
193	RTGCPTR GCPtr;
194	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
195	cbCoreCode, "Core Code", &GCPtr);
196	if (RT_SUCCESS(rc))
197	{
198	pVM->vmm.s.pvCoreCodeRC = GCPtr;
199	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
200	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
201	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
202
203	/*
204	* Finally, PGM probably has selected a switcher already but we need
205	* to get the routine addresses, so we'll reselect it.
206	* This may legally fail so, we're ignoring the rc.
207	*/
208	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
209	return rc;
210	}
211
212	/* shit */
213	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
214	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
215	}
216	else
217	VMSetError(pVM, rc, RT_SRC_POS,
218	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
219	cbCoreCode);
220
221	pVM->vmm.s.pvCoreCodeR3 = NULL;
222	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
223	pVM->vmm.s.pvCoreCodeRC = 0;
224	return rc;
225	#endif
226	}
227
228	/**
229	* Relocate the switchers, called by VMMR#Relocate.
230	*
231	* @param pVM Pointer to the shared VM structure.
232	* @param offDelta The relocation delta.
233	*/
234	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
235	{
236	#ifdef VBOX_WITH_RAW_MODE
237	/*
238	* Relocate all the switchers.
239	*/
240	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
241	{
242	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
243	if (pSwitcher && pSwitcher->pfnRelocate)
244	{
245	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
246	pSwitcher->pfnRelocate(pVM,
247	pSwitcher,
248	pVM->vmm.s.pvCoreCodeR0 + off,
249	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
250	pVM->vmm.s.pvCoreCodeRC + off,
251	pVM->vmm.s.HCPhysCoreCode + off);
252	}
253	}
254
255	/*
256	* Recalc the RC address for the current switcher.
257	*/
258	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
259	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
260	pVM->vmm.s.pfnGuestToHostRC = RCPtr + pSwitcher->offGCGuestToHost;
261	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offGCCallTrampoline;
262	pVM->pfnVMMGCGuestToHostAsm = RCPtr + pSwitcher->offGCGuestToHostAsm;
263	pVM->pfnVMMGCGuestToHostAsmHyperCtx = RCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
264	pVM->pfnVMMGCGuestToHostAsmGuestCtx = RCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
265
266	// AssertFailed();
267	#endif
268	}
269
270
271	/**
272	* Generic switcher code relocator.
273	*
274	* @param pVM The VM handle.
275	* @param pSwitcher The switcher definition.
276	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
277	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
278	* @param GCPtrCode The guest context address corresponding to pu8Code.
279	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
280	* @param SelCS The hypervisor CS selector.
281	* @param SelDS The hypervisor DS selector.
282	* @param SelTSS The hypervisor TSS selector.
283	* @param GCPtrGDT The GC address of the hypervisor GDT.
284	* @param SelCS64 The 64-bit mode hypervisor CS selector.
285	*/
286	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
287	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
288	{
289	union
290	{
291	const uint8_t *pu8;
292	const uint16_t *pu16;
293	const uint32_t *pu32;
294	const uint64_t *pu64;
295	const void *pv;
296	uintptr_t u;
297	} u;
298	u.pv = pSwitcher->pvFixups;
299
300	/*
301	* Process fixups.
302	*/
303	uint8_t u8;
304	while ((u8 = *u.pu8++) != FIX_THE_END)
305	{
306	/*
307	* Get the source (where to write the fixup).
308	*/
309	uint32_t offSrc = *u.pu32++;
310	Assert(offSrc < pSwitcher->cbCode);
311	union
312	{
313	uint8_t *pu8;
314	uint16_t *pu16;
315	uint32_t *pu32;
316	uint64_t *pu64;
317	uintptr_t u;
318	} uSrc;
319	uSrc.pu8 = pu8CodeR3 + offSrc;
320
321	/* The fixup target and method depends on the type. */
322	switch (u8)
323	{
324	/*
325	* 32-bit relative, source in HC and target in GC.
326	*/
327	case FIX_HC_2_GC_NEAR_REL:
328	{
329	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
330	uint32_t offTrg = *u.pu32++;
331	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
332	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
333	break;
334	}
335
336	/*
337	* 32-bit relative, source in HC and target in ID.
338	*/
339	case FIX_HC_2_ID_NEAR_REL:
340	{
341	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
342	uint32_t offTrg = *u.pu32++;
343	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
344	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
345	break;
346	}
347
348	/*
349	* 32-bit relative, source in GC and target in HC.
350	*/
351	case FIX_GC_2_HC_NEAR_REL:
352	{
353	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
354	uint32_t offTrg = *u.pu32++;
355	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
356	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
357	break;
358	}
359
360	/*
361	* 32-bit relative, source in GC and target in ID.
362	*/
363	case FIX_GC_2_ID_NEAR_REL:
364	{
365	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
366	uint32_t offTrg = *u.pu32++;
367	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
368	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
369	break;
370	}
371
372	/*
373	* 32-bit relative, source in ID and target in HC.
374	*/
375	case FIX_ID_2_HC_NEAR_REL:
376	{
377	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
378	uint32_t offTrg = *u.pu32++;
379	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
380	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
381	break;
382	}
383
384	/*
385	* 32-bit relative, source in ID and target in HC.
386	*/
387	case FIX_ID_2_GC_NEAR_REL:
388	{
389	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
390	uint32_t offTrg = *u.pu32++;
391	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
392	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
393	break;
394	}
395
396	/*
397	* 16:32 far jump, target in GC.
398	*/
399	case FIX_GC_FAR32:
400	{
401	uint32_t offTrg = *u.pu32++;
402	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
403	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
404	*uSrc.pu16++ = SelCS;
405	break;
406	}
407
408	/*
409	* Make 32-bit GC pointer given CPUM offset.
410	*/
411	case FIX_GC_CPUM_OFF:
412	{
413	uint32_t offCPUM = *u.pu32++;
414	Assert(offCPUM < sizeof(pVM->cpum));
415	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
416	break;
417	}
418
419	/*
420	* Make 32-bit GC pointer given CPUMCPU offset.
421	*/
422	case FIX_GC_CPUMCPU_OFF:
423	{
424	uint32_t offCPUM = *u.pu32++;
425	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
426	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
427	break;
428	}
429
430	/*
431	* Make 32-bit GC pointer given VM offset.
432	*/
433	case FIX_GC_VM_OFF:
434	{
435	uint32_t offVM = *u.pu32++;
436	Assert(offVM < sizeof(VM));
437	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
438	break;
439	}
440
441	/*
442	* Make 32-bit HC pointer given CPUM offset.
443	*/
444	case FIX_HC_CPUM_OFF:
445	{
446	uint32_t offCPUM = *u.pu32++;
447	Assert(offCPUM < sizeof(pVM->cpum));
448	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
449	break;
450	}
451
452	/*
453	* Make 32-bit R0 pointer given VM offset.
454	*/
455	case FIX_HC_VM_OFF:
456	{
457	uint32_t offVM = *u.pu32++;
458	Assert(offVM < sizeof(VM));
459	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
460	break;
461	}
462
463	/*
464	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
465	*/
466	case FIX_INTER_32BIT_CR3:
467	{
468
469	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
470	break;
471	}
472
473	/*
474	* Store the PAE CR3 (32-bit) for the intermediate memory context.
475	*/
476	case FIX_INTER_PAE_CR3:
477	{
478
479	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
480	break;
481	}
482
483	/*
484	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
485	*/
486	case FIX_INTER_AMD64_CR3:
487	{
488
489	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
490	break;
491	}
492
493	/*
494	* Store Hypervisor CS (16-bit).
495	*/
496	case FIX_HYPER_CS:
497	{
498	*uSrc.pu16 = SelCS;
499	break;
500	}
501
502	/*
503	* Store Hypervisor DS (16-bit).
504	*/
505	case FIX_HYPER_DS:
506	{
507	*uSrc.pu16 = SelDS;
508	break;
509	}
510
511	/*
512	* Store Hypervisor TSS (16-bit).
513	*/
514	case FIX_HYPER_TSS:
515	{
516	*uSrc.pu16 = SelTSS;
517	break;
518	}
519
520	/*
521	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
522	*/
523	case FIX_GC_TSS_GDTE_DW2:
524	{
525	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
526	*uSrc.pu32 = (uint32_t)GCPtr;
527	break;
528	}
529
530	/*
531	* Store the EFER or mask for the 32->64 bit switcher.
532	*/
533	case FIX_EFER_OR_MASK:
534	{
535	uint32_t u32OrMask = MSR_K6_EFER_LME \| MSR_K6_EFER_SCE;
536	if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
537	u32OrMask \|= MSR_K6_EFER_NXE;
538
539	*uSrc.pu32 = u32OrMask;
540	break;
541	}
542
543	/*
544	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
545	*/
546	case FIX_NO_FXSAVE_JMP:
547	{
548	uint32_t offTrg = *u.pu32++;
549	Assert(offTrg < pSwitcher->cbCode);
550	if (!CPUMSupportsFXSR(pVM))
551	{
552	uSrc.pu8++ = 0xe9; / jmp rel32 */
553	*uSrc.pu32++ = offTrg - (offSrc + 5);
554	}
555	else
556	{
557	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
558	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
559	}
560	break;
561	}
562
563	/*
564	* Insert relative jump to specified target it SYSENTER isn't used by the host.
565	*/
566	case FIX_NO_SYSENTER_JMP:
567	{
568	uint32_t offTrg = *u.pu32++;
569	Assert(offTrg < pSwitcher->cbCode);
570	if (!CPUMIsHostUsingSysEnter(pVM))
571	{
572	uSrc.pu8++ = 0xe9; / jmp rel32 */
573	*uSrc.pu32++ = offTrg - (offSrc + 5);
574	}
575	else
576	{
577	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
578	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
579	}
580	break;
581	}
582
583	/*
584	* Insert relative jump to specified target it SYSCALL isn't used by the host.
585	*/
586	case FIX_NO_SYSCALL_JMP:
587	{
588	uint32_t offTrg = *u.pu32++;
589	Assert(offTrg < pSwitcher->cbCode);
590	if (!CPUMIsHostUsingSysCall(pVM))
591	{
592	uSrc.pu8++ = 0xe9; / jmp rel32 */
593	*uSrc.pu32++ = offTrg - (offSrc + 5);
594	}
595	else
596	{
597	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
598	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
599	}
600	break;
601	}
602
603	/*
604	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
605	*/
606	case FIX_HC_32BIT:
607	{
608	uint32_t offTrg = *u.pu32++;
609	Assert(offSrc < pSwitcher->cbCode);
610	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
611	*uSrc.pu32 = R0PtrCode + offTrg;
612	break;
613	}
614
615	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
616	/*
617	* 64-bit HC Code Selector (no argument).
618	*/
619	case FIX_HC_64BIT_CS:
620	{
621	Assert(offSrc < pSwitcher->cbCode);
622	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
623	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
624	# else
625	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
626	# endif
627	break;
628	}
629
630	/*
631	* 64-bit HC pointer to the CPUM instance data (no argument).
632	*/
633	case FIX_HC_64BIT_CPUM:
634	{
635	Assert(offSrc < pSwitcher->cbCode);
636	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
637	break;
638	}
639	#endif
640	/*
641	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
642	*/
643	case FIX_HC_64BIT:
644	{
645	uint32_t offTrg = *u.pu32++;
646	Assert(offSrc < pSwitcher->cbCode);
647	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
648	*uSrc.pu64 = R0PtrCode + offTrg;
649	break;
650	}
651
652	#ifdef RT_ARCH_X86
653	case FIX_GC_64_BIT_CPUM_OFF:
654	{
655	uint32_t offCPUM = *u.pu32++;
656	Assert(offCPUM < sizeof(pVM->cpum));
657	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
658	break;
659	}
660	#endif
661
662	/*
663	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
664	*/
665	case FIX_ID_32BIT:
666	{
667	uint32_t offTrg = *u.pu32++;
668	Assert(offSrc < pSwitcher->cbCode);
669	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
670	*uSrc.pu32 = u32IDCode + offTrg;
671	break;
672	}
673
674	/*
675	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
676	*/
677	case FIX_ID_64BIT:
678	case FIX_HC_64BIT_NOCHECK:
679	{
680	uint32_t offTrg = *u.pu32++;
681	Assert(offSrc < pSwitcher->cbCode);
682	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
683	*uSrc.pu64 = u32IDCode + offTrg;
684	break;
685	}
686
687	/*
688	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
689	*/
690	case FIX_ID_FAR32_TO_64BIT_MODE:
691	{
692	uint32_t offTrg = *u.pu32++;
693	Assert(offSrc < pSwitcher->cbCode);
694	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
695	*uSrc.pu32++ = u32IDCode + offTrg;
696	*uSrc.pu16 = SelCS64;
697	AssertRelease(SelCS64);
698	break;
699	}
700
701	#ifdef VBOX_WITH_NMI
702	/*
703	* 32-bit address to the APIC base.
704	*/
705	case FIX_GC_APIC_BASE_32BIT:
706	{
707	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
708	break;
709	}
710	#endif
711
712	default:
713	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
714	break;
715	}
716	}
717
718	#ifdef LOG_ENABLED
719	/*
720	* If Log2 is enabled disassemble the switcher code.
721	*
722	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
723	*/
724	if (LogIs2Enabled())
725	{
726	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
727	" R0PtrCode = %p\n"
728	" pu8CodeR3 = %p\n"
729	" GCPtrCode = %RGv\n"
730	" u32IDCode = %08x\n"
731	" pVMRC = %RRv\n"
732	" pCPUMRC = %RRv\n"
733	" pVMR3 = %p\n"
734	" pCPUMR3 = %p\n"
735	" GCPtrGDT = %RGv\n"
736	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
737	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
738	" SelCS = %04x\n"
739	" SelDS = %04x\n"
740	" SelCS64 = %04x\n"
741	" SelTSS = %04x\n",
742	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
743	R0PtrCode,
744	pu8CodeR3,
745	GCPtrCode,
746	u32IDCode,
747	VM_RC_ADDR(pVM, pVM),
748	VM_RC_ADDR(pVM, &pVM->cpum),
749	pVM,
750	&pVM->cpum,
751	GCPtrGDT,
752	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
753	PGMGetHyperCR3(VMMGetCpu(pVM)),
754	SelCS, SelDS, SelCS64, SelTSS);
755
756	uint32_t offCode = 0;
757	while (offCode < pSwitcher->cbCode)
758	{
759	/*
760	* Figure out where this is.
761	*/
762	const char *pszDesc = NULL;
763	RTUINTPTR uBase;
764	uint32_t cbCode;
765	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
766	{
767	pszDesc = "HCCode0";
768	uBase = R0PtrCode;
769	offCode = pSwitcher->offHCCode0;
770	cbCode = pSwitcher->cbHCCode0;
771	}
772	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
773	{
774	pszDesc = "HCCode1";
775	uBase = R0PtrCode;
776	offCode = pSwitcher->offHCCode1;
777	cbCode = pSwitcher->cbHCCode1;
778	}
779	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
780	{
781	pszDesc = "GCCode";
782	uBase = GCPtrCode;
783	offCode = pSwitcher->offGCCode;
784	cbCode = pSwitcher->cbGCCode;
785	}
786	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
787	{
788	pszDesc = "IDCode0";
789	uBase = u32IDCode;
790	offCode = pSwitcher->offIDCode0;
791	cbCode = pSwitcher->cbIDCode0;
792	}
793	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
794	{
795	pszDesc = "IDCode1";
796	uBase = u32IDCode;
797	offCode = pSwitcher->offIDCode1;
798	cbCode = pSwitcher->cbIDCode1;
799	}
800	else
801	{
802	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
803	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
804	offCode++;
805	continue;
806	}
807
808	/*
809	* Disassemble it.
810	*/
811	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
812	DISCPUSTATE Cpu;
813
814	memset(&Cpu, 0, sizeof(Cpu));
815	Cpu.mode = CPUMODE_32BIT;
816	while (cbCode > 0)
817	{
818	/* try label it */
819	if (pSwitcher->offR0HostToGuest == offCode)
820	RTLogPrintf(" *R0HostToGuest:\n");
821	if (pSwitcher->offGCGuestToHost == offCode)
822	RTLogPrintf(" *GCGuestToHost:\n");
823	if (pSwitcher->offGCCallTrampoline == offCode)
824	RTLogPrintf(" *GCCallTrampoline:\n");
825	if (pSwitcher->offGCGuestToHostAsm == offCode)
826	RTLogPrintf(" *GCGuestToHostAsm:\n");
827	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
828	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
829	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
830	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
831
832	/* disas */
833	uint32_t cbInstr = 0;
834	char szDisas[256];
835	if (RT_SUCCESS(DISInstr(&Cpu, (uintptr_t)pu8CodeR3 + offCode, uBase - (uintptr_t)pu8CodeR3, &cbInstr, szDisas)))
836	RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
837	else
838	{
839	RTLogPrintf(" %04x: %02x '%c'\n",
840	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
841	cbInstr = 1;
842	}
843	offCode += cbInstr;
844	cbCode -= RT_MIN(cbInstr, cbCode);
845	}
846	}
847	}
848	#endif
849	}
850
851
852	/**
853	* Relocator for the 32-Bit to 32-Bit world switcher.
854	*/
855	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
856	{
857	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
858	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
859	}
860
861
862	/**
863	* Relocator for the 32-Bit to PAE world switcher.
864	*/
865	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
866	{
867	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
868	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
869	}
870
871
872	/**
873	* Relocator for the 32-Bit to AMD64 world switcher.
874	*/
875	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
876	{
877	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
878	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
879	}
880
881
882	/**
883	* Relocator for the PAE to 32-Bit world switcher.
884	*/
885	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
886	{
887	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
888	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
889	}
890
891
892	/**
893	* Relocator for the PAE to PAE world switcher.
894	*/
895	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
896	{
897	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
898	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
899	}
900
901	/**
902	* Relocator for the PAE to AMD64 world switcher.
903	*/
904	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
905	{
906	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
907	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
908	}
909
910
911	/**
912	* Relocator for the AMD64 to 32-bit world switcher.
913	*/
914	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
915	{
916	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
917	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
918	}
919
920
921	/**
922	* Relocator for the AMD64 to PAE world switcher.
923	*/
924	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
925	{
926	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
927	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
928	}
929
930
931	/**
932	* Selects the switcher to be used for switching to GC.
933	*
934	* @returns VBox status code.
935	* @param pVM VM handle.
936	* @param enmSwitcher The new switcher.
937	* @remark This function may be called before the VMM is initialized.
938	*/
939	VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
940	{
941	/*
942	* Validate input.
943	*/
944	if ( enmSwitcher < VMMSWITCHER_INVALID
945	\|\| enmSwitcher >= VMMSWITCHER_MAX)
946	{
947	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
948	return VERR_INVALID_PARAMETER;
949	}
950
951	/* Do nothing if the switcher is disabled. */
952	if (pVM->vmm.s.fSwitcherDisabled)
953	return VINF_SUCCESS;
954
955	/*
956	* Select the new switcher.
957	*/
958	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
959	if (pSwitcher)
960	{
961	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
962	pVM->vmm.s.enmSwitcher = enmSwitcher;
963
964	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
965	pVM->vmm.s.pfnHostToGuestR0 = pbCodeR0 + pSwitcher->offR0HostToGuest;
966
967	RTGCPTR GCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
968	pVM->vmm.s.pfnGuestToHostRC = GCPtr + pSwitcher->offGCGuestToHost;
969	pVM->vmm.s.pfnCallTrampolineRC = GCPtr + pSwitcher->offGCCallTrampoline;
970	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
971	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
972	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
973	return VINF_SUCCESS;
974	}
975
976	return VERR_NOT_IMPLEMENTED;
977	}
978
979
980	/**
981	* Disable the switcher logic permanently.
982	*
983	* @returns VBox status code.
984	* @param pVM VM handle.
985	*/
986	VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
987	{
988	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
989	* @code
990	* mov eax, VERR_INTERNAL_ERROR
991	* ret
992	* @endcode
993	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
994	*/
995	pVM->vmm.s.fSwitcherDisabled = true;
996	return VINF_SUCCESS;
997	}
998
999
1000	/**
1001	* Gets the switcher to be used for switching to GC.
1002	*
1003	* @returns host to guest ring 0 switcher entrypoint
1004	* @param pVM VM handle.
1005	* @param enmSwitcher The new switcher.
1006	*/
1007	VMMR3DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1008	{
1009	/*
1010	* Validate input.
1011	*/
1012	if ( enmSwitcher < VMMSWITCHER_INVALID
1013	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1014	{
1015	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1016	return NIL_RTR0PTR;
1017	}
1018
1019	/*
1020	* Select the new switcher.
1021	*/
1022	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1023	if (pSwitcher)
1024	{
1025	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1026	return pbCodeR0 + pSwitcher->offR0HostToGuest;
1027	}
1028	return NIL_RTR0PTR;
1029	}

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source: vbox/trunk/src/VBox/VMM/VMMSwitcher.cpp@ 30148

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